Apparatus and method for configurable ECC modes - Patent Application 20070122997

Abstract

An apparatus, system, and method for an enhanced ECC mode. A memory array includes several data column planes and a spare column plane. When the memory device is set to the enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in a column plane other than one of the subset of data column planes or in one of the spare column planes. In this way, the memory may be capable of performing single error correction or single error correction with double error detection (SECDED), depending on the selected mode.

Description

[Technical Field]

[0001] Cross-reference to related applications This application claims the benefit of U.S. Provisional Application No. 63 / 383,865, filed November 15, 2022, which is incorporated by reference herein in its entirety and for all purposes.

[0002] The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor memory devices. In particular, the present disclosure relates to volatile memories such as dynamic random access memories (DRAMs). Information may be stored in individual memory cells of the memory as physical signals (e.g., charges on capacitive elements). During an access operation, an access command may be received along with address information specifying which memory cell should be accessed. [Background technology]

[0003] There is growing interest in enabling memories to store information in an array associated with data. For example, error correction information may be stored in an array with its associated data. There may be a need to ensure that such information can be accessed along with the designated data without unduly affecting the performance of the semiconductor device. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. [Figure 2] FIG. 1 is a block diagram of a memory device according to some embodiments of the present disclosure. [Figure 3] FIG. 1 is a block diagram illustrating an example of a memory read operation according to some example embodiments of the present disclosure. [Figure 4] FIG. 1 is a schematic diagram of a portion of a memory bank according to some embodiments of the present disclosure. [Figure 5]1 is a flowchart of a method for performing enhanced ECC operations according to some embodiments of the present disclosure. [Figure 6] 1 is a flowchart of a method for writing an error correction code (ECC) mode to a mode register of a memory device according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0005] The following descriptions of specific embodiments are merely exemplary in nature and are in no way intended to limit the scope of the present disclosure or its application or uses. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings, which form a part hereof, and which show by way of illustration specific embodiments in which the described systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed systems and methods, it being understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. Moreover, for the sake of clarity, detailed descriptions of specific features will not be discussed when these would be apparent to those skilled in the art so as not to obscure the description of the embodiments of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

[0006] A memory array may generally include several memory cells arranged at the intersections of word lines (rows) and bit / digit lines (columns). The columns may be grouped together into column planes, and a column select (CS) signal may be used to select a set of columns in each of the active column planes to provide data. When an access command is received, the memory may pre-fetch a code word (e.g., several bits of data) along with one or more associated bits from the memory and replace the pre-fetched data with new data (e.g., as part of a write operation) or remove the pre-fetched data from the memory device (e.g., as part of a read operation). Some memory modes may include removing less than all of the pre-fetched data from the memory device. For example, in conventional memory devices, in a particular mode, half of the pre-fetched data may be removed from the device, and the rest may be ignored.

[0007] Memory devices can store additional information associated with each codeword. For example, the additional information can include parity bits used as part of an error correction scheme. Nevertheless, the maximum number of bits that can be retrieved as part of a single access pass may be limited by the memory's architecture, and this number may generally be based on the maximum number of data bits in a codeword plus a few additional bits (e.g., 128 data bits + 8 additional bits). Some memories can include a spare column plane that stores additional information in addition to the set of data column planes. Nevertheless, it may be desirable to include more bits of additional information than can be retrieved from the spare column plane for various uses (e.g., including a lower data bit to parity bit ratio, etc.). Some memory devices can use a "two-pass" architecture, where at least some of the additional bits are first retrieved and stored, and then a second access pass retrieves the codeword data bits. Nevertheless, this may incur a penalty in the latency of any given access operation. A one-pass or single-pass architecture for storing the expanded additional information, where the codeword and additional bits are retrieved into the memory array as part of a single access pass, can provide performance benefits over a two-pass architecture.

[0008] As used herein, the term data may refer to any bits of information that a controller desires to store and / or retrieve from memory. Data may refer to information written to memory by a controller and then further read from memory by the controller. The term parity may refer to any bits generated by a memory's error correction circuitry based on data, metadata, or a combination thereof. Parity may generally remain in memory. In some embodiments, the amount of data retrieved as part of a single access operation may represent a set of bits that is a larger piece of information. For example, data bits (e.g., 64 bits) retrieved as part of a single access operation may have no meaning by themselves, but may have meaning when combined with sets of data bits retrieved as part of other access operations (e.g., to other memory arrays and / or to the same array at different times).

[0009] This disclosure is interested in apparatus, systems, and methods for single-pass access of ECC information from a spare column plane or one of the data column planes along with an associated codeword, for example, to enable single-error correction (SEC) and double-error detection (DED). Some memory devices can operate in a mode in which less than all of the data bits that can be pre-fetched are removed from the device. For example, a memory device may pre-fetch 128 data bits as part of a codeword in 8x or 16x mode, while a 64-bit codeword is provided at the device's data terminal in 4x memory mode. The data bits of the codeword are stored in some, but not all, of the data column planes (e.g., half of the column planes) in 4x memory mode. The half of the data column planes may be selected and may be based on the column address. Additional bits associated with the data (e.g., parity bits) may be stored in both the spare column plane and also in data column planes not selected by the column address as part of the current access.

[0010] According to some embodiments of the present disclosure, an example memory device may include a set of data column planes and a spare column plane. The memory may be set in a mode that enables SECDED by storing some ECC data along with its associated data in the data column planes and some ECC data in the spare column plane. SECDED requires a lower ratio of codeword bits to ECC bits; that is, only 8 ECC parity bits per 128 bits of data may be capable of single-error detection (SED) in the data. On the other hand, 8 parity bits per 64 bits of data may enable SECDED. In some examples, the spare column plane may be smaller than the data column planes and therefore may not be capable of storing a sufficient number of ECC bits per column address access to enable SECDED for a 64-bit codeword architecture.

[0011] To provide spare ECC storage, some ECC data may be stored in the data column plane. When an access operation is performed, column select signals with a first value are provided to columns in a first portion of the data column plane and to the spare column plane, and column select signals with a second value are provided to one or more columns not in the first portion of the data column plane. The memory may store data in the first portion of the data column plane and may store ECC data in the spare column plane and / or in accessed columns not in the first portion of the data column plane. In this way, data for a codeword and ECC information may be pre-fetched together as part of a single access pass, rather than pre-fetching additional data bits to facilitate SECDED ECC operations.

[0012] In some embodiments, a mode register can be used to switch the behavior of the memory device. For example, when the enhanced ECC mode is disabled (e.g., when SEC is enabled), the memory can have a first 4x operational mode in which the memory stores data bits in a first portion of the data column plane and a second portion of the data column plane, and can pre-fetch ECC parity information from a spare column plane. In this 4x operational mode, the memory's ECC circuit can correct single-bit errors in the pre-fetched data bits based on the pre-fetched parity bits, and then remove the data bits (e.g., bits from the first portion) from the memory.

[0013] When enhanced ECC is enabled (e.g., when SECDED is enabled), as part of an access operation, the memory can pre-fetch data bits from a first portion of the data column planes and ECC parity bits from one of the spare column planes or from a column plane in a second portion of the data column planes (e.g., determined based on a column address). The ECC circuit can correct errors in the data based on the parity bits, and the corrected data can be transmitted from the device. Thus, fewer bits can be pre-fetched and processed by ECC in the second mode (e.g., SECDED-enabled mode) than in the first mode (e.g., SEC-enabled mode). SECDED is enabled in the second mode via a lower codeword bit-to-parity bit ratio.

[0014] 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device, integrated on a single semiconductor chip. The device may be operated by a controller 150, such as a processor.

[0015] Semiconductor device 100 includes a memory array 118. Memory array 118 is shown to include multiple memory banks. In the embodiment of FIG. 1, memory array 118 is shown to include eight memory banks, BANK0 through BANK7. More or fewer banks may be included in memory array 118 in other embodiments. As described in more detail herein, each bank may be further divided into two or more sub-banks. Although embodiments in which each bank includes two sub-banks are generally described herein, other embodiments may include more sub-banks per bank.

[0016] Each memory sub-bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. Selection of the word lines WL is performed by a row decoder 108, and selection of the bit lines BL is performed by a column decoder 110. In the embodiment of FIG. 1, the row decoder 108 includes a respective row decoder for each memory bank, and the column decoder 110 includes a respective column decoder for each memory bank. In some embodiments, components that are repeated for each bank, such as row and column decoders and refresh control circuitry 116, may also include components that are repeated for each sub-bank. For example, there may be a refresh control circuitry 116 for each sub-bank.

[0017] The bit lines BL are coupled to respective sense amplifiers (SAMP). Read data from the bit lines BL is amplified by the sense amplifiers SAMP and transferred to the ECC circuit 120 via local data lines (LIO), transfer gates (TG), and global data lines (GIO). Conversely, write data output from the ECC circuit 120 is transferred to the sense amplifiers SAMP via complementary main data lines GIO, transfer gates TG, and complementary local data lines LIO, and written in the memory cells MC coupled to the bit lines BL.

[0018] The semiconductor device 100 may employ a number of external terminals, such as solder pads, including a command and address (C / A) terminal coupled to a command and address bus for receiving commands and addresses, a clock terminal for receiving clocks CK and / CK, a data terminal DQ coupled to a data bus for providing data, and power supply terminals for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0019] The clock terminals are supplied with external clocks CK and / CK, which are provided to the input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 106 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock may be used for timing operations of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operation of circuits included therein, for example, to a data receiver to time the receipt of write data. The input / output circuit 122 may include several interface connections, each of which may be couplable to one of the DQ pads (e.g., solder pads that may serve as external connections to the device 100).

[0020] A memory address may be supplied to the C / A terminal. The memory address supplied to the C / A terminal is transferred to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies a decoded row address XADD to the row decoder 108 and a decoded column address YADD to the column decoder 110. The decoded row address XADD may be used to determine which row should be opened so that data along a bit line can be read along the bit line. The column decoder 110 may provide a column select signal CS, which may be used to determine which sense amplifier provides data to the LIO. The address decoder 104 may also provide a decoded bank address BADD, which may indicate a bank of the memory array 118 that includes the decoded row address XADD and column address YADD.

[0021] Commands may be supplied to the C / A terminal. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as read commands for performing read operations and write commands for performing write operations, and other commands and operations. An access command may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cells to be accessed.

[0022] Commands may be provided as internal command signals to command decoder 106 via command / address input circuit 102. Command decoder 106 includes circuitry that decodes the internal command signals to generate various internal signals and commands for performing operations. For example, command decoder 106 may provide signals that indicate whether data is to be read, written, etc.

[0023] The device 100 can receive an access command, which is a read command. When the read command is received and a bank address, a row address, and a column address are supplied in a timely manner, data to be read is read from memory cells in the memory array 118 corresponding to the row address and column address. The read command is received by the command decoder 106, which provides an internal command, thereby providing the data read from the memory array 118 to the ECC circuit 120. The ECC circuit 120 receives data bits and parity bits from the memory array 118 and detects and / or corrects errors in the data bits. The correct read data is provided along a data bus and output to the outside from data terminals DQ via input / output circuit 122.

[0024] The device 100 can receive an access command that is a write command. When the write command is received and a bank address, a row address, and a column address are provided in a timely manner, write data provided to the data terminals DQ is provided along the data bus and written to memory cells in the memory array 118 corresponding to the row address and column address. The write command is received by the command decoder 106, which provides an internal command that results in the write data being received by a data receiver in the input / output circuit 122. The write data is provided to the ECC circuit 120 via the input / output circuit 122. The ECC circuit generates parity bits based on the received data, and the received data and parity are provided by the ECC circuit 120 to the memory array 118 to be written to the memory cells MC.

[0025] Device 100 includes refresh control circuits 116 associated with each bank of memory array 118. Each refresh control circuit 116 can determine when to perform a refresh operation on the associated bank. Refresh control circuit 116 provides a refresh address RXADD (along with one or more refresh signals not shown in FIG. 1 ). Row decoder 108 performs the refresh operation on one or more word lines associated with RXADD. Refresh control circuit 116 can perform multiple types of refresh operations, and the refresh operation can determine other details, such as how address RXADD is generated and how many word lines are associated with address RXADD.

[0026] ECC circuit 120 can detect and / or correct errors in accessed data. As part of a write operation, ECC circuit 120 can receive bits from IO circuit 122 and generate a parity bit based on the received bits. The received bits and parity bit are written to memory array 118. During an example read operation, ECC circuit 120 receives a set of bits and their associated parity bits from array 118 and uses them to locate and / or correct errors. For example, a single error correction (SEC) scheme can locate and detect up to one bit of error. A single error correction double error detection (SECDED) scheme corrects up to one bit of error, but two errors may be detected (however, the bits causing these errors are not individually located and therefore cannot be corrected). ECC circuit 120 can correct the information and then provide the corrected information (and / or the detected error indicated by the signal) to IO circuit 122. Parity bits may generally not be provided to IO circuitry 122 .

[0027] Mode register 130 can include various settings and can be used to enable an enhanced ECC mode of memory 100. When the enhanced ECC mode is enabled, device 100 can store ECC data associated with data in a spare column plane or in a designated data column plane determined based on the column address.

[0028] The memory 100 can be operated in various modes based on the number of DQ pads used. The mode can determine both how many DQ pads the controller 150 expects to send / receive data along as well as the format and / or number of bits the controller 150 expects as part of a single access command. For example, the memory can have 16 physical DQ pads. In 16x mode, all 16 DQ pads are used. In 8x mode, eight of the DQ pads are used, and in 4x mode, four of the DQ pads are used. The mode can also determine the burst length on each DQ terminal as part of the DQ operation. The burst length represents the number of consecutive bits on each DQ terminal during an access operation.

[0029] For example, in 8x mode, the memory can send or receive 128 data bits along eight DQ terminals, each having a burst length of 16. In an example 4x mode, a burst length of 16 may also be used, so 64 bits may be sent or received as part of an access operation. This disclosure is generally described with respect to an example embodiment in which a 64 data bit codeword is accessed as part of 4x mode and ECC circuit 120 uses 8 bits of ECC parity. Other example embodiments may use different numbers of data and parity bits.

[0030] Device 100 includes a mode register 130 that can be used to control various optional modes of the memory. For example, mode register 130 can include a setting that determines whether enhanced ECC mode is enabled. If enhanced ECC mode is enabled, mode register 130 can set a one-pass quad operation mode. Controller 150 can perform a mode register write (MRW) operation to set a value in mode register 130 or can perform a mode register read (MRR) operation to check what the value in mode register 130 is. Mode register 130 includes several registers that can each store one or more bits corresponding to a setting or piece of information about the memory.

[0031] The controller 150 can provide a command and a row and column address as part of an access operation. In a 4x mode of operation, in response to an address and a read command, the memory can retrieve data and parity as part of a single access pass to the memory array.

[0032] The power supply terminals are supplied with power supply potentials VDD and VSS, which are supplied to an internal voltage generation circuit 124. The internal voltage generation circuit 124 generates various internal potentials VARY and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals.

[0033] Power supply potentials VDDQ and VSSQ are also supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In one embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input / output circuit 122 to prevent power supply noise generated by the input / output circuit 122 from propagating to other circuit blocks.

[0034] 2 is a block diagram of a memory device according to some embodiments of the present disclosure. Memory device 200 may, in some embodiments, represent a portion of memory device 100 of FIG. 1. The view of FIG. 2 shows portions of memory arrays 210-214 and 220-224 that may be part of a memory bank (e.g., BANK0-7 of memory array 118 of FIG. 1), along with selected circuits used in the data path, such as ECC circuitry 232 (e.g., 120 of FIG. 1) and IO circuitry 234 (e.g., 122 of FIG. 1). For clarity, certain circuits and signals have been omitted from the view of FIG. 2.

[0035] The memory device 200 is organized into several column planes 210-214. Each column plane represents a portion of a memory bank. Each column plane 210-214 includes several memory cells at the intersections of word lines WL and bit lines. The bit lines may be grouped together into sets that are activated by the value of a CS signal. For clarity, only a single vertical line is used to represent the bit lines of each column select set, but there may be multiple columns accessed by this value of CS. For example, each line may represent eight bit lines that are all commonly accessed by the value of CS. As used herein, a "value" of CS may represent a decoded signal provided to a set of bit lines. Thus, a first value may represent the first value of a multi-bit CS signal or, after decoding, the signal line associated with this value that is active. Word lines may extend across multiple column planes 210-214.

[0036] The memory 200 includes a set of data column planes 210 and a spare column plane 212. The spare column plane 212 may be used to store additional information, such as ECC parity bits.

[0037] In some embodiments, memory 200 may also include an optional global column redundancy (GCR) column plane 214. In some embodiments, GCR plane 214 may have fewer memory cells (e.g., fewer column select groups) than data column planes 210. GCR CP 214 includes some redundant columns that may be used as part of a repair operation. If the value of the CS signal identifies one of the data column planes 210 as containing a defective memory cell, the memory may be remapped so that data that would have been stored in this column plane for this value of CS is instead stored in GCR CP 214.

[0038] For example, in some embodiments, memory 210 may include 16 data column planes 210(0) through 210(15). Each of these data column planes 210 includes 64 sets of bit lines activated by the value of a column select signal, with each set of bit lines including 8 bit lines. Thus, when a word line is opened in response to a row address and a column select signal is provided to each of the 16 column planes, 8 bits are accessed from each of the 16 column planes, corresponding to a total of 128 bits. A column select signal is also provided to spare column plane 212, but this column select signal may be a different value than that provided to data column plane 210 due to the additional 8 bits. If a repair is performed, GCR CP 214 may also be accessed, and the value on the GCR LIO may be used while ignoring the LIO of the column plane that GCR CP 214 is replacing. Therefore, the maximum number of bits that can be retrieved as part of the access path is 128 bits from the data column plane 210 (with 8 bits substituted from the GCR CP 214 if there was a repair), along with 8 additional bits from the spare CP 212.

[0039] The memory may be operated in 4x mode, with less than the maximum number of bits provided to an external device. A column address may indicate which of the column planes 210(0)-(M) is used to store data accessed in 4x mode. For example, a CP select bit in the column address (e.g., the 10th bit of column address C10) may select data from the even or odd column planes, or from the first half of a column plane or the second half of a column plane. Other schemes may be used in other example embodiments.

[0040] A mode register (e.g., mode register 130 in FIG. 1), not shown in FIG. 2, can be used to enable enhanced ECC on the device. When enhanced ECC is disabled, ECC data is limited to data in the spare column plane 212. When enhanced ECC is enabled, the mode register has a setting that places the memory device in a one-pass 4x operating mode, which can facilitate storing some additional ECC data in two or more of the column planes 210(0)-(M). In both operating modes, all information received from / sent to an external device is the same. For example, the memory's controller (e.g., 150 in FIG. 1) may expect 64 data bits per access of the memory 200 in either mode, but the operating mode can determine how the memory array is accessed, the power consumption of the access operation, the size of the pre-fetched information, the behavior of the ECC circuit 232, and which information is stored in which column planes 210(0)-(M).

[0041] In an example read command, in an enhanced ECC mode of operation, column, row, and bank addresses are received from the controller. A row decoder (e.g., row decoder 108 of FIG. 1) opens a selected word line based on the row address. The column decoder generates a column select signal based on the column address. As part of a single access pass, a column select value with a first value is provided to a first portion of the column planes, and a column select signal with a second value may be provided to at least one column plane not in the first portion of the column planes. Along with this, a third column select signal (which may or may not have the same value as the first or second column select signal) is provided to the spare column plane 212. Which columns are in the first portion may be based on a CP select bit of the column address (e.g., C10). The data column planes in the first portion provide the data bits of the codeword, and the data column planes not in the first portion, or one of the spare column planes 212, provide the ECC parity bits. During enhanced ECC mode, only a portion of column planes 210(0)-(M) are accessed, so only a portion of the data bits provided by the device are accessed (along with the ECC bits). ECC circuit 232 receives the data along with the parity bits and locates and / or corrects errors in the codeword data. The (corrected) data is provided to IO circuit 234, which provides the data to the DQ terminals.

[0042] This one-pass enhanced ECC mode architecture can provide performance improvements over two-pass architectures that require additional accesses to retrieve some of the ECC data necessary to enable SECDED ECC operation. For example, there may be a latency time tCCD_L_WR that is part of the memory's design specifications. The time tCCD_L_WR represents the minimum time that must elapse before a bank group can be accessed again. The time tCCD_L_WR may be a long inter-column (or command) delay period. During write operations, a two-pass architecture can incur a latency of twice tCCD_L_WR because each access pass requires a delay of tCCD_L_WR before the bank can be accessed again. The additional tCCD_L_WR is incurred because, to generate parity bits based on all of the pre-fetched data in a two-pass architecture, half of the unwritten pre-fetched data bits must still be pre-fetched (e.g., read) so that they can be added to the write bits received from the controller. A one-pass 4x operating mode can eliminate the need for read-modify-write, since only the data bits that are accessed are pre-fetched.

[0043] In an example write command, in enhanced ECC mode, column, row, and bank addresses are received from the controller along with codeword data, which is provided through the IO circuitry to the ECC circuitry, which generates ECC parity bits based on the codeword data and then writes the codeword data and parity to the column planes accessed in a manner similar to that described for a read operation.

[0044] In enhanced ECC mode, each of data column planes 210(0)-(M) can store a mixture of data and ECC parity bits, with additional ECC data stored in spare column plane 212. When enhanced ECC mode is disabled, ECC data may be limited to spare column plane 212. In enhanced ECC mode, ECC circuit 232 has the ability to locate and correct a single error and also detect additional errors in the data. In non-enhanced ECC mode, ECC circuit 232 can only correct one error in the data because the number of parity bits may be insufficient to detect the additional error.

[0045] Additionally, accesses in the enhanced ECC mode may draw less power than accesses in a non-enhanced ECC architecture. In a non-enhanced ECC architecture, all of the column planes may be activated, and data read from their sense amplifiers 220 is sent along the LIOs to the ECC circuit 232, along with the sense amplifiers 222 and LIOs associated with the spare column plane 212 (and, if there is a repair, the sense amplifiers 224 and LIOs of the GCR 214). Nevertheless, in an enhanced ECC architecture, only a select portion (e.g., half) of the data column planes 210(0)-(M) may be activated, and thus less than all of the data LIOs are sent by each sense amplifier 220. Similarly, various switches, signal lines, etc. may not be used in every access in the enhanced ECC mode. Thus, less power is drawn in the enhanced ECC mode.

[0046] FIG. 3 is a block diagram illustrating an example of a memory read operation according to some example embodiments of the present disclosure. FIG. 3 shows a view of a memory array 300 showing a representation of which portions of the memory array are set aside for different types of information. The blocks shown in FIG. 3 represent a portion of the memory array but do not necessarily represent the spatial layout of where information is stored in the memory array. Memory array 300, in some embodiments, may be an implementation of memory array 118 of FIG. 1 and / or column planes 210-214 of FIG. 2 in an enhanced ECC mode of operation as described herein.

[0047] 3 is depicted for an example embodiment in which there are 16 data column planes, each providing 8 bits when activated by a column select signal, and a spare column plane that also provides 8 bits when activated by its respective column select value. The example memory is operated in 4x mode in which 64 data bits are accessed by a controller (e.g., 150 in FIG. 1). The CP select bit C10 of the column address is used to determine which column plane provides the data.

[0048] During an example read operation, when C10 is in a low logic state (e.g., C10=0), eight column planes are accessed in the first portion 301 of the memory array 300, each providing eight bits for the total 64 data bits. A second column select signal is provided to a single column plane in the second portion 302 and / or to the spare column plane 308 to retrieve eight total ECC parity bits. In some examples, the eight ECC parity bits may be stored exclusively in a single column plane or in the spare column plane 308. In other examples, half of the eight parity bits may be stored exclusively in a single column plane, and the other half may be stored in the spare column plane 308. In this example, half of the bits retrieved from the spare column plane 308 used in the eight ECC parity bits may be determined based on the C10 bit. ECC circuit 310 (eg, 232 in FIG. 2) receives the 64 data bits along with 8 parity bits and provides 64 corrected data bits using SECDED.

[0049] In another example read operation, if C10 has the opposite value (e.g., C10=1), 64 data bits may be accessed from the second portion 302, 8 ECC bits from the first portion 301, and / or from the spare column plane 308.

[0050] In an example write operation, when only four ECC parity bits are stored in each of the data column planes, and half are stored in the spare column plane 308, the four parity bits of the spare ECC in each can be protected. For example, memory 300 can employ a read-modify-write (or RMW) strategy in which all eight parity bits in the spare column plane 308 and the data column plane are pre-fetched, then four of these bits are relocated to each location (as needed) based on the newly written parity bit, and then all eight parity bits are written back. This can protect the spare four bits (thus not be inadvertently changed by a direct write operation, since data has not been written to these cells).

[0051] The blocks in first portion 301 and second portion 302 represent portions of these column planes that may be reserved for different storage and do not necessarily represent the physical arrangement of where information is stored in the portions of the column planes or the spatial relationship of the column planes in each portion relative to each other. For example, first portion 301 could represent even column planes, while second portion 302 represents odd column planes, and columns reserved for storing ECC bits could be distributed throughout the data column planes. In the example of FIG. 3 , because 8 bits of ECC are required for every 64 bits of data, first portion 301 and second portion 302 could each have 93.75% of their total memory space used for data and 6.25% used for ECC bits when enhanced ECC mode is enabled. In other words, from the controller's perspective, only 93.75% of the memory array can be addressed, since the remaining portion is reserved for ECC data that is expected to occur along with data. In the non-enhanced ECC mode, there may be 100% of the array set aside for data, while the number of ECC parity bits is diluted to 8 ECC parity bits per 128 data bits, which is insufficient for SECDED ECC calculations.

[0052] Table 1 summarizes the different operations in two different 4x modes according to some embodiments of the present disclosure. [Table 1]

[0053] In Table 1, the notations d and p are used to represent data bits and parity bits, respectively. For example, the first row uses the notation 64d+8p to represent that in enhanced ECC mode, 64 data bits and 8 parity bits are fetched. The mode register can also have a setting that disables enhanced ECC mode.

[0054] In the non-enhanced ECC mode, 128 bits of data and 8 parity bits are used by ECC circuit 232, while in the enhanced ECC mode, 64 bits of data and 8 bits of ECC parity are used by ECC circuit 232. In the non-enhanced ECC mode, ECC circuit 232 may implement the SEC scheme, while in the enhanced ECC mode, the SECDED scheme may be used. That is, a higher ratio of ECC parity to data bits is used in the enhanced ECC mode, which may provide more robust error protection.

[0055] The enhanced ECC mode may draw less power than the non-enhanced ECC mode. In the enhanced ECC mode, the CS signal may be provided to only a selected half of the column planes (based on C10). Thus, only half of the column planes need to activate their switches, drive voltages along the LIO lines, etc. This may reduce the power draw from a single access operation. For example, in the non-enhanced ECC mode, 17 different CS signals (16 data column planes and 1 spare column plane) and their associated LIO / GIO, etc. are asserted, while in the enhanced ECC mode, 9 different CS signals and their associated LIO / GIO, etc. are asserted.

[0056] 4 is a schematic diagram of a portion of a memory bank according to some embodiments of the present disclosure. Memory bank 400 may, in some embodiments, be included in memory 100 of FIG. 1, 200 of FIG. 20, and / or 300 of FIG. 3. Memory bank 400 shows a simplified schematic view of the layout of the memory bank along with example signals that may be used to activate various columns in the column plane as part of a second 4x mode of operation (e.g., a one-pass 4x mode of operation).

[0057] 4 is depicted in terms of an example embodiment in which there are 16 data column planes, each including 64 sets of bit lines (e.g., 64 values ​​of the CS signal), each providing 8 bits of data when activated by a respective CS signal. It should be understood that this is one example implementation of the present disclosure, and that other arrangements (e.g., more or fewer CS sets per CP, more or fewer CPs per memory bank, etc.) may be used in other example embodiments.

[0058] Memory bank 400 illustrates memory organized into 16 column planes 412-448 (e.g., 210 in FIG. 2 and / or 301-302 in FIG. 3), each associated with a DQ pad 410-440. Thus, a first DQ pad DQ3 410 is associated with column planes 412-418, a second DQ pad DQ2 420 is associated with column planes 422-428, a third DQ pad DQ1 430 is associated with column planes 432-438, and a fourth DQ pad DQ0 440 is associated with column planes 442-448. In the 4x mode of the example of FIG. 4, each of the four DQ pads DQ3-0 410, 420, 430, and 440 handles 16 data bits as part of an access operation, corresponding to a total of 64 data bits. In addition to the four DQ pads 410, 420, 430, and 440, the memory bank 400 may be associated with an ECC terminal 450 that may be used to send / receive ECC parity data as part of an access operation. The ECC terminal 450 may be associated with a spare column plane 452 (e.g., spare column plane 212 of FIG. 1 and / or spare column plane 308 of FIG. 3). In the simplified view of FIG. 4, a single word line WL is shown, along with the global row decoder 402 that drives the word line. Similarly, only selected lines are shown as bit lines, each representing a set of bit lines activated by a common CS signal in this CP. When activated, the bit lines are coupled to respective LIO lines.

[0059] The memory bank 400 is organized with the cells of the memory array between two sense amplifier regions 404. The sense amplifier regions 404 may extend in the same direction as the word lines WL. Column planes 412-448 are separated by sub-word line (SWL) drivers 406. Each column plane is adjacent to one other column plane and to an SWL driver 406. For example, column plane 412 is adjacent to an SWL driver 406 on one side and to column plane 414 on the other side. Column plane 414 is adjacent to column plane 412 on a first side and to a second SWL driver 406 on the opposite side. Opposite the SWL driver 406 is another column plane 416, and so on.

[0060] Thus, each data terminal is associated with four column planes, two pairs of column planes adjacent to each other and separated from the other pairs by SWL drivers. Each pair is associated with a different value of column plane select bit C10. For example, first DQ pad 410 is associated with column planes 412 and 414, both activated by C10 at a high logic level, and with column planes 416 and 418, both activated by C10 at a low logic level. Thus, column planes 412, 414, 422, 424, 432, 434, 442, and 444 all contain data accessed when C10=1, and column planes 416, 418, 426, 428, 436, 438, 446, and 448 all contain data accessed when C10=0. Whichever set of column planes is selected by C10, one or more column planes of other sets may be used to store ECC parity bits.

[0061] FIG. 4 illustrates an example access operation in enhanced ECC mode. The memory device receives a column address including C10=0 and a value decoded to a first column select signal CS0. Thus, CS0 is provided by the column decoder to column planes 416, 418, 426, 428, 436, 438, 446, and 448, and the bit lines associated with CS0 in each of these column planes each provide eight bits of data. The column decoder also provides CS0 to a spare column plane 452 and / or generates an additional CS signal to one of the column planes not selected by the value of C10 to retrieve ECC parity data. In this example embodiment, the value CS56 is provided to column plane 444. Thus, column plane 444 provides eight bits of ECC parity. Thus, from a single access pass, 64 bits of data (8 each from column planes 416, 418, 426, 428, 436, 438, 446, and 448) and 8 bits of parity (from column plane 444) are accessed. Arrows are used to indicate which CS signals and which column planes are accessed as part of a single access pass.

[0062] In other words, the column decoder (e.g., 110 in FIG. 1) can activate digit lines and couple them to the LIOs for column planes 416, 418, 426, 428, 436, 438, 446, and 448. This allows column planes activated by C10=0 to represent all of the available LIOs (e.g., eight LIOs per column plane). Nevertheless, in the set of column planes associated with C10=1, the column decoder can activate less than all of the LIOs because only CS 56 in column plane 444 is coupled to an LIO. The remaining LIOs associated with column planes activated by C10=1 are unused in this access operation.

[0063] 4, a similar access may occur as part of a second access operation, where a column address is received with C10=1 but including the same decoded value of CS. In this example, the column decoder provides CS0 to column planes 412, 414, 422, 424, 432, 434, 442, and 444, as well as to spare column plane 450, while the CS56 value is provided to column plane 448. Note that the same 8 bits may be provided from spare column plane 452, but the value of C10 controls which portion of these 8 bits are provided.

[0064] The controller may have different ranges of addressable values ​​based on the mode the memory is operating in. In this example, the controller may generate column addresses associated with CS values ​​ranging from CS0 to CS55. Yet, CS55 through CS63 may represent "unaddressable" space because the controller cannot directly access these columns (reserved for parity).

[0065] 5 is a flowchart of a method for implementing enhanced ECC operations according to some embodiments of the present disclosure. Method 500 may, in some embodiments, be performed by one or more of the apparatuses or systems described herein. For example, method 500 may be performed at least in part by memory 100 of FIG. 1, memory device 200 of FIG. 2, memory array 300 of FIG. 3, and / or memory bank 400 of FIG. 4.

[0066] Method 500 may include receiving a column address as part of the access operation at 510. In some examples, method 500 may also include receiving a row and bank address and an access command as part of the access operation. For example, the address and command may be received along a C / A terminal of the memory, such as the C / A terminal of FIG.

[0067] The method 500 may further include, at 520, accessing data bits from columns in a first portion of the plurality of data column planes as part of the access operation based on a column address. In some examples, the method 500 may include selecting the first portion of the plurality of data column planes based on the column address. In some examples, the method 500 may include selecting a first half of the column planes as the first portion or selecting a second half of the column planes as the first portion. The column address may include a column plane select bit (e.g., C10) specifying which column planes are in the first portion or not. For example, the method 500 may include selecting the first half when the column plane select bit is in a first state and selecting the second half when the column plane select bit is in a second state. In some examples, the method 500 may include generating a column select signal associated with the access operation with a column decoder (e.g., 110 in FIG. 1 ).

[0068] At 530, the method 500 may further include accessing a parity bit from one of the columns in a column plane not in the first portion of the plurality of data column planes or in a column of a spare column plane as part of the access operation based on the column address. For example, the method 500 may include accessing the parity bit from a column in a column plane not in the first portion of the plurality of data column planes in response to the column address having a first value, and accessing the parity bit from a column in the spare column plane in response to the column address having a second value. In some examples, the method 500 may further include correcting errors in the data bits based on the parity bit with an error correction code (ECC) circuit. For example, the method 500 may include implementing single error correction double error detection (SECDED) with the error correction code (ECC) circuit using the parity bit.

[0069] In some examples, method 500 may include performing a second access operation, such as receiving a second column address as part of the second access operation, accessing second data bits from a second portion of the plurality of data column planes that does not overlap with the first portion of the plurality of data column planes as part of the second access operation based on the second column address, and accessing a parity bit from one of the columns in the first portion of the plurality of data column planes or in a column of a spare column plane as part of the access operation based on the second column address.

[0070] 6 is a flowchart of a method for writing an error correction code (ECC) mode to a mode register of a memory device according to some embodiments of the present disclosure. Method 600 may, in some embodiments, be a method of operating a memory device. For example, method 600 may be performed by a controller, such as controller 150 of FIG. 1, when the controller operates a memory, such as semiconductor device 100 of FIG. 1, memory device 200 of FIG. 2, memory array 300 of FIG. 3, and / or memory bank 400 of FIG. 4.

[0071] At 610, the method 600 includes writing a value to a mode register of the memory device to set an error correction code (ECC) mode of the memory device to one of a first mode or a second mode. For example, the controller may perform an MRW operation to write a value to one or more registers that control the ECC mode of the memory. In some examples, the first mode and the second mode are both 4x modes of the memory device. In some examples, the method 600 further includes writing 64 bits of data to the memory array in the first and second modes. For example, the controller may provide the 64 bits of data in four 16-bit bursts. In some examples, the first mode represents a single-error-detection ECC mode, and the second mode represents a single-error-correction-double-error-detection (SECDED) ECC mode.

[0072] The method 600 may further include, at 620, accessing a first percentage of addresses of a memory array of the memory device to store data when the ECC is in the first mode.

[0073] At 630, the method 600 may further include accessing a second percentage of addresses of a memory array of the memory device to store data when the ECC is in the second mode, the first percentage being greater than the second percentage. In some examples, the method 600 further includes reserving a third percentage of the addresses for storing ECC parity data. The third percentage may be based on the difference between the first percentage and the second percentage. In some examples, the method 600 further includes accessing the memory array at once to write data in both the first mode and the second mode.

[0074] The method 600 may include generating a column address associated with an addressable area of ​​the memory array based on a first or second mode. Thus, when the memory is in the first mode, the controller may generate a column address associated with a first range of CS values ​​(e.g., CS0 to CS63), and when the memory is in the second mode, the controller may generate a column address associated with a second range of CS values ​​(e.g., CS0 to CS54).

[0075] Of course, it should be recognized that any one of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or may be separated and / or implemented among separate devices or device portions in accordance with the present systems, devices, and methods.

[0076] Finally, the above discussion is intended to be merely illustrative of the present system and should not be construed as limiting the scope of the appended claims to any particular embodiment or group of embodiments. Accordingly, while the present system has been described in particular detail with reference to exemplary embodiments, it should also be recognized that numerous modifications and alternative embodiments may be devised by those skilled in the art without departing from the broader and intended spirit and scope of the present system, as set forth in the following claims. Accordingly, the specification and drawings should be evaluated in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. a first data column plane having first bit lines; a second data column plane having second bit lines; a spare column plane with a third bit line; a column decoder configured to activate the first bit line and activate one of the second bit line or the third bit line as part of an access operation; an error correction code (ECC) circuit configured to access data bits along the first bit line and parity bits along the activated one of the second or third bit line as part of the access operation; An apparatus comprising:

2. As part of the second access operation, the column decoder is configured to activate a fourth bit line of the second data column plane and activate one of a fifth bit line of the first data column plane or a sixth bit line of the spare column plane; the ECC circuitry is configured to access a second data bit along the fourth bit line and a parity bit along the activated one of the fifth or sixth bit line; 2. The device according to claim 1, characterized in that:

3. 3. The apparatus of claim 2, wherein the column decoder is configured to activate the first bit line during the access operation based on a column select bit of a first column address having a first value specifying that the data bit is stored in the first data column plane, and to activate the fourth bit line during the second access operation based on the column select bit of a second column address having a second value specifying that the second data bit is stored in the first data column plane.

4. 2. The apparatus of claim 1, wherein the column decoder is configured to selectively activate the one of the second bit line or the third bit line based on a received column address.

5. 2. The apparatus of claim 1, wherein said first data column plane has the same number of memory cells as said spare column plane.

6. 2. The apparatus of claim 1, further comprising an input / output circuit configured to receive the data bits from the ECC circuit if the access operation is a read operation, and configured to provide the data bits to the ECC circuit if the access operation is a write operation.

7. 2. The apparatus of claim 1, wherein the ECC circuitry is configured to locate and correct errors in the data bits based on the parity bits when the access operation is a read operation.

8. 2. The apparatus of claim 1, wherein the column decoder is configured to provide a column select signal with a first value to the first data column plane and to provide one of a second column select signal with a second value to the second data column plane or a third column select signal with the first value to the spare column plane in response to a column address received as part of the access operation.

9. a first plurality of column planes; a second plurality of column planes; and spare row plane a memory bank comprising: a column decoder configured to select one of the first or second plurality of column planes based on a column address received as part of an access operation, wherein as part of the access operation, data bits in a selected one of the first or second plurality of column planes are accessed and parity bits in one of the spare column plane or an unselected one of the first or second plurality of column planes are accessed based on the column address; An apparatus comprising:

10. 10. The apparatus of claim 9, further comprising an error correction code (ECC) circuit configured to locate and correct errors in the data bits based on the parity bits.

11. 10. The apparatus of claim 9, wherein the ECC circuitry is configured to perform single error correct double error detect (SECDED) based on the parity bits and the data bits.

12. 10. The apparatus of claim 9, wherein the column decoder is configured to select the one of the first plurality of column planes or the second plurality of column planes based on a column plane select bit of the column address.

13. 12. The apparatus of claim 11, wherein the column decoder is configured to decode the column address to determine whether the parity bit is stored in the spare column plane or in a non-selected one of the first or second plurality of column planes.

14. 9. The apparatus of claim 8, wherein the apparatus is a memory device operating in quad mode.

15. receiving a column address as part of the access operation; accessing data bits from columns in a first portion of a plurality of data column planes as part of the access operation based on the column address; accessing a parity bit from one of the columns in a column plane not in the first portion of the plurality of data column planes or in a column of a spare column plane as part of the access operation based on the column address; A method comprising:

16. 16. The method of claim 15, further comprising correcting errors in the data bits based on the parity bits with an error correction code (ECC) circuit.

17. 16. The method of claim 15, further comprising using the parity bits to implement single error correct double error detect (SECDED) in an error correction code (ECC) circuit.

18. 16. The method of claim 15, further comprising: in response to the column address having a first value, accessing the parity bit from the column in the column plane that is not in the first portion of the plurality of data column planes.

19. 20. The method of claim 18, further comprising: accessing the parity bit from the column in the spare column plane in response to the column address having a second value.

20. receiving a second column address as part of a second access operation; accessing second data bits from a second portion of the plurality of data column planes that does not overlap with the first portion of the plurality of data column planes as part of the second access operation based on the second column address; accessing a parity bit from one of the columns in the first portion of the plurality of data column planes or in the columns of the spare column plane as part of the access operation based on the second column address; 20. The method of claim 19, further comprising:

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