Comprehensive impedance tuning performance optimization

Abstract

Embodiments disclosed herein include a method for field-adjusting calibration factors of multiple RF impedance match sections to control multiple plasma chambers. In one embodiment, the method includes collecting and storing data in a memory from the operation of the multiple RF impedance match sections, and finding a tuning space for each of the multiple RF impedance match sections from the collected data. In one embodiment, the method includes finding adjustments that account for variability in each of the multiple RF impedance match sections and finding adjustments to variable tuning elements of the multiple RF impedance match sections that account for time variations and process-related load impedances, and the method further includes obtaining an operating window for the variable tuning elements in the multiple RF impedance match sections.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. patent application Ser. No. 17 / 981,282, filed Nov. 4, 2022, the entire contents of which are incorporated herein by reference.

[0002] Embodiments relate to the field of semiconductor manufacturing, and more particularly to fleetwide control of impedance tuning for process performance optimization.

[0003] 2. Description of Related Art In semiconductor processing environments, especially high-volume manufacturing (HVM) environments, it is often desirable to process devices in parallel with one another. For example, multiple plasma chambers may be used in parallel to execute a given process recipe in the fabrication of a device. This results in increased yield and throughput. Ideally, multiple plasma chambers would be perfectly matched to produce uniform results for all devices. However, matching multiple chambers is extremely difficult. As device dimensions become smaller and smaller, this matching process becomes increasingly important.

[0004] For example, two chambers that have just been cleaned may perform differently. This can be due to a number of differences in the chambers, including sensor variations and effects over time. Matching similar processing chambers is difficult because so many variables can differ. Chamber mismatch also makes it more difficult to identify when a processing excursion occurs that needs to be addressed (e.g., by cleaning or parameter adjustment). Summary of the Invention

[0005] Embodiments disclosed herein include a method for field-adjusting calibration factors of multiple RF impedance match sections to control multiple plasma chambers. In one embodiment, the method includes collecting and storing data in a memory from the operation of the multiple RF impedance match sections, and finding a tuning space for each of the multiple RF impedance match sections from the collected data. In one embodiment, the method further includes finding adjustments that account for variability in each of the multiple RF impedance match sections, and finding adjustments to variable tuning elements of the multiple RF impedance match sections that account for time variations and process-related load impedances. In one embodiment, the method further includes obtaining an operating window for the variable tuning element in the multiple RF impedance match sections.

[0006] Embodiments further include a method for field adjusting calibration factors of a plurality of RF impedance match elements having a first variable tuning element and a second variable tuning element to control a plurality of plasma chambers. In one embodiment, the method includes collecting data for a plurality of RF impedance match elements, clustering the collected data into a plurality of data clusters, reconciling the data clusters to minimize impedance tuning variability among the plurality of RF impedance match elements, and updating the calibration factors of each of the plurality of RF impedance match elements using the data reconciliation.

[0007] Embodiments may further include a plasma processing system, in one embodiment, the plasma processing system may include a controller and a plurality of plasma chambers, each having an RF match, and the controller is configured to calibrate the RF matches of the plurality of plasma chambers using an RF match correction algorithm. [Brief explanation of the drawings]

[0008] [Figure 1A]1 is a schematic diagram of a semiconductor processing environment including a controller for controlling multiple plasma processing tools, according to one embodiment. [Figure 1B] 1 is a cross-sectional view of a plasma processing tool having a first RF generating device and a second RF generating device, according to one embodiment. [Figure 2A] 10 is a graph of recorded data showing clustering of first variable tuning elements according to one embodiment. [Figure 2B] 10 is a graph of recorded data showing clustering of second variable tuning elements according to one embodiment. [Figure 3A] 1 is a plot of tuning space for a first RF impedance match section and a second RF impedance match section before calibration, according to one embodiment. [Figure 3B] 10 is a plot of tuning space for a first RF impedance match section and a second RF impedance match section after calibration, according to one embodiment. [Figure 4] 1 is an illustration of a data cluster containing tuning settings of three uncalibrated RF impedance match sections, according to one embodiment. [Figure 5] FIG. 1 is a process flow diagram illustrating a process for calibrating multiple RF matches, according to one embodiment. [Figure 6] FIG. 10 is a process flow diagram illustrating a process for calibrating multiple RF matches according to a further embodiment. [Figure 7A] FIG. 1 is a schematic diagram of a performance template space illustrating probability paths between templates, according to one embodiment. [Figure 7B] FIG. 10 is a diagram of a template with RF matching clusters and centroids, according to one embodiment. [Figure 8A] FIG. 1 is a schematic diagram of a pair of templates illustrating a first type of deviation event, according to one embodiment. [Figure 8B] FIG. 1 is a schematic diagram of templates showing matching traces between templates and non-matching deviating traces between templates, according to one embodiment. [Figure 9] FIG. 1 illustrates a block diagram of an exemplary computer system that may be used with a processing tool, according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] The system described herein includes comprehensive control of impedance tuning for process performance optimization. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. It will be apparent to those skilled in the art that the embodiments may be practiced without such specific details. Otherwise, well-known aspects are not described in detail so as not to unnecessarily obscure the embodiments. Furthermore, it should be understood that the various embodiments illustrated in the accompanying drawings are illustrative representations and are not necessarily drawn to scale.

[0010] As mentioned above, chamber matching is a critical processing parameter when operating in a high volume manufacturing (HVM) environment. Specifically, good chamber matching enables high yield and high throughput. However, as device dimensions shrink, the demand for improved chamber matching continues to increase.

[0011] Thus, embodiments disclosed herein include processes and devices for implementing a method for field-adjusting the calibration coefficients of multiple RF impedance matches to control multiple plasma chambers. Generally, an RF impedance match is a device that minimizes reflected power by controlling the impedance seen by an RF source to match a variable impedance inside the chamber. The impedance inside the chamber can change as a result of various processing conditions that can alter the characteristics of the plasma inside the chamber. Therefore, precise control and monitoring of RF impedance matches can be used to improve chamber performance. Matching RF impedance matches can also potentially facilitate the detection of process excursions.

[0012] In embodiments disclosed herein, a control algorithm is used to adjust calibration coefficients of multiple RF impedance matching sections. The control algorithm may first include collecting data from the multiple RF impedance matching sections. The collected data is then clustered into multiple data clusters. Each data cluster may include the setting values ​​of the variable tuning elements (e.g., variable capacitors) of each RF impedance matching section for a particular processing condition (e.g., a particular process step in a recipe). After the data clusters are found, a matching process is used to minimize the impedance tuning variability among the multiple RF impedance matching sections. In some embodiments, this matching process may involve linear equality constraints, although other types of constraints may be used in other cases. In some embodiments, the control algorithm may then use the matching data to update the calibration coefficients of each of the multiple RF impedance matching sections. The calibration coefficients may include maximum and minimum set points for the variable tuning elements of each RF impedance matching section.

[0013] 1A, a schematic diagram of a semiconductor processing environment 100 is shown, according to one embodiment. In one embodiment, the semiconductor processing environment 100 may include a controller 105. The controller 105 may be used to control multiple semiconductor processing tools 110 (e.g., plasma tools, etc.). The controller 105 may be implemented as a standalone computing system or may be integrated within a server or other remote processing architecture.

[0014] In the illustrated embodiment, the plurality of semiconductor processing tools 110 includes three plasma tools (i.e., plasma tool 1, plasma tool 2, and plasma tool 3). However, it should be appreciated that there may be any number of semiconductor processing tools 110 communicatively coupled to the controller 105. The plurality of semiconductor processing tools 110 may be substantially similar to one another. For example, each of the semiconductor processing tools 110 may be configured to perform the same process step(s) of a recipe used to fabricate a device (e.g., a transistor, a memory device, a solar cell, a microelectromechanical system (MEMS), etc.). Additionally, the controller 105 may be part of a system used to control other processing tools (not shown) used to continue fabricating the device. That is, the controller 105 may not necessarily be dedicated to controlling the semiconductor processing tool 110.

[0015] In one embodiment, the controller 105 can be configured to provide chamber matching between semiconductor processing tools 110. For example, as described in more detail below, the controller 105 can be configured to implement an RF match correction algorithm. Even when semiconductor processing tools 110 are properly maintained and cleaned, differences in the tuning of variable tuning elements in RF matching can occur. That is, for a given load impedance in a semiconductor processing tool, variable tuning elements in different semiconductor processing tools 110 may require different set points. This can make it difficult to determine issues, such as when a process excursion occurs and when cleaning or replacement of consumables is required. These challenges are mitigated by properly calibrating the RF matching using the methods disclosed herein.

[0016] 1B, a cross-sectional view of a semiconductor processing tool 110 is shown, according to one embodiment. In one embodiment, the semiconductor processing tool 110 may comprise a chamber 111. The chamber 111 may be adapted to maintain a low-pressure environment (e.g., near vacuum pressure) capable of supporting generation of a plasma 120 within the chamber 111. For simplicity, portions of the chamber 111 have been omitted. For example, FIG. 1B omits the pumping and exhaust architecture for maintaining the vacuum pressure.

[0017] In one embodiment, the semiconductor processing tool 110 may include a pedestal 112 for supporting the substrate 115. The pedestal 112 may include a chuck, such as an electrostatic chuck (ESC). In some embodiments, the pedestal 112 may further include a heating element and / or a cooling element to control the temperature of the substrate 115. In one embodiment, the substrate 115 may include any typical form factor used in semiconductor processing. For example, the substrate 115 may have a wafer form factor (e.g., 200 mm, 300 mm, 300 mm, 450 mm, etc.). The substrate 115 may include silicon or other semiconductor materials. However, the substrate 115 may also include non-semiconductor materials (e.g., glass, sapphire, etc.).

[0018] In one embodiment, the semiconductor processing tool 110 can include a showerhead 117 or another lid-type structure. The showerhead 117 can be positioned opposite the pedestal 112. The showerhead 117 can be configured to flow one or more process gases or inert gases into the chamber 111.

[0019] In one embodiment, the first RF source 135 A is coupled to the showerhead 117. A A first RF impedance match section 130 (such as an RF generator) may provide RF power to the chamber 111 to ignite and maintain a plasma 120 within the chamber 111. A However, the first RF source 135 Aand the shower head 117. A may include one or more variable tuning elements (not shown) that allow the impedance to be changed to match the load impedance of the plasma 120 in the chamber 111. For example, the variable tuning elements may include a variable capacitor or the like.

[0020] In one embodiment, the second RF source 135 B is coupled to the pedestal 112. A second RF source 135 B The second RF impedance matching section 130 B The second RF impedance matching section 130 may be separated from the pedestal 112 by Bは , first RF impedance matching section 130 A For example, the second RF impedance matching section 130 may be substantially similar to B may comprise a pair of variable tuning elements (such as variable capacitors) to change the impedance to match the impedance of the plasma 120 in the chamber 111 .

[0021] In one embodiment, the first RF impedance matching section 130 A and the second RF impedance matching section 130 B One or both of these may be controlled by the controller 105. The controller 105 may implement an RF match correction algorithm in the RF impedance match section. The RF match correction algorithm may tune the RF impedance match section to match the RF impedance match sections of other semiconductor processing tools 110. The RF match correction algorithm is described in more detail below.

[0022] 2A and 2B, a pair of plots showing capacitance values ​​of variable tuning elements in multiple RF impedance match sections are shown, according to one embodiment. The plot in FIG. 2A can be series capacitance, and the plot in FIG. 2B can be shunt capacitance. In the embodiment shown in FIGS. 2A and 2B, a data collection step is shown. That is, data is collected from multiple RF impedance match sections to provide series capacitance and shunt capacitance values ​​at multiple different process conditions. The recorded values ​​can be grouped into clusters 240. Each cluster 240 can represent the capacitance value of an RF impedance match section at a given process condition. For example, the multiple RF impedance match sections can all be running the same process recipe. At each step of the process recipe (e.g., when a steady-state condition is achieved), capacitor values ​​(e.g., series capacitance and shunt capacitance) can be recorded, and the group of values ​​can be referred to as a cluster.

[0023] As described in more detail below, each of the clusters 240 may contain different capacitance values. That is, even when the same processing conditions are achieved in different semiconductor processing tools, the RF impedance match sections may exhibit different capacitance settings. The purpose of the embodiments described herein is to match these differences, thereby matching the RF impedance match section settings. This allows for tighter control, easier identification of process excursions, and the like.

[0024] 3A, a plot of a first RF impedance match 351 and a second RF impedance match 352 is shown, according to one embodiment. In the plot shown in FIG. 3A, the X-axis represents a first capacitance value (C1) and the Y-axis represents a second capacitance value (C2). The box for first RF impedance match 351 indicates the minimum and maximum values ​​of C1 (i.e., C 11min and C 11max ), and the minimum and maximum values ​​of C2 (i.e., C 21min and C21max The second RF impedance match 352 box shows the minimum and maximum values ​​of C1 (i.e., C 12min and C 12max ), and the minimum and maximum values ​​of C2 (i.e., C 22min and C 22max ) The stars 353 and 354 represent the post-tuning conditions of the first RF impedance match 351 and the second RF impedance match 352, respectively.

[0025] The first RF impedance match 351 and the second RF impedance match 352 are part of a cluster. However, as the offset boxes indicate, the first RF impedance match 351 and the second RF impedance match 352 are not matched. That is, the first RF impedance match 351 and the second RF impedance match 352 may not match each other even though they are properly tuned to minimize reflected power under the same processing conditions. This makes it difficult to identify deviations in individual semiconductor processing tools within a group of semiconductor processing tools. In other words, the semiconductor processing tools are not well matched.

[0026] Thus, a matching process is used to calibrate the RF impedance match coefficients so that the boxes are aligned. For example, in FIG. 3B, box 355 of the first impedance match is nearly overlapping with box 356 of the second impedance match. While shown with a slight offset, it should be recognized that in some embodiments there may be no offset and box 355 may completely overlap box 356. Additionally, tuning points 357 and 358 may also substantially overlap. As shown, box 355 is aligned with the minimum and maximum values ​​of C*1 (i.e., C* 11min and C* 11max ), and the minimum and maximum values ​​of C*2 (i.e., C* 21min and C* 21max ), and box 356 may be defined by the minimum and maximum values ​​of C*1 (i.e., C* 12min and C* 12max), and the minimum and maximum values ​​of C*2 (i.e., C* 22min and C* 22max ) can be defined by

[0027] 4, a plot of a cluster 440 of a set of three tuning points 453, 454, and 458 is shown, according to one embodiment. Each of the tuning points 453, 454, and 458 may include settings for a first capacitor C1 (X-axis) and a second capacitor C2 (Y-axis). For example, tuning point 453 may have a setting of (C 11 ,C 21 ) and tuning point 454 is set to (C 12 ,C 22 ) and tuning point 458 is set to (C 13 ,C 23 ) to match each of the RF impedance matches with each other. To match each of the RF impedance matches with each other, a calibration factor is applied to each of the RF impedance matches to match the difference between the tuning points. For example, tuning point 459 is set at coordinate (C 1m ,C 2m ) and may be the point that minimizes the difference between tuning points 453, 454, and 458.

[0028] 5, a process flow diagram of process 580 is shown illustrating a process for field adjusting calibration factors of a plurality of RF impedance matching elements having a first variable tuning element and a second variable tuning element for controlling a plurality of plasma chambers, according to one embodiment. In one embodiment, the plurality of RF impedance matching elements can include two or more RF impedance matching elements. Additionally, the first variable tuning element and the second variable tuning element can include a variable capacitor. In one embodiment, process 580 can be performed by a controller configured to control a plurality of semiconductor processing tools using a plurality of RF impedance matching elements.

[0029] In one embodiment, process 580 begins at step 581 with collecting data for multiple RF impedance match sections. In one embodiment, this data collection can be used to record the setpoint of the variable tuning element of each of the RF impedance match sections during execution of one or more process recipes. In one embodiment, the recorded data can have a form similar to the data shown in the plots of Figures 2A and 2B. The recorded data can be stored in memory local to the controller or in a remote memory device.

[0030] In one embodiment, process 580 may continue at step 582, which includes clustering the collected data into multiple data clusters. Each data cluster may be a collection of variable tuning element settings for multiple RF impedance match elements. For example, if there are three RF impedance match elements, a data cluster may include first and second capacitance settings for the three RF impedance match elements. A data cluster may be local to a given process recipe step. For example, a steady-state condition may be achieved in each of multiple semiconductor processing tools, and data for each RF impedance match element may be recorded. While a single data cluster is described herein, it should be appreciated that multiple data clusters may be formed to improve the accuracy of the tuning process.

[0031] In one embodiment, process 580 may continue at step 583, which includes matching the data clusters to minimize impedance tuning variability among multiple RF impedance match sections. In one embodiment, this matching is an algorithm that enables the generation of calibration coefficients that match the RF impedance match tuning points of the data clusters. For example, tuning points 453, 454, and 458 in FIG. 4 are matched to tuning point 459.

[0032] In one embodiment, the matching process is a data minimization process that includes one or more of linear equality constraints, linear inequality constraints, non-linear equality constraints, or non-linear inequality constraints. In the case of linear equality constraints: TIFF2025537538000002.tif5170 In one embodiment, the analytical solution for matching data clusters is: TIFF2025537538000003.tif6170 In one embodiment, TIFF2025537538000004.tif76170 In one embodiment, where each σ value is a measure of the variability of an individual capacitor (e.g., the variability of motor position). In one embodiment, the RF impedance match may be characterized in two-dimensional C1-C2 space. However, in other embodiments, the match may fit to the motor step or any hyperdimensional representation of the capacitor.

[0033] In one embodiment, process 580 may continue to step 584, which includes using the matching data to update a calibration factor for each of the plurality of RF impedance matches. Specifically, the calibration factor may be: The RF impedance match can be considered matched for chamber matching. Therefore, the presence of deviations or other changes in processing conditions can be more easily recognized by the controller. In some embodiments, the updated calibration coefficients can be used as part of the digital twin for subsequent processing steps.

[0034] In one embodiment, the updated calibration coefficients can be fed back and used in subsequent data collection processes, enabling an iterative learning process to more accurately monitor and track the set points of the variable tuning elements of multiple RF impedance match sections.

[0035] 6, a process flow diagram is shown illustrating a process 690 for field adjusting calibration factors of multiple RF impedance match elements having first and second variable tuning elements for controlling multiple plasma chambers, according to a further embodiment. Process 690 may be similar in some cases to process 580. However, process 690 may have some differences from process 580 in some embodiments.

[0036] In one embodiment, process 690 may begin at step 691 with collecting data from the operation of multiple RF impedance match sections. In one embodiment, this data collection may be used to record the setpoint of the variable tuning element of each of the RF impedance match sections during the execution of one or more process recipes. In one embodiment, the recorded data may have a form similar to the data shown in the plots of FIGS. 2A and 2B. The recorded data may be stored in memory local to the controller or in a remote memory device.

[0037] In one embodiment, process 690 may continue at step 692, which includes finding a tuning space for each of the multiple RF impedance match elements. As used herein, tuning space may refer to the coordinates of a C1-C2 plot, similar to the embodiment shown in FIGS. 3A and 3B above. That is, a cluster of variable tuning element settings may be recorded. A cluster (also referred to as a data cluster) is a group of multiple RF impedance match settings at the same process conditions. For example, the first step of a recipe may be implemented by multiple semiconductor processing tools, and the variable tuning element settings of each of the RF impedance match elements may be recorded as part of the data cluster.

[0038] In one embodiment, process 690 may continue at step 693, which includes finding adjustments that account for the variability in each of the multiple RF impedance matches. In one embodiment, this process may be similar to the matching process detailed above, i.e., a minimization process using linear equality constraints, linear inequality constraints, non-linear equality constraints, or non-linear inequality constraints: TIFF2025537538000007.tif5170As detailed above, TIFF2025537538000008.tif6170

[0039] In one embodiment, process 690 may continue with step 694, which includes finding adjustments to variable tuning elements of multiple RF impedance match sections to account for time-varying and process-related load impedances. More generally, step 694 may be used to adjust the V matrix to account for variations in the processing chamber. For example, variations due to chamber aging, sensor performance, process variability, and / or device variability may be identified. It will be appreciated that while step 694 is described as being implemented after step 693, it may also be performed simultaneously with or before step 693.

[0040] In one embodiment, process 690 may continue with step 695, which includes obtaining an operating window for the variable tuning elements in the multiple RF impedance match sections. In one embodiment, this step 695 may include adjusting the motor step of the variable capacitor to more precisely match the RF impedance match sections.

[0041] 7A, a diagram of a performance template space 770 is shown, according to one embodiment. In one embodiment, the performance template space 770 includes a starting point 771. The starting point 771 may correspond to conditions in a semiconductor processing chamber before ignition of a plasma. That is, the starting point 771 may be the first operation of a process recipe or the conditions in a semiconductor processing chamber before the start of a process recipe. In one embodiment, a probability trace (arrow) may provide a path to a subsequent template 772. As shown, the probability trace may connect a sequence of templates 7721-7723 to each other. Similarly, the probability trace may connect a second sequence of templates 7731-7732 to each other. The series of templates 772 and 773 may eventually loop back to the starting point 771 to restart the process recipe.

[0042] In one embodiment, a probability trace can be the probability of going from one template to another. The probability traces shown are high probability values. Traces with lower probabilities have been omitted. The probability of a given trace can depend on one or more variables, such as the processing environment, chamber aging, process recipe conditions, etc.

[0043] In the illustrated embodiment, templates 772 and 773 are each envelopes of different sizes in C1-C2 space. Each template 772 may represent a step in a process recipe. If a value falls outside of templates 772 and 773, it may indicate that a deviation has occurred, as described in more detail below.

[0044] In one embodiment, templates 772 and 773 may be points established over repeated iterations of a process recipe. However, performance template space 770 may also include new process routines. For example, template 774 may be a new template being explored by performance template space 770. Alternatively, template 774 may represent a deviation from existing templates 772 and 773.

[0045] 7B, a more detailed view of one of the templates 772 is shown, according to one embodiment. In one embodiment, the template 772 may include a set of clusters for different RF matches. For example, the triangular points represent the RF match X cluster 776. X The square points are for RF matching Y cluster 776 Y The circular points are for RF-matched Z clusters 776 Z Each match can be for a cluster centroid 778 X-Z The template 772 may also have a centroid 777. As can be appreciated, variations between RF match X, Y, Z may be grouped into clusters within a single template 772.

[0046] 8A, a diagram of a template 872 is shown, according to one embodiment. Template 872 may include clusters 876 and centroids 877. In one embodiment, a deviation template 872' may be provided outside of template 872. Deviation template 872' may include clusters 876'. Because deviation template 872' is outside of template 872, it is considered a deviation event. Identification of a deviation event may trigger an alert that a process is outside of a predetermined process envelope. This may indicate that a processing tool requires cleaning, maintenance, etc.

[0047] 8B, a diagram of a second type of deviation event is shown, according to one embodiment. As shown, a first template 8721 is provided. A probability trace 879 leads to a second template 8722. For example, the first template 8721 may be a template for the i-th The first template 8722 may be the i+1th template point, and the second template 8722 may be the i+1th template point. However, a deviation may occur if the probability trace 879' deviates from the probability trace 879 leading to the third template 8723. That is, a deviation may occur if the subsequent template 872 is outside the specified process envelope and / or if the probability trace 879' deviates from the expected probability trace 879.

[0048] Referring now to FIG. 9 , a block diagram of an exemplary computer system 900 of a processing tool is shown, according to one embodiment. In one embodiment, the computer system 900 is coupled to the processing tool and controls processing in the processing tool. The computer system 900 may be connected to (e.g., networked with) other machines in a local area network (LAN), an intranet, an extranet, or the Internet. The computer system 900 may operate in the role of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The computer system 900 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web appliance, a server, a network router, switch, or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be performed by the machine. Furthermore, although only a single machine is shown as computer system 900, the term "machine" should also be interpreted to include any collection of machines (e.g., computers) that individually or jointly execute an instruction set (or multiple instruction sets) to perform any one or more of the methods described herein.

[0049] The computer system 900 may include a computer program product or software 922 having a non-transitory machine-readable medium having instructions stored thereon, which may be used to program the computer system 900 (or other electronic device) to perform processes in accordance with the embodiments. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium (such as a computer-readable medium) may include a machine- (e.g., computer) readable storage medium (e.g., read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.) and a machine- (e.g., computer) readable transmission medium (electrical, optical, acoustic, or other form of propagated signal, e.g., infrared signal, digital signal, etc.).

[0050] In one embodiment, computer system 900 includes a system processor 902, a main memory 904 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 906 (e.g., flash memory or static random access memory (SRAM)), and a secondary memory 918 (e.g., a data storage device), which communicate with each other via a bus 930.

[0051] The system processor 902 represents one or more general-purpose processing devices (e.g., microsystem processors, central processing units, etc.). More specifically, the system processor may be a complex instruction set computing (CISC) microsystem processor, a reduced instruction set computing (RISC) microsystem processor, a very long instruction word (VLIW) microsystem processor, a system processor implementing other instruction sets, or a system processor implementing a combination of instruction sets. The system processor 902 may also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal system processor (DSP), a network system processor, etc. The system processor 902 is configured to execute processing logic 926 to perform the operations described herein.

[0052] The computer system 900 may further include a system network interface device 908 for communicating with other devices or machines. The computer system 900 may also include a video display unit 910 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 912 (such as a keyboard), a cursor control device 914 (such as a mouse), and a signal generation device 916 (such as a speaker).

[0053] The secondary memory 918 may include a machine-accessible storage medium 931 (or, more specifically, a computer-readable storage medium) having stored thereon one or more sets of instructions (e.g., software 922) that embody any one or more of the methods or functions described herein. This software 922 may also reside, completely or at least partially, within the main memory 904 and / or the system processor 902 while being executed by the computer system 900, with the main memory 904 and the system processor 902 also constituting machine-readable storage media. The software 922 may further be transmitted or received over the network 920 via the system network interface device 908. In one embodiment, the network interface device 908 may operate using RF, optical, acoustic, or inductive coupling.

[0054] While in an exemplary embodiment, machine-accessible storage medium 931 is illustrated as a single medium, the term "machine-readable storage medium" should be interpreted to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) on which one or more sets of instructions are stored. The term "machine-readable storage medium" should also be interpreted to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods. Accordingly, the term "machine-readable storage medium" should be interpreted to include, but not limited to, solid-state memory, and optical and magnetic media.

[0055] In the foregoing specification, specific and exemplary embodiments have been described. It will be apparent that various modifications may be made to such embodiments without departing from the scope of the following claims. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. 1. A method for field adjusting calibration factors of a plurality of RF impedance matches for controlling a plurality of plasma chambers, comprising: collecting and storing in memory data from operation of the plurality of RF impedance matching sections; Finding a tuning space for each of the plurality of RF impedance matching sections from the collected data; finding an adjustment that accounts for variability in each of the plurality of RF impedance matching sections; finding adjustments to variable tuning elements of the plurality of RF impedance match sections that account for time-varying and process-related load impedances; obtaining an operating window of the variable tuning element in the plurality of RF impedance matches; A method comprising:

2. The method of claim 1 , wherein each tuning space comprises a cluster, each cluster comprising settings for a first variable tuning element and a second variable tuning element of each of the plurality of RF impedance matching sections.

3. 3. The method of claim 2, wherein finding an adjustment to a variable tuning element of each of the plurality of RF impedance match sections comprises finding an optimal data match of a cluster to minimize impedance tuning variability.

4. The method of claim 3 , wherein finding clusters and subsequently aligning the data provides feedback to a digital twin of the manufacturing process.

5. The method of claim 2 , wherein finding the clusters creates a template operable to predict process deviations.

6. 2. The method of claim 1, wherein the plurality of RF impedance matches comprises first and second tuning element coordinates in two-dimensional space.

7. The method of claim 1 , wherein the plurality of RF impedance matches are in any hyperdimensional representation.

8. The method of claim 1 , wherein the memory is a local memory or a remote memory.

9. The method of claim 1 , wherein the variability in each of the plurality of RF impedance matches includes process variability, device variability, and / or aging effects.

10. 1. A method for field adjusting calibration factors of a plurality of RF impedance matches having a first variable tuning element and a second variable tuning element for controlling a plurality of plasma chambers, comprising: collecting data for the plurality of RF impedance match sections; clustering the collected data into a plurality of data clusters; matching the data clusters to minimize impedance tuning variability among the plurality of RF impedance match sections; updating a calibration factor for each of the plurality of RF impedance match sections using the matching data; A method comprising:

11. The method of claim 10 , wherein updating a calibration factor comprises setting a minimum value and a maximum value for each of the first and second variable tuning elements.

12. The method of claim 10 , wherein each data cluster includes a setting value for each of the first and second variable tuning elements.

13. The method of claim 10 , wherein the plurality of RF impedance matching sections includes at least a first RF impedance matching section and a second RF impedance matching section.

14. The method of claim 10 , further comprising feeding back the updated calibration coefficients for use in the process of collecting the data for iterative learning.

15. 11. The method of claim 10, wherein matching data to minimize impedance tuning variability among the plurality of RF impedance matching sections comprises a linear equality constraint, a linear inequality constraint, a nonlinear equality constraint, or a nonlinear inequality constraint.

16. The method of claim 10 , wherein the clustering creates a template operable to predict a process deviation.

17. 1. A plasma processing system comprising: A controller; a plurality of plasma chambers; each plasma chamber having an RF match; the controller is configured to calibrate RF matching of the plurality of plasma chambers using an RF matching correction algorithm. Plasma treatment system.

18. 20. The plasma processing system of claim 17, wherein the RF match correction algorithm uses optimization to satisfy linearity constraints.

19. the RF match correction algorithm: collecting data for a plurality of RF impedance match sections; clustering the collected data into a plurality of data clusters; matching the data clusters to minimize impedance tuning variability among the plurality of RF impedance match sections; updating a calibration factor for each of the plurality of RF impedance match sections using the matching data; 20. The plasma processing system of claim 17, comprising:

20. the RF match correction algorithm:

20. The plasma processing system of claim 19, further comprising feeding back the updated calibration coefficients for use in the process of collecting data for iterative learning.

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