Systems and methods for increasing passivation and increasing etch rates

Abstract

Systems and methods for increasing the etching rate of a substrate by advancing passivation are described. One method includes generating a kilohertz radio frequency (RF) signal and generating a megahertz RF signal. The method includes synchronously pulsing the kilohertz RF signal and the megahertz RF signal to transition to a first state. The method also includes achieving passivation on a mask layer of the substrate by synchronously transitioning the kilohertz RF signal and the megahertz RF signal from the first state to a second state. The method includes synchronously pulsing the kilohertz RF signal and the megahertz RF signal from the second state to a third state to advance passivation from a constriction in the substrate to a pillar in the substrate. The method includes synchronously transitioning the kilohertz RF signal and the megahertz RF signal from the third state to a fourth state.

Description

[Technical Field]

[0001] The present embodiments relate to systems and methods for increasing passivation and increasing etch rates. [Background technology]

[0002] The background discussion provided herein is intended to present the contents of the present disclosure generally. Work by the currently named inventors within the scope of what is described in this Background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure.

[0003] In a plasma tool, a radio frequency (RF) generator is provided. The plasma tool also includes a matcher and a plasma chamber. The RF generator is coupled to the plasma chamber through the matcher. A semiconductor wafer is placed in the plasma chamber and subjected to processing. It is important to process the semiconductor wafer at a desired rate. Summary of the Invention

[0004]

[0009] Embodiments of the present disclosure provide systems, apparatus, methods, and computer programs for increasing passivation and increasing etch rates. It should be understood that the embodiments can be implemented in various ways (e.g., as a process, an apparatus, a system, a device, or a method on a computer-readable medium). Some embodiments are described below.

[0005] In some embodiments, during high aspect ratio (HAR) etching, it is important to scale down critical dimensions (CDs), such as the width of features on a substrate. In scaling down, it is important to increase the depth of features while keeping their widths substantially constant. Multi-state pulsing (e.g., four or more states) can be used to strategically deposit polymer on top of existing mask material in a mask layer to achieve passivation, protecting the mask layer from erosion and increasing mask selectivity, or to deposit passivation within each feature to protect each CD, overcoming HAR-related challenges. Specifically, various mask shapes are tailored to precisely impart the desired benefits in the HAR etch process. For example, increasing mask selectivity allows for longer overetching (OE) and improves profile taper, or reduces mask height, or reducing each CD to improve profile taper and open up process space for subsequent steps. The profile is the profile of each feature on the substrate. For example, the profile may be the arcuate CD of the constriction of each feature, or the bottom CD of the pillar of each feature, or the taper of each feature, or the defect formations within each feature, or a combination thereof.

[0006] In one embodiment, the systems and methods described herein improve mask selectivity by adjusting the power pulse shape, thereby preventing build-in or contamination or device reliability issues. Optimizing the pulse shape and width results in improved profile or mask selectivity.

[0007] In some embodiments, multi-state pulsing, in which four or more states are applied, improves the profile or enhances mask selectivity with a reduced trade-off. For example, a first state (e.g., a high state) is applied for etching. This high state (e.g., State S1) is immediately followed by a second state (e.g., a low state). This low state (e.g., State S0) is applied to deposit passivation on the top of the mask layer and on the sidewalls of the mask layer. The passivation is incorporated into the mask layer. The second state is immediately followed by a third state to shape the mask layer (e.g., the passivation incorporated into the mask layer), enabling an improved profile. A fourth state immediately following the third state increases the density of the plasma to maintain the etch and reduce the trade-off. The first through fourth states are applied for a clock cycle of the clock signal and are repeated for each additional clock cycle of the clock signal.

[0008] The high state has a high level of power for etching structures (e.g., features) on the substrate. Both high-frequency and low-frequency power, when used, are optimized toward the higher of the high levels to enhance the vertical etch rate relative to the lateral etch rate. The vertical etch rate facilitates etching features vertically, and the lateral etch rate facilitates etching features horizontally. The high level of low-frequency power ranges from 1 kilowatt (kW) to 100 kW. The low low-frequency and low high-frequency power states result in passivation (e.g., deposition) of polymer on the sidewalls and on top of the mask layer. Passivation facilitates protection of the sidewalls and reduces the etch rate of etching the mask layer, resulting in a reduced maximum CD and increased mask selectivity. The CD is reduced at the constrictions in the substrate. The low low-frequency and low high-frequency power states have power levels ranging from 0 watts to as high as 2 kW to 5 kW.

[0009] The third state facilitates mask shaping. At the power level of the low state, the passivation is primarily at the top of the mask layer to enhance mask selectivity. The third state has a higher power level than the low state to change the shape of the passivation at the top and constriction. This change in shape allows for deeper deposition into the feature and protects the sidewalls of the feature.

[0010] The fourth state increases the plasma's lifetime by increasing its density, which would otherwise cause the plasma to turn off and slow the etch rate. The power level for the fourth state ranges from a medium level to the lower end of the range of power levels for the high state. For example, the power level for the fourth state ranges from 300 watts to 1 kW.

[0011] In some embodiments, the shape of each pulse for each state of multi-state pulsing and the duty cycle (e.g., width) of the pulse are optimized to maximize the benefits described herein. The duty cycle is optimized by iteratively optimizing the etch rate and matching the on and off times between different pulse shapes. Additional pulse steps can also be used to further refine the profile.

[0012] In one embodiment, a method for increasing passivation and etching a substrate is described. The method includes generating a kilohertz radio frequency (RF) signal and generating a megahertz RF signal. The method further includes supplying the kilohertz RF signal and the megahertz RF signal to an impedance matching circuit coupled to an electrode of a plasma chamber. During a clock cycle of a clock signal, the method includes synchronously pulsing the kilohertz RF signal and the megahertz RF signal to transition to a first state for etching the substrate. The method further includes maintaining the kilohertz RF signal and the megahertz RF signal in the first state for a first predetermined period of time. The method also includes synchronously transitioning the kilohertz RF signal and the megahertz RF signal from the first state to a second state to achieve passivation on sidewalls and a top surface of a mask layer of the substrate. The method includes maintaining the kilohertz RF signal and the megahertz RF signal in a second state for a second predetermined period longer than the first predetermined period. During the second state, the power level of the kilohertz RF signal is less than the power level of the kilohertz RF signal during the first state, and the power level of the megahertz RF signal is less than the power level of the megahertz RF signal during the first state. The method includes synchronously pulsing the kilohertz RF signal and the megahertz RF signal from the second state to a third state to advance passivation from the constriction in the substrate to the pillar in the substrate. The method also includes maintaining the kilohertz RF signal and the megahertz RF signal in the third state for a third predetermined period substantially equal to the first predetermined period. During the third state, the power level of the kilohertz RF signal is greater than the power level of the kilohertz RF signal during the second state, and the power level of the megahertz RF signal is greater than the power level of the megahertz RF signal during the second state. The method includes reducing passivation from the constriction in the substrate by transitioning the kilohertz RF signal and the megahertz RF signal from the third state to a fourth state in a synchronized manner.The method includes maintaining the kilohertz RF signal and the megahertz RF signal in a fourth state for a fourth predetermined time period that is longer than the third predetermined time period, wherein during the fourth state, a power level of the kilohertz RF signal is less than a power level of the kilohertz RF signal during the third state, and a power level of the megahertz RF signal is less than a power level of the megahertz RF signal during the third state.

[0013] In one embodiment, a controller for increasing a substrate etching rate through enhanced passivation is described. The controller includes a processor and a memory device coupled to the processor. The processor controls a first RF generator to generate a kilohertz RF signal and a second RF generator to generate a megahertz RF signal. During a clock cycle of a clock signal, the processor controls the first RF generator and the second RF generator to synchronously pulse the kilohertz RF signal and the megahertz RF signal to transition to a first state. The processor further controls the first RF generator and the second RF generator to maintain the kilohertz RF signal and the megahertz RF signal in the first state for a first predetermined period. The processor controls the first RF generator and the second RF generator to synchronously transition the kilohertz RF signal and the megahertz RF signal from the first state to a second state. The processor also controls the first RF generator and the second RF generator to maintain the kilohertz RF signal and the megahertz RF signal in the second state for a second predetermined period longer than the first predetermined period. During the second state, the power level of the kilohertz RF signal is less than the power level of the kilohertz RF signal during the first state, and the power level of the megahertz RF signal is less than the power level of the megahertz RF signal during the first state. The processor controls the first RF generator and the second RF generator to pulse the kilohertz RF signal and the megahertz RF signal from the second state to a third state to synchronize them. The processor also controls the first RF generator and the second RF generator to maintain the kilohertz RF signal and the megahertz RF signal in the third state for a third predetermined period substantially equal to the first predetermined period. During the third state, the power level of the kilohertz RF signal is greater than the power level of the kilohertz RF signal during the second state, and the power level of the megahertz RF signal is greater than the power level of the megahertz RF signal during the second state. The processor controls the first RF generator and the second RF generator to transition from the third state to a fourth state to synchronize the kilohertz RF signal and the megahertz RF signal.The processor controls the first RF generator and the second RF generator to maintain the kilohertz RF signal and the megahertz RF signal in the fourth state for a fourth predetermined time period longer than the third predetermined time period, and during the fourth state, the power level of the kilohertz RF signal is less than the power level of the kilohertz RF signal during the third state, and the power level of the megahertz RF signal is less than the power level of the megahertz RF signal during the third state.

[0014] In one embodiment, a system for increasing a substrate etching rate through enhanced passivation is described. The system includes a first RF generator generating a kilohertz RF signal and a second RF generator generating a megahertz RF signal. The system further includes an impedance matching circuit coupled to the first RF generator and the second RF generator, the impedance matching circuit receiving the kilohertz RF signal and the megahertz RF signal and outputting a modified RF signal. The system includes a plasma chamber coupled to the impedance matching circuit, the plasma chamber receiving the modified RF signal. The system includes a controller coupled to the first RF generator and the second RF generator. During a clock cycle of a clock signal, the controller controls the first RF generator and the second RF generator to transition to a first state by synchronously pulsing the kilohertz RF signal and the megahertz RF signal. Furthermore, the controller controls the first RF generator and the second RF generator to maintain the kilohertz RF signal and the megahertz RF signal in a first state for a first predetermined period. The controller controls the first RF generator and the second RF generator to transition from the first state to a second state to synchronize the kilohertz RF signal and the megahertz RF signal. The controller also controls the first RF generator and the second RF generator to maintain the kilohertz RF signal and the megahertz RF signal in the second state for a second predetermined period that is longer than the first predetermined period. During the second state, the power level of the kilohertz RF signal is less than the power level of the kilohertz RF signal during the first state, and the power level of the megahertz RF signal is less than the power level of the megahertz RF signal during the first state. The controller controls the first RF generator and the second RF generator to synchronously pulse the kilohertz RF signal and the megahertz RF signal from the second state to a third state, and further controls the first RF generator and the second RF generator to maintain the kilohertz RF signal and the megahertz RF signal in the third state for a third predetermined period that is substantially equal to the first predetermined period.During the third state, the power level of the kilohertz RF signal is greater than the power level of the kilohertz RF signal during the second state, and the power level of the megahertz RF signal is greater than the power level of the megahertz RF signal during the second state. The controller controls the first RF generator and the second RF generator to transition from the third state to a fourth state to synchronize the kilohertz RF signal and the megahertz RF signal. The controller controls the first RF generator and the second RF generator to maintain the kilohertz RF signal and the megahertz RF signal in the fourth state for a fourth predetermined period that is longer than the third predetermined period. During the fourth state, the power level of the kilohertz RF signal is less than the power level of the kilohertz RF signal during the third state, and the power level of the megahertz RF signal is less than the power level of the megahertz RF signal during the third state.

[0015] Some advantages of the systems and methods described herein include increased speed at which substrates can be processed. By driving passivation downward during the third state, the etch rate is increased. Furthermore, after the passivation is driven downward to form a passivation layer on the sidewalls, the sidewalls of the feature are protected from etching. By driving passivation downward, the vertical etch rate is increased and the lateral etch rate is decreased.

[0016] A further advantage of the systems and methods described herein is that they prevent plasma extinction between the third and fourth states. Without the third state, plasma extinction may occur, resulting in a reduced etch rate. By providing the third state, the chance of plasma extinction is reduced. The third state also increases the power level of the fourth state compared to when the third state is not applied. Increasing the power level of the fourth state further reduces the chance of plasma extinction.

[0017] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0018] The embodiments may be best understood by referring to the following description taken in conjunction with the accompanying drawings.

[0019] [Figure 1] FIG. 1 is a diagram of one embodiment of a system illustrating processing a substrate using multiple states of a radio frequency (RF) signal.

[0020] [Figure 2] FIG. 2 is one embodiment of a graph for illustrating multiple states of the power level of an RF signal.

[0021] [Figure 3A] FIG. 3A is a side view of one embodiment of a portion of a substrate illustrating the effect of applying a first state of one of the RF signals and a first state of a second of the RF signals.

[0022] [Figure 3B] FIG. 3B is a side view of one embodiment of a portion of a substrate illustrating the effect of applying a second state to one of the RF signals and a second state to a second of the RF signals.

[0023] [Figure 3C] FIG. 3C is a side view of one embodiment of a portion of a substrate illustrating the effect of applying a third state to one of the RF signals and a third state to a second of the RF signals.

[0024] [Figure 3D] FIG. 3D is a side view of one embodiment of a portion of a substrate illustrating the effect of applying a fourth state to one of the RF signals and a fourth state to a second of the RF signals.

[0025] [Figure 4]FIG. 4 is a diagram of one embodiment of the system to explain the operation of the RF generator of the system of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0026] In the following embodiments, systems and methods for increasing passivation and enhancing etch rates are described. It will be understood that the embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order to not unnecessarily obscure the embodiments.

[0027] 1 is a diagram of one embodiment of a system 100 illustrating processing a substrate S using multiple states of radio frequency (RF) signals 102 and 104. The system 100 includes a host computer 106, an RF generator 108, another RF generator 110, an impedance matching circuit (IMC) 112, and a plasma chamber 114. The host computer 106 includes a processor 116 and a memory device 118. The plasma chamber 114 includes an upper electrode 120 and a substrate support 122, such as an electrostatic chuck (ESC). The substrate support 122 includes a lower electrode 124.

[0028] An example of the substrate S is a semiconductor wafer. Illustratively, the substrate S is used to manufacture 3D memory, 3D NAND, or dynamic random access memory (DRAM) capacitors. Examples of the host computer 106 include a desktop computer, a controller, a tablet, a server, a laptop computer, a controller, and a smartphone. As used herein, a controller includes one or more processors and one or more memory devices. The one or more processors of the controller are coupled to the one or more memory devices of the controller. As used herein, a processor is an application specific integrated circuit (ASIC), a digital signal processor, a programmable logic device (PLD), a central processing unit (CPU), a microprocessor, an integrated controller, or a microcontroller. As used herein, examples of a memory device include a random access memory (RAM) and a read-only memory (ROM). Illustratively, the memory device is a flash memory, a hard disk, a storage device, or the like. A memory device is an example of a computer-readable medium.

[0029] An example of RF generator 108 is an RF generator having a low operating frequency of x kilohertz (kHz) (e.g., 100 kHz or 400 kHz). An example of RF generator 110 is an RF generator having a high operating frequency of y megahertz (MHz) (e.g., 60 MHz or 27 MHz). IMC 112 includes a network of electronic components, such as capacitors or inductors coupled to each other, or a combination thereof. For example, IMC 112 includes one or more series circuits and one or more shunt circuits. Each of the series circuits is a capacitor or inductor, and each of the shunt circuits is a capacitor or inductor.

[0030] The plasma chamber 114 is a capacitively coupled plasma (CCP) chamber. A lower electrode 124 is embedded in a substrate support 122. The upper electrode 120 and the lower electrode 124 are each made of a metal, such as aluminum or an aluminum alloy. The substrate S is placed on the upper surface of the substrate support 122, in a gap 126 formed between the bottom surface of the upper electrode 120 and the upper surface of the substrate support 122.

[0031] The processor 116 is coupled to the RF generator 108 via a transmission cable 128 and to the RF generator 110 via another transmission cable 130. Examples of transmission cables are cables for serial data transmission, parallel data transmission, or data transmission according to the Universal Serial Bus (USB) protocol. The RF generator 108 is coupled to an input I1 of the IMC 112 via an RF cable 132 and to another input I2 of the IMC 112 via another RF cable 134. An output O1 of the IMC 112 is coupled to the lower electrode 124 via an RF transmission line 136. The upper electrode 120 is coupled to ground potential.

[0032] The processor 116 generates a recipe signal 138 and transmits the recipe signal 138 to the RF generator 108 via the transfer cable 128. As an example, the recipe signal 138 includes data for generating the RF signal 102. Illustratively, the recipe signal 138 includes a frequency level of the RF signal 102, a power level of the RF signal 102 for a state S1, a power level of the RF signal 102 for a state S0, a power level of the RF signal 102 for a state SB, and a power level of the RF signal 102 for a state SA. Furthermore, the recipe signal 138 includes a duty cycle at which the power level of the RF signal 102 for a state S1 is generated by the RF generator 108, a duty cycle at which the power level of the RF signal 102 for a state S0 is generated by the RF generator 108, a duty cycle at which the power level of the RF signal 102 for a state SB is generated by the RF generator 108, and a duty cycle at which the power level of the RF signal 102 for a state SA is generated by the RF generator 108.

[0033] As an example, each duty cycle is the time interval (e.g., period) of the power level of the RF signal during which a corresponding (e.g., respective) state of the RF signal is generated by the RF generator. For example, the duty cycle of the power level of state S1 of RF signal 102 is the time interval during which the power level is generated by RF generator 108. The duty cycle is generated during each clock cycle of a clock signal, such as a digital pulse signal that periodically transitions between logic levels 1 and 1. Illustratively, a clock signal having multiple clock cycles is generated by processor 116 and transmitted to RF generator 108 via transmission cable 128 and to RF generator 110 via transmission cable 130 to synchronize the operation of host computer 106 and RF generators 108 and 110 with one another.

[0034] Further, by way of example, the power level of a state may include one or more power values ​​(e.g., magnitudes) within a predetermined power range for that state. For example, the power level may be a statistical value (e.g., average or median) of multiple power values ​​within the predetermined power range. Also, by way of example, the frequency level of an RF signal may include one or more frequency values ​​within a predetermined frequency range. For example, the frequency level may be a statistical value (e.g., average or median or operating frequency) of multiple frequency values ​​within the predetermined frequency range.

[0035] Similarly, the processor 116 generates a recipe signal 140 and transmits the recipe signal 140 to the RF generator via the transfer cable 130. As an example, the recipe signal 140 includes data for generating the RF signal 104. For example, the recipe signal 140 includes a frequency level of the RF signal 104, a power level of the RF signal 104 for a state S1, a power level of the RF signal 104 for a state S0, a power level of the RF signal 104 for a state SB, and a power level of the RF signal 104 for a state SA. Furthermore, the recipe signal 140 includes a duty cycle at which the power level of the RF signal 104 for a state S1 is generated by the RF generator 110, a duty cycle at which the power level of the RF signal 104 for a state S0 is generated by the RF generator 110, a duty cycle at which the power level of the RF signal 104 for a state SB is generated by the RF generator 110, and a duty cycle at which the power level of the RF signal 104 for a state SA is generated by the RF generator 110. As an example, each duty cycle of the power level of the RF signal 104 is the time interval during which a corresponding (e.g., respective) state of the RF signal 104 is generated by the RF generator 110. A duty cycle is generated during each clock cycle of the clock signal.

[0036] After receiving recipe signal 138, RF generator 108 stores data for generating RF signal 102. For example, one or more processors of RF generator 108 store the data for generating RF signal 102 in one or more memory devices of RF generator 108. Similarly, after receiving recipe signal 140, RF generator 110 stores data for generating RF signal 104. For example, one or more processors of RF generator 110 store the data for generating RF signal 104 in one or more memory devices of RF generator 110.

[0037] The processor 116 generates a trigger signal at the start of a clock cycle of the clock signal, transmits the trigger signal to the RF generator 108 via the transmission cable 128, and transmits the trigger signal to the RF generator 110 via the transmission cable 130. In response to receiving the trigger signal from the processor 116 via the transmission cable 128, the one or more processors of the RF generator 108 access data for generating the RF signal 102 from one or more memory devices of the RF generator 108 and generate the RF signal 102 in accordance with the data. In response to receiving the trigger signal from the processor 116 via the transmission cable 130, the one or more processors of the RF generator 110 access data for generating the RF signal 104 from one or more memory devices of the RF generator 110 and generate the RF signal 104 in accordance with the data.

[0038] The RF signal 102 is provided from the RF generator 108 via an RF cable 132 to an input I1 of the IMC 112, and the RF signal 104 is provided from the RF generator 110 via an RF cable 134 to an input I2 of the IMC 112. The IMC 112 modifies the impedance of the RF signal 102 to match the impedance of a load coupled to the output O1 of the IMC 112 with the impedance of a source coupled to the input I1, and outputs a first modified RF signal. Examples of sources coupled to the input I1 include the RF cable 132 and the RF generator 108. Examples of loads coupled to the output O1 include an RF transmission line 136 and a plasma chamber 114. The IMC 112 also modifies the impedance of the RF signal 104 to match the impedance of a load coupled to the output O1 of the IMC 112 with the impedance of a source coupled to the input I2, and outputs a second modified RF signal. Examples of sources coupled to the input I2 include the RF cable 134 and the RF generator 110. The IMC 112 provides a modified RF signal 142 at an output O1 by combining (eg, summing) the first and second modified RF signals.

[0039] The modified RF signal 142 is transmitted to the lower electrode 124 via the RF transmission line 136. Furthermore, when one or more process gases are supplied to the gap 126 in addition to supplying the modified RF signal 142, a plasma is ignited or maintained in the gap 126 to process the substrate S. An example of the one or more process gases includes an oxygen-containing gas, such as O. Other examples of the one or more process gases include a fluorine-containing gas, such as tetrafluoromethane (CF), sulfur hexafluoride (SF), hexafluoroethane (CF), etc. Examples of processing the substrate S include depositing material on the substrate, etching the substrate, and cleaning the substrate.

[0040] 2 is one embodiment of a graph 200 for illustrating multiple states of the power level of RF signal 102 (FIG. 1) and multiple states of the power level of RF signal 104 (FIG. 1). Graph 200 plots power level values ​​of RF signals 102 and 104 on the y-axis and time t on the x-axis. For example, graph 200 includes a plot 202 (solid line) of power level values ​​of RF signal 102 versus time t and a plot 204 (dashed line) of power level values ​​of RF signal 104 versus time t.

[0041] The power levels range from power level P0 to power level P10 in an ascending manner, and time t ranges progressively from time t0 to time t20. For example, the time interval between times t0 and t10 includes times t1, t2, t3, t4, t5, t6, t7, t8, and t9. In this example, time t10 occurs after time t9, which occurs after time t8, and so on, with time t1 occurring after time t0. Note that in this example, the time intervals between two consecutive times are equal. Illustratively, the time interval between times t2 and t1 is equal to the time interval between times t3 and t2. Also, in this example, various power levels P2, P3, P4, P5, P6, P7, P8, and P9 are between power levels P0 and P10. For example, power level P10 is greater than power level P9, which is greater than power level P8, and so on, with power level P1 being greater than power level P0. As another example, power level P1 is greater than power level P0, and power level P3 is greater than power level P1. Also in this example, power level P10 is greater than power level P3.

[0042] The clock signal has multiple cycles (e.g., cycle 1 and cycle 2). Cycle 1 extends or occurs from time t0 to time t10, and cycle 2 occurs from time t10 to time t20. Cycle 2 follows cycle 1.

[0043] At time t0, the power level of the RF signal 102 increases from power level P0 to power level P10, achieving state S1 of the RF signal 102. By way of example, power level P10 has a value (e.g., magnitude) in the range of 1 kilowatt (kW) to 100 kW. Illustratively, power level P10 has a power value of 1 kW. The power level of the RF signal 102 remains in state S1 (e.g., power level P10) from time t0 to time t1. The time interval between time t0 and time t1 is an example of a predetermined time interval, which is the duty cycle of state S1 of the RF signal 102. By way of example, the duty cycle of state S1 of the RF signal 102 is a time interval in the range of 5 percent (%) to 20 percent of cycle 1 of the clock signal.

[0044] Further, at time t1, the power level of the RF signal 102 decreases from power level P10 to power level P0, achieving state S0 of the RF signal 102. By way of example, power level P0 is a value (e.g., magnitude) that is substantially zero. Illustratively, power level P0 is a value within a range of 0 watts (W) to 200 watts. Further illustratively, power level P0 is zero watts. The power level of the RF signal 102 remains at state S0 (e.g., power level P0) from time t1 to time t6. The time interval between time t1 and time t6 is an example of a predetermined time interval, which is the duty cycle of state S0 of the RF signal 102 and is greater than the time interval between time t0 and time t1 of the duty cycle of state S1 of the RF signal 102. By way of example, the duty cycle of state S0 of the RF signal 102 is a time interval within a range of 20 percent to 60 percent of cycle 1 of the clock signal.

[0045] Further, at time t6, the power level of the RF signal 102 increases from power level P0 to power level P10, achieving state SB of the RF signal 102. The power level of the RF signal 102 remains in state SB (e.g., power level P10) from time t6 to time t7. The time interval between time t6 and time t7 is an example of a predetermined time interval, which is the duty cycle of state SB of the RF signal 102. By way of example, the duty cycle of state SB of the RF signal 102 is substantially equal to the duty cycle of state S1 of the RF signal 102. For example, the duty cycle of state SB of the RF signal 102 is a time interval within a range of 5 percent to 20 percent of cycle 1 of the clock signal. For further example, the duty cycle of state SB of the RF signal 102 is equal to the duty cycle of state S1 of the RF signal 102. As another example, the duty cycle of state SB of RF signal 102 is greater or less than the duty cycle of state S1 of RF signal 102 by a predetermined percentage (e.g., within 5 percent) of the duty cycle of state S1 of RF signal 102.

[0046] Also, at time t7, the power level of the RF signal 102 decreases from power level P10 to power level P0, achieving state SA of the RF signal 102. The power level of the RF signal 102 remains in state SA (e.g., power level P0) from time t7 to time t10. An example of the power level P0 of the RF signal 102 during state SB is zero watts. The time interval between time t7 and time t10 is an example of a predetermined time interval, which is the duty cycle of state SA of the RF signal 102 and is greater than the time interval between time t6 and time t7 of the duty cycle of state SB of the RF signal 102. As an example, the duty cycle of state SA of the RF signal 102 is a time interval in the range of 20 percent to 60 percent of cycle 1 of the clock signal. In the same manner as described herein with respect to cycle 1, states S1, S0, SB, and SA of the RF signal 102 are repeated during each additional cycle (e.g., cycle 2) of the clock signal.

[0047] Furthermore, at time t0, the power level of RF signal 104 increases from power level P0 to power level P3, achieving state S1 of RF signal 104. As an example, when both RF signals 102 and 104 transition to state S1 at time t0, RF signals 102 and 104 are pulsed synchronized to achieve state S1. Also, as an example, power level P3 has a value (e.g., magnitude) in the range of 1 kilowatt to 11 kilowatts. Illustratively, power level P3 has a power value of 1 kilowatt. The power level of RF signal 104 remains in state S1 (e.g., power level P3) from time t0 to time t1. The time interval between times t0 and t1 is the duty cycle of state S1 of RF signal 104. As an example, the duty cycle of state S1 of RF signal 104 is a time interval in the range of 5 percent to 20 percent of cycle 1 of the clock signal.

[0048] Further, at time t1, the power level of RF signal 104 decreases from power level P3 to power level P0, achieving state S0 of RF signal 104. As an example, when both RF signals 102 and 104 transition to state S0 at time t1, RF signals 102 and 104 are pulsed synchronized to achieve state S0. The power level of RF signal 104 remains at state S0 (e.g., power level P0) from time t1 to time t6. The time interval between times t1 and t6 is the duty cycle of state S0 of RF signal 104, which is greater than the time interval between times t0 and t1 of the duty cycle of state S1 of RF signal 104. As an example, the duty cycle of state S0 of RF signal 104 is a time interval within a range of 20 percent to 60 percent of cycle 1 of the clock signal.

[0049] Furthermore, at time t6, the power level of the RF signal 104 increases from power level P0 to power level P3, achieving state SB of the RF signal 104. As an example, when both RF signals 102 and 104 transition from state S0 to state SB at time t6, the RF signals 102 and 104 are pulsed synchronized to achieve state SB. The power level of the RF signal 104 remains in state SB (e.g., power level P3) from time t6 to time t7. The time interval between times t6 and t7 is equal to the time interval between t0 and t1. The time interval between times t6 and t7 is the duty cycle of state SB of the RF signal 104. As an example, the duty cycle of state SB of the RF signal 104 is substantially equal to the duty cycle of state S1 of the RF signal 104. For example, the duty cycle of state SB of the RF signal 104 is a time interval within a range of 5 percent to 20 percent of cycle 1 of the clock signal. To further illustrate, the duty cycle of state SB of RF signal 104 is equal to the duty cycle of state S1 of RF signal 104. To further illustrate, the duty cycle of state SB of RF signal 104 is greater than or less than the duty cycle of state S1 of RF signal 104 by a predetermined percentage (e.g., within 5 percent) of the duty cycle of state S1 of RF signal 104.

[0050] Also, at time t7, the power level of the RF signal 104 decreases from power level P3 to power level P1, achieving state SA of the RF signal 104. As an example, when both RF signals 102 and 104 transition from state SB to state SA at time t7, the RF signals 102 and 104 are pulsed synchronized to achieve state SB. As an example, power level P1 includes values ​​in the range of 200 watts to 1000 watts. For example, power level P1 is 200 watts. The power level of the RF signal 104 remains in state SA (e.g., power level P1) from time t7 to time t10. The time interval between times t7 and t10 is the duty cycle of state SA of the RF signal 104, which is greater than the time interval between times t6 and t7 of the duty cycle of state SB of the RF signal 104. As an example, the duty cycle of state SA of the RF signal 104 is a time interval in the range of 20 percent to 60 percent of cycle 1 of the clock signal. In the same manner as described herein with respect to cycle 1, the states S1, S0, SB, and SA of the RF signal 104 are repeated during each additional cycle (eg, cycle 2) of the clock signal.

[0051] Note that the sum of the duty cycles of states S1, S0, SB, and SA of RF signal 102 equals 100 percent of each cycle of the clock signal. For example, if the duty cycle of state S1 of RF signal 102 is 5 percent of cycle 1, the duty cycle of state S0 of RF signal 102 is 60 percent of cycle 1, and the duty cycle of state SB of RF signal 102 is 5 percent of cycle 1, then the duty cycle of state SA of RF signal 102 is 30 percent of cycle 1.

[0052] Similarly, the sum of the duty cycles of states S1, S0, SB, and SA of RF signal 104 equals 100 percent of each cycle of the clock signal. For example, if the duty cycle of state S1 of RF signal 104 is 5 percent of cycle 1, the duty cycle of state S0 of RF signal 104 is 60 percent of cycle 1, and the duty cycle of state SB of RF signal 104 is 5 percent of cycle 1, then the duty cycle of state SA of RF signal 104 is 30 percent of cycle 1.

[0053] Additionally, it should be noted that without including state SB of RF signal 104, the power level of the tertiary state of the RF signal (not shown) provided by RF generator 110 ranges from 0 watts to 200 watts. The tertiary state immediately follows the secondary state (not shown) of the RF signal, which in turn immediately follows the primary state (not shown) of the RF signal. The primary, secondary, and tertiary states are each different power levels of the RF signal (not shown) and are repeated during each cycle of the clock signal. By including state SB of RF signal 104, the power level P1 of state SA of RF signal 104 ranges from 200 watts to 1000 watts. The range of 200 watts to 1000 watts is expanded compared to the range of 0 watts to 200 watts. The expanded range reduces the amount of time that state SA of RF signal 104 occurs. This amount of time is reduced compared to the amount of time that the tertiary state (not shown) of the RF signal is applied, thereby reducing the amount of time that substrate S is processed. The expanded range increases the ion density of the plasma. The ion density is increased compared to the amount of ion density when the 0 Watts to 200 Watts range is applied. The increased ion density increases the stability of the plasma and prevents the plasma from being extinguished during processing of the substrate S. Additionally, the increased range results in faster depassivation of the constricted portion of the substrate S compared to when the 0 Watts to 200 Watts range is used.

[0054] In one embodiment, both RF signals 102 and 104 transition from state SA of a previous cycle (e.g., cycle 0) of the clock signal to state S1 within a predetermined time interval. The previous cycle precedes cycle 1 of the clock signal. When both RF signals 102 and 104 transition to state S1 within the predetermined time interval, RF signals 102 and 104 are pulsed in a synchronized manner to achieve state S1.

[0055] In one embodiment, both RF signals 102 and 104 transition from state S1 to state S0 within a predetermined time interval. When both RF signals 102 and 104 transition to state S0 within the predetermined time interval, RF signals 102 and 104 are pulsed in a synchronized manner to achieve state S0.

[0056] In one embodiment, both RF signals 102 and 104 transition from state SO to state SB within a predetermined time interval. When both RF signals 102 and 104 transition to state SB within the predetermined time interval, RF signals 102 and 104 are pulsed in a synchronized manner to achieve state SB.

[0057] In one embodiment, both RF signals 102 and 104 transition from state SB to state SA within a predetermined time interval. When both RF signals 102 and 104 transition to state SA within the predetermined time interval, RF signals 102 and 104 are pulsed in a synchronized manner to achieve state SA.

[0058] FIG. 3A is a side view of one embodiment of a portion 300 of a substrate S, illustrating the effect of applying a state S1 of an RF signal 102 and a state S1 of an RF signal 104 (FIG. 1). The portion 300 includes a substrate layer 302, a plurality of stack layers 304, a stack layer 306, another stack layer 308, and a mask layer 310. By way of example, the substrate layer 302 is silicon. By way of example, the stack layer 304 is a series of alternating silicon oxide and polysilicon (OPOP) layers, a series of alternating silicon oxide and silicon nitride (ONON) layers, or a silicon oxide layer. By way of example, the stack layer 306 is a polysilicon drain select gate (SGD) layer, and the stack layer 308 is a nitride or oxide layer. By way of example, the mask layer 310 is an aluminum nitride (AlN) layer, a silicon nitride layer, or a silicon oxide layer.

[0059] The stack layer 304 is located above and adjacent to the substrate layer 302. The stack layer 306 is located above and adjacent to the stack layer 304, and the stack layer 308 is located above and adjacent to the stack layer 306. The mask layer 310 is adjacent to and above the stack layer 308. The mask layer 310, the stack layer 308, the stack layer 306, and the stack layer 304 are stacked vertically along the y-axis. The y-axis is perpendicular to the x-axis and z-axis. The x-axis is horizontal. The z-axis is perpendicular to the y-axis.

[0060] During the period when the power levels of State S1 of RF signal 102 and State S1 of RF signal 104 occur, an etchant (e.g., a chemical) is generated in gap 126 when one or more process gases interact with modified RF signal 142. The etchant, represented in FIG. 3A as an "x," is an example of at least a portion of the plasma generated in gap 126. The etchant creates (e.g., etches) features in stack layers 304, 306, and 308. One example of one of the features is channel 312 extending vertically downward within stack layers 304, 306, and 308. Additionally, during the period when the power levels of State S1 of RF signal 102 and State S1 of RF signal 104 occur, a small amount of passivation migrates vertically downward within channel 312. The passivation is represented in FIG. 3A as an "o." Also, by way of example, the passivation portion is the deposition of a dielectric layer, such as a silicon layer or a silicon-containing layer, by etching one or more of stack layer 304, stack layer 306, and stack layer 308, as described herein.

[0061] In one embodiment, the substrate S includes more or fewer layers than the number of stack layers 304, 306, and 308 shown in FIG. 3A.

[0062] FIG. 3B is a diagram of one embodiment of a portion 320 of a substrate S illustrating passivation during state S0 of the RF signal 102 and state S0 of the RF signal 104 (FIG. 1). The portion 320 includes a substrate layer 302, stack layers 304, 306, and 308, and a mask layer 310. Furthermore, application of the power levels of state S0 of the RF signal 102 and state S0 of the RF signal 104 results in passivation 322 adjacent to and on sidewalls 324 of the mask layer 310 and passivation 326 on a top surface 328 of the mask layer 310. For example, the passivation 322 extends from the surface of the sidewalls 324 in the x-axis direction. In this example, the passivation 326 extends from the top surface 328 in the y-axis direction. By way of example, the sidewalls 324 laterally surround a portion of the channel 312 along the x-axis and z-axis, forming a tubular structure around a portion of the channel 312. Also, by way of example, each passivation portion 322 and 326 is a deposition of a dielectric layer, such as a silicon layer or a silicon-containing layer, by etching one or more of stack layer 304, stack layer 306, and stack layer 308. For example, atoms of a dielectric material, such as silicon, are removed by etching channel 312, and these atoms are deposited to form passivation portion 322 or 326.

[0063] 3C is a diagram of one embodiment of a portion 330 of the substrate S, illustrating that a portion of the passivation portion 322 (FIG. 3B) is lowered by application of the power levels of the RF signal 102 and RF signal 104 (FIG. 1) in the states SB and SB. The portion 330 includes the substrate layer 302, the stack layer 304, the stack layer 306, the stack layer 308, and the mask layer 310. During a period in which a plasma is generated or maintained in the gap 126 by application of the RF signal 102 and RF signal 104 in the states SB, at least a portion of the passivation portion 322 (FIG. 3B) is lowered vertically along the y-axis within the channel 312 and deposited on a sidewall 332 of the stack layer 304, a sidewall 334 of the stack layer 306, and a sidewall 336 of the stack layer 308. The sidewalls 332, 334, and 336 form the pillars of the channel 312, and the sidewall 324 forms the constriction of the channel 312. For example, the pillars of channel 312 include sidewalls 332, 334, and 336, and the narrowing portion of channel 312 includes sidewall 324. A portion of passivation 322 is deposited on the pillars to form passivation 338 adjacent to sidewalls 332, 334, and 336. For example, passivation 338 is formed adjacent to sidewalls 332, 334, and 336 in the direction along the x-axis, reducing the width of channel 312 adjacent to sidewalls 332, 334, and 334 and increasing the width of channel 312 at the narrowing portion. The width of channel 312 is an example of a critical dimension (CD) measured horizontally along the x-axis. Note that the amount of passivation 322 ( FIG. 3B ) adjacent to sidewall 324 of mask layer 310 is reduced to provide passivation 340 adjacent to sidewall 324. For example, the amount of passivation 340 is less than the amount of passivation 322 .

[0064] Applying the RF signal 102 in state SB and the RF signal 104 in state SB hardens the passivation portion 326 (FIG. 3B) into the passivation portion 342. Furthermore, applying the RF signal 102 in state SB and the RF signal 104 in state SB etches the feature in the substrate S vertically further downward along the y-axis compared to state S1. For example, when a portion of the passivation portion 322 (FIG. 3B) is lowered vertically downward, the passivation portion 338 is formed. By lowering the portion of the passivation portion 322 downward, the critical dimension (e.g., width along the x-axis) increases at the constriction, which can increase the etch rate of etching the feature in the substrate S. The passivation portion 338 also protects the pillars of the substrate S from etching, thereby increasing the etch rate.

[0065] FIG. 3D is a diagram of one embodiment of a portion 350 of a substrate S illustrating that application of state SA of RF signal 102 (FIG. 1) and state SA of RF signal 104 (FIG. 1) reduces passivation 340 (FIG. 3C) to substantially zero. For example, there is no passivation adjacent to sidewall 324 of mask layer 310. As another example, less than 5 percent of passivation 340 remains on sidewall 324 during or after application of state SA of RF signal 102 and state SA of RF signal 104. In this manner, passivation 340 is clipped from sidewall 324 of the constriction of channel 312. The clipping increases the CD at the constriction of substrate S, increasing the etch rate for etching substrate S. For example, the CD at the constriction increases to prepare for state S1 of RF signal 102 during the immediately following cycle of the clock signal.

[0066] 4 is a diagram of an embodiment of a system 400 to explain operational details of an RF generator 410, which is an example of RF generator 108 or RF generator 110 (FIG. 1). RF generator 410 includes a digital signal processor (DSP) 404 and multiple controllers.

[0067] The controller of the RF generator 410 includes a power controller PWRS1, a power controller PWRS0, a power controller PWRSB, and a power controller PWRSA. The controller of the RF generator 410 also includes a duty cycle controller DCS1, another duty cycle controller DCS0, a duty cycle controller DCSB, and a duty cycle controller DCSA. The RF generator 410 further includes a driver amplifier system (DAS) 406 and an RF power supply 408.

[0068] Examples of DSP 404 include an integrated circuit chip and a controller. DAS 406 includes a driver and an amplifier. Examples of drivers include one or more transistors, as described herein. An example of an RF power source, as described herein, is an RF oscillator, which is an electronic circuit that generates a periodic oscillating signal at a radio frequency (e.g., high or low frequency).

[0069] The DSP 404 is coupled to the processor 116 via a transfer cable 412. The transfer cable 412 is an example of the transfer cable 128 or the transfer cable 130 (FIG. 1). The DSP 404 is coupled to the power controllers PWRS1, PWRS0, PWRSB, and PWRSA. The DSP 404 is also coupled to the duty cycle controllers DCS1, DCS0, DCSB, and DCSA. The duty cycle controller DCS1 is coupled to the power controller PWRS1. Similarly, the duty cycle controller DCS0 is coupled to the power controller PWRS0, the duty cycle controller DCSB is coupled to the power controller PWRSB, and the duty cycle controller DCSA is coupled to the power controller PWRSA. The power controllers PWRS1, PWRS0, PWRSB, and PWRSA are coupled to the driver of the DAS 406. The driver of the DAS 406 is coupled to the amplifier of the DAS 406, which is coupled to the RF power supply 408.

[0070] The RF power supply 408 is coupled to an RF cable 414, which is an example of the RF cable 132 or the RF cable 134 (FIG. 1). The DSP 404 receives a recipe signal 416 via the transfer cable 412, obtains data for generating an RF signal 418 from the recipe signal 416, and stores the data for generating the RF signal 418 in a memory device of the DSP 404. The recipe signal 416 is an example of the recipe signal 138 or the recipe signal 140 (FIG. 1). The RF signal 418 is also an example of the RF signal 102 or the RF signal 104 (FIG. 1). The DSP 404 analyzes the data for generating the RF signal 418 to determine a power level for a state S1 of the RF signal 418, a power level for a state S0 of the RF signal 418, a power level for a state SB of the RF signal 418, and a power level for a state SA of the RF signal 418. Additionally, the DSP 404 analyzes the data for generating the RF signal 418 to determine a duty cycle for state S1 of the RF signal 418, a duty cycle for state S0 of the RF signal 418, a duty cycle for state SB of the RF signal 418, and a duty cycle for state SA of the RF signal 418. The DSP 404 also analyzes the data for generating the RF signal 418 to determine a frequency level (e.g., low frequency or high frequency) of the RF signal 418.

[0071] DSP 404 transmits the power level of state S1 of RF signal 418 to power controller PWRS1, the power level of state S0 of RF signal 418 to power controller PWRS0, the power level of state SB of RF signal 418 to power controller PWRSB, and the power level of state SA of RF signal 418 to power controller PWRSA. The processor of power controller PWRS1 stores the power level of state S1 of RF signal 418 in a memory device of power controller PWRS1. Similarly, the processor of power controller PWRS0 stores the power level of state S0 of RF signal 418 in the memory device of power controller PWRS0, the processor of power controller PWRSB stores the power level of state SB of RF signal 418 in the memory device of power controller PWRSB, and the processor of power controller PWRSA stores the power level of state SA of RF signal 418 in the memory device of power controller PWRSA.

[0072] DSP 404 also sends the duty cycle of state S1 of RF signal 418 to duty cycle controller DCS1, sends the duty cycle of state S0 of RF signal 418 to duty cycle controller DCS0, sends the duty cycle of state SB of RF signal 418 to duty cycle controller DCSB, and sends the duty cycle of state SA of RF signal 418 to duty cycle controller DCSA. The processor of duty cycle controller DCS1 stores the duty level of state S1 of RF signal 418 in a memory device of duty cycle controller DCS1. Similarly, the processor of duty cycle controller DCS0 stores the duty level of state S0 of RF signal 418 in a memory device of duty cycle controller DCS0, the processor of duty cycle controller DCSB stores the duty cycle of state SB of RF signal 418 in a memory device of duty cycle controller DCSB, and the processor of duty cycle controller DCSA stores the duty cycle of state SA of RF signal 418 in a memory device of duty cycle controller DCSA.

[0073] Additionally, DSP 404 transmits the frequency level of RF signal 418 to each of power controllers PWRS1, PWRS0, PWRSB, and PWRSA. The processor of power controller PWRS1 stores the frequency level of RF signal 418 in a memory device of power controller PWRS1. Similarly, the processor of power controller PWRS0 stores the frequency level of RF signal 418 in a memory device of power controller PWRSB, and the processor of power controller PWRSA stores the frequency level of RF signal 418 in a memory device of power controller PWRSA.

[0074] In response to receiving a trigger signal from the processor 116, the DSP 404 executes the recipe received in the recipe signal 416. For example, upon receiving the trigger signal, the DSP 404 sends a control signal to the duty cycle controller DCS1 to control the power controller PWRS1. In response to receiving the control signal from the DSP 404, the duty cycle controller DCS1 generates an on duty cycle control signal for the state S1 of the RF signal 418 and sends the on duty cycle control signal to the power controller PWRS1. Upon receiving the on duty cycle control signal for the state S1 of the RF signal 418, the processor of the power controller PWRS1 accesses the power level and frequency level for the state S1 of the RF signal 418 from the memory device of the power controller PWRS1 and generates an on command signal indicating the power level and frequency level. The processor of the power controller PWRS1 sends the on command signal to the DAS 406. In response to receiving the on command signal indicating the power level and frequency level for state S1 of RF signal 418, the driver of DAS 406 generates a current signal corresponding to the power level for state S1 of RF signal 418 and the frequency level of RF signal 418 and sends the current signal to the amplifier of DAS 406. The amplifier of DAS 406 amplifies the current signal (e.g., increases the magnitude of the current signal), outputs the amplified current signal, and sends the amplified current signal to RF power supply 408 to drive RF power supply 408. Upon receiving the amplified current signal for state S1 of RF signal 418, RF power supply 408 generates the power level and frequency level of RF signal 418 for state S1.

[0075] Additionally, in this example, the processor of duty cycle controller DCS1 includes a time counter that begins counting when the on duty cycle control signal is sent to power controller PWRS1. Based on the count, the processor of duty cycle controller DCS1 determines that the period of state S1 of RF signal 418 has ended, and upon such determination, the processor of duty cycle controller DCS1 generates an off duty cycle control signal. The processor of duty cycle controller DCS1 sends the off duty cycle control signal for state S1 of RF signal 418 to power controller PWRS1 and DSP 404. RF power supply 408 continues to generate the power level of state S1 of RF signal 418 until the off duty cycle control signal for state S1 is sent to power controller PWRS1.

[0076] Upon receiving the off duty cycle control signal for state S1 of RF signal 418, the processor of power controller PWRS1 generates an off command signal. The processor of power controller PWRS1 sends the off command signal to DAS 406. In response to receiving the off command signal, DAS 406 stops generating an amplified current signal corresponding to the power level for state S1 of RF signal 418, and RF power supply 408 ceases continuing to generate the power level for state S1 of RF signal 418.

[0077] Also in this example, in response to receiving an off duty cycle control signal for state S1 from the processor of duty cycle controller DCS1, DSP 404 sends a control signal to duty cycle controller DCS0 to control power controller PWRS0. In response to receiving the control signal from DSP 404, duty cycle controller DCS0 generates an on duty cycle control signal for state S0 of RF signal 418 and sends the on duty cycle control signal to power controller PWRS0. Upon receiving the on duty cycle control signal for state S0 of RF signal 418, the processor of power controller PWRS0 accesses the power level and frequency level for state S0 of RF signal 418 from the memory device of power controller PWRS0 and generates an on command signal indicating the power level and frequency level. The processor of power controller PWRS0 sends the on command signal to DAS 406. In response to receiving the on command signal, the driver of the DAS 406 generates a current signal corresponding to the power level and frequency level for state S0 of the RF signal 418 and sends the current signal to the amplifier of the DAS 406. The amplifier of the DAS 406 amplifies the current signal (e.g., increases the magnitude of the current signal), outputs the amplified current signal, and sends the amplified current signal to the RF power supply 408 to drive the RF power supply 408. Upon receiving the amplified current signal for state S0 of the RF signal 418, the RF power supply 408 generates the power level and frequency level of the RF signal 418 for state S0.

[0078] Note that in this example, when the power level for state S0 of RF signal 418 is zero, the processor of power controller PWRSO does not generate or send an ON command signal to DAS 406, and DAS 406 does not generate a current signal. If no current signal is generated, RF power supply 408 outputs such that the power level of state S0 of RF signal 418 is zero.

[0079] Additionally, in this example, the processor of duty cycle controller DCS0 includes a time counter that begins counting when the on duty cycle control signal is sent to power controller PWRS0. Based on the count, the processor of duty cycle controller DCS0 determines that the period of state S0 of RF signal 418 has ended, and upon such determination, the processor of duty cycle controller DCS0 generates an off duty cycle control signal. The processor of duty cycle controller DCS0 sends the off duty cycle control signal for state S0 of RF signal 418 to power controller PWRS0 and DSP 404. RF power supply 408 continues to generate or output the power level of state S0 of RF signal 418 until the off duty cycle control signal for state S0 is sent to power controller PWRS0.

[0080] Upon receiving the off duty cycle control signal for state S0 of RF signal 418, the processor of power controller PWRSO generates an off command signal. The processor of power controller PWRSO sends the off command signal to DAS 406. In response to receiving the off command signal, DAS 406 stops generating an amplified current signal corresponding to the power level for state S0 of RF signal 418, and RF power supply 408 ceases continuing to generate the power level for state S0 of RF signal 418.

[0081] Further, in this example, in response to receiving an off duty cycle control signal for state S0 from the processor of duty cycle controller DCS0, DSP 404 sends a control signal to duty cycle controller DCSB to facilitate control of power controller PWRSB. In response to receiving the control signal from DSP 404, duty cycle controller DCSB generates an on duty cycle control signal for state SB of RF signal 418 and sends the on duty cycle control signal to power controller PWRSB. Upon receiving the on duty cycle control signal for state SB of RF signal 418, the processor of power controller PWRSB accesses the power level for state SB of RF signal 418 and the frequency level of RF signal 418 from the memory device of power controller PWRSB and generates an on command signal indicating the power level and frequency level for state SB. The processor of power controller PWRSB sends the on command signal to DAS 406. In response to receiving the on command signal, the driver of the DAS 406 generates a current signal corresponding to the power level for state SB of the RF signal 418 and the frequency level of the RF signal 418, and sends the current signal to the amplifier of the DAS 406. The amplifier of the DAS 406 amplifies the current signal (e.g., increases the magnitude of the current signal), outputs the amplified current signal, and sends the amplified current signal to the RF power supply 408 to drive the RF power supply 408. Upon receiving the amplified current signal for state SB of the RF signal 418, the RF power supply 408 generates the power level of the RF signal 418 and the frequency level of the RF signal 418 for state SB.

[0082] Additionally, in this example, the processor of duty cycle controller DCSB includes a time counter that begins counting when the on duty cycle control signal is sent to power controller PWRSB. Based on the count, the processor of duty cycle controller DCSB determines that the period of state SB of RF signal 418 has ended, and upon such determination, the processor of duty cycle controller DCSB generates an off duty cycle control signal. The processor of duty cycle controller DCSB sends the off duty cycle control signal for state SB of RF signal 418 to power controller PWRSB and DSP 404. RF power supply 408 continues to generate the power level of state SB of RF signal 418 until the off duty cycle control signal for state SB is sent to power controller PWRSB.

[0083] Upon receiving the off duty cycle control signal for state SB of RF signal 418, the processor of power controller PWRSB generates an off command signal. The processor of power controller PWRSB sends the off command signal to DAS 406. In response to receiving the off command signal, DAS 406 stops generating an amplified current signal corresponding to the power level for state SB of RF signal 418, and RF power supply 408 ceases generating the power level for state SB of RF signal 418.

[0084] Also in this example, in response to receiving an off duty cycle control signal for state SB from the processor of duty cycle controller DCSB, DSP 404 sends a control signal to duty cycle controller DCSA to control power controller PWRSA. In response to receiving the control signal from DSP 404, duty cycle controller DCSA generates an on duty cycle control signal for state SA of RF signal 418 and sends the on duty cycle control signal to power controller PWRSA. Upon receiving the on duty cycle control signal for state SA of RF signal 418, the processor of power controller PWRSA accesses the power level and frequency level of RF signal 418 for state SA from the memory device of power controller PWRSA and generates an on command signal indicating the power level and frequency level. The processor of power controller PWRSA sends the on command signal to DAS 406. In response to receiving the on command signal, the driver of the DAS 406 generates a current signal corresponding to the power level for state SA of the RF signal 418 and the frequency level of the RF signal 418, and sends the current signal to the amplifier of the DAS 406. The amplifier of the DAS 406 amplifies the current signal (e.g., increases the magnitude of the current signal), outputs the amplified current signal, and sends the amplified current signal to the RF power supply 408 to drive the RF power supply 408. Upon receiving the amplified current signal for state SA of the RF signal 418, the RF power supply 408 generates the power level of the RF signal 418 and the frequency level of the RF signal 418 for state SA.

[0085] Note that in this example, when the power level of RF signal 418 for state SA is zero, the processor of power controller PWRSA does not generate or send an ON command signal to DAS 406, and DAS 406 does not generate a current signal. If no current signal is generated, RF power supply 408 outputs RF signal 418 such that the power level of state SA is zero.

[0086] Additionally, in this example, the processor of duty cycle controller DCSA includes a time counter that begins counting when the on duty cycle control signal is sent to power controller PWRSA. Based on the count, the processor of duty cycle controller DCSA determines that the period of state SA of RF signal 418 has ended, and upon such determination, the processor of duty cycle controller DCSA generates an off duty cycle control signal. The processor of duty cycle controller DCSA sends the off duty cycle control signal for state SA of RF signal 418 to power controller PWRSA and DSP 404. RF power supply 408 continues to generate the power level of state SA of RF signal 418 until the off duty cycle control signal for state SA is sent to power controller PWRSA.

[0087] Upon receiving the off duty cycle control signal for state SA of RF signal 418, the processor of power controller PWRSA generates an off command signal. The processor of power controller PWRSA sends the off command signal to DAS 406. In response to receiving the off command signal, DAS 406 stops generating an amplified current signal corresponding to the power level for state SA of RF signal 418, and RF power supply 408 ceases generating the power level for state SA of RF signal 418.

[0088] Further, in this example, in response to receiving an off-duty cycle control signal for state SA from the processor of duty cycle controller DCSB and determining that the clock signal received from processor 116 via transfer cable 412 indicates the end of cycle 1 and the beginning of cycle 2 of the clock signal, DSP 404 repeatedly sends control signals to duty cycle controller DCS1 to control power controller PWRS1 to repeat state S1 of RF signal 418 during cycle 2 of the clock signal. Further, during cycle 2, states S0, SB, and SA are repeated in the same manner as during cycle 1 of the clock signal.

[0089] In one embodiment, one or more controllers are used in place of DSP 404, power controllers PWRS1, PWRS0, PWRSB, and PWRSA, and duty cycle controllers DCS1, DCS0, DCSB, and DCSA. For example, a single controller performs the functions as performed by DSP 404, power controllers PWRS1, PWRS0, PWRSB, and PWRSA, and duty cycle controllers DCS1, DCS0, DCSB, and DCSA described herein. As another example, a single controller performs the functions as performed by power controllers PWRS1, PWRS0, PWRSB, and PWRSA described herein. As yet another example, a single controller performs the functions as performed by duty cycle controllers DCS1, DCS0, DCSB, and DCSA described herein.

[0090] The embodiments described herein may be practiced with various computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network.

[0091] In some embodiments, the controller is part of a system that may be part of the examples described above. Such systems include semiconductor processing equipment, such as one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems are integrated with electronics for controlling the operation of the system before, during, and after processing of semiconductor wafers or substrates. This electronics is referred to as a "controller," which may control various components or subcomponents of one or more systems. Depending on the processing requirements and / or the type of system, the controller is programmed to control any of the processes disclosed herein, such as process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer loading and unloading into the tool, and wafer loading and unloading into other transfer tools and / or load locks connected or interfacing with the system.

[0092] Broadly speaking, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that, for example, receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various personalizations (or program files) that define parameters, factors, variables, etc. for performing a particular process on or for a semiconductor wafer or for a system. Program instructions, in some embodiments, are part of a recipe defined by a process engineer to accomplish one or more processing steps during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer types.

[0093] The controller, in some embodiments, is part of, or coupled to, a computer integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be all or part of a host computer in the "cloud" or at a fab that allows remote access to wafer processing. By providing remote access to the system, the computer can monitor the current progress of a manufacturing operation, review the history of past manufacturing operations, review trends or performance criteria from multiple manufacturing operations, modify parameters of a current process, set up processing steps following a current process, or initiate a new process.

[0094] In some embodiments, a remote computer (e.g., a server) provides process recipes to the system over a network, including a local network or the Internet. The remote computer includes a user interface that allows for input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data defining parameters, factors, and / or variables for each processing step performed during one or more operations. It should be understood that the parameters, factors, and / or variables are specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as described above, a controller may be distributed, such as by including one or more separate controllers networked together and working toward a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on a chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) combined to control a process on the chamber.

[0095] Without being limited thereto, in various embodiments, exemplary systems to which the present methods may be applied include plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, clean chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems associated with or used in the fabrication and / or production of semiconductor wafers.

[0096] It is further noted that in some embodiments, the above operations are applicable to several types of plasma chambers (e.g., plasma chambers including inductively coupled plasma (ICP) reactors, transformer-coupled plasma chambers, conductor tools, dielectric tools, plasma chambers including electron cyclotron resonance (ECR) reactors, etc.). For example, one or more RF generators are coupled to an inductor in an ICP reactor. Examples of inductor shapes include a solenoid, a dome-shaped coil, a flat coil, etc.

[0097] As described above, depending on the process step or steps being performed by the tool, the host computer communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools installed throughout the factory, a main computer, other controllers, or tools used in material transport to and from containers of wafers to tool locations and / or load ports within a semiconductor manufacturing factory.

[0098] In view of the above embodiments, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These operations physically manipulate physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations.

[0099] Some embodiments also relate to a hardware unit or apparatus for performing these operations, where the apparatus is specially configured for a special purpose computer. When defined as a special purpose computer, the computer performs other processes, program execution, or routines that are not part of the special purpose computer while remaining operable for the special purpose.

[0100] In some embodiments, the operations may be processed by a computer selectively activated or configured by one or more computer programs stored in a computer memory or cache, or obtained over a computer network. When data is obtained over a computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0101] In one or more embodiments, the program may also be written as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is a data storage hardware unit (e.g., a memory device) that stores data, which is then read by a computer system. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), recordable CDs (CD-Rs), rewritable CDs (CD-RWs), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium comprises a computer-readable tangible medium distributed over network-coupled computer systems such that the computer-readable code is stored and executed in a distributed fashion.

[0102] Although the method operations above have been described in a particular order, it should be understood that in various embodiments, other housekeeping operations may be performed between operations, the method operations may be adjusted to occur at slightly different times, may be distributed in a system that allows the method operations to occur at various intervals, or may be performed in a different order than described above.

[0103] It should further be noted that in some embodiments, one or more features from any of the above-described embodiments may be combined with one or more features of any of the other embodiments without departing from the scope described in the various embodiments described in this disclosure.

[0104] Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. The present embodiments are therefore to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

1. 1. A method for increasing the passivation and etching rate of a substrate, comprising: generating a kilohertz radio frequency (RF) signal; generating a megahertz RF signal; providing the kilohertz RF signal and the megahertz RF signal to an impedance matching circuit coupled to an electrode of a plasma chamber; During a clock cycle of the clock signal, transitioning to a first state for etching the substrate by synchronously pulsing the kilohertz RF signal and the megahertz RF signal; maintaining the kilohertz RF signal and the megahertz RF signal in the first state for a first predetermined period of time; synchronously transitioning the kilohertz RF signal and the megahertz RF signal from the first state to a second state to achieve passivation on the sidewalls and top surface of a mask layer of the substrate; maintaining the kilohertz RF signal and the megahertz RF signal in the second state for a second predetermined time period longer than the first predetermined time period, wherein a power level of the kilohertz RF signal is less than a power level of the kilohertz RF signal during the first state and a power level of the megahertz RF signal is less than a power level of the megahertz RF signal during the first state; synchronously pulsing the kilohertz RF signal and the megahertz RF signal from the second state to a third state to advance the passivation from the substrate constriction to the substrate pillar; maintaining the kilohertz RF signal and the megahertz RF signal in the third state for a third predetermined time period substantially equal to the first predetermined time period, wherein a power level of the kilohertz RF signal is greater than the power level of the kilohertz RF signal during the second state and a power level of the megahertz RF signal is greater than the power level of the megahertz RF signal during the second state; transitioning the kilohertz RF signal and the megahertz RF signal from the third state to a fourth state in a synchronous manner, thereby reducing the passivation from the constriction in the substrate; maintaining the kilohertz RF signal and the megahertz RF signal in the fourth state for a fourth predetermined period longer than the third predetermined period, wherein a power level of the kilohertz RF signal is less than the power level of the kilohertz RF signal during the third state and a power level of the megahertz RF signal is less than the power level of the megahertz RF signal during the third state.

2. 10. The method of claim 1, the power level of the kilohertz RF signal during each of the first and third states is in the range of 1 kilowatt to 100 kilowatts for etching the substrate; The method, wherein the power level of the megahertz RF signal during each of the first and third states ranges from 1 kilowatt to 11 kilowatts for etching the substrate.

3. 3. The method of claim 2, the power level of the kilohertz RF signal during the first state is equal to the power level of the kilohertz RF signal during the third state to etch the substrate; The method, wherein the power level of the megahertz RF signal during the first state is equal to the power level of the megahertz RF signal during the third state to etch the substrate.

4. 10. The method of claim 1, wherein the power level of each of the kilohertz RF signal and the megahertz RF signal is substantially zero during the second state to achieve the passivation.

5. 5. The method of claim 4, the power level of each of the kilohertz RF signal and the megahertz RF signal during the second state ranges from 0 watts to 200 watts to achieve the passivation.

6. 10. The method of claim 1, the power level of the kilohertz RF signal is zero during the fourth state; The method, wherein the power level of the megahertz RF signal ranges from 200 watts to 1000 watts to reduce the passivation from the constriction of the substrate during the fourth state.

7. 10. The method of claim 1, the first predetermined period is in the range of 5 percent to 20 percent of the clock cycle; the second predetermined period is in the range of 20 percent to 60 percent of the clock cycle; the third predetermined period is in the range of 5 percent to 20 percent of the clock cycle; The method of claim 1, wherein the fourth predetermined period ranges from 20 percent to 60 percent of the clock cycle, such that the first through fourth periods sum to 100 percent of the clock cycle.

8. 8. The method of claim 7, the first predetermined period is five percent of the clock cycle; the second predetermined period is 60 percent of the clock cycle; the third predetermined period is five percent of the clock cycle; The method, wherein the fourth predetermined period is 30 percent of the clock cycle.

9. 10. The method of claim 1, the third state of the megahertz RF signal facilitating increasing a power level of the megahertz RF signal from a first range to a second range during the fourth state; the second range facilitates increasing the ion density of the plasma in the plasma chamber compared to the first range, thereby increasing the stability of the plasma; applying the second range for a shorter period of time than applying the first range; The short period of time is the fourth predetermined period of time.

10. 10. The method of claim 9, the first range is between 0 watts and 200 watts; The method wherein the second range is between 200 watts and 1000 watts.

11. 10. The method of claim 1, the first predetermined period of time is equal to the third predetermined period of time for etching the substrate; The method wherein the second predetermined period of time is longer than the fourth predetermined period of time to achieve the passivation.

12. 1. A controller for increasing passivation and etching rate of a substrate, the controller comprising:

1. A processor, comprising: controlling a first radio frequency (RF) generator to generate a kilohertz RF signal; controlling a second RF generator to generate a megahertz RF signal; controlling the first RF generator and the second RF generator during a clock cycle of a clock signal; transitioning to a first state by synchronously pulsing the kilohertz RF signal and the megahertz RF signal; maintaining the kilohertz RF signal and the megahertz RF signal in the first state for a first predetermined period of time; transitioning the kilohertz RF signal and the megahertz RF signal from the first state to a second state so as to synchronize the kilohertz RF signal and the megahertz RF signal; maintaining the kilohertz RF signal and the megahertz RF signal in the second state for a second predetermined time period longer than the first predetermined time period, wherein a power level of the kilohertz RF signal is less than a power level of the kilohertz RF signal during the first state and a power level of the megahertz RF signal is less than a power level of the megahertz RF signal during the first state; transitioning the kilohertz RF signal and the megahertz RF signal from the second state to a third state so as to synchronize the kilohertz RF signal and the megahertz RF signal; maintaining the kilohertz RF signal and the megahertz RF signal in the third state for a third predetermined time period substantially equal to the first predetermined time period, wherein a power level of the kilohertz RF signal is greater than the power level of the kilohertz RF signal during the second state and a power level of the megahertz RF signal is greater than the power level of the megahertz RF signal during the second state; transitioning the kilohertz RF signal and the megahertz RF signal from the third state to a fourth state to synchronize them; and a processor configured to maintain the kilohertz RF signal and the megahertz RF signal in the fourth state for a fourth predetermined period longer than the third predetermined period, wherein a power level of the kilohertz RF signal is less than the power level of the kilohertz RF signal during the third state and a power level of the megahertz RF signal is less than the power level of the megahertz RF signal during the third state; a memory device coupled to the processor; A controller equipped with

13. 13. The controller of claim 12, the power level of the kilohertz RF signal during each of the first and third states is in the range of 1 kilowatt to 100 kilowatts for etching the substrate; The power level of the megahertz RF signal during each of the first and third states ranges from 1 kilowatt to 11 kilowatts.

14. 14. The controller of claim 13, the power level of the kilohertz RF signal during the first state is equal to the power level of the kilohertz RF signal during the third state to etch the substrate; A controller, wherein the power level of the megahertz RF signal during the first state is equal to the power level of the megahertz RF signal during the third state.

15. 13. The controller of claim 12, The power level of each of the kilohertz RF signal and the megahertz RF signal is substantially zero during the second state.

16. 16. The controller of claim 15, The power level of each of the kilohertz RF signal and the megahertz RF signal during the second state ranges from 0 watts to 200 watts.

17. 13. The controller of claim 12, the power level of the kilohertz RF signal is zero during the fourth state; The power level of the megahertz RF signal ranges from 200 watts to 1000 watts during the fourth state.

18. 13. The controller of claim 12, the first predetermined period is in the range of 5 percent to 20 percent of the clock cycle; the second predetermined period is in the range of 20 percent to 60 percent of the clock cycle; the third predetermined period is in the range of 5 percent to 20 percent of the clock cycle; the fourth predetermined period of time is in the range of 20 percent to 60 percent of the clock cycle, such that the first through fourth periods sum to 100 percent of the clock cycle.

19. 18. The controller of claim 17, the first predetermined period is five percent of the clock cycle; the second predetermined period is 60 percent of the clock cycle; the third predetermined period is five percent of the clock cycle; The controller, wherein the fourth predetermined period is 30 percent of the clock cycle.

20. 1. A system for increasing the passivation and etching rate of a substrate, the system comprising: a first radio frequency (RF) generator configured to generate a kilohertz RF signal; a second RF generator configured to generate a megahertz RF signal; an impedance matching circuit coupled to the first RF generator and the second RF generator, the impedance matching circuit receiving the kilohertz RF signal and the megahertz RF signal and outputting a modified RF signal; a plasma chamber coupled to the impedance matching circuit, the plasma chamber receiving the modified RF signal; a controller coupled to the first RF generator and the second RF generator, controlling the first RF generator and the second RF generator during a clock cycle of a clock signal; transitioning to a first state by synchronously pulsing the kilohertz RF signal and the megahertz RF signal; maintaining the kilohertz RF signal and the megahertz RF signal in the first state for a first predetermined period of time; transitioning the kilohertz RF signal and the megahertz RF signal from the first state to a second state so as to synchronize the kilohertz RF signal and the megahertz RF signal; maintaining the kilohertz RF signal and the megahertz RF signal in the second state for a second predetermined time period longer than the first predetermined time period, wherein a power level of the kilohertz RF signal is less than a power level of the kilohertz RF signal during the first state and a power level of the megahertz RF signal is less than a power level of the megahertz RF signal during the first state; transitioning the kilohertz RF signal and the megahertz RF signal from the second state to a third state so as to synchronize the kilohertz RF signal and the megahertz RF signal; maintaining the kilohertz RF signal and the megahertz RF signal in the third state for a third predetermined time period substantially equal to the first predetermined time period, wherein a power level of the kilohertz RF signal is greater than the power level of the kilohertz RF signal during the second state and a power level of the megahertz RF signal is greater than the power level of the megahertz RF signal during the second state; transitioning the kilohertz RF signal and the megahertz RF signal from the third state to a fourth state to synchronize them; and a controller configured to maintain the kilohertz RF signal and the megahertz RF signal in the fourth state for a fourth predetermined period that is longer than the third predetermined period, wherein a power level of the kilohertz RF signal is less than the power level of the kilohertz RF signal during the third state and a power level of the megahertz RF signal is less than the power level of the megahertz RF signal during the third state.

21. 22. The system of claim 21, the third state of the megahertz RF signal facilitating increasing a power level of the megahertz RF signal from a first range to a second range during the fourth state; the second range facilitates increasing the ion density of the plasma in the plasma chamber compared to the first range, thereby increasing the stability of the plasma; applying the second range for a shorter period of time than applying the first range; The short period of time is the fourth predetermined period of time.

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