Semiconductor device and method for manufacturing the same

Abstract

A method for manufacturing a semiconductor device (10) includes providing a semiconductor region (14) of a first conductivity type. A first region (141) having the first conductivity type within the semiconductor region. The first region provides a JFET channel region (141A) for a JFET device (110). A second region (31) having a second conductivity type is provided within the first region. The second region provides a body region for the MOSFET device and a gate region for the JFET device. The second region includes a first portion (31A) and a second portion (31B) below the first portion. The second portion has a higher peak dopant concentration than the first portion. A third region (37) having the first conductivity type is provided within the second region and self-aligned to the second region. The third region provides a JFET source for the JFET device.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) Not applicable.

[0002] FIELD OF THE DISCLOSURE The present disclosure relates generally to electronic devices, and more particularly to methods of forming semiconductor devices and semiconductor device structures. [Background technology]

[0003] Silicon carbide (SiC) semiconductor devices, such as SiC MOSFETs, have several advantageous features compared to, for example, conventional silicon-based devices. For example, SiC MOSFETs are well suited for high-power applications. SiC MOSFETs can handle high voltages and high operating temperatures. Furthermore, SiC MOSFETs have low drain-source on-resistance (R DSON ) (for designs with short channel regions), and fast switching with low power losses, resulting in highly efficient operation. The short channel region design requirement is necessary because SiC MOSFETs have relatively low channel mobility compared to silicon-based devices.

[0004] The challenge arising from the short channel requirement is that the short channel leads to insufficient drain current saturation, which makes SiC MOSFETs unable to operate at high drain-source voltages (V DS ) can experience very high drain currents. In addition, the channel resistance has a negative dependence on temperature (i.e., resistance increases with increasing temperature), so device performance deteriorates if strong self-heating occurs during short-circuit operation. As a result, the short-circuit capability of SiC MOSFETs may be too short for the associated gate driver device to sense and turn off the SiC MOSFET before damage or failure occurs.

[0005] Poor short-circuit performance is a significant issue because short-circuit events can occur in many widely used power electronics applications, such as automotive traction inverters. Addressing this issue can also limit the minimum usable on-resistance of SiC MOSFETs. That is, there is a significant trade-off between short-circuit performance and on-resistance performance in SiC MOSFETs, which is becoming more challenging as next-generation devices require lower on-resistance.

[0006] Therefore, there is a need for structures and methods that provide reduced on-resistance and improved short-circuit capability in SiC devices, such as SiC MOSFETs. It would be beneficial if such structures and methods were cost-effective and easily manufacturable. [Brief explanation of the drawings]

[0007] [Figure 1] 1 illustrates a partial cross-sectional view of a semiconductor device according to the present disclosure. [Figure 2] 1 illustrates a dopant profile in an example junction field effect transistor (JFET) channel region according to the present specification. [Figure 3A] 1 shows a partial 2D plot of the PN junction profile of the doped base region. [Figure 3B] 1 shows a partial two-dimensional plot of a PN junction profile of a doped base region according to the present disclosure. [Figure 4A] 2 shows an enlarged cross-sectional view of a first JFET portion of the first JFET device designated by reference numeral 20A in FIG. 1; [Figure 4B] 2 shows an enlarged cross-sectional view of a second JFET portion of the second JFET device designated by reference numeral 20B in FIG. 1; [Figure 5] 10 graphically illustrates data for specific on-resistance (in milliohms*cm2) versus short circuit withstand capability (in microseconds) for semiconductor devices, including semiconductor devices according to the present disclosure. [Figure 6]1 illustrates a partial top view of a layout of a semiconductor device according to the present disclosure. [Figure 7] 7A-7D show partial cross-sectional views of the semiconductor device of FIG. 6 at various stages of fabrication in accordance with the present disclosure. [Figure 8] 7A-7D show partial cross-sectional views of the semiconductor device of FIG. 6 at various stages of fabrication in accordance with the present disclosure. [Figure 9] 7A-7D show partial cross-sectional views of the semiconductor device of FIG. 6 at various stages of fabrication in accordance with the present disclosure. [Figure 10] 7A-7D show partial cross-sectional views of the semiconductor device of FIG. 6 at various stages of fabrication in accordance with the present disclosure. [Figure 11] 7A-7D show partial cross-sectional views of the semiconductor device of FIG. 6 at various stages of fabrication in accordance with the present disclosure. [Figure 12] 7A-7D show partial cross-sectional views of the semiconductor device of FIG. 6 at various stages of fabrication in accordance with the present disclosure. [Figure 13] 7A-7D show partial cross-sectional views of the semiconductor device of FIG. 6 at various stages of fabrication in accordance with the present disclosure. [Figure 14] 7A-7D show partial cross-sectional views of the semiconductor device of FIG. 6 at various stages of fabrication in accordance with the present disclosure. [Figure 15] 7A-7D show partial cross-sectional views of the semiconductor device of FIG. 6 at various stages of fabrication in accordance with the present disclosure.

[0008] The following description provides various examples of semiconductor devices and methods for fabricating semiconductor devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the particular examples disclosed. In the following description, the terms "example" and "for example" are non-limiting.

[0009] For simplicity and clarity of illustration, components in the figures are not necessarily drawn to scale, the same reference numerals in different figures refer to the same components, and further, descriptions and details of well-known processes and components have been omitted for simplicity of illustration.

[0010] For clarity of the drawings, certain regions of the device structures, such as doped or dielectric regions, may be shown as having generally straight edges and precisely angled corners, however, those skilled in the art will understand that due to the diffusion and activation of dopants or layer formation, the edges of such regions may not be generally straight and the corners may not be precisely angled.

[0011] Although semiconductor devices are described herein as having particular N-type conductivity regions and particular P-type conductivity regions, those skilled in the art will understand that the conductivity types may be reversed and are possible in accordance with this specification, taking into account any necessary polarity reversal of voltages, reversal of transistor types and / or current direction, etc.

[0012] Furthermore, the terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0013] As used herein, a "current-carrying electrode" means an element of a device that allows current to flow through the device, e.g., the source or drain of a MOS transistor, the emitter or collector of a bipolar transistor, or the cathode or anode of a diode, and a "control electrode" means an element of a device that controls current flow through the device, e.g., the gate of a MOS transistor or the base of a bipolar transistor.

[0014] The term "major surface" when used with respect to a semiconductor region, wafer, or substrate means a surface of the semiconductor region, wafer, or substrate that forms an interface with another material, e.g., a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. A major surface may have a topography that varies in the x, y, and z directions.

[0015] The terms "comprises," "comprising," "includes," "including," "has," "have," and / or "having," as used herein, are open-ended terms that specify the presence of stated features, numbers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof.

[0016] The term "or" means any one or more of the items in the list joined by "or." As an example, "x or y" means any element of the 3-element set {(x), (y), (x,y)}. As another example, "x, y, or z" means any element of the 7-element set {(x), (y), (z), (x,y), (x,z), (y,z), (x,y,z)}.

[0017] Terms such as "first," "second," and the like may be used herein to describe various members, elements, regions, layers, and / or sections, but these members, elements, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one member, element, region, layer, and / or section from another. Thus, for example, a first member, first element, first region, first layer, and / or first section described below could be referred to as a second member, second element, second region, second layer, and / or second section without departing from the teachings of the present disclosure.

[0018] Those skilled in the art will recognize that the terms "during," "while," and "when," as used herein with respect to circuit operation, are not precise terms meaning that an action occurs immediately based on an initiating action, but rather that there may be some small, reasonable delay, e.g., a propagation delay between responses initiated by the initiating action. Furthermore, the term "while" means that a particular action occurs within at least a portion of the duration of the initiating action.

[0019] The use of the words "about," "approximately," or "substantially" means that the value of an element is expected to be close to a stated value or location. However, as is well known in the art, there is usually a small variance that prevents the value or location from being exactly as stated.

[0020] Unless otherwise specified, as used herein, the terms "over" or "on" include an orientation, arrangement, or relationship in which the specified elements may be in direct or indirect physical contact.

[0021] Unless otherwise specified, as used herein, the term "overlapping" includes an orientation, arrangement, or relationship in which the specified elements are at least partially or completely coincident or aligned in the same or different planes.

[0022] It will be further understood that the examples shown and described below as suitable may have other elements not specifically disclosed herein and / or may be practiced in the absence of any element not specifically disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0023] Generally, examples of the present invention relate to semiconductor device structures, such as SiC semiconductor devices, and methods for fabricating such devices that have improved short-circuit capability and ruggedness. More specifically, structures are described that use a first controlled pinch resistor in a first JFET region on the drain side of a semiconductor device. In some examples, a second controlled pinch resistor is added as part of a second JFET region on the source side of the semiconductor device, providing multiple controlled pinch resistors. Methods are described that use self-alignment techniques that enable the fabrication of smaller cell pitches. In some examples, the structures and methods further include providing a retrograde P-type well region and one or more high-energy N-type ion implants to control the pinch resistance in the first JFET region on the drain side. The structures and methods provide, among other things, improved short-circuit capability and ruggedness with a smaller impact on on-resistance compared to conventional SiC semiconductor devices. This improved trade-off is beneficial in emerging applications such as automotive inverters. The controlled pinch resistor is configured to provide short-circuit current saturation as an alternative to other approaches that reduce channel density or increase channel length or series resistance.

[0024] In one example, a method for manufacturing a semiconductor device includes providing a body of semiconductor material comprising a substrate and a semiconductor region overlying the substrate and having a first conductivity type. The semiconductor region comprises a first side of the semiconductor body, and the substrate comprises a second side of the semiconductor material body opposite the first side. The method includes providing a first doped region in the semiconductor region having the first conductivity type. The first doped region provides a first JFET channel region for a first JFET device. The method includes providing a first mask over the first side, the first mask having a first opening over the first doped region. The method includes providing a second doped region in the first doped region having a second conductivity type opposite the first conductivity type. The second doped region provides a body region for a MOSFET device, a gate region for the first JFET device, and a first JFET gate for the second JFET device. The method includes providing a first spacer structure in the first opening to define a second opening smaller than the first opening. The method includes providing a third doped region having a first conductivity type within the second doped region aligned with the second opening. The third doped region provides a second JFET channel region for the second JFET device, a first JFET source for the first JFET device, and a JFET drain for the second JFET device. The method includes providing a second spacer structure adjacent to the first spacer structure within the second opening to define a third opening smaller than the second opening. The method includes providing a fourth doped region having a second conductivity type within the third doped region aligned with the third opening. The fourth doped region provides a second JFET gate for the second JFET device. The method includes providing a fifth doped region having the first conductivity type adjacent to the fourth doped region. The fifth doped region provides a source for the MOSFET device and a second JFET source for the second JFET device. The method includes providing a sixth doped region having the second conductivity type extending through a portion of the fifth doped region and coupled to the second doped region.The sixth doped region provides a body contact for the MOSFET device and a gate contact to the first JFET gate for the second JFET device.

[0025] In one example, a method for manufacturing a semiconductor device includes providing a semiconductor substrate having a semiconductor region of a first conductivity type, a first side, and a second side opposite the first side, the semiconductor region having a first dopant concentration. The semiconductor substrate provides a drain for a MOSFET device and a first JFET drain for a first JFET device. At least the semiconductor region comprises silicon carbide (SiC). The method includes providing a first doped region on the first side extending into the semiconductor region and having the first conductivity type and a second dopant concentration higher than the first dopant concentration. The first doped region provides a first JFET channel region of the first JFET device. The method includes providing a second doped region in the first doped region extending from the first side into the first doped region and having a second conductivity type opposite the first conductivity type. The second doped region provides a body region for the MOSFET device and a gate region for the first JFET device, the second doped region comprising a first portion and a second portion, the first portion interposed between the first portion and the second portion, the second portion having a higher peak dopant concentration than the first portion. The method includes providing a third doped region within the second doped region self-aligned to the second doped region and having the first conductivity type, the third doped region providing a first JFET source for the first JFET device.

[0026] In one example, a semiconductor device includes a semiconductor substrate having a semiconductor region of a first conductivity type, a first side, and a second side opposite the first side. The semiconductor region has a first dopant concentration. The semiconductor substrate provides a drain for a MOSFET device and a first JFET drain for a first JFET device. At least the semiconductor region includes silicon carbide (SiC). A first doped region is adjacent to the first side and extends into the semiconductor region. The first doped region has the first conductivity type and a second dopant concentration higher than the first dopant concentration. The first doped region provides a first JFET channel region for the first JFET device. A second doped region is within the first doped region and extends from the first side into the first doped region. The second doped region has a second conductivity type opposite the first conductivity type. The second doped region provides a body region for the MOSFET device and a gate region for the first JFET device. The second doped region comprises a first portion and a second portion, the first portion being interposed between the first portion and the second portion, and the second portion having a higher peak dopant concentration than the first portion. A third doped region having the first conductivity type is within the second doped region and is self-aligned to the second doped region. The third doped region provides a first JFET source for the first JFET device.

[0027] This disclosure also includes other examples, which may be found in the drawings, claims, or description of this disclosure.

[0028] 1 illustrates a partial cross-sectional view of a semiconductor device 10 having improved short circuit capability and ruggedness in accordance with the present disclosure. In this example, the semiconductor device 10 comprises a SiC MOSFET device and includes a first JFET device 110 (including a first JFET region 20A) on the drain side of the SiC MOSFET. In some examples, the semiconductor device 10 further includes a second JFET device 120 (including a second JFET region 20B) on the source side of the SiC MOSFET. In accordance with the present disclosure, the pinch resistance of the first JFET region 20A, or the pinch resistances of both the first JFET region 20A and the second JFET region 20B, can be controlled to improve the short circuit capability and ruggedness of the semiconductor device 10.

[0029] In this example, semiconductor device 10 comprises a body of semiconductor material 11, which may also be referred to as a region of semiconductor material or a semiconductor workpiece. In some examples, body of semiconductor material 11 comprises a semiconductor substrate 12 and a semiconductor region 14 on or within substrate 12. Semiconductor substrate 12 may also be referred to as a substrate or starting substrate. In some examples, substrate 12 comprises SiC and has N-type conductivity. In some examples, semiconductor region 14 comprises an N-type conductivity SiC epitaxial layer formed on substrate 12.

[0030] In the example where semiconductor device 10 comprises a 1200 volt (V) SiC MOSFET, substrate 12 has a thickness of approximately 5.0×10 18 atoms / cm 3 In the 1200V example, semiconductor region 14 may have a thickness in the range of about 8 microns to about 12 microns and a dopant concentration of about 7.0×10 15 atoms / cm 3 ~Approx. 1.5×10 16 atoms / cm 3It is understood that the thickness and dopant concentration (including the dopant profile) of semiconductor region 14 may be adjusted according to breakdown voltage or other device requirements. In some examples, the upper side of semiconductor region 14 provides or defines an upper side 11A of body of semiconductor material 11, and the lower side of substrate 12 provides or defines a lower side 11B of body of semiconductor material 11. Lower side 11B is opposite upper side 11A. In this example, substrate 12 provides a drain for the SiC MOSFET and a first drain region for first JFET device 110.

[0031] According to the present specification, the semiconductor device 10 includes a doped region 141 in the semiconductor region 14 adjacent the top side 11A. The doped region 141 extends inward from the top side 11A into the semiconductor region 14. In some examples, the doped region 141 has a depth from about 1 micron to about 2 microns from the top side 11A. In this example, the doped region 141 has N-type conductivity and provides a first JFET channel region 141A for the first JFET device 110. According to the present specification, the doped region 141 has a dopant concentration and dopant profile configurable to control the pinch resistance of the first JFET device 110, thereby protecting the semiconductor device 10 during a short circuit event.

[0032] 2 shows an example dopant profile for doped region 141 suitable for a 1200V device. In some examples, doped region 141 has a dopant concentration of about 4.0×10 16 atoms / cm 3 ~Approx. 7.0×10 16 atoms / cm 3In some examples, the doped region 141 is provided using multiple doping processes, such as multiple ion implantations using nitrogen as an N-type dopant source. In some examples, the multiple ion implantations include at least a first ion implantation dose at a first ion implantation energy in a range of about 30 keV to about 320 keV and at least a second ion implantation dose at a second ion implantation energy in a range of about 460 keV to about 900 keV. In some examples, the multiple ion implantation doses are about 4.0×10 12 atoms / cm 2 ~Approx. 6.5×10 12 atoms / cm 2 provides a cumulative ion implantation dose of

[0033] 2, the multiple ion implantation doses may include more than five ion implantation doses of nitrogen into semiconductor region 14 to provide doped region 14. In one example, nine ion implantation doses may be about 1.0×10 with ion implantation energies in the range of about 30 keV to about 900 keV. 11 atoms / cm 2 ~about 2×10 12 atoms / cm 2 In some examples, the ion implantation energy increases as the ion implantation dose increases. With this multiple ion implantation of nitrogen, the highest N-type dopant concentration is distal to or spaced apart from the upper side 11A of the body 11 of semiconductor material, as shown in FIG. 2. In some examples, the series of ion implantations may be in a stepwise increasing order, where the ion implantation dose and ion implantation energy increase with each subsequent step. In other examples, any order may be used. In some examples, the multiple ion implantations are performed in a stepwise increasing order, where the ion implantation dose and ion implantation energy increase with each subsequent step. 12 atoms / cm 2 Doped region 141 is an example of a first doped region. In another example, phosphorus may be used as an N-type dopant, for example, with modifications to the ion implantation energy.

[0034] The semiconductor device 10 includes one or more doped regions 31 of P-type conductivity within the doped region 141. In some examples, the doped region 31 is a single interconnected doped region, such as multiple connected stripes. In other examples, the doped region 31 may be multiple separate doped regions, such as separate cell regions. In some examples, the doped region 31 extends within the doped region 141 to a depth within a range of about 0.5 microns to about 1.0 microns. The doped region 31 provides a body or base region for the SiC MOSFET, a gate region for the first JFET device 110, and a first JFET gate for the second JFET device 120.

[0035] According to the present specification, the doped region 31 comprises a plurality of vertically oriented portions or sections. In some examples, the doped region 31 comprises a first portion 31A and a second portion 31B, where the first portion 31A is interposed between the upper side 11A and the second portion 31B of the body 11 of semiconductor material. That is, the first portion 31A is proximate to the upper side 11A, and the second portion 31B is distal or spaced apart from the upper side 11A. According to the present specification, the second portion 31B comprises a retrograde portion having a higher peak dopant concentration than the first region 31A. In some examples, the second portion 31B, together with the doped region 141, is configured to control the JFET pinch of the first JFET device 110 to suppress short circuit current.

[0036] In some examples, the first portion 31A and the second portion 31B are formed using ion implantation. In some examples, the first portion 31A is formed first, followed by the second portion 31B. In one example, the first portion 31A is formed using about 2.0×10 13 atoms / cm 2 ~Approx. 4.0×10 13 atoms / cm 2 and an ion implantation energy of about 150 keV. In one example, second portion 31B is formed using aluminum dopant at an ion implantation dose of about 1.0×10 14 atoms / cm2 ~Approx. 6.0×10 14 atoms / cm 2 The second portion 31B is formed using aluminum dopants with an ion implantation dose of 0.1 V and an ion implantation energy of greater than about 400 keV. As described later, in some examples, the second portion 31B can be self-aligned to the first portion 31A using a spacer that provides the implanted dopant in the second region 31B that is initially laterally interposed relative to the first portion 31B. Due to the significant lateral spread of the implanted dopant, the higher concentration of the second portion 31B extends laterally into the doped region 141 that includes the first JFET channel region 141A, providing a more uniform PN junction profile and a narrower JFET channel distal to the top side 11A. A more uniform PN junction provides, among other things, better pinch-off of the JFET region 141, which leads to reduced current flow during a short-circuit event and reduced local self-heating effects. Conventional devices have been observed to have local self-heating effects in this portion of the device. As the temperature increases, the resistance of the JFET channel increases in a self-amplifying manner. In fact, the second region 31B has been found to reduce this effect seen in conventional devices.

[0037] Examples of differences in PN junction profiles between the base region and doped region 31 of a conventional device are shown in FIGS. 3A and 3B. More specifically, FIG. 3A shows a partial two-dimensional plot of a PN junction profile 310A of a conventional base region without second portion 31B. FIG. 3B shows a partial two-dimensional plot of a PN junction profile 310B including first portion 31A and second portion 31B according to the present disclosure. Indeed, it has been found that the PN junction profile 310A of the conventional device has an irregular profile 311, resulting in the undesired localized self-heating described above. In contrast, the PN junction profile 310 including second portion 31B has a more uniform profile, resulting in better JFET pinch and reduced localized self-heating during a short-circuit event, thereby improving performance and ruggedness.

[0038] Semiconductor device 10 further includes doped region 37 having N-type conductivity within doped region 31 and doped region 34 having P-type conductivity within doped region 37. In some examples described in more detail below, doped region 37 may be self-aligned to doped region 31, and doped region 34 may be self-aligned to doped region 37. This, among other things, provides semiconductor device 10 with a smaller cell size. Doped region 37 provides a JFET channel region 37A for second JFET device 120, a first JFET source 37B for first JFET device 110, and a JFET drain 37B for second JFET device 120. JFET channel region 37A may also be referred to as a second JFET channel region to distinguish it from first JFET channel region 141A. Doped region 34 provides a second JFET gate for second JFET device 120.

[0039] In some examples, the doped region 37 has a dopant concentration of about 5.0×10 in the JFET channel region 37A. 18 atoms / cm 3 ~Approx. 6.0×10 18 atoms / cm 3 In some examples, portion 37B of the doped region may have a higher dopant concentration than JFET channel region 37A using a separate doping process. In some examples, doped region 34 has a peak dopant concentration in the range of about 1.0×10 19 atoms / cm 3 ~Approx. 2.0×10 19 atoms / cm 3 The doped region 37 and the doped region 34 may be formed using ion implantation techniques. In some examples, portions 37A and 37B of the doped region 37 may be provided using multiple ion implantation doses.

[0040] Semiconductor device 10 further includes doped region 33 having N-type conductivity within doped region 37 and doped region 36 having P-type conductivity within doped region 37. In some examples, as described in more detail below, doped region 33 may be self-aligned to doped region 34. Doped region 33 provides a source region for the SiC MOSFET device and a JFET source region for second JFET device 120. Doped region 33 may also be referred to as a second JFET source region to distinguish it from JFET source region 37B for first JFET device 110. Doped region 36 extends through a portion of doped region 33 and a portion of doped region 37 and is coupled to doped region 31. Doped region 36 provides a body contact for the SiC MOSFET device and a gate contact to the first JFET gate for second JFET device 120.

[0041] Semiconductor device 10 further includes gate dielectric 26 on top side 11A of body 11 of semiconductor material, extending laterally between adjacent doped regions 37 and doped region portions 31, with portions 141A interposed between adjacent doped region portions 31. In some examples, gate dielectric 26 may include oxide and may have a thickness in the range of about 250 angstroms to about 600 angstroms. Conductor 44A is provided on gate dielectric 26, and conductor 44B is provided on a portion of top side 11A and is coupled to doped region 34, doped region 33, and doped region 36. In this configuration, doped region 34 is electrically shorted to doped region 33. In some examples, conductor 44A may include polysilicon or other conductive material, and conductor 44B may include nickel, nickel silicide, titanium, or other conductive material known to those skilled in the art. In some examples, conductor 46 is provided on bottom side 11B of body 11 of semiconductor material and is coupled to substrate 12. In some examples, conductor 46 may comprise multiple metal layers, such as nickel-titanium-nickel-silver, chromium-nickel-gold, or other conductive materials known to those skilled in the art. Conductors 44A, 44B, and 46 may be formed using a deposition process, such as evaporation, sputtering, or other techniques known to those skilled in the art. In some examples, conductor 44A may be referred to as a gate control electrode, conductor 44B may be referred to as a current-carrying or source electrode, and conductor 46 may be referred to as a current-carrying or drain electrode. When an appropriate gate voltage is applied to conductor 44A, a channel region 29 that carries current through semiconductor device 10 is formed in doped region 31 adjacent topside 11A.

[0042] FIG. 4A illustrates an enlarged cross-sectional view of a first JFET portion 20A of a first JFET device 110 of semiconductor device 10. In accordance with this specification, first JFET device 110 may have a highly tunable structure and implementation. For example, first JFET portion 20A of FIG. 4A may have an N-type dopant concentration 110ND (N D ), JFET channel width 110W (W JFET ), and the JFET channel length 110L (L). The parameters N D , WJFET By selecting the values ​​of , and L, it is possible to control the pinch-off and saturation levels of the short circuit current.

[0043] More specifically, the first JFET device 110 provides a structural means for tailoring the operating characteristics of the semiconductor device 10 to achieve a desired result. For example, the doping of the first JFET channel region 141A to N D may be selected to provide a desired level of series resistance when semiconductor device 10 is in the on state, but pinch off at specified high currents, such as during a short circuit event.

[0044] To provide such adjustment, the N-type dopant concentration is 110N.D. D ), JFET channel width 110W (W JFET ), and the JFET channel length 110L(L) may be selected and configured to cause pinch-off of the first JFET device 110 at a specified (e.g., short-circuit) current. In some examples, for a given value of the JFET channel length 110L(L), N D * W JFET It is possible to control a parameter that is precise, which can be referred to as the JFET channel dose for the first JFET channel region 141A. D * W JFET / L, the N-type dopant concentration is 110ND(N D ), JFET channel width 110W (W JFET ), or the JFET channel length 110L(L). D * W JFET N-type dopant concentration 110ND(N D ) does not need to be constant.

[0045] In some examples, the N-type dopant concentration is 110N.D.D ), JFET channel width 110W (W JFET ), and the value for JFET channel length 110L(L) is approximately L = 1 micron JFET channel length, N D =5.0×10 16 atoms / cm 3 , and W JFET = 0.7 microns. That is, the JFET channel length 110L(L) can be kept relatively short, for example, on the order of 0.5 microns to about 1.5 microns. In summary, desired operating characteristics in short circuit performance can be obtained using the ratio of channel dose to the selected channel length of the first JFET device 110.

[0046] According to this specification, the drain voltage of the JFET (V D ) increases, the saturation voltage (V DSAT ) until the drain current (I D ) also increases. V DSAT So, the JFET current I D The saturation value I DSAT The saturation value I DSAT By reaching and maintaining this, short circuit protection is achieved and time is provided for fault protection mechanisms to be implemented. The advantage of having the first JFET region 20A in series with the SiC MOSFET channel is that the first JFET region 20A has a low on-resistance that adds up to the total on-resistance of the SiC MOSFET, but has a pinch-off current that limits the maximum short circuit of the SiC MOSFET. This is an improvement over conventional SiC MOSFET devices.

[0047] 4B shows an enlarged cross-sectional view of the second JFET portion 20A of the first JFET device 110 of the semiconductor device 10. Similar to the first JFET device 110, the second JFET device 120 may have a highly tunable structure and implementation. For example, the second JFET portion 20B of FIG. 4B may have an N-type dopant concentration 120ND (N D ), JFET channel width 120W (W JFET ) and the JFET channel length 120L (L). The parameters ND , W JFET By selecting the values ​​of , and L, it is possible to further control the pinch-off and saturation levels of the short circuit current with the first JFET device 110, as previously described.

[0048] FIG. 5 shows the characteristic on-resistance (in milliohms) for semiconductor devices, including semiconductor devices according to the present disclosure. * cm 2 5 graphically illustrates data of short circuit withstand time (in microseconds) versus short circuit withstand time. More specifically, data sets 151 and 152 correspond to data for conventional SiC MOSFET devices that do not have a first JFET device 110 as described herein. More specifically, data set 152 corresponds to a semiconductor device conforming to the PN junction profile of FIG. 3A . Data set 153 corresponds to data for a semiconductor device that includes only a first JFET device 110 having the PN junction profile of FIG. 3B . That is, data set 153 is an example of a semiconductor device 10 that includes a first JFET device 110 according to the present disclosure, but does not include a second JFET device 120. As shown in FIG. 5 , the semiconductor device 10 has a longer short circuit withstand time and a lower specific on-resistance compared to conventional devices.

[0049] 6-15, example device layouts and fabrication methods that support smaller cell pitches (e.g., cell pitches in the range of about 4 microns or less) are described for semiconductor devices according to this specification. An example of such a semiconductor device may be semiconductor device 10, including variations thereof.

[0050] FIG. 6 illustrates a partial top view of a layout 100 of a semiconductor device, such as semiconductor device 10, in accordance with the present disclosure. In some examples, layout 100 includes a stripe cell configuration in which doped region 31 is provided as multiple generally parallel stripe regions or portions, which may be coupled to one another in another portion of semiconductor device 10 (e.g., a portion near the periphery of semiconductor device 10). As shown in FIG. 6, layout 100 includes doped region 31 (including first portion 31A) within doped region 141 (including first JFET channel region 141A). In addition, doped region 37 (including source region 37B of first JFET device 110) is provided within doped region 31, and doped region 34 is provided within doped region 37 in a nested stripe configuration. In addition, doped region 33 is provided within doped region 37 in a stripe configuration, with multiple individual doped regions 36 in a spaced-apart configuration within doped region 33 and doped region 37.

[0051] FIG. 7 illustrates a partial cross-sectional view of a semiconductor device, such as semiconductor device 10, at an early stage of fabrication in accordance with the present disclosure, as viewed along either reference line 130-130′ or reference line 140-140′ in FIG. 6 . The described methods relate to MOSFET devices, such as SiC MOSFET devices, including high-voltage SiC MOSFET devices. In this example, the methods are described for fabricating a 1200 V SiC MOSFET device. In some examples, a body of semiconductor material 11 is provided, comprising a substrate 12 and a semiconductor region 14. The body of semiconductor material 11 comprises an upper side 11A and a lower side 11B opposite the upper side 11A. The upper side 11A may be an example of a first side, and the lower side 11B may be an example of a second side.

[0052] In this example, the substrate 12 and the semiconductor region 14 may have a first conductivity type, such as N-type conductivity. In some examples, the substrate 12 may have a conductivity type of about 5.0×10 18 atoms / cm 3 and the semiconductor region 14 may have a thickness in the range of about 8 microns to about 12 microns and a dopant concentration of about 7.0×10 15 atoms / cm 3~Approx. 1.5×10 16 atoms / cm 3 The dopant concentration may be in the range of .gtoreq..times ...

[0053] In some examples, doped region 141 disposed within semiconductor region 14 may have a first conductivity type, or N-type conductivity. Doped region 141 extends inwardly from top side 11A into semiconductor region 14. In some examples, doped region 141 has a depth of about 1 micron to about 2 microns from top side 11A. According to this specification, doped region 141 provides a first JFET channel region 141A for first JFET device 110 shown in FIG. 1 . In some examples, doped region 141 has a dopant concentration of about 4.0×10 16 atoms / cm 3 ~Approx. 7.0×10 16 atoms / cm 3 1 and 2, doped region 141 may be provided using multiple doping steps, such as multiple ion implantations using nitrogen as an N-type dopant source. In addition, the doping of first JFET channel region 141A may be D may be selected to provide a desired level of series resistance when semiconductor device 10 is in the on state, but pinch off at a specified high current, such as during a short circuit event. Doped region 141 may be an example of a first doped region.

[0054] FIG. 8 shows a partial cross-sectional view of semiconductor device 10 at a later stage of fabrication, as viewed along either reference line 130-130′ or reference line 140-140′ in FIG. 6 . In this example, a first mask 51 is provided on top side 11A. First mask 51 includes a first opening 51A over doped region 141. In some examples, first mask 51 includes a dielectric material such as oxide. Opening 51A may be formed using photolithography and etching techniques. In some examples, a dielectric structure is first provided on top side 11A, followed by first mask 51. In some examples, the dielectric structure includes an oxide-polysilicon-oxide structure. Opening 51A may then be formed through first mask 51A and the dielectric structure. After opening 51A is formed, first portion 31A of doped region 31 may be provided in doped region 141. The first portion 31A has a second conductivity type opposite to the above conductivity type, or P-type conductivity. The first portion 31A has a conductivity of about 2.0×10 13 atoms / cm 2 ~Approx. 4.5×10 13 atoms / cm 2 The ion implantation energy may be about 100 keV to 200 keV and the ion implantation dose may be about 100 keV to 200 keV using aluminum dopants.

[0055] FIG. 9 illustrates a partial cross-sectional view of semiconductor device 10 at a later stage in fabrication, as viewed along either reference line 130-130′ or reference line 140-140′ in FIG. 6 . In some examples, a first spacer structure 52 is provided in opening 51A, which defines a second opening 52A over first portion 31A. In some examples, a dielectric structure is formed over first mask 51 and upper side 11A. An anisotropic etching technique can be used to remove portions of the dielectric structure but leave first spacer structure 52 along the sidewalls of first mask 51. In some examples, first spacer structure 52 can include oxide or a combination of oxide and polysilicon.

[0056] After the first spacer structures 52 are formed, the second portion 31B of the doped region 31 may be provided within the first portion 31A and within the doped region 141 using the first spacer structures 52, making the second portion 31B self-aligned to the first portion 31A. That is, in some examples, the second portion 31B is self-aligned to the first portion 31A. In some examples, the second portion 31B is about 1.0×10 14 atoms / cm 2 ~Approx. 6.0×10 14 atoms / cm 2 and an ion implantation energy greater than about 400 keV using aluminum dopants.

[0057] In some examples, the first portion 31A and the second portion 31B of the doped region 31 are activated at high temperatures. During dopant implantation at energies around or above about 400 keV, significant lateral spreading of the implanted ions causes the higher concentration of the second portion 31B to extend laterally within the doped region 141, including the first JFET channel region 141A, providing a more uniform PN junction profile and a narrower JFET channel distance to the topside 11A. A high dose of high-energy implanted ions provides a steeper PN junction, which, among other things, provides a well-controlled, narrow JFET channel that leads to a more efficient JFET pinch, resulting in reduced current flow during a short-circuit event and reduced local self-heating effects. As previously described, the doped region 31 provides the body region for the SiC MOSFET, the gate region for the first JFET device 110, and the first JFET gate for the second JFET device 120. The doped region 31 may be an example of a second doped region.

[0058] FIG. 10 illustrates a partial cross-sectional view of semiconductor device 10 at a later stage in fabrication, as viewed along either reference line 130-130' or reference line 140-140' in FIG. 6. In some examples, doped region 37 is provided within doped region 31 using first spacer structures 52 to self-align doped region 37 to first portion 31A of doped region 31. In this example, doped region 37 has a first conductivity type, or N-type conductivity. As previously described, doped region 37 provides a JFET channel region 37A for second JFET device 120, a first JFET source 37B for first JFET device 110, and a JFET drain 37B for second JFET device 120. In some examples, doped region 37 has a dopant concentration of about 3.0×10 in JFET channel region 37A. 18 atoms / cm 3 ~Approx. 9.0×10 18 atoms / cm 3 and may be formed by a first ion implantation step. In some examples, portion 37B of doped region may have a higher dopant concentration than JFET channel region 37A and may be formed by a separate ion implantation step. As previously mentioned, doped region 37 is configured to control the pinch-off and saturation levels of short-circuit current for second JFET device 120. Doped region 37 may be an example of a third doped region.

[0059] FIG. 11 illustrates a partial cross-sectional view of semiconductor device 10 at a later stage in fabrication, as viewed along either reference line 130-130′ or reference line 140-140′ in FIG. 6 . In some examples, a second spacer structure 53 is provided in second opening 52A, which defines a third opening 53A over doped region 37. In some examples, a dielectric structure is formed over first mask 51, first spacer structure 52, and upper side 11A. An anisotropic etching technique can be used to remove portions of the dielectric structure but leave second spacer structure 53 along the sidewalls of first spacer structure 52. In some examples, second spacer structure 53 can include oxide or a combination of oxide and polysilicon.

[0060] After the second spacer structures 53 are formed, the doped region 34 having the second conductivity type or P-type conductivity is provided using the second spacer structures 53, self-aligning the doped region 34 to the doped region 37. That is, in some examples, the doped region 34 is self-aligned to the doped region 37. In some examples, the doped region 34 is about 1.0×10 19 atoms / cm 3 ~Approx. 2.0×10 19 atoms / cm 3 The doped region 34 has a peak dopant concentration in the range of 0.1 to 1.0 V. Aluminum ion implantation may be used to form the doped region 34. As previously mentioned, the doped region 34 provides a second JFET gate for the second JFET device 120. The doped region 34 may be an example of a fourth doped region.

[0061] FIG. 12 illustrates a partial cross-sectional view of semiconductor device 10 at a later stage in fabrication, as viewed, for example, along reference line 130-130′ in FIG. 6 . In some examples, a third spacer structure 54 is provided in third opening 53A, which defines a fourth opening 54A over doped region 34. In some examples, a dielectric structure is formed over first mask 51, first spacer structure 52, second spacer structure 53, and upper side 11A. An anisotropic etching technique can be used to remove portions of the dielectric layer but leave third spacer structure 54 along the sidewalls of second spacer structure 53. In some examples, third spacer structure 54 can include oxide or a combination of oxide and polysilicon.

[0062] After the third spacers 54 are formed, the doped region 33 having the first conductivity or N-type conductivity is provided using the third spacer structures 54, making the doped region 33 self-aligned to the doped region 34. That is, in some examples, the doped region 33 is self-aligned to the doped region 34. In some examples, the doped region 33 comprises a continuous stripe region within the doped region 37, as opposed to multiple doped regions 33 within the doped region 37. The doped region 33 has a doping density of approximately 3.0×10 19atoms / cm 3 The doped region 33 may have a peak dopant concentration greater than 1000 Å and may be formed using ion implantation techniques. In another example, the mask 51, the first spacer structure 52, and the second spacer structure 53 may be removed, and a separate hard mask may be provided and patterned with openings 54D to provide the doped region 33. As previously mentioned, the doped region 33 provides a source region for the SiC MOSFET device and a JFET source region for the second JFET device 120. The doped region 33 may be an example of a fifth doped region.

[0063] 13 illustrates a partial cross-sectional view of semiconductor device 10 at a later stage in fabrication, as viewed along reference line 140-140′ in FIG. 6 . In some examples, mask 51, first spacer structure 52, second spacer structure 53, and third spacer structure 54 are removed. A second mask 56 may then be formed over top side 11A, and fifth openings 56A may be provided laterally spaced apart over doped region 33. Doped region 36 may then be provided in a portion of doped region 33 through fifth opening 56A. In this example, doped region 36 has a second conductivity type, or P-type conductivity. In some examples, doped region 36 has a dopant concentration of about 5.0×10 19 atoms / cm 3 The doped region 36 has a peak dopant concentration greater than 0.05 and can be formed using ion implantation techniques. Doped region 36 extends through a portion of doped region 33 and a portion of doped region 37 and is coupled to doped region 31. As previously mentioned, doped region 36 provides a body contact for the SiC MOSFET device and a gate contact to the first JFET gate (doped region 31) for second JFET device 120. Doped region 36 may be an example of a sixth doped region.

[0064] FIG. 14 shows a partial cross-sectional view of semiconductor device 10 during further processing, with the cross-section taken along reference line 130-130′ in FIG. 6 . FIG. 15 shows a partial cross-sectional view of semiconductor device 10 after further processing, with the cross-section taken along reference line 140-140′ in FIG. 6 . In some examples, second mask 56 may be removed and gate dielectric 26 may be provided over a portion of topside 11A. In a subsequent step, conductor 44A may be provided over gate dielectric 26, and conductor 44B may be provided coupled to doped region 33, doped region 34, and doped region 36. Conductor 44B is configured to electrically short doped region 33, doped region 34, and doped region 36 together. This provides a second gate region (doped region 34) for second JFET device 120 in a shorted gate to source configuration. In some examples, conductor 44A may include polysilicon or other conductive material known to those skilled in the art, and 44B may include nickel, nickel silicide, titanium, or other conductive material known to those skilled in the art.

[0065] In some examples, the body of semiconductor material 11 may be thinned from the bottom side 11B to provide the body of semiconductor material 11 with a target thickness. The conductor 46 may then be provided on the bottom side 11B. In some examples, the conductor 46 is provided on the bottom side 11B of the body of semiconductor material 11 and bonded to the substrate 12. In some examples, the conductor 46 may comprise multiple metal layers, such as nickel-titanium-nickel-silver, chromium-nickel-gold, or other conductive materials known to those skilled in the art. The conductors 44A, 44B, and 46 may be formed using a deposition process, such as evaporation, sputtering, or other techniques known to those skilled in the art.

[0066] In summary, methods and structures for semiconductor devices with improved short-circuit capability and durability have been described. More specifically, structures have been described that use a first controlled pinch resistor in a first JFET region on the drain side of the semiconductor device. In some examples, a second controlled pinch resistor is added as part of a second JFET region on the source side of the semiconductor device, providing multiple controlled pinch resistors. Methods have been described that use self-aligned techniques that enable the fabrication of smaller cell pitches. In some examples, the methods further include providing a retrograde P-type well region and one or more high-energy N-type ion implants to control the pinch resistance in the first JFET region on the drain side. The structures and methods provide, among other things, improved short-circuit capability with a smaller impact on on-resistance compared to conventional SiC semiconductor devices. This improved trade-off is beneficial in emerging applications such as automotive inverters. The controlled pinch resistor is configured to provide short-circuit current saturation as an alternative to other approaches that reduce channel density or increase channel length or series resistance.

[0067] It is understood that the different examples described herein can be combined with any of the other examples described herein to obtain different embodiments.

[0068] While the present subject matter has been described with reference to certain preferred embodiments, the foregoing drawings and description thereof illustrate only typical examples of the present subject matter and should not be considered as limiting its scope. It is apparent that many alternatives and modifications will be apparent to those skilled in the art. For example, the conductivity types of various regions can be reversed.

[0069] As the claims reflect below, inventive aspects may lie in fewer than all features of a single example disclosed above. For this reason, the claims expressed below are expressly incorporated into this specification, with each claim standing alone as a separate example of the present invention. Furthermore, some examples described herein may include some of the features of other examples, but not other features, and as will be understood by those skilled in the art, combinations of features from different examples are intended to be within the scope of the present invention and to form different examples.

Claims

1. A method for manufacturing a semiconductor device (10), comprising: Providing a body (11) of semiconductor material, said body (11) of semiconductor material comprising: A substrate (12) and a semiconductor region (14) having a first conductivity type overlying the substrate, the semiconductor region comprising a first side (11A) of the semiconductor body, and the substrate comprising a second side (11B) of the semiconductor body opposite the first side; providing a first doped region (141) having the first conductivity type within the semiconductor region, the first doped region providing a first JFET channel region (141A) for a first JFET device (110); providing a first mask (51) on the first side, the first mask having a first opening (51A) over the first doped region; providing a second doped region (31) in the first doped region having a second conductivity type opposite to the first conductivity type, the second doped region providing a body region for a MOSFET device, a gate region for the first JFET device, and a first JFET gate for a second JFET device (120); providing a first spacer structure (52) within the first opening to define a second opening (52A) smaller than the first opening; providing a third doped region (37) in the second doped region having the first conductivity type aligned with the second opening, the third doped region providing a second JFET channel region for the second JFET device, a first JFET source for the first JFET device, and a JFET drain for the second JFET device; providing a second spacer structure (53) adjacent to the first spacer structure in the second opening to define a third opening smaller than the second opening; providing a fourth doped region (34) of the second conductivity type within the third doped region aligned with the third opening, the fourth doped region providing a second JFET gate for the second JFET device; providing a fifth doped region (33) having the first conductivity type adjacent to the fourth doped region, the fifth doped region providing a source for the MOSFET device and a second JFET source for the second JFET device; providing a sixth doped region (36) having the second conductivity type extending through a portion of the fifth doped region and coupled to the second doped region, the sixth doped region providing a body contact for the MOSFET device and a gate contact to the first JFET gate for the second JFET device; A method comprising:

2. Providing the fifth doped region (33) providing a third spacer structure (54) adjacent to the second spacer structure in the third opening to define a fourth opening (54A) smaller than the third opening; and forming the fifth doped region aligned with the fourth opening; The method of claim 1 , comprising:

3. The method of claim 1 , wherein the MOSFET device comprises a silicon carbide (SiC) MOSFET device.

4. Providing the first doped region (141) a dopant concentration N configured to cause pinch-off of a short circuit current in the MOSFET device during a short circuit event; Ｄ 2. The method of claim 1, further comprising forming the first JFET channel region (141A) having a width W and a length L.

5. Providing the first doped region (141) A channel dose N for a value of L configured to cause the pinch-off at a specified short circuit current in the first JFET channel region (141A). Ｄ The method of claim 4, comprising providing W.

6. Providing the second doped region (31) performing a first ion implantation into a first portion (31A) of the second doped region at a first ion implantation energy; and performing a second ion implantation into a second portion (31B) of the second doped region at a second ion implantation energy greater than the first ion implantation energy; Including, the second portion is interposed between the first side of the body of semiconductor material and the first portion; and The method of claim 1 , wherein the first portion has a higher peak dopant concentration than the second portion.

7. performing the first ion implantation before providing the first spacer structure (52); 7. The method of claim 6, wherein performing the second ion implantation occurs after providing the first spacer structure.

8. the first ion implantation energy is about 150 keV; The first ion implantation is performed at a concentration of about 1.0×10 １３ atoms / cm ２ ~Approx. 6.0×10 １３ atoms / cm ２ Including an ion implantation dose of the second ion implantation energy is greater than about 400 keV; The second ion implantation is performed at a concentration of about 1.0×10 １４ atoms / cm ２ ~Approx. 6.0×10 １４ atoms / cm ２ 7. The method of claim 6, comprising an ion implantation dose of

9. Providing the first doped region (141) 10. The method of claim 1, comprising implanting dopants of the first conductivity type using a plurality of ion implantation doses including at least a first ion implantation dose at a first ion implantation energy in a range from about 30 keV to about 320 keV and at least a second ion implantation dose at a second ion implantation energy in a range from about 460 keV to about 900 keV.

10. Providing the first doped region (141) Approximately 4.0×10 １２ atoms / cm ２ ~Approx. 6.5×10 １２ atoms / cm ２ 10. The method of claim 9, comprising ion implanting the dopant comprising nitrogen at a cumulative ion implantation dose of

11. providing said body (11) of semiconductor material, providing said semiconductor region (14) comprising silicon carbide (SiC); providing a dopant concentration in the semiconductor region; and 2. The method of claim 1, wherein providing the first doped region comprises providing the first doped region having a peak dopant concentration greater than the dopant concentration of the semiconductor region.

12. 2. The method of claim 1, further comprising providing a conductor (44B) coupled to the sixth doped region (36), the fifth doped region (33), and the fourth doped region (34).

13. A method for manufacturing a semiconductor device (10), comprising: providing a semiconductor substrate (12) having a semiconductor region (14) of a first conductivity type, a first side (11A), and a second side (11B) opposite the first side, the semiconductor region having a first dopant concentration, the semiconductor substrate providing a drain for a MOSFET device and a first JFET drain for a first JFET device (110), at least the semiconductor region comprising silicon carbide (SiC); providing a first doped region (141) on the first side extending into the semiconductor region and having the first conductivity type and a second dopant concentration higher than the first dopant concentration, the first doped region providing a first JFET channel region (141A) for the first JFET device; providing a second doped region (31) within the first doped region extending from the first side into the first doped region and having a second conductivity type opposite to the first conductivity type; the second doped region provides a body region for the MOSFET device and a gate region for the first JFET device; the second doped region comprises a first portion (31A) and a second portion (31B); the first portion is interposed between the first side and the second portion; and the second portion having a higher peak dopant concentration than the first portion; and providing a third doped region (37) within the second doped region, the third doped region being self-aligned to the second doped region and having the first conductivity type, the third doped region providing a first JFET source for the first JFET device; A method comprising:

14. Providing the second doped region (31) a first ion implantation energy of less than about 150 keV and a １３ atoms / cm ２ ~Approx. 6.0×10 １３ atoms / cm ２ implanting the first portion (31A) of the second doped region with a first implant dose in the range of a second ion implantation energy greater than about 400 keV and a fluence of about 1.0×10 １４ atoms / cm ２ ~Approx. 6.0×10 １４ atoms / cm ２ implanting ions into the second portion (31B) of the second doped region with a second ion implantation dose in the range of 14. The method of claim 13, comprising:

15. Providing the first doped region (141) implanting dopants of the first conductivity type using a plurality of ion implantation doses, including at least one ion implantation dose at an ion implantation energy in a range of about 650 keV to about 900 keV; The multiple ion implantation doses are approximately 5.0×10 １２ atoms / cm ２ ~Approx. 6.0×10 １２ atoms / cm ２ 14. The method of claim 13, wherein the total ion implantation dose is in the range of:

16. Providing the first doped region (141) a doping concentration N configured to cause pinch-off of a short circuit current in the MOSFET device during a short circuit event; Ｄ 14. The method of claim 13, comprising forming the first JFET channel region (141A) having a width W and a length L.

17. the second doped region (31) provides a first JFET gate for a second JFET device (120); the third doped region (37) provides a second JFET channel region for the second JFET device and a second JFET drain for the second JFET device; The method further comprises: providing a fourth doped region (34) in the third doped region, the fourth doped region being self-aligned to the third doped region and having the second conductivity type, the fourth doped region providing a second JFET gate for the second JFET device; providing a fifth doped region (33) having the first conductivity type adjacent to the fourth doped region, the fifth doped region providing a source for the MOSFET device and a second JFET source for the second JFET device; providing a sixth doped region (36) having the second conductivity type extending through a portion of the fifth doped region and connected to the first portion of the second doped region, the sixth doped region providing a body contact for the MOSFET device, a gate contact to the gate region for the first JFET device, and a gate contact to the first JFET gate for the second JFET device; and providing a conductor (44B) electrically coupling together the sixth doped region, the fifth doped region, and the fourth doped region; 14. The method of claim 13, comprising:

18. A semiconductor device (10), comprising: a semiconductor substrate (12) having a semiconductor region (14) of a first conductivity type, a first side (11A), and a second side (11B) opposite the first side, the semiconductor region having a first dopant concentration, the semiconductor substrate providing a drain for a MOSFET device and a first JFET drain for a first JFET device (110), at least the semiconductor region comprising silicon carbide (SiC); a first doped region (141) extending into the semiconductor region and proximate the first side, the first doped region having the first conductivity type and a second dopant concentration higher than the first dopant concentration, the first doped region providing a first JFET channel region (141A) for the first JFET device; a second doped region (31) within the first doped region extending from the first side into the first doped region and having a second conductivity type opposite the first conductivity type; the second doped region provides a body region for the MOSFET device and a gate region for the first JFET device; the second doped region comprises a first portion (31A) and a second portion (31B); the first portion is interposed between the first side and the second portion; and a second doped region (31), the second portion having a higher peak dopant concentration than the first portion; and a third doped region (37) within the second doped region, self-aligned to the second doped region, the third doped region having the first conductivity type, the third doped region providing a first JFET source for the first JFET device; A semiconductor device (10) comprising:

19. The first JFET channel region (141) has a doping concentration N configured to cause pinch-off of the short circuit current of the MOSFET device during a short circuit event. Ｄ 19. The semiconductor device of claim 18, having a width W and a length L.

20. the second doped region (31) providing a first JFET gate for a second JFET device; The third doped region (37) provides a second JFET channel region for the second JFET device and a second JFET drain for the second JFET device. The semiconductor device further comprises: a fourth doped region (34) within the third doped region, self-aligned to the third doped region, the fourth doped region having the second conductivity type, the fourth doped region providing a second JFET gate for the second JFET device; a fifth doped region (33) having the first conductivity type adjacent to the fourth doped region, the fifth doped region providing a source for the MOSFET device and a second JFET source for the second JFET device; a sixth doped region (36) having the second conductivity type extending through a portion of the fifth doped region and coupled to the first portion of the second doped region, the sixth doped region (36) providing a body contact for the MOSFET device, a gate contact to the gate region for the first JFET device, and a gate contact to the first JFET gate for the second JFET device; and a conductor (44B) electrically coupling the sixth doped region, the fifth doped region, and the fourth doped region together; 20. The semiconductor device of claim 18, comprising:

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