Regulated mobile ionic synapses

Abstract

A method for fabricating a mobile ion modulated device includes depositing a dielectric layer on a substrate, positioning mobile ions within the dielectric layer, providing an electrode layer on the dielectric layer, and directing the mobile ions toward designated regions of the dielectric layer.

Description

[Technical Field]

[0001] The present disclosure relates generally to memories used in artificial intelligence (AI), and more specifically to artificial synapses that perform continuous weight updates in AI networks. [Background technology]

[0002] Synapses in the human brain function using neurotransmitters composed of mobile cations such as Na+, K+, Ca+, and H+. In fields such as artificial intelligence, the development of artificial synapses (e.g., "bio-inspired synapses") that are operationally based on real human synapses is a growing area of ​​research.

[0003] In neural networks, weights associated with neuronal connections are adjusted after a forward pass of data through the network. Weight updates help reconcile differences between actual and predicted results for multiple forward passes. For the purposes of neuromorphic computing, artificial synapses are used to perform weight updates in deep neural networks. Research exists into analog memory evaluation from digital memory development, such as phase change memory (PCM), resistive random access memory (RRAM), ferroelectric, floating gate, and electrochemical approaches for Li+-based structures. However, symmetric updates remain challenging. For example, in semiconductors relevant to AI, mobile ions in oxides or high-dielectric constant (High-K) materials are known to cause serious instability problems in MOS capacitors, and mobile ions can cause flat band shifts (DV) after certain stress (e.g., bias thermal stress (BTS)) tests. fb ) can be detected by Summary of the Invention

[0004] According to one embodiment, a computer-implemented method for fabricating a mobile ion modulated device includes depositing one or more dielectric layers on a substrate. Mobile ions are provided within the dielectric layers. An electrode layer is provided on the dielectric layers. The mobile ions are directed to designated regions of the dielectric layers. The placement of the mobile ions in designated regions of the dielectric layers allows for multiple levels of state for analog computing and analog synapses that may be used, for example, in neural networks. Faster and more efficient forms of AI may result.

[0005] In one embodiment that may be combined with the previous embodiment, the method includes forming a three-terminal device from the mobile ion-modulated device by patterning the electrode layer into one or more gates; and forming a source and a drain on the substrate. Such a three-terminal FET can be used to modulate mobile ions and allow symmetric updating. Symmetric diffusion that mimics biologically plausible synapses can be provided, which can be of benefit to AI, particularly in areas such as neural networks.

[0006] In one embodiment that can be combined with the previous embodiment, driving the mobile ions includes biasing the dielectric layer with a voltage, which can direct the mobile ions toward an alignment area, which overcomes instability problems in MOS capacitors.

[0007] In one embodiment that may be combined with the previous embodiment, the method includes driving the mobile ions to different positions within the dielectric layer to produce multiple states of the three-terminal device for analog computing, where different positions may represent different states of a more accurate neural network with improved speed of operation.

[0008] In one embodiment that may be combined with the previous embodiment, the method includes providing multiple gate stacks on the substrate including multiple superlattice high-k (HK) stacks and confining mobile ions in multiple layers, the multiple gate stacks providing a way to confine mobile ions for more precise control and positioning.

[0009] In one embodiment that may be combined with the previous embodiment, the method includes providing a plurality of gate stacks on the substrate including a superlattice material selected from the group consisting of HfSiO4, HfO2, HfSiO4, HfO2, HfSiO4, HfO2, or alternative HK layers such as HfSiO4. Alternatively, the Hf in the HK stacks can be replaced by Zr, Al, or Y. The superlattice structures with different band structures improve accommodation of mobile ions.

[0010] In one embodiment that may be combined with the previous embodiment, the method includes providing multiple gate stacks containing multiple bandgaps constructed from alternating dielectric materials, the multiple bandgaps of the various layers allowing for more precise tuning of mobile ions.

[0011] In one embodiment that may be combined with the previous embodiment, the method includes performing symmetric set and reset operations by driving an equal number of mobile ions within the dielectric layer in a first direction for a set operation and in a second direction opposite the first direction for a reset operation. Driving mobile ions into set and reset operations improves the accuracy and speed of the three-terminal structure, allowing its use as an analog synapse in a neural network.

[0012] In one embodiment that may be combined with the previous embodiment, driving the mobile ions includes heating the dielectric layer, which may improve the accuracy of application of a bias voltage or may alternatively be used without a voltage to position the mobile ions.

[0013] In one embodiment that may be combined with the previous embodiment, the driving of the mobile ions comprises heating the dielectric layer before or during the biasing of the electrode layer, wherein heating the dielectric layer in combination with an applied voltage bias facilitates more accurate and faster positioning of the mobile ions.

[0014] In one embodiment that may be combined with the previous embodiment, the method includes tuning conductance in adjacent channel layers by reapplying at least one of biasing or heating the dielectric layer, wherein tuning provides more precise positioning of mobile ions.

[0015] In one embodiment, a method for fabricating a mobile ion modulated device includes growing a thermal dielectric layer on a substrate. A buried gate is defined in the thermal dielectric layer by metallization and reactive ion etching. An additional thermal dielectric is added on the thermal dielectric layer, and chemical mechanical polishing (CMP) is performed. A high-k material is deposited on the thermal dielectric layer, and mobile ions are positioned in the high-k material. A channel material is deposited on the high-k material, and the source and drain (S / D) contacts are defined on the channel material. The buried gate is an alternative construction to a top gate and enhances manufacturing by using CMOS-like metallization in the construction of a three-terminal FET.

[0016] In one embodiment that may be combined with the previous embodiment, the channel material in the operation of depositing the high-k material is selected from the group consisting of an organic semiconductor, an oxide semiconductor, or a carbon nanotube, enabling advanced technology nodes.

[0017] In one embodiment that may be combined with the previous embodiment, the step of depositing the high-k material is configured to form alternating layers of high-k material having different bandgaps and to position mobile ions in more than one of the alternating layers of high-k material, resulting in more precise placement of mobile ions.

[0018] In one embodiment that may be combined with the previous embodiment, a plurality of gate stacks on the substrate comprise a superlattice material selected from the group consisting of HfSiO4, HfO2, HfSiO4, HfO2, HfSiO4, HfO2, or HfSiO4, which lends itself to symmetric updating and the ability to mimic biologically convincing synapses according to the diffusion of ions.

[0019] According to one embodiment, a mobile ion-modulated device comprises a three-terminal FET device structure having a gate stack filled with mobile ions. The gate stack includes multiple layers of material configured to confine the mobile ions. A source, a drain, and a gate are disposed on the substrate. A voltage biasing is disposed between the gate and at least one of the source or the source and the drain. The placement of mobile ions in designated regions of a dielectric layer allows for multiple levels of states for analog computing and analog synapses that may be used, for example, in neural networks. Faster and more efficient forms of AI may result.

[0020] In one embodiment that may be combined with the previous embodiment, the gate includes a top gate disposed above the substrate. The gate material of the gate stack includes a layer of dielectric material. The gate stack confines the mobile ions within the layer of dielectric material. The voltage biasing is configured to control the placement of the mobile ions within the layer. An applied voltage can direct the mobile ions toward an alignment area, which overcomes instability problems in MOS capacitors.

[0021] In one embodiment that may be combined with the previous embodiment, the gate comprises a buried gate disposed within a dielectric layer on the substrate, the gate material of the gate stack includes a layer of a high-k superlattice, and the voltage biasing is configured to control the placement of the mobile ions within the layer of the high-k superlattice material, which lends itself to symmetric updating and the ability to mimic biologically convincing synapses according to ion diffusion.

[0022] In one embodiment that may be combined with the previous embodiment, the high-K superlattice material is selected from the group consisting of HfSiO4, HfO2, HfSiO4, HfO2, HfSiO4, HfO2, or HfSiO4. The aforementioned materials are particularly suitable for superlattice materials.

[0023] In one embodiment that may be combined with the previous embodiment, the three-terminal FET structure is configured as an analog synapse, and the voltage biasing is configured to provide a quiescent state, an inhibited state, a potentiated state, and a readout state based on the respective configurations of at least the mobile ions within the three-terminal FET device, the various states allowing for use as an analog synapse in a neural network.

[0024] These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. [Brief explanation of the drawings]

[0025] The drawings are of exemplary embodiments. The drawings do not depict every embodiment. Other embodiments may be used in addition or instead. Details that may be obvious or unnecessary may be omitted to save space or for a more effective illustration. Some embodiments may be practiced using additional components or steps and / or without all components or steps shown. When the same number appears in different drawings, it refers to the same or similar components or steps.

[0026] [Figure 1A] FIG. 1 is a diagram of a three-terminal device including a gate stack filled with mobile ions, consistent with an illustrative embodiment.

[0027] [Figure 1B] FIG. 1 is a diagram of a three-terminal device structure having a buried gate and a mobile ion gate stack consistent with an example embodiment.

[0028] [Figure 2] FIG. 1C is a diagram of tuning mobile ions in a high-k stack in a three-terminal device as shown in FIGS. 1A and 1B, consistent with an example embodiment.

[0029] [Figure 3] FIG. 1 is a diagram of the operation of an analog synapse using a three-terminal device including a gate stack filled with regulated mobile ions, consistent with an exemplary embodiment.

[0030] [Figure 4] FIG. 1 is a process flow diagram for a stacked gate device having a mobile ion adjustment step consistent with an example embodiment.

[0031] [Figure 5]FIG. 1 is a process flow diagram for a buried gate device having a mobile ion adjustment step consistent with an example embodiment.

[0032] [Figure 6A] FIG. 2 illustrates a first portion of a process flow for a buried gate device with a high-K stack consistent with an example embodiment.

[0033] [Figure 6B] 6B is a continuation of the process flow shown in FIG. 6A for a buried gate device with a high-K stack, consistent with an example embodiment.

[0034] [Figure 7] 10 is a flowchart illustrating the operation of a device with mobile ion modulation consistent with an example embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0035] Overview In the following detailed description, numerous specific details are set forth by way of example to provide a thorough understanding of the relevant teachings. However, it should be understood that the present teachings can be practiced without such details. In other instances, well-known methods, procedures, components, and / or circuit configurations have been described at a relatively high level, without detail, to avoid unnecessarily obscuring aspects of the present teachings. It should be understood that the present disclosure is not limited to the depictions in the drawings, as there may be fewer or more elements than shown and described.

[0036] Efforts have been made to remove impure mobile ions through process optimization, but according to the present disclosure, impure mobile ions can be regulated and used in a confined and controllable manner, which is advantageous for synapse applications in AI.

[0037] As used herein, the term "dielectric" may be broadly interpreted to include oxide materials such as SiO2, HfO2, ZrO2, HfSiO, and HfZrO, and non-oxide materials such as SiN and AlN.

[0038] 1A is a diagram 100A of a three-terminal device 101 including a gate stack 125 filled with mobile ions consistent with an exemplary embodiment. While the three-terminal device in FIG. 1A is a FET, it should be understood that the present disclosure is not limited to modulating mobile ions on a FET. The three-terminal device 101 includes a drain 105, a gate 110, and a source 115. The drain 105 and source 115 are disposed on a substrate 120. The drain 105 and source 115 may comprise a buried source and drain or a top source and drain with deposited and transferred channels.

[0039] 1A is a top gate, but a recessed gate EG130 may be used, as shown in FIG. 1B. The gate 110 may be disposed on one or more gate stacks 125 that include a layer of dielectric material (e.g., SiO, SiN, HK, or a high-K superlattice stack (e.g., HfSiO, HfO, HfSiO, HfO, HfSiO, HfO, HfSiO).

[0040] Substrate 120 may be constructed from Si, although the present disclosure is not limited to Si. For example, the substrate may be made from any suitable substrate material, such as single crystal Si, silicon germanium (SiGe), aluminum gallium arsenide (AlGaAs), AlGaAs, AlGaAs, AlGaAs, AlN, GaSb, GaAlSb, GaAs, GaAsSb, GaN, InSb, InAs, InGaAs, InGaAsP, InGaN, InN, InP, and alloy combinations.

[0041] According to the present disclosure, three-terminal devices with regulated mobile ion synapses and methods of fabrication advantageously provide improved performance. For example, there are improvements in the operation of three-terminal FETs and improvements in hardware for AI applications. The use of regulated mobile ions in AI networks (e.g., neural networks) provides benefits related to symmetric updating due to symmetric diffusion mechanisms. Furthermore, three-terminal devices offer the feasibility of mimicking biologically convincing synapses, following the diffusion of ions in semiconductors. More accurate operation of neural networks at faster speeds can be achieved with savings in power and reduced computational load.

[0042] Additional advantages of the devices of the present disclosure are disclosed herein.

[0043] Example of a three-terminal device with tailored mobile ions FIG. 1B is a diagram 100B of a three-terminal device 201 having a buried gate and a mobile ion gate stack consistent with an exemplary embodiment. The device 201 includes a substrate 120, which may be constructed from Si or another material as disclosed for the substrate shown in FIG. 1A. A drain 105 and a source 115 are disposed on a channel 127. On the substrate 120 is a layer 128, which may be constructed from SiO2. A buried gate (EG 130) is shown within the layer 128. The EG 130 may be formed by CMOS-like metallization and reactive-ion etching (RIE), followed by depositing more oxide and chemical-mechanical polishing (CMP). Multiple gate stacks 125 are disposed above the EG 130. The gate stacks confine the mobile ions (identified by a sign). There are multiple alternating bandgaps, including a bandgap 126, which alternates with the bandgaps comprising the gate stacks 125 to form a heterostructure. The heterostructure facilitates the confinement of mobile ions in a more ordered arrangement. Channels 129 are optional and serve to isolate the materials by separating the two heterostructures with an HK stack, for the purpose of scalability in the formation of high-density synaptic arrays.

[0044] The channel 127 can be formed by depositing a semiconductor material or by transferring a channel material (e.g., oxide / organic semiconductors, carbon nanotubes, 2D materials, etc. for advanced technology nodes).

[0045] FIG. 2 illustrates at 200 the modulation of mobile ions in a high-k stack in a three-terminal device such as that shown in FIGS. 1A and 1B, consistent with exemplary embodiments. Here, there may be a high-k superlattice or layer of dielectric material used as a gate stack. The gate stack device 101 with a top gate and the gate stack device 201 with a buried gate shown in FIG. 2 have already been shown and described with respect to FIGS. 1A and 1B. FIG. 2 illustrates a possible band structure for a high-k superlattice for modulating mobile ions. Mobile ions (illustrated by the + symbol) located within a narrow bandgap dielectric are modulated.

[0046] The gate stack can be a superlattice built from HfSiO4, HfO2, HfSiO4, HfO2, / HfSiO4, HfO2, HfSiO4, to name just a few non-limiting possible examples.

[0047] FIG. 3 illustrates operation 300A-300D of an analog synapse using a three-terminal device including a gate stack filled with regulated mobile ions, consistent with an exemplary embodiment. Example (a) shows a three-terminal device with regulated mobile ions in a stationary state. The mobile ions, identified by plus signs, and electrons (identified by minus signs) are shown relatively aligned. Example (b) shows a negative gate pulse (e.g., inhibition) being applied to the device. There is some movement of the electrons and mobile ions away from the aligned rows shown in example (a). Example (c) shows a positive gate pulse (enhancement) being applied. Compared to example (b), a reversal of the positions of the mobile ion and electron pairs directly below the gate is shown in example (c). In example (d), a read pulse is applied between the source and drain. A negative pulse can supply electrons that attract mobile cations, leaving electrons paired with negative charges or holes in the channel; a negative pulse is referred to as inhibition. A positive pulse then causes the hole to recombine with the electron, releasing a mobile ion that pairs with the electron near the channel; the positive pulse is called potentiation. The charge transported during inhibition and potentiation can be detected from the read current in the channel between the source and drain. Note that analog synapses can be used with different structures (e.g., the recessed gate in FIG. 1B) and the combined options shown in FIG. 2.

[0048] Exemplary Process Flow 4 illustrates a process flow for a stacked gate device with a mobile ion modulation step consistent with exemplary embodiments. For purposes of brevity, conventional techniques for semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Furthermore, various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functions not described in detail herein. In particular, because the various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, for purposes of brevity, many conventional steps are only briefly described herein or omitted entirely without providing details of well-known processes.

[0049] Fabrication of the devices discussed herein may comprise, for example, a multi-step sequence of photolithographic and / or chemical processing steps that facilitate the progressive creation of electronics-based systems, devices, components, and / or circuits in semiconductor and / or superconducting devices (e.g., integrated circuits). For example, the device of FIG. 4 may be fabricated using techniques such as, but not limited to, photolithography, microlithography, nanolithography, nanoimprint lithography, photomasking techniques, patterning techniques, photoresist techniques (e.g., positive photoresist, negative photoresist, hybrid photoresist, and / or other photoresist techniques), etching techniques (e.g., reactive ion etching (RIE)), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, and / or other etching techniques), evaporation techniques, sputtering techniques, plasma ashing techniques, thermal treatments (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, and / or other thermal treatments), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical-mechanical planarization (CMP), and the like. The semiconductor device may be fabricated on one or more substrates (e.g., a silicon (Si) substrate and / or another substrate) by employing techniques including chemical mechanical planarization (CMP), backgrinding techniques, and / or other techniques for manufacturing integrated circuits.

[0050] The illustrated process flow begins with a substrate, which may be made of Si (although other materials may be used). A dielectric 405 is grown or deposited, or a high-K material is disposed, on a Si wafer, such as substrate 120. Mobile ions 123 are introduced into the dielectric 405 if such mobile ions were not incorporated into the growth / deposition of the dielectric (or HK) on substrate 120. A top conductive electrode 410 is deposited on the dielectric layer 405. Optionally, a bias (shown as V+ / -) and / or heating may be applied to the top electrode 410 to drive the mobile ions 123 to the bottom or top interface. GND is connected to the substrate 120, especially when a bias is applied to the top electrode 410. The top electrode 140 may be patterned as a gate contact 110 for each transistor on the substrate 120. Finally, source / drain (S / D) formation is completed to complete the structure. A spacer (e.g., a SiO2 / SiN stack) may be included to complete the process flow.

[0051] FIG. 5 illustrates a process flow for a buried gate device with a mobile ion adjustment step consistent with an exemplary embodiment. The process flow in FIG. 5 has some differences from the process flow in FIG. 4 because the gate is buried. A thermal dielectric 405 can be grown on the substrate 120. In a non-limiting example, the substrate 120 used can be Si and the dielectric used can be SiO2. The buried gate 130 can be defined by metallization and reactive ion etching (RIE), followed by depositing more dielectric and chemical mechanical polishing (CMP). A high-K material 510 or another dielectric is grown on the Si substrate 120. Mobile ions 123 can be simultaneously incorporated into the dielectric 510 or introduced in a separate operation.

[0052] 5, a channel material 127 may be deposited or transferred onto the dielectric layer 510. The channel material may include dielectric / organic semiconductor materials, carbon nanotubes, 2D materials, etc. Source 105 and drain 105 (S / D) contacts are then defined on the channel material 127. A passivation scheme may be employed to define the source and drain on the channel material.

[0053] 6A illustrates the first portion of a process flow for a buried gate device with a high-K stack consistent with an exemplary embodiment. Thermal oxide, shown as SiO2, on a substrate 120. It should be understood that the present disclosure is not limited to SiO2 as the dielectric, and the substrate 120 is not limited to Si. The buried gate (EG) is defined by performing metallization and RIE, followed by depositing more oxide and performing a CMP operation. Another oxide or high-K material is grown / deposited on the Si substrate 120, and mobile ions 123 can be incorporated simultaneously or introduced in a subsequent operation.

[0054] Figure 6B illustrates a continuation of the process flow shown in Figure 6A for a buried gate device with a high-K stack, consistent with an exemplary embodiment. The two process flows in Figure 6A, including or followed by the introduction of mobile ions, growing / depositing a dielectric or high-K on a Si wafer, are repeated with alternating high-K layers having different bandgaps. The next operation involves depositing or transferring a channel material 127 (e.g., oxide / organic semiconductor carbon nanotubes, 2D materials, etc.). Source 105 and drain 105 (S / D) contacts are defined. A passivation scheme may be applied.

[0055] Example Process With the foregoing overview of an exemplary architecture, it may be beneficial to now consider a high-level discussion of an exemplary process. To that end, Figure 7 is a flowchart illustrating the operation of a device with mobile ion modulation consistent with exemplary embodiments.

[0056] 7 is illustrated as a collection of blocks in a logical order, which represent sequences of operations that may be implemented in hardware, software, or a combination thereof. In the software context, the blocks represent computer-executable instructions that, when executed by one or more processors, perform the described operations. Generally, computer-executable instructions may include routines, programs, objects, components, data structures, and the like that perform a function or implement an abstract data type. Within each process, the order in which the operations are described is not intended to be considered limiting, and any number of the described blocks can be combined in any order and / or executed in parallel to implement a process.

[0057] In operation 702, a step of depositing a dielectric layer on a substrate is performed. For example, referring to FIG. 1A, the dielectric layer 128 can be an oxide, such as a SiO layer, on the substrate 120. The substrate can be a silicon substrate. However, the present disclosure is not limited to SiO oxide and Si substrates.

[0058] In operation 704, mobile ions are positioned in the dielectric layer. For example, referring to FIG. 1A, a plurality of mobile ions 123 are disposed on the gate stack layer. Referring to FIG. 4, the mobile ions 123 are disposed in the dielectric layer 405.

[0059] An electrode layer is provided on the dielectric layer in operation 706. Figure 4 shows a top electrode layer 410 disposed on the dielectric layer 405.

[0060] In operation 708, the mobile ions are driven to designated regions of the dielectric layer. FIG. 4 shows the voltage bias V+ / - and ground nodes. When a voltage bias is applied, the sparse distribution of mobile ions changes to the aligned rows of mobile ions shown. Different voltage levels and / or different polarities will drive the mobile ions to different regions of the dielectric layer. Different positions can be used to construct analog synapses. The method may terminate after operation 708.

[0061] conclusion The description of various embodiments of the present teachings has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements of the embodiments beyond those found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0062] While the foregoing has described what is believed to be the best mode and / or other examples, it should be understood that various modifications may be made thereto, that the subject matter disclosed herein may be implemented in a variety of forms and examples, and that the teachings may be applied to many applications, only a few of which are described herein. It is intended by the following claims to claim any and all applications, modifications, and variations that fall within the true scope of the present teachings.

[0063] The components, operations, steps, features, objects, benefits, and advantages discussed herein are merely exemplary. None of them, nor the discussion related thereto, are intended to limit the scope of protection. While various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, dimensions, sizes, and other specifications set forth in this specification, including the following claims, are approximate and not exact. They are intended to have a reasonable range consistent with the functions to which they pertain and that which is customary in the art to which they pertain.

[0064] Many other embodiments are contemplated, including those having fewer, additional, and / or different components, steps, features, objects, benefits, and advantages, and in which the components and / or steps are configured and / or ordered differently.

[0065] The flowcharts and diagrams in the figures herein illustrate the architecture, functionality, and operation of possible implementations according to various embodiments of the present disclosure.

[0066] While the foregoing has been described in conjunction with exemplary embodiments, it should be understood that the term "exemplary" is intended as an example only, not as best or optimal. Except as stated immediately above, nothing described or illustrated is intended to or should be construed as providing to the public any component, step, feature, object, benefit, advantage, or equivalent, whether or not claimed.

[0067] Terms and expressions used herein will be understood to have the ordinary meanings ascribed to such terms and expressions in relation to their corresponding respective fields of inquiry and study, unless a specific meaning is otherwise stated herein. Relative terms such as first and second, and the like, may be used solely to distinguish one entity or action from another, without necessarily requiring or implying any actual relationship or order between such entities or actions. The terms "comprises," "comprising," or other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements does not include only those elements, but may also include other elements not expressly listed in or inherent to such process, method, article, or apparatus list. An element preceded by "a" or "an" does not, in the absence of further constraints, exclude the presence of additional identical elements in a process, method, article, or apparatus that includes that element.

[0068] An Abstract is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. It can also be seen that in the foregoing Detailed Description, various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

Claims

1. 1. A method of making a mobile ion modulated device, said method comprising: depositing a dielectric layer on the substrate; providing mobile ions within the dielectric layer; providing an electrode layer on the dielectric layer; and driving the mobile ions into designated regions of the dielectric layer; A method comprising:

2. forming a three-terminal device from the mobile ion-modulated device by patterning the electrode layer into one or more gates; and forming a source and a drain on the substrate; The method of claim 1 further comprising:

3. 3. The method of claim 2, wherein the step of driving the mobile ions comprises biasing the oxide layer with a voltage.

4. 3. The method of claim 2, further comprising driving the mobile ions to different positions within the dielectric layer to provide multiple states of the three-terminal device for analog computing.

5. The method of claim 2 further comprising providing a plurality of gate stacks on the substrate comprising a plurality of superlattice HK stacks and confining mobile ions in a plurality of layers.

6. HfSiO ４ , HfO ２ , HfSiO ４ , HfO ２ , HfSiO ４ , HfO ２ , or HfSiO ４ 3. The method of claim 2, further comprising providing a plurality of gate stacks on the substrate comprising a superlattice material selected from the group consisting of:

7. The method of claim 2 further comprising providing a plurality of gate stacks containing multiple bandgaps constructed from alternating dielectric materials.

8. 3. The method of claim 2, further comprising performing symmetric set and reset operations by driving the same number of mobile ions within the dielectric layer in a first direction for a set operation and in a second direction opposite the first direction in a reset operation.

9. The method of claim 1 , wherein the step of driving the mobile ions comprises heating the dielectric layer.

10. 2. The method of claim 1, wherein the step of driving the mobile ions comprises heating the dielectric layer before or during the step of biasing the electrode layer.

11. 11. The method of claim 10, further comprising tuning conductance in adjacent channel layers by reapplying at least one of biasing or heating the dielectric layer.

12. 1. A method of making a mobile ion modulated device, said method comprising: depositing a thermal dielectric layer on the substrate; defining a buried gate in said thermal dielectric layer by metallization reactive ion etching; adding an additional thermal dielectric layer over the thermal dielectric layer and performing chemical mechanical polishing (CMP); depositing a high-k material on the thermal dielectric layer and positioning mobile ions within the high-k material; depositing a channel material on the high-k material; and defining source and drain (S / D) contacts on the channel material; A method comprising:

13. The method of claim 12 , wherein the channel material in the operation of depositing the high-k material is selected from the group consisting of an organic semiconductor, an oxide semiconductor, or a carbon nanotube.

14. 13. The method of claim 12, further comprising repeating the step of depositing the high-k material to form alternating layers of high-k material having different bandgaps, and locating mobile ions in more than one of the alternating layers of the high-k material.

15. HfSiO ４ , HfO ２ , HfSiO ４ , HfO ２ , HfSiO ４ , HfO ２ , or HfSiO ４ 13. The method of claim 12, further comprising providing a plurality of gate stacks on the substrate comprising a superlattice material selected from the group consisting of:

16. a three-terminal FET device structure having a gate stack filled with mobile ions; the gate stack includes multiple layers of material configured to confine the mobile ions; a source, a drain, and a gate disposed on the substrate; and a voltage biasing resistor disposed between at least one of the gate and the source, or between the source and the drain; A mobile ion regulated device comprising:

17. The gate includes a top gate disposed above the substrate; The gate material of the gate stack includes a layer of dielectric material; the gate stack confines the mobile ions within the layer of the dielectric material; the voltage biasing is configured to control the placement of the mobile ions within the layer.

17. The device of claim 16.

18. the gate comprises a buried gate disposed in a dielectric layer over the substrate; the gate material of the gate stack comprises a layer of a high-k superlattice; the voltage biasing is configured to control the placement of the mobile ions within the layer of the high-k superlattice material.

17. The device of claim 16.

19. The high-K superlattice material is HfSiO ４ , HfO ２ , HfSiO ４ , HfO ２ , HfSiO ４ , HfO ２ , or HfSiO ４ 17. The device of claim 16, selected from the group consisting of:

20. the three-terminal FET structure is configured as an analog synapse; the voltage biasing is configured to provide a quiescent state, a suppressed state, an enhanced state, and a read state based on respective configurations of at least the mobile ions within the three-terminal FET device.

17. The device of claim 16.

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