Atomic layer etching with electron wavefronts.

Abstract

We present atomic layer etching (ALE) of substrates using precisely controlled wafer-scale waves of electrons. A gaseous plasma volume containing a uniform steady-state composition of diluent, reactive species, and electrons is generated in the positive column of a direct-current plasma close to the substrate. A corrosion layer forms on the substrate through adsorption of reactive species to atoms at the substrate surface. The substrate is positively biased to attract electrons from the volume to the substrate surface, energizing the electrons to stimulate electronic transitions of the corrosion layer species, resulting in their expulsion via electron-stimulated desorption (ESD). The substrate is negatively biased to repel electrons from the substrate surface back into the volume, followed by zero bias to restore the steady-state composition of the volume.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority to U.S. Application No. 18 / 149,893, filed January 4, 2023, and entitled "Atomic Layer Etching by Electron Wavefront," the contents of which are incorporated herein by reference. Additionally, this application is related to U.S. Application No. 17,524,330, filed November 11, 2021, and entitled "DC Plasma Control for Electron Enhanced Material Processing" (Attorney Docket No. P2641-US), the entire disclosure of which is incorporated herein by reference. This application is further related to U.S. Application No. 17,668,301, filed February 9, 2022, and entitled "Electron Bias Control Signals for Electron Enhanced Material Processing" (Attorney Docket No. P2645-US), the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates generally to systems and methods for material processing, including atomic layer etching, in direct current plasma at room temperature (or other temperatures, if desired). The present disclosure relates generally to systems and methods for controlling free electrons in direct current plasma reaction chambers used for material processing, and more particularly to generating a waveform for a bias signal to control the kinetic energy of the free electrons to generate precisely controlled wafer-scale waves of electrons in a direct current plasma at room temperature (or other temperatures, if desired). [Background technology]

[0003] For example, the fabrication of integrated circuits involves processing corresponding substrates in a direct current plasma reaction chamber, where electrons and / or ions are accelerated toward the substrate surface and initiate reactions that physically change the substrate surface. In some cases, and primarily due to the relatively small mass of electrons compared to ions, electron-mediated substrate processing may be preferred to reduce damage to the substrate surface beyond the targeted physical changes expected by the processing step itself.

[0004] In some cases, plasma processing may involve placing a substrate in a region of a direct current plasma reaction chamber such that the exact value of the substrate's surface floating potential is unknown. Thus, a bias signal externally applied to the substrate may impart free electron energies in regions of the plasma close to the surface of the substrate that do not correlate with the electron energy thresholds / levels of the (atomic) material present at the surface of the substrate.

[0005] The above-referenced U.S. application Ser. No. 17,524,330, the entire disclosure of which is incorporated herein by reference, describes a method and system for precisely and selectively controlling the value of the surface floating potential of a substrate, thereby enabling precise and selective control of the energy levels of atoms at the surface of the substrate. The above-referenced U.S. application Ser. No. 17,668,301, the entire disclosure of which is incorporated herein by reference, utilizes such precise and selective control of the energy levels of atoms at the surface of a substrate to generate waveforms whose timing and amplitude correspond to signals used to bias free electrons in a DC plasma chamber to generate wafer-scale waves that specifically target the energy levels of atoms at the surface of the substrate.

[0006] The teachings of the present disclosure utilize the ability to generate wafer-scale waves of electrons (eg, electron wavefronts) that specifically target atomic energy levels at the surface of a substrate to etch away atomic layers of the substrate. Summary of the Invention

[0007] Systems and methods are disclosed for material processing, particularly atomic layer etching (ALE), using precisely controlled wafer-scale waves of electrons in a direct current plasma at room temperature (or other temperatures as desired). In this disclosure, such material processing is referred to as electron-enhanced material processing (EEMP), where the kinetic energy of free electrons in the direct current plasma can be precisely controlled to precisely (and selectively) target the electron energy levels of atoms on the surface of the substrate being processed. Such atoms may include atoms of adsorbed layers above the top atomic layer of the substrate. Under the local conditions created via the methods and systems of the present teachings, the low energy of the free electrons arriving at the substrate surface as an electron wavefront can promote desorption of the adsorbed layers along with the underlying surface atomic layer of the substrate.

[0008] According to a first embodiment of the present disclosure, a method for atomic layer etching of a substrate is disclosed, the method comprising the steps of generating a gaseous plasma quantity containing diluent species, reactive species, and electrons of a uniform steady-state composition in a positive column of a direct current plasma proximate to the substrate, thereby generating a floating potential at the substrate surface; adjusting the floating potential to a reference potential; forming a corrosion layer on the substrate, the corrosion layer including corrosion layer species formed by adsorption of reactive species to atoms of the atomic layer on the substrate surface; applying a positive bias potential to the substrate with respect to the floating potential; attracting electrons from the gaseous plasma quantity to the substrate surface based on the applying step and imparting energy levels to the attracted electrons to stimulate electronic transitions of the corrosion layer species; and desorbing the corrosion species layer based on the stimulating step, thereby etching away the atomic layer.

[0009] According to a second embodiment of the present disclosure, a method for atomic layer etching of a substrate via an electron wave front is disclosed, the method comprising the steps of: generating a gaseous plasma quantity including a uniform steady-state composition of diluent species, reactive species, and electrons in a positive column of a direct current plasma proximate to the substrate, thereby generating a floating potential at the substrate surface; adjusting the floating potential to a reference potential; and applying to the substrate a sequence of periodic bias signals referenced to the reference potential, the periodic bias signals including a positive bias potential followed by a negative bias potential, and then a zero bias potential equal to the reference potential, thereby causing arrival of an electron wave front having uniform energy and density across the entire surface of the substrate at arrival times predetermined by the periodic bias signal, wherein at each arrival time, the electron wave front stimulates electronic transitions in a corrosion layer formed on the substrate surface, thereby etching one atomic layer of the substrate.

[0010] Further aspects of the present disclosure are set forth in the specification, drawings and claims of this application. [Brief explanation of the drawings]

[0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of the exemplary embodiments, serve to explain the principles and embodiments of the present disclosure. [Figure 1A] 1 is a simplified schematic diagram of a DC plasma reaction chamber that can be used in a DC plasma processing system. [Figure 1B] 1B is a graph showing the evolution of the (electrical) potential of the plasma during operation of the DC plasma reaction chamber of FIG. 1A. [Figure 1C] 1B shows a simplified schematic diagram of a DC plasma processing system including a (substrate) stage positioned in the region of the DC plasma reaction chamber of FIG. 1A. [Figure 1D] 1D illustrates an exemplary biasing of a stage of the DC plasma processing system of FIG. 1C via an external bias signal generator. [Figure 1E]1D shows an exemplary bias signal generated by the external bias signal generator of FIG. 1D and the corresponding potential generated at the stage surface. [Figure 1F] 1 shows exemplary energy levels of atoms at the surface of the stage. [Figure 2A] 1 shows a simplified schematic diagram of a DC plasma processing system according to one embodiment of the present disclosure, including means for controlling the surface potential of a stage. [Figure 2B] 2B is a graph showing control of the surface potential of the stage of the DC plasma processing apparatus of FIG. 2A. [Figure 2C] 2B is a graph illustrating the adjustment of the surface potential of the stage relative to the reference ground potential of the DC plasma processing system of FIG. 2A. [Figure 3A] 1 shows a simplified schematic diagram of a DC plasma processing system according to one embodiment of the present disclosure, including means for controlling a surface potential of a stage and means for measuring the surface potential. [Figure 3B] 3B shows a simplified schematic diagram of a DC plasma processing system according to one embodiment of the present disclosure, based on the system of FIG. 3A with the addition of means for automatic control of the surface potential. [Figure 4A] 3C is a simplified schematic diagram of a DC plasma processing system according to an embodiment of the present disclosure based on the system of FIG. 3B with the addition of stage biasing means. [Figure 4B] 4B illustrates exemplary bias signals supplied to the stages of the DC plasma processing system of FIG. 4A and the corresponding potentials generated at the surfaces of the stages. [Figure 4C] 1 shows exemplary energy levels of atoms at the surface of the stage. [Figure 5] 1 is a process chart illustrating various steps of a method according to one embodiment of the present disclosure for treating a surface of a substrate. [Figure 6A] 1 is a graph illustrating the kinetics of electron-enhanced material processing (EEMP) for different materials according to the present disclosure. [Figure 6B]1 is a graph illustrating the kinetics of electron-enhanced material processing (EEMP) for different materials according to the present disclosure. [Figure 6C] 1 is a graph illustrating the kinetics of electron-enhanced material processing (EEMP) for different materials according to the present disclosure. [Figure 7A] 10 is a graph illustrating waveforms of EEMP bias signals for processing different materials, according to some exemplary embodiments of the present disclosure. [Figure 7B] 10 is a graph illustrating waveforms of EEMP bias signals for processing different materials, according to some exemplary embodiments of the present disclosure. [Figure 7C] 10 is a graph illustrating waveforms of EEMP bias signals for processing different materials, according to some exemplary embodiments of the present disclosure. [Figure 8A] 1 is a graph illustrating an idealized waveform of an EEMP bias signal. [Figure 8B] 1 is a graph showing a practical waveform of an EEMP bias signal. [Figure 8C] 1 is a graph showing an analog waveform under a capacitive load condition. [Figure 9A] 8C is a graph showing a digitized waveform for producing the practical waveform of FIG. 8B and a corresponding digitized waveform with predistortion. [Figure 9B] 9B is a graph illustrating an analog waveform generated from the predistorted digitized waveform of FIG. 9A under capacitive load conditions. [Figure 10A] 1 is a graph illustrating gain versus frequency for a band-limited linear power amplifier according to an embodiment of the present disclosure and for a conventional power amplifier. [Figure 10B] 10B is a graph showing an analog waveform generated from the predistorted digitized waveform of FIG. 9A through the band-limited linear power amplifier of FIG. 10A under capacitive load conditions. [Figure 11] 4 is a process chart illustrating various steps of a method for treating a surface of a substrate according to another embodiment of the present disclosure. [Figure 12A]1A-1D show various schematic diagrams representative of initialization tasks and corresponding states of a direct current plasma reaction chamber in preparation for atomic layer etching (ALE) of a substrate surface via electron-enhanced material processing (EEMP) according to the present disclosure. [Figure 12B] 1A-1D show various schematic diagrams representative of initialization tasks and corresponding states of a direct current plasma reaction chamber in preparation for atomic layer etching (ALE) of a substrate surface via electron-enhanced material processing (EEMP) according to the present disclosure. [Figure 12C] 1A-1D show various schematic diagrams representative of initialization tasks and corresponding states of a direct current plasma reaction chamber in preparation for atomic layer etching (ALE) of a substrate surface via electron-enhanced material processing (EEMP) according to the present disclosure. [Figure 13A] 1A-1D show various schematic diagrams representative of the state of a DC plasma reaction chamber during the active phase of atomic layer etching (ALE) according to the present disclosure. [Figure 13B] 1A-1D show various schematic diagrams representative of the state of a DC plasma reaction chamber during the active phase of atomic layer etching (ALE) according to the present disclosure. [Figure 13C] 1A-1D show various schematic diagrams representative of the state of a DC plasma reaction chamber during the active phase of atomic layer etching (ALE) according to the present disclosure. [Figure 13D] 1A-1D show various schematic diagrams representative of the state of a DC plasma reaction chamber during the active phase of atomic layer etching (ALE) according to the present disclosure. [Figure 13E] 1A-1D show various schematic diagrams representative of the state of a DC plasma reaction chamber during the active phase of atomic layer etching (ALE) according to the present disclosure. [Figure 14] FIG. 1 is a representative schematic diagram of a DC plasma reaction chamber during the neutralization phase of atomic layer etching (ALE) according to the present disclosure. [Figure 15] FIG. 1 is a representative schematic diagram of a DC plasma reaction chamber during an initialization phase of atomic layer etching (ALE) according to the present disclosure.

[0012] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION OF THE INVENTION

[0013] 1A shows a simplified schematic diagram of a prior art DC plasma reaction chamber (110) that may be used in a DC plasma processing system. A bias for the DC plasma reaction chamber (110) may be provided by a DC voltage source (150) coupled between an anode A and a cathode C of the DC plasma reaction chamber (110). During operation, a glow discharge (plasma) may be formed within the chamber (110) based on the interaction of gas with electrons in the current flowing between the anode A and the cathode C. This generates free ions and electrons within the chamber. The operating principles of such a DC plasma reaction chamber (110) are well known to those skilled in the art, and therefore, relevant details will not be discussed further in this disclosure.

[0014] 1A, the glow discharge formed within the chamber (110) may include glow regions (G1, G2, G3, G4) that emit significant light and dark regions (D1, D2, D3, D4) that may not emit light. Such regions may represent different operating characteristics of the DC plasma reaction chamber (110), including, for example, temperature and electrical potential.

[0015] FIG. 1B shows the plasma (electrical) potential V along the axial (longitudinal) direction X of the chamber (110) during operation. PP As shown in Figure 1B, the plasma potential V PP is the value V representing the potential applied to the cathode C by the DC voltage source (150 in Figure 1A). C , the value V representing the potential applied to anode A by the DC voltage source (150 in FIG. 1A) A For example, as shown in FIG. 1D below, the value V A is zero volts (e.g., reference ground), and the value V C It should be noted that is negative (eg, negative for values ​​in the range of about 0 (zero) to 500 volts).

[0016] Continuing to refer to FIG. 1B, the potential V in the region near the cathode C (e.g., D1, G1, D2) and the region near the anode A (e.g., G4) PP The rapid fluctuations in V may correspond to regions of higher operating temperature in the chamber (110). The other region G3, also known as the positive column, is a region of somewhat uniform / constant potential, V PP For example, as shown in FIG. 1B, the segment [X G31 , X G32 ] is included in the positive column region G3, such a segment [X G31 , X G32 ] across the plasma potential V PP The variation of is minimal, in other words, the segment [X G31 , X G32 ] potential V PP can be considered constant. Therefore, as shown in Figure 1B, the segment [X G31 , X G32 ] plasma potential V pp is the value V G3 The lower operating temperature and constant potential value of the plasma in the positive column region G3 allows such region to be used for substrate processing, as shown in Figures 1C and 1D.

[0017] 1C shows a simplified schematic diagram of a DC plasma processing system (100C) including a (substrate) stage S positioned in the positive column region G3 of the DC plasma reaction chamber (110). The stage S may be designed to support a flat substrate and therefore may include a flat / planar surface on its upper surface. The stage S shown in FIG. 1C is electrically isolated (not connected to an external potential) and therefore is not connected to the plasma potential V, as is well known to those skilled in the art. PP In the presence of S is generated, and the potential V S is the surface floating potential V FP This is called the (surface) floating potential V FP and plasma potential V PPThe relationship between the area [X G31 , X G32 ] plasma potential V PP is V G3 and the floating potential V FP is the plasma potential V G3 lower than (plasma potential V G3 is negative with respect to

[0018] The floating potential V shown in the graph of Figure 1C FP can be attributed to a "plasma sheath" that develops in the presence of stage S. As known to those skilled in the art, walls or barriers within a plasma develop a negative potential relative to the bulk of the plasma. As a result, an equilibrium potential drop occurs between the bulk of the plasma and the wall or barrier. This potential drop is limited to a small region of space adjacent to the wall or barrier due to a charge imbalance that develops between the plasma and the wall or barrier. This layer of charge imbalance has a finite thickness, characterized by the Debye length, and is called the "plasma sheath" or "sheath." The thickness of such a layer is several Debye lengths, the magnitude of which depends on various plasma characteristics. For example, when the dimensions of the bulk plasma (e.g., chamber 110) are much larger than the Debye length, the Debye length depends on the plasma temperature and electron density. For the specific case of DC plasma operating conditions supported by the teachings of the present disclosure (e.g., an EEMP system near to moderately above room temperature), the Debye length is on the order of a few millimeters (e.g., less than 10 millimeters), and the potential V G3 and V FP The difference between V and V is on the order of a few volts (e.g., less than 10 volts). It should be noted that the plasma sheath can occur in the presence of any wall or barrier, whether conductive or not. Thus, once the substrate (whether conductive or insulating) is placed on the stage S, it is exposed to the same floating potential V as described above with reference to FIG. 1C. FP can occur on the surface of the substrate.

[0019] 1D illustrates an exemplary biasing of stage S of the DC plasma processing system of FIG. 1C via an external bias signal generator (180) capacitively coupled to stage S by a capacitor C. In the exemplary configuration (100D) shown in FIG. 1D, a potential V applied to anode A is A is zero volts (e.g., tied to a reference ground, Gnd). Additionally, as shown in FIG. 1D, a bias signal V applied to the stage S by an external bias signal generator (180) B can be referenced to a reference ground potential Gnd. In some prior art implementations, the bias signal V B may be DC coupled to the stage S, however, the teachings of the present disclosure strictly prohibit such DC coupling to the stage to avoid a discharge path for DC current through any intermediate point within the chamber (110), which could significantly alter the operating conditions within the chamber (110).

[0020] In the DC plasma processing system shown in FIG. 1D, the bias signal V B is the potential seen by free electrons and / or ions near the stage S, or the substrate, if present (e.g., the surface potential V S ) can be used to control the energy of the free electrons and / or ions to a material-specific level required for (optimal) processing of the substrate. For example, as shown in the graph on the left side of FIG. 1E, the bias signal V generated by an external bias signal generator (e.g., 180 in FIG. 1D) can be used to control the energy of the free electrons and / or ions to a material-specific level required for (optimal) processing of the substrate. B starts from zero and increases the voltage amplitude V B1 As shown in the top right graph of Figure 1E, during processing step (a), the voltage amplitude V B1 is applied to the stage S (e.g., AC coupled), the voltage amplitude V B1 is the surface floating potential V FPa (or subtracted if negative) to generate a surface potential V S However, the free electrons and / or ions are at the plasma potential V PPa, so that the free electrons and / or ions see a plasma potential V PPa The surface potential V exceeds S For example, as shown in the upper right graph of FIG. 1E, the (kinetic) energy of free electrons and / or ions is Potential difference V KEa =(V B1 -ΔV FPa ), where: ΔV FPa , =(V PPa -V FPa )

[0021] On the other hand, different differential ΔV FPb , =(V PPb -V FPb ) can occur at different plasma potentials V PPb , or different floating potentials V FPb Considering the process step (b) represented by the lower right graph of FIG. 1E, which may have different operating conditions from the operating conditions of the process step (a) including the same applied voltage amplitude V B1 , resulting in different (kinetic) energies of the free electrons and / or ions. The teachings of the present disclosure eliminate variations in operating conditions within the chamber (e.g., 110 in FIG. 1D ) and / or compensate for such variations, e.g., to enable precise control of the energy of the free electrons (and / or ions). It should be noted that variations in operating conditions are expected when considering different types of processes (e.g., (a) and (b) in FIG. 1E ) performed within the chamber (110), including, for example, etching the substrate with different reactive gases, cleaning the substrate, or other processes that may alter and / or remove composition / material from the surface of the substrate. It should be noted that, as known to those skilled in the art, different operating conditions for performing different types of processes may further include corresponding variations and / or adjustments to any one of the DC plasma current, temperature, gas mixture, or flow rates within the chamber (110).

[0022] When the substrate is placed on the surface of the stage S, the bias signal V BThe kinetic energy of the free electrons and / or ions obtained by the application of V accelerates them towards the surface of the substrate and may cause them to collide with the substrate, releasing their kinetic energy to atoms on the surface of the substrate. However, these atoms are not at the potential at which they exist, in other words, the floating potential, V. FP The various energy levels of such atoms for the process type (a) described above with reference to FIG. 1E are based on the energy level E of the nuclei of the atoms at the substrate surface. n , the energy level E of electrons bound to the nuclei of atoms on the substrate surface B , and the energy level E of the electron in the orbital of the electron bound to the atomic nucleus on the substrate surface e , as shown in Figure 1F.

[0023] As can be seen in Figure 1F, the nuclear energy level E n is the (negative) potential V FPa and the electron energy level E e is the (negative) potential (E n +E B In other words, to excite an atom to a level that breaks the bond between the electron and the nucleus, the electron must be at the energy level E e Therefore, if we consider a plasma that is processed only through free electrons, the potential difference V KEa =(V B1 -ΔV FPa ) is the bias signal V B The kinetic energy of the free electrons supplied by the application of e must be equal to or greater than . However, E e =(E n +E B ) and E n is the a priori unknown floating potential V FPa Therefore, the energy level E e It may be impossible to precisely control the kinetic energy of the free electrons in order to precisely target them.

[0024] Floating potential (e.g., V in Figure 1F) FPa While the floating potential (F) can be empirically and / or experimentally determined for a given process under stable operating conditions in a DC plasma chamber, inconsistencies and / or lack of reproducibility in such operating conditions can invalidate the determined floating potential. Furthermore, because different types of processes result in disparate floating potentials, the task of precisely controlling the kinetic energy of free electrons to precisely target the energy levels of atoms on the substrate surface may be unfeasible. As a result, in some prior art implementations, atoms on the substrate surface may be imparted with kinetic energy substantially greater than the energy levels of the targeted atoms, which may result in a lack of selectivity (because atoms of different materials / compositions with different energy levels may equally experience enough energy levels to break orbital bonds). Electron-enhanced material processing (EEMP) according to the teachings of the present disclosure overcomes such drawbacks and, therefore, enables the precise control of the kinetic energy of free electrons to precisely and selectively target the energy levels of atoms on the substrate surface.

[0025] 2A shows a simplified schematic diagram of a DC plasma processing system (200A) according to one embodiment of the present disclosure, which includes means (250, 260) for controlling the surface potential of the stage S when electrically isolated. In other words, these means (250, 260) control the floating potential V FP As shown in FIG. 2A, the means (250, 260) includes an adjustable DC voltage source (250) coupled to the anode A of the DC plasma reaction chamber (110) and a DC current source (260) coupled to the cathode C of the DC plasma reaction chamber (110). Thus, the potential V A of the anode A can be controlled to be in a range above zero volts (positive) relative to a reference ground (Gnd of zero volts), and the current I p flowing (draining) between the anode A and the cathode C through the reaction chamber (110) can be set by the DC current source (260). Thus, the potential V A of the cathode C can be controlled to be above zero volts (positive) relative to a reference ground (Gnd of zero volts). Cis not forced by an external DC voltage source (e.g., 150 in FIG. 1D), but rather (floats) to the adjustable potential V of anode A. A and settles to a (negative) voltage based on the set current Ip. Such a configuration allows the floating potential V to be increased while maintaining a constant set current Ip through the reaction chamber (110) to establish and maintain a higher level of process stability and optimization. FP This allows the control / adjustment of

[0026] FIG. 2B illustrates the surface potential V of the stage S of the DC plasma processing system (200A) described above with reference to FIG. 2A. FP In particular, FIG. 2B shows two graphs, distinguished by the use of solid or dashed lines, each graph representing two different voltages (V) applied to anode A by adjustable DC voltage source (250). A1 , V A2 ) across the longitudinal extension X of the chamber (110) relative to PP As can be seen in Figure 2B, the voltage V A1 to voltage V A2 A positive step increase in anode potential to +ΔV 12 With respect to the floating potential (V FP1 , V FP2 ) and cathode potential (V C1 , V C2 ) is the same positive step, +ΔV 12 In fact, as shown in Figure 2B, the plasma potential V PP For the whole of 12 In other words, the range [X C , X A For any longitudinal coordinate X in the PP (X) is the step increase, +ΔV 12 A similar behavior applies to the negative step variation applied to anode A by the adjustable DC voltage source (250). In other words, the control of the potential of anode A by the adjustable DC voltage source follows the plasma potential V at any longitudinal coordinate X. PP and therefore the floating potential VFP and the voltage V at the top of stage S S As will be discussed later in this disclosure, such linearity is important when operating a DC plasma chamber for different types of material processing while maintaining a floating potential V FP This can be used in an EEMP system according to the present teachings to implement a closed-loop control subsystem that automatically controls the value of V to a preset value (e.g., zero volts).

[0027] Figure 2C shows the anode voltage V A1 2B, which shows two graphs similar to the one described above with reference to FIG. 2B, including the special case where V is equal to zero volts (solid line). As can be seen in FIG. 2B, the floating potential voltage in such a case is a negative value V FP1 and therefore the plasma potential V PP Furthermore, as can be seen in Figure 2C, a positive step increase in the anode potential, +ΔV 13 =(V A1 -V FP1 ), the floating potential is equal to zero volts, V FP3 According to one embodiment of the present disclosure, the floating potential V FP Such zeroing of may allow for precise control of the kinetic energy of free electrons within a DC plasma in order to precisely (and selectively) target the energy levels of atoms at the surface of the substrate (whether conductive or insulating) being processed. In other words, referring back to FIG. 1F, the energy level E of the nuclei of the atoms targeted / selected for processing may be n The a priori unknown floating potential that determines the floating potential V FP On the other hand, as shown in FIG. 4B below, this causes the target electron energy level E e , the kinetic energy level of free electrons in a DC plasma (e.g., V in Figure 1F) KEa ), and the bias voltage V applied to the stage S B allows all the voltages to be referenced to the same known and fixed reference, zero volt potential Gnd. FPIt should be noted that while providing a known level of may be provided by zeroing such potential as described above, such zeroing should not be considered as limiting the scope of the present disclosure, as other pre-set / adjusted non-zero values ​​of floating potential may similarly function as reference potentials for precisely controlling the kinetic energy of free electrons in a DC plasma in order to precisely (selectively) target the energy levels of atoms at the surface of the substrate (whether conductive or insulating) being processed.

[0028] FIG. 3A shows a means for controlling the surface potential of the stage S (250, 260 in FIG. 2A) and a surface potential V S (e.g., floating potential, V FP ) means for measuring (R, 311, V in Figure 3A) R 3 shows a simplified schematic diagram of a direct current plasma processing system (300A) according to an embodiment of the present disclosure, comprising: a surface potential V S Means for measuring (R, 311, V R ), or in other words, the floating potential (surface) above the stage V FP Means for measuring (R, 311, V R ) represents an improvement over the system (200A) described above with reference to FIG. 2A. FP By enabling such measurement of the surface potential V, adjustment of the DC voltage source (250) as described above with reference to FIGS. 2A-2C can be performed to FP This may be done while monitoring / measuring the floating potential V, including for example forcing such potential to zero (VFP=0 volts). FP This allows for precise control of the

[0029] Still referring to FIG. 3A, the means (R, 311, V R) includes a reference plate R located in the DC plasma chamber (110) in the same (longitudinal coordinate) segment [XG31, XG32] as the stage S. The reference plate R may be made of any conductive material that can withstand the (internal) operating conditions of the chamber (110) and may have any planar shape, including, for example, planar shapes according to a square, rectangle, circle, pentagon, trapezoid, or others. The reference plate R is located in the same area as the stage S and therefore has the same substantially constant plasma potential V PP Since the reference plate R is located in the region of FP In other words, the (surface) potential V on the reference plate R R By measuring the potential V, the floating potential at the stage S can be determined. An insulated conductive wire (311) attached to the reference plate R is connected to the potential V R to measurement electronics (e.g., transducers) located outside the chamber (110). It should be noted that such measurement electronics should not provide a DC current path to the plasma through plate R.

[0030] Continuing with reference to FIG. 3A , the location of the reference plate R may be any longitudinal extension of the chamber (110) within the segments [XG31, XG32] that is technically feasible and practical. The chamber (110) may include an access door adjacent to the stage S on one side of the chamber (110), and in some exemplary embodiments, the reference plate R may be positioned against or near a wall of the chamber (110) opposite the access door and the stage S. Furthermore, according to exemplary embodiments, the center of the reference plate R and the center of the stage S (e.g., the intersection of the two T-shaped segments of the stage as shown) may be contained within a line perpendicular to the axial direction (e.g., the centerline, the direction of the longitudinal extension) of the chamber (110). Applicant of the present disclosure has proposed a method for tracking the floating potential of the stage S using a means (R, 311, V R ) was confirmed to have high accuracy.

[0031] FIG. 3B illustrates the surface potential V on the stage S based on the system (300A) of FIG. 3A. FP 1 shows a simplified schematic diagram of a DC plasma processing system (300B) according to an embodiment of the present disclosure, with the addition of a means (320, CT) for automatic control of the floating potential V at stage S while operating the DC plasma chamber for different types of processes. FP The control electronics (320) is configured to incorporate a closed-loop control system that automatically controls the value of V to a preset value (e.g., zero volts). In particular, as shown in FIG. 3B, the control electronics (320) controls the (surface) potential V of the reference plate R via the coupling provided by the insulated conductive wire (311). R is taken as input, and the voltage V supplied to the anode A is A , and thus the floating potential V in the stage S, as described above with reference to FIGS. 2A-2C. FP The control (error) signal CT is adjusted to a floating potential V, e.g., zero volts. FP The control electronics 320 may be generated with respect to a desired target / preset value of V. Those skilled in the art are familiar with design techniques for implementing control electronics 320, which are beyond the scope of this disclosure. In particular, those skilled in the art are familiar with the use of operational amplifiers or error amplifiers in such control electronics 320, the input of which is connected to a potential V. R , and the floating potential V FP to a desired target / preset value (e.g., zero volts) and generate an error signal (e.g., CT) based on the difference in the inputs.

[0032] FIG. 4A shows a biasing means (C S 3B with the addition of bias means (C , 480). S , 480) is the capacitor C of the bias means SIn other words, the bias signal V generated at the output of the bias signal generator (480) is B is the capacitor C S The bias signal generator (480) generates and outputs a bias signal V according to desired characteristics including, for example, amplitude, frequency, duty cycle, and / or rising / falling edges / slope. B Note that the stage S may include a programmable waveform generator configured to output a waveform of a bias signal V. B a first conductive portion (e.g., a capacitor C) for electrically coupling the stage S to the S Note that the stage may include a first portion (e.g., a vertical lead connected to the first portion) and a second portion (e.g., a horizontal support plate) that may include conductive and / or insulating material.

[0033] FIG. 4B illustrates an exemplary bias signal V applied to stage S of the DC plasma processing system (400A) of FIG. 4A. B1 , and the corresponding surface potential V generated on the surface of the stage S. S As will be clearly understood by those skilled in the art, the graph shown in FIG. FP 1E corresponds to a configuration of the system (400) where V is adjusted or controlled to be zero volts. Thus, in view of (or in contrast to) the discussion above with reference to FIG. 1E, the (kinetic) energy of free electrons and / or ions attracted to the surface of the stage S or a substrate thereon is equal to the potential difference V KE =(V B1 -ΔV FP ) and ΔV FP =(V PP -V FP) Therefore, in practical substrate processing applications using a DC plasma chamber, ΔV FP The value of V KE (e.g., the energy level E of the target electron in Figure 4C) e Since the approximate value V KE =V B1 is considered reasonable, which in turn allows for the bias signal V provided to stage S to precisely and selectively target the energy levels of atoms (e.g., bound electrons) at the surface of the substrate for performing electron-enhanced material processing (EEMP) according to the teachings of the present disclosure. B1 This allows for simple and easy generation of

[0034] 4A and 4B, the excitation of the energy levels of atoms at the surface of the stage S or at the surface of a substrate disposed on the stage S is primarily due to the surface potential V S Note that the excitation of the energy levels may be based on the instantaneous change in the bias voltage V. B1 This can be achieved immediately at the end of the transition to , in other words, at the end of the ramp shown in FIG. 4B.

[0035] 4C illustrates exemplary energy levels of atoms at the surface of the stage S of the DC plasma processing system (400A) of FIG. 4A. FIG. 4C illustrates the floating potential V , based on the above description with reference to FIGS. 2A-2C , further based on the reference plate R, based on the above description with reference to FIG. 3A , further based on the (optional) closed-loop control system provided by the control electronics (320), based on the above description with reference to FIG. 3B , and further based on the capacitive coupling of the bias signal V B provided by the bias signal generator (480), based on the above description with reference to FIG. 4A . FP Based on the zeroing of KE This highlights the benefits of electron-enhanced materials processing (EEMP) according to the teachings of the present disclosure, which allows for precise and selective targeted tailoring of the material.

[0036] 5 is a process chart (500) illustrating various steps of a method according to an embodiment of the present disclosure for treating a surface of a substrate. As shown in FIG. 5, such steps include: positioning a substrate support stage in a region of a DC plasma reaction chamber configured to generate a positive column of DC plasma according to step (510); generating DC plasma by coupling an adjustable DC voltage source and a DC current source to an anode and a cathode of the DC plasma reaction chamber, respectively, according to step (520); generating a floating potential at the surface of the substrate support stage based on the generating step according to step (530); adjusting the potential of the anode via the adjustable DC voltage source while maintaining a constant DC current between the anode and the cathode via the DC current source according to step (540); and setting the floating potential to a reference ground potential of the adjustable DC voltage source based on the adjusting and maintaining step according to step (550).

[0037] 6A-6C are graphs illustrating the reaction kinetics of electron-enhanced material processing (EEMP) according to the present disclosure for different (categories / types / classes) of materials, including single crystal or two-dimensional (2D) materials, such as semiconductor or insulator materials (FIG. 6A), metals and metal alloys (FIG. 6B), and composite materials, such as polymers, composites, nanomaterials, or three-dimensional (3D) materials (FIG. 6C). In this case, the reaction, or target reaction, is determined by the bias signal V applied to the stage (e.g., S in FIG. 4A). B This can be referred to as the breaking of chemical bonds (e.g., bonds between electrons and atomic nuclei) of atoms of a material at the surface of a substrate placed on a stage (e.g., S in FIG. 4A) in response to a level of . As is evident from such a graph, the reaction rate RR is proportional to the reaction threshold voltage V RTH , reaction cut-off voltage V RCO , and the reaction threshold voltage V RTHV It should be noted that for each material or type of material, such characteristic voltages may be different and are generally part of a priori acquired knowledge base. For example, the V RTHis the V of the metal material (e.g., Figure 6B) RTH , or V of the composite material (e.g., Figure 6C) RTH and V of the crystalline material (e.g., Figure 6A). RTHV is the V of a metal material (e.g., FIG. 6B) or a complex material (e.g., FIG. 6C). RTHV may differ from

[0038] It should be noted that 2D materials compatible with electron-enhanced materials processing (EEMP) according to the present disclosure include, for example, graphene, boron nitride, molybdenum disulfide, tungsten diselenide, or platinum diselenide; nanomaterials compatible with EEMP according to the present disclosure include, for example, carbon nanotubes, nanosilver particles, titanium oxide particles, or quantum dots; and 3D materials compatible with EEMP according to the present disclosure include, for example, any 3D structure formed of a material, including polymers, collagen fibers, or metals, such as titanium, or 3D-printed polymer / polymer, polymer / carbon, or polymer / metal microstructures. Single crystals compatible with EEMP according to the present disclosure include, for example, semiconducting single crystals of Group IV silicon, germanium, Group III-V gallium arsenide, gallium nitride, silicon carbide, indium gallium arsenide, Group II-VI zinc selenide, and quantum well stacks containing alternating Group II-VI and / or Group III-V compound semiconductors. Single crystals compatible with EEMPs according to the present disclosure further include semiconducting single crystals such as, for example, quartz, sapphire, or diamond. Polymers compatible with EEMPs according to the present disclosure include, for example, polypropylene, polyethylene, polyetheretherketone, and polycarbonate. Composites compatible with EEMPs according to the present disclosure include, for example, polymers containing metal particles, carbon particles, carbon fibers, or carbon nanotubes. The materials and structures listed herein should be considered non-limiting with respect to the list of materials compatibility for EEMPs according to the present teachings; this list may grow as new materials / structures and corresponding bond energies and reaction energies that may be targeted by the present EEMPs are obtained, for example, through advanced methods for computer simulation of chemical bonding.

[0039] Continuing with reference to FIGS. 6A-6C, for example, as described above with reference to FIG. 4B, when a substrate is placed on a stage (e.g., S in FIG. 4A), a floating potential (e.g., V in FIG. 4B) is generated. FP ) can be adjusted (controlled) to a known potential (e.g., zero volts or other). Thus, the energy levels of atoms at the substrate surface assume the same potential (e.g., as the ground state) and no reaction may be observed at the substrate surface, or in other words, the reaction rate RR of the target bond (in the ground state) is zero, as shown in Figures 6A-6C. The bias voltage V B As r increases, the reaction rate RR of the target bonds remains zero, and then a small (e.g., few) number of target bonds slowly begin to react, or in other words, once a small number of target bonds reach their respective excited states, the reaction cutoff voltage V RCO The bias voltage V B is the reaction threshold voltage V RTH When the bias voltage V reaches B With further increase in , the reaction rate RR increases with a (substantially) constant slope, which increases with increasing bias voltage V B is the reaction threshold voltage V RTHV This continues until the threshold voltage V RTH and the reaction threshold voltage V RTHV Between these, the reaction rate RR increases until (almost) all of the target bonds react. As shown in Figures 6A-6C, the reaction threshold shift voltage V RTHV Further exceeding the bias voltage V B Increasing the bias voltage V B As the bias voltage V decreases, the reaction rate RR becomes similar to the graphs shown in Figures 6A to 6C. B is the reaction cut-off voltage V RCO When the reaction temperature drops below , the reaction rate RR drops to zero as all target bonds on the substrate surface return to their ground state.

[0040] As is clear from the graphs in FIGS. 6A to 6C, the voltage V RTH and V RTHV The (substantially) constant slope of the reaction rate RR between or the difference between the two voltages may be a function of the material used for the (surface of) the substrate being treated. RTH and V RTHV The difference between the surface and the substrate temperature may be due to atomic-level defects on the surface of a single crystal material such as a semiconductor or insulator (e.g., FIG. 6A), atomic-level defects and associated grain boundaries on the surface of a metal, metal alloy, or nanomaterial (e.g., FIG. 6B), or the presence of three-dimensional (3D) structures in polymers, composites, or other 3D materials (e.g., FIG. 6C). As will be described later in this disclosure, the teachings of the present disclosure provide a method for controlling the activation (or deactivation) of a reaction governed by the reaction rate RR, e.g., the graphs shown in FIGS. 6A-6C, by using voltage levels V specifically targeted to the material used for the substrate. B In particular, specific waveforms for each material represented in the graphs of reaction rate RR in Figures 6A, 6B, and 6C are shown in Figures 7A, 7B, and 7C, respectively.

[0041] 7A-7C are graphs illustrating waveforms of EEMP bias signals V(t) according to some exemplary embodiments of the present disclosure for processing different materials. In particular, FIG. 7A illustrates waveforms for processing single-crystal materials such as semiconductors or insulators, FIG. 7B illustrates waveforms for processing metals, metal alloys, or nanomaterials, and FIG. 7C illustrates waveforms for processing polymers, composites, or three-dimensional materials. Such graphs may be used to illustrate ideal voltage levels (e.g., V) of bias signals V(t) for use in the EEMP processes according to the present disclosure described above. B , V BN ), which represents the potential V FP to a known level, such as zero volts or other fixed known level, and FP Voltage / potential level relative to (e.g., V B It should be noted that the method may include energizing free electrons in a direct current plasma with a

[0042] Each graph in FIG. 7A to FIG. 7C shows the time course of the (periodic) bias signal V(t). EEMP The EEMP process of the material on the surface of the substrate is carried out over a predetermined number of cycles, T, according to a priori knowledge of the process. EEMP , the bias signal V(t) generated through the repetition of the RR characteristics. Different EEMP processes (e.g., with different RR characteristics) may be implemented using different layers of material in the substrate and / or different operating conditions and / or potentials V in the DC plasma reaction chamber. FP can be carried out sequentially on the same substrate, taking into account (controlled / preset) levels of

[0043] Continuing with reference to FIGS. 7A-7C, according to one embodiment of the present disclosure, the waveform of the bias signal V(t) is EEMP are three different phases (e.g., time intervals, time segments, durations) ΔT, which include voltage levels above zero volts (or a reference voltage level), below zero volts, and equal to zero volts, respectively. BP , ΔT BN , and ΔT BZ In other words, the time interval ΔT BP During this time, the level V of the bias signal V(t) B is strictly greater than zero volts (or a reference voltage level) for a time interval ΔT BN During this time, the level V of the bias signal V(t) BN is strictly less than zero volts and for the time interval ΔT BZ During this time, the level of the bias signal V(t) is equal to zero volts.

[0044] According to one embodiment of the present disclosure, the duration T of the cycle of the waveforms shown in FIGS. EEMPmay be in the range of 1 μs to 10 μs, or in other words, the frequency of the bias signal V(t) may be in the range of 100 KHz to 1 MHz. According to further embodiments of the present disclosure, the waveform of the bias signal V(t) may be DC-free, or in other words, the integral over a cycle of the waveforms shown in FIGS. 7A-7C may have a value of zero. Such DC-free characteristics of waveforms according to the present teachings may be advantageous in controlling the preset / controlled local surface potential (e.g., V) of the substrate, as described above with reference to, for example, FIGS. 2A-4C. FP ) shown in Figures 7A-7C. B , V BN ) can be applied to the substrate surface. FP is adjusted (e.g., preset, controlled) to a (fixed, known) level different from zero volts, the waveform FP 7A to 7C. In other words, the potential V FP Note that this can be adjusted by substituting the value of

[0045] According to one embodiment of the present disclosure, the time interval ΔT shown in FIGS. BP , ΔT BN , and ΔT BZ The length of each of the time intervals ΔT can be based on the type of material (at the surface) of the substrate, including the corresponding reaction rate RR, as described above with reference to FIGS. BP The length of the time interval ΔT BNThe ratio of t to t may be in the range of (approximately) 1 / 10 to (approximately) 1 / 1. For example, in the case of crystalline materials (e.g., FIG. 7A), the ratio may be about 10 / 65 (±10%), in the case of metallic materials (e.g., FIG. 7B), the ratio may be about 1 / 2 (±10%), and in the case of composite materials (e.g., FIG. 7C), the ratio may be about 1 / 1 (±10%). Furthermore, as shown in FIGS. 7A-7C, the overall cycle length T EEMP The length of the time interval ΔT BZ According to a non-limiting embodiment of the present disclosure, the ratio of the time interval ΔT BZ The length of the period is T EEMP may be based only on the time interval ΔT BP and ΔT BN The length of each of the above may be independent.

[0046] For the exemplary, non-limiting case shown in FIGS. 7A-7C, the time interval (ΔT BP , ΔT BN , ΔT BZ ) the total cycle length T EEMP The ratio of t to t can be (e.g., ±10%), and can be about (10 / 100, 65 / 100, 25 / 100) for crystalline materials (e.g., Figure 7A), about (25 / 100, 50 / 100, 25 / 100) for metallic materials (e.g., Figure 7B), and about (37.5 / 100, 37.5 / 100, 25 / 100) for composite materials (e.g., Figure 7C). Figures 7A-7C show cycle T with a length of 4 μs (frequency 250 KHz). EEMP However, as noted above in this disclosure, such lengths may be in the range of 1 μs to 10 μs (e.g., frequencies between 100 KHz and 1 MHz) and should not be considered as limiting the scope of this disclosure.

[0047] Continuing to refer to the waveforms in Figures 7A-7C, the phase ΔT BPDuring this time, the waveform applies a bias voltage V(t) to a (positive) level (e.g., V ) to activate a (targeted) EEMP reaction at the substrate surface based on collisions between energized (free) electrons and target bonds at the substrate surface (e.g., surface materials including single crystal for FIG. 7A, metal for FIG. 7B, and composite for FIG. 7C). B According to one embodiment of the present disclosure, the (high) level V of the bias voltage V(t) can be set to B The length of time that ΔT is maintained must be long enough to keep the energized (free) electrons on the substrate surface and react with the target bond. Such a length is determined by the phase ΔT shown in Figures 7A-7C. BP (Part of) the rising or falling slope included in (e.g., the bias voltage (V(t)) when the target high level V B It should be noted that the expression does not necessarily include a period (while not included).

[0048] Furthermore, phase ΔT BN 7A-7C, the waveforms of FIGS. 7A-7C drive the bias signal V(t) to a (negative) level V(t) to deactivate the EEMP reaction on the substrate surface and also to discharge (e.g., repel) any free electrons from the substrate surface, thereby neutralizing the charge on the substrate. BN Phase ΔT BN During this time, the kinetic energy is BN It should be noted that the energized free ions may be given to the free ions in the DC plasma by , so that the energized free ions may move slowly toward the substrate surface and thereby further participate in the neutralization of the substrate. Furthermore, it should be noted that due to their low energy level, the energized free ions may (and should not) not react with the bonds on the substrate surface. The voltage level V of the bias signal V(t) BN The magnitude of ΔT is therefore high enough (e.g., can be more negative) for the free ions to move slowly towards the substrate, and the phase ΔT BN The duration of the voltage level V BN Magnitude and phase ΔT BPIn combination with the duration of ΔT, it may be long enough to cause suppression (or control) of the DC component of the bias signal V(t). The time ΔT may be long enough so that the free electrons do not have enough energy to damage the corrosion layer, but also too little energy to reach and neutralize the substrate, bringing the net charge and current to zero. BN Length and V BN The depth / size of the

[0049] Phase ΔT BZ During this time, the waveforms of FIGS. 7A to 7C show that the voltage level of the bias signal V(t) is zero (or floating potential V FP (same preset level). Therefore, the phase ΔT BZ is the bias signal V(t) for each cycle T EEMP may be used to restore a similar initial bias condition of the substrate at the start of FP This may allow for a more stable and accurate process (EEMP) when compared to other prior art processes. Therefore, based on the description provided, the cycle T describing the waveform of the bias signal V(t) EEMP Each phase ΔT BP , ΔT BN , and ΔT BZ can be referred to as the active (EEMP) response phase, the (EEMP) neutralization phase, and the (EEMP) initialization phase, respectively, the latter two phases being inactive phases with respect to the targeted (EEMP) response.

[0050] Figure 8 shows the active phase ΔT BP Further timing details describing each portion of the waveform in (e.g., time interval t BR , t BH , and t BR 7A-7C, including the idealized waveform of the EEMP bias signal V(t) described above with reference to FIGS. 7A-7C. In particular, the waveform of the EEMP bias signal V(t) is shown for the time interval t BRis the value of the bias signal V(t) from its starting value at the beginning of the phase (e.g., V(t)=0) to the target high level V B The transition time can be specified to reach the time interval t BH is the target high level V(t) of the bias signal V(t). B and a time interval t BF is the bias signal V(t) during the active phase ΔT BP A transition time can be specified to return to the starting value (e.g., V(t)=0) at the end of the time interval t BR is the starting value to a higher level V B The rising (e.g., leading) edge slope of the bias signal V(t) can be specified to reach BF can define the falling (eg, trailing) edge slope of the bias signal V(t) to return to the starting value.

[0051] Still referring to FIG. 8A, time interval t BH During this time, the bias signal V(t) is RTH High level V B , and thus, as described above with reference to, for example, FIGS. 6A-6C, the target binding is, as described above with reference to, for example, FIGS. 7A-7C, in the time interval t BH Each excited state can be reached as long as the duration of the active phase ΔT is long enough to keep the energized (free) electrons on the substrate surface to react with the target bond. According to an exemplary embodiment of the present disclosure, BP The length of the time interval t for BH The ratio of V(t) to T(t) may be in the range of about 1 / 4 (e.g., ±10%) to about 3 / 4 (e.g., ±10%). Thus, a periodic bias signal V(t) having a frequency of 250 KHz and a cycle length T equal to 4 μs is EEMP Consider the case of performing EEMP processing on a single crystal material (e.g., as shown in Figures 6A and 7A above), where the length of the time interval t BHcan be in the range of about 0.1 μs to about 0.3 μs.

[0052] Further referring to FIG. 8A, the bias signal V(t) is applied during the active phase ΔT BP As the reaction threshold voltage V increases at the onset of RTH The level of the bias signal V(t) that exceeds BR Similarly, if the bias signal V(t) is BH As the voltage decreases at the end of RTH The level of the bias signal V(t) that exceeds BF 8A is effectively seen by free electrons in a DC plasma, the level of the bias signal V(t) can be maintained for a portion of the reaction threshold voltage V RTH A time interval t that is greater than or equal to BR and t BF may be included in the determination (or interpretation) of the graph of reaction rate RR described above with reference to Figures 6A-6C. However, the time interval t BR and t BF Since the slope of the rising and falling edges defined by B may be in the range of 10 volts to about 200 volts), a portion of which may be considered irrelevant / unimportant compared to the minimum time required to keep energized (free) electrons on the substrate surface to react with target bonds.

[0053] FIG. 8B is a graph illustrating a practical waveform of an EEMP bias signal. Such a waveform represents a practically achievable waveform that can be modeled from the ideal waveform described above with reference to FIG. 8A. In particular, the practical waveform of FIG. 8B, as shown, exhibits a corresponding steady-state level (e.g., V B , V BN, zero volts). Such realistic waveforms may be generated by electronic equipment that may include a power amplifier (e.g., coupled to and / or part of the bias signal generator of FIG. 4A) whose output is coupled to a load under perfectly matched conditions. However, such perfectly matched conditions are not provided by the capacitive load (e.g., stage S of FIG. 4A) in DC plasma processing according to the present disclosure, and therefore, the steady-state level (e.g., V B , V BN Before settling to a voltage (voltage, zero volts), signal reflections including ringing and associated distortions can be expected.

[0054] The ringing shown in FIG. 8C occurs at the target high level V B The active stage phase ΔT before settling BP Between and target low level V BN Neutralization phase ΔT before settling BN The ringing of the bias signal V(t) (e.g., V BU ) during the active phase. BP is the overshoot voltage V BOS Targeting high levels of V B and the undershoot voltage V BUS Targeting high levels of V B The spread of uncertain voltage V below BU Those skilled in the art will understand that the undershoot voltage V BUS The level of the bias signal V(t) is the threshold voltage V RTH The overshoot voltage V BOS The level of the bias signal V(t) is the threshold voltage V' of the reaction of non-target bonds that may be present on the substrate surface. RTH The spread of uncertain voltage V BU It will be clearly understood that during the activation phase, activation of the EEMP target response can be disrupted. On the other hand, during the neutralization phase, ΔT BNThe ringing during the active phase ΔT does not significantly affect the EEMP process because the free ions are kept well below the reaction energy of any ion-driven reactions (e.g., thermochemical reactions). BP Reduction of the ringing shown in FIG. 8C, including the ringing in the middle, may be provided by predistortion (eg, distortion compensation) of the bias signal V(t).

[0055] FIG. 9A shows a digitized waveform (WF, circled digital samples) for generating the practical waveform of FIG. 8B and the corresponding predistorted digitized waveform (WF P , digital samples marked with squares). In particular, generation of the practical waveform of FIG. 8B may be provided by uploading the corresponding digital samples WF of the digitized waveform to a digital signal generator whose output may be provided to a power amplifier (e.g., coupled to or part of the bias signal generator of FIG. 4A). Similarly, generation of the corresponding practical waveform with predistortion may be provided by uploading the corresponding digital samples WF of the predistorted digitized waveform P may be provided by uploading the signal to a digital signal generator.

[0056] With continued reference to FIG. 9A, predistortion can be performed using a practical predistortion waveform (e.g., WF) that can provide a reduced amount of ringing when subjected to the capacitive load conditions of a stage (e.g., S in FIG. 4A), as shown in FIG. 9B. P ) can be used to change / equalize the slope / transition of the digitized waveform with predistortion. As shown in FIG. 9B, using predistortion can reduce the overall active phase ΔT BP During this time, the bias signal level V(t) is equal to the target threshold voltage V RTH Any non-target reaction threshold voltage V' exceeds RTH The spread of the uncertainty voltage V BU Such predistortion can cause a decrease in the bias signal V(t) from the desired high level VB The desired length of the time interval t BH In other words, the predistortion may result in a waveform that includes a time interval t BH The length can be maintained.

[0057] FIG. 10A is a graph representative of gain versus frequency of a band-limited linear power amplifier according to an embodiment of the present disclosure (e.g., graph G1) and a graph representing gain versus frequency of a conventional power amplifier (e.g., graph G2). According to one embodiment of the present disclosure, a band-limited linear power amplifier used for EEMP processing may include a flat gain G1 within 0.75 dB within the frequency range of 10 KHz to 10 MHz, as shown in FIG. 10A. This operating (passband) range of the band-limited linear power amplifier includes any corresponding (higher frequency) harmonics that may be reflected from capacitive loads, as well as some of the ringing (e.g., uncertainty voltage spread, V) shown in FIGS. 8C and 9B. BU The 100 KHz to 1 MHz frequency range of operation of the bias signal V(t) is chosen to reduce any corresponding (higher frequency) harmonics that may produce distortion of the signal, including

[0058] FIG. 10B shows the predistorted digitized waveform WF of FIG. 9A through the band-limited linear power amplifier of FIG. 10A under capacitive load conditions. P 9B is a graph showing the analog waveform generated from the waveform shown in FIG. 9B. In particular, when compared to the waveform described above with reference to FIG. 9B, the spread of the uncertainty voltage V BU A decrease in is observed, indicating a larger process window for target EEMP response control / manipulation. It should be noted that the waveform in Figure 9B can be reproduced by a conventional power amplifier whose gain vs. frequency G2 is shown in Figure 10A. In particular, as shown in Figure 10A, the cutoff frequency f of the conventional power amplifier C2 is the cutoff frequency f of the band-limited linear power amplifier according to the present teachings. C1may be substantially larger than V(t) and may pass high frequency harmonics of the bias signal V(t) and thus reproduce such harmonics as distortion.

[0059] 11 is a process chart (1100) illustrating various steps of a method according to one embodiment of the present disclosure for processing a surface of a substrate. As shown in FIG. 11, these steps include, in step (1110), placing a substrate on a support stage within a region of a DC plasma reaction chamber configured to generate a positive column of DC plasma, in step (1120), generating DC plasma, in step (1130), presetting a floating potential of the substrate surface to a reference potential, in step (1130), and capacitively coupling a periodic bias signal to the support stage, the periodic bias signal having a bias voltage referenced to the floating potential, in step (1140), the periodic bias signal including an activation phase having a positive voltage, a neutralization phase having a negative voltage, and an initialization phase having zero voltage, relative to a known reaction threshold voltage of a target chemical bond of atoms on the surface of the substrate.

[0060] The various steps of the process chart (1100) in FIG. 11 can be used for atomic layer etching (ALE) of a substrate surface. Such steps target atomic bonds on the substrate surface via low-energy electrons (e.g., with energies less than 500 eV), thereby avoiding surface damage to the substrate beyond that associated with the targeted chemical bonds. Atomic layer etching according to the present disclosure may be based on electron stimulated desorption (ESD), in which the desorption process is stimulated by electronic excitation of quantum transitions (e.g., energy level jumps) at the surface of a substrate (e.g., a wafer) and is controlled by material-specific energy thresholds. ESD proceeds via a fundamentally different mechanism than the (traditional) subsurface collision cascade initiated by momentum transfer via ion bombardment. These material-specific energy thresholds provide the opportunity to tailor / target electron energy to specific materials, thereby enabling ALE according to the present disclosure to achieve high specificity and selectivity between different materials.

[0061] Low-energy electrons (e.g., less than 500 eV), including part of the precisely controlled wafer-scale waves of electrons generated in accordance with the present teachings, can interact with a substrate surface disposed, for example, in the DC plasma reaction chamber (110) of a DC plasma processing system described above with reference to FIG. 4A. These electrons can cause physical and chemical changes in the substrate surface.

[0062] Atomic layer etching according to the present disclosure involves the use of an adsorbed layer on the surface of the substrate to be etched. The adsorbed layer is composed of reactive species present in the plasma. The formation of the adsorbed layer is purely chemical and may involve weak or strong bond interactions between the reactive species and the substrate. Reactive species include H atoms (radicals), H+, H-, H2, H2+, and H 2ー(H species are defined as reactive species in this example). The presence of an adsorbed layer can result in more significant physical and chemical changes to the substrate surface. A reactive layer (adsorbed layer) attached to an underlying surface layer is defined as a corrosion layer. In combination with low-energy electrons reaching the substrate surface, the conditions created within a DC plasma reaction chamber (e.g., 110 in FIG. 4A) can promote desorption (e.g., desorption or removal of the corrosion layer) of the corrosion layer attached to the substrate as ionic, neutral atomic, and / or molecular species.

[0063] The above-described process for removing corrosion layers (adsorbed layers along with underlying surface atomic layers) using low-energy electrons, which may be used in atomic layer etching (ALE) according to the present disclosure, is referred to herein as electron-stimulated desorption (ESD). This effect results from electron excitation, not thermal excitation resulting from the collision (momentum transfer) of low-energy electrons. It should be noted that momentum transfer from low-energy electrons may not provide enough energy to desorb corrosion layers (surface species, including reactive species bound to the surface atomic layer of the substrate, the corrosion layer). Because the mass of electrons is very small compared to the colliding corrosion layer species (surface-bound atoms and surface reactive species), the energy transfer to surface-bound atoms upon collision is negligible (typically less than 0.1 eV), insufficient to cause removal of reactive species, which may include bonds in the range of approximately 1 eV to 8 eV. However, electron excitation may be energetic enough to cause desorption of (targeted) corrosion layers by ESD.

[0064] It should be noted that the EEMP process of the present teachings is distinct from electron beam-based processes and ion bombardment processes (e.g., RIE) known in the art. While the EEMP process of the present teachings differs from electron beam-based processes, both can utilize ESD to remove corrosion layer species, the difference lies in the scale at which they operate. Such beam techniques are highly localized, at best on the millimeter scale. In stark contrast, and advantageously, the EEMP process of the present teachings can operate at any scale that a direct current plasma positive column can occupy, or be made to occupy, including ranges (widths) from millimeters to meters. The EEMP process of the present teachings and the ion bombardment process differ in their fundamental operating mechanisms. The EEMP process of the present teachings operates via ESD. In ESD, arriving electrons resonantly excite and destabilize only the corrosion layer species, thereby raising their binding energy (without momentum transfer). The corrosion layer species then exert a repulsive force on the underlying (excited) layer of the substrate. As a result, only the erosion layer species are kinetically repelled (removed) from the substrate and subsequently enter (and are swept out of) the positive column. Ion bombardment processes known in the art impart momentum transfer to the erosion layer species via collisions that cause subsurface collision cascades due to the large mass of the ions. With sufficient momentum, these subsurface collision cascades can expel the erosion layer species. Essentially, these subsurface momentum cascades inevitably leave a trace / effect of the surface layer being removed in the newly exposed layer (subsurface). The interaction of the ion-enhanced process with the subsurface layer has undesirable consequences for smooth finish, maintaining stoichiometry, embedding ions into the substrate, and impact damage, which are not present in EEMP.

[0065] Electronic excitation can occur when electrons arriving at a surface transfer energy to the bonding electrons of corrosion layer species, raising their binding energy (resonant excitation of the bonding electrons by the arriving electrons), destabilizing the surface corrosion layer species. In this case, the excited corrosion layer species may move from a stable ground-state electronic configuration to an excited-state electronic configuration with a repulsive potential. This repulsive potential then imparts kinetic energy to the corrosion layer species, facilitating their ejection from the substrate surface, thereby completing the removal / etching of the top layer of the substrate. As previously mentioned, these ejection thresholds are material-dependent, so by adjusting the energy of the incident electrons and providing different reactive species, ESD can affect a variety of materials with high specificity and selectivity.

[0066] Atomic layer etching (ALE) by electron-enhanced material processing (EEMP) according to the present disclosure includes the steps of providing a substance that adsorbs onto atoms of the top atomic layer of a substrate to be etched to generate erosion layer species on the substrate surface; generating energetic electrons that target the chemical bonds of the erosion layer species; and exciting the erosion layer species using an electron stimulated desorption (ESD) process, thereby ejecting / releasing the erosion layer species, thereby etching away the top atomic layer of the substrate.

[0067] 12A, 12B, and 12C show various schematic diagrams representing initialization tasks and corresponding states of a direct current plasma reaction chamber (e.g., 110 in FIG. 4A) in preparation for atomic layer etching (ALE) of a surface of a substrate Sub via electron-enhanced material processing (EEMP) according to the present disclosure.

[0068] As shown in FIG. 12A and with further reference to FIG. 4A, the substrate Sub is placed on a stage S, which is located in a region of a direct current plasma reaction chamber (110) configured to include a positive column region G3, as previously described. In FIG. 12A (and the following figures), the substrate Sub is represented by atomic layers (L1, L2, L3), each of which contains atoms of the material that makes up the substrate Sub. In the exemplary, non-limiting case of the substrate Sub shown in FIG. 12A, three layers (L1, L2, L3) are shown, each of which contains atoms represented by a (large) circle. In the exemplary, non-limiting case of the substrate Sub shown in FIG. 12A, each layer (L1, L2, L3) contains silicon atoms Si; in other words, the exemplary, non-limiting substrate Sub may be considered a silicon substrate. As previously described in this disclosure, electron-enhanced material processing (EEMP) according to the present disclosure, including its application to atomic layer etching (ALE), is applicable to different categories / types / classes of materials and, therefore, can be applied to different substrates containing such materials. In other words, the substrate Sub may include any of such materials in any one of the layers (e.g., L1, L2, L3, ... and thereafter). Furthermore, two such layers may include the same material (i.e., atoms) or different materials (e.g., adjacent atomic layers).

[0069] The legend in the top right of FIG. 12A (and the following figures) relates to the symbols used in the figures, which represent material particles, such as atoms, ions, or molecules, that may be present in the plasma reaction chamber (110) during various states / phases of processing of the substrate Sub. Such material particles correspond to reactive (e.g., soluble) gases, represented by small circles; diluent (e.g., solvent) gases, represented by crosses; electrons, represented by dots (legend: e-); excited-state substrate Sub atoms, represented by large circles containing asterisks; and ground-state substrate Sub atoms, represented by large (empty) circles. The legend associated with such symbols refers to exemplary reactive gases, which may include hydrogen (H atoms, e.g., hydrogen molecules, H), diluent gases, which may include argon (Ar), and excited-state (Si *) or ground state (Si) silicon atoms (e.g., atomic bonds).

[0070] As shown in FIG. 12A, a silicon substrate Sub is positioned on a stage S in preparation for an atomic layer etching (ALE) process. In this case, the plasma reaction chamber (110), and thus the stage S and the substrate Sub, may be placed under vacuum by means well known to those skilled in the art. Other parameters within the plasma reaction chamber that may affect the substrate Sub, such as temperature (including, for example, the stage / substrate), may also be set / controlled. Additionally, in FIG. 12A, material particles (H species, Ar+, e-, Si * ) indicates that no DC plasma, and therefore no excited silicon atoms, are present in the plasma reaction chamber (110).

[0071] FIG. 12A illustrates a time t during which the stage S, and therefore the substrate Sub, is not actively biased by a bias signal generator (e.g., 480 in FIG. 4A). OFF Therefore, as shown in FIG. 12A, t OFF At time t, there is no bias signal V(t) coupled to the stage S and therefore to the substrate Sub. As discussed above in this disclosure, the bias signal V(t) is a time-varying bias voltage (e.g., V in FIG. 4A) that is capacitively coupled to the stage S. B ) may represent a corresponding voltage level (e.g., V RTH and V BN ) and phase (e.g., ΔT BP , ΔT BN , and ΔT BZ ) are described above with reference to, for example, FIGS.

[0072] FIG. 12B may represent a state of an atomic layer etching process (ALE) at time t0, where a diluent gas (e.g., argon) or a reactive gas (e.g., hydrogen) is present in the plasma reaction chamber (110) and generates a DC plasma (in the positive column, e.g., glow region G3). When the DC plasma is generated (e.g., ignited), some of the diluent gas and some (if not all) of the reactive gas are ionized to generate free electrons e shown in FIG. 12B. As a result, the distribution of ion species in the positive column of the DC plasma may include ions of the diluent gas, represented by Ar+ in FIG. 12B, as well as particles of the reactive gas, which may include H species as shown in FIG. 12B and subsequent figures.

[0073] It should be noted that the dilution gas and the reactive gas may be introduced into the plasma reaction chamber (110) simultaneously as a mixed gas or separately and sequentially, and thus such gases may ionize / ignite simultaneously or separately within the plasma reaction chamber. Furthermore, according to some exemplary embodiments, reactive species (e.g., H species) may be generated in a separate chamber and then introduced into the plasma reaction chamber (110) to provide the distribution of ion species shown in FIG. 12B. It should also be noted that a large portion of the free electrons e shown in FIG. 12B may correspond to the current (e.g., Ip in FIG. 4A) flowing between the anode A and cathode C of the plasma reaction chamber (110).

[0074] As noted above in this disclosure, the atomic layer etching (ALE) process of the present disclosure is not limited to argon as the diluent gas and hydrogen as the reactive gas. Some non-limiting exemplary diluent gases may include any one of argon (Ar), neon (Ne), or xenon (Xe). Some non-limiting exemplary reactive gases may include hydrogen (H), chlorine (Cl), methane (CH), carbon monoxide (CO), oxygen (O), or others, alone or in combination. Furthermore, according to one embodiment of the present disclosure, the ratio of reactive gas to diluent gas used (prior to plasma ignition) in the atomic layer etching (ALE) process of the present disclosure may be in the range of about 2 / 100 to about 50 / 100 or more.

[0075] As described above in this disclosure, during the atomic layer etching (ALE) process of the present teachings, a portion (e.g., from about a few percent to about 100%, e.g., fully ionized) of the reactant gas introduced into the chamber (110) may be ionized to generate reactive species (e.g., H species). The ionized portion of such reactant gas, as well as the corresponding distribution of reactive species, i.e., the relative number of H species in the exemplary case of hydrogen, can be controlled via process parameters, including, for example, the magnitude of the current Ip described above with reference to FIG. 4A. While the present description of the atomic layer etching (ALE) process considers H species of the ionized reactant gas (e.g., in forming an adlayer), it should be noted that other components (e.g., reactive species) of the ionized reactant gas, including, for example, H+ and / or H− in the exemplary case of hydrogen, may alternatively be used to provide different etching performance, including, for example, selectivity with respect to target material / atoms and / or substrate surface finish / smoothness.

[0076] As discussed above with reference to, for example, FIG. 1C, the presence of a DC plasma and, therefore, the corresponding plasma potential V PP Considering the distribution of ion species shown in FIG. 12B, in the positive column of a DC plasma, the (surface) floating potential V FPmay occur at the surface of the stage S, and therefore the substrate Sub, in FIG. 12B. For example, as described above with reference to FIG. FP can be adjusted to a known reference potential, for example, the reference ground potential of the DC plasma processing apparatus (e.g., FIG. 4A) used in the atomic layer process herein. FP It should be noted that the adjustment of may be performed after the distribution of ion species in the DC plasma reaction chamber (110) has stabilized (e.g., reached a steady state or equilibrium) and before applying the bias voltage to state S.

[0077] As shown in FIG. 12B at time t0, the stage S, and therefore the substrate Sub, may be actively biased (e.g., by a stage voltage V) by a bias signal generator (e.g., 480 in FIG. 4A). S In Figure 12B, V S = 0V). In other words, at time t, a bias signal generator (e.g., 480 in FIG. 4A) can bias stage S, and thus substrate Sub, with a voltage provided by bias signal V(t) coupled to stage S, and thus substrate Sub. The bias signal V(t) can be applied to a floating potential V FP Because V(t) may be referenced to the same reference ground potential to which V is adjusted, the coupling of a bias signal V(t) having an amplitude of zero volts (0 V) at time t to the stage S, and therefore to the substrate Sub, as shown in FIG. 12B, may not substantially change or affect the distribution of ion species provided to the positive column of the DC plasma.

[0078] Continuing to refer to Figure 12B, it can be seen that some of the reactive species (e.g., H species) are bonded (i.e., adsorbed) to atoms (e.g., Si) of the (top) surface layer L1 of the substrate Sub. In other words, Figure 12B shows the (initiation of) formation of an adsorbed layer of reactive species on the surface layer L1 (e.g., shown in Figure 12B as three individual H species bonded to layer L1). The combination of adsorbed reactive species on the surface layer L1 can be referred to as an etch layer, which is removed by electron stimulated desorption (ESD), effectively etching away an atomic layer (e.g., L1) of the substrate Sub.

[0079] The formation of the corrosion layer may proceed in stages (but quickly) and is based on parameters found at the location of stage S. These may include the temperature of stage S, the pressure within the DC plasma reaction chamber (110), the current (e.g., Ip in FIG. 4A) flowing between the anode A and cathode C of the plasma reaction chamber (110), and / or the flow rate of the DC plasma, which may determine the residence time of reactive species (e.g., H species) in contact with the surface (e.g., layer L1) of the substrate Sub. To etch away the entire surface layer L1 of the substrate Sub, each atom (e.g., Si) of the surface layer L1 may contain at least one adsorbed reactive species. This is shown in FIG. 12C.

[0080] FIG. 12C may represent the state of the atomic layer etching (ALE) process at time t1 when the corrosion layer is formed. In other words, as shown in FIG. 12C, each atom (e.g., Si) of the surface layer L1 includes (e.g., is attached to) at least one adsorbed reactive species (e.g., H species, which may include one or more of SiH1, SiH2, or SiH3 to form the corrosion layer species). It should be noted that the corrosion layer formation time of the atomic layer etching (ALE) process according to the present teachings is relatively fast, on the order of a few microseconds (μs) to about 10 μs. Such rapid corrosion layer formation is believed to be primarily due to the reactive species (e.g., H species) being turned on and continuously present (e.g., not switched on and off) throughout the plasma for the entire duration of the atomic layer etching process. This is due to the (initialization) phase ΔT described above, e.g., with reference to FIGS. 7A / 7B / 7C. BZ 12C with reference to FIG.

[0081] Assuming that the time t0 shown in FIG. 12C corresponds to the time when the corrosion layer starts to form, the period from the time t0 to the time t1 when the corrosion layer starts to form is at least the duration ΔT BZ Once the corrosion layer is formed (e.g., at time t1), the substrate Sub is ready for the active phase of the atomic layer etching (ALE) process according to the present disclosure, which involves electron stimulated desorption (ESD) of the corrosion layer via an ESD mechanism. This is shown in FIG. 12C as a future phase ΔT of the bias signal V(t). BP (For example, cycle T described above with reference to Figures 7A / 7B / 7C EEMP (part of ).

[0082] 13A, 13B, 13C, 13D, and 13E show various schematic diagrams representative of the state of the DC plasma reaction chamber (110) during the active phase of atomic layer etching (ALE) according to the present disclosure. In other words, during such active phase, the stage S is driven for cycles T of the bias signal V(t) described above with reference to, for example, FIGS. 7A / 7B / 7C. EEMP Positive pulse ΔT of the active phase BP The voltage V corresponding to S Such conditions include the rise time / fall time / edge of the positive pulse (e.g., t BR and t BF ) and the target reaction threshold voltage V RTH The high level of the positive pulse provided by the (high) positive voltage corresponding to (e.g., t in Figures 8A / B / C and 9A / B) BH ) during the active phase ΔT BP The state may include:

[0083] FIG. 13A shows the state where a corrosion layer is formed (e.g., according to FIG. 12C) and the stage voltage V S may represent the state of the atomic layer etching (ALE) process at time t when the stage voltage V follows (or begins to follow) the rising edge of the positive pulse. Sis the target reaction threshold voltage V RTH However, the stage voltage V S , i.e., the substrate surface Sub is at a floating potential V FP Since the stage S is at a positive voltage with respect to the substrate surface Sub, some of the (negatively charged) free electrons e are attracted to the stage S and therefore move towards the substrate surface Sub. On the other hand, the ions of the diluent gas (Ar+) have a mass that is substantially larger than the mass of the free electrons e, and therefore move towards the substrate surface Sub within the time scale of the entire positive pulse (e.g., ΔT, which is on the order of a few microseconds). BP , e.g., less than 4 μs), its spatial position can be considered to be substantially constant, as provided, for example, by the ion distribution depicted in FIG. 12C.

[0084] Positive pulse, i.e., stage voltage V S As the stage voltage V increases, more free electrons e are attracted to the substrate surface Sub. This is shown in FIG. 13B, where at time t3, S is the target reaction threshold voltage V RTH In this case, the corrosion layer formed on the surface of the substrate Sub (i.e., H species adsorbed on Si atoms of L1) may be in contact with electrons e- having an energy level close to, but not equal to, the target reaction energy level required to stimulate the electron transition in the corrosion layer.

[0085] once positive pulse, hence the stage voltage V S is the target reaction threshold voltage V RTH When the stage voltage V reaches t, the electrons e at the substrate surface Sub may have enough energy to stimulate electron transitions in the corrosion layer. This is shown in FIG. 13C, where at time t, the stage voltage V S is the target reaction threshold voltage V RTH and the atoms of the surface layer L1 of the substrate Sub (i.e., the corrosion layer species) are in their respective excited states (e.g., SiH1, SiH2, or SiH3, which represent the excited states of the corrosion layer species SiH1, SiH2, or SiH3). *) is reached. In other words, FIG. 13C illustrates the initiation of the electron stimulated desorption (ESD) process used in the atomic layer etching (ALE) of the present teachings (e.g., via the arrival of a wafer-scale wavefront of electrons, the E-wave, with uniform density and energy at the substrate surface). This E-wave can be smaller than the diameter of the substrate stage and is scalable to the dimensions of the positive column. The target reaction threshold voltage V of the corrosion layer is RTH is clearly different from the threshold voltage of the non-corroded layer (e.g., L1 in FIG. 12A). RTH The V of ESD used in this specification is similar. RTH The highest V present in the corrosion layer RTH value, thus removing all species present in the corrosion layer. Note that the electron stimulation of the transition is considered to be quasi-instantaneous (e.g., a fraction of a microsecond) once the surface species comes into contact with the electron e- of the target reaction energy level.

[0086] As shown in FIG. 13D, at time t5, the stage voltage V S The target reaction threshold voltage V RTH and the ESD process results in the respective excited states (e.g., Si in Figure 13C). * ) can provide the corrosion layer species with enough kinetic energy to expel the corrosion layer species from the substrate surface Sub. This is shown in FIG. 13D as the expelled corrosion layer species (SiH X ) * 13C and 13D, the timing for executing the sequence of states of the atomic layer etching (ALE) process shown in FIGS. 13C and 13D is on the order of a fraction of a microsecond (μs), and may be less than a few microseconds. For example, as described above with reference to FIG. 7A, a periodic bias signal V(t) having a frequency of 250 KHz, and therefore a cycle T equal to 4 μs, may be used. EEMPConsidering the length of the stage voltage V S is the target reaction threshold voltage V RTH The length of the time interval t corresponding to the time when BH can be in the range of about 0.1 μs to about 0.3 μs.

[0087] FIG. 13E shows that the corrosion layer is expelled (e.g., according to FIG. 13D) and the stage voltage V S may represent the state of the atomic layer etch (ALE) process at time t6 when the stage voltage V follows (or begins to follow) the falling edge of the positive pulse. S is the target reaction threshold voltage V RTH 13E, once the corrosion layer species are exhausted, they may be converted to neutral (e.g., gas) molecules (e.g., SiH4) by the presence of atoms and / or related species of the reactive gas (e.g., H species) in the region of the DC plasma reaction chamber (110) surrounding the substrate Sub. This allows, for example, a preset flow rate of a dilution gas (e.g., argon) in the DC plasma reaction chamber (110) to remove all residues / species of the etched away corrosion layer (e.g., SiH4).

[0088] 13E may represent the final state of the DC plasma reaction chamber (110) during an active phase of atomic layer etching (ALE) according to the present disclosure. As discussed above in this disclosure, such an active phase occurs during cycle T of the bias signal V(t) discussed above, for example, with reference to FIGS. 7A / 7B / 7C. EEMP The active phase of the BPThe application of such a positive pulse can remove the corrosion layer without ion bombardment (e.g., as occurs in conventional ALE processes), but rather by an ESD mechanism initiated by the transfer of energy from low-energy electrons to excite corrosion layer species. The application of such a positive pulse can remove the corrosion layer without ion bombardment (e.g., as occurs in conventional ALE processes), but rather by an ESD mechanism initiated by the transfer of energy from low-energy electrons to excite corrosion layer species, resulting in substantially no heat generation and no (undesirable) damage to the substrate structure (e.g., lattice).

[0089] As can be seen in Figures 13A / 13B / 13C / 13D / 13E, the distribution of ion species surrounding the substrate Sub in the DC plasma reaction chamber (110) changes with increasing stage voltage V S 12B. The ion species distribution is perturbed by actively biasing the stage S at V(t). In particular, electrons e- migrate toward the surface of the substrate Sub, resulting in a distribution of ion species that can be characterized as non-homogeneous, or at least different from the steady-state (e.g., equilibrium) distribution described above with reference to FIG. 12B. To restore the steady-state distribution within the DC plasma reaction chamber (110), as shown in FIG. 13E, a negative bias signal (e.g., V(t)=V BN ) for a sufficiently long time, ΔT BN , can be applied to stage S.

[0090] 14 is a representative schematic diagram of the state of the DC plasma reaction chamber 110 at time t7 of the neutralization phase of atomic layer etching (ALE) according to the present disclosure. During such a neutralization phase, the stage S is driven by a cycle T of the bias signal V(t), e.g., as described above with reference to FIGS. 7A / 7B / 7C. EEMP Negative pulse ΔT in the neutralization phase BN The negative voltage V S =V BN Such a negative bias voltage V BNcan be used to repel electrons e from the substrate surface Sub in order to (gradually but quickly) restore a steady state distribution (of ions) within the DC plasma reaction chamber (110) in preparation for atomic etching of the next layer (e.g., L2). BN During this time, the negative bias voltage V BN It should be noted that throughout the neutralization phase defined by applying V(t), all other process parameters governing the species / plasma presence within the DC plasma reaction chamber may remain unchanged, including, for example, diluent and reactant gas inflow, anode / cathode voltage / current, and temperature, pressure, and flow rates. In other words, upon completion of the neutralization phase, the conditions within the DC plasma reaction chamber (110) may be substantially the same as those described above at time t with reference to FIG. 12B. From this, a zero bias signal (e.g., V(t)=0 V) may be applied for a sufficiently long time, ΔT, to restore the conditions for the formation of a corrosion layer on the exposed surface layer L2 of the substrate Sub, as shown in FIG. 14. BZ , the plasma floating potential V at the surface of the substrate Sub is applied to the stage S over FP can be returned to exactly the same potential (e.g., 0 V) ​​for each ALE cycle, thereby enabling precise control and reproducibility of the voltage / energy of all E-wave electrons delivered to the substrate Sub for each ALE cycle according to the present teachings.

[0091] 15 is a representative schematic diagram of the state of the DC plasma reaction chamber 110 at time t8 during the initialization phase of atomic layer etching (ALE) according to the present disclosure. During such initialization phase, the stage S is driven for cycle T of the bias signal V(t) as described above with reference to, for example, FIGS. 7A / 7B / 7C. EEMP Initialization phase ΔT BZ corresponding to zero volts, V S= 0V. Such a zero volt bias voltage may be applied long enough to allow the formation of a corrosion layer, for example, as described above with reference to Figures 12B and 12C. In other words, at the completion of the phase step, the conditions within the DC plasma reaction chamber (110) may be substantially the same as those described above with reference to Figure 12C at time t1.

[0092] Once the initialization phase is complete, the activation phase ΔT described above is performed to remove the next atomic layer (e.g., L2). BP , neutralization phase ΔT BN , and the initialization phase ΔT BZ For example, time t8 shown in FIG. 15 corresponds to the completion of the initialization phase (i.e., ΔT BZ A negative bias voltage V BN Assuming that the time has elapsed since the application of t8, the positive pulse of the active phase of the next ALE cycle occurs at any time t8 + ΔT Start can be supplied at time ΔT Start can be as small as zero. In other words, the atomic layer etching (ALE) process according to the present disclosure can be performed using, for example, the cycle T EEMP It should be noted that if, for example, a different etching performance or a different target reaction (e.g., a different reactant species and / or a different material atomic layer) is desired for etching the next layer of the substrate, the conditions within the DC reaction chamber (110) and / or the waveform of the bias signal V(t) can be changed / selected before the next ALE cycle begins. Additionally, the reaction chamber can be purged before introducing a different reactant gas. The time for such change / selection can be varied by inserting a longer initialization bias signal equal to zero volts before the start of the next EEMP cycle, or can be as short as zero (e.g., ΔT Start =0).

[0093] As shown in various figures (e.g., Figures 13-15) used to illustrate various states of a DC plasma reaction chamber (e.g., 110) during an atomic layer etching (ALE) process of a substrate (e.g., Sub) according to the present disclosure, in the positive column (e.g., G3) above the stage (e.g., S), a volume of gaseous plasma is formed having a uniform steady-state composition (including a fixed / controlled temperature) and containing ions (e.g., Ar+ and H species) and electrons (e.g., e-) with a narrow distribution of electron energies (e.g., Figures 12B / 12C).

[0094] During the activation phase of the ALE cycle (e.g., Figures 13A / 13B / 13C / 13D / 13E), when a positive bias is applied to the stage (e.g., S), electrons (e.g., e-) uniformly distributed throughout the stage are attracted / pulled to the stage surface from the volume within the DC plasma reaction chamber (e.g., 110) located above the stage. During the neutralization phase of the ALE cycle (e.g., Figure 14), when a negative bias is applied to the stage (e.g., S), electrons (e.g., e-) uniformly distributed throughout the stage are repelled from the stage surface to the volume above the stage. During the initialization phase of the ALE cycle (e.g., Figure 15), when a zero volt bias voltage is applied to the stage (e.g., S), the initial conditions described above with reference to Figure 12C are recreated within the DC plasma reaction chamber (110) adjacent to the stage. This involves the application of a floating potential V FP This involves returning the stage to an initial potential, thereby returning electrons in the plasma volume above the stage to their initial state, allowing for (precise and) consistent control of the energy of the E-wave electrons used in each ALE cycle. When such ALE cycles are repeated at a constant pace, electrons (e.g., e) arrive at well-defined intervals with uniform density and energy across the entire surface area of ​​the stage (e.g., S). Each arrival of electrons at the stage surface at these intervals (e.g., arrival times) is referred to herein as an "electron wavefront" or a precisely controlled wafer-scale wave of electrons (e.g., represented by the E-wave in FIG. 13C).

[0095] Although numerous embodiments of the present disclosure have been described, it will be understood that various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, other embodiments are within the scope of the following claims.

[0096] The foregoing examples are provided to those of ordinary skill in the art as a complete disclosure and description of how to make and use the embodiments of the present disclosure, and are not intended to limit the scope of what the inventors regard as their disclosure.

[0097] Modifications of the above-described modes for carrying out the methods and systems disclosed herein that are obvious to those skilled in the art are intended to be within the scope of the following claims. All patents and publications mentioned in this specification are indicative of the level of skill of those skilled in the art to which this disclosure pertains. All references cited in this disclosure are incorporated by reference to the same extent as if each reference were individually incorporated by reference in its entirety.

[0098] It is understood that the present disclosure is not limited to particular methods or systems, as such may vary. It is also understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting. As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural references unless the content clearly dictates otherwise. The term "plurality" includes two or more references unless the content clearly dictates otherwise. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

Claims

1. 1. A method for atomic layer etching of a substrate, comprising: generating a gaseous plasma volume containing diluent species, reactive species, and electrons of uniform steady-state composition in a positive column of a direct current plasma adjacent to the substrate, thereby generating a floating potential at the substrate surface; adjusting the floating potential to a known reference potential; forming a corrosion layer on the substrate, the corrosion layer comprising corrosion layer species formed by adsorption of reactive species onto atoms of an atomic layer on the substrate surface; applying a positive bias potential to the substrate relative to the floating potential; attracting electrons from the gaseous plasma volume to the substrate surface based on the applying step and imparting energy levels to the attracted electrons to stimulate electronic transitions of the corrosion layer species; and desorbing the corrosion layer species based on the stimulating step, thereby etching away an atomic layer; A method comprising:

2. 10. The method of claim 1, wherein the step of applying the positive bias potential is based on capacitive coupling of a positive pulse signal to the substrate support stage relative to a known reference potential; The method, wherein the positive pulse signal comprises a high voltage level equal to a reaction threshold voltage for stimulating electronic transitions of the corrosion layer species.

3. 3. The method of claim 2, wherein the duration of the high voltage level is in the range of about 0.1 μs to about 0.3 μs.

4. The method according to any one of claims 1 to 3, further comprising: applying a negative bias potential to the substrate relative to a floating potential; and applying the negative bias potential to repel electrons from the substrate surface into the volume of the gaseous plasma, thereby restoring a uniform steady-state composition; A method comprising:

5. 5. The method of claim 4, wherein the step of applying the negative bias potential immediately follows the step of applying the positive bias potential.

6. 6. The method of claim 4 or 5, wherein the duration of applying the positive bias potential is within the range of about 1 / 10 to about 1 / 1 of the duration of applying the negative bias potential.

7. 5. The method of claim 4, further comprising: generating an electron wavefront having uniform energy and density across the surface of the substrate by altering the sequence of applying the positive bias potential and the negative bias potential; and repeating said alternating sequence at a regular pace to cause said electron wavefront to impinge on the surface of said substrate at time intervals established by said regular pace, and to etch away a corresponding atomic layer of said substrate surface at each time interval; A method comprising:

8. 8. The method of claim 1, wherein the substrate comprises a first atomic layer of atoms of a first material and a second atomic layer of atoms of a second material, the first atomic layer being adjacent to and in contact with the second atomic layer; and a uniform energy of the electron wavefront at a first arrival time for etching away the first atomic layer is different from a uniform energy of the electron wavefront at a second arrival time for etching away the second atomic layer.

9. 9. The method of claim 7 or 8, further comprising: Following the step of applying the negative bias potential, the method comprises the step of applying an initialization bias potential equal to a floating potential to the substrate for a time sufficient to form another corrosion layer on the substrate.

10. 10. The method of claim 9, further comprising: The method comprises restoring a uniform steady state within the positive column based on the step of applying the initialization bias potential.

11. 11. The method of claim 9 or 10, further comprising: capacitively coupling a periodic bias signal referenced to the known reference potential to a substrate support stage; applying the positive bias potential to the substrate is performed with a positive voltage during an active phase of the periodic bias signal, the positive voltage being based on a known reaction threshold voltage for stimulating electronic transitions of the corrosion layer species; applying the negative bias potential to the substrate is performed by a negative voltage during a neutralization phase of the periodic bias signal; and the step of applying the initialization bias potential to the substrate is performed by a zero voltage of an initialization phase of the periodic bias signal; The method comprises capacitively coupling the periodic bias signal to a substrate support stage.

12. 12. The method of claim 11, wherein the positive voltage is greater than or equal to the reaction threshold voltage.

13. 12. The method of claim 11, wherein the positive voltage is strictly greater than the reaction threshold voltage for a duration in the range of 1 / 4 to 3 / 4 of the total time length of the active phase.

14. 14. The method according to any one of claims 11 to 13, wherein the negative voltage has a magnitude low enough to keep the energy level of dilution species in the volume of gaseous plasma below the reaction energy level of the corrosion layer species.

15. The method of any one of claims 11 to 14, wherein the DC component of the periodic bias signal is zero.

16. The method of any one of claims 11 to 15, wherein the frequency of the periodic bias signal is in the range of 100 KHZ to 1 MHZ.

17. 17. The method of claim 16, wherein the ratio of the length of time of the activation stage to the length of time of the neutralization phase is in the range of 1 / 10 to 1 / 1.

18. 17. The method of claim 16, A method wherein a ratio of a time length of the initialization phase to a time length of a cycle of the periodic bias signal is approximately 1 / 4.

19. 9. The method according to claim 1, wherein the atoms of the atomic layer on the substrate surface are atoms composed of one of: a) a single crystal or two-dimensional material; b) a metal; c) a composite or three-dimensional material.

20. 20. The method of claim 19, wherein the single crystal or two-dimensional material comprises a semiconductor or an insulator.

21. 21. The method of claim 20, wherein the semiconductor comprises one of Group IV silicon, germanium, Group III-V gallium arsenide, gallium nitride, silicon carbide, and indium gallium arsenide.

22. 20. The method of claim 19, wherein the single crystal or two-dimensional material comprises any one of graphene, boron nitride, molybdenum disulfide, tungsten selenide, or platinum diselenide.

23. 20. The method of claim 19, wherein the composite or three-dimensional material comprises a polymer, a composite material, or a nanomaterial.

24. 20. The method of claim 19, wherein the composite or three-dimensional material comprises any one of carbon nanotubes, nanosilver particles, titanium oxide particles, or quantum dots.

25. The method according to any one of claims 1 to 24, the diluent gas comprises any one or combination of argon, neon, or xenon; The method wherein the reactant gas comprises any one or combination of hydrogen, chlorine, methane, carbon monoxide, oxygen, or the like.

26. 26. The method of claim 25, wherein the ratio of the reactant gas to the diluent gas is in the range of about 2 / 100 to about 50 / 100.

27. 26. The method of claim 25, wherein the diluent species are argon ions and the reactive species are hydrogen species.

28. 1. A method for atomic layer etching a substrate via an electron wavefront, comprising: generating a gaseous plasma volume comprising diluent species, reactive species, and electrons of uniform steady-state composition within a positive column of a direct current plasma adjacent to the substrate, thereby generating a floating potential at the surface of the substrate; adjusting the floating potential to a reference potential; and applying to the substrate a sequence of periodic bias signals referenced to the reference potential, the periodic bias signals including a positive bias potential followed by a negative bias potential followed by a zero bias potential equal to the reference potential, thereby causing an electron wavefront to arrive with uniform energy and density across the surface of the substrate at an arrival time predetermined by the periodic bias signal; Equipped with At each arrival time, the electron wavefront stimulates electron transitions in a corrosion layer formed on the substrate surface, thereby etching one atomic layer in the substrate.

29. 30. The method of claim 28, wherein adjusting the floating potential includes adjusting a potential applied to an anode of a DC plasma chamber containing the positive column, and allowing a cathode of the DC plasma chamber to float to a constant potential based on a fixed current conducted between the anode and the cathode, the fixed current being supplied by a current source coupled to the cathode.

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