Systems and methods for controlling tilt across the surface of a substrate

Abstract

Systems and methods are described for controlling tilt across a surface of a substrate. One method includes providing a current signal to a magnetic coil coupled to a plasma chamber. The current signal generates a magnetic field within the plasma chamber. The method further includes controlling a direct current (DC) power supply to output the current signal at multiple amplitudes in a pulsed manner during a clock cycle. The method includes repeating the current signal at multiple amplitudes for each additional clock cycle.

Description

[Technical Field]

[0001] The present embodiments relate to systems and methods for controlling tilt across the surface of a substrate. [Background technology]

[0002] A plasma tool includes a radio frequency (RF) generator, a matcher, and a plasma chamber. A substrate is placed in the plasma chamber for etching. The RF generator produces an RF signal that is transmitted to the plasma chamber through the matcher. Gases are supplied to the plasma chamber, where the power of the RF signal interacts with the gases to generate a plasma within the plasma chamber. The plasma is used to process the substrate. The substrate is etched to create features in the substrate.

[0003] The background description provided herein is intended to present the contents of the present disclosure generally. Work by the presently named inventors within the scope of what is described in this Background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0004]

[0006] Embodiments of the present disclosure provide systems, apparatus, methods, and computer programs for controlling tilt across a surface of a substrate, such as a semiconductor wafer. It should be appreciated that the embodiments can be implemented in many ways, such as a process, an apparatus, a system, a device, or a method on a computer-readable medium. Some embodiments are described below.

[0005] In one embodiment, a direct current (DC) magnetic coil generates a small magnetic field of a few gauss at the semiconductor wafer to adjust the tilt near the center of the wafer. For example, a portion of the central magnetic field is vertical, adjusting the tilt near the center of the wafer. The magnetic field introduces an azimuthal tilt component on the wafer for the slit etch process. The tilt component is generated by a radial component of the magnetic field, which increases radially outward from the center of the wafer. The tilt component can be reduced, e.g., eliminated, by applying the systems and methods described herein. The systems and methods are applied to alternate variables such as the magnetic field amplitude, the magnetic field polarity, the duration the magnetic field is applied, or a combination thereof. For example, the tilt component is reduced by switching polarity every minute or so during the slit etch process. Illustratively, the polarity is switched at recipe step boundaries of about one minute in some recipes. Further illustratively, a first polarity is applied during a first recipe step, and a second polarity is applied during a second recipe step. The first polarity is opposite the second polarity. As another further example, the first polarity is applied for a shorter period of time than the period of application of the second polarity, or vice versa. As another example, each recipe step is divided into two or more sub-steps, with the polarity switching between the sub-steps. As yet another example, the polarity is switched at regular time intervals that do not necessarily coincide with any of the recipe steps.

[0006] In one embodiment, a method for controlling tilt across a surface of a substrate is described. The method includes providing a current signal to a magnetic coil coupled to a plasma chamber. The current signal generates a magnetic field within the plasma chamber. The method further includes controlling a DC power supply to output the current signal at multiple amplitudes in a pulsed manner during a clock cycle. The method includes repeating the current signal at multiple amplitudes for each additional clock cycle.

[0007] In one embodiment, a method for controlling tilt across a surface of a substrate is described. The method includes providing a current signal to a magnetic coil coupled to a plasma chamber. The current signal generates a magnetic field within the plasma chamber. The method includes controlling a DC power supply to output a current signal of multiple amplitudes in a pulsed manner during a clock cycle. The multiple amplitudes are output at the start of a process run. The method includes repeating the current signal of multiple amplitudes at the start of each additional process run.

[0008] In one embodiment, a method for controlling tilt across a surface of a substrate is described. The method includes providing a current signal to a magnetic coil coupled to a plasma chamber. The current signal generates a magnetic field within the plasma chamber. The method includes controlling a DC power supply to output multiple amplitude current signals in a pulsed manner during a clock cycle. Each of the multiple amplitudes is output during a process run. The method includes repeating the multiple amplitude current signals during each additional process run.

[0009] Some advantages of the systems and methods described herein for controlling tilt across the surface of a substrate include varying a variable of a current signal supplied to a magnetic coil coupled to a plasma chamber. The variable is varied in a pulsed manner to generate a series of amplitudes and a series of transitions from one amplitude to another in the current signal. By varying the variable, tilt across the top surface of the semiconductor wafer is controlled to reduce, e.g., eliminate, the tilt. As an example, the global tilt range across the top surface of the semiconductor wafer is reduced from a range of 71 nanometers (nm) to 87 nanometers to approximately 51 nanometers, increasing tilt symmetry across the top surface of the wafer.

[0010] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0011] The embodiments may be best understood by referring to the following description taken in conjunction with the accompanying drawings.

[0012] [Figure 1] FIG. 1 is a diagram of an embodiment of a system illustrating the use of magnetic coils to control tilt across the surface of a substrate.

[0013] [Figure 2] FIG. 2 is an embodiment of a graph showing a parameter of a process operation, such as a recipe step, during each cycle of a clock signal.

[0014] [Figure 3] FIG. 3 is an embodiment of a graph showing that the amplitude or polarity, or a combination thereof, of the current signal is periodically changed.

[0015] [Figure 4] FIG. 4 is an embodiment of a graph showing that the amplitude, or polarity, or a combination thereof, of the current signal is changed at the end or start of each process operation.

[0016] [Figure 5] FIG. 5 is an embodiment of a graph showing that the amplitude, or polarity, or a combination thereof, of the current signal is changed during each process operation.

[0017] [Figure 6A] FIG. 6A is a graph embodiment illustrating another scheme in which the amplitude or polarity, or a combination thereof, of the current signal is periodically changed.

[0018] [Figure 6B] FIG. 6B is a graph embodiment illustrating yet another scheme in which the amplitude or polarity, or a combination thereof, of the current signal is periodically changed.

[0019] [Figure 6C]FIG. 6C is a graph embodiment illustrating yet another scheme in which the amplitude or polarity, or a combination thereof, of the current signal is periodically changed.

[0020] [Figure 6D] FIG. 6D is a graph embodiment illustrating another scheme in which the amplitude or polarity, or a combination thereof, of the current signal is periodically changed.

[0021] [Figure 6E] FIG. 6E is a graph embodiment illustrating yet another scheme in which the amplitude, or polarity, or a combination thereof, of the current signal is periodically changed.

[0022] [Figure 6F] FIG. 6F is a graph embodiment illustrating yet another scheme in which the amplitude, or polarity, or a combination thereof, of the current signal is periodically changed.

[0023] [Figure 7] FIG. 7 is a diagram of an embodiment of a system showing a direct current (DC) power supply for generating a current amplitude signal.

[0024] [Figure 8] FIG. 8 is a diagram of an embodiment of the system showing the polarity change circuitry. DETAILED DESCRIPTION OF THE INVENTION

[0025] In the following embodiments, systems and methods for controlling tilt across a surface of a substrate are described. It will be apparent that the present embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order to not unnecessarily obscure the present embodiments.

[0026] 1 is a diagram of an embodiment of a system 100 illustrating the use of a magnetic coil 102 to control tilt across the surface of a substrate S. The system 100 includes a host computer 104, a direct current (DC) power supply 106, a radio frequency (RF) generator (RFG) 108, an impedance matching circuit (IMC) 110, and a plasma chamber 112. The host computer 104 includes a processor system 114 and a memory device system 118. The DC power supply 106 also includes a DC power supply 120 and a polarity change circuit 122. The plasma chamber 112 includes an upper electrode 124 and a substrate support pedestal 126. The system 100 further includes a driver system 132, a motor system 134, a process gas supply 136, and a valve system 138.

[0027] Examples of host computers used herein include desktop computers, controllers, laptop computers, tablets, and smartphones. An example of the DC power supply 120 is a string of cells, such as a string of batteries. An example of the polarity change circuit 122 is described below with reference to FIG. 8. The processor system 114 includes one or more processors, and the memory device system 118 includes one or more memory devices. By way of example, the processor is an application specific integrated circuit (ASIC), a central processing unit (CPU), a field programmable gate array (FPGA), a microprocessor, a programmable logic device (PLD), an integrated controller, or a microcontroller. Examples of memory devices used herein include read-only memory (ROM) and random access memory (RAM). Illustratively, the memory device is flash memory or a redundant array of independent disks (RAID).

[0028] As an example, the magnetic coil 102 is a coil having one or more turns. For example, the magnetic coil 102 is different from a transformer-coupled plasma (TCP) coil. For example, the magnetic coil 102 has multiple turns of copper wire, while a TCP coil is a solid piece of copper. As another example, the magnetic coil 102 is not a TCP coil. The magnetic coil 102 has a terminal 102A and another terminal 102B. After traversing some of the turns from terminal 102A, terminal 102B is reached. For example, the magnetic coil 102 is made of a metal such as copper. For further example, the magnetic coil 102 does not promote plasma generation in the plasma chamber 112. An example of the substrate support pedestal 126 is an electrostatic chuck (ESC), and an example of the substrate S is a semiconductor wafer. For example, the substrate support pedestal 126 has a lower electrode embedded therein. An example of the plasma chamber 112 is a capacitively coupled plasma (CCP) chamber. The plasma chamber 112 includes a top wall TW, a side wall SW, and a bottom wall BW. The top wall TW is fitted to the side wall SW, and the side wall SW is fitted to the bottom wall BW. The top wall TW is disposed above the bottom wall BW.

[0029] Also, by way of example, the RF generator 108 is an RF generator operating at a frequency of 100 kilohertz (kHz), an RF generator operating at a frequency of 400 kHz, an RF generator operating at a frequency of 2 megahertz (MHz), an RF generator operating at a frequency of 27 MHz, or an RF generator operating at a frequency of 60 MHz. An example of the impedance matching circuit 110 is an impedance matching network, a matcher, or a matching circuit. Illustratively, the impedance matching circuit 110 includes a network of electronic components, such as capacitors and inductors, connected to each other. Further illustratively, the impedance matching circuit 110 includes one or more series electronic components, one or more shunt electronic components, or a combination thereof.

[0030] An example of the driver system 132 includes one or more drivers, such as one or more transistors. Additionally, an example of the motor system 134 includes one or more electric motors. An example of the process gas supply 136 is one or more containers for storing one or more process gases, such as an oxygen-containing gas, a nitrogen-containing gas, and a fluorine-containing gas. An example of the valve system 138 includes one or more valves. Illustratively, each valve is connected to a corresponding one of the containers in the process gas supply 136.

[0031] The processor system 114 is connected to a memory device system 118, a DC power supply 120, and a polarity change circuit 122. The DC power supply 120 is further connected to the polarity change circuit 122, which is connected to the magnetic coil 102. The magnetic coil 102 is coupled to the plasma chamber 112. For example, the magnetic coil 102 is disposed above the top wall TW and outside the plasma chamber 112. Also illustratively, a plane passing through the turns of the magnetic coil 102 is along the top wall TW, e.g., substantially parallel to the top wall TW. Further illustratively, a plane passing through the magnetic coil 102 is parallel to the top wall TW. The upper electrode 124 is disposed above the substrate support pedestal 126 and below the top wall TW.

[0032] The processor system 114 is connected to an RF generator 108. The RF generator 108 is connected to an impedance matching circuit 110 via an RF cable 128, and the impedance matching circuit is connected to a lower electrode of a substrate support pedestal 126 via an RF transmission line 130. A substrate S is placed on the upper surface of the substrate support pedestal 126.

[0033] The processor system 114 is connected to a driver system 132, which is connected to a motor system 134. For example, each driver of the driver system 132 is connected to a respective electric motor of the motor system 134. The motor system 134 is also connected to a valve system 138. For example, each electric motor is connected to a respective valve of the valve system 138. The valve system 138 is connected to a gap 142 between the upper electrode 124 and the substrate support pedestal 126 via a gas supply line 140 and the upper electrode 124. The gap 142 is formed in the plasma chamber 112, and the substrate S is disposed in the gap 142.

[0034] The processor system 114 generates a recipe signal 142 and transmits the recipe signal 142 to the RF generator 108. As an example, the recipe signal 142 includes one or more power levels. Each power level is an amount of power supplied by the RF generator 108. After receiving the recipe signal 142, in response to receiving a trigger signal 143 from the processor system 114, the RF generator 108 generates an RF signal 144 based on the recipe signal 142. For example, the RF signal 144 has one or more power levels. The RF generator 108 transmits the RF signal 144 to the impedance matching circuit 110 via the RF cable 128.

[0035] Upon receiving the RF signal 144, the impedance matching circuit 110 modifies the impedance of the RF signal 144 by matching the impedance of a load connected to the output of the impedance matching circuit 110 with the impedance of a source connected to the input of the impedance matching circuit 110. Examples of loads include the RF transmission line 130 and the plasma chamber 112, and examples of sources include the RF cable 128 and the RF generator 108. The impedance of the RF signal 144 is modified to output a modified RF signal 146. The modified RF signal 146 is transmitted from the output of the impedance matching circuit 110 to the lower electrode of the substrate support pedestal 126.

[0036] Also, while the modified RF signal 146 is being provided, the processor system 114 sends a control signal to the driver system 132. Upon receiving the control signal, each driver of the driver system 132 generates a respective current signal and provides the respective current signal to a respective electric motor. Upon receiving the current signal, the electric motor rotates and operates (e.g., opens, closes, or partially opens) a respective valve of the valve system 138 to control the supply of a respective process gas from the process gas supply 130 to the gap 142 via the valve, the gas supply line 140, and the upper electrode 124. For example, when a valve is open or partially open, process gas is supplied from the process gas supply 136 to the gap 142. On the other hand, when the valve is closed, the supply of process gas from the process gas supply 136 to the gap 142 is cut off.

[0037] When one or more process gases are supplied to the plasma chamber 112 along with the modified RF signal 146, a plasma is generated or maintained in the gap 142 to process the substrate S. Examples of processing the substrate S include depositing material on the substrate S, etching to create features such as channels or trenches in the substrate S, and cleaning the substrate S. Each feature has a slope. For example, the sidewalls of each feature are sloped and not vertical. For example, the surface of the sidewall forms an acute angle with respect to vertical. For another example, an acute angle with respect to vertical is formed by a line connecting the center of the top surface of the feature, which has an opening, to the center of the bottom wall of the feature. The sidewalls of the feature are adjacent to the bottom wall, and the top surface is adjacent to the sidewall. The top surface is also above the bottom wall.

[0038] Furthermore, during the period when one or more process gases are supplied to the plasma chamber 112 in addition to the modified RF signal 146, the processor system 114 generates and sends one or more control signals 148, such as one or more on control signals, one or more off control signals, or a combination thereof, to the DC power supply 120 and sends one or more position control signals 150 to the polarity circuit 122. As an example, the one or more control signals 148 are generated based on one or more amplitudes of one or more current values ​​of a current signal 152 output from the DC power supply 106 and one or more durations of each of the one or more amplitudes of the current signal 152. Illustratively, each amplitude of the current value is represented as an amplitude level. In this example, the one or more position control signals 150 are generated based on one or more polarities, such as positive or negative, of the one or more amplitudes of the current signal 152.

[0039] Additionally, upon receiving one or more control signals 148 and one or more position control signals 150 during a period in which one or more process gases are supplied to the plasma chamber 112 in addition to the modified RF signal 146, the DC power supply 106 generates a current signal 152 having one or more amplitudes, one or more durations of the one or more amplitudes, and one or more polarities of the one or more amplitudes. The current signal 152 is transmitted from the DC power supply 106 to the magnetic coil 102. As the current signal 152 passes through the magnetic coil, for example, from terminal 102A to terminal 102B or from terminal 102B to terminal 102A, a magnetic field is generated in the gap 142.

[0040] The magnetic field alters the slope of features of the substrate S. For example, the slope of features across the top surface of the substrate S may be altered to be symmetrical. As another example, the slope may be altered to be zero or to decrease from zero to within a predetermined threshold.

[0041] In one embodiment, rather than magnetic coil 102 having turns, a separate magnetic coil having two or more turns is used.

[0042] In one embodiment, two or more magnetic coils are used in the system 100 .

[0043] In one embodiment, the magnetic coil 102 is disposed within the plasma chamber 112 such that the magnetic coil 102 is coupled to the plasma chamber 112. For example, the magnetic coil 102 is mounted on a pedestal (not shown) to which an upper electrode is fixed. The upper electrode is disposed below the pedestal.

[0044] FIG. 2 illustrates an embodiment of a graph 200 illustrating parameters of multiple process operations during each cycle of a clock signal, such as a digital pulse signal. The clock signal is generated by the processor system 114 (FIG. 1) to have multiple clock cycles, such as clock cycle 1, clock cycle 2, etc. For example, the processor system 114 includes a clock oscillator that generates the clock signal. Example parameters include the chemistry of one or more process gases and the power level of the RF signal 144 (FIG. 1). By way of example, the chemistry may include one process gas or a mixture of two or more process gases. By way of example, chemical m may be different from chemical (m+1), where m is zero or a positive integer. By way of further example, chemical m may include an oxygen-containing gas and chemical (m+1) may include a nitrogen-containing gas. By way of further example, chemical m may include a first mixture of two or more process gases, and chemical (m+1) may include a second mixture of two or more process gases. At least one of the process gases in the first mixture may be different from at least one of the process gases in the second mixture.

[0045] As an example, power level (m+1) is not equal to power level m, where m is a positive integer. For example, power level 2 is greater than or less than power level 1, and power level 3 is greater than or less than each of power levels 1 and 2. As an example, each power level includes a statistical power quantity, such as an average or median value, of multiple power quantities. Also, as an example, all power quantities at power level m do not include all power quantities at power level (m+1). For example, a first power level includes a first statistical power quantity of a first group of power quantities, and a second power level includes a second statistical power quantity of a second group of power quantities. Because the second power level is greater than the first power level, the maximum value of the first group is less than the minimum value of the second group.

[0046] Graph 200 plots the parameter on the y-axis and time t on the x-axis. Time t ranges from time t0 to time t32. The range from time t0 to time t32 includes time t1, time t2, time t3, time t4, ..., up to time t32. Note that the time interval between any two consecutive times is equal. For example, the time interval between time t0 and time t1 is equal to the time interval between time t1 and time t2. Also, by way of example, the period between time t0 and time t4 is one minute, the period between time t4 and time t8 is one minute, and so on.

[0047] During the time interval between times t0 and t4, the processor system 114 controls the valve system 138 (FIG. 1) to provide one or more process gas chemistry 1 via the gas supply line 140 (FIG. 1) to the gap 142 (FIG. 1), or controls the RF generator 108 to generate a power level 1 of the RF signal 144, or a combination thereof, to perform a first process operation. An example of a first process operation is recipe step 1. Illustratively, during the first process operation, the substrate S is processed with a first method, such as etching. Similarly, during the time interval between times t4 and t8, the processor system 114 controls the valve system 138 to provide one or more process gas chemistry 2 via the gas supply line 140 to the gap 142, or controls the RF generator 108 to generate a power level 2 of the RF signal 144, or a combination thereof, to perform a second process operation. An example of a second process operation is recipe step 2. Illustratively, during the second process operation, material is deposited on the substrate S or the substrate S is further etched to process the substrate S in a second manner. Also, during the time interval between times t8 and t12, the processor system 114 controls the valve system 138 to provide one or more process gas chemistry 3 to the gap 142 via the gas supply line 140, or controls the RF generator 108 to generate a power level 3 of the RF signal 144, or a combination thereof to perform a third process operation. Illustratively, during the third process operation, the substrate S is again etched. An example of a third process operation is recipe step 3. During the time interval between times t12 and t16, the processor system 114 controls the valve system 138 to provide one or more process gas chemistry 4 to the gap 142 via the gas supply line 140, or controls the RF generator 108 to generate a power level 4 of the RF signal 144, or a combination thereof to perform a fourth process operation. An example of a fourth process operation is recipe step 4. Illustratively, during the fourth process operation, another material is deposited on the substrate S or the substrate S is further etched. The time interval from time t0 to time t16 is during clock cycle 1.Similarly, during clock cycle 2, which includes the time interval from time t16 to time t32, processor system 114 controls valve system 138 to repeatedly apply chemicals 1-4 and controls RF generator 108 to generate power levels 1-4.

[0048] In clock cycle 1, recipe step 1 starts at time t0 and ends at time t4. Recipe step 2 starts at time t4 and ends at time t8. Recipe step 3 starts at time t8 and ends at time t12, and recipe step 4 starts at time t12 and ends at time t16. Similarly, in clock cycle 2, recipe steps 1 through 4 are repeated.

[0049] In one embodiment, rather than applying a different chemical during each time interval t0-t4, t4-t8, t8-t12, and t12-t16, the same chemical is applied during two or more time intervals. For example, chemical 1 is applied during the time interval from time t0 to time 8.

[0050] In one embodiment, rather than applying unequal power levels during each of the time intervals t0-t4, t4-t8, t8-t12, and t12-t16, equal power levels are applied during two or more of the time intervals. For example, power level 1 is applied during the time interval from time t0 to time t8.

[0051] 3 is an embodiment of a graph 300 illustrating that the amplitude, polarity, or duration, or a combination thereof, of a current signal 302 is periodically changed. The current signal 302 is an example of the current signal 152 (FIG. 1). The graph 300 plots the current signal 302 on the y-axis and time t on the x-axis. The current signal 302 ranges from a current value −Id to a current value I4. For example, the current value −Id of the current signal 302 is less than the current value −Ic of the current signal 302, which is less than the current value −Ib of the current signal 302, which is less than the current value −Ia of the current signal 302. The current value −Ia is less than the current value 0 of the current signal 302. Furthermore, in this example, the amplitude 0 of current signal 302 is smaller than the amplitude of current value I1 of current signal 302, which is smaller than the amplitude of current value I2 of current signal 302, which is smaller than the amplitude of current value I3 of current signal 302. The amplitude of current value I3 is smaller than the amplitude of current value I4 of current signal 302.

[0052] Each current value described herein has an amplitude, a polarity, and a duration. For example, current value -Id has an amplitude of Id, current value -Ic has an amplitude of Ic, current value -Ib has an amplitude of Ib, and current value -Ia has an amplitude of Ia. Also, in this example, current values ​​-Ia to -Id have negative polarities. For example, current values ​​-Ia to -Id are represented by negative values. In this example, current values ​​I1 to I4 have positive polarities. For example, current values ​​I1 to I4 are positive values. As another example, a portion of current signal 302 having any current value greater than zero flows in the opposite direction to a portion of current signal 302 having any current value less than zero. To further illustrate, a portion of current signal 302 having any positive current value flows from terminal 102A (FIG. 1) to terminal 102B (FIG. 1), and a portion of current signal 302 having any negative current value flows from terminal 102B to positive terminal 102A. Furthermore, in this example, current value -Id has a duration that includes the period from time t0 to time t2.5, current value -Ib has a duration that includes the period from time t2.5 to time t5, current value I4 has a duration that includes the period from time t5 to time t7.5, and current value I2 has a duration that includes the period from time t7.5 to time t10. Time t2.5 is between times t2 and t3, and time t7.5 is between times t7 and t8.

[0053] 2 , the processor system 114 (FIG. 1) controls the DC power supply 106 to output current values ​​−Id, −Ib, I2, and I4 in a pulsed manner by varying the amplitude, polarity, or duration, or a combination thereof, of the current signal 302 at predetermined time intervals, e.g., periodically, regularly, or repeatedly. For example, the current signal 302 has a current value −Id from time t0 to time t2.5. Thereafter, the current signal 302 transitions from the current value −Id to a current value −Ib at time t2.5 and maintains the current value −Ib from time t2.5 to time t5. Furthermore, the current signal 302 transitions from the current value −Ib to a current value I2 at time t5 and maintains the current value I2 from time t5 to time t7.5. At time t5, the processor system 114 controls the DC power supply 116 to change the polarity of the current signal 302 from negative to positive and change the amplitude of the current signal 302 from Ib to I2. At time t7.5, the current signal 302 transitions from the current value I2 to the current value I4 and maintains the current value I4 from time t7.5 to time t10. The period between time t0 and time t2.5 is equal to the period between time t2.5 and time t5, the period between time t5 and time t7.5, and the period between time t7.5 and time t10, and the amplitude of the current signal 302 is changed at each predetermined time interval.

[0054] Similarly, during the period between times t10 and t20, regardless of the clock cycles of the clock signal, the processor system 114 controls the DC power supply 106 to repeatedly change the amplitude, polarity, or duration, or a combination thereof, of the current signal 302 in a manner similar to the way the amplitude, polarity, or duration, or a combination thereof, of the current signal 302 is changed between times t0 and t10. By way of example, the period between times t0 and t10 and the period between times t10 and t20 may be referred to herein as a repeating period. Note that each amplitude -Id, -Ib, I2, and I4 of the current signal 302 is represented as a horizontal level, and the transition between any two adjacent amplitudes -Id, -Ib, I2, and I4 is represented vertically. By way of example, each horizontal level described herein has a slope of zero, and the vertical direction has a slope of infinity.

[0055] 3 have one or more durations that are different from one or more remaining durations of one or more of the remaining current values ​​of current signal 302. For example, processor system 114 controls DC power supply 106 to have current value −Id for a longer or shorter period than the period during which DC power supply 106 is controlled to have current value −Ib. Note that the sum of the durations of current values ​​−Id, −Ib, I2, and I4 equals 100 percent of each repeat period.

[0056] In one embodiment, during each repetition period, one or more of the amplitudes of the current values ​​of current signal 302 shown in Figure 3 are different, such as greater or less than, one or more of the remaining amplitudes of current signal 302. For example, during the period between times t0 and t2.5, current signal 302 has amplitude Ia and negative polarity rather than amplitude Id and negative polarity.

[0057] 3 has a different polarity than one or more of the polarities of one or more of the remaining current values ​​of current signal 302. For example, during the period between times t0 and t2.5, current signal 302 has an amplitude I4 and a positive polarity rather than an amplitude Id and a negative polarity.

[0058] 4 is an embodiment of a graph 400 illustrating that the amplitude, polarity, or duration, or a combination thereof, of a current signal 402 is changed at the end or beginning of each process operation. Current signal 402 is an example of current signal 152 (FIG. 1). Graph 400 plots the current value of current signal 402 on the y-axis and time t on the x-axis.

[0059] During clock cycle 1, the processor system 114 (FIG. 1) controls the DC power supply 106 to change the amplitude, polarity, or duration, or a combination thereof, of the current signal 402 at the end of each process operation to output current values ​​−Id, −Ib, I2, and I4 in a pulsed manner. For example, the current signal 402 has a current value −Id from time t0 to time t4, at which time process step 1 (FIG. 2) completes and process step 2 (FIG. 2) begins. The current signal 402 then transitions from the current value −Id to a current value −Ib at time t4 and maintains the current value −Ib from time t4 to time t8, at which time process step 2 completes and process step 3 (FIG. 2) begins. The current signal 402 transitions from a current value −Ib to a current value I2 at time t8, and also transitions from negative polarity to positive polarity at time t8, maintaining the amplitude I2 from time t8 to time t12. At time t8, the processor system 114 controls the DC power supply 116 to change the polarity of the current signal 402 from negative to positive. At time t12, process step 3 is completed and process step 4 ( FIG. 2 ) begins. Furthermore, the current signal 402 transitions from a current value I2 to a current value I4 at time t12 and maintains the current value I4 from time t12 to time t16. At time t16, process step 4 is completed and process step 1 of clock cycle 2 begins. During cycle 2, the processor system 114 controls the DC power supply 106 to change the amplitude, polarity, or duration, or combination thereof, of the current signal 402 in a manner similar to the way the amplitude, polarity, or duration, or combination thereof, of the current signal 402 is changed during cycle 1. Note that each amplitude -Id, -Ib, I2, and I4 of the current signal 402 is represented as a horizontal level, and the transition between any two adjacent amplitudes -Id, -Ib, I2, and I4 is represented vertically.

[0060] 4 have one or more durations that are different from one or more remaining durations of one or more of the remaining current values ​​of current signal 402. For example, processor system 114 controls DC power supply 106 to have current value −Id for a longer or shorter period than the period during which DC power supply 106 is controlled to have current value −Ib. Note that the sum of the durations of current values ​​−Id, −Ib, I2, and I4 equals 100 percent of each period of clock cycles 1 and 2.

[0061] 4 is different, such as greater than or less than, one or more of the remaining amplitudes of current signal 402. For example, during the period between times t0 and t4, current signal 402 has amplitude Ia and negative polarity rather than amplitude Id and negative polarity.

[0062] 4 has a polarity that is different from one or more of the polarities of one or more of the remaining current values ​​of current signal 402. For example, during the period between times t0 and t4, current signal 402 has a positive polarity amplitude I4 rather than a negative polarity amplitude Id.

[0063] 5 is an embodiment of a graph 500 illustrating that the amplitude, polarity, or duration, or a combination thereof, of a current signal 502 is changed during each process operation. The current signal 502 is an example of the current signal 152 (FIG. 1). The graph 500 plots the current value of the current signal 502 on the y-axis and time t on the x-axis.

[0064] During clock cycle 1, the processor system 114 (FIG. 1) controls the DC power supply 106 to vary the amplitude, polarity, or duration, or a combination thereof, of the current signal 502 during each process operation to output current values ​​−Id, −Ic, −Ib, −Ia, I4, I3, I2, and I1 in a pulsed manner. For example, the current signal 502 has a current value −Id from time t0 to time t2. At time t2, process step 1 (FIG. 2) is in progress. The current signal 502 then transitions from the current value −Id to a current value −Ic at time t2 and maintains the current value −Ic from time t2 to time t4. The current signal 502 transitions from the current value −Ic to a current value −Ib at time t4 and maintains the current value −Ib from time t4 to time t6. At time t6, process step 2 (FIG. 2) is in progress. Furthermore, the current signal 502 transitions from a current value −Ib to a current value −Ia at time t6 and maintains the current value −Ia from time t6 to time t8. At time t8, the processor system 114 controls the DC power supply 116 to change the polarity of the current signal 502 from negative to positive and transition the amplitude from Ia to I4.

[0065] The current signal 502 maintains a current value I4 from time t8 to time t10, transitioning from the current value I4 to a current value I3 at time t10. At time t10, process step 3 is in progress. Thereafter, the current signal 502 maintains a current value I3 from time t10 to time t12, transitioning from the current value I3 to a current value I2 at time t12. The current signal 502 maintains a current value I2 from time t12 to time t14, transitioning from the current value I2 to a current value I1 at time t14. At time t14, process step 4 is in progress. The current signal 502 maintains a current value I1 from time t14 to time t16, transitioning from the current value I1 to a current value −Id at time t16. At time t16, the processor system 114 controls the DC power supply 116 to change the polarity of the current signal 502 from positive to negative. During cycle 2, the processor system 114 controls the DC power supply 106 to change the amplitude, polarity, or duration, or a combination thereof, of the current signal 502 in a manner similar to the way the amplitude, polarity, or a combination thereof of the current signal 502 is changed during cycle 1. Note that each amplitude -Id, -Ic, -Ib, -Ia, I4, I3, I2, and I1 of the current signal 502 is represented as a horizontal level, and the transition between any two adjacent ones of the amplitudes -Id, -Ic, -Ib, -Ia, I4, I3, I2, and I1 is represented vertically.

[0066] 5 have one or more durations that are different from one or more remaining durations of one or more of the remaining current values ​​of current signal 502. For example, processor system 114 controls DC power supply 106 to have current value −Id for a period that is longer or shorter than the period during which DC power supply 106 is controlled to have current value −Ic. Note that the sum of the durations of current values ​​−Id, −Ic, −Ib, −Ia, I4, I3, I2, and I1 equals 100 percent of each period of clock cycles 1 and 2.

[0067] 5 is different, such as greater than or less than, one or more of the remaining amplitudes of current signal 502. For example, during the period between times t0 and t2, current signal 502 has amplitude Ia and negative polarity rather than amplitude Id and negative polarity.

[0068] 5 has a different polarity than one or more of the remaining amplitudes of current signal 502. For example, during the period between times t0 and t2, current signal 502 has an amplitude I4 instead of amplitude Id and a positive polarity instead of a negative polarity.

[0069] 6A is an embodiment of a graph 600 illustrating another manner in which the amplitude, polarity, or duration, or a combination thereof, of a current signal 602 is periodically varied. The current signal 602 is an example of the current signal 152 (FIG. 1). The graph 600 plots the current signal 602 on the y-axis and time t on the x-axis.

[0070] 2 , processor system 114 (FIG. 1) controls DC power supply 106 to output current values ​​−Id, I4, −Ib, and I2 in a pulsed manner by varying the amplitude, polarity, or duration, or a combination thereof, of current signal 602 at predetermined time intervals, e.g., periodically, regularly, or repeatedly. For example, current signal 602 has a current value −Id from time t0 to time t2.5. Thereafter, current signal 602 transitions from the current value −Id to a current value I4 at time t2.5 and maintains the current value I4 from time t2.5 to time t5. Current signal 602 transitions from the current value I4 to a current value −Ib at time t5 and maintains the current value −Ib from time t5 to time t7.5. Furthermore, current signal 602 transitions from a current value −Ib to a current value I2 at time t7.5 and maintains the current value I2 from time t7.5 to time t10. At time t10, processor system 114 controls DC power supply 116 to change the polarity of current signal 602 from positive to negative and to change the amplitude of current signal 602 from I2 to Id. Similarly, during the period between times t10 and t20, regardless of the clock cycles of the clock signal, processor system 114 controls DC power supply 106 to change the amplitude, polarity, or duration, or a combination thereof, of current signal 602 in a manner similar to the manner in which the amplitude, polarity, or duration, or a combination thereof, of current signal 602 is changed between times t0 and t10, repeatedly controlling DC power supply 106 in each repeating period. It should be noted that each amplitude -Id, I4, -Ib, and I2 of the current signal 602 is represented as a horizontal level, and the transition between any two adjacent amplitudes -Id, I4, -Ib, and I2 is represented vertically.

[0071] 6A have one or more durations that are different from one or more remaining durations of one or more of the remaining current values ​​of current signal 602. For example, processor system 114 controls DC power supply 106 to have current value −Id for a longer or shorter period than the period during which DC power supply 106 is controlled to have current value I4. Note that the sum of the durations of current values ​​−Id, I4, −Ib, and I2 equals 100 percent of each repeat period.

[0072] In one embodiment, during each repetition period, one or more of the amplitudes of the current values ​​of current signal 602 shown in Figure 6A are different, such as greater or less than, one or more of the remaining amplitudes of current signal 602. For example, during the period between times t0 and t2.5, current signal 602 has amplitude Ia and negative polarity, rather than amplitude Id and negative polarity.

[0073] In one embodiment, during each repeat period, one or more of the current values ​​of current signal 602 shown in FIG. 6A has a different polarity than one or more remaining polarities of one or more of the remaining current values ​​of current signal 602. For example, during the period between times t0 and t2.5, current signal 602 has an amplitude I3 and a positive polarity rather than an amplitude Id and a negative polarity.

[0074] In one embodiment, during each clock cycle of the clock signal, one or more of the current values ​​of current signal 602 have one or more durations that are different from those shown in Figure 6A, with each different duration being consistent with a corresponding process operation in Figure 2. For example, processor system 114 controls DC power supply 106 to have a current value -Id during a period from time t0 to time t4, a current value I4 from time t4 to time t8, a current value -Ib from time t8 to time t12, and a current value I2 from time t12 to time t16. In this example, processor system 114 controls DC power supply 106 to have current values ​​-Id, I4, -Ib, and I2 during each additional cycle, such as cycle 2, of the clock signal, in a manner similar to how processor system 114 controls DC power supply 106 to have current values ​​-Id, I4, -Ib, and I2 during cycle 1. Note that the sum of the durations of current values ​​-Id, I4, -Ib, and I2 is equal to 100 percent of each clock cycle period of the clock signal.

[0075] 6A , to achieve different durations during each process operation. For example, the processor system 114 controls the DC power supply 106 to have a current value of −Id from time t0 to time t2, a current value of I4 from time t2 to time t4, a current value of −Ib from time t4 to time t6, and a current value of I2 from time t6 to time t8. Furthermore, in this example, the processor system 114 controls the DC power supply 106 to have a current value of −Id from time t8 to time t10, a current value of I4 from time t10 to time t12, a current value of −Ib from time t12 to time t614, and a current value of I2 from time t14 to time t16. In this example, the processor system 114 controls the DC power supply 106 to have current values ​​−Id, I4, −Ib, and I2 during each additional cycle, such as cycle 2, of the clock signal in a similar manner as the processor system 114 controls the DC power supply 106 to have current values ​​−Id, I4, −Ib, and I2 during cycle 1. Note that the sum of the durations of the current values ​​−Id, I4, −Ib, and I2 equals 100 percent of each clock cycle period of the clock signal.

[0076] 6B is an embodiment of a graph 610 illustrating another manner in which the amplitude, polarity, or duration, or a combination thereof, of a current signal 612 is periodically changed. There is a linear gradient transition between two adjacent polarities or two adjacent amplitudes of the current signal 612. The current signal 612 is an example of the current signal 152 (FIG. 1). The graph 610 plots the current signal 612 on the y-axis and time t on the x-axis.

[0077] 2 , processor system 114 (FIG. 1) controls DC power supply 106 to output current values ​​−Id, −Ib, I2, and I4 in a pulsed manner by varying the amplitude, polarity, or duration, or a combination thereof, of current signal 612 at predetermined time intervals, e.g., periodically or periodically. For example, current signal 612 has a current value −Id from time t0 to time t2. Current signal 612 then transitions from the current value −Id to a current value −Ib during the time period from time t2 to time t2.5, and maintains the current value −Ib from time t2.5 to time t4.5, which is between times t4 and t5. Current signal 612 transitions from the current value −Ib to a current value I2 during the time period from time t4.5 to time t5, and maintains the current value I2 from time t5 to time t7. Furthermore, current signal 612 transitions from current value I2 to current value I4 during the period from time t7 to time t7.5 and maintains current value I4 from time t7.5 to time t9.5, which is between times t9 and t10. During the period between times t9.5 and t10, processor system 114 controls DC power supply 116 to change the polarity of current signal 612 from positive to negative and change the amplitude of current signal 612 from I4 to Id. Similarly, during the period between times t10 and t20, independent of clock cycles of the clock signal, processor system 114 controls DC power supply 106 to change the amplitude, or polarity, or combination thereof, of current signal 612 in a manner similar to how the amplitude, polarity, or combination thereof of current signal 612 is changed between times t0 and t10, repeatedly controlling DC power supply 106 for each predetermined time interval.

[0078] Note that each slope transition of current signal 612 from one current value to the next, such as from the immediately following current value, is linear and has a positive or negative slope. For example, the slope transition between current values ​​-Id and -Ib from time t2 to time t2.5 has a positive slope, and the slope transition between current values ​​I4 and -Id from time t9.5 to time t10 has a negative slope. Note that each amplitude -Id, -Ib, I2, and I4 of current signal 702 is represented as a horizontal level.

[0079] In one embodiment, during each repeating period, one or more of the current values ​​of the current signal 612 shown in FIG. 6B have one or more durations that are different from one or more remaining durations of one or more of the remaining current values ​​of the current signal 612. For example, the processor system 114 controls the DC power supply 106 to have the current value −Id for a longer or shorter period than the period during which the DC power supply 106 is controlled to have the current value I4. In this example, the processor system 114 controls the DC power supply 106 to have the current value −Id for a longer or shorter period to change the transition period from the current value −Id to the current value −Ib. In this example, the duration of the current value −Id includes a longer or shorter period and a changed transition period. As another example, the processor system 114 controls the DC power supply 106 to change the transition period from the current value −Id to the current value −Ib. Changing the transition period changes the period during which the current value −Id is maintained. In this example, the duration of the current value −Id includes a changed period and a changed transition period. As yet another example, the processor system 114 controls the DC power supply 106 to have a current value I4 during cycle 1 for a longer or shorter period of time than the period during which the DC power supply 106 is controlled to have a current value −Id during cycle 2. In this example, the processor system 114 controls the DC power supply 106 to have the current value I4 for a longer or shorter period of time to change the transition period from the current value I4 in cycle 1 to the current value −Id in cycle 2. In this example, the duration of the current value I4 includes the longer or shorter period and the changed transition period. As yet another example, the processor system 114 controls the DC power supply 106 to change the transition period from the current value I4 in cycle 1 to the current value −Id in cycle 2. Changing the transition period changes the period during which the current value I4 is maintained in cycle 1. In this example, the duration of the current value I4 includes the changed period of time and the changed transition period. Note that the sum of the durations of current values ​​-Id, -Ib, I2, and I4 equals 100 percent of each repetition period.

[0080] In one embodiment, during each repeat period, one or more of the amplitudes of the current values ​​of current signal 612 shown in FIG. 6B are different, such as greater or less than, one or more of the remaining amplitudes of current signal 612. For example, during the period between times t0 and t2, current signal 612 has amplitude Ia and negative polarity, rather than amplitude Id and negative polarity.

[0081] 6 has a different polarity than one or more of the remaining polarities of one or more of the remaining current values ​​of current signal 612. For example, during the period between times t0 and t2, current signal 612 has an amplitude I3 and a positive polarity rather than an amplitude Id and a negative polarity.

[0082] In one embodiment, during each clock cycle of the clock signal, one or more of the current values ​​of current signal 612 have one or more durations different from those shown in Figure 6B, with each different duration being consistent with a corresponding process operation in Figure 2. For example, processor system 114 controls DC power supply 106 to have a current value of -Id from time t0 to time t3.5, to transition between current values ​​-Id and -Ib from time t3.5 to time t4, to have a current value of -Ib from time t4 to time t7.5, to transition between current values ​​-Ib and I2 from time t7.5 to time t8, to have a current value of I2 from time t8 to time t11.5, to transition between current values ​​I2 and I4 from time t11.5 to time t12, to have a current value I4 from time t12 to time t15.5, and to transition between current values ​​I4 and -Id from time t15.5 to time t16. Time t3.5 is between time t3 and time t4, time t11.5 is between time t11 and time t12, and time t15.5 is between time t15 and time t16. In this example, processor system 114 controls DC power supply 106 to have current values ​​−Id, I4, −Ib, and I2 during each additional cycle, such as cycle 2, of the clock signal, in a similar manner as processor system 114 controls DC power supply 106 to have current values ​​−Id, I4, −Ib, and I2 during cycle 1. Note that the sum of the durations of current values ​​−Id, I4, −Ib, and I2 equals 100 percent of each clock cycle period of the clock signal.

[0083] 6B , during each clock cycle of the clock signal, one or more of the current values ​​of current signal 612 have one or more durations different from those shown in FIG. 6B to achieve the different durations during each process operation. For example, processor system 114 controls DC power supply 106 to have a current value −Id during a time period from time t0 to time t1.5, transition from the current value −Id to a current value −Ic during a time period from time t1.5 to time t2, have a current value −Ic from time t2 to time 3.5, transition from the current value −Ic to a current value −Ib during a time period from time t3.5 to time t4, have a current value −Ib during a time period from time t4 to time t5.5, transition from the current value −Ib to a current value −Ia during a time period from time t5.5 to time t6, have a current value −Ia during a time period from time t6 to time t7.5, and transition from the current value −Ia to a current value I4 during a time period from time t7.5 to time t8. Time t1.5 is between time t1 and time t2, and time t5.5 is between time t5 and time t6. Also in this example, the processor system 114 controls the DC power supply 106 to have a current value of I4 from time t8 to time t9.5, transition from the current value I4 to a current value I3 during the time period from time t9.5 to time t10, have a current value I3 from time t10 to time t11.5, transition from the current value I3 to a current value I2 during the time period from time t11.5 to time t12, have a current value I2 from time t12 to time t13.5, transition from the current value I2 to a current value I1 during the time period from time t13.5 to time t14, have a current value I1 from time t14 to time t15.5, and transition from the current value I1 to a current value −Id during the time period from time t15.5 to time t16. In this example, the processor system 114 controls the DC power supply 106 to have current values ​​−Id, −Ic, −Ib, −Ia, I4, I3, I2, and I1 during each additional cycle, such as cycle 2, of the clock signal in a similar manner as the processor system 114 controls the DC power supply 106 to have current values ​​−Id, −Ic, −Ib, −Ia, I4, I3, I2, and I1 during cycle 1. Note that the sum of the durations of the current values ​​−Id, −Ic, −Ib, −Ia, I4, I3, I2, and I1 equals 100 percent of the period of each clock cycle of the clock signal.

[0084] 6C is an embodiment of graph 620 illustrating another manner in which the amplitude, polarity, or duration, or a combination thereof, of current signal 622 is periodically varied. There is a curved transition between two adjacent polarities or two adjacent amplitudes of current signal 622. Current signal 622 is an example of current signal 152 (FIG. 1). Unlike the linear transitions shown in graph 610, the transitions of current signal 622 are curved and sloped.

[0085] Graph 620 plots current signal 622 on the y-axis and time t on the x-axis. Regardless of the start or end of each process operation shown in FIG. 2 , processor system 114 (FIG. 1) controls DC power supply 106 to change the amplitude, polarity, or duration, or a combination thereof, of current signal 622 at predetermined time intervals, e.g., periodically or periodically, to output current values ​​−Id, −Ib, I2, and I4 in a pulsed manner. For example, current signal 622 has a current value −Id from time t0 to time t1.5. Current signal 622 then transitions from the current value −Id to a current value −Ib during the time period from time t1.5 to time t2.5 and maintains the current value −Ib from time t2.5 to time t4. Current signal 622 transitions from the current value −Ib to a current value I2 during the time period from time t4 to time t5 and maintains the current value I2 from time t5 to time t6.5. Furthermore, current signal 622 transitions from a current value of I2 to a current value of I4 during the period from time t6.5 to time t7.5 and maintains the current value I4 from time t7.5 to time t9. During the period from time t9 to time t10, processor system 114 controls DC power supply 116 to change the polarity of current signal 622 from positive to negative and to change the amplitude of current signal 622 from I4 to Id. Similarly, during the period between times t10 and t20, independent of the clock cycles of the clock signal, processor system 114 controls DC power supply 106 to change the amplitude, polarity, or duration, or a combination thereof, of current signal 622 in a manner similar to the manner in which the amplitude, polarity, or duration, or a combination thereof, of current signal 622 is changed between times t0 and t10, repeatedly controlling DC power supply 106 for each predetermined time interval.

[0086] Note that each slope transition from one current value to the next in current signal 622 is curved and has a positive or negative slope. For example, the slope transition between current values ​​−Id and −Ib from time t1.5 to time t2.5 has a positive slope, and the slope transition between current values ​​I4 and −Id from time t9 to time t10 has a negative slope.

[0087] In one embodiment, during each repeat period, one or more of the current values ​​of current signal 622 shown in FIG. 6C have one or more durations that are different from one or more remaining durations of one or more of the remaining current values ​​of current signal 622, in a similar manner as one or more of the current values ​​of current signal 612 shown in FIG. 6B have one or more different durations.

[0088] In one embodiment, during each repeat period, one or more amplitudes of one or more of the current values ​​of current signal 622 shown in FIG. 6C are different, such as greater than or less than, one or more of the remaining amplitudes of current signal 622. For example, during the period between times t0 and t1.5, current signal 622 has amplitude Ia and negative polarity, rather than amplitude Id and negative polarity.

[0089] 6C has a different polarity than one or more of the remaining polarities of one or more of the remaining current values ​​of current signal 622. For example, during the period between times t0 and t1.5, current signal 622 has an amplitude I3 and a positive polarity rather than an amplitude Id and a negative polarity.

[0090] In one embodiment, during each clock cycle of the clock signal, one or more of the current values ​​of current signal 622 have one or more durations different from those shown in Figure 6C, with each different duration coinciding with a corresponding process operation in Figure 2. The same examples as described above with reference to Figure 6B apply here.

[0091] In one embodiment, during each clock cycle of the clock signal, one or more of the current values ​​of current signal 622 have one or more durations different from those shown in Figure 6C to achieve the different durations during each process operation. The same example as described above with reference to Figure 6B applies here.

[0092] 6D is an embodiment of a graph 630 illustrating another manner in which the amplitude, polarity, or duration, or a combination thereof, of a current signal 632 is periodically varied. The current signal 632 has multiple triangular and inverted triangular shapes. The current signal 632 is an example of the current signal 152 (FIG. 1). The graph 630 plots the current signal 632 on the y-axis and time t on the x-axis.

[0093] 2, the processor system 114 (FIG. 1) controls the DC power supply 106 to output current values ​​−Id and I4 in a pulsed manner by varying the amplitude, polarity, or duration, or a combination thereof, of the current signal 632 at predetermined time intervals, e.g., periodically or periodically. For example, the current signal 632 has a current value of zero from time t0 to time t0.5, which is between time t0 and time t1. The current signal 632 transitions from a zero current value to a current value −Id during the time period from time t0.5 to time t1.5. Thereafter, the current signal 632 transitions from a current value −Id to a zero current value during the time period from time t1.5 to time t2.5, and maintains the zero current value from time t2.5 to time t3.5. The transition from time t0.5 to time t1.5 has a negative slope and is a straight line, and the transition from time t1.5 to time t2.5 has a positive slope and is a straight line.

[0094] The combination of the transition from time t0.5 to time t1.5 and the transition from time t1.5 to time t2.5 forms an inverted triangle. The current value of −Id at time t1.5 is the peak current value with the maximum current amplitude and negative polarity of the inverted triangle extending from time t0.5 to time t2.5.

[0095] Current signal 632 transitions from zero to I4 during the time period from time t3.5 to time t4.5, and from I4 to zero during the time period from time t4.5 to time t5.5. The transition from time t3.5 to time t4.5 is a straight line with a positive slope, and the transition from time t4.5 to time t5.5 is a straight line with a negative slope. Current signal 632 maintains the zero current value from time t5.5 to time t6.

[0096] The combination of the transition from time t3.5 to time t4.5 and the transition from time t4.5 to time t5.5 forms a triangle. The current value of I4 at time t4.5 is the peak current value with the maximum current amplitude and positive polarity of the triangle extending from time t3.5 to time t5.5.

[0097] Thus, current signal 632 periodically cycles through a triangle and an inverted triangle shape from time t6 to time t12. The period between times t0 and t6 or between times t6 and t12 is an example of a repeating period.

[0098] In one embodiment, during each repeat period, one or more of the current values ​​of current signal 632 shown in FIG. 6D have one or more durations that are different from one or more remaining durations of one or more of the remaining current values ​​of current signal 632. For example, during each repeat period, each inverted triangular current signal 632 is applied for a longer or shorter time than shown in FIG. 6D . Illustratively, an inverted triangle extending from time t0.5 to time t2.5 instead extends from time t0 to time t3. As another example, during each repeat period, each triangular current signal 632 is applied for a longer or shorter time than shown in FIG. 6D . Illustratively, a triangle extending from time t3.5 to time t5.5 instead extends from time t3 to time t6. Note that the sum of the durations of the triangle and inverted triangular current signals 632 and the zero current values ​​during each repeat period equals 100 percent of the repeat period.

[0099] 6D are different, such as greater than or less than, one or more of the remaining peak current values ​​of current signal 632. For example, rather than achieving a peak current value −I at time t1.5, current signal 632 achieves an amplitude I and a negative polarity. As another example, rather than achieving a peak current value I at time t4.5, current signal 632 achieves an amplitude I and a positive polarity.

[0100] 6D has a different polarity than one or more of the remaining current values ​​of current signal 632. For example, rather than achieving a peak current value −Id at time t1.5, a peak current value I2 is achieved at time t1.5. The peak current value I2 is achieved by transitioning from a current value of zero at time t0.5 to a current value I2 at time t1.5.

[0101] In one embodiment, during each clock cycle of the clock signal, one or more of the current values ​​of current signal 632 have one or more durations different from those shown in Figure 6D, with each different duration coinciding with a corresponding process operation in Figure 2. For example, processor system 114 controls DC power supply 106 to transition from a zero current value to a current value -Id during a time period from time t0 to time t2, from a current value -Id to a zero current value during a time period from time t2 to time t4, from a zero current value to a current value -Ic from time t4 to time t6, from a current value -Ic to a zero current value from time t6 to time t8, from a zero current value to a current value I3 from time t8 to time t10, from a current value I3 to a zero current value from time t10 to time t12, from a current value I3 to a zero current value from time t12 to time t14, and from a current value I4 to a zero current value from time t14 to time t16. In this example, the processor system 114 controls the DC power supply 106 to transition between the current values ​​of zero, −Id, −Ic, I3, and I4 during each additional cycle, such as cycle 2, of the clock signal in a similar manner as the processor system 114 controlled the DC power supply 106 to transition between the current values ​​of zero, −Id, −Ic, I3, and I4 during cycle 1. Note that the sum of the durations formed by the current values ​​of zero, −Id, −Ic, I3, and I4 equals 100 percent of each clock cycle period of the clock signal.

[0102] In one embodiment, during each clock cycle of the clock signal, one or more of the current values ​​of current signal 632 have one or more durations different from those shown in FIG. 6D to achieve different durations during each process operation. For example, the processor system 114 controls the DC power supply 106 to transition from zero current to −Id during the time period from time t0 to time t1, from −Id to zero current during the time period from time t1 to time t2, from zero current to −Ic during the time period from time t2 to time t3, from −Ic to zero current during the time period from time t3 to time t4, from zero current to −Ib during the time period from time t4 to time t5, from −Ib to zero current during the time period from time t5 to time t6, from zero current to −Ia during the time period from time t6 to time t7, and from −Ia to zero current during the time period from time t7 to time t8.

[0103] In this example, the processor system 114 controls the DC power supply 106 to transition from zero current to I1 during the time period from time t8 to time t9, from I1 to zero current during the time period from time t9 to time t10, from zero current to I2 during the time period from time t10 to time t11, from I2 to zero current during the time period from time t11 to time t11, from zero current to I3 during the time period from time t12 to time t13, from I3 to zero current during the time period from time t13 to time t14, from zero current to I4 during the time period from time t14 to time t15, and from I4 to zero current during the time period from time t15 to time t16.

[0104] Further, in this example, the processor system 114 controls the DC power supply 106 to have current values ​​−Id, −Ic, −Ib, −Ia, 0, I1, I2, I3, and I4 during each additional cycle, such as cycle 2, of the clock signal in a similar manner as the processor system 114 controls the DC power supply 106 to have current values ​​−Id, −Ic, −Ib, −Ia, 0, I1, I2, I3, and I4 during cycle 1. Note that the sum of the durations formed by the current values ​​−Id, −Ic, −Ib, −Ia, 0, I1, I2, I3, and I4 equals 100 percent of each clock cycle period of the clock signal.

[0105] In one embodiment, rather than each inverted triangle being an inverted isosceles triangle, an inverted right triangle is formed by current signal 632. For example, current signal 632 transitions from a zero current value to a −I current value at time t0.5. Current signal 632 transitions from a −I current value to a zero current value during the time period from time t0.5 to time t2.5.

[0106] Similarly, in one embodiment, rather than each triangle being isosceles, a right triangle is formed by the current signal 632. For example, at time t3.5, the current signal 632 transitions from a zero current value to a current value of I4. During the time period from time t3.5 to time t6, the coil current transitions from a current value of I4 to a zero current value.

[0107] 6E is an embodiment of a graph 640 illustrating another manner in which the amplitude or polarity, or a combination thereof, of a current signal 642 is periodically varied. The current signal 642 is a sine wave. There are curved transitions between two adjacent peak current values ​​of the current signal 642. The current signal 642 is an example of the current signal 152 (FIG. 1). The current signal 642 is similar to the current signal 632 (FIG. 6D) except that the transitions of the current signal 642 are curved and sloped to form a sine wave, whereas the transitions of the current signal 642 are linear.

[0108] In one embodiment, during each repeat period, one or more of the current values ​​of current signal 642 shown in FIG. 6D have one or more durations that are different from one or more remaining durations of one or more of the remaining current values ​​of current signal 642, similar to how one or more of the current values ​​of current signal 632 shown in FIG. 6C have one or more different durations.

[0109] 6E is different, such as greater than or less than, one or more of the remaining peak current values ​​of current signal 642. For example, rather than achieving a peak current value −I at time t1.5, current signal 642 achieves an amplitude I and a negative polarity. As another example, rather than achieving a peak current value I at time t4.5, current signal 642 achieves an amplitude I and a positive polarity.

[0110] In one embodiment, during each repeat period, one or more of the current values ​​of current signal 642 shown in Figure 6E has a polarity that is different from one or more remaining polarities of one or more of the remaining current values ​​of current signal 642. The same examples as described above with reference to Figure 6D apply here.

[0111] In one embodiment, during each clock cycle of the clock signal, one or more of the current values ​​of current signal 642 have one or more durations different from those shown in Figure 6D, with each different duration coinciding with a corresponding process operation in Figure 2. The same examples as described above with reference to Figure 6D apply here.

[0112] In one embodiment, during each clock cycle of the clock signal, one or more of the current values ​​of current signal 642 have one or more durations different from those shown in Figure 6E to achieve the different durations during each process operation. The same example as described above with reference to Figure 6D applies here.

[0113] 6F is an embodiment of a graph 650 illustrating yet another manner in which the amplitude, polarity, or duration, or a combination of patterns thereof, of a current signal 652 is periodically changed. For example, the pattern of the coil current 652 changes at predetermined time intervals. The current signal 652 is an example of the current signal 152 (FIG. 1). The graph 650 plots the current signal 652 on the y-axis and time t on the x-axis.

[0114] 2 , processor system 114 (FIG. 1) controls DC power supply 106 to output current values ​​−Id, −Ic, −Ib, I4, I3, and I2 in a pulsed manner by changing the amplitude, polarity, duration, or pattern, or a combination thereof, of current signal 652 at predetermined time intervals, e.g., periodically or periodically. Current signal 652 is output in a pulsed manner to form multiple patterns, including a first pattern. For example, current signal 652 transitions from a zero current value to a current value I4 at time t0 and maintains the current value I4 from time t0 to time t0.5. Thereafter, current signal 652 transitions from the current value I4 to a current value −Id at time t0.5 and maintains the current value −Id from time t0.5 to time t1. At time t1, the current signal 652 transitions from a current value −Id to a current value I4, and maintains the current value I4 during the period from time t1 to time t1.5. At time t1.5, the current signal 652 transitions from the current value I4 to a current value −Id, and maintains the current value −Id from time t1.5 to time t2. Thereafter, the current signal 652 transitions from the current value −Id to a current value I4 at time t2, and maintains the current value I4 from time t2 to time t2.5. The current signal 652 transitions from the current value I4 to a current value −Id at time t2.5. The period from time t0 to time t2.5 is an example of a predetermined time interval.

[0115] After a predetermined time interval, the processor system 114 controls the DC power supply 106 to change the first pattern of the current signal 652 formed during the period from time t0 to time t2.5. The first pattern is changed to form a second pattern of the current signal 652. The second pattern is formed during the period from time t2.5 to time t4. For example, during the period from time t2.5 to time t3, the current signal 652 maintains a current value of −Id and transitions from the current value −Id to a current value of −Ic at time t3. Next, during the period from time t3 to time t3.5, the current signal 652 maintains a current value of −Ic and transitions from the current value −Ic to a current value of −Ib at time t3.5. Thereafter, during the period from time t3.5 to time t4, the current signal 652 maintains a current value of −Ib and transitions from the current value −Ib to a current value of I4 at time t4. Furthermore, during the period from time t4 to time t4.5, the current signal 652 maintains the current value I4, and at time t4.5, it transitions from the current value I4 to the current value I3. During the period from time t4.5 to time t5, the current signal 652 maintains the current value I3, and at time t5, it transitions from the current value I3 to the current value I2. During the period from time t5 to time t5.5, the current signal 652 transitions from the current value I2 to the current value I4. The period from time t2.5 to time t5.5 is an example of a predetermined time interval. During the period from time t5.5 to time t8, the first pattern is repeated. During the period from time t8 to time t11, the second pattern is repeated. It should be noted that each amplitude -Id, I4, -Ic, -Ib, I3, and I2 of the current signal 652 is represented as a horizontal level, and the transition between any two adjacent amplitudes -Id, I4, -Ic, -Ib, I3, and I2 is represented vertically.

[0116] 6F have one or more durations that are different from one or more remaining durations of one or more of the remaining current values ​​of current signal 652. For example, processor system 114 controls DC power supply 106 to have current value −Id for a longer or shorter period than the period during which DC power supply 106 is controlled to have current value I4. Note that the sum of the durations of current values ​​I4 and −Id equals 100 percent of each repeat period.

[0117] In one embodiment, during each repeat period, one or more of the amplitudes of the current values ​​of current signal 652 shown in FIG. 6F are different, such as greater or less than, one or more of the remaining amplitudes of current signal 652. For example, during the period between times t0 and t0.5, current signal 652 has amplitude I3 and positive polarity rather than amplitude I4 and positive polarity.

[0118] 6F has a different polarity than one or more of the remaining polarities of one or more of the remaining current values ​​of current signal 652. For example, during the period between times t0 and t0.5, current signal 602 has an amplitude Ic and a negative polarity rather than an amplitude I4 and a positive polarity.

[0119] In one embodiment, during each clock cycle of the clock signal, one or more of the current values ​​of current signal 652 have one or more durations different from those shown in Figure 6F to match each pattern of current signal 652 with the corresponding process operation in Figure 2. For example, processor system 114 controls DC power supply 106 to change the duration for which current value I4 is maintained, or the duration for which current value -Id is maintained, or a combination thereof, to extend the first pattern from time t0 to time t4. In this example, processor system 114 controls DC power supply 106 to change the duration for which current value -Id is maintained, the duration for which current value -Ic is maintained, the duration for which current value -Ib is maintained, the duration for which current value I4 is maintained, the duration for which current value I3 is maintained, or the duration for which current value I2 is maintained, or a combination thereof, to extend the second pattern from time t4 to time t8. Similarly, in cycle 1, the first pattern is extended from time t8 to time t12, and the second pattern is extended from time t12 to time t16. The first and second patterns are repeated in each cycle of the clock signal, as in cycle 1 of the clock signal. Note that the sum of the durations of current values ​​-Id, I4, -Ic, -Ib, I3, and I2 equals 100 percent of each clock cycle period of the clock signal.

[0120] 6F , to achieve each pattern of current signal 652 during each process operation. For example, processor system 114 controls DC power supply 106 to change the duration for which current value I4 is maintained, or the duration for which current value −Id is maintained, or a combination thereof, to extend a first pattern from time t0 to time t2. In this example, processor system 114 controls DC power supply 106 to change the duration for which current value −Id is maintained, the duration for which current value −Ic is maintained, the duration for which current value −Ib is maintained, the duration for which current value I4 is maintained, the duration for which current value I3 is maintained, or the duration for which current value I2 is maintained, or a combination thereof, to extend a second pattern from time t2 to time t4. Similarly, the first pattern is extended during the period from time t4 to time t6, and the second pattern is extended during the period from time t6 to time t8. Similarly, the first and second patterns alternate between cycles t8 to t16 during cycle 1 of the clock signal. The first and second patterns are repeated during each subsequent cycle of the clock signal, e.g., cycle 2, as well as cycle 1 of the clock signal. Note that the sum of the durations of current values ​​-Id, I4, -Ic, -Ib, I3, and I2 equals 100 percent of each clock cycle period of the clock signal.

[0121] FIG. 7 is a diagram of an embodiment of a system 700 showing a direct current (DC) power supply 700 for generating a current amplitude signal 704. The DC power supply 700 is an example of the DC power supply 120 (FIG. 1). The DC power supply 700 includes a plurality of DC batteries 1-n (n is a positive integer). The DC power supply 700 also includes a plurality of switches 1-n. The DC power supply 700 includes a summing unit 702, such as a summer. An example of each DC battery is a battery. As an example, each switch described herein is one or more transistors. As an example, the summing unit 702 is implemented as an ASIC or PLD. The DC power supply 700 includes a terminal 706 and another terminal 708. The terminal 708 is connected to the ground potential of each of the DC batteries 1-n.

[0122] The processor system 114 is connected to each of the switches 1 to n. Also, each DC battery is connected to a respective switch. For example, DC battery 1 is connected to switch 1, DC battery 2 is connected to switch 2, and so on, with DC battery n being connected to switch n. Switches 1 to n are connected to an adder 702. The adder 702 is connected to the polarity change circuit 122 (FIG. 1).

[0123] To reduce the amount of current supplied from the DC power supply 700, the processor system 114 generates and sends one or more off control signals to the corresponding one or more switches 1-n to open the one or more switches 1-n. For example, the processor system 114 generates and sends a first off control signal to switch 1 to open switch 1, and generates and sends a second off control signal to switch 2 to open switch 2. The one or more off control signals are examples of the one or more control signals 148 (FIG. 1). When one or more switches 1-n are open, the corresponding one or more DC battery cells 1-n are disconnected from the summing unit 702. For example, when switch 1 is open, DC battery 1 is disconnected from the summing unit 702, and when switch 2 is open, DC battery 2 is disconnected from the summing unit 702. When one or more switches 1-n are open, one or more current signals 1-n from the corresponding one or more DC battery cells 1-n connected to the one or more switches 1-n are not supplied to the summing unit 702. As an example, when switches 1 and 2 are open, current signal 1 from DC battery 1 is not provided to summing unit 702 and current signal 2 from DC battery 2 is not provided to summing unit 702 .

[0124] On the other hand, to increase the amount of current supplied from the DC power supply 700, the processor system 114 generates one or more ON control signals and sends them to the corresponding one or more switches 1-n to close the one or more switches 1-n. For example, the processor system 114 generates a first ON control signal and sends it to switch 1 to close switch 1, and generates a second ON control signal and sends it to switch 2 to close switch 2. The one or more ON control signals are examples of the one or more control signals 148. When one or more switches 1-n are closed, the corresponding one or more DC battery cells 1-n are connected to the adder 702. For example, when switch 1 is closed, DC battery 1 is connected to the adder 702, and when switch 2 is closed, DC battery 2 is connected to the adder 702. When one or more switches 1-n are closed, one or more current signals 1-n from the corresponding one or more DC battery cells 1-n connected to the one or more switches 1-n are supplied to the adder 702. For example, when switches 1 and 2 are closed, current signal 1 from DC battery 1 is supplied to adder 702, and current signal 2 from DC battery 2 is supplied to adder 702. Adder 702 adds one or more n current signals from one or more n DC batteries connected to adder 702 via one or more switches 1 to n, and outputs current amplitude signal 704 from adder 702 to terminal 706.

[0125] Adding one or more n current signals changes the amplitude of current amplitude signal 704. For example, when current signal 1 is not added to current signals 2 to n by adder 702, the amplitude of current amplitude signal 704 decreases compared to when current signal 1 is added to current signals 2 to n. On the other hand, when current signal 1 is added to current signals 2 to n by adder 702, the amplitude of current amplitude signal 704 increases compared to when current signal 1 is not added to current signals 2 to n.

[0126] Changing the amplitude of the current amplitude signal 704 changes the amplitude of the current signal 152. For example, the amplitude of the current signal 152 may be maintained at one level for a period of time or may transition to another amplitude level. The current amplitude signal 704 is sent to the polarity change circuit 122 via terminal 706 to change the polarity of the current amplitude signal 704.

[0127] Additionally, controlling the time that the corresponding switch 1-n is closed controls one or more durations of the current amplitude signal 704. For example, the processor system 114 controls the switches 1-n to be closed for a time period equal to the duration of the amplitude of the current amplitude signal 704. For example, increasing the time that the switches 1-n are closed increases the time interval, such as the period during which the current amplitude signal 704 is output at the terminal 706, thereby increasing the duration of the amplitude. Conversely, decreasing the time that the switches 1-n are closed decreases the time interval, such as the period during which the current amplitude signal 704 is output at the terminal 706, thereby decreasing the duration of the amplitude.

[0128] 8 is a diagram of an embodiment of a system 800 showing a polarity change circuit 802. The polarity change circuit 802 is an example of the polarity change circuit 122 (FIG. 1). The system 800 includes a DC power supply 700, a processor system 114, and the polarity change circuit 802. The polarity change circuit 802 includes switches SW1 and SW2. Switch SW1 has terminals T1a, T1b, and T1c. Switch SW2 has terminals T2a, T2b, and T2c.

[0129] The processor system 114 is connected to switches SW1 and SW2. Terminal 706 is connected to terminal T1a, and terminal 708 is connected to terminal T2a. Terminal T1b is connected to terminal 102A of magnetic coil 102, and terminal T1c is connected to terminal 102B of magnetic coil 102. Terminal T2b is connected to terminal 102B, and terminal T2c is connected to terminal 102A.

[0130] The processor system 114 controls the switches SW1 and SW2 to change their positions. The positions are changed to change the polarity of the current amplitude signal 704 from positive to negative or from negative to positive, thereby outputting the current signal 152. For example, the processor system 114 sends a first position control signal to the switch SW1 and a first position control signal to the switch SW2. The first position control signal is an example of the position control signal 150 (FIG. 1). Upon receiving the first position control signal, the terminal T1a of the switch SW1 is connected to the terminal T1b. Furthermore, upon receiving the first position control signal, the terminal T2a of the switch SW2 is connected to the terminal T2b. When the terminal T1a is connected to the terminal T1b and the terminal T2a is connected to the terminal T2b, the current amplitude signal 704 output from the terminal 706 is transmitted to the terminal T1b via the terminal T1a as the current signal 152 having a positive polarity. A current signal 152 having a positive polarity is transmitted from terminal T1b to terminal 102A to generate a magnetic field in a first direction within gap 142 (FIG. 1). A return current signal 804 generated as a result of the magnetic field having the first direction is transmitted from terminal 102B through terminals T2b and T2a to terminal 708, which is connected to ground potential.

[0131] Similarly, as another example, the processor system 114 sends a second position control signal to the switch SW1 and a second position control signal to the switch SW2. The second position control signal is an example of the position control signal 150. Upon receiving the second position control signal, the terminal T1a of the switch SW1 is connected to the terminal T1c. Furthermore, upon receiving the second position control signal, the terminal T2a of the switch SW2 is connected to the terminal T2c. When the terminal T1a is connected to the terminal T1c and the terminal T2a is connected to the terminal T2c, the current amplitude signal 704 output from the terminal 706 is transmitted to the terminal T1c via the terminal T1a as a current signal 152 having a negative polarity. The current signal 152 having a negative polarity is transmitted from the terminal T1c to the terminal 102B, generating a magnetic field in a second direction within the gap 142 (FIG. 1). The second direction is opposite to the first direction. A feedback current signal 806 generated as a result of the magnetic field having the second direction is transmitted from terminal 102B through terminals T2c and T2a to terminal 708, which is connected to ground potential.

[0132] In one embodiment, by periodically changing the polarity of the current signal 152, tilt symmetry can be achieved across the top surface of the substrate S. Illustratively, the tilt changes direction with the change in polarity. Illustratively, when the polarity is positive, the tilt is upward along the top surface, and when the polarity is negative, the tilt is downward along the top surface. Illustratively, the symmetry can be achieved across an axis passing through the center of the substrate S. Illustratively, the top half of the substrate S has a tilt that is symmetrical relative to the bottom half of the substrate S. Illustratively, the symmetric tilt can be radially inward or outward and is largely independent of the azimuthal angle across the top surface of the substrate S.

[0133] As an example, the slope of a feature on a substrate S is the angle formed between the center of the opening of the feature and the center of the bottom wall of the feature. The feature has an opening on a top surface. The feature also has a bottom wall and a sidewall. The opening is separated from the bottom wall by the sidewall.

[0134] It should be noted that while tilt symmetry is achievable, in one embodiment, zero tilt is achieved in all features of the substrate S by controlling one or more durations of the current signal 152, or one or more amplitudes of the current signal 152, or by changing one or more polarities of the current signal 152, or a combination thereof.

[0135] In one embodiment, the terms time period and time interval are used interchangeably herein. In one embodiment, the terms predetermined time interval and recurring time period are used interchangeably herein.

[0136] Broadly, in various embodiments, a controller, as used herein, is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define parameters, factors, variables, etc. for performing a particular process on or for a semiconductor wafer or system. Program instructions, in some embodiments, are part of a recipe defined by a process engineer to implement one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0137] In various embodiments, exemplary systems to which the methods may be applied include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a tracking chamber or module, and any other semiconductor processing system associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0138] It should be further noted that in some embodiments, the above operations also apply to several types of plasma chambers, such as inductively coupled plasma (ICP) reactors, transformer-coupled plasma chambers, plasma chambers with conductive tools, dielectric tools, and plasma chambers with electron cyclotron resonance (ECR) reactors. For example, one or more RF generators are connected to an inductor in an ICP reactor. The inductor may have a shape such as a solenoid, a dome coil, a flat coil, etc.

[0139] Some embodiments also relate to hardware units or apparatus for performing these operations. The apparatus is specially configured for a special purpose computer. When defined as a special purpose computer, the computer is operable for a specific purpose, but also performs other processes, program execution, or routines not included in the specific purpose.

[0140] One or more embodiments may also be fabricated as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit, such as a memory device, that stores data and that is subsequently read by a computer system. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc ROMs (CD-ROMs), CD recordables (CD-Rs), CD rewritables (CD-RWs), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium comprises a computer-readable tangible medium distributed over a network-coupled computer system so that the computer-readable code is stored and executed in a distributed manner.

[0141] Although the method operations above have been described in a particular order, it should be understood that in various embodiments, other housekeeping operations may be performed between operations, or the method operations may be coordinated to occur at slightly different times, or may be distributed across the system to occur at various intervals, or may be performed in a different order than described above.

[0142] It is further noted that in one embodiment, one or more features from any of the above-described embodiments may be combined with one or more features of any other of the above-described embodiments without departing from the scope described in the various embodiments described in this disclosure.

[0143] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Accordingly, the present embodiments should be considered as illustrative and not restrictive, and the embodiments should not be limited to the details set forth herein.

Claims

1. 1. A method for controlling tilt across a surface of a substrate, comprising: providing a current signal to a magnetic coil coupled to a plasma chamber to generate a magnetic field within the plasma chamber; controlling a direct current (DC) power supply to pulse the current signal at a plurality of amplitudes during a clock cycle; repeating the current signals of the plurality of amplitudes for each additional clock cycle. A method comprising:

2. 2. The method of claim 1, wherein controlling the DC power supply includes controlling the DC power supply to change polarity of the current signal during the clock cycle to output the current signal having multiple polarities during the clock cycle; The method, wherein repeating includes repeating the plurality of polarities during the additional clock cycles.

3. 2. The method of claim 1, wherein the plurality of amplitudes includes a first amplitude and a second amplitude; the first amplitude is output during a first time interval and the second amplitude is output during a second time interval; The first amplitude transitions to the second amplitude to output the plurality of amplitudes in the pulsed manner.

4. 4. The method of claim 3, wherein controlling the DC power supply includes controlling a transition from the first amplitude to the second amplitude to have a linear gradient to output the plurality of amplitudes in the pulsed manner; The linear gradient is a positive gradient or a negative gradient.

5. 4. The method of claim 3, wherein controlling the DC power supply includes controlling a transition from the first amplitude to the second amplitude to have a curved slope to output the plurality of amplitudes in the pulsed manner; The method wherein the curve slope is a positive slope or a negative slope.

6. 4. The method of claim 3, wherein the plurality of polarities includes a first polarity and a second polarity; controlling the DC power supply includes controlling the DC power supply such that the current signal has the first polarity during the first time interval in which the current signal has the first amplitude and the second polarity during the second time interval in which the current signal has the second amplitude.

7. 7. The method of claim 6, wherein controlling the DC power supply includes controlling a transition from the first polarity to the second polarity to have a linear gradient to output the plurality of amplitudes in the pulsed manner; The linear gradient is a positive gradient or a negative gradient.

8. 7. The method of claim 6, wherein controlling the DC power supply includes controlling a transition from the first polarity to the second polarity to have a curved slope to output the plurality of amplitudes in the pulsed manner; The method wherein the curve slope is a positive slope or a negative slope.

9. 2. The method of claim 1, wherein the plurality of amplitudes are output during a process operation; During said process operation, the substrate is treated using chemicals and power levels.

10. 2. The method of claim 1, wherein the plurality of amplitudes are output at the beginning of a first process operation; During the first process operation, the substrate is processed using a first chemistry and a first power level; the cycling of the plurality of amplitudes occurs at the beginning of a second process operation; During the second process operation, the substrate is processed using a second chemistry and a second power level.

11. 10. The method of claim 1, wherein the plasma chamber is a capacitively coupled plasma chamber; the capacitively coupled plasma chamber includes an upper electrode and a substrate support; the upper electrode is disposed above the substrate support table; The method, wherein the magnetic coil is positioned above the upper electrode.

12. The method of claim 11 , wherein the magnetic coil is thicker than a transformer coupled plasma (TCP) coil.

13. 1. A method for controlling tilt across a surface of a substrate, comprising: providing a current signal to a magnetic coil coupled to a plasma chamber to generate a magnetic field within the plasma chamber; controlling a direct current (DC) power supply to pulse the current signal at a plurality of amplitudes during a clock cycle, the current signal being output at the start of a process operation; repeating the current signals of the plurality of amplitudes at the start of each additional process operation. A method comprising:

14. 14. The method of claim 13, wherein controlling the DC power supply includes controlling the DC power supply to change polarity of the current signal at the end of the process operation and at the start of the additional process operation to output the current signal having multiple polarities during the clock cycle.

15. 14. The method of claim 13, wherein the plurality of amplitudes includes a first amplitude and a second amplitude; the first amplitude is output during a first time interval and the second amplitude is output during a second time interval; The method wherein the first amplitude transitions to the second amplitude and the plurality of amplitudes are output in the pulsed manner.

16. 16. The method of claim 15, wherein controlling the DC power supply includes controlling a transition from the first amplitude to the second amplitude to have a linear slope to output the plurality of amplitudes in the pulsed manner; The linear gradient is a positive gradient or a negative gradient.

17. 16. The method of claim 15, wherein controlling the DC power supply includes controlling a transition from the first amplitude to the second amplitude to have a curved slope to output the plurality of amplitudes in the pulsed manner; The method wherein the curve slope is a positive slope or a negative slope.

18. 16. The method of claim 15, wherein the plurality of polarities includes a first polarity and a second polarity; controlling the DC power supply includes controlling the DC power supply so that the current signal has the first polarity during the first time interval during which the current signal has the first amplitude, and the current signal has the second polarity during the second time interval during which the current signal has the second amplitude.

19. 19. The method of claim 18, wherein controlling the DC power supply includes controlling a transition from the first polarity to the second polarity to have a linear gradient to output the plurality of amplitudes in the pulsed manner; The linear gradient is a positive gradient or a negative gradient.

20. 19. The method of claim 18, wherein controlling the DC power supply includes controlling a transition from the first polarity to the second polarity to have a curved slope to output the plurality of amplitudes in the pulsed manner; The method wherein the curve slope is a positive slope or a negative slope.

21. 1. A method for controlling tilt across a surface of a substrate, comprising: providing a current signal to a magnetic coil coupled to a plasma chamber to generate a magnetic field within the plasma chamber; controlling a direct current (DC) power supply to pulse the current signal at a plurality of amplitudes during a clock cycle, each of the plurality of amplitudes being output during a process operation; repeating the current signals of the plurality of amplitudes during each additional process operation. A method comprising:

22. 22. The method of claim 21, wherein controlling the DC power supply includes controlling the DC power supply to change polarity of the current signal during the process operation to output the current signal having multiple polarities during the process operation; The method, wherein the repeating includes repeating the plurality of polarities during the additional process operation.

23. 22. The method of claim 21, wherein the plurality of amplitudes includes a first amplitude and a second amplitude; the first amplitude is output during a first time interval and the second amplitude is output during a second time interval; The method wherein the first amplitude transitions to the second amplitude and the plurality of amplitudes are output in the pulsed manner.

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