Thermal expansion matched chip module with integrated liquid cooler

Abstract

The chip and cooler assembly includes an active or passive interposer having a front surface and a back surface. An integrated circuit chip is mounted on the back surface of the interposer. Each chip has a front surface attached to the interposer and a back surface facing away from the interposer. A gap separates the chips. The assembly also includes a frame fitted into the gap between the chips. The frame is CTE-matched to the chips. The frame and chip define a back surface. A cooler module is attached to the back surface. The cooler module is CTE-matched to the chip. The cooler module includes a microchannel cooler disposed directly against the back surface of the chip and a manifold attached to the microchannel cooler on the opposite side of the chip. The manifold is CTE-matched to the microchannel cooler.

Description

[Background technology]

[0001] The present invention relates to the fields of electricity, electronics, and computers, and more particularly to thermal management of integrated circuit assemblies.

[0002] Integrated circuits generate waste heat during operation. This heat, if not removed, can degrade the circuit's performance. In the worst case, retained heat can lead to thermal runaway. Therefore, it is desirable to remove the waste heat from the integrated circuit chip. Typically, this is done using a cold plate attached to the chip. In multi-chip assemblies, individual cold plates may be attached to each individual chip. Alternatively, a conformable thermal interface material may be used as an intermediate layer between multiple chips and a single shared cold plate. In some cases, the cold plate is made flexible to accommodate multiple chips that may have different thicknesses or heights. Typically, the cold plate is made of metal to achieve high thermal conductivity.

[0003] Electronic modules or packages typically need to provide power, input / output (I / O) connections, cooling, and mechanical protection for the active semiconductor devices they contain. In semiconductor chip packaging, organic substrates are typically used to expand the fine-pitch, typically 0.15–0.2 mm, Controlled Collapse Chip Connector (C4) solder bumps on the silicon die into larger-pitch, typically 1.0–1.2 mm, BGA (ball grid array) or LGA (land grid array) connections. In a BGA, the chip package is attached to a printed circuit board (PCB) by reflowing solder balls to form a permanent connection, while an LGA-type interposer provides a connection that allows for easy removal and replacement of the chip package on the PCB.

[0004] For LGA interposers, or connectors / sockets, a mechanical load is required to compress springs or other contact elements to form individual electrical connections. Generally, with organic packaging substrates, a lid formed from a thermally conductive material, such as copper, is attached to the chip and organic substrate to protect the chip during handling and to add mechanical strength to the organic substrate. A thermal interface material (TIM) is applied between the back surface of the chip and the lid to provide a thermal path. If necessary, a heat sink is then attached to the outer surface of the lid using a second TIM layer. The chip is placed face-down, or device-side down, on the packaging substrate and connected by C4s.

[0005] Typical organic laminates used to package chips have a coefficient of thermal expansion (CTE) of approximately 13–18 ppm / °C, which is larger than the silicon CTE of approximately 3 ppm / °C. This difference limits the size of chips that can be reliably attached to the laminate with C4 solder balls and the minimum pitch of the solder balls due to stresses generated during thermal cycling. The CTE mismatch between the silicon chip and copper lid (CTE of ~17 ppm / °C) means that for reliable operation of large chips, a thicker, flexible TIM layer is required, which performs less well than rigid TIM layers such as silver-filled epoxy, solder, or metals such as indium.

[0006] Current-generation multi-chip high-performance computing modules incorporate stacked chips and high-bandwidth memory chip stacks (HBM). Lower chips in each stack contain through-silicon vias (TSVs). The chip stacks are mounted on a silicon carrier, which has multiple wiring layers and TSVs to interconnect the mounted chips. An interposer is then attached to an organic laminate. Key advantages of silicon carriers, also called interposers, are that they can be fabricated with finer-pitch wiring than organic laminates, and because they are CTE-matched to the chips, larger chips can be mounted to the silicon carrier with finer-pitch solder balls, both of which can increase data bandwidth between chips. A disadvantage of silicon interposers is that due to the etching process used to form the TSVs, they are typically thin, approximately 0.05–0.2 mm thick, which means they are brittle and can easily crack when extended over a large area. Glass, which has a CTE match to silicon, can be used to fabricate carriers or interposers with multiple fine-pitch wiring layers and through-vias that are functionally equivalent to silicon carriers in many respects. Both silicon and glass are brittle materials, strong in compression but fail in tension above a critical load. Their fracture strength depends on the presence of the largest crack nucleation sites. TSVs are crack nucleation sites. Stacked chips are increasingly being joined by "hybrid bonding," in which oxide layers and copper connections are bonded directly to each other, eliminating the need for solder bumps. In some higher-power-density modules, integrating liquid cooling directly into the module lid is believed to provide improved cooling. Multichip modules such as those described above are typically mounted to PCBs using LGA rather than BGA connections to allow for interchangeability.Current prior art high performance multichip modules use materials with different CTEs, requiring very careful engineering, design, and assembly methods to ensure reliable long-term operation. Any bending of the large area silicon or glass carrier is desirably avoided, as it could fracture the carrier. Summary of the Invention

[0007] The principles of the present invention provide a technology for thermal expansion matched chip modules with integrated liquid cooling.

[0008] In one embodiment, an exemplary chip and cooler assembly includes an interposer having a front surface and a back surface, and multiple integrated circuit chips mounted on the back surface of the interposer. Each of the chips has a front surface attached to the interposer and a back surface facing away from the interposer. The chips are separated by a gap. The chip and cooler assembly also includes a frame fitted into the gap between the chips. The frame is CTE-matched to the chips. The frame and chip define a back surface. A chip cooler module is attached to the back surface. The cooler module is CTE-matched to the chips. The cooler module includes a microchannel cooler disposed directly against the back surface of the chip, and a manifold attached to the microchannel cooler on the opposite side of the chip. The manifold is CTE-matched to the microchannel cooler.

[0009] In another embodiment, an exemplary method includes assembling multiple chips onto the backside of an interposer. The chips are CTE-matched to the interposer. The method also includes assembling a frame in the gaps between the chips; depositing an adhesive on the backside of the chips; and placing a chip cooler module against the adhesive. The microchannel cooler is CTE-matched to the chips and the interposer.

[0010] In view of the above, the techniques of the present invention can provide substantial beneficial technical effects. For example, one or more embodiments may provide one or more of the following:

[0011] Rigid, thermally matched, integrated multi-chip modules with improved integration, cooling performance, and reliability.

[0012] A thick thermal expansion matched manifold that provides stiffness and fluid distribution to the module.

[0013] Glass or silicon carriers with redistribution wiring layers allow fine pitch interconnects and high wiring density, improving chip-to-chip bandwidth.

[0014] Thermal expansion matched microchannel coolers with rigid thermal interfaces (silver epoxy, solder, or metal) reduce chip operating temperatures, improve reliability, and reduce leakage currents.

[0015] For carriers with a 1 mm pitch land grid array, fine pitch through vias are not required.

[0016] Elastomeric seals in the load block on the opposite side of the module from the LGA can be used to provide a coolant fluid connection, and additional elastomer seals can be used to evenly distribute mechanical loads without additional fluid connections.

[0017] An underfill or other filler material is used to bond the interposer, one or more frame pieces, the microchannel cooler, and the chip together and to fill any voids or gaps that exist between the interposer and the microchannel cooler, thereby forming a rigid, integrated structure.

[0018] Some embodiments may not have these potential advantages, and these potential advantages are not necessarily required for all embodiments. These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. [Brief explanation of the drawings]

[0019] [Figure 1] 1A and 1B schematically illustrate a side view of an integrated circuit chip assembly including multiple chips on an interposer, according to an exemplary embodiment.

[0020] [Figure 2] 1 illustrates a thermal expansion matched chip cooler module in an exploded assembly schematic view according to an exemplary embodiment;

[0021] [Figure 3] 2, the integrated circuit chip assembly shown in FIG. 1, and a thermal expansion matched frame according to an exemplary embodiment, in an exploded schematic view of the assembly.

[0022] [Figure 4] 2 shows a schematic diagram of a plan view (from above) of the integrated circuit chip assembly shown in FIG. 1 with thermal epoxy, according to an exemplary embodiment;

[0023] [Figure 5] A schematic diagram illustrates a side view of the integrated circuit chip assembly shown in FIG. 1 with a frame and thermal epoxy, according to an exemplary embodiment.

[0024] [Figure 6] 4 shows a schematic side view of the assembly of the components shown in FIG. 3 after the handler has been removed with additional thermal epoxy and underfill.

[0025] [Figure 7]4 illustrates a schematic of an LGA load block for the assembled components shown in FIG. 3.

[0026] [Figure 8] 1 illustrates a schematic diagram of a thermal expansion matched multi-piece frame in accordance with an exemplary embodiment;

[0027] [Figure 9] 1 illustrates a schematic diagram of a thermal expansion matched frame including recessed grooves to aid underfill flow, according to an exemplary embodiment;

[0028] [Figure 10] 1 illustrates a flowchart of an exemplary method according to an aspect of the present invention.

[0029] [Figure 11] 1 illustrates a schematic diagram of a chip and cooler assembly having stiffeners at each edge of the assembly according to an exemplary embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0030] FIG. 1 schematically illustrates a side view of a processor module 100 including multiple chips 102, 112 on an interposer 114, according to an exemplary embodiment. Each of the chips 102, 112 has a front surface 104 and a back surface 106. In one or more embodiments, the chip 102 is a processor or computational unit, while the chip 112 is memory, such as high-bandwidth memory (HBM). Gaps 108 separate adjacent chips. Some of the gaps contain silicon capacitors 110. In one or more embodiments, the chip 102 is attached to the interposer 114 by controlled collapse chip connectors (C4), i.e., fine-pitch solder bumps, or by copper / oxide hybrid bonding. The interposer 114 also includes redistribution wiring layers (RDLs) 120 and 122 and through-silicon vias (TSVs) 124 connecting the RDLs. The interposer 114 has land grid array (LGA) pads 126 on its front side. In one or more embodiments, the TSVs have a pitch of 1 to 1.5 mm or smaller. The RDL 120 provides signal connections between chips on the top surface of the interposer and is configured to distribute power via C4s. The TSVs connected to the chips via the RDL 120 and C4s provide signals and power outside the module. For LGAs connected to power, multiple TSVs may be used in parallel to reduce electrical resistance. Depending on the detailed design, the RDL layer 122 on the LGA side of the interposer may or may not be present; if not present, the LGA pads are directly connected to the TSVs. In one or more embodiments, during fabrication of the processor module 100, the LGA side of the interposer 114 can be mounted on a handler wafer 128 with a removable adhesive layer during fabrication of the RDL 120 and chip attachment.

[0031] In one or more embodiments, chip stacks such as HBM (high bandwidth memory modules) or thin capacitors (e.g., silicon capacitors) can be included in processor module 100. In alternative embodiments, the active silicon interposer can include additional elements such as integrated decoupling capacitors, active devices for power conversion, or other active devices for distributing I / O signals or for other purposes. When such devices are added to the silicon interposer, they can be formed on the top, bottom, or both surfaces. In one embodiment, the active silicon interposer can correspond to a chip or array of chips with TSVs and LGA pads formed on the backside and an HBM memory stack or additional active chips bonded to the front surface, as shown in FIG. 1 .

[0032] 2 illustrates an exploded schematic view of an assembly of a thermal expansion matched chip cooler module 200 according to an exemplary embodiment. The module 200 includes a microchannel cooler 202, a lower manifold 204, and an upper manifold 206, all of which are bonded together with a rigid material such as glass frit.

[0033] FIG. 2 shows a perspective view of a silicon microchannel cooler 202 in which a pattern of alternating fins 208 (not to scale) running from left to right is created by using a deep reactive etching process to pattern the silicon to a depth of approximately 300 microns. The specific shape of the fins depends on the specifics of the application and can be optimized as known to those skilled in the art. The etched microchannels 210 are surrounded on all sides by frame regions 211, e.g., 3.5 mm wide, which allow the microchannel layer to be sealed by an overlying glass manifold layer. The microchannel layer has nominal dimensions of 77 x 87 x 0.775 mm.

[0034] In one or more embodiments, the glass manifold layers 204, 206 are each approximately 77 x 87 x 5 mm in size and are made from Schott Borofloat® 33 glass (a registered trademark of SCHOTT AG, Mainz, Germany) or other glass material with a CTE match to silicon. The lower glass manifold layer 204 is machined to form three recessed slots or grooves 214, 216 in its lower surface and three arrays of through-holes or vertical channels 212 aligned with these grooves. The grooves 214, 216 are approximately 2.4 mm wide in one or more embodiments and serve to restrict the flow of water toward the microchannels. The fluid pathway through the glass uses an array of holes to avoid overly weakening the glass layer. The upper glass manifold layer 206 is machined to form tapered manifold channels 218, 220 extending from central holes 222, 224 such that after assembly of the chip cooler module 200, the tapered channels 218, 220 overlap and provide fluid to / from the holes 212 in the lower manifold layer. In an exemplary, non-limiting embodiment, the glass layer and the microchannel layer are permanently and firmly bonded together by using a glass frit material, such as Ferro 11-036 (manufactured by Ferro Corporation of Mayfield Heights, Ohio), between them.

[0035] In operation, cooling fluid is provided from the LGA load block 700 (shown in FIG. 7 ) through a flexible seal, such as an O-ring, to the central inlet 224 on the top surface of the glass microchannel cooler. The coolant then flows along the tapered channels 220 in the upper glass manifold layer, eventually flowing down through the holes 212 and into the recessed grooves 216 on the bottom of the lower glass manifold layer. From the channels or grooves 216, the coolant flows across the microchannel layer 202 to the outlet recessed grooves 214 on the bottom of the lower glass manifold layer. From the grooves or channels 214, the coolant then flows up through the holes 212 to the tapered outlet manifolds 218 on the bottom surface of the upper glass manifold layer and then to the outlet openings 222. The outlet openings 222 are sealed to the fluid channels in the LGA load block 700 by a flexible member. Alternative configurations are possible.

[0036] In one or more embodiments, the fins 208 and channels 210 of the silicon microchannel cooler 202 are formed by deep reactive-ion etching (DRIE), a highly anisotropic etching process typically used to create deep penetrations, steep-slope holes, and trenches in high-aspect-ratio silicon wafers / substrates. In one or more embodiments, the manifold layers 204, 206 are formed by machining polished plates of borosilicate glass. In one or more embodiments, the microchannel cooler and manifold layers are assembled and attached by screen-printing a frit in a pattern over the entire surface, drying, glazing, aligning / stack, clamping, and firing.

[0037] In one or more embodiments, the lower manifold 204 includes a plurality of vertical channels 212 that open to two outwardly directed outlet grooves 214 and a central inlet groove 216. The grooves 214, 216 correspond to outlet chambers 218 and inlet chambers 220 of the upper manifold 206. Each outlet chamber 218 has an outlet nozzle 222, and each inlet chamber 220 has an inlet nozzle 224. The longitudinal direction of the alternating fins of the microchannel cooler 202 is oriented perpendicular to the inlet and outlet grooves. Note that in other embodiments, additional manifold layers may be used depending on the particular application, and therefore the use of only two layers in these figures should not be considered limiting.

[0038] FIG. 3 illustrates an exploded schematic view of the assembly of the thermal expansion-matched chip cooler module 200 shown in FIG. 2, the processor module 100 shown in FIG. 1, and a thermal expansion-matched frame 300, according to an exemplary embodiment. The frame 300 includes edges 302, 304, 306, 308 and cross pieces 310, 312. In one or more embodiments, the portions of the cross pieces 310, 312 that overlap the capacitors 110 are thinner than the edges 302, 304, 306, 308. Thus, the frame 300 fits into the gaps 108 between the chips 102 on the processor module 100, providing a uniform surface against which the module 200 can be mounted. The frame 300 further extends beyond the chips 102, 112 to the edges of the interposer 114 and also to the edges of the microchannel cooler 202. In other words, the frame 300 occupies the space around the chip 102 and between the interposer 114 and the microchannel cooler 202. In one or more embodiments, the frame 300 or a separate piece of the frame is made from CTE-matched glass (i.e., glass with the same coefficient of thermal expansion as silicon) or silicon. Generally, the frame 300 is intended to occupy the empty space between the mounted silicon or glass carrier 114 and the flat base of the chip cooler module 200, leaving a small gap, on the order of about 25 to 200 microns in height, which will then be filled with underfill or other filler material. This serves to increase the strength and rigidity of the final structure and minimizes the volume fraction of the module, which is not perfectly CTE-matched to the silicon. In a preferred embodiment, the spacer frame is constructed from a material that is CTE matched to silicon, such as silicon or Borofloat® 33 glass, and need not be a single piece, but can be multiple pieces or even layers of pieces (see Figures 8 and 9 for alternative structures 800, 900 of the frame 300).

[0039] In one or more embodiments, the chip 102 is attached to the carrier or interposer with C4 solder balls on a 150-micron pitch, the HBM module 112 is attached to the carrier with microbumps on a 55-micron pitch, and the capacitors 110 and optional EEPROM chip are also attached using solder. In a specific embodiment, the interposer 114 measures 77 x 87 x 0.5 mm, and the chips 102 are each 30 x 25 mm. The silicon or glass carrier can be thicker than typical because the through-via pitch requirement is relaxed to just 1 mm. Interposers made from silicon-CTE-matched glass with a 0.25 mm via pitch and a 0.5 mm thickness are commercially available. An exemplary CTE-matched glass is Borofloat® 33 glass, available from SCHOTT North America, Inc. of Rye Brook, New York. Generally, "CTE matched" in the context of this disclosure means matched to within 5 percent of the average of the values ​​at 20° C. and 300° C., respectively. In an exemplary embodiment that does not limit the scope of the invention, the handler 128 is approximately 0.775 mm thick, as is the processor chip 102; the HBM stack is approximately 0.72 mm thick; and commercially available silicon capacitors are used, which can be on the order of 0.1 mm thick.

[0040] In one or more embodiments, the chip 102 is attached to the carrier or interposer with a copper-oxide hybrid bond, a copper-copper bond, or any other solid, fused, or permanent bond. Bonding can be performed at the chip or wafer scale. The frame 300 can then be bonded to the carrier with adhesive, epoxy, solder, a copper-oxide hybrid bond, a copper-copper bond, or any other suitable bond. Depending on the thermal processing requirements of the gap fill material and the desired mechanical properties, the frame bonding material can be appropriately selected to withstand the necessary downstream processing. The gaps between the dies and between the die and the frame can be substantially equal to enable a simple gap fill process. The gap fill can utilize organic or inorganic materials. As described in alternative embodiments, organic materials can include underfill. Inorganic gap fill materials can include silicon-based materials or other dielectric or semiconductor materials. Silicon-based materials, or other semiconductors or dielectrics, can enable the CTE of the gap fill material to match the adjacent dies and frame. Exemplary materials include silicon nitride, silicon oxide, SiCOH, and SiCN. For example, silicon dioxide has a density of about 0.6 x 10 -6 / K, while germanium has a CTE of about 5.8×10 -6 / K. Silicon-based gap fill materials can be applied or deposited at the die or wafer level. They can be deposited by various chemical vapor deposition techniques, such as plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD). Additionally, silicon inks and pastes can be deposited at low temperatures. Silicon can also be sputtered at low temperatures. Depending on the thermal limitations of the chip interposer assembly, deposition temperatures can be kept below 400°C or 450°C. Alternatively, gap fill materials can be deposited at low temperatures (e.g., 200°C) and annealed at moderate temperatures (e.g., 400°C) without adversely affecting the copper features of the chip and carrier. Encapsulation of the chip and carrier can be achieved with an initial thin inorganic material, followed by another hard dielectric or semiconductor layer. Deposition techniques typically deposit material on the backside of the die and frame, thereby degrading the thermal performance of the cooling solution. Grinding, polishing, or etching of the film can be performed to planarize and remove the film on the backside of the die, revealing the chip and frame. All of the above processes can be performed in the presence of a handler with a high temperature compatible temporary bonding film, or without a handler if the carrier or interposer is thick enough.

[0041] 4 schematically illustrates a plan view (from above) of the processor module 100 shown in FIG. 1 with a thermal epoxy or other heat-filled, rigid adhesive 400 applied to the chips 102 and 112, according to an exemplary embodiment. The thermal epoxy 400 may be, for example, a silver-filled epoxy material such as Ablestik 965-1L (manufactured by Henkel Corporation of Rocky Hill, Connecticut), which may be applied on the top or backside of the processor chips, HBM memory modules, and other components requiring cooling.

[0042] FIG. 5 shows a schematic diagram of a side view of the integrated circuit chip assembly shown in FIG. 1 after the frame 300 has been placed and the thermal epoxy 400 has been deposited, according to an exemplary embodiment.

[0043] FIG. 6 schematically illustrates a side view of an assembly 600 of the components shown in FIG. 3 to form a thermal expansion-matched chip module with an integrated liquid cooler. Thus, to assemble the assembly 600, thermal (e.g., silver) epoxy or other heat-filled rigid adhesive 400 is applied to the backside of the chips 102 and 112, the frame 300 and cooler module 200 are stacked on the chip assembly 100, the parts are aligned and clamped together in a clamping fixture (not shown), and the silver epoxy is then cured in a loading fixture. After removing the assembly from the loading fixture, the next step is to apply the underfill. A capillary underfill material, generally an epoxy or similar polymer containing fine particles of silica or other filler, is used to fill gaps between the carrier, components, spacer frame, and microchannel cooler. Typically, heat is used to reduce the viscosity of the underfill and accelerate its flow. In one or more embodiments, a vacuum underfill step is used after removing the module from the clamping fixture to ensure all gaps are filled. In this process, the module and the open container with the pool of underfill are placed in a chamber, which is then evacuated. The lower portion of the module—i.e., the handler, loaded carrier, spacer frame, and a portion of the glass microchannel cooler—is submerged in the pool of underfill, and the chamber is then evacuated, thus using atmospheric pressure to force the underfill material 602 into all gaps between the loaded carrier and the silicon microchannel cooler. Care can be taken to ensure that the underfill material does not enter the glass microchannel cooler through the ports on the top surface. After removing the module from the chamber and wiping any excess underfill from the sides and bottom of the handler, the underfill material is cured. Figure 6 shows the underfilled assembly after the handler 128 and adhesive have been removed, exposing the LGA pads.

[0044] FIG. 7 schematically illustrates a load block 700 for clamping an assembled module to an LGA. The load block 700 has a body 702 with three holes 704, 706, and 708 (corresponding to the inlet and outlet nozzles of the module 200) formed therein. Circular grooves 710 are also formed in a surface 712 of the body 702 for receiving O-rings (not shown). When the load block is in use, O-rings are inserted into all of the grooves 710, and the load block 700, holding the O-rings, is pressed down against the module 600 to seal the fluid inlet / outlet openings and actuate the LGA. Only the O-rings contact the upper glass manifold layer. Providing an evenly distributed array of O-rings, in addition to the three peripheral nozzle holes 704, 706, and 708, allows the assembly to be compressed against the LGA socket without uneven force causing the module to crack.

[0045] In one or more embodiments, the underfill can be applied after the silver epoxy has cured or can be cured simultaneously with the silver epoxy. The underfill secures the frame to the interposer and cooler module to form a rigid, integrated structure.

[0046] If a handler 128 was used during assembly, it is removed to expose the LGA pads on the interposer. The carrier can be removed by a laser stripping process, which uses a laser directed through the handler to ablate or decompose the adhesive material, or by using a solvent to dissolve the adhesive material. In the case of a solvent, if holes are provided in the handler to allow the solvent to act more quickly, tape can be applied to the bottom surface before the vacuum underfill step to prevent these holes from being inadvertently filled with underfill.

[0047] A modified assembly process can be used if a solder or other metallic thermal interface is provided between the chips 102 and 112 and the microchannel cooler 202. Solder or other metallic thermal bonding materials can be used to reduce the thermal resistance between the heat-dissipating components and the microchannel cooler. In such a process, the back surfaces of the heat-dissipating chips and memory stacks on the mounted carrier can be metallized by evaporation through a metal mask, and similarly, all or part of the underside of the glass microchannel cooler can be metallized so that the solder wets the surface. Rather than applying silver-filled epoxy in the process described above, a solder paste or preform can be placed, if desired, and a reflow process can be used to bond the components together before proceeding with the remaining stages of vacuum underfill and handler removal. An additional alternative assembly method is to use Cu-to-Cu and oxide-to-oxide hybrid bonding instead of solder balls to bond the chips, HBM memory stacks, etc. to the carrier.

[0048] Large LGA sockets require significant loads for actuation. For example, for a 77 x 87 mm module and a 75 x 85 array of 1 mm pitch LGAs, a typical actuation load is 44 gm / contact, for a total required load of 280.5 kg. As previously mentioned, with brittle materials such as glass or silicon, it is important to avoid tensile loads that could result in fracture. For example, bending forces applied to the described module would result in a tensile load on one surface and a compressive load on the opposite surface. Such tensile loads can be avoided by applying the load as evenly as possible across the module surface while uniformly supporting the opposite surface to avoid any bending forces. In a preferred embodiment, additional, purely mechanical, O-rings or other flexible means are used between the LGA load block and the module to distribute the load more evenly. In a preferred embodiment, the LGA load block 700 has a smooth surface facing the module and annular recesses for receiving O-rings, three of which also provide fluid inlet and outlet ports to and from the module. The LGA load block, through a clamping mechanism, provides a controlled force that clamps the module, LGA, and PCB together. In one or more embodiments, the PCB has a stiffener plate behind it to which the clamping mechanism is connected.

[0049] FIG. 7 is a schematic diagram illustrating a possible distribution of O-rings on a module to more evenly distribute the LGA load, with ten of the O-rings being for purely mechanical purposes and three providing fluid connections. FIG. 7 shows an LGA load block 700 with grooves 710 for receiving O-rings, which, in one or more embodiments, are appropriately recessed so that only the compressed O-ring, and not the load block, contacts the glass manifold surface. One related advantage of this module structure over perfect CTE matching is its greater thickness than prior art modules, since plate stiffness is proportional to the cube of the thickness. For the given example, the thickness is approximately 12 mm, compared to approximately 4 mm for a typical chip package. If desired, stiffness can be further increased by using thicker or additional glass layers in the manifold. This greater stiffness allows for somewhat uneven load application by using the 13 O-rings shown in FIG. 7. LGA provides a more uniform load by compressible contacts on a 1mm pitch that press against the bottom surface of the module.

[0050] 8 schematically illustrates a thermally matched, multi-piece frame 800 including a central cross piece 802 and arms 804, 806, 808, 810. Corner pieces 812, 814, 816, 818 are assembled with central cross piece 802 to define fill vents 820, 822, 824, 826 and underfill nozzles 828, 830, 832, 834; if conventional atmospheric underfill injection is used, underfill is introduced through nozzles 828, 830, 832, 834 during assembly, and air is exhausted out through vents 820, 822, 824, 826.

[0051] FIG. 9 schematically illustrates a thermal expansion matched frame 900 having a central cross piece 902 connected to edge pieces 904 that include recessed grooves 906, 908, 910, 912 for venting air and channels 914, 916, 918, 920 for underfill flow when conventional atmospheric underfill injection is used.

[0052] FIG. 11 schematically illustrates a chip and cooler assembly 1100 having stiffeners 1102 at each edge of the assembly, according to an exemplary embodiment. The assembly 1100 includes an interposer 1104, a first chip 1106, a second chip 1108, an underfill 1110, a microchannel cooler 1112, and a fluidic mating plate 1114. In one or more embodiments, the fluidic mating plate 1114 is similar to the load block 700 and has an O-ring that directly interfaces with the upper surface of the microchannel cooler 1112. In one or more embodiments, the fluidic mating plate 1114 is made from stainless steel. In one or more embodiments, the microchannel cooler 1112 is similar to the combination of the upper portion 206 of the cooler manifold and the microchannel cooler 202 identified in the cooler module 200 ( FIG. 2 ). In one or more embodiments, the microchannel cooler 1112 is made from silicon for thermal conductivity. In one or more embodiments, the stiffener 1102 is made from multiple layers 1116, 1118, 1120, 1122 of silicon bonded together, for example, by adhesive 1124. In one or more embodiments, the top layer 1122 is present on one edge of the assembly but not on the opposite edge; this may advantageously allow the microchannel cooler 1112 to expand or contract laterally due to temperature changes. Furthermore, adhesive is a non-limiting example of a bonding technique for the multiple layers 1116, 1118, 1120, 1122 of silicon; other examples include any suitable bonding material / method, such as hybrid bonding, direct bonding, solder, and the like.

[0053] Given the foregoing discussion, it will be understood that, in general, an exemplary chip and cooler assembly 600 includes an interposer 114 having a front surface 118 and a back surface 116, and multiple integrated circuit chips 102, 112 mounted on the back surface of the interposer. Each of the chips has a front surface 104 attached to the interposer and a back surface 106 facing away from the interposer. A gap separates the chips. The chip and cooler assembly 600 also includes a frame 300 fitted into the gap between the chips. The frame extends beyond the chips to the edge of the interposer. The frame is CTE-matched to the chips. The frame and chip define a back surface. A chip cooler module 200 is attached to the back surface. The chip cooler module is CTE-matched to the chips. The chip cooler module includes a microchannel cooler 202 attached to the backside of the chip, and manifolds 204, 206 attached to the microchannel cooler on the opposite side of the chip, with the manifolds CTE-matched to the microchannel cooler.

[0054] In one or more embodiments, the chip and cooler assembly 600 also includes multiple thinner chips embedded in the gaps between the multiple chips, with the frame being thinner over the thinner chips and thicker where the thinner chips are not present.

[0055] In one or more embodiments, the chips have electrical contacts on their front surfaces, and the interposer includes land grid array pads disposed on the front surface of the interposer and through silicon vias connecting the electrical contacts of the chips to the land grid array pads.

[0056] In one or more embodiments, the interposer includes a redistribution wiring layer 120 that is CTE matched to and adjacent to the chip.

[0057] In one or more embodiments, the material of the manifold is glass. In one or more embodiments, the material of the lower portion 204 of the manifold is silicon. In one or more embodiments, the material of the microchannel cooler is silicon.

[0058] In one or more embodiments, the chip and cooler assembly 600 also includes a filled thermal epoxy that attaches the microchannel cooler to the chip, such as silver-filled epoxy 400. In other embodiments, a metallic substance, material, or compound (e.g., indium foil, silver-tin solder) attaches the microchannel cooler to the chip.

[0059] In one or more embodiments, the module is between 2 mm and 25 mm thick. In some embodiments, the module is between 4 mm and 12 mm thick.

[0060] In one or more embodiments, the chip and cooler assembly also includes an underfill that bonds the interposer, chip, frame, and cooler together and fills the gaps between them.

[0061] In one or more embodiments, the frame has multiple pieces. In one or more embodiments, the multiple pieces include multiple layers; for example, multiple layers of silicon bonded together as discussed elsewhere herein, see layers 1116, 1118, 1120, 1122 in FIG. 11 . In one or more embodiments, the multiple layers include a first layer that extends along all edges of the assembly and a second layer over the first layer; the second layer (e.g., 1122, not on the left but on the right of FIG. 11 ) extends along a first edge of the assembly but does not extend along an edge of the assembly opposite the first edge.

[0062] In one or more embodiments, the chip and cooler assembly 600 also includes a load block 700 on top of the manifold, where the load block has holes that align with the holes in the manifold, has flexible members (e.g., O-rings) surrounding the matching holes, and has additional flexible members (e.g., O-rings) distributed in a uniform array across the interface of the load block and the manifold.

[0063] In one or more embodiments, the manifold includes an upper piece 206 and a lower piece 204, and has a central inlet hole 224 and two peripheral outlet holes 222 that extend from the top of the manifold through the upper piece to grooves 220, 218 through the bottom of the upper piece, and the lower piece includes a plurality of holes 212 that open from respective grooves through the lower piece to the microchannel cooler.

[0064] In one or more embodiments, the chip and cooler assembly also includes a glass frit that bonds the upper piece of the manifold to the lower piece of the manifold and that bonds the lower piece of the manifold to the microchannel cooler.

[0065] According to another aspect, and referring to FIG. 10 , an exemplary method 1000 includes assembling multiple chips onto the backside of an interposer at 1002. The chips are CTE-matched to the interposer. The method also includes assembling a frame in the gaps between the chips at 1004; depositing thermal epoxy 400 onto the backside of the chips at 1006; and mounting a chip cooler module 200 against the thermal epoxy at 1010. The microchannel cooler is CTE-matched to the chips and the interposer.

[0066] In one or more embodiments, the method 1000 also includes, at 1008, forming the chip cooler module 200 by attaching the manifolds 204, 206 to the microchannel cooler 202; and, at 1012, filling the gaps between the chip, frame, microchannel, and interposer with underfill 602.

[0067] In one or more embodiments, the method 1000 also includes, at 1014, combining the thermal expansion-matched chip and cooler assembly 600 and load block 700, with a first plurality of O-rings connecting the holes in the load block 700 to the holes in the upper manifold 206, and a second plurality of O-rings distributing the mechanical load across the interface of the load block and the manifold.

[0068] In one or more embodiments, the method 1000 also includes, at 1016, loading the chip and cooler assembly into a land grid array socket while applying pressure to the load block.

[0069] In one or more embodiments, the method 1000 also includes, at 1018, flowing coolant from the load block through a manifold.

[0070] The description of various embodiments of the present invention is presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements beyond those found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. an interposer having a front surface and a back surface; a plurality of integrated circuit chips mounted on the backside of the interposer, each of the chips having a front side attached to the interposer and a back side facing away from the interposer, with gaps separating the chips; a frame fitted around the chip, wherein the frame is CTE-matched to the chip, and the frame and the chip define a back surface; and a cooler module attached to the back surface, the cooler module being CTE-matched to the chip, the cooler module having a microchannel cooler disposed against the back surface of the chip, and a manifold attached to the microchannel cooler on an opposite side of the chip, the manifold being CTE-matched to the microchannel cooler; A chip and cooler assembly comprising:

2. 2. The chip and cooler assembly of claim 1, further comprising a plurality of thinner chips embedded in portions of the gaps between the plurality of chips, wherein the frame is thinner over the thinner chips than where the thinner chips are not present.

3. 2. The chip and cooler assembly of claim 1, wherein the chips have electrical contacts on their front surfaces, and the interposer has land grid array pads disposed on the front surface of the interposer and through silicon vias connecting the electrical contacts of the chips to the land grid array pads.

4. The chip and cooler assembly of claim 1 , wherein the interposer is CTE-matched to the chip and includes a redistribution wiring layer adjacent to the chip.

5. The chip and cooler assembly of claim 1 , wherein the manifold material comprises glass.

6. The chip and cooler assembly of claim 1 , wherein at least one of the chips is mounted to the interposer by a hybrid bond.

7. The chip and cooler assembly of claim 1 , wherein the frame has multiple pieces.

8. The chip and cooler assembly of claim 7 , wherein the multiple pieces include multiple layers of silicon bonded together.

9. 9. The chip and cooler assembly of claim 8, wherein the plurality of layers includes a first layer present around the entire edge of the assembly and a second layer on top of the first layer, the second layer being present on a first side of the assembly but not on a side of the assembly opposite the first side.

10. The chip and cooler assembly of claim 1 further comprising a filled, thermally rigid adhesive that attaches the microchannel cooler to the chip.

11. The chip and cooler assembly of claim 1 , further comprising a metallic material that attaches the microchannel cooler to the chip.

12. The chip and cooler assembly of claim 1 , wherein the module is between 2 mm and 25 mm thick.

13. The chip and cooler assembly of claim 1 , wherein the module is between 4 mm and 12 mm thick.

14. The chip and cooler assembly of claim 1 , further comprising a filler material adhering the interposer, frame, chip, and cooler together and filling gaps therebetween.

15. The filler material is about 0.6×10 －６ / K and about 5.8 × 10 －６ 15. The chip and cooler assembly of claim 14, having a CTE between 0.15 and 0.15 K.

16. 2. The chip and cooler assembly of claim 1, further comprising a load block on the manifold, wherein the load block has holes aligned with holes in the manifold, has O-rings surrounding the aligned holes, and has additional O-rings distributed in a uniform array across an interface of the load block and the manifold.

17. 17. The chip and cooler assembly of claim 16, wherein the manifold includes an upper piece and a lower piece, and includes one or more inlet holes and one or more outlet holes extending from the top of the manifold through the upper piece to grooves that pass across the bottom of the upper piece, and the lower piece includes a plurality of holes that open from respective grooves through the lower piece to the microchannel cooler.

18. The chip and cooler assembly of claim 1 , wherein the interposer is an active interposer.

19. assembling a plurality of chips on a backside of the interposer, wherein the chips are CTE-matched to the interposer; assembling a frame in the gap between the chips; depositing an adhesive on the backside of the chip; and placing a chip cooler module against the adhesive, wherein the chip cooler module is CTE-matched to the chip and the interposer; A method for providing the above.

20. attaching a manifold to a microchannel cooler to form the chip cooler module; and filling gaps between the chip, the frame, the microchannel, and the interposer with underfill; 20. The method of claim 19 further comprising:

21. assembling a load block to the manifold, a first plurality of O-rings connecting holes in the load block to holes in the manifold, and a second plurality of O-rings distributing mechanical loads across an interface between the load block and the manifold to form a chip and cooler assembly.

21. The method of claim 20, further comprising:

22. loading the chip and cooler assembly into a land grid array socket with pressure applied to the load block.

22. The method of claim 21 further comprising:

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