SYSTEM AND METHOD FOR CHIPLET SYNCHRONIZATION - Patent application

Abstract

The disclosed computer-implemented method may include a chiplet involved in performing operations of a process reaching a synchronization barrier. The method may further include the chiplet receiving a dedicated control message pushed to the chiplet by another chiplet involved in performing operations of the process, the dedicated control message being pushed by the other chiplet over a control network. The method may also include the chiplet advancing the synchronization barrier in response to receiving the dedicated control message. Various other methods, systems, and computer-readable storage media are also disclosed.

Description

[Background technology]

[0001] A chiplet is a small integrated circuit (IC) that contains a well-defined subset of functionality. Chiplets are designed to be combined with other chiplets on an interposer within a single package. A set of chiplets can be implemented in a mix-and-match assembly, which can offer several advantages over a traditional system on chip (SoC).

[0002] The accompanying drawings illustrate several exemplary embodiments and constitute a part of this specification, and together with the following description, these drawings demonstrate and explain various principles of the present disclosure. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram of an example system for chiplet synchronization. [Figure 2] FIG. 10 is a block diagram of an additional example system for chiplet synchronization. [Figure 3] FIG. 1 is a flow diagram of an example method for chiplet synchronization. [Figure 4] FIG. 2 is a block diagram illustrating a chiplet having a local dispatcher that exchanges dedicated control messages over a control network. [Figure 5] FIG. 2 is a block diagram illustrating a parallel processor that implements a chiplet synchronization process. DETAILED DESCRIPTION OF THE INVENTION

[0004] Throughout the drawings, like reference numerals and descriptions indicate similar, but not necessarily identical, elements. While the exemplary embodiments described herein are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are herein described in detail. However, the exemplary embodiments described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims.

[0005] The present disclosure is generally directed to systems and methods for chiplet synchronization. In one example, central processing unit (CPU) hardware provides an on-chip parallel network with point-to-point communication capabilities. Chilets are configured to use this parallel network as a control bus for dedicated control messages and as a push mechanism for chiplet synchronization with parallel operations. Each chiplet maintains one or more counters for each other chiplet involved in executing an operation of a process (e.g., a thread), and the counters are incremented upon receiving a dedicated control message from another chiplet involved in the operation. Advancing a synchronization barrier in each chiplet when all of the counters are incremented ensures that the chiplets remain synchronized in executing operations while appearing as a single chip to the process. The use of a parallel control network avoids traffic congestion on the data network and improves throughput of the data and control networks. The push mechanism reduces traffic on the control network, and the on-chip implementation avoids hardwired point-to-point connections between chiplets, which are impractical for a large number of chiplets (e.g., 1000 or more).

[0006] In one example, a computer-implemented method performed at least in part by a computing device having a plurality of chiplets may include a chiplet involved in performing operations for a process reaching a synchronization barrier; the chiplet receiving a dedicated control message pushed to the chiplet by other chiplets involved in performing operations for the process, the dedicated control message being pushed by the other chiplets over a control network; and the chiplet advancing the synchronization barrier in response to receiving the dedicated control message.

[0007] Another example may be that of the exemplary method described above, where the control network corresponds to an on-chip network that provides connectivity between the chiplet and at least one of the other chiplets.

[0008] Another example may be that of the exemplary method described above, where the connection is a point-to-point connection.

[0009] Another example may be that of the exemplary method described above, where the control network corresponds to a separate control network implemented in parallel with a separate data network that also provides connectivity between the chiplet and at least one of the other chiplets.

[0010] Another example may be that of the exemplary method described above, where the chiplet and at least one of the other chiplets are implemented on different chips.

[0011] Another example may be any of the example methods described above, further including the chiplet pushing one or more outgoing dedicated control messages in response to reaching the synchronization barrier, the one or more outgoing dedicated control messages being pushed to other chiplets via the control network.

[0012] Another example may be any of the example methods described above, further including the chiplet maintaining a set of counters that includes at least one counter for each other chiplet.

[0013] Another example may be any of the exemplary methods described above, further comprising incrementing a counter of the set of counters in response to receiving the dedicated control message.

[0014] Another example may be any of the exemplary methods described above, further comprising: advancing the synchronization barrier further occurring in response to reaching the synchronization barrier.

[0015] In one example, a system may include a chiplet processor and a physical memory including computer-executable instructions that, when executed by the chiplet processor, cause a chiplet involved in performing operations of a process to reach a synchronization barrier, receive a dedicated control message pushed to the chiplet by other chiplets involved in performing operations of the process, the dedicated control message being pushed to the chiplet by the other chiplets over a control network, and advance the synchronization barrier in response to receiving the dedicated control message.

[0016] Another example may be a system of the exemplary systems described above, where the control network corresponds to an on-chip network that provides connectivity between the chiplet and at least one of the other chiplets.

[0017] Another example may be any of the exemplary systems described above, where the connection is a point-to-point connection.

[0018] Another example may be any of the example systems described above, where the control network corresponds to a separate control network implemented in parallel with a separate data network that also provides connectivity between the chiplet and at least one of the other chiplets.

[0019] Another example may be any of the exemplary systems described above, where the chiplet and at least one of the other chiplets are implemented on different chips.

[0020] Another example may be any of the example systems described above, where the instructions further cause the chiplet to push one or more outgoing dedicated control messages in response to reaching the synchronization barrier, the one or more outgoing dedicated control messages being pushed to other chiplets via the control network.

[0021] Another example may be any of the example systems described above, where the instructions further cause the chiplet processor to maintain a set of counters including at least one counter for each of the other chiplets.

[0022] Another example may be any of the exemplary systems described above, where the instructions further cause the chiplet processor to increment a counter of the set of counters in response to receiving the dedicated control message.

[0023] Another example may be any of the exemplary systems described above, where advancing the synchronization barrier is responsive to reaching the synchronization barrier.

[0024] In one example, a computer-readable storage medium may include one or more computer-executable instructions that, when executed by a chiplet processor performing operations of a process, cause the chiplet processor to: cause a chiplet involved in performing the operations of the process to reach a synchronization barrier; receive a dedicated control message pushed to the chiplet by other chiplets involved in performing the operations of the process, the dedicated control message being pushed to the chiplet by the other chiplets over a control network; and advance the synchronization barrier in response to receiving the dedicated control message.

[0025] Another example may be the computer-readable storage medium described above, wherein the control network corresponds to an on-chip network that provides connectivity between the chiplet and at least one of the other chiplets.

[0026] A detailed description of an exemplary system for chiplet synchronization is provided below with reference to Figures 1-2. A detailed description of a corresponding computer-implemented method is also provided with reference to Figure 3. Additionally, a detailed description of an exemplary chiplet having a local dispatcher exchanging dedicated control messages over a parallel on-chip network is provided with reference to Figure 4. Furthermore, a detailed description of an exemplary chiplet processor implementing the chiplet synchronization process is provided with reference to Figure 5.

[0027] 1 is a block diagram of an example system 100 for chiplet synchronization. As illustrated in this figure, the example system 100 may include one or more modules 102 for performing one or more tasks. As described in more detail below, the modules 102 may include a synchronization barrier observation module 104, a control message reception module 106, and a synchronization barrier advancement module 108. Although illustrated as separate elements, one or more of the modules 102 in FIG. 1 may represent portions of a single module or application.

[0028] In certain embodiments, one or more of the modules 102 in Figure 1 may represent one or more software applications or programs that, when executed by a computing device, cause the computing device to perform one or more tasks. For example, as described in more detail below, one or more of the modules 102 may represent modules stored and configured to execute on one or more computing devices, such as the devices shown in Figure 2 (e.g., computing device 202 and / or server 206). Also, one or more of the modules 102 in Figure 1 may represent all or part of one or more special-purpose computers configured to perform one or more tasks.

[0029] 1 , the exemplary system 100 may also include one or more memory devices, such as memory 140. Memory 140 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. In one example, memory 140 may store, load, and / or maintain one or more of modules 102. In additional or alternative examples, memory 140 may represent any one or combination of various elements (e.g., main chiplet processor memory, additional chiplet elements 120, standalone processing elements, etc.) that store and / or perform operations of module 102. Examples of memory 140 include, but are not limited to, random access memory (RAM), read only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), optical disk drive, cache, any variation or combination of one or more of these, or any other suitable storage memory.

[0030] As illustrated in FIG. 1 , the exemplary system 100 may also include one or more physical processors, such as physical processor 130. Physical processor 130 generally represents any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In one example, physical processor 130 may access and / or modify one or more of modules 102 stored in memory 140. Additionally or alternatively, physical processor 130 may execute one or more of modules 102 to facilitate chiplet synchronization. Examples of physical processor 130 include, but are not limited to, a microprocessor, a microcontroller, a central processing unit (CPU), a field-programmable gate array (FPGA) implementing a soft-core processor, an application-specific integrated circuit (ASIC), portions of one or more of these, variations or combinations of one or more of these, or any other suitable physical processor.

[0031] 1 , the exemplary system 100 may also include one or more additional chiplet elements, such as additional chiplet element 120. Additional chiplet element 120 generally represents any type or form of physical memory, communication medium, network interface, dispatch controller, process operation, or combination thereof. In one example, the additional chiplet element may perform process operations, maintain / manage associated data, exchange data messages over a data network, send and receive dedicated control messages over a parallel on-chip network, and / or maintain / manage data used for synchronization. Examples of additional chiplet elements include, but are not limited to, operations for process 122, synchronization barrier 124, dedicated control message 126, and control network 128.

[0032] The example system 100 of Figure 1 can be implemented in a variety of ways. For example, all or a portion of the example system 100 can represent a portion of the example system 200 of Figure 2. As shown in Figure 2, the system 200 can include a computing device 202 that communicates with a server 206 over a network 204. In some examples, the network 204 can represent a parallel network (e.g., separate data and control networks, where synchronization between devices (e.g., chiplets within a single socket or across multiple sockets) is performed over a separate logical or physical control network).

[0033] In one example, all or a portion of the functionality of modules 102 may be performed by computing device 202, server 206, and / or any other suitable computing system. As described in more detail below, one or more of modules 102 of FIG. 1, when executed by at least one processor of computing device 202 and / or server 206, may enable computing device 202 and / or server 206 to perform chiplet synchronization.

[0034] Computing device 202 generally represents any type or form of computing device capable of reading computer-executable instructions. For example, computing device 202 may be any computer capable of receiving, processing, and storing data. Additional examples of computing device 202 include, but are not limited to, laptops, tablets, desktops, servers, mobile phones, personal digital assistants (PDAs), multimedia players, embedded systems, wearable devices (e.g., smart watches, smart glasses, etc.), smart vehicles, so-called Internet of Things devices (e.g., smart appliances, etc.), game consoles, variations or combinations of one or more of these, or any other suitable computing device.

[0035] Server 206 generally represents any type or form of computing device capable of receiving, processing, and storing data. Additional examples of server 206 include, but are not limited to, a storage server, a database server, an application server, and / or a web server configured to run particular software applications and / or provide various storage, database, and / or web services. Although shown as a single entity in Figure 2, server 206 may include and / or represent multiple servers functioning and / or operating in conjunction with one another.

[0036] Network 204 generally represents any medium or architecture capable of facilitating communication or data transfer. In one example, network 204 may facilitate communication between computing device 202 and server 206. In this example, network 204 may facilitate communication or data transfer using wireless and / or wired connections. Examples of network 204 include, but are not limited to, an intranet, a wide area network (WAN), a local area network (LAN), a personal area network (PAN), the Internet, Power Line Communications (PLC), a cellular network (e.g., a Global System for Mobile Communications (GSM) network), one or more portions thereof, one or more variations or combinations thereof, or any other suitable network.

[0037] Many other devices or subsystems may be connected to system 100 of Figure 1 and / or system 200 of Figure 2. Conversely, not all of the components and devices shown in Figures 1 and 2 need be present to practice the embodiments described and / or illustrated herein. Also, the above-referenced devices and subsystems may be interconnected in ways different from that shown in Figure 2. Furthermore, system 100 and system 200 may employ any number of software, firmware, and / or hardware configurations. For example, one or more of the exemplary embodiments disclosed herein may be encoded as a computer program (also referred to as computer software, a software application, computer-readable instructions, and / or computer control logic) on a computer-readable medium.

[0038] As used herein, the term "computer-readable medium" generally refers to any form of device, carrier, or medium capable of storing or carrying computer-readable instructions. Examples of computer-readable media include, but are not limited to, transmission-type media such as carrier waves, and non-transitory-type media such as magnetic storage media (e.g., hard disk drives, tape drives, and floppy disks), optical storage media (e.g., compact disks (CDs), digital video disks (DVDs), and Blu-ray disks), electronic storage media (e.g., solid-state drives and flash media), and other distribution systems.

[0039] Figure 3 is a flow diagram of an example computer-implemented method 300 for chiplet synchronization. The steps illustrated in Figure 3 may be performed by any suitable computer-executable code and / or computing system, including system 100 of Figure 1, system 200 of Figure 2, and / or variations or combinations of one or more thereof. In one example, each of the steps illustrated in Figure 3 may represent an algorithm whose structure includes and / or is represented by multiple sub-steps, examples of which are provided in more detail below.

[0040] 3, one or more of the systems described herein may reach a synchronization barrier at step 302. For example, the synchronization barrier observation module 104, as part of the computing device 202 of FIG. 2, may detect that a chiplet involved in performing the operations of a process may reach a synchronization barrier.

[0041] The term "synchronization barrier," as used herein, generally refers to a type of synchronization method in which a barrier for a group of processes in source code means that any process must stop at this point and cannot move forward until all other processes have reached the barrier. Examples of synchronization barriers include, but are not limited to, implicit barriers imposed by collective routines and directive-based parallel languages, latches used in parallel computing where the barrier has a raised or lowered state and cannot be raised again once in the lowered state, and countdown latches that automatically lower once a predetermined number of processes have arrived.

[0042] As used herein, the term "process" generally refers to a minimum sequence of programmed instructions that can be managed independently by a scheduler that is typically part of an operating system. Examples of processes include, but are not limited to, components (e.g., threads) of a process. Multiple threads of a given process may execute simultaneously, sharing resources such as memory (through multithreading), but different processes do not share these resources. The threads of a process may share their executable code and the values ​​of their dynamically allocated variables and non-thread-local global variables at any given time.

[0043] As used herein, the term "operation" generally refers to an action that is performed to accomplish a given task. Examples of operations include, but are not limited to, input, processing, output, storage, and control.

[0044] The systems described herein may perform step 302 in various ways. In some examples, the synchronization barrier observation module 104, as part of the computing device 202 of FIG. 2, can observe that a chiplet has performed process operations until it reaches a synchronization barrier. Performing process operations can include the chiplet exchanging data with other chiplets over a data network connecting the chiplets, where the on-chip network can be implemented as a parallel control network that avoids traffic congestion on the data network. In some of these examples, the synchronization barrier observation module 104, as part of the computing device 202 of FIG. 2, can detect an event or receive a notification indicating that a synchronization barrier has been reached. In additional or alternative examples, the synchronization barrier observation module 104, as part of the computing device 202 of FIG. 2, can push one or more outgoing-only control messages to other chiplets over the on-chip network in response to the chiplet reaching a synchronization barrier.

[0045] One or more of the systems described herein may receive a dedicated control message at step 304. For example, the control message receiving module 106, as part of the computing device 202 of FIG. 2, may receive a dedicated control message pushed to the chiplet by other chiplets involved in performing operations of a process, the dedicated control message being pushed over a control network by the other chiplets.

[0046] As used herein, the term "dedicated control message" generally refers to a message that includes requests, commands, and / or notifications that affect the operation of a chiplet. Examples of dedicated control messages include, but are not limited to, broadcast, multicast, and / or narrowcast messages, including requests regarding the current state of the chiplet (e.g., awake, sleep, etc.), commands to change state (e.g., wake up, etc.), notifications regarding synchronization, etc.

[0047] As used herein, the term “pushed” generally refers to a push mechanism that performs a transmission to a receiver rather than in response to a request from the receiver. Examples of the use of a push mechanism include, but are not limited to, broadcasting, multicasting, or narrowcasting a message by a sender in response to the satisfaction of a condition at the sender and / or the occurrence of an event (e.g., reaching a synchronization barrier). While push mechanisms often involve receivers subscribing to receive pushed messages from a sender, a broadcast push to all chiplets can be performed without requiring a subscription. If the chiplets involved in performing operations for a process know which other chiplets are involved in performing operations for the process, and if the control network has a switch fabric implementation, a multicast or narrowcast push to other chiplets can be performed without requiring a subscription.

[0048] As used herein, the term "control network" generally refers to a network that has characteristics of a data network but is used primarily (e.g., exclusively) to communicate control messages. Examples of on-chip networks include, but are not limited to, a control network implemented in parallel with a data network, an on-chip network (e.g., integrated on the same chip (i.e., the same piece of silicon) as chiplets and / or chiplet packages), and / or an inter-chip (e.g., socket-to-socket) control network that provides connectivity between chiplets implemented on different chips. In some of these examples, the control network may provide point-to-point connections, provide a shared broadcast bus, have a hierarchical tree topology, have another topology, etc.

[0049] As used herein, the term "point-to-point connection" generally refers to a communication connection between two communication endpoints or nodes. Examples of point-to-point connections include, but are not limited to, physical (i.e., hardwired) connections and virtual connections, which avoid the need for a physical connection between every node (e.g., a chiplet) and every other node (e.g., another chiplet) and have no round-trip time because messaging is direct rather than indirect.

[0050] The systems described herein may perform step 304 in various ways. In some examples, the control message receiving module 106, as part of the computing device 202 of FIG. 2, can receive dedicated control messages from each of the other chiplets. In some of these examples, the control message receiving module 106, as part of the computing device 202 of FIG. 2, can receive dedicated control messages using a local dispatcher for the chiplet. In additional or alternative examples, the control message receiving module 106, as part of the computing device 202 of FIG. 2, can cause a chiplet to maintain a set of counters that includes at least one counter for each of the other chiplets. In some of these examples, the control message receiving module 106, as part of the computing device 202 of FIG. 2, can increment a counter of the set of counters in response to receiving the dedicated control message.

[0051] One or more of the systems described herein may advance a synchronization control barrier in step 306. For example, the synchronization barrier advancement module 108, as part of the computing device 202 of FIG. 2, may advance the synchronization barrier by a chiplet in response to receiving a dedicated control message.

[0052] The systems described herein may perform step 306 in a variety of ways. In some examples, the synchronization barrier advancement module 108, as part of the computing device 202 of FIG. 2, may advance the synchronization barrier in response to all counters in the set of counters being incremented in step 304. In some of these examples, the synchronization barrier advancement module 108, as part of the computing device 202 of FIG. 2, may further advance the synchronization barrier in response to reaching the synchronization barrier in step 302.

[0053] 4, chiplet package 400 may include a processing unit 402 (e.g., a central processing unit, a graphics processing unit, etc.) that executes processes, such as processes 404 and 406. Chiplet package 400 may also include chiplets 408-422 with local dispatchers 424-436 that exchange various messages over a data network 438 and a parallel on-chip network 440. For example, local dispatchers 424-436 may exchange data messages related to process operation over data network 438 and dedicated control messages over parallel on-chip network 440.

[0054] The parallel on-chip network 440 can provide connectivity between the chiplets 408-424 and / or the processing unit 402 in various ways. For example, the parallel on-chip network 440 can provide virtual point-to-point connectivity by utilizing a communication medium having a switch fabric that can route dedicated control messages in a narrowcast, multicast, and / or broadcast manner. Alternatively, the parallel on-chip network 440 can include a communication medium (e.g., a shared broadcast bus) over which dedicated control messages are transmitted in a broadcast manner, employing collision handling procedures similar to those used in optical and / or wireless networks. For example, if two or more chiplets perform simultaneous transmissions that result in transmission collisions, the two or more chiplets can locally implement randomized delays to detect the collision and retry their respective transmissions. Alternatively, the network 440 can have a hierarchical tree topology or another topology.

[0055] In one example, processing unit 402 can assign tasks to perform operations of process 404 to chiplets 408-416 and tasks to perform operations of process 406 to chiplets 418-424. These assignments form virtual machines, one of which includes chiplets 408-416 and the other of which includes chiplets 418-424. The assignments can inform each chiplet of the identity of each of the other chiplets in the same virtual machine. In some examples, a chiplet can broadcast a dedicated control message to all other chiplets identifying the chiplet as a sender and indicating that the chiplet has reached a synchronization barrier. A first portion of the other chiplets can recognize the chiplet's identity as a sender, have knowledge that the chiplet is not in the same virtual machine as the first portion of the other chiplets, and ignore the dedicated control message. A second portion of the other chiplets can recognize the chiplet's identity as a sender, have knowledge that the chiplet is in the same virtual machine as the second portion of the other chiplets, and advance their respective synchronization barriers at least in part in response to the dedicated control message. In another example, a chiplet can multicast a dedicated control message to other chiplets assigned to the same virtual machine as the chiplet, where the message can identify the chiplet as the sender and indicate that the chiplet has reached a synchronization barrier. Other chiplets that receive the multicast dedicated control message and recognize the identity of the chiplet as the sender can advance their respective synchronization barriers at least in part in response to the multicast dedicated control message. In another example, a chiplet can narrowcast a dedicated control message to each of the other chiplets assigned to the same virtual machine as the chiplet, where the message can identify the chiplet as the sender and indicate that the chiplet has reached a synchronization barrier.Other chiplets that receive the narrowcast dedicated control message and recognize the identity of the chiplet as the sender may advance their respective synchronization barriers at least in part in response to the narrowcast dedicated control message.

[0056] 5, a chiplet processor 500 (e.g., chiplet 408 of FIG. 4) may implement a thread operation process 502 that includes sending and receiving a data message 504 and an outgoing data message 506 over a data network (e.g., data network 438 of FIG. 4). The thread operation process 502 may observe a synchronization barrier 508 and provide notification 510 that the barrier has been reached. This notification may trigger one or more local dispatchers (e.g., local dispatcher 424 of FIG. 4) to send one or more outgoing-only control messages 512 over a parallel on-chip control network (e.g., on-chip network 440 of FIG. 4) to other chiplet processors (e.g., chiplets 426-432 of FIG. 4) involved in performing the operation of the same process (e.g., process 404 of FIG. 4) as chiplet processor 500.

[0057] Chiplet processor 500 may also implement a synchronization process 514 that receives notification 510 and / or observes events associated with the transmission of notification 510 and / or outgoing dedicated control message 512. Synchronization process 514 may also maintain and manage set of counters 518 that includes a counter for each other chiplet processor involved in performing operations for the same process. For example, synchronization process 514 may maintain and manage a set of four counters, one for each other chiplet processor assigned to the same virtual machine as chiplet processor 500. When one or more local dispatchers receive a dedicated control message from each of the other chiplet processors, synchronization process 514 may increment (e.g., raise high) the respective counter maintained and managed by synchronization process 514. In response to all counters in set of counters 518 being incremented and in response to notification 510, synchronization process 514 may advance barrier 508 at 520. The advancement of the barrier 508 allows the thread operating process 502 to continue executing the process's operations until it reaches the advanced barrier.

[0058] As described above, the disclosed system and method implements multi-client barriers using hardware blocks connected via a parallel on-chip network used as a control bus. Typically, such multi-client barriers are contained in shared memory locations. Managing these barrier objects in shared memory locations poses many challenges. For example, accessing a shared layer of memory requires long latency and high energy because the shared memory location is at a system coherence point and potentially requires dynamic random-access memory (DRAM) accesses. Furthermore, utilizing memory-mapped input / output (MMIO) hardware mapped to memory locations still requires a long traversal of the data fabric hierarchy to access the shared coherence point. Also, using regular memory-backed structures to store synchronization objects requires loading the current value into a core, updating the value, and then storing the new value to a location in memory. These operations add latency and consume energy. Furthermore, requests to synchronization objects can be extremely time-critical and share bus resources with regular memory requests on the on-chip fabric. Furthermore, access to a synchronization object utilizes a "pull" method, since all clients wishing to perform synchronization must "pull" the object from its memory address. If there is no synchronization hardware on the other side, this "pull" method results in a spin loop, which consumes energy and introduces noise on the shared data bus.

[0059] The disclosed system and method instead maintain and manage synchronization objects within hardware connected to the parallel on-chip network, providing various benefits. For example, this embodiment allows clients to “push” updates to other clients that share the synchronization object. Advantageously, clients can broadcast and / or multicast dedicated control messages to all other receiving clients, so that only a single message is needed to acquire or release a lock or arrive / wait at a barrier. Additionally, by implementing a command bus on the parallel on-chip network, chiplets can avoid waiting behind other memory accesses when attempting to perform these latency-critical synchronization operations, potentially optimizing routing for a limited number of clients that specifically need to perform synchronization. Also, achieving low-power operation is facilitated by avoiding the need to utilize a larger, less energy-efficient data fabric for fast synchronization queries. Furthermore, implementing a multi-client barrier on the parallel on-chip network facilitates limiting interference between virtual machines that share the same data fabric path to memory. For example, two multi-client partitions can share a single memory system, with each partition being used by a separate virtual machine. If both of these partitions need to use a shared memory system to execute the barrier, high memory system usage from one virtual machine can cause additional hardware synchronization latency to another virtual machine due to synchronization using shared data path resources. Such synchronization latency is undesirable. Utilizing a parallel on-chip network for synchronization improves this undesirable latency because the client is under firmware or hardware control and experiences less interference from data messages.

[0060] While the foregoing disclosure describes various embodiments using specific block diagrams, flow diagrams, and examples, each block diagram element, flow diagram step, operation, and / or component described and / or shown herein can be implemented, individually and / or collectively, using a wide variety of hardware, software, or firmware (or any combination thereof) configurations. Additionally, any disclosure of components stored within other components shall be considered exemplary in nature, as many other architectures may be implemented to achieve the same functionality.

[0061] In some examples, all or a portion of the example system 100 of Figure 1 may represent part of a cloud computing or network-based environment. A cloud computing environment may provide various services and applications over the Internet. These cloud-based services (e.g., software as a service, platform as a service, infrastructure as a service, etc.) may be accessible through a web browser or other remote interface. Various functionality described herein may be provided through a remote desktop environment or any other cloud-based computing environment.

[0062] In various embodiments, all or a portion of the example system 100 of FIG. 1 can facilitate multi-tenancy within a cloud-based computing environment. In other words, the modules described herein can configure a computing system (e.g., a server) to facilitate multi-tenancy for one or more of the functions described herein. For example, one or more of the modules described herein can program a server to allow two or more clients (e.g., customers) to share an application running on the server. A server so programmed can share applications, operating systems, processing systems, and / or storage systems among multiple customers (i.e., tenants). Additionally, one or more of the modules described herein can partition data and / or configuration information of a multi-tenant application by customer, such that one customer cannot access data and / or configuration information of another customer.

[0063] According to various embodiments, all or a portion of the example system 100 of Figure 1 may be implemented within a virtual environment. For example, the modules and / or data described herein may reside and / or execute within a virtual machine. As used herein, the term "virtual machine" generally refers to any operating system environment that is abstracted from computing hardware by a virtual machine manager (e.g., a hypervisor).

[0064] In some examples, all or a portion of the example system 100 of FIG. 1 may represent a portion of a mobile computing environment. The mobile computing environment may be implemented by a wide range of mobile computing devices, including mobile phones, tablet computers, e-readers, personal digital assistants, wearable computing devices (e.g., computing devices with head-mounted displays, smart watches, etc.), one or more variations or combinations thereof, or any other suitable mobile computing device. In some examples, the mobile computing environment may have one or more different capabilities, including, for example, dependence on battery power, presenting only one foreground application at any given time, remote management capabilities, touchscreen capabilities, location and movement data (e.g., provided by a global positioning system, gyroscope, accelerometer, etc.), a restricted platform that restricts system-level configuration changes and / or limits the ability of third-party software to inspect the behavior of other applications, controls that restrict application installation (e.g., provided only from approved application stores), etc. The various capabilities described herein may be provided to and / or interact with the mobile computing environment.

[0065] The process parameters and order of steps described and / or illustrated herein are provided by way of example only and can be changed as desired. For example, although the steps illustrated and / or described herein may be illustrated or described in a particular order, these steps do not necessarily have to be performed in the order illustrated or described. The various exemplary methods described and / or illustrated herein can also omit one or more of the steps described or illustrated herein or can include additional steps in addition to those disclosed.

[0066] Although various embodiments have been described and / or illustrated herein in the context of a fully functional computing system, one or more of these exemplary embodiments may be distributed as a program product in various forms, regardless of the particular type of computer-readable medium used to actually execute the distribution. The embodiments disclosed herein may also be implemented using modules that perform certain tasks. These modules may include scripts, batch files, or other executable files that may be stored on a computer-readable storage medium or within a computing system. In some embodiments, these modules may configure a computing system to execute one or more of the exemplary embodiments disclosed herein.

[0067] The foregoing description is provided to enable those skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many changes and modifications are possible without departing from the spirit and scope of the present disclosure. The embodiments disclosed herein should be considered in all respects as illustrative and not restrictive. In determining the scope of the present disclosure, reference should be made to the appended claims and their equivalents.

[0068] Unless otherwise specified, the terms "connected to" and "coupled to" (and their derivatives) as used in this specification and claims should be interpreted as allowing both direct and indirect connections (i.e., via other elements or components). Additionally, the terms "a" or "an" as used in this specification and claims should be interpreted as meaning "at least one of." Finally, for ease of use, the terms "including" and "having" (and their derivatives) as used in this specification and claims are interchangeable with the term "comprising," and have the same meaning.

Claims

1. 1. A computer-implemented method comprising: At least a portion of the method is performed by a computing device comprising a plurality of chiplets; The method comprises: the chiplets involved in executing the operations of the process reaching a synchronization barrier; receiving, by the chiplet, dedicated control messages pushed to the chiplet by other chiplets involved in performing operations of the process, the dedicated control messages being pushed by the other chiplets over a control network; the chiplet advancing the synchronization barrier in response to receiving the dedicated control message. method.

2. the control network corresponds to an on-chip network providing connectivity between the chiplet and at least one of the other chiplets; 10. The method of claim 1.

3. the connection is a point-to-point connection; The method of claim 2.

4. the control network corresponds to a separate control network implemented in parallel with a separate data network that also provides connectivity between the chiplet and at least one of the other chiplets. The method of claim 2.

5. The chiplet and at least one of the other chiplets are implemented on different chips.

10. The method of claim 1.

6. the chiplet pushing one or more originating-only control messages in response to reaching the synchronization barrier; the one or more outgoing-only control messages are pushed to the other chiplets via the control network.

10. The method of claim 1.

7. the chiplet maintaining a set of counters including at least one counter for each of the other chiplets.

10. The method of claim 1.

8. incrementing a counter of the set of counters in response to receiving the dedicated control message. The method of claim 7.

9. advancing the synchronization barrier occurs in response to reaching the synchronization barrier.

10. The method of claim 1.

10. 1. A system comprising: a chiplet processor; a physical memory containing computer-executable instructions; The computer-executable instructions, when executed by the chiplet processor in performing the operations of a process, the chiplets involved in executing the operations of the process reaching a synchronization barrier; receiving, by the chiplet, dedicated control messages pushed to the chiplet by other chiplets involved in performing operations of the process, the dedicated control messages being pushed by the other chiplets over a control network; the chiplet advancing the synchronization barrier in response to receiving the dedicated control message; causing the chiplet processor to perform system.

11. the control network corresponds to an on-chip network providing connectivity between the chiplet and at least one of the other chiplets; The system of claim 10.

12. the connection is a point-to-point connection; The system of claim 11.

13. the control network corresponds to a separate control network implemented in parallel with a separate data network that also provides connectivity between the chiplet and at least one of the other chiplets. The system of claim 11.

14. The chiplet and at least one of the other chiplets are implemented on different chips. The system of claim 10.

15. The computer-executable instructions include: causing the chiplet processor to push one or more outgoing-only control messages in response to reaching the synchronization barrier, the one or more outgoing-only control messages being pushed to the other chiplets via the control network. The system of claim 10.

16. The computer-executable instructions include: causing the chiplet processor to maintain a set of counters including at least one counter for each of the other chiplets; The system of claim 10.

17. The computer-executable instructions include: causing the chiplet processor to increment a counter of the set of counters in response to receiving the dedicated control message; 17. The system of claim 16.

18. advancing the synchronization barrier occurs in response to reaching the synchronization barrier. The system of claim 10.

19. A computer-readable storage medium containing one or more computer-executable instructions, The computer-executable instructions, when executed by a chiplet processor to perform the operations of a process, the chiplets involved in executing the operations of the process reaching a synchronization barrier; receiving, by the chiplet, dedicated control messages pushed to the chiplet by other chiplets involved in performing operations of the process, the dedicated control messages being pushed by the other chiplets over a control network; the chiplet advancing the synchronization barrier in response to receiving the dedicated control message; causing the chiplet processor to perform A computer-readable storage medium.

20. the control network corresponds to an on-chip network providing connectivity between the chiplet and at least one of the other chiplets; 20. The computer-readable storage medium of claim 19.

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