Indication device

Abstract

The display device may include first, second, and third sub-pixels adjacent to each other, each including a storage capacitor, a scan line extending in a first direction and selectively transmitting a scan signal and a control signal to each of the first, second, and third sub-pixels, a data line extending in the second direction intersecting the first direction and transmitting a data signal to each of the first, second, and third sub-pixels, and a first power line electrically connected to each of the first, second, and third sub-pixels and supplied with a first driving power voltage. The first power line may be located between the storage capacitor and the data line.

Description

[Technical Field]

[0001] The present invention relates to a display device. [Background technology]

[0002] 2. Description of the Related Art In recent years, with the growing interest in information displays, research and development into display devices has been continuously carried out. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention can provide a display device with improved reliability. [Means for solving the problem]

[0004] A display device according to an embodiment may include first, second, and third sub-pixels adjacent to each other, each including a storage capacitor; scan lines extending in a first direction and selectively transmitting scan signals and control signals to each of the first, second, and third sub-pixels; data lines extending in a second direction intersecting the first direction and transmitting data signals to each of the first, second, and third sub-pixels; and first power lines electrically connected to each of the first, second, and third sub-pixels and supplied with a first driving power voltage. The first power lines may be located between the storage capacitors and the data lines.

[0005] In an embodiment, the display device may further include a substrate; a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer sequentially disposed on the substrate; a second power wiring supplied with a second driving power voltage different from the first driving power voltage; and an initialization power wiring supplied with an initialization power voltage. The first power wiring may include a first vertical power wiring configured as a first conductive layer disposed on the substrate and a first horizontal power wiring configured as a second conductive layer disposed on the second insulating layer. When viewed in a plan view, the first vertical power wiring may be located between the storage capacitor and the data line of each of the first, second, and third sub-pixels.

[0006] In this embodiment, each of the first, second, and third sub-pixels may include a light-emitting element; a first transistor controlling a current of the light-emitting element; a second transistor connected between the data line and a gate electrode of the first transistor and turned on by the scan signal; a third transistor connected between the initialization power line and a source electrode of the first transistor and turned on by the control signal; and the storage capacitor including a lower electrode electrically connected to the gate electrode of the first transistor and the source electrode of the second transistor, and an upper electrode electrically connected to the source electrode of the first transistor and the source electrode of the third transistor.

[0007] In an embodiment, the first, second, and third transistors may be located on one side of the storage capacitor.

[0008] In an embodiment, the second power wiring may include a second vertical power wiring configured as the first conductive layer and a second horizontal power wiring configured as the second conductive layer. In a plan view, the storage capacitor may be located between the second vertical power wiring and the first vertical power wiring.

[0009] In the embodiment, the initialization power line may be located between the first vertical power line and the data line in plan view.

[0010] In an embodiment, the gate electrode of the first transistor of each of the first, second, and third sub-pixels may be disposed between the storage capacitor and the first vertical power line.

[0011] In an embodiment, the lower electrode may be disposed on the substrate, and the upper electrode may be disposed on the first insulating layer and overlap the lower electrode with the first insulating layer sandwiched therebetween.

[0012] In an embodiment, the top electrode may be disposed in the same layer as the active patterns of the first, second and third transistors.

[0013] In an embodiment, the upper electrode may be integrally formed with the source electrode of the first transistor and the source electrode of the third transistor.

[0014] In an embodiment, the light-emitting element may include a first electrode configured as a third conductive layer disposed on the fourth insulating layer; a light-emitting layer disposed on the first electrode; and a second electrode disposed on the light-emitting layer.

[0015] In the embodiment, the first electrode may be electrically connected to the source electrode of the first transistor via a contact portion that penetrates the second to fourth insulating layers.

[0016] In the embodiment, the initialization power line may be located between the second vertical power line and the storage capacitor in plan view.

[0017] In the embodiment, the initialization power line may be located on one side of the storage capacitor, and the first vertical power line may be located on the other side of the storage capacitor, as viewed in a plane.

[0018] In the embodiment, when viewed in a plane, the third transistor of the first, second, and third transistors may be located on one side of the storage capacitor, and the first and second transistors may be located on the other side of the storage capacitor.

[0019] In an embodiment, each of the first, second, and third sub-pixels may further include an encapsulation layer disposed on the light-emitting element; a color filter layer disposed on the encapsulation layer; and an overcoat layer disposed on the color filter layer.

[0020] A display device according to an embodiment may include: a substrate; first, second, third, and fourth insulating layers sequentially stacked on the substrate; first, second, and third sub-pixels, each including a pixel circuit including a storage capacitor and first, second, and third transistors disposed on the substrate, and a light-emitting element electrically connected to the pixel circuit; scan lines disposed on the substrate and selectively transmitting scan signals and control signals to the first, second, and third sub-pixels; data lines transmitting data signals to the first, second, and third sub-pixels; a first power supply line supplied with a first power supply voltage; a second power supply line supplied with a second power supply voltage different from the first power supply voltage; and an initialization power supply line supplied with an initialization power supply voltage different from the first and second power supply voltages. A gate electrode of the first transistor may be located between the storage capacitor and the first power supply line.

[0021] In an embodiment, the first power wiring may include a first vertical power wiring disposed on the substrate and a first horizontal power wiring disposed on the second insulating layer, and the first vertical power wiring may be located between the storage capacitor and the data wiring.

[0022] In an embodiment, the first, second, and third transistors may be located on one side of the storage capacitor in a plan view.

[0023] In the embodiment, the storage capacitor may be located between the initialization power line and the first vertical power line in plan view. [Effects of the Invention]

[0024] According to the embodiment, the first vertical power supply wiring is arranged between the storage capacitor of each subpixel and the data wiring, thereby reducing the area of ​​the gate electrode of the first transistor (or driving transistor) of each subpixel and ensuring the area of ​​the storage capacitor.

[0025] According to the embodiment, it is possible to provide a display device with improved reliability by increasing the capacitance of the storage capacitor of each sub-pixel.

[0026] The effects of the embodiments are not limited to the above-mentioned examples, and various other effects are included in the present specification. [Brief explanation of the drawings]

[0027] [Figure 1] 1 is a schematic plan view showing a display device according to an embodiment; [Figure 2] FIG. 2 is a schematic cross-sectional view showing the display panel of FIG. [Figure 3] 2 is a schematic circuit diagram showing the electrical connections of components included in each pixel shown in FIG. 1. FIG. [Figure 4] FIG. 2 is a schematic plan view showing a pixel according to an embodiment. [Figure 5] FIG. 2 is a schematic plan view showing a pixel according to an embodiment. [Figure 6] FIG. 6 is a schematic plan view showing only the components included in the first conductive layer in the pixel of FIG. 5; [Figure 7] 6 is a schematic plan view showing only components included in a transistor and a second conductive layer in the pixel of FIG. 5. FIG. [Figure 8] FIG. 6 is a schematic cross-sectional view taken along line I-I' in FIG. [Figure 9] FIG. 6 is a schematic cross-sectional view taken along line II-II' in FIG. [Figure 10] FIG. 6 is a schematic cross-sectional view taken along line II-II' in FIG. [Figure 11] 6 is a schematic cross-sectional view showing a pixel according to an embodiment, taken along line I-I' in FIG. 5. FIG. [Figure 12] FIG. 2 is a schematic plan view showing a pixel according to an embodiment. [Figure 13] 13 is a schematic plan view showing only the components included in the first conductive layer in the pixel of FIG. 12. FIG. [Figure 14] 13 is a schematic plan view showing only components included in a transistor and a second conductive layer in the pixel of FIG. 12. FIG. [Figure 15] FIG. 13 is a schematic cross-sectional view taken along line III-III' in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0028] Although the present invention is susceptible to various modifications and can be embodied in various forms, only specific embodiments are illustrated in the drawings and the present disclosure will be described based on these. However, the present invention is not limited to the specific disclosed embodiments, and it should be understood that all modifications, equivalents, and alternatives falling within the technical scope of the present invention are included in the present invention.

[0029] In the description of each drawing, like reference numerals are used for like elements. In the accompanying drawings, the dimensions of structures are exaggerated for clarity of the present disclosure. Terms such as "first," "second," etc. are used to describe various elements, but the elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be referred to as a "second element," and similarly, a second element can be referred to as a "first element" without departing from the scope of the present disclosure.

[0030] In this application, the use of terms such as "comprises" or "has" specifies the presence of a specified feature, numeral, step, operation, component, part, or combination thereof, and does not preclude the presence or addition of one or more other features, numerals, steps, operations, components, parts, or combinations thereof. Furthermore, when a layer, film, region, plate, or other portion is described as being "on" another portion, this includes not only the case where it is "directly on" the other portion, but also the case where another portion is located between them. Furthermore, in this specification, when a layer, film, region, plate, or other portion is described as being formed on another portion, this does not mean that it is formed only in an upward direction, but also includes the case where it is formed in a lateral or downward direction. Conversely, when a layer, film, region, plate, or other portion is described as being "under" another portion, this includes not only the case where it is "directly under" the other portion, but also the case where another portion is located between them.

[0031] In this application, when it is stated that a certain component (for example, a 'first component') is 'operatively or communicatively coupled with / to' or 'connected to' another component (for example, a 'second component'), it should be understood that the certain component may be directly connected to the other component or may be connected via another component (for example, a 'third component'). On the other hand, when it is stated that a certain component (for example, a 'first component') is 'directly connected' or 'directly connected to' another component (for example, a 'second component'), it can be understood that there is no other component (for example, a 'third component') between the certain component and the other component.

[0032] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, along with other matters necessary for those skilled in the art to easily understand the contents of the present invention. In the following description, the singular expression also includes the plural expression unless the context clearly indicates that only the singular is included.

[0033] FIG. 1 is a schematic plan view showing a display device DD according to an embodiment, and FIG. 2 is a schematic cross-sectional view showing a display panel DP of FIG.

[0034] 1 and 2, for convenience, the structure of the display device DD, particularly the display panel DP provided in the display device DD, is simply shown with a display area DA where an image is displayed at the center.

[0035] 1 and 2, for convenience, the structure of a display device DD, particularly a display panel DP included in the display device DD, is simply shown with a display area DA where an image is displayed at the center.

[0036] 1 and 2, the display panel DP (or display device DD) according to the embodiment may be provided in various shapes. For example, the display panel DP may be provided in a rectangular plate shape having two pairs of parallel sides. However, the present invention is not limited thereto. When the display panel DP is provided in a rectangular plate shape, one pair of the two pairs of sides may be longer than the other pair of sides.

[0037] At least a portion of the display panel DP may have flexibility, and the flexible portion may be folded, but is not limited thereto.

[0038] The display panel DP can display images. The display panel DP may be a self-emissive display panel, such as an organic light-emitting display panel (OLED panel) using organic light-emitting diodes (OLEDs) as light-emitting elements, a micro-LED or nano-LED display panel using micro-LEDs as light-emitting elements, or a quantum dot organic light-emitting display panel (QD OLED panel) using quantum dots and organic light-emitting diodes. Alternatively, the display panel DP may be a non-emissive display panel, such as a liquid crystal display panel (LCD panel), an electrophoretic display panel (EPD panel), or an electrowetting display panel (EWD panel). When a non-emissive display panel is used as the display panel DP, the display device DD may include a backlight unit that supplies light to the display panel DP. In an embodiment, the display panel DP may be an organic light-emitting display panel.

[0039] The display panel DP can include a substrate SUB and pixels PXL provided on the substrate SUB.

[0040] The substrate SUB may include a transparent insulating material to allow light to pass through, but is not limited to this. The substrate SUB may be a rigid substrate or a flexible substrate.

[0041] The rigid substrate may be, for example, any one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystalline glass substrate.

[0042] The flexible substrate may be one of a film substrate containing a polymer organic material and a plastic substrate, for example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate.

[0043] One region of the substrate SUB may be provided as a display area DA in which the pixels PXL are arranged, and the remaining region of the substrate SUB may be provided as a non-display area NDA. As an example, the substrate SUB may include a display area DA including pixel areas PXA in which the pixels PXL are arranged, and a non-display area NDA arranged around the display area DA (or adjacent to the display area DA).

[0044] The non-display area NDA may be located adjacent to the display area DA. The non-display area NDA may be provided on at least one side of the display area DA. For example, the non-display area NDA may surround (or surround) the periphery (or edge) of the display area DA. The non-display area NDA may be provided with wiring sections connected to each pixel PXL and driving sections connected to the wiring sections for driving the pixels PXL.

[0045] Each of the pixels PXL may be provided within the display area DA of the substrate SUB. The pixel PXL may include a light-emitting element that emits white light and / or colored light and a pixel circuit for driving the light-emitting element. The pixel circuit may include at least one transistor electrically connected to the light-emitting element. Each of the pixels PXL may emit light of one of the colors red, green, and blue, but is not limited thereto. Each of the pixels PXL may also emit light of one of the colors cyan, magenta, yellow, and white.

[0046] A plurality of pixels PXL may be provided and arranged in a matrix along pixel rows extending in a first direction DR1 and pixel columns extending in a second direction DR2 intersecting the first direction DR1. The arrangement of the pixels PXL is not particularly limited, and the pixels PXL may be arranged in various forms. According to an embodiment, when a plurality of pixels PXL are provided, the pixels PXL may be provided to have different areas (or sizes). For example, in the case of pixels PXL that emit different colors of light, the pixels PXL may be provided to have different areas (or sizes) or different shapes for each color.

[0047] The driving unit can provide a predetermined signal and a predetermined voltage to each pixel PXL through the wiring unit to control driving of the pixel PXL.

[0048] The display panel DP (or each of the pixels PXL) may include a pixel circuit layer PCL, a display element layer DPL, and a encapsulation layer TFE located on a substrate SUB.

[0049] The pixel circuit layer PCL is provided on the substrate SUB and may include transistors and signal wiring connected to the transistors. For example, the transistor may have a structure in which an active pattern (or semiconductor pattern), a gate electrode, a source electrode, and a drain electrode are stacked in this order with an insulating layer sandwiched therebetween. The semiconductor pattern may include amorphous silicon, polysilicon, low-temperature polysilicon, an organic semiconductor, and / or an oxide semiconductor. The gate electrode, the source electrode, and the drain electrode may include, but are not limited to, one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo). For example, the pixel circuit layer PCL may include at least one insulating layer.

[0050] A display element layer DPL may be disposed on the pixel circuit layer PCL. The display element layer DPL may include a light-emitting element that emits light. The light-emitting element may be, for example, an organic light-emitting diode (OLED), but is not limited thereto. According to an embodiment, the light-emitting element may be an inorganic light-emitting element containing an inorganic light-emitting material, or a light-emitting element that emits light by changing the wavelength of the emitted light using quantum dots.

[0051] An encapsulating layer TFE may be disposed on the display element layer DPL. The encapsulating layer TFE may be a encapsulating substrate or may be in the form of a encapsulating film made of multiple layers. When the encapsulating layer TFE is in the form of a encapsulating film, it may include an inorganic film and / or an organic film. For example, the encapsulating layer TFE may be in the form of an inorganic film, an organic film, and another inorganic film stacked in this order. The encapsulating layer TFE can prevent external air and moisture from penetrating into the display element layer DPL and the pixel circuit layer PCL.

[0052] FIG. 3 is a schematic circuit diagram showing the electrical connections of the components included in each of the pixels PXL shown in FIG.

[0053] For convenience, FIG. 3 shows a pixel PXL located in the ith pixel row (or ith horizontal line) and the jth pixel column (where i and j are natural numbers).

[0054] 1 to 3, the pixel PXL may include a light emitting unit EMU that generates light of a brightness corresponding to a data signal. For example, the pixel PXL may further include a pixel circuit PXC for driving the light emitting unit EMU.

[0055] The light emitting unit EMU may include a light emitting element LD connected between a first power supply wiring PL1 supplied with a first driving power supply voltage VDD and a second power supply wiring PL2 supplied with a second driving power supply voltage VSS. For example, the light emitting unit EMU may include a pixel circuit PXC and a light emitting element LD including a first electrode AE ​​connected to the first driving power supply voltage VDD via the first power supply wiring PL1 and a second electrode CE connected to the second driving power supply voltage VSS via the second power supply wiring PL2. The first electrode AE ​​may be an anode, and the second electrode CE may be a cathode. The first driving power supply voltage VDD and the second driving power supply voltage VSS may have different potentials. In this case, the potential difference between the first and second driving power supply voltages VDD and VSS may be set to be equal to or greater than the threshold voltage of the light emitting element LD during the light emitting period of the pixel PXL.

[0056] When a pixel PXL (or sub-pixel) is located in the i-th pixel row and the j-th pixel column in the display area DA, the pixel circuit PXC of the pixel PXL (or sub-pixel) may be electrically connected to the i-th scan line Si and the j-th data line Dj, and may also be electrically connected to the i-th control line CLi and the j-th sensing line SENj.

[0057] The pixel circuit PXC described above may include first to third transistors T1, T2, and T3 and a storage capacitor Cst.

[0058] The first transistor T1 is a driving transistor for controlling the driving current applied to the light-emitting element LD and may be electrically connected between a first driving power supply voltage VDD and the light-emitting element LD. Specifically, a first terminal of the first transistor T1 may be electrically connected to the first driving power supply voltage VDD via a first power supply wiring PL1, a second terminal of the first transistor T1 may be electrically connected to a second node N2, and a gate electrode of the first transistor T1 may be electrically connected to the first node N1. The first transistor T1 may control the amount of driving current applied to the light-emitting element LD from the first driving power supply voltage VDD via the second node N2 in accordance with the voltage applied to the first node N1. In an embodiment, the first terminal of the first transistor T1 may be a drain electrode, and the second terminal of the first transistor T1 may be a source electrode, but is not limited thereto. According to an embodiment, the first terminal may be a source electrode, and the second terminal may be a drain electrode.

[0059] The second transistor T2 may be electrically connected between a data line Dj (for example, the jth data line) and a first node N1 as a switching transistor that selects a pixel PXL in response to a scan signal and activates the pixel PXL. A first terminal of the second transistor T2 may be electrically connected to the data line Dj, a second terminal of the second transistor T2 may be electrically connected to the first node N1 (or the gate electrode of the first transistor T1), and a gate electrode of the second transistor T2 may be electrically connected to a scan line Si (or the i-th scan line). The first and second terminals of the second transistor T2 may be different terminals, and for example, if the first terminal is a drain electrode, the second terminal may be a source electrode.

[0060] The second transistor T2 is turned on when a scan signal of a gate-on voltage (e.g., a high-level voltage) is supplied from the scan line Si, and can electrically connect the data line Dj to the first node N1. The first node N1 is a point where the second terminal of the second transistor T2 and the gate electrode of the first transistor T1 are connected, and the second transistor T2 can transmit a data signal to the gate electrode of the first transistor T1.

[0061] The third transistor T3 electrically connects the first transistor T1 to a sensing line SENj (for example, the jth sensing line) to obtain a sensing signal via the sensing line SENj and detect characteristics of the pixel PXL, such as the threshold voltage of the first transistor T1, using the sensing signal. Information regarding the characteristics of the pixel PXL may be used to convert image data so that characteristic deviations between the pixels PXL can be compensated for. A second terminal of the third transistor T3 may be electrically connected to the second terminal of the first transistor T1, a first terminal of the third transistor T3 may be electrically connected to the sensing line SENj, and a gate electrode of the third transistor T3 may be electrically connected to a control line CLi (for example, the ith control line). The first terminal may be a drain electrode, and the second terminal may be a source electrode.

[0062] The third transistor T3 is an initialization transistor that can initialize the second node N2, and is turned on when a sensing control signal is supplied from the control line CLi to transfer the initialization power supply voltage to the second node N2, thereby initializing the storage capacitor Cst electrically connected to the second node N2.

[0063] The storage capacitor Cst may include a lower electrode LE (or a first storage electrode) and an upper electrode UE (or a second storage electrode). The lower electrode LE may be electrically connected to a first node N1, and the upper electrode UE may be electrically connected to a second node N2. The storage capacitor Cst charges a data voltage corresponding to a data signal supplied to the first node N1 during one frame period. Thus, the storage capacitor Cst may store a voltage corresponding to the difference between the voltage of the gate electrode of the first transistor T1 and the voltage of the second node N2.

[0064] 3 shows an example in which all of the first to third transistors T1, T2, and T3 are N-type transistors, but the present invention is not limited to this. For example, at least one of the first to third transistors T1, T2, and T3 may be changed to a P-type transistor.

[0065] The structure of the pixel circuit PXC can be implemented in various ways.

[0066] In the following examples, for convenience of explanation, the horizontal direction (X-axis direction or horizontal direction) on the plane is indicated as the first direction DR1, the vertical direction (Y-axis direction or vertical direction) on the plane is indicated as the second direction DR2, and the vertical direction on the cross section is indicated as the third direction DR3.

[0067] Figures 4 and 5 are schematic plan views showing a pixel PXL according to one embodiment, Figure 6 is a schematic plan view showing only the components included in the first conductive layer C1 in the pixel PXL of Figure 5, and Figure 7 is a schematic plan view showing only the components included in the transistors T1, T2, T3 and the second conductive layer C2 in the pixel PXL of Figure 5.

[0068] The pixel PXL shown in FIG. 5 further shows the first light-emitting region EMA1 of the first sub-pixel SPX1, the second light-emitting region EMA2 of the second sub-pixel SPX2, and the third light-emitting region EMA3 of the third sub-pixel SPX3 in the pixel PXL of FIG.

[0069] 1 to 7, a pixel PXL according to an embodiment may be arranged in a pixel area PXA, which is one area of ​​a display area DA. The pixel area PXA (or display area DA) may include a wiring area LA. As an example, the wiring area LA may be located between two pixels PXL arranged adjacent to each other in the same pixel column. In an embodiment, the wiring area LA may be an area in which signal lines extending in a first direction DR1 are arranged. As an example, a first horizontal power supply line PL1b, a scan line SC, and a second horizontal power supply line PL2b extending in the first direction DR1 (or horizontal direction) may be arranged in the wiring area LA, but is not limited thereto.

[0070] The pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1 may include a first pixel circuit PXC1 and a first light-emitting element (see "LD1" in FIG. 8) driven by the first pixel circuit PXC1. The second sub-pixel SPX2 may include a second pixel circuit PXC2 and a second light-emitting element (see "LD2" in FIG. 8) driven by the second pixel circuit PXC2. The third sub-pixel SPX3 may include a third pixel circuit PXC3 and a third light-emitting element (see "LD3" in FIG. 8) driven by the third pixel circuit PXC3. Each of the first to third pixel circuits PXC1, PXC2, and PXC3 may be the pixel circuit PXC described with reference to FIG. 3, and each of the first to third light-emitting elements LD1, LD2, and LD3 may be the light-emitting element LD described with reference to FIG. 3.

[0071] The pixel region PXA may include a first light-emitting region EMA1, a second light-emitting region EMA2, and a third light-emitting region EMA3. The pixel region PXA may also include a non-light-emitting region NEA surrounding the first to third light-emitting regions EMA1, EMA2, and EMA3. A pixel defining layer (see "PDL" in FIG. 8) that defines the first to third light-emitting regions EMA1, EMA2, and EMA3 may be disposed in the non-light-emitting region NEA.

[0072] The first light-emitting region EMA1 may be a region where light is emitted from the first light-emitting element LD1 of the first sub-pixel SPX1. For example, the first light-emitting region EMA1 may correspond to a region where the first light-emitting layer EML1 of the first light-emitting element LD1 is disposed.

[0073] The second light-emitting region EMA2 may be a region where light is emitted from the second light-emitting element LD2 of the second sub-pixel SPX2. For example, the second light-emitting region EMA2 may correspond to a region where the second light-emitting layer EML2 of the second light-emitting element LD2 is disposed.

[0074] The third light-emitting region EMA3 may be a region where light is emitted from the third light-emitting element LD3 of the third sub-pixel SPX3. For example, the third light-emitting region EMA3 may correspond to a region where the third light-emitting layer EML3 of the third light-emitting element LD3 is disposed.

[0075] In the pixel region PXA, signal lines electrically connected to the first to third sub-pixels SPX1, SPX2, and SPX3 may be arranged. As an example, in the pixel region PXA, scan lines SC, data lines D1, D2, and D3, power supply lines PL, initialization power supply lines IPL, and the like may be arranged, but are not limited to this.

[0076] The scan lines SC are located in the wiring area LA and may extend in a first direction DR1. The scan lines SC may be selectively supplied with scan signals and sensing control signals. The scan lines SC may be configured as a second conductive layer C2. The second conductive layer C2 may be formed of a single layer or multiple layers made of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), or oxides or alloys thereof.

[0077] The scan line SC may include a first sub-scan line SSL1 extending in the second direction DR2. The first sub-scan line SSL1 may be configured as a second conductive layer C2 and formed integrally with the scan line SC. In this case, the first sub-scan line SSL1 may be a region of the scan line SC.

[0078] The first sub-scan line SSL1 may be formed integrally with the second gate electrode GE2 of the second transistor T2 of each of the first to third pixel circuits PXC1, PXC2, and PXC3. As an example, a part of the first sub-scan line SSL1 may be the second gate electrode GE2 of the second transistor T2 of each of the first to third pixel circuits PXC1, PXC2, and PXC3.

[0079] For example, the first sub-scan line SSL1 may be formed integrally with the third gate electrode GE3 of the third transistor T3 of each of the first to third pixel circuits PXC1, PXC2, and PXC3. As an example, another part of the first sub-scan line SSL1 may be the third gate electrode GE3 of the third transistor T3 of each of the first to third pixel circuits PXC1, PXC2, and PXC3.

[0080] The scan line SC can supply a scan signal to the second gate electrode GE2 of the second transistor T2 of each of the first to third pixel circuits PXC1, PXC2, and PXC3 during the driving period of the light-emitting element LD, and can supply a sensing control signal to the third gate electrode GE3 of the third transistor T3 of each of the first to third pixel circuits PXC1, PXC2, and PXC3 during the sensing period.

[0081] The data wirings D1, D2, and D3 may include a first data wiring D1, a second data wiring D2, and a third data wiring D3 that extend along the second direction DR2 and are arranged in the first direction DR1. Each of the first to third data wirings D1, D2, and D3 may be supplied with a data signal.

[0082] The first data wiring D1 may be electrically connected to the second transistor T2 of the first pixel circuit PXC1 (or the first sub-pixel SPX1), the second data wiring D2 may be electrically connected to the second transistor T2 of the second pixel circuit PXC2 (or the second sub-pixel SPX2), and the third data wiring D3 may be electrically connected to the second transistor T2 of the third pixel circuit PXC3 (or the third sub-pixel SPX3). Each of the first to third data wirings D1, D2, and D3 may be configured as a first conductive layer C1. The first conductive layer C1 may include the same material as the second conductive layer C2 described above, or may include one or more suitable (or selected) materials from the materials exemplified as components of the second conductive layer C2, but is not limited thereto.

[0083] The power supply wiring PL can include a first power supply wiring PL1 and a second power supply wiring PL2.

[0084] The first power supply wiring PL1 may be supplied with a first drive power supply voltage VDD. The first power supply wiring PL1 may include a first vertical power supply wiring PL1a and a first horizontal power supply wiring PL1b.

[0085] The first vertical power supply wiring PL1a may extend along the second direction DR2 and may be arranged between the first to third storage capacitors Cst1, Cst2, and Cst3 and the data wirings D1, D2, and D3 in a plan view. For example, the first vertical power supply wiring PL1a may be arranged between the first to third storage capacitors Cst1, Cst2, and Cst3 and the initialization power supply wiring IPL adjacent to the first data wiring D1. The first vertical power supply wiring PL1a may be formed as a first conductive layer C1. The first vertical power supply wiring PL1a may be electrically connected to a first horizontal power supply wiring PL1b located in a different layer via a corresponding contact hole.

[0086] The first horizontal power supply wiring PL1b is located in the wiring area LA and may extend in the first direction DR1. The first horizontal power supply wiring PL1b may be configured as the second conductive layer C2. The first vertical power supply wiring PL1a configured as the first conductive layer C1 and the first horizontal power supply wiring PL1b configured as the second conductive layer C2 may be electrically connected to each other via corresponding contact holes. The first vertical power supply wiring PL1a and the first horizontal power supply wiring PL1b electrically connected to each other may have a mesh structure.

[0087] The second power supply wiring PL2 may be supplied with a second drive power supply voltage VSS. The second power supply wiring PL2 may include a second vertical power supply wiring PL2a and a second horizontal power supply wiring PL2b.

[0088] The second vertical power supply wiring PL2a may extend along the second direction DR2 and may be located on one side (for example, the left side) of the first to third storage capacitors Cst1, Cst2, and Cst3 in a plan view. The second vertical power supply wiring PL2a may be configured as the first conductive layer C1. The second vertical power supply wiring PL2a may be electrically connected to an additional conductive pattern ACP located in a different layer through a corresponding contact hole.

[0089] The additional conductive pattern ACP may be configured as a second conductive layer C2 and extend in the second direction DR2 to overlap the second vertical power supply wiring PL2a. The second vertical power supply wiring PL2a may be electrically connected to the additional conductive pattern ACP located in a different layer through a corresponding contact hole to achieve a double-layer structure. This reduces the wiring resistance of the second vertical power supply wiring PL2a.

[0090] The second horizontal power supply wiring PL2b is located in the wiring area LA and may extend in the first direction DR1. The second horizontal power supply wiring PL2b may be configured as a second conductive layer C2. The second vertical power supply wiring PL2a configured as the first conductive layer C1 and the second horizontal power supply wiring PL2b configured as the second conductive layer C2 may be electrically connected to each other via corresponding contact holes. The second vertical power supply wiring PL2a and the second horizontal power supply wiring PL2b electrically connected to each other may have a mesh structure.

[0091] The initialization power supply wiring IPL may extend in the second direction DR2 and be configured as a first conductive layer C1. The initialization power supply wiring IPL may be arranged between the first vertical power supply wiring PL1a and the data wirings D1, D2, and D3 when viewed in a plan view. The first vertical power supply wiring PL1a, the initialization power supply wiring IPL, and the data wirings D1, D2, and D3 may be arranged to be spaced apart in the first direction DR1. The initialization power supply wiring IPL may be the sensing line SENj described with reference to FIG. 3. The initialization power supply wiring IPL may be supplied with an initialization voltage. The initialization power supply wiring IPL may be electrically connected to the third transistors T3 of the first to third pixel circuits PXC1, PXC2, and PXC3 (or the first to third sub-pixels SPX1, SPX2, and SPX3).

[0092] The first pixel circuit PXC1 of the first sub-pixel SPX1, the second pixel circuit PXC2 of the second sub-pixel SPX2, and the third pixel circuit PXC3 of the third sub-pixel SPX3 may have substantially similar or identical structures. The following description will focus on the first pixel circuit PXC1, and the description of the second pixel circuit PXC2 and the third pixel circuit PXC3 will be simplified.

[0093] The first pixel circuit PXC1 may include first to third transistors T1, T2, and T3 and a first storage capacitor Cst1.

[0094] The first transistor T1 may include a first gate electrode GE1, a first active pattern ACT1, a first source electrode SE1, and a first drain electrode DE1.

[0095] The first gate electrode GE1 may be electrically connected to the second source electrode SE2 of the second transistor T2 through a corresponding contact hole. The first gate electrode GE1 may be configured as a second conductive layer C2. In an embodiment, the first gate electrode GE1 may be electrically connected to the lower metal pattern BML through a corresponding contact hole. In an embodiment, the first gate electrode GE1 may be disposed between the first storage capacitor Cst1 and the first vertical power line PL1a.

[0096] The lower metal pattern BML (or first lower metal pattern) may be configured as a first conductive layer C1 and may overlap the first transistor T1. The lower metal pattern BML may be electrically connected to the first gate electrode GE1 through a corresponding contact hole. By electrically connecting the lower metal pattern BML to the first gate electrode GE1, floating of the lower metal pattern BML may be prevented, and the wiring resistance of the first gate electrode GE1 may be reduced.

[0097] The first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be configured as semiconductor patterns made of polysilicon, amorphous silicon, an oxide semiconductor, etc. The first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be formed of a semiconductor layer that is undoped with impurities or doped with impurities. For example, the first source electrode SE1 and the first drain electrode DE1 may be doped with impurities to have conductivity, and the first active pattern ACT1 may be made of an intrinsic semiconductor layer that is undoped with impurities.

[0098] The first active pattern ACT1 may be positioned under the first gate electrode GE1 formed as the second conductive layer C2 and may overlap the first gate electrode GE1. The first active pattern ACT1 may form a channel region of the first transistor T1.

[0099] The first source electrode SE1 may be connected to one end of the first active pattern ACT1. The first source electrode SE1 may be doped with impurities in an impurity doping process performed after forming the second conductive layer C2, thereby becoming conductive. In this embodiment, the first source electrode SE1 may be integrally formed with and connected to a third source electrode SE3 of the third transistor T3.

[0100] The first drain electrode DE1 may be connected to the other end of the first active pattern ACT1. The first drain electrode DE1 may be doped with impurities in an impurity doping process performed after forming the second conductive layer C2, thereby making the first drain electrode DE1 conductive. The first drain electrode DE1 may be electrically connected to the first conductive pattern CP1 through a corresponding contact hole.

[0101] The first conductive pattern CP1 is configured as a second conductive layer C2 and can overlap the first drain electrode DE1 and the first vertical power supply line PL1a. A portion of the first conductive pattern CP1 may be electrically connected to the first drain electrode DE1 through a corresponding contact hole. Another portion of the first conductive pattern CP1 may be electrically connected to the first vertical power supply line PL1a through the contact hole. The first drain electrode DE1 and the first vertical power supply line PL1a may be electrically connected to each other through the first conductive pattern CP1.

[0102] The second transistor T2 may include a second gate electrode GE2, a second active pattern ACT2, a second source electrode SE2, and a second drain electrode DE2.

[0103] The second gate electrode GE2 may be formed integrally with the first sub-scan line SSL1 and configured as a second conductive layer C2. The second gate electrode GE2 may overlap the second active pattern ACT2.

[0104] The second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may be configured as semiconductor patterns made of polysilicon, amorphous silicon, an oxide semiconductor, etc. The second source electrode SE2 and the second drain electrode DE2 may be doped with impurities to have conductivity, and the second active pattern ACT2 may be made of an intrinsic semiconductor layer that is not doped with impurities.

[0105] The second active pattern ACT2 may be positioned under the second gate electrode GE2 and may overlap the second gate electrode GE2, and may form a channel region of the second transistor T2.

[0106] The second source electrode SE2 may be connected to one end of the second active pattern ACT2. The second source electrode SE2 may be doped with impurities in an impurity doping process performed after forming the second conductive layer C2, thereby making the second source electrode SE2 conductive. The second source electrode SE2 may be electrically connected to the first gate electrode GE1 through a corresponding contact hole.

[0107] The second drain electrode DE2 may be connected to the other end of the second active pattern ACT2. The second drain electrode DE2 may be doped with impurities in an impurity doping process performed after forming the second conductive layer C2, thereby becoming conductive. The second drain electrode DE2 may be electrically connected to the second conductive pattern CP2 through a corresponding contact hole.

[0108] The second conductive pattern CP2 may be configured as a second conductive layer C2 and may overlap the first data line D1 and the second drain electrode DE2. A portion of the second conductive pattern CP2 may be electrically connected to the second drain electrode DE2 through a corresponding contact hole. Another portion of the second conductive pattern CP2 may be electrically connected to the first data line D1 through the contact hole. The second drain electrode DE2 and the first data line D1 may be electrically connected to each other through the second conductive pattern CP2.

[0109] The third transistor T3 may include a third gate electrode GE3, a third active pattern ACT3, a third source electrode SE3, and a third drain electrode DE3.

[0110] The third gate electrode GE3 may be configured as the second conductive layer C2 and may be formed integrally with the first sub-scan line SSL1. The third gate electrode GE3 may overlap the third active pattern ACT3.

[0111] The third active pattern ACT3, the third source electrode SE3, and the third drain electrode DE3 may be configured as semiconductor patterns made of polysilicon, amorphous silicon, an oxide semiconductor, etc. The third source electrode SE3 and the third drain electrode DE3 may be doped with impurities to have conductivity, and the third active pattern ACT3 may be configured as an intrinsic semiconductor layer that is not doped with impurities.

[0112] The third active pattern ACT3 may overlap the third gate electrode GE3 and may form a channel region of the third transistor T3.

[0113] The third source electrode SE3 may be connected to one end of the third active pattern ACT3. The third source electrode SE3 may be doped with impurities in an impurity doping process performed after forming the second conductive layer C2, thereby making the third source electrode SE3 conductive. The third source electrode SE3 may be integrally formed with the first source electrode SE1 and connected to the first source electrode SE1. By integrally forming the third source electrode SE3 and the first source electrode SE1, a separate first connection member for connecting the third source electrode SE3 and the first source electrode SE1 may be omitted.

[0114] The third drain electrode DE3 may be connected to the other end of the third active pattern ACT3. The third drain electrode DE3 may be doped with impurities in an impurity doping process performed after forming the second conductive layer C2, thereby becoming conductive. The third drain electrode DE3 may be electrically connected to the third conductive pattern CP3 through a corresponding contact hole.

[0115] The third conductive pattern CP3 may overlap the initialization power wiring IPL and the third drain electrode DE3. A part of the third conductive pattern CP3 may be electrically connected to the third drain electrode DE3 through a corresponding contact hole. Another part of the third conductive pattern CP3 may be electrically connected to the initialization power wiring IPL through the contact hole. The third drain electrode DE3 and the initialization power wiring IPL may be electrically connected to each other through the third conductive pattern CP3.

[0116] The first storage capacitor Cst1 may include a first bottom electrode LE1 and a first top electrode UE1, and may be the storage capacitor Cst described with reference to FIG.

[0117] The first bottom electrode LE1 may be configured as a first conductive layer C1 and may be integrally formed with the lower metal pattern BML. The first bottom electrode LE1 (or the lower metal pattern BML) may be disposed between the second vertical power supply wiring PL2a and the first vertical power supply wiring PL1a in a plan view. In an embodiment, the first bottom electrode LE1 may be electrically connected to the first gate electrode GE1 and the second source electrode SE2 via corresponding contact holes.

[0118] The first upper electrode UE1 may be integrally formed with the first source electrode SE1 and the third source electrode SE3 and connected to the first source electrode SE1 and the third source electrode SE3. The first upper electrode UE1 may be configured as a semiconductor pattern made of polysilicon, amorphous silicon, an oxide semiconductor, or the like, and may be conductive after being doped with impurities. The first upper electrode UE1 may overlap the first lower electrode LE1 and may have a size (or area) similar to or larger than the first lower electrode LE1, but is not limited thereto.

[0119] In an embodiment, the first upper electrode UE1 may be arranged so as not to overlap with the first gate electrode GE1. In plan view, the first upper electrode UE1 may be arranged between the second vertical power supply line PL2a and the first vertical power supply line PL1a.

[0120] The first source electrode SE1, the third source electrode SE3, and the first upper electrode UE1, which are integrally formed in the first pixel circuit PXC1 having the above-described configuration, may be electrically connected to the 1-1 electrode AE1 (or the first anode) via the contact portion CNT.

[0121] The first-1 electrode AE1 may be configured as the third conductive layer C3. The third conductive layer C3 and the second conductive layer C2 may include the same material. The third conductive layer C3 may include, but is not limited to, one or more suitable materials from the materials exemplified as the materials for the second conductive layer C2. The first-1 electrode AE1 may overlap a portion of the first pixel circuit PXC1, such as the first transistor T1 and the first storage capacitor Cst1. For example, the first-1 electrode AE1 may overlap a portion of the signal wiring electrically connected to the first pixel circuit PXC1. In this embodiment, the first-1 electrode AE1 may overlap the first light-emitting layer EML1 corresponding to the first light-emitting region EMA1. If the first sub-pixel SPX1 is a red pixel, the first light-emitting layer EML1 may emit red light, but is not limited to this.

[0122] The second pixel circuit PXC2 may include first to third transistors T1, T2, and T3 and a second storage capacitor Cst2.

[0123] The first transistor T1 may include a first gate electrode GE1, a first active pattern ACT1, a first source electrode SE1, and a first drain electrode DE1.

[0124] The first gate electrode GE1 may be electrically connected to the second source electrode SE2 of the second transistor T2 through a corresponding contact hole. The first gate electrode GE1 may be configured as a second conductive layer C2 and electrically connected to the lower metal pattern BML (or the second lower electrode LE2) through the contact hole. In an embodiment, the first gate electrode GE1 may be located between the second storage capacitor Cst2 and the first vertical power line PL1a.

[0125] The lower metal pattern BML (or second lower metal pattern) may be configured as a first conductive layer C1 and may overlap the first transistor T1. The lower metal pattern BML may also be integrally formed with the second bottom electrode LE2 of the second storage capacitor Cst2.

[0126] The first active pattern ACT1 may overlap the first gate electrode GE1 and may form a channel region of the first transistor T1.

[0127] The first source electrode SE1 may be connected to one end of the first active pattern ACT1. In an embodiment, the first source electrode SE1 may be integrally formed with and connected to a third source electrode SE3 of the third transistor T3.

[0128] The first drain electrode DE1 may be connected to the other end of the first active pattern ACT1 and may be electrically connected to the fourth conductive pattern CP4 through a corresponding contact hole.

[0129] The fourth conductive pattern CP4 is configured as the second conductive layer C2 and can overlap the first drain electrode DE1 and the first vertical power supply line PL1a. A part of the fourth conductive pattern CP4 may be electrically connected to the first drain electrode DE1 through a corresponding contact hole. Another part of the fourth conductive pattern CP4 may be electrically connected to the first vertical power supply line PL1a through the contact hole. The first drain electrode DE1 and the first vertical power supply line PL1a may be electrically connected to each other through the fourth conductive pattern CP4.

[0130] The second transistor T2 may include a second gate electrode GE2, a second active pattern ACT2, a second source electrode SE2, and a second drain electrode DE2.

[0131] The second gate electrode GE2 may be formed integrally with the first sub-scan line SSL1 and configured as a second conductive layer C2.

[0132] The second active pattern ACT2 can form the channel region of the second transistor T2.

[0133] The second source electrode SE2 may be connected to one end of the second active pattern ACT2 and may be electrically connected to the first gate electrode GE1 through a corresponding contact hole.

[0134] The second drain electrode DE2 may be connected to the other end of the second active pattern ACT2 and may be electrically connected to the fifth conductive pattern CP5 through a corresponding contact hole.

[0135] The fifth conductive pattern CP5 is configured as a second conductive layer C2 and may overlap the second data line D2 and the second drain electrode DE2. A portion of the fifth conductive pattern CP5 may be electrically connected to the second drain electrode DE2 through a corresponding contact hole. Another portion of the fifth conductive pattern CP5 may be electrically connected to the second data line D2 through the contact hole. The second drain electrode DE2 and the second data line D2 may be electrically connected through the fifth conductive pattern CP5.

[0136] The third transistor T3 may include a third gate electrode GE3, a third active pattern ACT3, a third source electrode SE3, and a third drain electrode DE3.

[0137] The third gate electrode GE3 may be configured as a second conductive layer C2 and may be formed integrally with the first sub-scan line SSL1.

[0138] The third active pattern ACT3 may form a channel region of the third transistor T3.

[0139] The third source electrode SE3 may be connected to one end of the third active pattern ACT3. The third source electrode SE3 may be integrally formed with the first source electrode SE1 and connected to the first source electrode SE1. By integrally forming the third source electrode SE3 and the first source electrode SE1, a separate second connection member for connecting the third source electrode SE3 and the first source electrode SE1 may be omitted.

[0140] The third drain electrode DE3 may be connected to the other end of the third active pattern ACT3 and may be electrically connected to the sixth conductive pattern CP6 through a corresponding contact hole.

[0141] The sixth conductive pattern CP6 is configured as the second conductive layer C2 and can overlap with the third drain electrode DE3 and the initialization power wiring IPL. A part of the sixth conductive pattern CP6 may be electrically connected to the third drain electrode DE3 through a corresponding contact hole. Another part of the sixth conductive pattern CP6 may be electrically connected to the initialization power wiring IPL through the contact hole. The third drain electrode DE3 and the initialization power wiring IPL may be electrically connected to each other through the sixth conductive pattern CP6.

[0142] The second storage capacitor Cst2 may include a second bottom electrode LE2 and a second top electrode UE2, and may be the storage capacitor Cst described with reference to FIG.

[0143] The second bottom electrode LE2 may be configured as the first conductive layer C1 and may be formed integrally with the lower metal pattern BML. The second bottom electrode LE2 (or the lower metal pattern BML) may be disposed between the second vertical power supply wiring PL2a and the first vertical power supply wiring PL1a in a plan view. In an embodiment, the second bottom electrode LE2 may be electrically connected to the first gate electrode GE1 and the second source electrode SE2 via corresponding contact holes.

[0144] The second upper electrode UE2 may be integrally formed with the first source electrode SE1 and the third source electrode SE3 and connected to the first source electrode SE1 and the third source electrode SE3. The second upper electrode UE2 may overlap the second lower electrode LE2 and have a size (or area) similar to or larger than the second lower electrode LE2, but is not limited thereto.

[0145] In an embodiment, the second upper electrode UE2 may be arranged so as not to overlap with the first gate electrode GE1. In plan view, the second upper electrode UE2 may be arranged between the second vertical power supply line PL2a and the first vertical power supply line PL1a.

[0146] The first source electrode SE1, the third source electrode SE3, and the second upper electrode UE2, which are integrally formed in the second pixel circuit PXC2 having the above-described configuration, may be electrically connected to the first-second electrode AE2 (or the second anode) via the contact portion CNT.

[0147] The first-second electrode AE2 may be configured as a third conductive layer C3. The first-second electrode AE2 may overlap a portion of the second pixel circuit PXC2, such as the first transistor T1 and the second storage capacitor Cst2. For example, the first-second electrode AE2 may overlap a portion of the signal wiring electrically connected to the second pixel circuit PXC2. In an embodiment, the first-second electrode AE2 may overlap a second light-emitting layer EML2 corresponding to the second light-emitting region EMA2. When the second sub-pixel SPX2 is a green pixel, the second light-emitting layer EML2 may emit green light, but is not limited thereto.

[0148] The third sub-pixel PXC3 may include first to third transistors T1, T2, and T3 and a third storage capacitor Cst3.

[0149] The first transistor T1 may include a first gate electrode GE1, a first active pattern ACT1, a first source electrode SE1, and a first drain electrode DE1.

[0150] The first gate electrode GE1 may be electrically connected to the second source electrode SE2 of the second transistor T2 through a corresponding contact hole. The first gate electrode GE1 may be configured as a second conductive layer C2 and electrically connected to the lower metal pattern BML (or the third lower electrode LE3) through the contact hole. In an embodiment, the first gate electrode GE1 may be disposed between the third storage capacitor Cst3 and the first vertical power line PL1a.

[0151] The lower metal pattern BML (or third lower metal pattern) may be configured as the first conductive layer C1 and may overlap the first transistor T1. For example, the lower metal pattern BML may be integral with the third lower electrode LE3 of the third storage capacitor Cst3.

[0152] The first active pattern ACT1 may overlap the first gate electrode GE1 and may form a channel region of the first transistor T1.

[0153] The first source electrode SE1 may be connected to one end of the first active pattern ACT1. In an embodiment, the first source electrode SE1 may be integrally formed with and connected to a third source electrode SE3 of the third transistor T3.

[0154] The first drain electrode DE1 may be connected to the other end of the first active pattern ACT1 and may be electrically connected to the seventh conductive pattern CP7 through a corresponding contact hole.

[0155] The seventh conductive pattern CP7 is configured as the second conductive layer C2 and can overlap the first drain electrode DE1 and the first vertical power supply line PL1a. A part of the seventh conductive pattern CP7 may be electrically connected to the first drain electrode DE1 through a corresponding contact hole. Another part of the seventh conductive pattern CP7 may be electrically connected to the first vertical power supply line PL1a through the contact hole. The first drain electrode DE1 and the first vertical power supply line PL1a may be electrically connected to each other through the seventh conductive pattern CP7.

[0156] The second transistor T2 may include a second gate electrode GE2, a second active pattern ACT2, a second source electrode SE2, and a second drain electrode DE2.

[0157] The second gate electrode GE2 may be formed integrally with the first sub-scan line SSL1 and configured as a second conductive layer C2.

[0158] The second active pattern ACT2 can form the channel region of the second transistor T2.

[0159] The second source electrode SE2 may be connected to one end of the second active pattern ACT2 and may be electrically connected to the first gate electrode GE1 through a corresponding contact hole.

[0160] The second drain electrode DE2 may be connected to the other end of the second active pattern ACT2 and may be electrically connected to the eighth conductive pattern CP8 through a corresponding contact hole.

[0161] The eighth conductive pattern CP8 is configured as the second conductive layer C2 and may overlap the third data line D3 and the second drain electrode DE2. A portion of the eighth conductive pattern CP8 may be electrically connected to the second drain electrode DE2 through a corresponding contact hole. Another portion of the eighth conductive pattern CP8 may be electrically connected to the third data line D3 through the contact hole. The second drain electrode DE2 and the third data line D3 may be electrically connected through the eighth conductive pattern CP8.

[0162] The third transistor T3 may include a third gate electrode GE3, a third active pattern ACT3, a third source electrode SE3, and a third drain electrode DE3.

[0163] The third gate electrode GE3 may be configured as a second conductive layer C2 and may be formed integrally with the first sub-scan line SSL1.

[0164] The third active pattern ACT3 may form a channel region of the third transistor T3.

[0165] The third source electrode SE3 may be connected to one end of the third active pattern ACT3. The third source electrode SE3 may be integrally formed with the first source electrode SE1 and connected to the first source electrode SE1. By integrally forming the third source electrode SE3 and the first source electrode SE1, a separate third connection member for connecting the third source electrode SE3 and the first source electrode SE1 may be omitted.

[0166] The third drain electrode DE3 may be connected to the other end of the third active pattern ACT3 and may be electrically connected to the ninth conductive pattern CP9 through a corresponding contact hole.

[0167] The ninth conductive pattern CP9 is configured as the second conductive layer C2 and can overlap with the third drain electrode DE3 and the initialization power wiring IPL. A part of the ninth conductive pattern CP9 may be electrically connected to the third drain electrode DE3 through a corresponding contact hole. Another part of the ninth conductive pattern CP9 may be electrically connected to the initialization power wiring IPL through the contact hole. The third drain electrode DE3 and the initialization power wiring IPL may be electrically connected to each other through the ninth conductive pattern CP9.

[0168] The third storage capacitor Cst3 may include a third bottom electrode LE3 and a third top electrode UE3, and may be the storage capacitor Cst described with reference to FIG.

[0169] The third bottom electrode LE3 may be configured as the first conductive layer C1 and may be formed integrally with the bottom metal pattern BML. The third bottom electrode LE3 (or the bottom metal pattern BML) may be disposed between the second vertical power supply wiring PL2a and the first vertical power supply wiring PL1a in a plan view. In an embodiment, the third bottom electrode LE3 may be electrically connected to the first gate electrode GE1 and the second source electrode SE2 via corresponding contact holes.

[0170] The third upper electrode UE3 may be integrally formed with the first source electrode SE1 and the third source electrode SE3 and connected to the first source electrode SE1 and the third source electrode SE3. The third upper electrode UE3 may overlap the third lower electrode LE3 and have a size (or area) similar to or larger than the third lower electrode LE3, but is not limited thereto.

[0171] In an embodiment, the third upper electrode UE3 may be arranged so as not to overlap with the first gate electrode GE1. In plan view, the third upper electrode UE3 may be arranged between the second vertical power supply line PL2a and the first vertical power supply line PL1a.

[0172] The first source electrode SE1, the third source electrode SE3, and the third upper electrode UE3, which are integrally formed in the third pixel circuit PXC3 having the above-described configuration, may be electrically connected to the first-third electrode AE3 (or the third anode) via the contact portion CNT.

[0173] The first-third electrode AE3 may be configured as a third conductive layer C3. The first-third electrode AE3 may overlap some components of the third pixel circuit PXC3, such as the first transistor T1 and the third storage capacitor Cst3. For example, the first-third electrode AE3 may overlap some signal wiring electrically connected to the third pixel circuit PXC3. In an embodiment, the first-third electrode AE3 may overlap the third light-emitting layer EML3 corresponding to the third light-emitting region EMA3. When the third sub-pixel SPX3 is a blue pixel, the third light-emitting layer EML3 may emit blue light, but is not limited thereto.

[0174] In the above-described embodiment, the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 may be arranged along the second direction DR2 and positioned on the same line. In the pixel region PXA, the first to third storage capacitors Cst1, Cst2, and Cst3 may be positioned between the second vertical power line PL2a and the first vertical power line PL1a. For example, the second vertical power line PL2a may be positioned on one side (for example, the left side) of the first to third storage capacitors Cst1, Cst2, and Cst3 in the pixel region PXA, and the first vertical power line PL1a may be positioned on the other side (for example, the right side) of the first to third storage capacitors Cst1, Cst2, and Cst3 in the pixel region PXA.

[0175] When the first vertical power supply line PL1a is located to the right of the first to third storage capacitors Cst1, Cst2, and Cst3, the first transistors T1 of the first to third pixel circuits PXC1, PXC2, and PXC3 electrically connected to the first vertical power supply line PL1a may be located to the right of the storage capacitor of the corresponding pixel circuit. For example, the first transistor T1 of the first pixel circuit PXC1 may be located between the right side of the first storage capacitor Cst1 and the first vertical power supply line PL1a, the first transistor T1 of the second pixel circuit PXC2 may be located between the right side of the second storage capacitor Cst2 and the first vertical power supply line PL1a, and the first transistor T1 of the third pixel circuit PXC3 may be located between the right side of the third storage capacitor Cst3 and the first vertical power supply line PL1a. In this case, the first gate electrode GE1 of the first transistor T1 of the first pixel circuit PXC1 can be located between the right side of the first storage capacitor Cst1 and the first vertical power supply line PL1a, the first gate electrode GE1 of the first transistor T1 of the second pixel circuit PXC2 can be located between the right side of the second storage capacitor Cst2 and the first vertical power supply line PL1a, and the first gate electrode GE1 of the first transistor T1 of the third pixel circuit PXC3 can be located between the right side of the third storage capacitor Cst3 and the first vertical power supply line PL1a.

[0176] For example, in the above-described embodiment, the initialization power line IPL and the first to third data lines D1, D2, and D3 electrically connected to the first to third pixel circuits PXC1, PXC2, and PXC3 may be located to the right of the first to third storage capacitors Cst1, Cst2, and Cst3 and spaced apart from the first vertical power line PL1a. In the pixel region PXA, the second vertical power line PL2a, the first to third storage capacitors Cst1, Cst2, and Cst3, the first vertical power line PL1a, the initialization power line IPL, the first data line D1, the second data line D2, and the third data line D3 may be arranged in this order along the first direction DR1.

[0177] When the initialization power line IPL is located to the right of the first to third storage capacitors Cst1, Cst2, and Cst3, the third transistor T3 of each of the first to third pixel circuits PXC1, PXC2, and PXC3 electrically connected to the initialization power line IPL may be located to the right of the storage capacitor of the corresponding pixel circuit. For example, the third transistor T3 of the first pixel circuit PXC1 may be located between the right side of the first storage capacitor Cst1 and the initialization power line IPL, the third transistor T3 of the second pixel circuit PXC2 may be located between the right side of the second storage capacitor Cst2 and the initialization power line IPL, and the third transistor T3 of the third pixel circuit PXC3 may be located between the right side of the third storage capacitor Cst3 and the initialization power line IPL.

[0178] When the first data line D1 is located to the right of the first to third storage capacitors Cst1, Cst2, and Cst3, the second transistor T2 of the first pixel circuit PXC1 electrically connected to the first data line D1 may be located to the right of the first storage capacitor Cst1. When the second data line D2 is located to the right of the first to third storage capacitors Cst1, Cst2, and Cst3, the second transistor T2 of the second pixel circuit PXC2 electrically connected to the second data line D2 may be located to the right of the second storage capacitor Cst2. When the third data line D3 is located to the right of the first to third storage capacitors Cst1, Cst2, and Cst3, the second transistor T2 of the third pixel circuit PXC3 electrically connected to the third data line D3 may be located to the right of the third storage capacitor Cst3.

[0179] As described above, the first to third transistors T1, T2, and T3 of the first pixel circuit PXC1 may be located to the right of the first storage capacitor Cst1, the first to third transistors T1, T2, and T3 of the second pixel circuit PXC2 may be located to the right of the second storage capacitor Cst2, and the first to third transistors T1, T2, and T3 of the third pixel circuit PXC3 may be located to the right of the third storage capacitor Cst3. In this case, in each of the first to third sub-pixels SPX1, SPX2, and SPX3, the first gate electrode GE1 and the second source electrode SE2 (or the corresponding data line) may be electrically connected to the right of the storage capacitor of the corresponding sub-pixel. This reduces or prevents the electrical connection between the first gate electrode GE1 and the second source electrode SE2 from affecting the first to third storage capacitors Cst1, Cst2, and Cst3. In this case, in each of the first to third sub-pixels SPX1, SPX2, and SPX3, the area (or size) of the first gate electrode GE1 of the first transistor T1 can be reduced, thereby ensuring the area of ​​the storage capacitor of the corresponding sub-pixel by the reduced area (or size) of the first gate electrode GE1. For example, in the first sub-pixel SPX1, the area of ​​the first gate electrode GE1 of the first transistor T1 can be reduced and the areas of the first bottom electrode LE1 and the first top electrode UE1 can be increased by the reduced area of ​​the first gate electrode GE1, thereby further ensuring the overlapping area between the first bottom electrode LE1 and the first top electrode UE1 and improving the capacitance of the first storage capacitor Cst1. In the second sub-pixel SPX2, the area of ​​the first gate electrode GE1 of the first transistor T1 can be reduced and the areas of the second bottom electrode LE2 and the second top electrode UE2 can be increased by the reduced area of ​​the first gate electrode GE1, thereby further ensuring the overlapping area between the second bottom electrode LE2 and the second top electrode UE2 and improving the capacitance of the second storage capacitor Cst2.In the third sub-pixel SPX3, the area of ​​the first gate electrode GE1 of the first transistor T1 is reduced, and the areas of the third bottom electrode LE3 and the third top electrode UE3 are increased by the reduced area of ​​the first gate electrode GE1, thereby further securing the overlapping area of ​​the third bottom electrode LE3 and the third top electrode UE3 and improving the capacitance of the third storage capacitor Cst3.

[0180] According to the above-described embodiment, the capacitance of each of the first to third storage capacitors Cst1, Cst2, and Cst3 can be increased, thereby improving the reliability of the pixel PXL (or the display device DD).

[0181] According to the above-described embodiment, in each of the first to third pixel circuits PXC1, PXC2, and PXC3, the first source electrode SE1 of the first transistor T1 and the third source electrode SE3 of the third transistor T3 are integrally formed, thereby eliminating the need for a connection member (e.g., a contact hole or a conductive pattern) for electrically connecting the first source electrode SE1 and the third source electrode SE3. As a result, in the first pixel circuit PXC1, the area of ​​the first storage capacitor Cst1 can be further secured, thereby increasing the capacitance of the first storage capacitor Cst1. In the second pixel circuit PXC2, the area of ​​the second storage capacitor Cst2 can be further secured, thereby increasing the capacitance of the second storage capacitor Cst2. In the third pixel circuit PXC3, the area of ​​the third storage capacitor Cst3 can be further secured, thereby increasing the capacitance of the third storage capacitor Cst3.

[0182] According to the above-described embodiment, by arranging the first vertical power supply line PL1a to the right of the first to third storage capacitors Cst1, Cst2, and Cst3, the first to third transistors T1, T2, and T3 of the first to third pixel circuits PXC1, PXC2, and PXC3 can be located to the right of the storage capacitor of the corresponding pixel circuit. This makes it easy to form the first to third transistors T1, T2, and T3 to the right of the first to third storage capacitors Cst1, Cst2, and Cst3, respectively, thereby reducing design constraints due to the positions of the first to third transistors T1, T2, and T3.

[0183] Hereinafter, the stacked structure (or cross-sectional structure) of the pixel PXL according to the above-described embodiment will be mainly described with reference to FIGS.

[0184] 8 is a schematic cross-sectional view taken along line II' in FIG. 5, and FIGS. 9 and 10 are schematic cross-sectional views taken along line II' in FIG.

[0185] FIG. 10 shows a modification of the embodiment of FIG. 9 with respect to the position of the second insulating layer INS2 and the like.

[0186] In Figures 8 to 10, the layered structure of the pixel PXL is shown in a simplified manner, with each electrode shown as a single-film electrode and each insulating layer shown as a single-film insulating layer, but this is not limited to this.

[0187] In order to avoid redundant explanations regarding the embodiment of FIGS. 8 to 10, differences from the previously described embodiment will be mainly described.

[0188] 1 to 10, the pixel PXL according to the embodiment may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 adjacent to each other.

[0189] The first subpixel SPX1 may include a first light-emitting region EMA1 and a non-light-emitting region NEA surrounding the first light-emitting region EMA1. The second subpixel SPX2 may include a second light-emitting region EMA2 and a non-light-emitting region NEA surrounding the second light-emitting region EMA2. The third subpixel SPX3 may include a third light-emitting region EMA3 and a non-light-emitting region NEA surrounding the third light-emitting region EMA3.

[0190] Each of the first to third sub-pixels SPX1, SPX2, and SPX3 can include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and a sealing layer TFE.

[0191] The substrate SUB may include a transparent insulating material to allow light to pass through. The substrate SUB may be a rigid substrate or a flexible substrate.

[0192] The pixel circuit layer PCL may be provided with circuit elements (for example, first to third transistors T1, T2, and T3) and signal wiring electrically connected to the circuit elements. The display element layer DPL may be provided with light-emitting elements (see "LD" in FIG. 3) electrically connected to the circuit elements of the first to third sub-pixels SPX1, SPX2, and SPX3, respectively.

[0193] At least one insulating layer may be disposed on the substrate SUB. For example, a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, and a fourth insulating layer INS4 may be disposed on the substrate SUB, stacked in sequence along the third direction DR3. For example, at least one conductive layer may be disposed on the substrate SUB. For example, the conductive layer may include a first conductive layer C1 disposed between the substrate SUB and the first insulating layer INS1, a second conductive layer C2 disposed on the second insulating layer INS2, and a third conductive layer C3 disposed on the fourth insulating layer INS4.

[0194] The first conductive layer C1 may include a first vertical power supply line PL1a, a second vertical power supply line PL2a, an initialization power supply line IPL, first to third data lines D1, D2, and D3, a bottom metal pattern BML, and first to third bottom electrodes LE1, LE2, and LE3. The second conductive layer C2 may include a first horizontal power supply line PL1b, a second horizontal power supply line PL2b, an additional conductive pattern ACP, first to ninth conductive patterns CP1 to CP9, first to third gate electrodes GE1, GE2, and GE3, a scan line SC, and a first sub-scan line SSL1. The third conductive layer C3 may include a first electrode AE1, a first-second electrode AE2, and a first-third electrode AE3.

[0195] The pixel circuit layer PCL may be disposed on a substrate SUB. The pixel circuit layer PCL may have the above-described first to fourth insulating layers INS1, INS2, INS3, and INS4 disposed thereon.

[0196] The first insulating layer INS1 (or buffer layer) may be disposed over the entire surface of the substrate SUB. The first insulating layer INS1 may prevent impurities from diffusing into the first to third transistors T1, T2, and T3. The first insulating layer INS1 may be an inorganic insulating film containing an inorganic material. The first insulating layer INS1 may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiOxNy), or at least one metal oxide such as aluminum oxide (AlxOy). The first insulating layer INS1 may be provided as a single layer or as a multi-layer structure (at least two or more layers). When the first insulating layer INS1 is provided as a multi-layer structure, each layer may be formed of the same material or different materials. The first insulating layer INS1 may be omitted depending on the material and process conditions of the substrate SUB.

[0197] The second insulating layer INS2 (or gate insulating layer) may be disposed over the entire surface of the first insulating layer INS1. The second insulating layer INS2 may include the same material as the first insulating layer INS1 described above, or may include a suitable material (or a material selected from the materials exemplified for the first insulating layer INS1). For example, the second insulating layer INS2 may include an inorganic insulating film containing an inorganic material. In an embodiment, the second insulating layer INS2 may be partially disposed on the first insulating layer INS1, as shown in FIG. 10. For example, the second insulating layer INS2 may be etched along with the base material of the second conductive layer C2 during the manufacturing process of the second conductive layer C2 so that the second insulating layer INS2 is disposed only below the second conductive layer C2. In this case, the second insulating layer INS2 may have the same width as the second conductive layer C2 located thereover, but is not limited to this.

[0198] A third insulating layer INS3 (or an interlayer insulating layer) may be provided and / or formed entirely on the second insulating layer INS2. The third insulating layer INS3 may include the same material as the first insulating layer INS1, or may include one or more suitable (or selected) materials from the materials exemplified as constituent materials of the first insulating layer INS1. As an example, the third insulating layer INS3 may be an inorganic insulating film containing an inorganic material.

[0199] The fourth insulating layer INS4 (or via layer) may be provided and / or formed entirely on the third insulating layer INS3. The fourth insulating layer INS4 may be an inorganic insulating film containing an inorganic material or an organic insulating film containing an organic material. The inorganic insulating film may include, for example, at least one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and aluminum oxide (AlxOy). The organic insulating film may include, for example, at least one of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin. In an embodiment, the fourth insulating layer INS4 may be an organic insulating film containing an organic material.

[0200] Each of the second to fourth insulating layers INS2, INS3, and INS4 may be partially opened to include a contact portion CNT (or a contact hole). The contact portion CNT may be a connection point for electrically connecting each of the first to third pixel circuits PXC1, PXC2, and PXC3 to the light-emitting elements LD of the first to third sub-pixels SPX1, SPX2, and SPX3.

[0201] The pixel circuit layer PCL of each of the first to third sub-pixels SPX1, SPX2, and SPX3 may include first to third transistors T1, T2, and T3 and a storage capacitor disposed on the first insulating layer INS1. For example, the pixel circuit layer PCL of the first sub-pixel SPX1 may include first to third transistors T1, T2, and T3 and a first storage capacitor Cst1 disposed on the first insulating layer INS1. The pixel circuit layer PCL of the second sub-pixel SPX2 may include first to third transistors T1, T2, and T3 and a second storage capacitor Cst2 disposed on the first insulating layer INS1. The pixel circuit layer PCL of the third sub-pixel SPX3 may include first to third transistors T1, T2, and T3 and a third storage capacitor Cst3 disposed on the first insulating layer INS1.

[0202] The first transistor T1 may include a first active pattern ACT1 disposed on a first insulating layer INS1, a first source electrode SE1, a first drain electrode DE1, and a first gate electrode GE1 disposed on a second insulating layer INS2. A lower metal pattern BML may be disposed below the first transistor T1. The lower metal pattern BML may be configured as a first conductive layer C1 located between the substrate SUB and the first insulating layer INS1, and may be formed integrally with a corresponding one of the first to third lower electrodes LE1, LE2, and LE3.

[0203] The second transistor T2 may include a second active pattern ACT2 disposed on the first insulating layer INS1, a second source electrode SE2, a second drain electrode DE2, and a second gate electrode GE2 disposed on the second insulating layer INS2.

[0204] The third transistor T3 may include a third active pattern ACT3 disposed on the first insulating layer INS1, a third source electrode SE3, a third drain electrode DE3, and a third gate electrode GE3 disposed on the second insulating layer INS2.

[0205] The first storage capacitor Cst1 may include a first bottom electrode LE1 disposed between the substrate SUB and a first insulating layer INS1 and a first top electrode UE1 overlapping the first bottom electrode LE1 with the first insulating layer INS1 sandwiched therebetween. The first bottom electrode LE1 may be configured as a first conductive layer C1, and the first top electrode UE1 may be configured as a semiconductor pattern disposed between the first insulating layer INS1 and a second insulating layer INS2 and doped with impurities to have conductivity. In the first subpixel SPX1, the first bottom electrode LE1 may be formed integrally with the lower metal pattern BML, and the first top electrode UE1 may be formed integrally with the first source electrode SE1 and the third source electrode SE3. The first top electrode UE1 may be electrically connected to a portion of the display element layer DPL, for example, the first-1 electrode AE1, via a corresponding contact portion CNT.

[0206] The second storage capacitor Cst2 may include a second bottom electrode LE2 disposed between the substrate SUB and the first insulating layer INS1 and a second top electrode UE2 overlapping the second bottom electrode LE2 with the first insulating layer INS1 sandwiched therebetween. The second bottom electrode LE2 may be configured as a first conductive layer C1, and the second top electrode UE2 may be configured as a semiconductor pattern disposed between the first insulating layer INS1 and the second insulating layer INS2 and doped with impurities to have conductivity. In the second subpixel SPX2, the second bottom electrode LE2 may be formed integrally with the lower metal pattern BML, and the second top electrode UE2 may be formed integrally with the first source electrode SE1 and the third source electrode SE3. The second top electrode UE2 may be electrically connected to a portion of the display element layer DPL, for example, the first-second electrode AE2, via a corresponding contact CNT.

[0207] The third storage capacitor Cst3 may include a third bottom electrode LE3 disposed between the substrate SUB and the first insulating layer INS1 and a third top electrode UE3 overlapping the third bottom electrode LE3 with the first insulating layer INS1 sandwiched therebetween. The third bottom electrode LE3 may be configured as a first conductive layer C1, and the third top electrode UE3 may be configured as a semiconductor pattern disposed between the first insulating layer INS1 and the second insulating layer INS2 and doped with impurities to have conductivity. In the third subpixel SPX3, the third bottom electrode LE3 may be formed integrally with the lower metal pattern BML, and the third top electrode UE3 may be formed integrally with the first source electrode SE1 and the third source electrode SE3. The third top electrode UE3 may be electrically connected to a portion of the display element layer DPL, for example, the first-third electrode AE3, via a contact CNT.

[0208] A third insulating layer INS3 and a fourth insulating layer INS4 may be continuously provided and / or formed on the first to third transistors T1, T2, and T3 and the first to third storage capacitors Cst1, Cst2, and Cst3.

[0209] A display element layer DPL may be provided and / or formed on the fourth insulating layer INS4.

[0210] The display element layer DPL may include a first light-emitting element LD1, a second light-emitting element LD2, a third light-emitting element LD3, and a pixel defining layer PDL. The first light-emitting element LD1 may be disposed in the display element layer DPL of the first sub-pixel SPX1 and electrically connected to the first pixel circuit PXC1. The second light-emitting element LD2 may be disposed in the display element layer DPL of the second sub-pixel SPX2 and electrically connected to the second pixel circuit PXC2. The third light-emitting element LD3 may be disposed in the display element layer DPL of the third sub-pixel SPX3 and electrically connected to the third pixel circuit PXC3. Each of the first to third light-emitting elements LD1, LD2, LD3 may be the light-emitting element LD described with reference to FIG. 3.

[0211] The first light emitting element LD1 may include a first-first electrode AE1, a first light emitting layer EML1, and a second electrode CE. The second light emitting element LD2 may include a first-second electrode AE2, a second light emitting layer EML2, and a second electrode CE. The third light emitting element LD3 may include a first-third electrode AE3, a third light emitting layer EML3, and a second electrode CE.

[0212] The 1-1 electrode AE1, the 1-2 electrode AE2, and the 1-3 electrode AE3 may be configured as a third conductive layer C3 provided and / or formed on the fourth insulating layer INS4 of the corresponding subpixel. The 1-1 electrode AE1, the 1-2 electrode AE2, and the 1-3 electrode AE3 may be arranged spaced apart from each other on the fourth insulating layer INS4. The 1-1 electrode AE1 may be the anode of the first light-emitting element LD1, the 1-2 electrode AE2 may be the anode of the second light-emitting element LD2, and the 1-3 electrode AE3 may be the anode of the third light-emitting element LD3.

[0213] The 1-1 electrode AE1 may be electrically connected to the first upper electrode UE1 of the first storage capacitor Cst1 through a corresponding contact portion CNT. The 1-2 electrode AE2 may be electrically connected to the second upper electrode UE2 of the second storage capacitor Cst2 through a corresponding contact portion CNT. The 1-3 electrode AE3 may be electrically connected to the third upper electrode UE3 of the third storage capacitor Cst3 through a corresponding contact portion CNT.

[0214] Each of the 1-1 electrode AE1, the 1-2 electrode AE2, and the 1-3 electrode AE3 may be made of a conductive substance (or material). The conductive substance may include an opaque metal. Examples of the opaque metal include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys thereof. However, the materials of the 1-1 electrode AE1, the 1-2 electrode AE2, and the 1-3 electrode AE3 are not limited to those in the above-described embodiment. According to an embodiment, the 1-1 electrode AE1, the 1-2 electrode AE2, and the 1-3 electrode AE3 may include a transparent conductive substance (or material). Examples of the transparent conductive substance (or material) include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO), and conductive polymers such as poly(3,4-ethylenedioxythiophene) (PEDOT). When the first-first electrode AE1, the first-second electrode AE2, and the first-third electrode AE3 include a transparent conductive substance (or material), another conductive layer made of an opaque metal may be added to reflect light emitted from the first, second, and third emitting layers EML1, EML2, and EML3 in the image display direction of the display device DD (or toward above the encapsulation layer TFE).

[0215] The 1-1 electrode AE1 may be located at least in the first light-emitting area EMA1, the 1-2 electrode AE2 may be located at least in the second light-emitting area EMA2, and the 1-3 electrode AE3 may be located at least in the third light-emitting area EMA3.

[0216] The pixel defining layer PDL is provided on the pixel circuit layer PCL in the non-emissive area NEA and can define (or partition) a first emissive area EMA1, a second emissive area EMA2, and a third emissive area EMA3. The pixel defining layer PDL can include an organic insulating film made of an organic material. Examples of the organic material include acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. According to an embodiment, the pixel defining layer PDL can include a light absorbing material or be coated with a light absorbing agent to absorb light entering from the outside. For example, the pixel defining layer PDL can include, but is not limited to, a carbon-based black pigment.

[0217] The pixel definition layer PDL is partially opened to include openings OP that expose a region of each of the first to third electrodes AE1, AE2, and AE3, and can protrude from the fourth insulating layer INS4 in the third direction DR3 along the peripheries of each of the first to third light emitting regions EMA1, EMA2, and EMA3.

[0218] A first light-emitting layer EML1 may be disposed on the first-1 electrode AE1 exposed by the opening OP in the pixel defining layer PDL, a second light-emitting layer EML2 may be disposed on the first-2 electrode AE2 exposed by another opening OP in the pixel defining layer PDL, and a third light-emitting layer EML3 may be disposed on the first-3 electrode AE3 exposed by yet another opening OP in the pixel defining layer PDL.

[0219] The first emitting layer EML1 may be located only on the first electrode AE1 within an opening OP of the pixel defining layer PDL, the second emitting layer EML2 may be located only on the first electrode AE2 within another opening OP of the pixel defining layer PDL, and the third emitting layer EML3 may be located only on the first electrode AE3 within yet another opening OP of the pixel defining layer PDL. Each of the first emitting layer EML1, the second emitting layer EML2, and the third emitting layer EML3 may be provided in a desired region of the corresponding subpixel (for example, above a region of the first electrode (see "AE" in FIG. 3) exposed by the opening OP of the pixel defining layer PDL) by an inkjet printing method or the like, but is not limited to this.

[0220] Each of the first, second, and third light-emitting layers EML1, EML2, and EML3 may have a multilayer thin film structure including a light-generating layer. For example, the first light-emitting layer EML1 may include a light-generating layer that generates and emits red light, the second light-emitting layer EML2 may include a light-generating layer that generates and emits green light, and the third light-emitting layer EML3 may include a light-generating layer that generates and emits blue light, but these examples are not limited thereto. According to an embodiment, each of the first, second, and third light-emitting layers EML1, EML2, and EML3 may include a light-generating layer that generates and emits white light. In this case, a color conversion layer may be provided to convert the white light (or first color light) into light of a specific color (or second color light).

[0221] A second electrode CE may be provided and / or formed on the first light emitting layer EML1, the second light emitting layer EML2, the third light emitting layer EML3, and the pixel defining layer PDL.

[0222] The second electrode CE may be a common layer provided in common to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The second electrode CE may be provided in the form of a plate over the entire display area DA, but is not limited thereto.

[0223] The second electrode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the first, second, and third light-emitting layers EML1, EML2, and EML3. The second electrode CE may be formed of a metal material or a transparent conductive material to have a relatively thin thickness. For example, the second electrode CE may be made of various transparent conductive materials. The second electrode CE may include at least one of various transparent conductive materials, such as indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide, and may be substantially transparent or semi-transparent to achieve a predetermined transmittance. This allows light emitted from the first, second, and third light-emitting layers EML1, EML2, and EML3 located below the second electrode CE to be emitted toward the upper side of the encapsulation layer TFE through the second electrode CE.

[0224] For example, the second electrode CE may be electrically connected to the second power supply wiring PL2.

[0225] A sealing layer TFE may be provided and / or formed all over the second electrode CE.

[0226] The encapsulation layer TFE may include a first incapsulation layer ENC1, a second incapsulation layer ENC2, and a third incapsulation layer ENC3, which are sequentially positioned on the second electrode CE. The first incapsulation layer ENC1 may be formed on the display element layer DPL (or the second electrode CE) and may be positioned over at least a portion of the display area DA and the non-display area NDA. The second incapsulation layer ENC2 may be formed on the first incapsulation layer ENC1 and may be positioned over at least a portion of the display area DA and the non-display area NDA. The third incapsulation layer ENC3 may be formed on the second incapsulation layer ENC2 and may be positioned over at least a portion of the display area DA and the non-display area NDA. According to an embodiment, the third incapsulation layer ENC3 may be positioned over the entire display area DA and the non-display area NDA.

[0227] The first and third incapsulation layers ENC1 and ENC3 may each be made of an inorganic film containing an inorganic material, and the second incapsulation layer ENC2 may be made of an organic film containing an organic material. The inorganic film may include, for example, silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). The organic film may include an organic insulating material such as a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0228] According to an embodiment, a color filter layer and / or a color conversion layer that converts light emitted from the first to third light-emitting elements LD1, LD2, and LD3 into light with excellent color reproducibility may be selectively provided and / or formed on the sealing layer TFE.

[0229] FIG. 11 is a schematic cross-sectional view showing a pixel PXL according to an embodiment, taken along line I-I' in FIG.

[0230] In order to avoid repetitive explanations regarding the embodiment of FIG. 11, differences from the previously described embodiment will be mainly described.

[0231] 1 to 5 and 11, the pixel PXL according to the embodiment may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, a sealing layer TFE, a color filter layer CFL, and an overcoat layer OC.

[0232] The color filter layer CFL may be formed on the encapsulation layer TFE through a continuous process. The color filter layer CFL may include color filters CF and a light-blocking pattern BM. The color filters CF may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0233] The first color filter CF1 may be disposed on one surface of the third incapsulation layer ENC3 of the encapsulation layer TFE to correspond to the first emission layer EML1. The second color filter CF2 may be disposed on one surface of the third incapsulation layer ENC3 of the encapsulation layer TFE to correspond to the second emission layer EML2. The third color filter CF3 may be disposed on one surface of the third incapsulation layer ENC3 of the encapsulation layer TFE to correspond to the third emission layer EML3.

[0234] The light-shielding pattern BM may be located adjacent to the first, second, and third color filters CF1, CF2, and CF3 on one surface of the third incapsulation layer ENC3 of the encapsulation layer TFE. For example, the light-shielding pattern BM may be located on one surface of the third incapsulation layer ENC3 in the non-emitting area NEA so as to correspond to the pixel defining layer PDL. The light-shielding pattern BM may include a light-shielding material. For example, the light-shielding pattern BM may be a black matrix, but is not limited thereto. According to the embodiment, the light-shielding pattern BM may include at least one light-shielding material and / or a reflective material, and may further direct light emitted from each of the first, second, and third emission layers EML1, EML2, and EML3 toward an image display direction of the display device DD, thereby improving light output efficiency. The light-shielding pattern BM may prevent color mixing of light emitted from the first, second, and third emission layers EML1, EML2, and EML3.

[0235] Each of the first, second, and third color filters CF1, CF2, and CF3 may contain a colorant, such as a dye or pigment, that absorbs wavelengths other than the corresponding color wavelength. The first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter. While the drawings illustrate a case in which adjacent color filters CF are spaced apart across a light-shielding pattern BM, adjacent color filters CF may at least partially overlap on the light-shielding pattern BM. According to an embodiment, the first to third color filters CF1, CF2, and CF3 are arranged to overlap each other in the non-light-emitting area NEA and can be used as a light-shielding member that blocks optical interference between adjacent sub-pixels. In this case, the light-shielding pattern BM may be omitted.

[0236] An overcoat layer OC may be disposed on the above-mentioned color filter layer CFL.

[0237] The overcoat layer OC is disposed on the color filter layer CFL to cover the color filter layer CFL and other underlying components. The overcoat layer OC prevents impurities such as moisture or air from penetrating from the outside and damaging or contaminating the color filter layer CFL. For example, the overcoat layer OC prevents colorants in the color filter layer CFL from diffusing into other components. The overcoat layer OC may include, but is not limited to, an inorganic insulating film containing an inorganic material.

[0238] Figure 12 is a schematic plan view showing a pixel PXL according to one embodiment, Figure 13 is a schematic plan view showing only the configuration included in the first conductive layer C1 in the pixel PXL of Figure 12, Figure 14 is a schematic plan view showing only the configuration included in the transistors T1, T2, T3 and the second conductive layer C2 in the pixel PXL of Figure 12, and Figure 15 is a schematic cross-sectional view along line III-III' in Figure 12.

[0239] The embodiment of FIG. 12 shows a modification of FIG. 4 in terms of the position of the initialization power supply wiring IPL and the like.

[0240] Regarding the embodiment of FIGS. 12 to 15, in order to avoid redundant explanation, differences from the previously described embodiment will be mainly described.

[0241] 1 to 3 and 12 to 15, the pixel PXL according to the embodiment may include a first sub-pixel SPX1 including a first pixel circuit PXC1, a second sub-pixel SPX2 including a second pixel circuit PXC2, and a third sub-pixel SPX3 including a third pixel circuit PXC3. Each of the first to third pixel circuits PXC1, PXC2, and PXC3 may include first to third transistors T1, T2, and T3 and a storage capacitor Cst.

[0242] In the pixel region PXA where the pixels PXL are provided, signal lines electrically connected to the first to third pixel circuits PXC1, PXC2, and PXC3 may be arranged. As an example, in the pixel region PXA, scan lines SC, first to third data lines D1, D2, and D3, a power supply line PL, and an initialization power supply line IPL may be arranged.

[0243] The scan line SC may be configured as a second conductive layer C2 extending along the first direction DR1 and disposed on a second insulating layer INS2. The scan line SC may include first and second sub-scan lines SSL1 and SSL2 extending in the second direction DR2. The first sub-scan line SSL1 may be formed integrally with the second gate electrode GE2 of the second transistor T2 of each of the first to third pixel circuits PXC1, PXC2, and PXC3. The second sub-scan line SSL2 may be formed integrally with the third gate electrode GE3 of the third transistor T3 of each of the first to third pixel circuits PXC1, PXC2, and PXC3.

[0244] The first data wiring D1 may be electrically connected to the second transistor T2 of the first pixel circuit PXC1, the second data wiring D2 may be electrically connected to the second transistor T2 of the second pixel circuit PXC2, and the third data wiring D3 may be electrically connected to the second transistor T2 of the third pixel circuit PXC3.

[0245] The power supply wiring PL may include a first power supply wiring PL1 and a second power supply wiring PL2. The first power supply wiring PL1 may include a first vertical power supply wiring PL1a and a first horizontal power supply wiring PL1b arranged on different layers and electrically connected via corresponding contact holes. The second power supply wiring PL2 may include a second vertical power supply wiring PL2a and a second horizontal power supply wiring PL2b arranged on different layers and electrically connected via corresponding contact holes. In the embodiment, the first vertical power supply wiring PL1a may be arranged between the first to third storage capacitors Cst1, Cst2, and Cst3 and the first data wiring D1.

[0246] The initialization power line IPL may be disposed between the second vertical power line PL2a and the first to third storage capacitors Cst1, Cst2, and Cst3 in a plan view. In this case, the second vertical power line PL2a may be located on one side (for example, the left side) of the initialization power line IPL, and the first to third storage capacitors Cst1, Cst2, and Cst3 may be located on the other side (for example, the right side) of the initialization power line IPL.

[0247] In this embodiment, the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 may be arranged along the second direction DR2 and positioned on the same line. The first to third storage capacitors Cst1, Cst2, and Cst3 may be positioned between the initialization power line IPL and the first vertical power line PL1a. In this case, the initialization power line IPL may be positioned on one side (for example, the left side) of the first to third storage capacitors Cst1, Cst2, and Cst3, and the first vertical power line PL1a may be positioned on the other side (for example, the right side) of the first to third storage capacitors Cst1, Cst2, and Cst3.

[0248] When the first vertical power supply line PL1a is located to the right of the first to third storage capacitors Cst1, Cst2, and Cst3, the first transistors T1 of each of the first to third pixel circuits PXC1, PXC2, and PXC3 electrically connected to the first vertical power supply line PL1a may be located to the right of the storage capacitor of the corresponding pixel circuit. In this embodiment, the first to third data lines D1, D2, and D3 may be located apart from the first vertical power supply line PL1a along the first direction DR1 from one side (for example, the right side) of the first vertical power supply line PL1a. When each of the first to third data lines D1, D2, and D3 is located to the right of the first vertical power line PL1a, the second transistor T2 of the first pixel circuit PXC1 electrically connected to the first data line D1, the second transistor T2 of the second pixel circuit PXC2 electrically connected to the second data line D2, and the second transistor T2 of the third pixel circuit PXC3 electrically connected to the third data line D3 may be located to the right of the storage capacitor of the corresponding pixel circuit.

[0249] When the initialization power supply wiring IPL is located to the left of the first to third storage capacitors Cst1, Cst2, and Cst3, the third transistor T3 of each of the first to third pixel circuits PXC1, PXC2, and PXC3 electrically connected to the initialization power supply wiring IPL may be arranged to the left of the storage capacitor of the corresponding pixel circuit.

[0250] As described above, the first and second transistors T1 and T2 may be arranged to the right of the first, second, and third storage capacitors Cst1, Cst2, and Cst3, respectively, and the third transistor T3 may be arranged to the left of the first, second, and third storage capacitors Cst1, Cst2, and Cst3. In this case, it is possible to reduce or prevent the electrical connection between the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2 from directly affecting the first, second, and third storage capacitors Cst1, Cst2, and Cst3, respectively. As a result, the area (or size) of the first gate electrode GE1 of the first transistor T1 in each of the first, second, and third pixel circuits PXC1, PXC2, and PXC3 (or the first, second, and third sub-pixels SPX1, SPX2, and SPX3) can be reduced, thereby ensuring an additional area for the storage capacitor of the corresponding sub-pixel by the reduced area (or size) of the first gate electrode GE1, and increasing the capacitance of the storage capacitor.

[0251] Although the present invention has been described above with reference to preferred embodiments, it will be understood that those skilled in the art or those with ordinary knowledge in the art can make various modifications and changes to the present invention without departing from the technical scope of the present invention as defined in the claims below.

[0252] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims

1. first, second, and third sub-pixels adjacent to each other, each sub-pixel having a storage capacitor; a scan line extending in a first direction and selectively transmitting a scan signal and a control signal to each of the first to third sub-pixels; a data line that transmits a data signal to each of the first to third sub-pixels and extends in the second direction intersecting the first direction; a first power supply wiring electrically connected to each of the first, second, and third sub-pixels and supplied with a first driving power supply voltage; The first power wiring is located between the storage capacitor and the data wiring.

2. A substrate; a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer disposed in this order on the substrate; a second power supply wiring to which a second driving power supply voltage different from the first driving power supply voltage is supplied; an initialization power supply wiring to which an initialization power supply voltage is supplied; the first power supply wiring includes a first vertical power supply wiring configured as a first conductive layer disposed on the substrate and a first horizontal power supply wiring configured as a second conductive layer disposed on the second insulating layer; The display device of claim 1 , wherein the first vertical power supply wiring is located between the storage capacitor and the data wiring of each of the first, second, and third sub-pixels in a plan view.

3. Each of the first, second, and third sub-pixels comprises: A light-emitting element; a first transistor for controlling a current of the light emitting element; a second transistor connected between the data line and the gate electrode of the first transistor and turned on by the scan signal; a third transistor connected between the initialization power supply wiring and the source electrode of the first transistor and turned on by the control signal; 3. The display device of claim 2, further comprising: the storage capacitor including a lower electrode electrically connected to the gate electrode of the first transistor and the source electrode of the second transistor; and an upper electrode electrically connected to the source electrode of the first transistor and the source electrode of the third transistor.

4. The display device of claim 3 , wherein the first, second, and third transistors are located on one side of the storage capacitor.

5. the second power supply wiring includes a second vertical power supply wiring configured as the first conductive layer and a second horizontal power supply wiring configured as the second conductive layer; 4. The display device according to claim 3, wherein the storage capacitor is located between the second vertical power supply wiring and the first vertical power supply wiring in a plan view.

6. 6. The display device according to claim 5, wherein the initialization power supply wiring is located between the first vertical power supply wiring and the data wiring in plan view.

7. The display device of claim 6 , wherein the gate electrode of the first transistor of each of the first, second, and third sub-pixels is disposed between the storage capacitor and the first vertical power line.

8. The display device according to claim 3 , wherein the lower electrode is disposed on the substrate, and the upper electrode is disposed on the first insulating layer and overlaps the lower electrode with the first insulating layer sandwiched therebetween.

9. The display device according to claim 8 , wherein the upper electrode is disposed in the same layer as the active patterns of the first, second, and third transistors.

10. The display device according to claim 9 , wherein the upper electrode is formed integrally with the source electrode of the first transistor and the source electrode of the third transistor.

11. The light-emitting element is a first electrode configured as a third conductive layer disposed on the fourth insulating layer; a light-emitting layer disposed on the first electrode; The display device according to claim 3 , further comprising: a second electrode disposed on the light-emitting layer.

12. 12. The display device according to claim 11, wherein the first electrode is electrically connected to the source electrode of the first transistor via a contact portion that penetrates the second to fourth insulating layers.

13. The display device according to claim 5 , wherein the initialization power wiring is located between the second vertical power wiring and the storage capacitor in a plan view.

14. 14. The display device of claim 13, wherein the initialization power line is located on one side of the storage capacitor and the first vertical power line is located on the other side of the storage capacitor when viewed in a plane.

15. 15. The display device of claim 14, wherein, in a plan view, the third transistor of the first, second, and third transistors is located on one side of the storage capacitor, and the first and second transistors are located on the other side of the storage capacitor.

16. Each of the first, second, and third sub-pixels comprises: a sealing layer disposed on the light-emitting element; a color filter layer disposed on the sealing layer; The display device according to claim 3 , further comprising: an overcoat layer disposed on the color filter layer.

17. A substrate; first, second, third, and fourth insulating layers sequentially stacked on the substrate; first, second, and third sub-pixels, each including a pixel circuit including a storage capacitor and first, second, and third transistors disposed on the substrate, and a light-emitting element electrically connected to the pixel circuit; scan lines disposed on the substrate for selectively transmitting scan signals and control signals to the first, second, and third sub-pixels; data lines transmitting data signals to the first, second, and third sub-pixels; a first power supply wiring to which a first power supply voltage is supplied; a second power supply wiring to which a second power supply voltage different from the first power supply voltage is supplied; an initialization power supply wiring to which an initialization power supply voltage different from the first and second power supply voltages is supplied, The display device, wherein the gate electrode of the first transistor is located between the storage capacitor and the first power supply wiring.

18. the first power supply wiring includes a first vertical power supply wiring disposed on the substrate and a first horizontal power supply wiring disposed on the second insulating layer; The display device of claim 17 , wherein the first vertical power supply line is located between the storage capacitor and the data line.

19. The display device of claim 18 , wherein the first, second, and third transistors are located on one side of the storage capacitor in a plan view.

20. 20. The display device of claim 18, wherein the storage capacitor is located between the initialization power wiring and the first vertical power wiring in a plan view.

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