Semiconductor device

Abstract

To provide a semiconductor device with improved operation speed.SOLUTION: The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes first to third transistors having the same conductivity type and a capacitor. Gates of the first to third transistors are electrically connected to a write word line, a first terminal of the capacitor, and a read word line. A second terminal of the capacitor is electrically connected to the read bit line. One of a source and a drain of the first transistor is electrically connected to the write bit line, and the other is electrically connected to a gate of the second transistor. The second transistor and the third transistor are electrically connected in series between the read bit line and the first wiring. Channel formation regions of the first to third transistors each include a metal oxide layer, for example.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] One aspect of the invention disclosed in the specification of this application is a semiconductor device, a method of operating the same, a method of using the same, The present invention relates to a semiconductor device and a manufacturing method thereof. It's not that.

[0002] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and is a semiconductor element (transistor). Transistors, diodes, photodiodes, etc.), and devices that have such circuits. It also refers to any device that can function by utilizing the characteristics of semiconductors. For example, integrated circuits, Chips with integrated circuits and electronic components that house chips in packages are types of semiconductor devices. In addition, a storage device, a display device, a light-emitting device, a lighting device, an electronic device, etc. may be a semiconductor device or may have a semiconductor device. [Background technology]

[0003] A transistor having a metal oxide in the channel formation region (hereinafter referred to as a "metal oxide transistor") These transistors are sometimes called "oxide semiconductor transistors," "OS transistors," or "OS transistors.") For example, in the embedded storage device described in Non-Patent Document 1, Transistor (capacitor element) An OS transistor is used as the write transistor of the cell. In the memory device described in Non-Patent Document 2, the write transistor of the 2T1C type gain cell is S transistors are used, and Si transistors are used as readout transistors. .

[0004] In this specification, as in Non-Patent Documents 1 and 2, the memory cell is provided with an OS transistor. The storage device used is sometimes called the "OS storage device."

[0005] Logic circuits include static logic circuits, dynamic logic circuits, and pseudo (p Dynamic logic circuits can be classified into dynamic (seudo) logic circuits. Since it is a circuit that operates by temporarily storing data in nodes, it is called static logic. Compared to a conventional circuit, the leakage current of a transistor becomes a problem. A technology that uses OS transistors to suppress voltage drops at dynamic nodes is disclosed. It has been done. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-17693 [Non-patent literature]

[0007] [Non-Patent Document 1] T. Onuki et al., “Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS,” IEEE J. Solid-State Circuits, Vol. 52, No. 4, pp. 925-932, 2017. [Non-patent document 2] T. Ishizu et al., “A 140MHz 1Mbit 2T1C Gain-Cell Memory with 60-nm Indium-Gallium-Zinc Oxide Transistor Embedded into 65-nm CMOS Logic Process Technology,”Symp.VLSI Circuits Dig.Tech.Papers,pp.162-163,2017. Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one aspect of the present invention is to provide a novel semiconductor device including transistors of a single conductivity type and providing a method of operation of the present invention, reducing the number of transistors, increasing the operating speed, reducing power consumption, or This achieves high rewrite endurance.

[0009] One embodiment of the present invention does not necessarily solve all of these problems. This does not preclude the existence of problems. Problems other than those listed will be obvious from the description of this specification. These problems can also be addressed as an aspect of the present invention. [Means for solving the problem]

[0010] (1) One aspect of the present invention is a write word line, a read word line, a write bit line, a read A semiconductor device having a bit line, a first wiring, and a memory cell, the memory cell being connected to the same conductor. The first to third transistors are of the same type as the first to third transistors, and a capacitor. The gate is electrically connected to a write word line, a first terminal of the capacitance element, and a read word line. a second terminal of the capacitance element electrically connected to a read bit line; One of the source and drain of the second transistor is electrically connected to the write bit line, and the other is connected to the second transistor. The second and third transistors are electrically connected to the gate of the read bit. The second wiring is electrically connected in series between the ground line and the first wiring.

[0011] (2) In the above-mentioned configuration (1), the first to third transistors each have a back gate. The back gates are provided with first to third voltages input thereto, respectively.

[0012] (3) In one aspect of the present invention, an input node, first to fourth wirings, and the first to fourth wirings of the same conductivity type are connected to each other. A dynamic logic circuit having a first to fourth transistor, The first signal is input to the first transistor, and the source and drain of the first transistor are connected to the first wiring and the input node. The second to third transistors are electrically connected to the second wiring and the third wiring, respectively. The four transistors are electrically connected in series, and the gate of the second transistor is connected to the input of a second signal. The gate of the fourth transistor receives an inverted signal of the second signal, and the gate of the third transistor receives an inverted signal of the second signal. The gate is electrically connected to the input node, and the third transistor has a back gate. The back gate is electrically connected to the fourth wiring.

[0013] (4) One aspect of the present invention is a method for generating a dynamic signal from an input node, a first dynamic node, a second dynamic node, and a and a dynamic logic circuit having first through sixth transistors of the same conductivity type - Patents.com The first dynamic node is connected to the drains of the first to third transistors. are electrically connected to the second dynamic node, and the fourth to sixth transistors are connected to the second dynamic node. The drains of the first and fourth transistors are electrically connected to the input node. the sources of the second, third, fifth and sixth transistors are electrically connected to the first A voltage is input, and the first signal is input to the gates of the first transistor and the sixth transistor. The gates of the fourth transistor and the third transistor receive a second signal. The gates of the first and fifth transistors are connected to a dynamic logic circuit to which a third signal is input.

[0014] (5) One aspect of the present invention is a capacitor including a first input node, a second input node, an output node, and a first capacitance element. a buffer circuit having a capacitor, a second capacitor, and first to sixth transistors of the same conductivity type; The first terminal of the first capacitance element is electrically connected to a first input node, and the second capacitance element is The first terminal is electrically connected to the second input node, and the second terminal of the first capacitance element is electrically connected to the first transistor. The source of the first transistor, the drain of the second transistor, and the gate of the third transistor are electrically connected. The second terminal of the second capacitance element is connected to the source of the fourth transistor and the source of the fifth transistor. The drain of the sixth transistor and the gate of the sixth transistor are electrically connected to each other, and the third transistor is connected to the output node. The source of the transistor and the drain of the sixth transistor are electrically connected.

[0015] In this specification, ordinal numbers such as "first," "second," and "third" are used to indicate order. It may be used to avoid confusion between components. In these cases, the use of ordinal numbers does not limit the number of components. For example, "first" By replacing the terms "second" or "third," one embodiment of the present invention can be described.

[0016] In this specification, when it is stated that X and Y are connected, it means that X and Y are electrically connected. There are cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. The case where the device is connected is also considered to be disclosed in this specification. Connection relationships, for example, are not limited to those shown in the drawings or text, but include connections shown in the drawings or text. Any other connection relationships than those shown in the figure or text are also considered to be disclosed. (For example, a device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.).

[0017] A transistor has at least three terminals called a gate, a source, and a drain. The transistor may further have a back gate. The control terminal controls the conduction state of the two terminals that function as source or drain. are the input and output terminals of the transistor. The two input and output terminals are the conductivity type (n The potential applied to the three terminals of the transistor varies depending on the type of transistor (channel type, p-channel type) and the Therefore, one becomes the source and the other becomes the drain. The terms "gate" and "drain" can be interchanged. The two terminals may be referred to as the first terminal, the second terminal, etc.

[0018] Depending on the circuit configuration and device structure, a node may be a terminal, wiring, electrode, conductive layer, conductor, or insulator. It is possible to call them pure regions, etc. Also, terminals, wiring, etc. can be called nodes. It is possible to do this.

[0019] Voltage is the voltage between a certain potential and a reference potential (e.g., ground potential (GND) or source potential). Therefore, voltage can be replaced with electric potential. Therefore, even if it is written as GND, it does not necessarily mean 0V. Sometimes it doesn't taste like it.

[0020] In this specification, the terms "above" and "below" that indicate the positional relationship between components are used. , may be used for convenience in explaining with reference to the drawings. The relationship changes depending on the direction in which each component is depicted. The terms are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0021] As used herein, the terms "film" and "layer" are used interchangeably, or For example, the term "conductive layer" can be used interchangeably with the term "conductive layer" In some cases, it may be possible to change the term to "conductive film." For example, the term "insulating film" It may be possible to change the term to "insulating layer." [Effects of the Invention]

[0022] According to one aspect of the present invention, a novel semiconductor device including a single conductivity type transistor and a Providing a method for operating the device, reducing the number of transistors, improving the operating speed, reducing power consumption, or It is possible to realize rewrite endurance.

[0023] The description of multiple effects does not preclude the existence of other effects. It is not necessary to have all of the effects exemplified above. Problems, effects, and novel features other than those described above will be apparent from the description and drawings of this specification. It becomes clear. [Brief explanation of the drawings]

[0024] [Figure 1] A: A block diagram showing an example of the configuration of a memory device. B: A circuit diagram showing an example of the configuration of a memory cell. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a memory cell array. [Figure 3] FIG. 10 is a circuit diagram showing an example of the configuration of a row decoder. [Figure 4] FIG. 10 is a circuit diagram showing an example of the configuration of a decoder. [Figure 5] FIG. 2 is a circuit diagram showing a configuration example of a peripheral circuit. [Figure 6] 1A is a circuit diagram showing an example of the configuration of an output circuit, and B is a timing chart showing an example of the operation of the output circuit. [Figure 7] 4 is a timing chart showing an example of the operation of the storage device. [Figure 8] 4 is a timing chart showing an example of the operation of the storage device. [Figure 9] 5A and 5B are schematic diagrams of output waveforms of a read bit line and a read circuit. [Figure 10] FIG. 1 is a circuit diagram showing a configuration example of a memory cell. [Figure 11] FIG. 1 is a schematic perspective view showing an example of the configuration of an application processor chip. [Figure 12] A: Block diagram showing an example of the configuration of a processing unit. B: Block diagram showing a schematic example of stacking a processing engine and an embedded storage device. [Figure 13] FIG. 1 is a schematic diagram showing a configuration example of an electronic device. [Figure 14] A and B are cross-sectional views showing examples of the structure of an OS transistor. [Figure 15] A: Circuit diagram of the fabricated four-stage shift register. B: Operation waveforms of the four-stage shift register. [Figure 16] FIG. 10 is a diagram showing calculation results of the read access time of a memory cell. [Figure 17] A, B: Shmoo plots (VDDM / VH vs. tWPW), (VDDM / VH vs. tRAC) of the storage device at room temperature. [Figure 18] A: Circuit diagram of the test circuit, B: Measurement results of the current-voltage characteristics of the readout transistor, C: Calculation results of the threshold voltage of the readout transistor. [Figure 19] A: Circuit diagram of the test circuit. B: Calculation results of voltage VSN. [Figure 20] A: Micrograph of the storage device. B: Table showing the specifications of the storage device. DETAILED DESCRIPTION OF THE INVENTION

[0025] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be implemented in the following manner. The present invention is not to be construed as being limited to the description of the embodiments and examples shown below.

[0026] The following embodiments and examples can be combined as appropriate. In the embodiments, a plurality of configuration examples (including manufacturing method examples, operation method examples, and usage method examples) are shown. In this case, the configuration examples may be appropriately combined with each other, and the configuration examples described in other embodiments may be appropriately combined with each other. It is also possible to combine one or more of the configuration examples as appropriate.

[0027] In the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the scale is not necessarily limited to that. The drawings are only a schematic representation of an ideal example. The figures are not limited to the shapes or values ​​shown in the drawings. For example, the signal due to noise may be signal, voltage, or current variations, or timing errors can include current variations, etc.

[0028] First Embodiment As an example of a semiconductor device, a memory device including an OS transistor will be described. The memory device 100 shown in FIG. 1A includes a memory cell array 110 and a peripheral circuit 120. Voltages such as VDDM, VSSM, and Vbg1 to Vbg3 are input to the device 100. DDM and VSSM are the high and low power supply voltages, respectively. For example, the voltage VSSM is This is the ground potential (GND).

[0029] The memory cell array 110 and the peripheral circuit 120 are configured with OS transistors. The memory cell array 110 has a plurality of memory cells 11. As an example, the arrangement of the memory cells 11 is The peripheral circuit 120 includes a row decoder 122, a write circuit 124, a read circuit 126, a write circuit 128, a write circuit 129, a write circuit 130, a write circuit 131, a write circuit 132, a write circuit 133, a write circuit 134, a write circuit 135, a write circuit 136, a write circuit 137, a write circuit 138, a write circuit 139 The peripheral circuit 120 includes a data input circuit 125 and an output circuit 126. 0], address signals RA[4:0], RAB[4:0], and various control signals are input. As an example, the memory width of the storage device 100 is 32 bits, and the data DIN[31: DOUT[31:0] and DOUT[31:0] are write data and read data, respectively.

[0030] Metal oxides used in OS transistors include Zn oxide, Zn-Sn oxide, and Ga-S n-oxide, In-Ga oxide, In-Zn oxide, In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf). Oxides containing aluminum, gallium, yttrium, copper, vanadium, and beryl Sodium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum buten, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or The present invention may also include one or more selected from the group consisting of magnesium, etc. In the literature, metal oxynitrides such as In-M-Zn oxynitrides are included in the category of metal oxides. It will be included.

[0031] To improve the reliability and electrical characteristics of OS transistors, we have developed various types of OS transistors, such as CAAC-OS and nc-OS. It is preferable to use a metal oxide having a crystalline portion. -aligned crystalline oxide semiconductor CAAC-OS has a c-axis orientation and multiple lattice structures in the ab-plane direction. The nanocrystals are connected to form a distorted crystal structure. In the region where crystals are connected, between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement The nc-OS refers to the area where the lattice orientation changes. It is an abbreviation for line oxide semiconductor.

[0032] Metal oxides have a large band gap (for example, 2.5 eV or more), making them suitable for use in OS transistors. For example, when the voltage between the source and drain is 3.5 V and the temperature is 5℃), the off-current per 1 μm of channel width is 1×10 -20 Less than A, 1 x 1 0 -22 Less than A or 1 x 10 -24 The minimum off-state current can be less than A. The on / off ratio of the drain current can be between 20 and 150 orders of magnitude. Therefore, in a memory element using an OS transistor, the voltage is transferred from the retention node to the OS transistor. Since the amount of charge leaked from the device is extremely small, it can be used as a nonvolatile memory element. be.

[0033] Metal oxides have a large band gap, which makes it difficult for electrons to be excited, and the effective mass of holes is Because of this, OS transistors have a higher Therefore, for example, avalanche breakdown may not occur easily. Hot carrier degradation can be suppressed in some cases. , the OS transistor can be driven at a high drain voltage.

[0034] OS transistors are accumulation-type transistors that use electrons as majority carriers. Compared with an inverted transistor having a pn junction (typically a Si transistor), Drain-Induced Barrier Loss (DIBL), one of the channel effects, In other words, OS transistors have a lower thermal resistance than Si transistors. High resistance to short channel effects.

[0035] OS transistors have high resistance to short channel effects, which increases the signal The use of OS transistors allows the channel length to be reduced without degrading reliability. As the channel length becomes smaller, the drain electric field becomes stronger. However, as mentioned above, OS transistors have a higher avalanche breakdown rate than Si transistors. It's hard to wake up.

[0036] Since OS transistors have high resistance to short channel effects, the gate insulating layer is made of Si transistors. For example, the channel length and width can be 50 n. Even for miniaturized OS transistors of less than 10 nm, a thick gate insulating layer of about 10 nm is required. A thick gate insulating layer can reduce the gate parasitic capacitance. This allows for improved circuit operating speed. The gate leakage current is reduced, resulting in improved static power dissipation. Power consumption can be reduced.

[0037] <<Memory Cells>> As shown in FIG. 1B, a write word line WWL, a read word line RWL, a write bit line W BL, the read bit line RBL, the wiring PL, and BGC1 to BGC3. The wirings PL and BGC1 to BGC3 are connected to the power supply lines VDDM, Vb g1, Vbg2, and Vbg3 are input respectively.

[0038] The memory cell 11 is a 3T1C type gain cell, and includes transistors M1 to M3, a capacitance element C The transistors M1 to M3 are write transistors, read transistors, and The node SN is a storage node.

[0039] The gate, source, drain and back gate of the transistor M1 are connected to the write word line WW L, the node SN, the write bit line WBL, and the wiring BGC1. The gate, source, drain and back gate of transistor M2 are connected to node SN, read The bit line RBL, the source of the transistor M3, and the wiring BGC2 are electrically connected to the The gate, drain, and back gate of the transistor M3 are connected to the read word line RWL , and the wiring PL and BGC3 are electrically connected to the first terminal and the second terminal of the capacitance element CS1, respectively. The transistor is electrically connected to a node SN and a read bit line RBL.

[0040] Data is written by charging and discharging node SN, and transistor M3 is turned on. Therefore, in principle, there is no limit to the number of times that the memory cell 11 can be rewritten. Data can be written and read with low energy, and no power is consumed to retain data. Since the transistor M1 is an OS transistor with a very small off-state current, the memory cell 11 can store data. High durability.

[0041] By inputting voltages Vbg1 to Vbg3 to the back gates of the transistors M1 to M3, respectively As a result, the threshold voltages (hereinafter sometimes referred to as "Vt") of the transistors M1 to M3 are It is preferable to provide a back gate at least for the transistor M2. As will be described later, the voltage Vbg2 shifts the Vt of the transistor M2 to the negative voltage side. By softening the memory cell, high data retention characteristics and high speed reading are possible.

[0042] <<Memory cell array>> FIG. 2 shows an example of the circuit configuration of the memory cell array 110. The wiring PL is shared by two adjacent rows. In the memory cell array 110, for example, the wiring PL is shared by two adjacent columns. A part or all of the wirings BGC1 to BGC3 may be shared by two adjacent rows. Good too.

[0043] In this specification, when it is necessary to specify one of a plurality of read bit lines RBL, is the read bit line RBL <0> When the read bit line RBL is written as , refers to any read bit line RBL. The same applies to other elements. For example, Read bit line RBL <0> represents the read bit line of the 0th row, and memory cells 11<31, 0> represents the memory cell 11 in the 31st row and 0th column. When using codes with row and column numbers added to them to distinguish them from elements of Cell 11 For example, transistor M1<0,0> is the transistor of memory cell 11<0,0>. Represents Sta M1.

[0044] <<Peripheral circuits>> The peripheral circuit 120 is composed of transistors of a single conductivity type (here, n-channel type). It is easy to control the conductivity type of silicon by impurity introduction techniques. It is very difficult to control the conductivity type of metal oxide semiconductors. oxides (e.g., In oxides), or metal oxides containing zinc (e.g., Zn oxides) Although n-type semiconductors have been successfully fabricated, p-type semiconductors have not yet been fabricated. A practical level complementary logic circuit (also called a CMOS logic circuit) that is composed only of Therefore, the peripheral circuit 120 does not include a complementary logic circuit but a simple logic circuit. A logic circuit consisting of one conductivity type (here, n-channel type) transistors is used. In this specification, a circuit configured with transistors of a single conductivity type is referred to as a "single These are sometimes called "conductivity circuits."

[0045] The peripheral circuit 120 uses a dynamic logic circuit. The circuit must maintain the voltage of the dynamic node during the evaluation period. Since the off-state characteristics of Si transistors are insufficient, dynamic logic The circuit operates at a low frequency or when the clock signal is stopped. In contrast, the voltage of the OS transistor is not maintained. The OS dynamic logic circuit (hereinafter referred to as "OS dynamic logic circuit") The transistor has an extremely small off-state current, so it can suppress charge leakage from the dynamic node. In other words, the clock signal frequency does not need to be increased more than necessary, so dynamic power consumption is reduced. Furthermore, clock gating and power gating are possible. In the first embodiment, the features of such an OS dynamic logic circuit are specifically described. will be explained.

[0046] In general, dynamic logic circuits use fewer transistors than static logic circuits. The OS dynamic logic circuit has a Therefore, there is no need to provide a circuit (such as a keeper circuit) for By applying a micrologic circuit to the peripheral circuit 120, the area of ​​the memory device 100 can be reduced. Cut.

[0047] Specific examples of the peripheral circuit 120 will be described below with reference to FIGS. 3 to 5, 6A, 6B, and 7 to 9. The configuration will be explained.

[0048] <Row Decoder 122> As shown in FIG. 3, the row decoder 122 receives voltages VDDM, VSSM, and an address signal RA [4:0], RAB[4:0], and signals WE, RE, PREN, and PREP are input.

[0049] The signals WE and RE are a write enable signal and a read enable signal, respectively. E and RE set the state of the storage device 100. When both signals WE and RE are "L" (low level), At some point, the storage device 100 is in a standby state. When the signal RE is at "H", data is written. Read out the data.

[0050] The signals PREP and PREN are inverses of each other. In this case, the signals PREN and PREP function as clock signals and Controls pre-charge or pre-discharge.

[0051] The row decoder 122 includes a decoder 130 and a word line driver 132. decodes the address signals RA[4:0] and RAB[4:0] and selects the row to be accessed. The word line driver 132 has the function of specifying the write operation of the row specified by the decoder 130. Select (also called "assert") the write word line WWL or the read word line RWL. It has a function.

[0052] (Decoder 130) The decoder 130 is configured with a precharge type pass transistor logic circuit. The transistor M19 and the plurality of circuits 20 are arranged in a complete halving of the height 4. It is a tree structure, and the number of circuits 20 is 31 (=2 5 -1). It is placed at the root of the binary tree structure. The transistor M19 is provided between the input node of the circuit 20 and the power supply line for the voltage VDDM. The signal PREN is input to the gate of the transistor M19. 19 functions as a pull-up circuit. The signal PREN is an enable signal for the decoder 130. It functions as:

[0053] In this specification, the power supply line for voltage VDDM may be referred to as the "VDDM line." A similar description may also be used for power lines.

[0054] The word line driver 132 has 32 circuits 22. The circuits 22 are arranged at the leaves of a binary tree structure. The circuit 22 is electrically connected to the circuit 20. <j>(j is between 0 and 31 The two output nodes of (integer) are connected to the write word line WWL. <j>, read word line RWL <j>are electrically connected to the respective

[0055] 4 shows an example of the configuration of the circuit 20 arranged at a depth p (p is an integer between 0 and 4). Reference numeral 20 denotes a pass transistor logic circuit composed of transistors M20 and M21. In the circuit 20, the node A0 is an input node, and the nodes X1 and X0 are output nodes. The gates of the transistors M20 and M21 are connected to the address signals RA[4-p] and RAB[4- p] are input respectively.

[0056] The circuit 20 functions as a 1-input, 2-output demultiplexer. p] is "H" (="1"), node A0 and node X1 are conductive, and the address signal When RA[4-p] is "L" (="0"), node A0 and node X0 are conductive.

[0057] In the transistor M19, the back gate and the gate are connected. The Vt of transistor M19 changes dynamically. Transistor M19 is on. When the transistor M19 is turned on, the same positive voltage as the gate is input to the back gate, and the Vt of the transistor M19 is negative. Therefore, the current driving capability of the transistor M19 is improved. The decrease in output voltage due to t (hereinafter referred to as "Vt drop") can be suppressed. , the Vt of the transistors M20 and M21 also changes dynamically.

[0058] Six OS transistors are electrically connected in series to the node A0 of the final stage circuit 20. The back gate and gate of each OS transistor are electrically connected to each other, This makes it possible to improve the operating speed of the driver 130 and suppress the voltage drop at the output node.

[0059] (word line driver 132) As shown in FIG. 5, the circuit 22 is a discharge type dynamic logic circuit. The input node A1 is an input node. and is electrically connected to the node X0 or X1 of the final stage circuit 20. Node Y1, Y2 is a dynamic node, and Y3 is a write word line WWL, Y4 is a read word line R5, and Y5 is a read word line R6. WL is electrically connected.

[0060] The signal PREP is input to the gates of the transistors M23 and M24, and the transistors M25 and M26 are The signal RE is input to the gate of M28, and the signal WE is input to the gates of transistors M26 and M27. The back gates of the transistors M23 to M28 are electrically connected to the gates of the transistors M23 to M28. The back gate and gate are electrically connected. By configuring 22, the operating speed can be improved without inputting an external voltage for Vt control. can.

[0061] The transistors M23 and M25 are connected to the node Y1 and the power supply line for the voltage VSSM (hereinafter referred to as "VSS The transistors M24 and M26 are electrically connected in parallel between the Transistor M2 is electrically connected in parallel between node Y2 and the VSSM line. 7 controls the conduction between node A1 and node Y1, and transistor M28 controls the conduction between node A1 and node Y2. Controls the conduction of Y2.

[0062] The period when the signal PREP is at "H" is the discharge period, and the period when the signal PREP is at "L" is the discharge period. The period when the voltages of the nodes Y1 and Y2 are "L" is the evaluation period. Specifically, since the transistors M23 and M24 are on, the node Y Therefore, during the discharge period, the voltage VSSM is input to Y1 and Y2. The write word line WWL and the read word line RWL are in a non-selected state.

[0063] The signals WE and RE function as enable signals for the circuit 22. During the evaluation period, the signals When WE or RE goes to "H", the circuit 22 becomes active and the logic of the node A1 Specifically, when the signal WE is "H", If so, it is determined whether the write word line WWL is in a selected state or a non-selected state. On the other hand, when the signal RE is "H", the read word line RWL is in a selected state or a non-selected state. It is determined whether

[0064] When the signal WE is "H", the voltage VSSM is input to the read word line RWL. The write word line WWL is connected to the node A1, so the node When the voltage of node A1 is "H", it is in the selected state, and when the voltage of node A1 is "L", it is in the unselected state. When the signal RE is at "H", the write word line WWL is at the voltage VSS Since M is input, the non-selected state is maintained. The read word line RWL is connected to the node A1. Therefore, if the voltage of node A1 is "H", it will be in the selected state, and the voltage of node A1 will If it is "L", the non-selected state is maintained.

[0065] <Write circuit 124> In the write circuit 124, the circuit 24 shown in FIG. 5 is provided for each write bit line WBL. The circuit 24 includes nodes A3 and Y3 and transistors M41 to M44.

[0066] Nodes A3 and Y3 are the input node and the output node, respectively. (i is 0 In the example (an integer from 1 to 31), data DIN[i] is input to node A3, and node Y3 is Write bit line WBL electrically connected to

[0067] The transistors M41 to M44 are electrically connected in series between the VSSM line and the VDDM line. The gate of transistor M42 is node A3, and the drain of transistor M41 is The connection node between the input of the transistor M41 and the source of the transistor M42 is the node Y3. The signals PREP, PREN, and WE are input to the gates of M41, M43, and M44, respectively. In the transistors M41 to M44, the back gates and gates are electrically connected. The circuit 24 is configured with an OS transistor whose back gate and gate are electrically connected. This improves the operating speed of the circuit 24 without inputting a voltage for Vt control from the outside. can.

[0068] The circuit 24 is a discharge type dynamic logic circuit, and the node Y3 is a dynamic The signals PREP and PREN function as clock signals for the circuit 24. The period when the signal PREP is "H" is the discharge period, and the period when the signal PREP is "L" is the discharge period. During the discharge period, the voltage VSSM is input to node Y3. During the evaluation period, the signal WE goes high, discharging the node Y3. The logic of node Y3 is the same as that of node A3. In other words, when a signal WE of "H" is input, Then, the circuit 24 inputs the data DIN to the write bit line WBL.

[0069] <Read circuit 125> The read circuit 125 is provided with a circuit 25 (see FIG. 5) for each read bit line RBL. The circuit 25 includes transistors M51 to M54, nodes A4 and Y4. is an input node and is electrically connected to the read bit line RBL. Node Y4 is an output node. The node Y is an output node that outputs the data RO read from the read bit line RBL. 4 is electrically connected to a circuit 26 provided in the output circuit 126. Thus, the circuit 26 functions as an output buffer circuit.

[0070] Transistors M52, M51, and M53 are electrically connected in series between the VSSM and VDDM lines. The connection between the drain of transistor M51 and the source of transistor M53 The next node is node Y4. The gate of transistor M51 is electrically connected to node A4. The signals CRE and CREB are input to the gates of the transistors M52 and M53, respectively. The signals CRE and CREB are inverses of each other. The back gates of the transistors are electrically connected to the power supply lines for the voltages BGR1 and BGR2. In the station M53, the back gate and the gate are electrically connected.

[0071] In the transistor M54, the gate and the back gate are electrically connected. A signal RST is input to the transistor M54. The transistor M54 connects the node A4 to the power supply line for the voltage VCH. Transistor M54 acts as a reset circuit to initialize the voltage at node A4. The signal RST controls the initialization of node A4. Transistor M54 is turned on. When this occurs, node A4 is fixed to the voltage VCH. The initialization operation of node A4 is performed This discharges the read bit line RBL and sets the voltage of the read bit line RBL to "L". Therefore, the voltage VCH is lower than the voltage VDDM and is a low voltage (for example, the voltage VSS (voltage equal to M).

[0072] The circuit 25 is a charge-type dynamic logic circuit. The node Y4 is a dynamic The signals CRE and CREB function as clock signals for the circuit 25. The period when EB is "H" is the charge period, and the period when signal CREB is "L" is the evaluation period. During the charge period, the voltage VDDM is input to node Y4. Transistor M53 is off and transistor M52 is on, so the voltage at node Y4 The voltage at node A4 changes depending on the voltage at node A4. When "Y4" is "L" / "H", the voltage of node Y4 is "L" / "H".

[0073] The back gate voltage of transistors M51 and M52 can be adjusted to adjust the read speed. This is to improve the back gate voltage of at least the transistor M51. For example, in order to improve the on-current characteristics of the transistor M51, it is preferable to set the voltage B It is preferable that GR1 is equal to or higher than the voltage VSSM. By shifting to the evaluation period, the voltage of node Y4 becomes a voltage at which data can be determined. For example, the voltage is the same as the "H" voltage supplied as the signal CRE, By using the same voltage as the voltage VDDM for the voltage BGR1, the voltage used in the circuit 25 can be Don't increase the number.

[0074] For example, the voltage BGR2 can be the same as the voltage BGR1. By improving the on-current characteristics of both M51 and M52, the voltage at node Y4 can be used to determine the data. This further reduces the time it takes to reach the voltage that is possible.

[0075] <Output circuit 126> The output circuit 126 has 32 circuits 26. The circuits 26 output data from the data RO to the data DO. As shown in FIG. 6A, the circuit 26 generates and temporarily stores data DO. 5, A6, B5, B6, Y5, transistors M60 to M67, and capacitance elements CO1 and CO2. The circuit 26 supplies the voltages VDDM, VDDM1 to VDDM3, VSSM, VSSM1 to VSSM3, VBGINV, VBGO, VBGDD, VBGSS, signal SGD1, SGD 2 is input to the node A5. The node A5 is electrically connected to the node Y4 of the circuit 25. For example, The voltage VDDM3 is a high power supply voltage, and the voltage VDDM1 is a voltage higher than the voltage VDDM2. The voltages VSSM1 to VSSM3 are low power supply voltages. In this embodiment, the voltage VDDM 3.3V, voltage VDDM1 to 4.0V, voltage VDDM2 to 1.0V, voltage VDDM3 to 5.0V. Also, voltage VSSM, voltage VSSM1, voltage VSSM2, and voltage V Set SSM3 to 0V.

[0076] The transistors M60 and M61 form an inverter circuit 26A. The transistor M61 inverts the data RO to generate the data ROB. The transistor M6 has a connection structure, and the back gate is supplied with the voltage VBGINV. At 0, the gate and back gate of the transistor M60 are electrically connected. The output is electrically connected to node A5, and data RO is input to node B5. This is the output node of the data circuit 26A.

[0077] For example, the voltage VBGINV shifts the Vt of the transistor M61 to the negative voltage side. This can improve the operating speed of the inverter circuit 26A. A lock gate may be electrically connected to the gate to dynamically vary Vt.

[0078] The capacitance elements CO1 and CO2 and the transistors M62 to M67 constitute an output buffer circuit 26B. The output buffer circuit 26B is a differential input, capacitively coupled buffer circuit. The two terminals of the capacitor CO1 are electrically connected to the nodes A5 and A6, respectively. The two terminals of the transistor A2 are electrically connected to nodes B5 and B6, respectively. are electrically connected to the gates of the transistors M66 and M67, respectively. The connection node between the source of M66 and the drain of transistor M67 is node Y5.

[0079] The gates of the transistors M62 and M64 are supplied with voltages VGS1 and VGS2, respectively. The gates of the transistors M63 and M65 are supplied with signals SGD1 and SGD2. The back gates of the transistors M62 to M65 are supplied with the voltage VBGO. The back gates of 67 are supplied with voltages VBGDD and VBGSS, respectively.

[0080] Transistors M62 and M64 are current sources for inputting bias currents to nodes A6 and B6. The transistors M63 and M65 function as reset terminals that initialize the nodes A6 and B6. The transistors M66 and M67 act as a gate circuit. A buffer circuit is formed that outputs a signal corresponding to the voltage at node Y6 from node Y5.

[0081] The back gate voltage of transistors M62 to M67 can be adjusted, This can improve the driving capability of the driver circuit 26B and achieve stable operation. The voltage VBGO is input to the back gates of the transistors M62 to M65. Alternatively, a different voltage may be input to the back gate of the transistors M62 to M67. In some transistors, the gate and the back gate may be electrically connected.

[0082] An example of the operation of the circuit 26 will be described with reference to FIG. 6B. First, the circuit 26 is initialized. Specifically, an initial voltage is input to nodes A6 and B6. H” to turn on transistors M63 and M65. For example, the signal SGD1 is set to 7.0 V, signal SGD2 is set to 3.3V. Then, voltage VDDM1 (4.0V) is applied to node A6. is supplied, and the voltage VDDM2 (1.0 V) is input to the node B6. The voltage VDDM1 is set to ON to turn on transistor M66 and OFF to turn off transistor M67. , VDDM2, VBGDD, VBGSS, etc. are set.

[0083] In the example of FIG. 6B, the signals RST, CREB, and The signal CRE of "L" is input to the circuit 25, and the data RO of "H" is input to the node A5. Therefore, the voltage VSSM3 is input to the node B5.

[0084] When the signals SGD1 and SGD2 are set to "L" (voltage VSSM), the transistors M63 and M6 5 turns off, and the initialization of nodes A6 and B6 is completed. After the initialization operation, nodes A5 and Since there is capacitive coupling between nodes A6 and B5 and B6, The voltages at nodes A6 and B6 change depending on the voltages at nodes A5 and B5. When the data RO changes from "H" to "L", the voltage at node A6 drops and the transistor Transistor M66 is turned off, and transistor M60 is turned off, causing the voltage at node B5 to Then, the voltage at node B6 also rises, turning on transistor M67 and The node Y5 outputs "L" (voltage VSSM) as data DO. When "H" is input as data RO, node Y5 outputs "H" as data DO. .

[0085] When the voltage VDDM1 is the same as the voltage VDDM, "H" is input to the node A5. Then, the voltage that is lower than the voltage VDDM by the Vt of transistor M66 is output as data DO. By making the voltage VDDM1 higher than the voltage VDDM, the node A5 is set to "H". This can suppress the voltage drop of the data DO when the data is input. By isolating the node A6 with the capacitance element CO1 and performing the above initialization operation, The data DO output can be switched by charging and discharging the node A5. By isolating the node B6 with the capacitance element CO2 and performing the above initialization operation, actual operation At this time, the output of data DO can be switched by charging and discharging node B5. Since there is no need to charge or discharge node A6 and node B6, the operating speed of circuit 26 can be improved. be.

[0086] <<Example of operation>> 7 and 8 are timing charts illustrating an example of the operation of the storage device 100. 8, tWCY is the write cycle time, tWPW is the write pulse width, tRCY is the read cycle time, and tRAC is the read access time. (a1) , (a2), (a3) ​​are addresses, and ( / a1), ( / a2), ( / a3) are addresses. ), (a2), (a3). Data RO[31:0] is the inverted address of the read circuit. 125 is the data read from the memory cell array 110. Data (a1) is the address The data (a1) is the data to be written to the memory cell 11 at address (a2). This is the data read from the memory cell 11 in (a2).

[0087] <Initialization operation, standby state> The initialization operation is performed to set the storage device 100 in a state where write and read operations are possible. This is an operation that is executed, for example, after power is turned on. Specifically, the read bit line RBL, An initial voltage is input to nodes A6 and B6 of the circuit 26, respectively.

[0088] As shown in Figure 7, the signals PREP, CREB, SGD1, and SGD2 become "H". WE and RE are at "L". In the circuit 25, the voltage VCH is input to the read bit line RBL. In circuit 25, transistor M53 is turned on and node Y4 is pulled to voltage VD Therefore, the read circuit 125 reads data RO[31:0] as ff The output is ffffff (hexadecimal). The nodes A6 and B6 of the circuit 26 are connected to the voltage VDDM. When the signals SGD1 and SGD2 become "L", the memory device 10 0 is standby mode.

[0089] <Write operation> An example of a write operation will be described with reference to FIG. 8. The signals WE and RE are both set to "H" ("1"). "), when it is "L" ("0"), the storage device 100 performs a write operation.

[0090] During the period T1, the write word line WWL and the write bit line WBL are discharged. The signal PREP is at "H". The write word line WWL <0> ~WWL <31> ni row The decoder 122 inputs the voltage VSSM to the write bit line WBL <0> ~WBL <31> The voltage VSSM is applied to the row by the write circuit 124. The decoder 122 reads the word line RWL <0> ~RWL <31> Fix to voltage VSS .

[0091] During the period T2, data is written to the memory cell 11 designated by the address signal RA[4:0]. The signals PREP and PREN are "L" and "H". Write bit line WBL <0> ~WBL <31> Data DIN[0]~DIN

[31] is The row decoder 122 is activated and the address signals RA[4: 0], RAB[4:0] are decoded. For example, if the address (a1) is "00001", If so, the row decoder 122 connects the write word line WWL <1> A high selection signal is output to Therefore, the memory cells 11<1,0> to 11<1,31> are in a selected state. The signals M1<1,0> to M1<1,31> are turned on, and the data DIN[0] to DIN

[0031] are written to the nodes SN<1,0> to SN<1,31>, respectively. When PREN goes to "H" and then "L", one cycle of the write operation is completed and all memories are written. Resistor 11 is deselected.

[0092] <Read operation> An example of a read operation will be described with reference to FIG. 8. The signals WE and RE are "L" and "H". If so, the storage device 100 performs a read operation.

[0093] In the period T3, the read bit line RBL is reset and the read word line RWL is discharged. The signals PREP, RST, CRE, and CREB are set to "H" and "H" respectively. , "L", "H". Read word line RWL <0> ~RWL <31> Ha row decoder 1 22 is fixed to the voltage VSSM. <0> ~RBL <31> is fixed to voltage VCH by read circuit 125, and the output node of circuit 25 (node ​​Y4 ) is fixed to the voltage VDDM. <0> ~WWL <31> is clamped to voltage VSS by row decoder 122 during a read operation.

[0094] During the period T4, data (a2) is read from the memory cell array 110. P and PREN are "L" and "H". The row decoder 122 is activated and the address Decode the signals RA[4:0] and RAB[4:0]. For example, if the address (a2) is " 00010", the row decoder 122 reads the read word line RWL <2> Select "H" A select signal is output to select the memory cells 11<2,0> to 11<2,31>. The transistors M3<2,0> to M3<2,31> are turned on, and the memory cells 11< The data held in 2,0> to 11<2,31> is transmitted to the read bit line RBL <0> ~RBL<3 1>. The read circuit 125 writes data to the read bit line RBL <0> ~RB L <31> The data is read out and output to the output circuit 126 as data RO[31:0]. More specifically, the voltage at node Y4 of circuit 25 varies depending on the voltage at read bit line RBL. Depending on the voltage at node Y4, the circuit 26 outputs "0" ("L") as data DO. ”) or “1” (“H”). The read access time tRAC is determined by the signals CRE and After PREN and PREN transition from "L" to "H", the voltage at node Y4 This is the time it takes to determine whether the value is "0" or "1".

[0095] An example of the operation of the memory cell 11 and the circuit 25 will be described with reference to FIGS. 5, 8, and 9. 10A and 10B show schematic output waveforms of the read bit line RBL and node Y4 during a read operation.

[0096] When the signal RST goes high, the transistor M54 turns on, and the read bit line RBL Since the parasitic capacitance of the read bit line RBL is relatively large, the read bit line RB Inputting a constant voltage to L by discharging rather than charging is effective in improving the readout speed. When the signal RST goes low, the transistor M54 turns off and the read bit The line RBL is electrically floating. While the signal RST is at "H", the transistor M53 is on, data "1" ("H") is written to node Y4.

[0097] Next, the signal RST is set to "L" and the voltage of the read word line RWL is set to "H". If data "0" is written to node SN, transistor M3 is turned on. Since the node M2 ​​is off, the voltages of the read bit line RBL and node Y4 do not change. That is, data RO is maintained at "1" ("H").

[0098] On the other hand, if data "1" is written to node SN, transistor M2 is turned on. Therefore, the drain current of transistor M2 causes the read bit line RBL to The node SN is capacitively coupled to the read bit line RBL, so the read bit As the voltage on line RBL rises, the voltage on node SN also rises due to the bootstrap effect. Therefore, the drain current of transistor M2 increases, and the read bit line RBL is charged. Eventually, when transistor M52 turns on, node Y4 is discharged and the data The data RO becomes "0" ("L").

[0099] It should be noted that the data RO is the inverted data of the data held in the memory cell 11. Therefore, the data DO is also inverted data. In order to make the logic the same, change the circuit configuration of the circuit 26 so that the data RO can be inverted. For example, the node B5 may be electrically connected to the capacitance element CO1, and the node A5 may be electrically connected to the capacitance element CO2. Electrically connect to element CO2.

[0100] When the capacitance element CS1 capacitively couples the node SN and the VSSM line, The voltage of the bit line RBL changes as shown by the dotted line. In this case, the bootstrap effect Since the read bit line RBL is not selected, the charging speed of the read word line RWL is slow. During this period, the read bit line RBL may not be boosted to a voltage that allows data to be determined. In other words, the read access time tRAC can be shortened by using the bootstrap effect. This allows for reduction in the number of read errors.

[0101] To improve the read speed, the Vt of the transistor M2 is shifted to the negative voltage side by the voltage Vbg2. In this case, it is preferable to soften the non-selected memory cell 11 to improve the on-current characteristics. The increase in leakage current from the unselected memory cell 11 to the read bit line RBL becomes a problem. These leakage currents not only shorten the data retention time but also cause data read errors. Therefore, the transistor M3 prioritizes the off-current characteristics over the on-current characteristics, and the voltage Vbg3 is set lower than voltage Vbg2.

[0102] In order to retain data for a long time, it is preferable that the off-state current of the transistor M1 be low. Therefore, it is preferable that the voltage Vbg1 is equal to or lower than the voltage Vbg3.

[0103] Since the memory cell 11 is a 3T1C type, the Vt drop in the voltage of the read bit line RBL is apparent. However, the bootstrap effect prevents the voltage of the read bit line RBL from dropping below Vt. That is, it is possible to provide a 3T1C type memory cell 11 with a bootstrap effect. By applying a gain cell, high data retention characteristics and high operating speed are achieved. The device 100 can further include a charge-type dynamic load in the readout circuit 125. The use of a logic circuit is effective in shortening the read access time tRAC.

[0104] (Modification of memory cell) FIG. 10 shows another example of the configuration of a memory cell having the bootstrap effect. The memory cell 12 is a modified example of the memory cell 11, and includes transistors M5 to M7 and a capacitance element C The transistors M5 to M7 are write transistors. The back gate of the transistors M5 to M7 is The first terminal of the capacitance element CS5 is electrically connected to the wirings BGC1 to BGC3. The two terminals are electrically connected to nodes SN and N6. The node N6 is connected to the transistor M6. This is the connection node with the transistor M7. The voltages Vbg1 to Vbg3 are the same as those of the memory cell 11. It is set as follows.

[0105] Memory cell 12 operates in the same manner as memory cell 11. Read word line RWL is selected When node SN holds a "1", transistor M7 turns on. 6 is charged by the drain current of transistor M6. Therefore, the bootstrap effect As a result, the voltage at node SN also rises in accordance with the rise in the voltage at node N6. The voltage rise of the read bit line RBL is accelerated.

[0106] The memory device 100 does not use p-channel transistors. The number of masks can be reduced. This reduces the manufacturing cost. The complementary circuit must be designed to prevent latch-up. However, the memory device 100 is free from latch-up, and therefore has a high degree of freedom in layout. This allows patterns to be arranged at high density.

[0107] Since a single conductivity type dynamic logic circuit is used, the transistors of the peripheral circuit 120 The reduction in the number of transistors in the peripheral circuit 120 contributes to the miniaturization of the memory device 100. This is effective for reducing power consumption. Table 1 shows the number of transistors in the peripheral circuit 120 and The number of transistors in the peripheral circuits of the OS storage device 120 is compared. The number of transistors per two bit lines is the number of transistors in the read circuit 125, The peripheral circuit of Non-Patent Document 2 does not include the transistor of the output circuit 126. The number of transistors in Non-Patent Document 2 is 122, a write circuit 124, and a CMOS static logic corresponding to a read circuit 125. This is an estimate of the number of transistors in the circuit.

[0108] [Table 1]

[0109] As described above, this embodiment provides high operating speed, high rewrite endurance, and high data retention characteristics. It is possible to provide an OS storage device that realizes low power consumption and a reduced number of transistors. In Example 2 described later, the specific performance of the OS storage device of this embodiment will be explained. do.

[0110] Second Embodiment The manufacturing technology of OS transistors is compatible with CMOS manufacturing technology, and OS transistors are used The single conductivity type memory device can be stacked on a CMOS logic circuit. In this form, there are CMOS circuits using Si transistors and OS transistors. A semiconductor device having a single conductivity type circuit formed thereon will be described.

[0111] When the memory device of the first embodiment is configured using only OS transistors, it is relatively small (e.g., For example, it is suitable for storage devices (128 bits to 1 Mbit).

[0112] For example, the embedded storage device 2 of the application processor (AP) 200 shown in FIG. The storage device of the first embodiment is used in the AP200. The AP200 is a system-on-chip. The chips that make up the AP200 are C It has a stacked structure of a MOS transistor layer 221 and an OS transistor layer 222. CMOS The transistor layer 221 includes various functional circuits that configure the AP 200, such as the CPU 21 0, a bus 211, peripheral circuits 213 and 215, and an input / output interface circuit 217 are provided. The peripheral circuits 213 and 215 include a power supply circuit, a communication circuit, an image processing circuit, an audio processing circuit, and the like. A circuit or the like is provided.

[0113] A plurality of embedded memory devices 205 are provided in the OS transistor layer 222. The number of built-in storage devices 205 may be one. Data is exchanged with the CPU 210 via the bus 211. 05 stores, for example, the setting data of the AP 200. In such an application, an external E Although an EPROM chip can be used, using embedded storage 205 This is effective in reducing the cost, size, and power consumption of the AP200.

[0114] A plurality of OS transistor layers 222 can be stacked on the CMOS transistor layer 221. For example, if two OS transistor layers 222 are provided, the embedded memory device A peripheral circuit 205 is provided on the upper layer, and a memory cell array is provided on the upper layer. A memory cell array is provided in the upper layer.

[0115] Of course, the semiconductor device to which the storage device of the first embodiment can be applied is an application processor. Not limited to processors, but also microcontroller units (MCUs), CPUs, GPUs, and FPGAs The memory device of the first embodiment can be provided in various semiconductor devices such as GA, imaging devices, and display devices. This can be done.

[0116] For example, the processor 230 shown in FIG. 12A has multiple embedded memory devices 235. The built-in storage device 235 can be the storage device of the first embodiment. The device 230 includes a bus interface (I / F) 231, a plurality of processing engines (PE, P The processing engine 233 is further included. , data transmission between the arithmetic processing unit 230 and the external storage device 239 is performed. For example, DRAM, flash memory, SRAM, etc. are used for 39.

[0117] The chip structure of the processor 230 is a stacked structure similar to that of the AP 200. The device 235 is provided in the OS transistor layer, and the bus I / F 231 and the PE 233 are CMOS The PE233 is a CMOS logic device that uses Si transistors. As shown in FIG. 12B, the built-in memory device 235 The embedded memory device 235 includes a memory cell array 236, a peripheral The memory cell array 236 and the peripheral circuit 237 are made of OS transistors. The embedded memory device 235 has a small number of transistors, so it occupies a small area. The control circuit 224 shown in FIG. The control circuit 224 is configured with a CMOS logic circuit. 235 control signal and control of data transmission between the PE 233 and the bus I / F 231. To control.

[0118] In order to perform parallel processing, multiple PEs 233 are arranged in an array. To efficiently perform parallel processing, low power consumption, high operating speed, and high rewrite endurance are required. Embedded storage is needed. Embedded storage 235 meets this need. By providing an embedded storage device 235 in the vicinity of the PE 233, it is possible to This reduces the time and power required for data transmission and allows the PE233 to operate efficiently. Since it is possible to provide a high-performance arithmetic processing device 230 with low power consumption, The processing device 230 is suitable for scientific and technical calculations, machine learning (e.g., deep learning), etc., and is, for example, , can be used as an accelerator for machine learning.

[0119] As shown in FIG. 13, a processor chip 7 incorporating the storage device 100 of the first embodiment is The 010 can be incorporated into a variety of electronic devices.

[0120] The robot 7100 is equipped with an illuminance sensor, a microphone, a camera, a speaker, a display, and Various sensors (infrared sensors, ultrasonic sensors, acceleration sensors, piezo sensors, optical sensors, The processor chip 7010 is equipped with a sensor, a moving mechanism, etc. Control peripheral devices.

[0121] The microphone has the function of detecting audio signals such as the user's voice and environmental sounds. The speaker also has the function of emitting audio signals such as voice and warning sounds. The robot 7100 analyzes the audio signal input through the microphone and The robot 7100 can emit audio signals from a speaker. , and a speaker can be used to communicate with the user.

[0122] The camera has a function of capturing an image of the surroundings of the robot 7100. The robot 7100 has the function of moving using a moving mechanism. It can capture images of the surroundings, analyze the images, and detect whether there are any obstacles when moving. Cut.

[0123] The flying object 7120 has a propeller, a camera, a battery, etc., and is an autonomous flying object. The processor chip 7010 controls these peripheral devices. The SAPchip 7010 analyzes image data captured by the camera to determine whether there are any obstacles when moving. It is possible to detect such things.

[0124] The cleaning robot 7140 has a display on the top surface and multiple cameras on the sides. The cleaning robot has a brush, operation buttons, various sensors, etc. The cleaning robot 7140 is equipped with tires, a suction nozzle, etc. The cleaning robot 7140 is self-propelled. The dust can be detected and sucked up from the suction port provided on the bottom surface. The processor chip 7010 analyzes the image captured by the camera and detects obstacles such as walls, furniture, or steps. In addition, image analysis can be used to detect wires or other objects that may be tangled in the brushes. If it detects an object that is likely to get stuck, it can stop the brush from rotating.

[0125] The car 7160 has an engine, tires, brakes, a steering system, a camera, etc. For example, the processor chip 7010 may provide navigation information, speed, engine status, gear Based on data such as the driving status and frequency of brake use, the driving status of the car 7160 is optimized. Control is performed to optimize the process.

[0126] The processor chip 7010 is used in a television receiver (TV) 7200, a smartphone, 7210, PC (personal computer) 7220, 7230, game console 7240, 7 260, etc. For example, the processor chip built in the TV device 7200 The chip 7010 can function as an image engine. For example, The 7010 performs image processing such as noise reduction and resolution up-conversion. The smartphone 7210 is an example of a mobile information terminal. The processor chip 7010 includes a display unit, a camera, a speaker, various sensors, and a display unit. These peripheral devices are controlled by

[0127] The PC7220 and 7230 are examples of notebook PCs and desktop PCs, respectively. 30, a keyboard 7232 and a monitor device 7233 can be connected wirelessly or by wire. The game console 7240 is an example of a portable game console. The game console 7260 is a stationary game console. The game machine 7260 is an example of a game machine. The controller 7262 can incorporate a processor chip 7010. It is also possible.

[0128] Third Embodiment 14A and 14B, a configuration example of an OS transistor will be described. The left side of FIG. 4B shows a cross-sectional view of the OS transistor in the channel length direction, and the right side shows the OS transistor. 1 shows a cross-sectional view of the capacitor in the channel width direction.

[0129] The OS transistor 5001 shown in FIG. 14A is formed on an insulating surface. The OS transistor 5001 is formed on the insulating layer 5021. The OS transistor 5001 is covered with insulating layers 5022 to 5031 and a metal oxide layer 5011 to 5013 and conductive layers 5050 to 5054.

[0130] The insulating layer, metal oxide layer, conductive layer, etc. shown in the figure may be a single layer or a laminated layer. Sputtering method, molecular beam epitaxy (MBE method), pulsed laser ablation method (PLA method), chemical vapor deposition (CVD method), atomic layer deposition (ALD method), etc. The CVD method can be a plasma CVD method, a thermal CVD method, an organic metal CVD method, etc. Examples include the CVD method.

[0131] The metal oxide layers 5011 to 5013 are collectively referred to as a metal oxide layer 5010. As shown, the metal oxide layer 5010 is made of metal oxide layer 5011, metal oxide layer 5012, and metal The OS transistor 5001 has a portion where an oxide layer 5013 is stacked in this order. In this state, the channel is formed primarily in the metal oxide layer 5012.

[0132] The gate electrode of the OS transistor 5001 is formed by a conductive layer 5050, and the source electrode or A pair of electrodes functioning as drain electrodes are composed of conductive layers 5051 and 5052. The metal oxide layer 5010 and the conductive layers 5050 to 5052 are insulating layers that function as barrier layers. The back gate electrode is covered with a conductive layer 5051. The OS transistor 5001 can be configured without a back gate electrode. The same applies to the OS transistor 5003 described later. The gate insulating layer is made up of insulating layer 5027, and the gate insulating layer on the back gate side is made up of insulating layer 5 It is composed of layers of 024 to 5026.

[0133] 14A shows an example in which the metal oxide layer 5010 has a three-layer structure, but is not limited to this. The oxide layer 5010 is, for example, a metal oxide layer 5011 or a metal oxide layer 5013. It can have a two-layer structure, or it can be composed of one of the metal oxide layers 5011 to 5013. Alternatively, the metal oxide layer 5010 may be made up of four or more metal oxide layers.

[0134] The conductive material used for the conductive layers 5050 to 5054 is doped with impurity elements such as phosphorus. Semiconductors such as polycrystalline silicon, silicides such as nickel silicide, molybdenum Titanium, Tantalum, Tungsten, Aluminum, Copper, Chromium, Neodymium, Scandium Metals such as tantalum nitride, titanium nitride, etc., or metal nitrides containing the above-mentioned metals , molybdenum nitride, tungsten nitride, etc. Indium tin oxide, tungsten oxide, etc. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, oxide Indium oxide containing titanium, indium tin oxide containing titanium oxide, indium zinc Conductive materials such as indium tin oxide and silicon oxide doped indium tin oxide can be used. do.

[0135] For example, the conductive layer 5053 is a conductive layer (for example, tantalum nitride) having a barrier property against hydrogen. The conductive layer 5054 is a conductive layer (for example, a tank) having a higher conductivity than the conductive layer 5053. With such a structure, the conductive layer 5053 and the conductive The stacked electrode layer 5054 functions as wiring and also suppresses the diffusion of hydrogen into the metal oxide layer 5010. It has the function of

[0136] The insulating materials used for the insulating layers 5021 to 5031 include aluminum nitride, aluminum oxide, and the like. Aluminum, aluminum oxide nitride, aluminum oxide nitride, magnesium oxide, silicon nitride , silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide Yttrium oxide, Zirconium oxide, Lanthanum oxide, Neodymium oxide, Hafnium oxide The insulating layers 5021 to 5031 are made of aluminum, tantalum oxide, aluminum silicate, etc. The insulating layers 5021 to 5031 are made of a single layer or a laminate of these insulating materials. The layers may include multiple insulating materials.

[0137] In this specification, an oxynitride is a compound in which the oxygen content is higher than the nitrogen content, and An oxide is a compound that contains more nitrogen than oxygen.

[0138] In the OS transistor 5001, an insulating layer (hereinafter referred to as It is preferable that the metal oxide layer 5010 is surrounded by a barrier layer (under the barrier layer). With this structure, oxygen is released from the metal oxide layer 5010, and the metal Since the penetration of hydrogen into the oxide layer 5010 can be suppressed, the OS transistor 5001 For example, the insulating layer 5031 can function as a barrier layer, At least one of the insulating layers 5021, 5022, and 5024 may function as a barrier layer. The barrier layer is made of aluminum oxide, aluminum oxynitride, gallium oxide, or gallium oxynitride. Sodium, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride It can be made of materials such as silicon or silicon nitride.

[0139] The OS transistor 5003 shown in FIG. 14B is a modification of the OS transistor 5001. The main difference is the structure of the gate electrode. A metal oxide layer 5013, an insulating layer 5027, and a conductive layer 5050 are provided. The gate electrode is formed in a self-aligned manner by utilizing the opening. The gate electrode width can be controlled by the thickness, which allows fabrication of OS transistors with short channel lengths. Furthermore, the gate electrode (5050) is connected to the semiconductor substrate via the gate insulating layer (5027). Since there is no overlapping area with the source electrode and the drain electrode (5051, 5052), The parasitic capacitance between the gate and source and between the gate and drain is reduced, resulting in improved frequency characteristics. It will be improved. [Example]

[0140] In this embodiment, an OS dynamic logic circuit will be described.

[0141] A four-stage shift register 180 was fabricated using a 60 nm OS transistor process. As shown in FIG. 15A, the four-stage shift register 180 includes shift registers 181_1 to 181_1. _4, and clock signals φ1 to φ4 and voltages VDDD and VSSS are input. The register 181_1 is an OS dynamic logic circuit, and the transistors M81 to M86 , nodes IN, Y8, and Y9. Nodes Y8 and Y9 are dynamic nodes. The gate of the transistor M83 is the input node, and the node Y9 is the output node. Y9 is electrically connected to the input node of the shift register 181_2. The reference numeral 81 denotes an OS transistor, and the channel forming regions of the transistors M81 to M86 are The shift registers 181_2 to 181_ are made of a crystalline In-Ga-Zn oxide layer. 4 has the same circuit configuration as the shift register 181_1.

[0142] 15B shows the measurement results of the operating waveform of the four-stage shift register 180. DDD is 0V and 3.3V. The "L" and "H" of clock signals φ1 to φ4 are 0V and 5. 15B, signal IN is a pulse signal input to node IN, The signals OUT1 to OUT4 are output signals from the shift registers 181_1 to 181_4. The signal IN is sequentially shifted by the shift registers 181_1 to 181_3. The register 181_3 outputs the shifted pulse signal, and the clock signal φ4 falls. At this time, the input of clock signals φ1 to φ4 and voltage VDDD is stopped. After 1 second, the clock signals When the signals φ1 to φ4 and the voltage VDDD are input again, the shift register 181_4 In other words, after power gating, the four-stage shift register 180 operates normally. This is because the shift registers 181_1 to 181_ This is because the voltages at nodes Y8 and Y9 of 4 are maintained.

[0143] Therefore, according to this embodiment, a dynamic logic circuit using OS transistors can be Power gating is possible without providing a circuit to maintain the voltage of the dynamic node. It has been shown to be possible. [Example]

[0144] In this example, the design, manufacture, performance, etc. of the storage device 100 according to the first embodiment will be described.

[0145] <Operating speed> For memory cells 11 and 19, the read access of data "1" was performed by simulation. The W / L of the transistors M1 to M3 was calculated. The channel width / channel length is 60 nm / 60 nm. The capacitance of the capacitor CS1 is 1 The back gate voltages (Vbg1 to Vbg3) of transistors M1 to M3 are , -5V, 8V, 2V, and the voltages VSSM and VDDM are 0V and 3.3V. The process parameters are typical values ​​and the temperature is room temperature (RT). is.

[0146] The memory cell 19 is a comparative example, and the first and second terminals of the capacitance element CS1 are connected to the nodes SN and SN. It is electrically connected to the VSSM line. Other than this, it has the same configuration as the memory cell 11. Even if the read word line RWL is in a selected state, the memory cell 19 does not have a bootstrap effect. On the other hand, the bootstrap effect occurs in the memory cell 11, so the memory The read access time tRAC of cell 11 is reduced by 33%. Boosting the node SN by the boost effect is very effective in improving the read speed.

[0147] The memory device 100 was fabricated using a 60 nm OS transistor process. The channel formation region of the transistor was formed from a crystalline In-Ga-Zn oxide layer. 17B is a Schmoo plot (VDDM / VH vs. t WPW), (VDDM / VH vs. tRAC), respectively. The voltage VH is the control signal ( The voltage of "H" of the transistors M1 to M2 of the memory cell 11 is The back gate voltages of M3 are −7 V, 5 V, and 0 V. Transistor M51 in circuit 25 The back gate voltage of M52 is 5V. The voltage VDDM / VH is 3.3V / 5.0V. The pulse width tWPW and read access time tRAC are 20 ns and 45 ns, respectively. In other words, the write / read time can be achieved at 20ns / 45ns, and The output energy achieved was 97.9pJ / 58.6pJ.

[0148] <Rewrite durability·1> Using the test circuit 15, which is a 2T1C gain cell, the A write / read (rewrite) cycle test was performed. As shown in Figure 18A, the test circuit 15 denotes transistors M11 and M12, a capacitance element CS11, a node SN, and a write word line WWL, read word line RWL, write bit line WBL, read bit line RBL, wiring P L. Transistor M11 is the write transistor and transistor M12 is the read transistor. The transistors M11 and M12 are OS transistors with back gates. The channel forming region is formed from a crystalline In-Ga-Zn oxide layer. The W / L of transistors M11 and M12 is 500nm / 500nm and 60nm / 60nm. be.

[0149] In the write / read cycle test, the back gate of transistor M11 is fixed at -7V. The back gate of transistor M12 is electrically floating. A voltage of 1.8V is input to RBL and 0V is input to PL. The pulse widths tWPW on the write word line WWL are 10 ns and 100 ns, respectively. The "H" / "L" of the write bit line WBL is 3.3V / 0V, and the "H" / "L" of the write bit line WBL is 1.8V. / 0V.

[0150] In the write cycle, data "1" or "0" is written alternately to node SN. The cumulative number of "1" (or "0") write cycles is 10 to the nth power (n is an integer between 0 and 14). ) a read cycle was executed. In the read cycle, first, data "1" or "0" is written to the node SN, and then the data read operation is repeated to M12 I PL -V RWL The characteristics were measured. PL is the current flowing through the wiring PL, and V RWL is the voltage of the read word line RWL. RWL The data "1" is read out. The cycle changes from -3.0V to 1.0V in steps of +0.05V, and data "0" is read. The voltage was changed from 0 V to 4.0 V in increments of +0.05 V during the cycle. When " / "0" is held at node SN, PL -V RWL The characteristic curve is shown. Using root extrapolation, the measured I PL -V RWL From the characteristic curve, the Vt of transistor M12 The calculation results are shown in Figure 18C. The difference in Vt when data "0" is held is 10 14 Approximately 2.5V after a write cycle Therefore, 10 14 Even after a write cycle, the two states are interchangeable with a sufficient margin. It is possible to distinguish between them.

[0151] The results of the write / read cycle test showed that the memory device 100 using the test circuit 15 was 10 14 It can withstand cycles, which means it has high rewrite endurance.

[0152] <Rewrite durability 2> Using the test circuit 16 shown in FIG. 19A, write / read (write) Test circuit 16 is a 2T1C gate similar to test circuit 15. The difference between test circuit 16 and test circuit 15 is that instead of transistor M12, The transistor M13 is a p-channel Si transistor (bulk transistor). Similar to the transistor M12, the transistor M13 is also a read transistor. It functions as a star.

[0153] In a write / read cycle test using the test circuit 16, the voltage of the transistor M11 The clock gate is fixed at -3V. The read bit line RBL is set to 0V, and the wiring PL is set to 1.2V. The voltage of V is input. The "H" / "L" of the write word line WWL is 2.5V / -0.8V. The "H" / "L" of the write bit line WBL is 1.2V / 0V.

[0154] As with the write / read cycle test using the test circuit 15, the device Data "1" or "0" was written alternately to node SN.

[0155] In addition, if the cumulative number of write cycles of data "1" (or "0") is 10 to the nth power (n is 0 or more), A read cycle was performed every time the number of bits reached 14 (an integer between 14 and 15). In the read cycle test, I PL Measure I PL From the value of Voltage of board SN V SN was calculated.

[0156] Figure 19B shows V SN The calculation results are shown below. 10 14 After the write cycle, data "1" V when holding SN is 0.63V, and V when data "0" is held SN teeth The V when data "1" is held is 0.01V. SN and data "0" is retained. V when SN The difference is about 0.62V. 14 Write cycle Even after the test, the two states can still be distinguished from each other.

[0157] The results of this write / read cycle test show that even at an ambient temperature of 85°C, the test circuit 16 The storage device 100 using 14 This allows for high rewrite endurance. means.

[0158] <Specifications> 20A shows a micrograph of the memory device 100 using the test circuit 15. In A, the output circuit 126 is not shown.

[0159] FIG. 20B shows the specifications of the storage device 100. At room temperature, the storage device 100 is in standby mode. The static power (standby power) of the The active power for low-power operation is 97.9 μW / MHz and 258.6 μW / MHz. Assuming the load capacitance of circuit 25 is 10 fF, the active power is 123.6 When the memory capacity of the memory cell array 110 is expanded to 1 Mbit, In this case, the active power is 133. The power consumption of the storage device 100 is estimated to be 7 μW / MHz. .

[0160] <Summary> A 1k-bit OS memory device was fabricated using a 60nm OS transistor process. The write time is 20ns, the read time is 45ns, and the 14 Cycle-resistant This means high rewrite endurance. The OS storage device we created has high operating speed and low power consumption. It was confirmed that the performance required for embedded storage devices can be achieved. [Explanation of symbols]

[0161] 11, 12, 19: Memory cells, 15, 16: Test circuits, 20, 22, 24, 25 26: Circuit; 26A: Inverter circuit; 26B: Output buffer circuit; 100: memory device, 110: memory cell array, 120: peripheral circuit, 122: row data coder, 124: write circuit, 125: read circuit, 126: output circuit, 130 : decoder, 132: word line driver, 180: 4-stage shift register, 181_1, 181_2, 181_3, 181_4: Soft register, 200: Application Processor (AP), 205: Embedded Storage Device, 210 : CPU, 211: bus, 213, 215: peripheral circuits, 217: input / output interface Interface circuit, 221: CMOS transistor layer, 222: OS transistor layer, 2 24: Control circuit, 230: Processing unit, 233: Processing engine (PE), 235 : Built-in memory device, 236: Memory cell array, 237: Peripheral circuit, 239: External part storage device, 5001, 5003: OS transistor, 5010, 5011, 5012, 5013: Metal oxide layer, 5021, 5022, 5023, 5024, 5025, 5026, 50 27, 5028, 5029, 5030, 5031: Insulating layer, 5050, 5051, 50 52, 5053, 5054: conductive layer, 7010: Processor chip, 7100: Robot, 7120: Flying object, 7140 : Cleaning robot, 7160: Automobile, 7200: Television receiver (TV) device, 7210: Smartphone, 7220: Personal computer (PC), 7230 : Personal computer (PC), 7232: Keyboard, 7233: Monitor device , 7240: Game console, 7260: Game console, 7262: Controller, A0, A1, A3, A4, A5, A6, B5, B6, N6, SN, X0, X1, Y1, Y 2, Y3, Y4, Y5: Node, CO1, CO2, CS1, CS5, CS11: Capacitive elements, M1, M2, M3, M5, M6, M7, M11, M12, M19, M20, M21, M2 3, M24, M25, M26, M27, M28, M41, M42, M43, M44, M5 1, M52, M53, M54, M60, M61, M62, M63, M64, M65, M6 6, M67, M81, M82, M83, M84, M85, M86: Transistors, BGL1, BGL2, BGL3, PL: Wiring, RBL: read bit line, RWL: read word line, WBL: write bit line, W WL: Write word line < / j> < / j> < / j>

Claims

[Claim 1] a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell; the memory cell has a retention node, first to third transistors, and a capacitance element; channel formation regions of the first to third transistors each include a metal oxide layer; the gates of the first to third transistors are electrically connected to the write word line, the retention node, and the read word line, respectively; one of a source and a drain of the first transistor is electrically connected to the write bit line, and the other is electrically connected to the retention node; the second transistor and the third transistor are electrically connected in series between the read bit line and the first wiring; a first terminal of the capacitance element electrically connected to the retention node; The second terminal of the capacitive element is electrically connected to the read bit line.

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