Imaging device and imaging apparatus

Abstract

SOLUTION: The image sensor includes first to third pixel blocks, a first substrate including a first signal conversion section 40 - 1, a second substrate including a first signal processing block 220 - 1, a second signal processing block 220 - 2 including a second signal conversion section 40 - 2, and a third signal processing block 220 - 3 including a third signal conversion section 40 - 3, and outputs a signal from a first pixel to the first signal conversion section, A first signal bonding unit 310 - 1 that bonds the first substrate and the second substrate, a second signal bonding unit 310 - 2 that outputs a signal from the second pixel to the second signal conversion unit and bonds the first substrate and the second substrate, and a third signal bonding unit 310 - 3 that outputs a signal from the third pixel to the third signal conversion unit and bonds the first substrate and the second substrate, in which the second pixel block is provided between the first pixel block and the third pixel block, An interval L1 between the first signal bonding part and the second signal bonding part is narrower than an interval L2 between the second signal bonding part and the third signal bonding part.EFFECT: To expand a dynamic range.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to an imaging element and an imaging device. This application claims priority based on Japanese Patent Application No. 2021-137590, filed on August 25, 2021, the contents of which are incorporated herein by reference. [Background technology]

[0002] BACKGROUND ART There is known an imaging device having a signal processing circuit that processes pixel signals from a pixel block made up of a plurality of pixels (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2017 / 018188 Summary of the Invention

[0004] An imaging element according to a first aspect of the present invention includes a first substrate having a first pixel block having a first pixel, a second pixel block having a second pixel, and a third pixel block having a third pixel, the first pixel block, the second pixel block, and the third pixel block being arranged side by side in a column direction; a second substrate having a first signal processing block having a first signal conversion unit that processes signals from the first pixels, a second signal processing block having a second signal conversion unit that processes signals from the second pixels, and a third signal processing block having a third signal conversion unit that processes signals from the third pixels; The pixel block is provided with a first signal connecting portion that outputs a signal from a pixel to the first signal conversion portion and connects the first substrate and the second substrate, a second signal connecting portion that outputs a signal from the second pixel to the second signal conversion portion and connects the first substrate and the second substrate, and a third signal connecting portion that outputs a signal from the third pixel to the third signal conversion portion and connects the first substrate and the second substrate, wherein the second pixel block is provided between the first pixel block and the third pixel block, and the distance between the first signal connecting portion and the second signal connecting portion is narrower than the distance between the second signal connecting portion and the third signal connecting portion.

[0005] An imaging device according to a second aspect of the present invention includes the imaging element according to the first aspect. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is an exploded perspective view showing an overview of an image pickup element 400 according to an embodiment of the present invention. [Figure 2] FIG. 2 is a plan view showing an example of a specific configuration of a pixel section 110. [Figure 3] FIG. 2 is a diagram showing an example of a circuit configuration of a pixel 112. [Figure 4] 2 is a diagram showing an example of a more specific configuration of a main circuit section 210. FIG. [Figure 5] 2 is a plan view showing an example of a specific configuration of a signal processing block 220. FIG. [Figure 6] FIG. 2 is a plan view showing an example of a plurality of signal processing blocks 220 according to the embodiment. [Figure 7]2 is a plan view showing details of an example of a plurality of signal processing blocks 220 according to the embodiment. FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along the line A1-A1 in FIG. 7. [Figure 9] 2 is a cross-sectional view showing an example of a bonding surface 300 between a first substrate 100 and a second substrate 200. FIG. [Figure 10] FIG. 10 is a schematic plan view showing an example of the arrangement of a first signal junction 310-1 and a first control junction 325-1. [Figure 11] FIG. 2 is a schematic plan view showing an example of the configuration of an imaging element 400. [Figure 12] 10 is a diagram for explaining an example of a wiring method for the imaging element 400. FIG. [Figure 13] 10 is a diagram for explaining an example of a wiring method for the imaging element 400. FIG. [Figure 14] FIG. 1 is a block diagram showing an example of the configuration of an imaging device 500 according to an embodiment. [Figure 15] FIG. 10 is a plan view showing an example of a signal processing block 220 of an image sensor 401 according to a first modified example of an embodiment of the present invention. [Figure 16] FIG. 16 is a cross-sectional view taken along the line A2-A2 in FIG. [Figure 17] FIG. 10 is a plan view showing an example of a signal processing block 220 of an image sensor 402 according to a second modified example of an embodiment of the present invention. [Figure 18] 18 is a cross-sectional view taken along the line A3-A3 in FIG. 17. [Figure 19] FIG. 10 is a plan view showing the arrangement of a plurality of first signal connectors 310-1 in an image sensor 403 according to a third modified example of one embodiment of the present invention. [Figure 20] 10 is a plan view showing an example of the arrangement of a plurality of first signal bonding portions 310-1 when the first substrate 100 is misaligned with respect to the second substrate 200. FIG. [Figure 21] 10 is a plan view showing another example of the arrangement of the plurality of first signal bonding portions 310-1 when the first substrate 100 is misaligned with respect to the second substrate 200. FIG. [Figure 22]10 is a plan view showing another example of the arrangement of the plurality of first signal bonding portions 310-1 when the first substrate 100 is misaligned with respect to the second substrate 200. FIG. [Figure 23] FIG. 10 is a plan view showing another arrangement of the plurality of second signal pads 312-1 at the plurality of first signal junctions 310-1. [Figure 24] FIG. 10 is a plan view showing an example of a signal processing block 220 of an image sensor 404 according to a fourth modified example of an embodiment of the present invention. [Figure 25] FIG. 10 is a plan view showing an example of a signal processing block 220 of an image sensor 405 according to a fifth modified example of an embodiment of the present invention. [Figure 26] FIG. 13 is a plan view showing an example of a signal processing block 220 of an image sensor 406 according to a sixth modified example of an embodiment of the present invention. [Figure 27] FIG. 13 is a plan view showing an example of a signal processing block 220 of an image sensor 407 according to a seventh modified example of an embodiment of the present invention. [Figure 28] FIG. 13 is a plan view showing an example of a signal processing block 220 of an image sensor 408 according to an eighth modified example of an embodiment of the present invention. [Figure 29] FIG. 13 is a schematic plan view showing an example of the arrangement of a first signal junction 310-1 and a first control junction 325-1 in an image sensor 409 according to a ninth modified example of one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0007] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0008] In this specification, the X-axis and Y-axis are perpendicular to each other, and the Z-axis is perpendicular to the XY plane. The XYZ-axes form a right-handed system. The direction parallel to the Z-axis (Z-axis direction) may be referred to as the stacking direction of the imaging element 400. In this specification, the terms "upper" and "lower" are not limited to the up and down directions in the direction of gravity. These terms simply refer to relative directions in the Z-axis direction. In this specification, the arrangement in the X-axis direction will be referred to as a "row" and the arrangement in the Y-axis direction will be referred to as a "column", but the row and column directions are not limited to this.

[0009] 1 is a diagram showing an overview of an image sensor 400 according to this embodiment. The image sensor 400 captures an image of a subject. The image sensor 400 generates image data of the captured subject. The image sensor 400 includes a first substrate (pixel chip) 100 and a second substrate (signal processing chip) 200. As shown in FIG. 1, a first substrate 100 is laminated on a second substrate 200.

[0010] The first substrate 100 has a pixel section 110. As will be described later, the pixel section 110 has a plurality of pixels 112. The pixels 112 output pixel signals based on incident light. The second substrate 200 has a main circuit section 210 and a peripheral circuit section 230 .

[0011] The main circuit unit 210 receives pixel signals output from the first substrate 100. The main circuit unit 210 processes the input pixel signals. In this example, the main circuit unit 210 is disposed on the second substrate 200 at a position facing the pixel unit 110. The main circuit unit 210 may output a control signal to the pixel unit 110 to control driving of the pixel unit 110.

[0012] The peripheral circuit section 230 controls the driving of the main circuit section 210. The peripheral circuit section 230 is arranged around the main circuit section 210 on the second substrate 200. The peripheral circuit section 230 may also be electrically connected to the first substrate 100 and control the driving of the pixel section 110. In this example, the peripheral circuit section 230 is arranged along two sides of the second substrate 200, but the arrangement of the peripheral circuit section 230 is not limited to this example.

[0013] The imaging element 400 may have a third substrate stacked on the first substrate 100 and the second substrate 200. For example, the third substrate has a data processing unit. For example, the data processing unit performs addition processing, thinning processing, and other image processing of the signals output by the second substrate 200. The structure of the imaging element 400 may be a back-illuminated type or a front-illuminated type.

[0014] 2 shows an example of a specific configuration of the pixel section 110. In this example, an enlarged view of the pixel section 110 and a pixel block 120 provided in the pixel section 110 is shown.

[0015] The pixel unit 110 has a plurality of pixel groups 115 arranged side by side in the row direction (second direction) and the column direction (first direction). The pixel unit 110 of this example has M×N pixel blocks 120 (M and N are natural numbers). In this example, the case where M is equal to N is illustrated, but M and N may be different. The first direction may be the row direction, and the second direction may be the column direction.

[0016] Each pixel block 120 has at least one pixel 112. In this example, the pixel block 120 has m×n pixels 112 (m and n are natural numbers). For example, the pixel block 120 has 16×16 pixels 112. The number of pixels 112 corresponding to the pixel block 120 is not limited to this. In this example, the case where m is equal to n is illustrated, but m may be different from n. In the pixel block 120, a plurality of pixels 112 are arranged in both the row and column directions. For example, a pixel block 120 has a plurality of pixels 112 connected to a common control line in the row direction. For example, each pixel 112 in the pixel block 120 is connected to the common control line so that the pixels 112 are set to the same exposure time. In one example, n pixels 112 arranged in the row direction are connected by a common control line.

[0017] On the other hand, between different pixel blocks 120, one pixel block 120 may be set to an exposure time different from that of the other pixel block 120. For example, when one pixel block 120 and the other pixel block 120 are arranged in the same row, the multiple pixels 112 in the m-th row of one pixel block 120 are commonly connected by a control line that is different from the common control line to which the multiple pixels 112 in the m-th row of the other pixel block 120 are connected.

[0018] For example, when one pixel block 120 and the other pixel block 120 are arranged in the same column, the pixels 112 in the nth row of one pixel block 120 are commonly connected by a signal line that is different from the common signal line to which the pixels 112 in the nth row of the other pixel block 120 are connected.

[0019] Each pixel block 120 has one or more pixels 112. The pixel blocks 120 are arranged corresponding to signal processing blocks 220, which will be described later. That is, one pixel block 120 is arranged for one signal processing block 220. In one pixel block 120, m pixels 112 arranged along the column direction are connected to a common signal line. In this example, one pixel block 120 is arranged for one signal processing block 220. The pixel block 120 has m×n pixels 112. For example, the pixel block 120 has 16×16 pixels 112. The number of pixels 112 corresponding to the pixel block 120 is not limited to this. In other words, the pixel block 120 may have one pixel 112. When multiple pixel blocks 120 are arranged for one signal processing block 220, different exposure times may be set for each pixel block 120. In this case, the pixel block 120 has 2m×n pixels 112. Specifically, for example, the pixel block 120 has 32×16 pixels 112. The number of pixels 112 corresponding to the pixel block 120 is not limited to this.

[0020] The pixels 112 have a photoelectric conversion function that converts light into electric charges. The pixels 112 accumulate the electric charges generated by the photoelectric conversion. m pixels 112 are arranged in the column direction and connected to a common signal line 122. The m pixels 112 are arranged in n columns in the row direction in the pixel block 120. The plurality of pixel blocks 120 includes a first pixel block 120-1, a second pixel block 120-2, and a third pixel block 120-3. The first pixel block 120-1 includes a plurality of first pixels, which are m×n pixels 112. The second pixel block 120-2 includes a plurality of second pixels, which are m×n pixels 112. The third pixel block 120-3 includes a plurality of third pixels, which are m×n pixels 112. For example, the first pixel block 120-1, the second pixel block 120-2, and the third pixel block 120-3 are arranged side by side in this order in the column direction, i.e., the second pixel block 120-2 is arranged between the first pixel block 120-1 and the third pixel block 120-3.

[0021] 3 shows an example of the circuit configuration of the pixel 112. The pixel 112 includes a photoelectric conversion unit 104, a transfer unit 123, a discharge unit 124, a reset unit 126, and a pixel output unit 127. The pixel output unit 127 includes an amplifier unit 128 and a selection unit 129. In this example, the transfer unit 123, the discharge unit 124, the reset unit 126, the amplifier unit 128, and the selector unit 129 are described as N-channel FETs, but the type of transistor is not limited to this.

[0022] The photoelectric conversion unit 104 has a photoelectric conversion function of converting light into electric charges. The photoelectric conversion unit 104 accumulates the electric charges generated by the photoelectric conversion. The photoelectric conversion unit 104 is configured by, for example, a photodiode.

[0023] The transfer unit 123 transfers the charges in the photoelectric conversion unit 104 to the accumulation unit 125. The transfer unit 123 controls the electrical connection between the photoelectric conversion unit 104 and the accumulation unit 125. The transfer unit 123 is configured by, for example, a transistor. The transfer unit 123 may be an element that has a gate terminal and configures part of a transistor with a part of the photoelectric conversion unit 104 as the source terminal and a part of the accumulation unit 125 as the drain terminal. The gate terminal of the transfer unit 123 is connected to a transfer control line 143 for inputting a transfer control signal φTX. The transfer control line 143 will be described later.

[0024] The discharge unit 124 controls the connection between the photoelectric conversion unit 104 and the power supply wiring, and discharges the charge accumulated in the photoelectric conversion unit 104 to the power supply wiring to which the power supply voltage VDD is supplied. The gate terminal of the discharge unit 124 is connected to a discharge control line for inputting a discharge control signal φPDRST. Note that although the discharge unit 124 has been described as discharging the charge of the photoelectric conversion unit 104 to the power supply wiring to which the power supply voltage VDD is supplied, the discharge unit 124 may also discharge the charge to a power supply wiring to which a power supply voltage different from the power supply voltage VDD is supplied.

[0025] The charge from the photoelectric conversion unit 104 is transferred to the accumulation unit 125 by the transfer unit 123. The accumulation unit 125 is configured by, for example, a floating diffusion (FD).

[0026] The reset unit 126 controls the connection between the storage unit 125 and the power supply wiring, and resets the potential of the photoelectric conversion unit 104 to the power supply voltage VDD, which is a reference potential. The reset unit 126 controls the electrical connection between the storage unit 125 and the power supply wiring. The reset unit 126 is configured by, for example, a transistor. The reset unit 126 may be an element that has a gate terminal and configures part of a transistor with a part of the storage unit 125 as the source terminal and a part of a diffusion region connected to the power supply wiring as the drain terminal. The gate terminal of the reset unit 126 is connected to a reset control line 144 for inputting a reset control signal φRST. The reset control line 144 will be described later.

[0027] The pixel output unit 127 outputs a signal based on the potential of the storage unit 125 to the signal line 122. The pixel output unit 127 has an amplifier unit 128 and a selection unit 129. The amplifier unit 128 and the selection unit 129 are each composed of a transistor. The amplifier unit 128 has a gate terminal connected to the storage unit 125, a drain terminal connected to a power supply line to which a power supply voltage VDD is supplied, and a source terminal connected to the drain terminal of the selection unit 129.

[0028] The selection unit 129 controls the electrical connection between the pixel 112 and the signal line 122. When the selection unit 129 electrically connects the pixel 112 and the signal line 122, a pixel signal is output from the pixel 112 to the signal line 122. The selection unit 129 may be an element that has a gate terminal and forms part of a transistor, with a part of the amplifier unit 128 as its source terminal and a part of a diffusion region connected to the signal line 122 as its drain terminal. The gate terminal of the selection unit 129 is connected to a selection control line 145 that spans multiple pixel blocks 120 and is used to input a selection control signal φSEL. The source terminal of the selection unit 129 is connected to the load current source 121.

[0029] The load current source 121 is connected to the signal line 122 and supplies a current for reading out pixel signals from the pixels 112. This stabilizes the operation of the amplifier unit 128. The load current source 121 is also connected to the signal line 122. The load current source 121 may be provided on the first semiconductor substrate 100 or on the second semiconductor substrate 200. Furthermore, the storage unit 125 and pixel output unit 127 may be shared with other pixels 112. Furthermore, the pixel 112 may be configured with a plurality of photoelectric conversion units 104 and transfer units 123.

[0030] 4 shows an example of a more specific configuration of the main circuit section 210. In this example, an enlarged view of the main circuit section 210 and the signal processing block 220 provided in the main circuit section 210 is shown.

[0031] The main circuit unit 210 has signal processing blocks 220 arranged in the row and column directions. In this example, the main circuit unit 210 has M×N signal processing blocks 220. The main circuit unit 210 has a signal processing block 220 directly below a pixel block 120. One pixel block 120 and one signal processing block 220 have approximately the same shape and size. In this example, the main circuit unit 210 has one signal processing block 220 for one pixel block 120.

[0032] The signal processing block 220 is located directly below the pixel block 120 in the stacking direction. The signal processing block 220 located directly below the pixel block 120 is electrically connected to the pixel block 120 directly above in the stacking direction by local control lines such as the transfer control line 143 and the discharge control line. The pixel block 120 outputs a pixel signal to the signal processing block 220 directly below via a signal line 122.

[0033] The signal processing blocks 220 are disposed at positions corresponding to the pixel blocks 120. The signal processing blocks 220 control the driving of the corresponding pixel blocks 120. For example, the signal processing blocks 220 control the exposure time of the pixel blocks 120. The signal processing blocks 220 may control the exposure time for each pixel block 120. Furthermore, the signal processing block 220 has a processing circuit such as an AD converter, and processes the signal output from the pixel block 120. In one example, the signal processing block 220 converts the analog pixel signal output from the corresponding pixel block 120 into a digital signal. The signal processing block 220 in this example includes an exposure control unit 10, a pixel driving unit 20, and a signal processing unit 25.

[0034] The exposure control unit 10 controls exposure of the plurality of pixels 112. The exposure control unit 10 generates a signal for controlling the exposure time of the pixels 112. In one example, the exposure control unit 10 adjusts at least one of the start timing and end timing of exposure to control the exposure time for each pixel block 120. The exposure control unit 10 in this example is provided extending in the row direction.

[0035] The pixel driving unit 20 is bonded to the first substrate 100 and drives a plurality of pixels 112. The pixel driving unit 20 selects and drives an arbitrary pixel 112 from the plurality of pixels 112. In this example, the pixel driving unit 20 is provided extending in the column direction. As a result, the pixel driving unit 20 is disposed at a position corresponding to the m pixels 112 disposed in the column direction. The exposure control unit 10 and the pixel driving unit 20 are disposed in an L-shape, with the pixel driving unit 20 extending in the column direction and the exposure control unit 10 extending in the row direction.

[0036] The signal processing unit 25 includes a signal input unit 30, a plurality of signal conversion units 40, and a signal output unit 50. The signal input unit 30 joins the first substrate 100 and the second substrate 200. The signal input unit 30 inputs pixel signals input from the first substrate 100 to a plurality of signal conversion units 40. The signal input units 30 are provided corresponding to n pixels 112 arranged in the row direction, and input pixel signals to the plurality of signal conversion units 40 for each column.

[0037] The signal conversion unit 40 includes an ADC (Analog-to-Digital Converter). N signal conversion units 40 are provided corresponding to the n pixels 112. The multiple signal conversion units 40 digitally convert (process) analog signals (signals) from the pixels 112 output by the pixel unit 110. The multiple signal conversion units 40 in this example convert analog pixel signals into digital signals. Each signal conversion unit 40 sequentially converts analog signals from m pixels 112 arranged in the column direction into digital signals. The multiple signal conversion units 40 digitally convert, in parallel, analog signals from the pixels 112 arranged in n columns in the row direction. The signal processing block 220 may include one signal conversion unit 40.

[0038] The signal output section 50 receives digital signals from the plurality of signal conversion sections 40. In one example, the signal output section 50 temporarily stores the digital signals. The signal output section 50 may include a latch circuit for storing the digital signals. The signal output unit 50 is provided between the signal conversion unit 40 and the exposure control unit 10 in the column direction, and outputs a digital signal. The signal output unit 50 in this example outputs the digital signal to the outside of the main circuit unit 210. The signal output unit 50 extends in the row direction, and is provided adjacent to the signal conversion unit 40 and the exposure control unit 10.

[0039] The image sensor 400 of this example has a function of reading out pixel signals in parallel using a signal processing block 220 provided for each pixel block 120. The image sensor 400 can set the exposure time for each pixel block 120 according to the intensity of incident light, thereby expanding the dynamic range.

[0040] 5 shows an example of a specific configuration of the signal processing block 220. The signal conversion unit 40 of this example includes a comparator 42 and a storage unit 44. The signal processing block 220 of this example includes a local control unit 12 and a level shift unit 14 that configure the exposure control unit 10.

[0041] The comparators 42 are arranged extending in the column direction. n comparators 42 are arranged in the row direction. One comparator 42 is provided for m pixels 112. The comparators 42 sequentially read out pixel signals from the m pixels 112 and convert them into digital signals.

[0042] The storage unit 44 temporarily stores the digital signal from the comparator 42. In this example, the storage unit 44 is provided on the negative side of the comparator 42 in the Y-axis direction in the signal conversion unit 40. For example, the storage unit 44 has a latch circuit. The storage unit 44 may have a memory configured with an SRAM or the like.

[0043] The local control unit 12 outputs a control signal for controlling the operations of the transfer unit 123 and the discharge unit 124. The local control unit 12 locally controls either the first transfer control signal φTX1 or the second transfer control signal φTX2. In this specification, local control refers to controlling the driving of each pixel block 120. For example, the local control unit 12 performs local control using a second transfer control signal φTX2. The local control unit 12 extends in the row direction. The local control unit 12 is provided between the level shift unit 14 and the signal output unit 50.

[0044] The level shift unit 14 converts the voltage level of the control signal output by the local control unit 12 and outputs the converted signal. The level shift unit 14 extends in the row direction. The level shift unit 14 is provided closer to the outer periphery of the signal processing block 220 than the local control unit 12. The positive end of the level shift unit 14 in the X-axis direction and the negative end of the level shift unit 14 in the Y-axis direction are located on the outermost sides of the signal processing block 220. The negative end of the level shift unit 14 in the X-axis direction is in contact with the pixel driving unit 20.

[0045] The level shift unit 14 and pixel driving unit 20 handle the level-shifted signal. On the other hand, the local control unit 12, the level shift unit 14 and the pixel driving unit 20 handle the pixel signal output from the first substrate 100.

[0046] 6 shows an example of a plurality of signal processing blocks 220 according to the embodiment. In this example, the plurality of signal processing blocks 220 are arranged in a mirrored manner relative to adjacent ones. The figure illustrates 12 of the plurality of signal processing blocks 220 provided in the main circuit unit 210.

[0047] The inverted arrangement means that the areas in which each component of the signal processing block 220 (e.g., the exposure control unit 10, the pixel driving unit 20, and the signal processing unit 25) is formed are arranged symmetrically with respect to the boundary line between the blocks. That is, it is not necessary to reverse the arrangement of the circuits constituting the signal processing block 220. Furthermore, the readout order of the pixels in the signal processing block 220 is not limited to being reversed.

[0048] Of the 12 signal processing blocks 220, three signal processing blocks 220 arranged side by side in the Y-axis direction at the negative end in the X-axis direction will be described below. In this embodiment, for convenience of explanation, the three signal processing blocks 220 arranged in the Y-axis direction at the negative end of the X-axis direction will be referred to as the first signal processing block 220-1 to the third signal processing block 220-3 as shown below, but any three signal processing blocks 220 arranged in the Y-axis direction can be referred to as the first signal processing block to the third signal processing block.

[0049] As shown in Fig. 7, the three signal processing blocks 220 include a first signal processing block 220-1, a second signal processing block 220-2, and a third signal processing block 220-3. Note that Fig. 7 and Figs. 15, 17, 24 to 28 described below focus on the configuration of the signal processing block 220 (signal processing unit 25). Here, among the plurality of pixels 112, the pixels 112 whose signals are processed by the first signal processing block 220-1, the second signal processing block 220-2, and the third signal processing block 220-3 are referred to as the plurality of first pixels, the plurality of second pixels, and the plurality of third pixels, respectively. The first signal processing block 220-1 has a plurality of first signal conversion units 40-1 that process signals from a plurality of first pixels. The plurality of first signal conversion units 40-1 are arranged side by side in the row direction. The second signal processing block 220-2 has a plurality of second signal conversion units 40-2 that process signals from a plurality of second pixels, and the third signal processing block 220-3 has a plurality of third signal conversion units 40-3 that process signals from a plurality of third pixels. The signal processing blocks 220-1, 220-2, and 220-3 may each have one signal conversion unit 40-1, 40-2, and 40-3.

[0050] 8, the first substrate 100 and the second substrate 200 have semiconductor layers 151 and 241 and wiring layers 152 and 242, respectively. In the first substrate 100, the pixel section 110 is mainly formed in the semiconductor layer 151. In the second substrate 200, the main circuit section 210 is mainly formed in the semiconductor layer 241. The semiconductor layer 151 of the first substrate 100 is located on the opposite side of the second substrate 200 from the wiring layer 152 of the first substrate 100 in the Z-axis direction. The semiconductor layer 241 of the second substrate 200 is located on the opposite side of the first substrate 100 from the wiring layer 242 of the second substrate 200 in the Z-axis direction. The wiring layer 152 of the first substrate 100 is located between the semiconductor layer 151 of the first substrate 100 and the wiring layer 242 of the second substrate 200. The wiring layer 242 of the second substrate 200 is located between the wiring layer 152 of the first substrate 100 and the semiconductor layer 241 of the second substrate 200. The first substrate 100 and the second substrate 200 are bonded at a bonding surface 300. The semiconductor layer 151 of the first substrate 100, the wiring layer 152 of the first substrate 100, the wiring layer 242 of the second substrate 200, and the semiconductor layer 241 of the second substrate 200 are stacked in the above order. The imaging element 400 has a microlens 113 and a color filter. The microlens 113 and the color filter are provided for each pixel 112. The photoelectric conversion unit 104 in each pixel 112 receives light that has passed through the microlens 113 and the color filter. The surface of the photoelectric conversion unit 104 functions as the light receiving surface 112a of the pixel 112. The direction perpendicular to the light receiving surface 112a and the direction along the optical axis of the microlens 113 are the direction along the Z axis (stacking direction).

[0051] The following describes bonding at bonding surface 300 between first substrate 100 and second substrate 200. In particular, bonding of the first pixel block to the third pixel block on first substrate 100 and the first signal processing block to the third signal processing block on second substrate 200 will be described.

[0052] As shown in FIGS. 7 and 8 , the image sensor 400 of this example has a plurality of bonding portions 305 on the bonding surface 300. The bonding portions 305 bond the first substrate 100 and the second substrate 200 together. The bonding portions 305 are used to input pixel signals from the first substrate 100 to the signal conversion unit 40 of the second substrate 200. For example, the image sensor 400 has a plurality of first signal bonding portions 310-1, a plurality of second signal bonding portions 310-2, and a plurality of third signal bonding portions 310-3 as the plurality of bonding portions 305. The image sensor 400 also has a plurality of first reference potential bonding portions 315-1, a plurality of second reference potential bonding portions 315-2, and a plurality of third reference potential bonding portions 315-3 as the plurality of bonding portions 305. In FIG. 7, the joints 310-1, 310-2, 310-3, 315-1, 315-2, and 315-3 and the signal conversion unit 40 are shown on the same plane, but in reality, as shown in FIG. 8, the positions of the two in the Z direction are different.

[0053] Hereinafter, when referring to the signal junctions 310-1, 310-2, and 310-3 regardless of the signal processing block 220, they will be referred to as signal junctions 310, and when referring to the reference potential junctions 315-1, 315-2, and 315-3 regardless of the signal processing block 220, they will be referred to as reference potential junctions 315. The signal junction unit 310 outputs signals from each pixel 112 to the signal conversion unit 40 via the signal input unit 30. The reference potential junction unit 315 is used for the reference potential of the signal processing block 220. The reference potential is, for example, a ground voltage.

[0054] As shown in FIG. 7, the first signal junction portion 310-1, the second signal junction portion 310-2, and the third signal junction portion 310-3 are arranged in this order in the column direction. The first signal connecting unit 310-1 outputs the signal from the first pixel to the first signal converting unit 40-1. 7, the first signal junction 310-1, the reference potential junctions 315-1 and 315-2, the second signal junction 310-2, the third signal junction 310-3, and the third reference potential junction 315-3 are arranged in this order in the column direction on the junction surface 300. In particular, the first signal junction 310-1, the reference potential junctions 315-1 and 315-2, and the second signal junction 310-2 are arranged next to each other in the column direction. Furthermore, when viewed from the Z-axis direction, the first signal conversion unit 40-1, the first signal junction unit 310-1, the reference potential junctions 315-1 and 315-2, the second signal junction unit 310-2, the second signal conversion unit 40-2, the third signal conversion unit 40-3, the third signal junction unit 310-3, and the third reference potential junction unit 315-3 are arranged in this order in the column direction. Note that in Fig. 7, the signal output unit 50, the local control unit 12, and the level shift unit 14 are omitted between the second signal conversion unit 40-2 and the third signal conversion unit 40-3.

[0055] 8, the first signal junction portion 310-1 has a first signal pad (first pad) 311-1 and a second signal pad (second pad) 312-1. The first signal pad (first pad) 311-1 and the second signal pad (second pad) 312-1 are electrically connected to each other. The first signal pad 311-1 and the second signal pad 312-1 are formed of a conductive metal such as copper or a copper alloy, etc. For example, the first signal pad 311-1 and the second signal pad 312-1 each have a rectangular shape in a plan view. The first signal pad 311-1 is provided on the end surface (bonding surface 300) of the first substrate 100 facing the second substrate 200. The second signal pad 312-1 is provided on the end surface (bonding surface 300) of the second substrate 200 facing the first substrate 100. The first signal pad 311-1 is connected to the first pixel by a signal line 122. The second signal pad 312-1 is connected to the signal input unit 30 by a signal line 122. The signal input unit 30 outputs a signal from the first pixel to the first signal conversion unit 40-1.

[0056] The second signal connector 310-2 outputs a signal from the second pixel to the second signal converter 40-2. The third signal connector 310-3 outputs a signal from the third pixel to the third signal converter 40-3. The second signal connector 310-2 and the third signal connector 310-3 are configured similarly to the first signal connector 310-1. 7, the column-direction spacing L1 between the first signal junction 310-1 and the second signal junction 310-2 is narrower than the column-direction spacing L2 between the second signal junction 310-2 and the third signal junction 310-3. Furthermore, the column-direction spacing between the first reference potential junction 315-1 and the second reference potential junction 315-2 is narrower than the column-direction spacing between the second reference potential junction 315-2 and the third reference potential junction 315-3.

[0057] 8, the first signal conversion unit 40-1, the second signal conversion unit 40-2, and the third signal conversion unit 40-3 are each disposed on a semiconductor layer 241 on the second substrate 200. For example, the pixel driving unit 20 is also disposed on the semiconductor layer 241. When the imaging element 400 is viewed in the Z-axis direction, the first signal conversion unit 40-1, the first signal connection unit 310-1, the second signal connection unit 310-2, and the second signal conversion unit 40-2 are arranged in the Y-direction in the order of the first signal conversion unit 40-1, the first signal connection unit 310-1, the second signal connection unit 310-2, and the second signal conversion unit 40-2.

[0058] The first reference potential junction 315-1 is used for the reference potential of the first signal processing block 220-1. The first reference potential junction 315-1 has a configuration similar to that of the first signal junction 310-1. The first reference potential junction 315-1 has a first reference potential pad 316-1 and a second reference potential pad 317-1 that are configured similarly to the first signal pad 311-1 and the second signal pad 312-1 of the first signal junction 310-1. The first reference potential pad 316-1 and the second reference potential pad 317-1 are electrically connected. Although not shown, the first reference potential pad 316-1 is connected by a reference potential line 140 to a reference potential pad provided on the surface of the first substrate 100 opposite to the second substrate 200. The second reference potential pad 317-1 is connected by the reference potential line 140 to the GND port of the first signal conversion unit 40-1 or the like.

[0059] The second reference potential junction 315-2 and the third reference potential junction 315-3 are used for the reference potentials of the second signal processing block 220-2 and the third signal processing block 220-3, respectively. The second reference potential junction 315-2 and the third reference potential junction 315-3 are configured similarly to the first reference potential junction 315-1. The first signal junction 310-1, the second signal junction 310-2, and the third signal junction 310-3 respectively join the first substrate 100 and the second substrate 200. Similarly, the first reference potential junction 315-1, the second reference potential junction 315-2, and the third reference potential junction 315-3 respectively join the first substrate 100 and the second substrate 200.

[0060] 9, a plurality of reference joints (bumps) 320 including joints 310-1, 310-2, 310-3, 315-1, 315-2, and 315-3 are arranged in the row and column directions on the joint surface 300. Note that FIG. 9 shows the reference joints 320 corresponding to the range R1 in FIG. For example, the plurality of reference junctions 320 are arranged at positions corresponding to the plurality of pixels 112. Note that a first signal junction 310-1 and a first reference potential junction 315-1 are shown in FIG. Of the multiple reference junctions 320, the reference junctions 320 connected to the first signal conversion unit 40-1, etc. via the signal lines 122, etc., become the junctions 310-1, 310-2, 310-3, 315-1, 315-2, 315-3, and the first reference potential junction 315-1, etc., which will be described later. The multiple reference junctions 320 are also arranged on the junction surface 300 at positions corresponding to the pixel driving unit 20, the multiple signal conversion units 40, etc.

[0061] As shown in FIG. 10, for example, when the imaging element 400 is viewed in the Z-axis direction, the multiple first signal junction sections 310-1 are arranged in a row at a position where at least a portion of each overlaps with one first pixel 112-1 at the end of the first side in the column direction, and at a position where at least a portion of each overlaps with multiple first pixels 112-1 arranged in the row direction. A first signal line 122-1 that transmits a signal from the first pixel 112-1 is connected to the first signal junction 310-1. The first signal line 122-1 is provided on each of the first substrate 100 and the second substrate 200. The first signal junction 310-1 transmits the signal from the first pixel 112-1 to the signal input unit 30 via the first signal junction 310-1. A portion of the first signal line 122-1 provided on the first substrate 100 extends in the column direction.

[0062] The image sensor 400 of this example has a plurality of control junctions 325 on the junction surface 300. The control junctions 325 are junctions for transmitting control signals for controlling the pixels 112 of the pixel block 120 from the pixel driver 20 of the signal processing block 220 to the plurality of first pixels 112. For example, the image sensor 400 of this example has a plurality of first control junctions 325-1 on the junction surface 300. The first control junction 325-1 is a junction for transmitting control signals for controlling the plurality of first pixels 112-1 from the first signal processing block 220-1 to the plurality of first pixels 112-1 of the first pixel block 120-1. The plurality of first control junctions 325-1 are configured similarly to the first signal junctions 310-1 and join the first substrate 100 and the second substrate 200. The multiple first control junctions 325-1 are arranged on the junction surface 300 between the first substrate 100 and the second substrate 200, at positions that overlap the pixel driving unit 20 of the first signal processing block 220-1 when viewed in the Z-axis direction. Hereinafter, when a control junction is referred to without regard to the signal processing block 220, it will be referred to as a control junction 325. The first control junction 325-1 is connected to a first control line 130-1 that transmits a signal for controlling the first pixel 112-1. The first control line 130-1 transmits a control signal from the pixel driver 20 to the first pixel 112-1 via the first control junction 325-1. The first control line 130-1 extends in the row direction from the first control junction 325-1. For example, when the imaging element 400 is viewed in the Z-axis direction, the multiple first control junctions 325-1 are arranged in a position where at least a portion overlaps with one first pixel 112-1 at the end of the first side in the row direction, and at a position where at least a portion overlaps with multiple first pixels 112-1 arranged in the column direction.

[0063] That is, two bonding portions 310-1 and 325-1 are arranged at a position corresponding to the first pixel 112-1 arranged at the end on the first side in the row direction and at the end on the first side in the column direction.

[0064] 7, the first signal processing block 220-1 has a first load current source 221-1. The first load current source 221-1 is a current source used to read out signals from a plurality of first pixels. The first load current source 221-1 is connected to a first signal line 122-1 and supplied to the pixel 112-1 via a first signal junction 310-1. Therefore, in the first signal processing block 220-1, the load current source 221-1 is disposed at a position overlapping the first signal junction 310-1 when viewed in the Z-axis direction. The second signal processing block 220-2 and the third signal processing block 220-3 include a second load current source 221-2 and a third load current source 221-3 configured similarly to the first load current source 221-1.

[0065] 11 shows an example of the configuration of the image sensor 400. In this example, an example of a wiring method for the image sensor 400 is shown. The first substrate 100 includes connection regions 132 provided on both ends of the pixel section 110. The second substrate 200 includes a connection region 232 and a global driving section 234 provided in a peripheral circuit section 230.

[0066] The global driving unit 234 outputs a control signal for driving the pixel 112 to the connection region 232. For example, the global driving unit 234 outputs a reset control signal φRST and a selection control signal φSEL as control signals. The connection region 232 outputs a control signal from the global driving unit 234 to the connection region 132. In one example, the connection region 232 is electrically connected to the connection region 132 by a conductive via or the like.

[0067] The connection region 132 outputs a control signal to the pixel unit 110 to control driving of the pixel unit 110. The connection region 132 in this example outputs the control signal to the pixel unit 110 via a transfer control line 143, a reset control line 144, and a selection control line 145 that extend in the row direction. That is, the image sensor 400 in this example globally controls the pixel unit 110 using the reset control signal φRST and the selection control signal φSEL.

[0068] In the image sensor 400 of this example, a control signal is output from the second substrate 200 to the first substrate 100, and then a pixel signal is returned from the pixel section 110 to the main circuit section 210. However, in the image sensor 400, the global driving section 234 may be disposed on the first substrate 100.

[0069] 12 is a diagram illustrating an example of a wiring method for the imaging element 400. In this example, the global driving section 234 is provided in the peripheral circuit section 230 disposed on both ends of the main circuit section 210.

[0070] The local control line 141-1 is connected to the first pixel block 120-1. In this example, the local control line 141 is connected to the gate terminals of the transfer unit 123 and the discharge unit 124 provided in the first pixel block 120-1. The local control line 141-1 supplies the first transfer control signal φTX1 and the second transfer control signal φTX2 output from the first signal processing block 220-1 via the control junction 325 to the first pixel block 120-1. The local control line 141-1 may be provided corresponding to the pixel block 120. For example, in the pixel block 120, a common local control line 141-1 is connected to n pixels 112 arranged in the row direction.

[0071] The local control line 141-2 is connected to the second pixel block 120-2. In this example, the local control line 141-2 is connected to the gate terminals of the transfer unit 123 and the discharge unit 124 provided in the second pixel block 120-2. The local control line 141-2 supplies the first transfer control signal φTX1 and the second transfer control signal φTX2 output from the second signal processing block 220-2 via the control junction 325 to the second pixel block 120-2.

[0072] The global driver 234 outputs a reset control signal φRST, a selection control signal φSEL, and a transfer selection control signal φTXSEL. The global driver 234 is connected to a reset control line 144 and a selection control line 145 that output signals to each pixel block 120. The global driver 234 supplies a reset control signal φRST to the plurality of pixel blocks 120 via a reset control line 144. The global driver 234 also supplies a selection control signal φSEL to the plurality of pixel blocks 120 via a selection control line 145. The global driver 234 supplies a transfer selection control signal φTXSEL to the plurality of signal processing blocks 220 via a transfer selection control line.

[0073] The transfer selection control signal φTXSEL is supplied from the global driver 234 to the signal processing block 220 to control the exposure time for each pixel block 120. The signal processing block 220, to which the transfer selection control signal φTXSEL is supplied, outputs the transfer selection control signal φTXSEL to the corresponding pixel block 120. The pixel block 120 determines whether to input the transfer selection control signal φTXSEL to the pixel 112 as the first transfer control signal φTX1 or the second transfer control signal φTX2. As a result, input of the first transfer control signal φTX1 or the second transfer control signal φTX2 to the pixel 112 is skipped.

[0074] For example, when the first transfer control signal φTX1 determines the end time of exposure, the signal processing block 220 extends the exposure time by skipping the first transfer control signal φTX1. In this way, the transfer selection control signal φTXSEL can adjust the exposure time of the pixel block 120. The same applies when the second transfer control signal φTX2 determines the start or end time of exposure.

[0075] The transfer control line 143 is provided in common to multiple pixel blocks 120. In this example, the transfer control line 143 is wired so as to cross the first substrate 100 in the row direction. The transfer control line 143 may also be wired so as to cross the first substrate 100 in the column direction. Similarly, the reset control line 144 and the selection control line 145 are provided in common to multiple pixel blocks 120.

[0076] For example, the transfer control line 143 is connected to the gate terminals of the reset unit 126 and the selection unit 129 of the pixel block 120, and supplies a reset control signal φRST and a selection control signal φSEL. The transfer control line 143 is also connected to each of the multiple signal processing blocks 220, and supplies a transfer selection control signal φTXSEL to the exposure control unit 10.

[0077] 13 is a diagram for explaining an example of a wiring method for the image sensor 400. In this example, wiring for inputting pixel signals from the pixels 112 to the signal processing block 220 is shown. The ground wiring GND is set to a predetermined reference potential VGND. In this example, the ground wiring GND is wired in the row direction so as to cross the pixel chip 100. The ground wiring GND is connected to the signal input unit 30 of the signal processing block 220 via a reference potential junction 315.

[0078] The signal input unit 30 is connected to the output wiring of the voltage VPOUT and the power supply wiring of the voltage VDD via a signal junction unit 310. The signal input unit 30 is connected to a ground wiring GND set to a reference potential VGND. The signal input unit 30 outputs a pixel signal to a correspondingly provided comparator 42. For example, n comparators 42 are provided in the row direction.

[0079] 14 is a block diagram showing an example of the configuration of an image capturing apparatus 500 according to an embodiment. The image capturing apparatus 500 includes an image sensor 400, a system control unit 501, a drive unit 502, a photometry unit 503, a work memory 504, a recording unit 505, a display unit 506, a drive unit 514, and a photographing lens 520.

[0080] The photographing lens 520 guides the subject light beam incident along the optical axis OA to the image sensor 400. The photographing lens 520 is composed of a group of multiple optical lenses and forms an image of the subject light beam from the scene near its focal plane. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the image capturing device 500. In FIG. 13, the photographing lens 520 is represented by a virtual single lens placed near the pupil.

[0081] The driver 514 drives the photographing lens 520. In one example, the driver 514 changes the focus position by moving the optical lens group of the photographing lens 520. The driver 514 may also drive an iris diaphragm in the photographing lens 520 to control the amount of subject light entering the image sensor 400.

[0082] The drive unit 502 has a control circuit that executes charge accumulation control such as timing control and area control of the image sensor 400 in accordance with instructions from the system control unit 501. Furthermore, the operation unit 508 receives instructions from the photographer using a release button or the like.

[0083] The image sensor 400 passes pixel signals to an image processing unit 511 in the system control unit 501. The image processing unit 511 generates image data by performing various image processes using the work memory 504 as a workspace. For example, when generating image data in JPEG file format, a color video signal is generated from a signal obtained using the Bayer array, and then compression processing is performed. The generated image data is recorded in a recording unit 505 and converted into a display signal, which is then displayed on a display unit 506 for a preset time.

[0084] The photometry unit 503 detects the luminance distribution of a scene prior to a series of shooting sequences for generating image data. The photometry unit 503 includes, for example, an AE sensor with approximately one million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the luminance of each region of the scene.

[0085] The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated luminance distribution. The image sensor 400 may also serve as the photometry unit 503. The calculation unit 512 also executes various calculations for operating the imaging device 500. Part or all of the drive unit 502 may be mounted on the image sensor 400. Part of the system control unit 501 may be mounted on the image sensor 400.

[0086] As described above, in the image sensor 400 of this embodiment, the distance L1 between the first signal junction 310-1 and the second signal junction 310-2 is narrower than the distance L2 between the second signal junction 310-2 and the third signal junction 310-3. Therefore, by concentrating the signal lines connected to the first signal junction 310-1 and the second signal junction 310-2 in a narrower range in the column direction, for example, compared to the signal lines connected to the second signal junction 310-2 and the third signal junction 310-3, the circuit area required in the column direction can be reduced. This improves the layout efficiency of the first signal junction 310-1 and the second signal junction 310-2 in both the row direction (X-axis direction) and the column direction (Y-axis direction). This reduction in circuit area allows the image sensor 400 to be miniaturized.

[0087] When the image sensor 400 is viewed in the Z-axis direction, the first signal conversion unit 40-1, the first signal connection unit 310-1, the second signal connection unit 310-2, and the second signal conversion unit 40-2 are arranged side by side in this order. Therefore, the first signal processing block 220-1 and the second signal processing block 220-2 can be arranged in a mirror image (plane-symmetrical) with respect to a reference plane perpendicular to the column direction. This further improves the layout efficiency of the signal processing blocks 220-1 and 220-2. Identical components are arranged adjacent to each other at the boundary between the signal processing blocks 220-1 and 220-2. Each component of the signal processing block 220 is formed in a well region provided on a semiconductor substrate. The well regions are separated according to the signals they handle. The well regions are separated depending on whether the power supply used is a digital power supply or an analog power supply. Furthermore, even if the signal conversion unit 40 uses the same analog power supply, it may be separated from an area that uses another analog power supply from the perspective of noise. Separating the well regions requires well isolation regions spaced according to the manufacturing process rules.

[0088] In the image sensor 400 of this embodiment, the pixel current source 221, which is an analog power supply, and the memory unit 44 and signal output unit 50, which require digital power supplies, can be arranged separately by inverting the pixel current source 221. By gathering the first signal junction unit 310-1 and the second signal junction unit 310-2 together so that the pixel current source 221, the memory unit 44, and the signal output unit 50 can be arranged separately, it is possible to omit well isolation regions spaced according to the manufacturing process rules. This reduces the circuit area, allowing the image sensor 400 to be made smaller. In the signal processing block 220 of this embodiment, well regions for forming the level shift unit 14 and the pixel driving unit 20 are separated from other well regions. For example, the level shift unit 14 and the pixel driving unit 20 can be provided in an L-shape, thereby sharing the well regions of the level shift unit 14 and the pixel driving unit 20. Sharing the well region makes it possible to omit a well isolation region, thereby improving layout efficiency. Furthermore, the signal lines transmitting analog signals and the signal lines transmitting digital signals can be physically separated. This reduces the effect of noise caused by digital signals on analog signals. In the image sensor 400 of this embodiment, the signal input unit 30 to which analog signals are input and the signal output unit 50 to which digital signals are output are physically separated by an inverted arrangement. By gathering the signal lines connected to the first signal junction unit 310-1 and the second signal junction unit 310-2 together so that the signal input unit 30 and the signal output unit 50 can be physically separated, the effect of noise caused by digital signals on analog signals can be reduced.

[0089] The first signal processing block 220-1 has a plurality of first signal conversion units 40-1 arranged in the row direction, which allows signals from a plurality of first pixels 112-1 to be processed in a shorter time by the plurality of first signal conversion units 40-1. The first pixel block 120-1 has a plurality of first pixels 112-1, and therefore, the first pixel block 120-1 can output even more signals due to the plurality of first pixels 112-1.

[0090] Furthermore, the imaging device 500 of this embodiment can be configured using the imaging element 400 with improved layout efficiency. The image sensor 400 does not necessarily have to include the reference potential junctions 315-1, 315-2, and 315-3. In this case, only the signal junctions 310-1, 310-2, and 310-3 are provided aligned in the column direction.

[0091] The configuration of the image pickup device 400 of this embodiment can be modified in various ways as described below. 15 and 16, in the image sensor 400 of this embodiment, the first reference potential junction 315-1 and the second reference potential junction 315-2 may be integrated as a reference potential junction 330. The reference potential junction 330 has the same configuration as the first reference potential junction 315-1. The reference potential junction 330 is used for the reference potential of the first signal processing block 220-1 and the reference potential of the second signal processing block 220-2. The reference potential junction 330 joins the first substrate 100 and the second substrate 200 together. In the image sensor 401 of the first modified example, it is possible to reduce the well region of the reference potential junction 330. Therefore, it is possible to reduce the size of the image sensor 401 in the column direction and reduce the circuit area of ​​the image sensor 401.

[0092] An image sensor 402 according to a second modified example shown in Figures 17 and 18 will now be described. In the image sensor 402, of a pair of first signal conversion units 40-1 adjacent to each other in the row direction, one first signal conversion unit 40-1 will be referred to as a first signal conversion unit 40-1-1, and the other first signal conversion unit 40-1 will be referred to as a first signal conversion unit 40-1-2. Similarly, of a pair of second signal conversion units 40-2 adjacent to each other in the row direction, one second signal conversion unit 40-2 is referred to as second signal conversion unit 40-2-1, and the other second signal conversion unit 40-2 is referred to as second signal conversion unit 40-2-2. The first signal junction 310-1 for the first signal conversion unit 40-1-1 is referred to as the first signal junction 310-1-1, and the second signal junction 310-2 for the second signal conversion unit 40-2-1 is referred to as the second signal junction 310-2-1. The reference potential junction 330 shared by the first signal conversion unit 40-1-1 and the second signal conversion unit 40-2-1 is referred to as the reference potential junction 330-1.

[0093] The first signal junction 310-1 for the first signal conversion unit 40-1-2 is referred to as the first signal junction 310-1-2, and the second signal junction 310-2 for the second signal conversion unit 40-2-2 is referred to as the second signal junction 310-2-2. The reference potential junction 330 shared by the first signal conversion unit 40-1-2 and the second signal conversion unit 40-2-2 is referred to as the reference potential junction 330-2.

[0094] The plurality of first signal junctions 310-1-1, the plurality of second signal junctions 310-2-1, and the plurality of reference potential junctions 330-1 are arranged at intervals from one another in the row direction. The plurality of first signal junctions 310-1-2, the plurality of second signal junctions 310-2-2, and the plurality of reference potential junctions 330-2 are arranged at intervals in the row direction. The plurality of junctions 310-1-1, 310-2-1, 330-1 for the signal conversion units 40-1-1, 40-2-1 and the plurality of junctions 310-1-2, 310-2-2, 330-2 for the signal conversion units 40-1-2, 40-2-2 are arranged with offset positions in the column direction (so as not to overlap in the column direction). More specifically, for example, the plurality of first signal junctions 310-1-1 and the plurality of first signal junctions 310-1-2 are arranged with offset positions in the column direction.

[0095] The signal conversion units 40-1 and 40-2 and the joints 310-1, 310-2, and 330 are formed on different layers in the Z-axis direction. Therefore, even though the signal conversion units 40-1 and 40-2 and the joints 310-1, 310-2, and 330 appear to interfere with each other in the plan view of Figure 17, they do not actually interfere with each other. It is sufficient that the components within the signal conversion units 40-1 and 40-2 and the components within the joints 310-1, 310-2, and 330 do not interfere with each other.

[0096] In the imaging element 402 of the second modified example configured as described above, the first signal junction portion 310-1-1 and the plurality of first signal junction portions 310-1-2 are arranged with their positions offset in the column direction. Therefore, the first signal pad 311-1 and the second signal pad 312-1 constituting the signal junction portions 310-1-1 and 310-1-2 can be made wider in the row direction. Therefore, even if the first signal pad 311-1 is offset in the row direction relative to the second signal pad 312-1 when the substrates 100 and 200 are stacked, a portion where the pads 311-1 and 312-1 face each other is likely to remain. Therefore, the first signal connecting member reliably connects the pads 311-1 and 312-1, improving the bonding yield of the pads 311-1 and 312-1.

[0097] The image sensor 402 of the second modification only needs to have one first signal junction 310-1-1 for the first signal conversion unit 40-1-1, one second signal junction 310-2-1 for the second signal conversion unit 40-2-1, and one reference potential junction 330-1 shared by the first signal conversion unit 40-1-1 and the second signal conversion unit 40-2-1. The same applies to the first signal junction 310-1-2, the second signal junction 310-2-2, and the reference potential junction 330-2.

[0098] In an image pickup device 403 of the third modified example shown in FIG. 19, the arrangement of the plurality of first signal connectors 310-1 is changed from that of the image pickup device 402 of the second modified example. The first signal pads 311-1 are arranged at intervals on a reference line M1 extending in the row direction. The second signal pads 312-1 are arranged at intervals in the row direction. Furthermore, among the first signal pads 311-1, any one second signal pad 312-1 and any other second signal pad 312-1 are arranged so that their positions are offset in the column direction by less than the length of the first signal pads 311-1 in the column direction. In the image sensor 403 of this example, among the second signal pads 312-1, a pair of second signal pads 312-1 adjacent in the row direction are arranged so that their positions are offset in the column direction by less than the length of the first signal pads 311-1 in the column direction. In other words, the first signal pad 311-1 is likely to come into contact with at least one of a pair of second signal pads 312-1 adjacent in the row direction.

[0099] In this variant, the multiple first signal pads 311-1 are arranged at an angle with respect to the row direction so that as they move toward the second side opposite the first side in the row direction, they gradually move toward the second side opposite the first side in the column direction.

[0100] In the imaging element 403 of the third modified example configured as described above, for example, when there is no misalignment of the second substrate 200 relative to the first substrate 100 in the row and column directions, it is assumed that the multiple first signal pads 311-1 of the first substrate 100 are joined to the multiple second signal pads 312-1 of the second substrate 200, as shown in FIG. 19. Even if the first substrate 100 is shifted only in the row direction relative to the second substrate 200 from the state shown in FIG. 19, as shown in FIG. 20, some of the multiple second signal pads 312-1 and some of the multiple first signal pads 311-1 are bonded to each other.

[0101] Even if the first substrate 100 shifts only in the column direction relative to the second substrate 200 from the state shown in FIG. 19, as shown in FIG. 21, some of the multiple second signal pads 312-1 and some of the multiple first signal pads 311-1 are bonded to each other. Even if the first substrate 100 shifts in the row and column directions relative to the second substrate 200 from the state shown in Figure 19, for example, as shown in Figure 22, some of the multiple second signal pads 312-1 and some of the multiple first signal pads 311-1 are joined.

[0102] In the imaging element 403 of the third modified example configured as described above, even if the first substrate 100 is misaligned in the column direction relative to the second substrate 200, the multiple second signal pads 312-1 and the multiple first signal pads 311-1 can be more reliably connected. The positions of the multiple first signal pads 311-1 in the column direction may be equal to each other.

[0103] In the imaging element 403 of the third modified example, a plurality of second signal pads 312-1 may be arranged as shown in FIG. In this modification, some of the second signal pads 312-1 are arranged at an angle with respect to the row direction so as to gradually move toward the second column side as they move toward the second row side, while the remaining second signal pads 312-1 are arranged at an angle with respect to the row direction so as to gradually move toward the first column side as they move toward the second row side. It should be noted that the first pad is the first signal pad 311-1 and the second pad is the second signal pad 312-1. However, the first pad may be the second signal pad 312-1 and the second pad may be the first signal pad 311-1.

[0104] In an image sensor 404 of the fourth modified example shown in FIG. 24, one reference potential junction 330 is provided for a plurality of first signal conversion units 40-1 adjacent to each other in the row direction. More specifically, in the imaging element 404, one reference potential junction 330 is provided for a pair of first signal conversion units 40-1 and a pair of second signal conversion units 40-2 adjacent to each other in the row direction. The reference potential junction 330 is disposed between the signal conversion units 40-1 and 40-2 of a pair of first signal conversion units 40-1 that are disposed at the end on the first side in the row direction. The reference potential junction 330 is disposed between the odd-numbered (hereinafter simply referred to as odd-numbered) signal conversion units 40-1 and 40-2 counting from the end on the first side in the row direction. That is, the reference potential junction 330 is disposed for every other pair of signal conversion units 40-1 and 40-2.

[0105] The imaging element 404 has a plurality of first signal connectors 310-1 for the even-numbered (hereinafter simply referred to as even-numbered) first signal converters 40-1 counting from the first end in the row direction, and a plurality of second signal connectors 310-2 for the even-numbered second signal converters 40-2. The plurality of first signal connectors 310-1 are arranged at intervals from one another in the column direction, and the plurality of second signal connectors 310-2 are arranged at intervals from one another in the column direction. The even-numbered signal conversion units 40-1 and 40-2 are connected to the reference potential junction unit 330 via wiring (not shown).

[0106] In the image sensor 404 of the fourth modified example configured as described above, one reference potential junction 330 is provided for each pair of signal conversion units 40-1, 40-2 adjacent to each other in the row direction. This makes it possible to ensure a space between the signal conversion units 40-1, 40-2 for arranging, for example, a plurality of signal junction units 310-1, 310-2. A plurality of signal junctions 310-1 and 310-2 are arranged between pairs of even-numbered signal conversion units 40-1 and 40-2 where no reference potential junction 330 is arranged. This makes it possible to ensure that even if the first signal pad 311-1 is misaligned with respect to the second signal pad 312-1 in the column direction, a portion where the pads 311-1 and 312-1 face each other remains. Therefore, the pads 311-1 and 312-1 can be reliably connected by the signal connection member, improving the bonding yield of the pads 311-1 and 312-1. Furthermore, by arranging the reference potential junctions 330 at equal intervals in the row direction, the impedances of the wirings connected to the reference potential junctions 330 can be made equal to each other.

[0107] In addition, the image pickup element 404 of the fourth modified example may have a plurality of signal junctions 310-1, 310-2 for the odd-numbered signal conversion units 40-1, 40-2, and a reference potential junction 330 may be disposed between the even-numbered signal conversion units 40-1, 40-2, as in the image pickup element 405 of the fifth modified example shown in FIG. The reference potential junction 330 may be disposed for every two or more pairs of signal conversion units 40-1 and 40-2.

[0108] 26, the image sensor 406 of the sixth modification example has a reference potential junction 330 disposed between one of the plurality of first signal conversion units 40-1 and one of the plurality of second signal conversion units 40-2. More specifically, the reference potential junction 330 is disposed between the pair of signal conversion units 40-1 and 40-2 at the end on the first side in the row direction. Between the signal conversion units 40-1 and 40-2 where the reference potential junction 330 is not arranged, a plurality of first signal junctions 310-1 and a plurality of second signal junctions 310-2 are arranged.

[0109] The imaging element 406 of the sixth modified example configured as described above can achieve the same effect as the imaging element 404 of the fourth modified example between the signal conversion units 40-1 and 40-2, which do not have the reference potential junction 330 disposed therebetween. The position of the pair of signal conversion units 40-1 and 40-2 without the reference potential junction 330 disposed therebetween is not particularly limited.

[0110] 27, when the image sensor 407 is viewed in the Z-axis direction, the reference potential junction 330 is disposed at a position on the junction surface 300 that does not overlap with the first signal conversion unit 40-1 in the row direction. In this example, the reference potential junction 330 is disposed at a position on the junction surface 300 that overlaps with the pixel driving unit 20. The reference potential junction 330 is disposed at a position shifted in the column direction from a position between the pair of signal conversion units 40-1 and 40-2. The reference potential junction 330 is connected to the reference potential wiring 240. The reference potential wiring 240 extends in the row direction between the first signal conversion unit 40-1 and the second signal conversion unit 40-2. No reference potential junction 330 is arranged between pairs of signal conversion units 40-1 and 40-2, but instead a plurality of first signal junctions 310-1 and a plurality of second signal junctions 310-2 are arranged between the pairs of signal conversion units 40-1 and 40-2. The first signal processing blocks 220-1 are arranged in a row direction. The first signal processing blocks 220-1 adjacent to each other in the row direction are connected to each other by a reference potential wiring 240.

[0111] In the image sensor 407 of the seventh modified example configured as described above, when the image sensor 407 is viewed in the Z-axis direction, the reference potential junction 330 is disposed at a position on the junction surface 300 in the row direction so as not to overlap with the first signal conversion unit 40-1. This makes it possible to ensure a space between the signal conversion units 40-1 and 40-2 in which, for example, a plurality of signal junction units 310-1 and 310-2 can be disposed. Furthermore, the bonding yield of both pads 311-1 and 312-1 can be improved.

[0112] As in the image pickup element 408 of the eighth modified example shown in FIG. 28, in the image pickup element 407 of the seventh modified example, when the image pickup element 408 is viewed in the Z-axis direction, the reference potential junction 330 may be positioned on the junction surface 300 at a position that overlaps with the first signal conversion unit 40-1. The imaging element 408 of the eighth modified example configured as above can achieve the same effects as the imaging element 407 of the seventh modified example.

[0113] In the imaging element 409 of the ninth modified example shown in Figure 29, the positions of the first signal junction 310-1 and the first control junction 325-1, which are arranged at the end on the first side in the row direction and the end on the first side in the column direction, are shifted compared to the imaging element 400 of this embodiment. Specifically, when the imaging element 409 is viewed in the Z-axis direction, the first control junction 325-1 located at the end on the first side in the column direction is the second from the end on the first side in the row direction and is located at a position overlapping with the first pixel 112-1 at the end on the first side in the column direction. In this example, when the imaging element 409 is viewed in the Z-axis direction, the first signal junction 310-1, which is second from the end on the first side in the row direction, is positioned so as to overlap the first pixel 112-1, which is second from the end on the first side in the column direction and second from the end on the first side in the row direction.

[0114] It is preferable that the shift length of the positions of the joints 310-1 and 325-1 is small, that is, the shift length is preferably limited to approximately the length of one first pixel 112-1 in the row direction and the length of one first pixel 112-1 in the column direction.

[0115] For example, if the first pixel 112-1 is made smaller, when the imaging element 409 is viewed in the Z-axis direction, only one joint can be arranged at a position overlapping one first pixel 112-1. Even in such a case, the imaging element 409 of the ninth modified example can be configured so that only the first signal junction 310-1 or the first control junction 325-1 is arranged at a position overlapping one first pixel 112-1. When the imaging element 409 is viewed in the Z-axis direction, instead of positioning the first control junction 325-1 arranged at the end of the first side in the column direction at a position overlapping with the first pixel 112-1 that is second from the end of the first side in the row direction, the first signal junction 310-1 arranged at the end of the first side in the row direction may be positioned at a position that is second from the end of the first side in the column direction and overlaps with the first pixel 112-1 that is at the end of the first side in the row direction.

[0116] Although one embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and configuration changes, combinations, deletions, etc. are also included within the scope that does not deviate from the gist of the present invention. For example, in the above-described embodiment and modified examples, the imaging device does not need to include the reference potential junctions 315-1, 315-2, and 330 and the load current sources 221-1 and 221-2. [Explanation of symbols]

[0117] 40-1 First signal conversion unit 40-2 Second signal conversion unit 40-3 Third signal conversion unit 100 First substrate 112-1 1st pixel 112a Photosensitive surface 120-1 1st pixel block 120-2 2nd pixel block 120-3 3rd pixel block 200 Second board 220-1 First signal processing block 220-2 Second signal processing block 220-3 3rd signal processing block 300 Joint surface 310-1 First signal junction 310-2 Second signal junction 310-3 Third Signal Junction 311-1 1st signal pad (1st pad) 312-1 Second signal pad (second pad) 325-1 First Control Junction 330 Reference potential junction 400,401,402,403,404,405,406,407,408,409 Image sensor 500 Imaging device L1,L2 interval

Claims

[Claim 1] a first substrate including a first pixel block having a first pixel, a second pixel block having a second pixel, and a third pixel block having a third pixel, the first pixel block, the second pixel block, and the third pixel block being arranged side by side in a column direction; a second substrate laminated on the first substrate, the second substrate having a first signal processing block including a first signal conversion unit that processes signals from the first pixels and a first pixel driving unit that controls the first pixels, a second signal processing block including a second signal conversion unit that processes signals from the second pixels and a second pixel driving unit that controls the second pixels, and a third signal processing block including a third signal conversion unit that processes signals from the third pixels and a third pixel driving unit that controls the third pixels; a first signal joining unit that outputs a signal from the first pixel to the first signal conversion unit and joins the first substrate and the second substrate; a second signal joining unit that outputs a signal from the second pixel to the second signal conversion unit and joins the first substrate and the second substrate; a third signal joining unit that outputs a signal from the third pixel to the third signal conversion unit and joins the first substrate and the second substrate; a first control joint that outputs a signal from the first pixel driving unit to the first pixel and joins the first substrate and the second substrate; a second control joint that outputs a signal from the second pixel driving unit to the second pixel and joins the first substrate and the second substrate; a third control joint unit that outputs a signal from the third pixel driving unit to the third pixel and joins the first substrate and the second substrate; Equipped with the second pixel block is provided between the first pixel block and the third pixel block in the column direction, a distance between the first signal junction and the second signal junction is narrower than a distance between the second signal junction and the third signal junction; the first signal processing block includes a plurality of the first signal conversion units arranged in a row direction; a plurality of the first signal junction portions are provided; In the plurality of first signal conversion units, of a pair of the first signal conversion units adjacent to each other in the row direction, the first signal connection unit for one of the first signal conversion units and the first signal connection unit for the other first signal conversion unit are arranged with positions shifted in the column direction. Image sensor.

Images