Semiconductor device and method of manufacturing the same

Abstract

To prevent a vibration film 10c from being damaged by collision.SOLUTION: A semiconductor element 1 includes a first semiconductor substrate 10 having a cantilever-like vibration film 10c and a first sidewall 10c surrounding a lower surface of the vibration film 10a, the first sidewall 10a supporting a base of the vibration film 10c, and a second semiconductor substrate 30 stacked on the first semiconductor substrate 10. And a second semiconductor wafer 30 having a second sidewall 10c surrounding the upper surface of the vibration film 30a and a first stopper 10c projecting from the second sidewall 30a so as to face the upper surface of the vibration film 10c and extending in parallel with the vibration film 10c in a direction from the base of the vibration film 10c toward the tip to limit the vibration range of the vibration film 30c.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Conventionally, micro electromechanical system (MEMS) technology has been provided, which uses semiconductor manufacturing technology to fabricate mechanical structures on semiconductor substrates such as silicon. An example of a MEMS device that applies MEMS technology is a semiconductor device in which a transducer that drives a cantilever-shaped diaphragm with a piezoelectric body and a subframe that forms a frame surrounding the diaphragm are each formed from a silicon substrate, and these are laminated and bonded together (see Patent Document 1).

[0003] In such semiconductor devices, a stopper is sometimes provided to limit the range of movement of the tip of the cantilever-shaped diaphragm to prevent the diaphragm from being damaged by an excessive increase in amplitude (see Patent Document 1). Also, the vibration of the diaphragm is sometimes suppressed by providing a micro-hole or orifice that covers the top of the diaphragm and suppresses the flow of air (see the same document). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2021 / 157486

[0005] [overview] The tip of the cantilevered diaphragm can sometimes collide forcefully with the structure surrounding the diaphragm, such as a stopper.

[0006] The present disclosure has been proposed in view of the above-described circumstances, and aims to provide a semiconductor device in which the vibration membrane is not damaged by a collision, and a method for manufacturing the same.

[0007] In order to solve the above-mentioned problems, the semiconductor device of the present disclosure includes a cantilever-shaped vibration membrane and a first side wall surrounding the lower surface of the vibration membrane, the first side wall being a first semiconductor substrate supporting the base of the vibration membrane, and a second semiconductor substrate stacked on the first semiconductor substrate, the second semiconductor substrate including a second side wall surrounding the upper surface of the vibration membrane and a first stopper protruding from the second side wall to face the vibration membrane and extending parallel to the vibration membrane in a direction from the base to the tip of the vibration membrane to limit the vibration range of the vibration membrane.

[0008] The method for manufacturing a semiconductor device disclosed herein includes the steps of stacking a piezoelectric element, which has a piezoelectric film sandwiched between a pair of electrode plates, on a first semiconductor substrate; forming, on a second semiconductor substrate, a frame-shaped second side wall and a first stopper protruding inward from the second side wall; stacking the second semiconductor substrate on the first semiconductor substrate so that the piezoelectric element is surrounded by the second side wall; and forming, on the first semiconductor substrate, a cantilever-shaped vibration membrane on which the piezoelectric element is stacked, and a first side wall that surrounds the vibration membrane and supports the base of the vibration membrane, wherein the first stopper faces the vibration membrane and extends parallel to the direction from the base of the vibration membrane to the tip. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of the semiconductor device of the present embodiment. [Figure 2] FIG. 2 is a front view of the semiconductor device of the present embodiment. [Figure 3] FIG. 3 is a cross-sectional view of the semiconductor device of this embodiment. [Figure 4] FIG. 4 is a plan view of the semiconductor device of the first modification. [Figure 5] FIG. 5 is a cross-sectional view of the semiconductor device of the first modification. [Figure 6] FIG. 6 is a cross-sectional view of a semiconductor device according to the second modification. [Figure 7A] FIG. 7A is a process diagram of a method for manufacturing a first semiconductor substrate. [Figure 7B] FIG. 7B is a process diagram of a method for manufacturing a first semiconductor substrate. [Figure 7C]FIG. 7C is a process diagram of a method for manufacturing a first semiconductor substrate. [Figure 7D] FIG. 7D is a process diagram of a method for manufacturing a first semiconductor substrate. [Figure 7E] FIG. 7E is a process diagram of a method for manufacturing a first semiconductor substrate. [Figure 7F] FIG. 7F is a process diagram of a method for manufacturing a first semiconductor substrate. [Figure 7G] FIG. 7G is a process diagram of a method for manufacturing a first semiconductor substrate. [Figure 8] FIG. 8 is a plan view of the first semiconductor substrate shown in FIG. 7G. [Figure 9A] FIG. 9A is a process diagram of a method for manufacturing a second semiconductor substrate. [Figure 9B] FIG. 9B is a process diagram of a method for manufacturing a second semiconductor substrate. [Figure 9C] FIG. 9C is a process diagram of a method for manufacturing a second semiconductor substrate. [Figure 9D] FIG. 9D is a process diagram of a method for manufacturing a second semiconductor substrate. [Figure 9E] FIG. 9E is a process diagram of a method for manufacturing a second semiconductor substrate. [Figure 10] FIG. 10 is a plan view of the second semiconductor substrate shown in FIG. 9E. [Figure 11] FIG. 11 is a process diagram of a method for manufacturing a semiconductor device. [Figure 12A] FIG. 12A is a cross-sectional view of a main part of a semiconductor device according to an embodiment. [Figure 12B] FIG. 12B is a graph showing the displacement of the vibrating membrane of the semiconductor device of the example. [Figure 12C] FIG. 12C is a graph showing the relationship between frequency and displacement of the vibrating membrane in the semiconductor device of the example. [Figure 12D] FIG. 12D is a cross-sectional view of a main part of the semiconductor device of the reference example.

[0010] [Detailed explanation] Hereinafter, embodiments of a semiconductor device and a manufacturing method thereof according to the present disclosure will be described in detail with reference to the drawings. The embodiments are comprehensive or specific examples. The numerical values, shapes, materials, components, and the installation positions and connection forms of the components shown in the embodiments are merely examples and are not intended to limit the scope of the present disclosure. Furthermore, among the components in the following embodiments, components that are not recited in the independent claims that represent the highest concepts will be described as optional components. Furthermore, the dimensional proportions in the drawings are exaggerated for the sake of explanation and may differ from the actual proportions. Furthermore, the following embodiments and their variations may include similar components, and similar components will be assigned common reference numerals, and redundant explanations will be omitted.

[0011] FIG. 1 is a plan view of a semiconductor device 1 according to the present embodiment, and FIG. 2 is a front view. FIG. 3 is a cross-sectional view of the semiconductor device 1 taken along the line III-III shown in the plan view of FIG. 1. The semiconductor device 1 according to the present embodiment is based on MEMS technology using semiconductor manufacturing techniques, and is configured by bonding a first semiconductor substrate 10 and a second semiconductor substrate 30 together with an adhesive layer 41. In the semiconductor device 1, the first semiconductor substrate 10 forms a transducer that converts electrical signals into sound waves and vice versa using a diaphragm 10c formed by stacking piezoelectric elements. The second semiconductor substrate 30 forms a subframe that surrounds the diaphragm 10c of the transducer in a frame-like shape, protecting the diaphragm 10c and improving the rigidity of the semiconductor device 1. Furthermore, it forms a subframe that prevents air leakage in the direction in which the diaphragm 10c extends, thereby improving the characteristics of the sound generated by the diaphragm 10c.

[0012] In the first semiconductor substrate 10, a first semiconductor layer 11, a first insulator layer 12, and a second semiconductor layer 13 are stacked in this order. The first semiconductor layer 11 and the second semiconductor layer 13 may be made of silicon (Si). The first insulator layer 12 may be made of silicon dioxide (SiO2). The stack of the first semiconductor layer 11, the first insulator layer 12, and the second semiconductor layer 13 may constitute an SOI (silicon on insulator) wafer, and the first insulator layer 12 may constitute a buried oxide (BOX) layer.

[0013] The first semiconductor substrate 10 has a first recess 10b formed from the lower surface of the first semiconductor layer 11 to the lower surface of the second semiconductor layer 13 so that the second semiconductor layer 13 forms a vibrating membrane 10c that vibrates in the thickness direction. The first semiconductor layer 11 and the first insulator layer 12 have a frame-shaped first sidewall 10a formed along the outer periphery of the first semiconductor substrate 10 so as to surround the lower surface of the vibrating membrane 10c and the first recess 10b.

[0014] In the second semiconductor layer 13, a through groove 10d is formed around the periphery of the vibrating membrane 10c that contacts the first side wall 10a, leaving the base of the vibrating membrane 10c supported by the first side wall 10a. The vibrating membrane 10c forms a cantilever with the base supported by the first side wall 10a as a fixed end and the tip distal to the base as a free end.

[0015] In the first semiconductor substrate 10, a second insulator layer 14, a first protective layer 15, and a second protective layer 16 are stacked in this order on a second semiconductor layer 13. In the region of the second semiconductor layer 13 where the vibrating membrane 10c is formed, a laminate is interposed between the second insulator layer 14 and the first protective layer 15, in which a first metal layer 17, a piezoelectric layer 18, and a second metal layer 19 are stacked in this order. This laminate sandwiches the piezoelectric layer 18 between a pair of electrode plates made of the first metal layer 17 and the second metal layer 19, constituting a piezoelectric element that bends the piezoelectric layer 18 in response to a voltage applied between the electrode plates, thereby driving the vibrating membrane 10c to vibrate. Between the first protective layer 15 and the second protective layer 16, electrodes 21 are interposed, connected to the first metal layer 17 and the second metal layer 19, respectively. The electrodes 21 are electrically connected to a pair of electrode pads 22 exposed on the second protective layer 16 by wiring (not shown).

[0016] The second insulating layer 14 may be formed by sequentially stacking silicon dioxide and aluminum oxide (Al2O3). The first protective layer 15 and the second protective layer 16 may be formed by sequentially stacking aluminum oxide and silicon dioxide. Here, SiO2 serves as an interlayer insulating film, and Al2O3 serves as a hydrogen barrier film. The first metal layer 17 may be formed by sequentially stacking titanium oxide (TiO2) and platinum (Pt). The titanium oxide is interposed between the upper platinum layer and the lower second insulating layer 14 to ensure close contact. The piezoelectric layer 18 may be formed by zinc zirconate titanate (PZT). The second metal layer 19 may be formed by sequentially stacking iridium oxide (IrO2) and iridium (Ir).

[0017] The second semiconductor substrate 30 is stacked on the first semiconductor substrate 10, and they are bonded to each other by an adhesive layer 41 interposed therebetween. A frame-shaped second sidewall 30a is formed on the second semiconductor substrate 30 along the outer periphery of the first semiconductor substrate 10, surrounding the vibration membrane 10c of the first semiconductor substrate 10. The second sidewall 30a, together with the vibration membrane 10c, forms an upwardly open space 30b surrounding the vibration membrane 10c. The second semiconductor substrate 30 may be made of silicon.

[0018] The second semiconductor substrate 30 further includes a first stopper 30c that protrudes from the second sidewall 30a to face the top surface of the diaphragm 10c and extends parallel to the diaphragm 10c from its base to its tip, limiting the vibration range of the diaphragm 10c. The first stopper 30c has a predetermined gap between it and the top surface of the diaphragm 10c and has a length that does not reach the tip of the diaphragm 10c. The first stopper 30c may have a length that is less than half the length from the base to the tip of the diaphragm 10c, for example. The length of the first stopper 30c may be less than one-third or one-quarter of the length from the base to the tip of the diaphragm 10c. The first stopper 30c covers a portion of the opening formed by the upwardly open space 30b surrounded by the diaphragm 10c and the second sidewall 30a.

[0019] In the second semiconductor substrate 30, which is rectangular in plan view, notches 30f are formed at a pair of opposing corners of the short side on the first stopper 30c side. The notches 30f extend in the depth direction along the edge of the second semiconductor substrate 30, so that the electrode pads 22 formed on the second protective layer 16 of the first semiconductor substrate 10 are exposed.

[0020] In the semiconductor device 1 of this embodiment, the first stopper 30c that limits the vibration range of the vibrating membrane 10c protrudes from the second sidewall 30a so as to face the upper surface of the vibrating membrane 10c, extends parallel to the direction from the base to the tip of the vibrating membrane 10c, and has a predetermined gap width between it and the top of the vibrating membrane 10c. Therefore, when the amplitude of the vibrating membrane 10c becomes large, the vibration range of the vibrating membrane 10c is limited by the first stopper 30c, preventing damage to the vibrating membrane 10c due to an excessively large amplitude.

[0021] The first stopper 30c has a length that does not reach the tip of the vibrating membrane 10c. The first stopper 30c may have a length that does not reach half the length from the base to the tip. In this embodiment, the first stopper 30c limits the vibration range of the vibrating membrane 10c at a position that does not reach the tip of the vibrating membrane 10c, thereby preventing the vibration amplitude of the vibrating membrane 10c from excessively increasing and causing damage. At this position, the velocity of the vibrating membrane 10c is slower than that of the tip of the vibrating membrane 10c. Therefore, even when the vibration of the vibrating membrane 10c reaches the vibration range limited by the first stopper 30c and touches the first stopper 30c, the impact applied to the vibrating membrane 10c from the first stopper 30c is small, thereby suppressing damage that may occur to the vibrating membrane 10c due to the impact.

[0022] FIG. 4 is a plan view of the semiconductor device 2 of Modification 1. FIG. 5 is a cross-sectional view of the semiconductor device 2 taken along the cutting plane VV in the plan view of FIG. 4. The semiconductor device 2 of Modification 1 differs from the semiconductor device 1 shown in FIGS. 1 to 3 in that the upwardly open space 30b, which is formed by the vibration membrane 10c and the second sidewall 30a and is partially covered by the first stopper 30c, is closed by a sealing portion 30d having a through-hole 30e that suppresses airflow. The other configuration of the semiconductor device 2 of Modification 1 is similar to that of the semiconductor device 1, and therefore, the corresponding components will be designated by the same reference numerals to indicate their correspondence.

[0023] In semiconductor device 2 of variation 1, sealing portion 30d protruding from second side wall 30a extends to face the upper surface of vibrating membrane 10c, closing space 30b formed by vibrating membrane 10c and second side wall 30a and open upward except for a portion covered by first stopper 30c. A gap width larger than the gap width between first stopper 30c and the upper surface of vibrating membrane 10c is secured between sealing portion 30d and the upper surface of vibrating membrane 10c to prevent vibrating membrane 10c from colliding with sealing portion 30d.

[0024] The sealing portion 30d is provided with a through-hole 30e that allows air to pass through. The through-hole 30e is formed as a micropore or orifice that restricts the flow of air passing through. The volume and pressure within the closed space 30b formed on the upper surface of the vibrating membrane 10c fluctuate in response to the vibration of the vibrating membrane 10c, and air flows in and out through the through-hole 30e, which connects the space 30b to the outside. However, the through-hole 30e is configured to restrict the flow of air passing through. This restricts the pressure fluctuations in the space 30b, and also restricts the vibration of the vibrating membrane 10c.

[0025] In the semiconductor device 2 of the first modification, not only is the vibration range of the vibrating membrane 10c limited by the first stopper 30c, but the vibration is also suppressed by the sealing portion 30d having the through-hole 30e. The vibration of the vibrating membrane 10c is suppressed by the sealing portion 30d regardless of the amplitude, preventing damage to the vibrating membrane 10c due to excessively large amplitude of the vibrating membrane 10c. Furthermore, because the vibration of the vibrating membrane 10c is suppressed regardless of the amplitude, it is also prevented from reaching the vibration range limited by the first stopper 30c. This reduces the occurrence of damage that could occur due to the impact applied by the first stopper 30c when the amplitude of the vibrating membrane 10c reaches the vibration range.

[0026] 6 is a cross-sectional view of semiconductor device 3 of modified example 2. Semiconductor device 3 of modified example 2 differs from semiconductor device 1 shown in FIGS. 1 to 3 in that second stopper 10e is further formed on first semiconductor substrate 10, protruding from first side wall 10a so as to face the underside of vibrating membrane 10c, and extending parallel to the direction from the base to the tip of vibrating membrane 10c to limit the vibration range of vibrating membrane 10c. Other configurations of semiconductor device 3 of modified example 2 are similar to those of semiconductor device 1, and therefore corresponding components will be assigned common reference numerals to indicate correspondences.

[0027] The second stopper 10e has a predetermined gap width between itself and the lower surface of the vibrating membrane 10c and a length that does not reach the tip of the vibrating membrane 10c. The second stopper 10e may have a length that is less than half the length from the base to the tip of the vibrating membrane 10c. The length of the second stopper 10e may be less than one-third or one-quarter of the length from the base to the tip of the vibrating membrane 10c. The gap width formed between the second stopper 10e and the lower surface of the vibrating membrane 10c may be smaller than the gap width formed between the first stopper 30c and the upper surface of the vibrating membrane 10c. The length of the second stopper 10e in the direction from the base to the tip of the vibrating membrane 10c may be shorter than the length of the first stopper 30c. The second stopper 10e covers a portion of the opening formed by the downwardly open first recess 10b surrounded by the vibrating membrane 10c and the first sidewall 10a. The second stopper 10e is made of the first semiconductor layer 11 of the first semiconductor substrate 10, and the gap between the second stopper 10e and the vibration membrane 10c is formed by removing the first insulating layer 12.

[0028] In the semiconductor device 3 of the second modification, the vibration range of the vibrating membrane 10c is limited not only by the first stopper 30c facing the upper surface of the vibrating membrane 10c, but also by the second stopper 10e facing the lower surface of the vibrating membrane 10c. Therefore, the vibration range of the vibrating membrane 10c can be limited not only in the direction of the upper surface of the vibrating membrane 10c, but also in the direction of the lower surface of the vibrating membrane 10c. Furthermore, in the semiconductor device 3, the gap between the second stopper 10e and the vibrating membrane 10c can be easily formed by removing the first insulator layer 12.

[0029] It should be noted that the semiconductor device of the present disclosure is not limited to the configuration described above. For example, the semiconductor device 1 shown in Figures 1 to 3 includes the first stopper 30c, and the semiconductor device 3 of Modification 2 includes the first stopper 30c and the second stopper 10e, but it may be configured to include only the second stopper 10e and not the first stopper 30c. Furthermore, the semiconductor device 2 of Modification 1 includes the first stopper 30c and the sealing portion 30d, but it may also be configured to include the second stopper 10e.

[0030] Next, a method for manufacturing a semiconductor device according to the present disclosure will be described, taking as an example the semiconductor device 2 of Modification 1 shown in FIGS.

[0031] The process of fabricating a first semiconductor substrate 10 will be described with reference to Figures 7A to 7G. As shown in Figure 7A, a third insulator layer 25 is laminated on the bottom surface of a first semiconductor layer 11, and a first insulator layer 12, a second semiconductor layer 13, a second insulator layer 14, a first metal layer 17, a piezoelectric layer 18, and a second metal layer 19 are laminated in this order on the top surface of the first semiconductor layer. An SOI wafer may be used for the laminate consisting of the first semiconductor layer 11, the first insulator layer 12, and the second semiconductor layer 13. In the SOI wafer, the first insulator layer 12 forms a BOX layer.

[0032] As shown in FIG. 7B, unnecessary portions are removed by etching so that the first metal layer 17, piezoelectric layer 18, and second metal layer 19, which are stacked in this order on the second insulator layer 14, are formed into the appropriate shape. As shown in FIG. 7C, a first protective layer 15 is formed to cover the second insulator layer 14, which is formed by stacking the first metal layer 17, piezoelectric layer 18, and second metal layer 19, which have been etched into the appropriate shape. As shown in FIG. 7D, a first opening 15a is formed in the first protective layer 15 so that electrodes can be connected to the first metal layer 17 and the second metal layer 19, respectively. In addition, a second opening 15b is formed in the first protective layer 15 at a position where the through groove 10d is to be formed in the first semiconductor layer 11.

[0033] As shown in FIG. 7E, an electrode 21 and a wiring (not shown) connected to the electrode 21 are formed. The electrode 21 and the wiring may be formed by laminating an aluminum (Al) copper (Cu) alloy and titanium nitride (TiN). TiN is a barrier metal. As shown in FIG. 7F, the first protective layer 15 in which the electrode 21 and the second opening 15b are formed is covered with a second protective layer 16, and then the electrode pad 22 (see FIG. 4) and the second protective layer 16 covering the second opening 15b are removed by etching.

[0034] 7G, second opening 15b is etched down to the top surface of first semiconductor layer 11, leaving the base and forming groove 29 that surrounds vibrating membrane 10c. The structure formed in this manner differs from first semiconductor substrate 10 in semiconductor device 2 in that first recess 10b is absent and the bottom surface of first semiconductor layer 11 is covered with third insulator layer 25, but the rest of the structure is similar to first semiconductor substrate 10. Hereinafter, for convenience, this structure will be referred to as first semiconductor substrate 10.

[0035] Fig. 8 is a plan view of first semiconductor substrate 10 shown in the process diagram of Fig. 7G. The process diagram of Fig. 7G corresponds to the cross section shown by section line VIIG-VIIG in Fig. 8. A groove 29 is formed on the top surface of the first structure shown in Fig. 8, surrounding vibration membrane 10c, leaving the base. First metal layer 17 and second metal layer 19 (not shown) stacked on vibration membrane 10c are each connected to electrode pads 22 via wiring 23.

[0036] The process of fabricating a second semiconductor substrate 30 will be described with reference to FIGS. 9A to 9E. As shown in FIG. 9A, a fourth insulator layer 31 and a fifth insulator layer 32 are stacked to cover the bottom and top surfaces of the second semiconductor substrate 30, respectively. The second semiconductor substrate 30 may be made of Si, and the fourth insulator layer 31 and the fifth insulator layer 32 may be made of SiO2. In this case, the SiO2 of the fourth insulator layer 31 and the fifth insulator layer 32 may be formed by heating the second semiconductor substrate 30 made of Si to oxidize the surface. Then, the fifth insulator layer 32 covering the top surface of the second semiconductor substrate 30 is etched to form second recesses 30g in a predetermined pattern that open into the fifth insulator layer 32 and reach a predetermined depth from the top surface of the second semiconductor substrate 30. As shown in FIG. 9B, the fourth insulator layer 31 covering the bottom surface of the second semiconductor substrate 30 is also etched to form openings 31a in the fourth insulator layer 31 in a predetermined pattern.

[0037] 9C , a temporary wafer 51 is attached to the fifth insulator layer 32 covering the top surface 31b of the second semiconductor substrate 30, with an adhesive layer 52 such as tape interposed therebetween. Then, a resist 53 is laminated on the fourth insulator layer 31 covering the bottom surface of the second semiconductor substrate 30, and the second semiconductor substrate 30 is etched in the portion of the fourth insulator layer 31 where the resist 53 is not formed and where the opening 31a is formed, to form a third recess 30h reaching a predetermined height in the bottom surface of the second semiconductor substrate 30. By forming the third recess 30h, the second recess 30g formed in the top surface of the second semiconductor substrate 30 communicates with the third recess 30h formed in the bottom surface of the second semiconductor substrate 30, becoming a through-hole 30e.

[0038] As shown in FIG. 9D, the resist 53 is removed from the bottom surface of the second semiconductor substrate 30, and the second semiconductor substrate 30 is etched using the fourth insulator layer 31 as a mask to form a fourth recess 30i adjacent to the third recess 30h but not reaching the height of the third recess 30h. The third recess 30h and the fourth recess 30i are connected to form a space 30b. The frame-like structure surrounding the space 30b forms a second sidewall 30a. Then, as shown in FIG. 9E, the fourth insulator layer 31, the adhesive layer 52 stacked on the fifth insulator layer 32 covering the top surface of the second semiconductor substrate 30, and the temporary wafer 51 are removed.

[0039] FIG. 10 is a plan view of the second semiconductor substrate 30 shown in the process diagram of FIG. 9E. The process diagram of FIG. 9E corresponds to a cross section taken along the cutting line IXE-IXE shown in FIG. 10. The central portion of the top surface of the second semiconductor substrate 30 is covered with a first stopper 30c and a sealing portion 30d, and a through-hole 30e is provided in the sealing portion 30d. In addition, notches 30f are formed in a pair of opposing corners of the short side of the rectangular top surface on the first stopper 30c side in plan view. The notches are formed by etching in the process shown in FIGS. 9A and 9C.

[0040] 11 is a process diagram of a method for manufacturing the semiconductor device 2. The second semiconductor substrate 30 is stacked on the first semiconductor substrate 10 so that the vibrating membrane 10c to be formed on the top surface of the first semiconductor substrate 10 shown in the process diagram of FIG. 7G is surrounded by the second sidewall 30a of the second semiconductor substrate 30 shown in the process diagram of FIG. 9E. The first semiconductor substrate 10 and the second semiconductor substrate 30 are bonded to each other by an adhesive layer 41 interposed therebetween.

[0041] Next, etching is performed to form a predetermined pattern of first recesses 10b that penetrate the third insulator layer 25, penetrate the first semiconductor layer 11 and the first insulator layer 12, and reach the underside of the second semiconductor layer 13. The third insulator layer 25 is then removed. By forming the first recesses 10b, the grooves 29 communicate with the first recesses 10b to form through-grooves 10d, and a frame-shaped first sidewall 10a is formed along the communicating grooves, surrounding the first recesses 10b. The second semiconductor layer 13 directly above the first recesses 10b, surrounded by the first sidewall 10a, forms a cantilever-shaped diaphragm 10c, with a fixed end at its base supported by the first sidewall 10a and a free end at its tip distal to the base. A piezoelectric element is stacked on the diaphragm 10c, which is formed by sequentially stacking a first metal layer 17, a piezoelectric layer 18, and a second metal layer 19. This series of steps results in the fabrication of the semiconductor device 2 of Variation 1, as shown in FIG. 5 .

[0042] In the semiconductor device 2 of Variation 1 fabricated by the above-described manufacturing method, when the amplitude of the vibrating membrane 10c increases, the vibration range of the vibrating membrane 10c is limited by the first stopper 30c, preventing damage to the vibrating membrane 10c due to excessively large amplitude. Furthermore, the vibration of the vibrating membrane 10c is suppressed regardless of the amplitude by the sealing portion 30d with the through-hole 30e, preventing the amplitude from increasing excessively. Furthermore, the amplitude of the vibrating membrane 10c is prevented from reaching the vibration range limited by the first stopper 30c, reducing the possibility of damage to the vibrating membrane 10c due to an impact applied to the vibrating membrane 10c from the first stopper 30c.

[0043] Although the manufacturing method has been described here using the semiconductor device 2 of Modification 1 as an example, the manufacturing method of the semiconductor device of this embodiment is not limited to this and can be similarly applied to the semiconductor devices shown in Figures 1 to 3, the semiconductor device 3 of Modification 2 shown in Figure 6, etc.

[0044] Next, an embodiment of the semiconductor device of the present disclosure will be described, taking the semiconductor device 1 shown in FIGS.

[0045] FIG. 12A is a cross-sectional view of a main portion of the semiconductor device 1. This cross-sectional view corresponds to the cross-sectional view of the semiconductor device 1 shown in FIG. 3 and is a schematic drawing of the main portion to clarify the relationship between the diaphragm 10c of the semiconductor device 1 and the first stopper 30c that limits the vibration range of the diaphragm 10c. As shown in FIG. 12A, the thickness of the second semiconductor substrate 30 is T1, and the thickness of the first stopper 30c is T2. The height from the diaphragm 10c to the first stopper 30c is H. In FIG. 12A, an orthogonal coordinate system is set such that the origin O is the starting point of the diaphragm 10c, the extension direction of the diaphragm 10c is the Y axis, and the height direction is the Z axis. The first stopper 30c extends from Y=0 to a predetermined length in the Y direction.

[0046] FIG. 12B is a graph showing the displacement of the vibrating membrane 10c of the semiconductor device 1. Here, the length of the vibrating membrane 10c in the Y direction is 3 mm, and the tip of the vibrating membrane 10c is displaced 400 μm in the Z direction. This displacement is set as the maximum vibration range of the vibrating membrane 10c, and the first stopper 30c is formed to limit vibrations that exceed this vibration range. In this case, if the first stopper 30c extends from Y=0 to Y=1.5 mm, the height H of the first stopper 30c is approximately 140 μm, as can be seen from the graph in FIG. 12B. If the first stopper 30c extends to Y=1.0 mm, the height H of the first stopper 30c is approximately 70 μm. Considering that the thickness T2 of the first stopper 30c needs to be at least approximately 100 μm, the thickness T1 of the second semiconductor substrate 30 is determined by the vibration range of the vibrating membrane 10c so that the vibrating membrane 10c does not protrude from the top surface of the semiconductor device 1, and can be thinned to approximately 400 μm, which is the maximum displacement of the vibrating membrane 10c.

[0047] 12C is a graph showing the relationship between frequency and displacement of the tip of vibrating membrane 10c in semiconductor device 1. As shown in FIG. 12C, the displacement of the tip of vibrating membrane 10c is overwhelmingly large for the primary resonance, while the displacements of secondary and tertiary resonances are small. For this reason, only the primary resonance is considered for the displacement of vibrating membrane 10c in FIG. 12B. However, when lowering height H of first stopper 30c, it is necessary to consider the displacement of vibrating membrane 10c vibrating in modes other than the primary resonance.

[0048] 12D shows, as a reference example, a case in which, instead of the first stopper 30c in FIG. 12A, a third stopper 30j extending in the opposite direction to the Y direction is provided on the second side wall 30a opposite to the side on which the first stopper 30c is provided. The third stopper 30j limits the vibration range of the vibrating membrane 10c at the tip of the vibrating membrane 10c. If the height H of the third stopper 30j is set to 400 μm, which is the maximum displacement of the tip of the vibrating membrane 10c, and the thickness T2 of the third stopper 30j is set to 100 μm, the thickness T1 of the second semiconductor substrate 30 is 500 μm.

[0049] As shown in Fig. 12A, first stopper 30c that limits the vibration range of vibrating membrane 10c is formed to extend a predetermined length in the Y direction in which vibrating membrane 10c extends from origin O, which is the starting point of vibrating membrane 10c in Fig. 12A. Therefore, as shown in Fig. 12B, the vibration range of vibrating membrane 10c can be limited to the range in the Y direction in which displacement of vibrating membrane 10c is small, and height H of first stopper 30c can be reduced, and thickness T1 of second semiconductor substrate 30 can also be made thinner. This is clear when compared with the case in which third stopper 30j that limits the vibration range of vibrating membrane 10c is provided at the tip of vibrating membrane 10c, as shown as a reference example in Fig. 12D.

[0050] Although the present disclosure has been described in detail above, it will be apparent to those skilled in the art that the present disclosure is not limited to the embodiments described herein. One or more elements of one embodiment can be combined with one or more elements of another embodiment. The present disclosure can be implemented in modified and altered forms without departing from the spirit and scope of the present disclosure, as defined by the claims. Therefore, the description of the present disclosure is intended to be illustrative and explanatory, and is not intended to be limiting of the present disclosure.

[0051] (Appendix 1) The semiconductor device 1 includes a first semiconductor substrate 10 including a cantilevered diaphragm 10c and a first sidewall 10a surrounding the bottom surface of the diaphragm 10c, with the first sidewall 10a supporting the base of the diaphragm 10c, and a second semiconductor substrate 30 stacked on the first semiconductor substrate 10, the second sidewall 30a surrounding the top surface of the diaphragm 10c, and a first stopper 30c protruding from the second sidewall 30a to face the diaphragm 10c and extending parallel to the diaphragm 10c in a direction from the base to the tip of the diaphragm 10c to limit the vibration range of the diaphragm 10c. The first stopper 30c limits the vibration range of the diaphragm 10c, preventing it from being damaged by an excessive increase in amplitude.

[0052] (Appendix 2) In the semiconductor device 1 described in Supplementary Note 1, the first stopper 30c may have a predetermined gap width between it and the vibrating membrane 10c. The vibration range of the vibrating membrane 10c can be limited depending on the gap width.

[0053] (Appendix 3) In the semiconductor device 1 described in Supplementary Note 1 or 2, the first stopper 30c may have a length that does not reach the tip of the vibrating membrane 10c from the base. Because the first stopper 30c has a length that does not reach the tip of the vibrating membrane 10c, even when the vibration of the vibrating membrane 10c reaches the vibration range limited by the first stopper 30c and touches the first stopper 30c, the speed of the vibrating membrane 10c is smaller than that of the tip of the vibrating membrane 10c, and the impact applied from the first stopper 30c to the vibrating membrane 10c is small, thereby suppressing damage that may occur to the vibrating membrane 10c due to the impact.

[0054] (Appendix 4) The semiconductor device 1 described in any one of Supplementary Notes 1 to 3 further includes a sealing portion 30d that closes the space 30b that is surrounded by the vibrating membrane 10c and the second sidewall 30a, is open upward, and is partially covered by the first stopper 30c, and the sealing portion 30d may have a through-hole 30e that suppresses the flow of air passing through. Air flows in and out through the through-hole 30e that connects the space 30b to the outside, but the through-hole 30e is configured to suppress the flow of air passing through. This suppresses pressure fluctuations in the space 30b and vibration of the vibrating membrane 10c.

[0055] (Appendix 5) In the semiconductor device 1 described in any one of Supplementary Notes 1 to 4, the first semiconductor substrate 10 may further include a second stopper 10e that protrudes from the first sidewall 10a to face the vibrating membrane 10c and extends parallel to the vibrating membrane 10c in a direction from the base to the tip of the vibrating membrane 10c to limit the vibration range of the vibrating membrane 10c. The vibration range of the vibrating membrane 10c can be limited not only in the direction toward the upper surface of the vibrating membrane 10c but also in the direction toward the lower surface of the vibrating membrane 10c. The gap between the second stopper 10e and the vibrating membrane 10c can be easily formed by removing the first insulator layer 12.

[0056] (Appendix 6) In the semiconductor device 1 described in Supplementary Note 5, the second stopper 10e may have a predetermined gap width between it and the vibrating membrane 10c. The vibration range of the vibrating membrane 10c can be limited depending on the gap width.

[0057] (Appendix 7) In the semiconductor device 1 described in Supplementary Note 5 or 6, second stopper 10e may have a length that does not reach the tip of vibrating membrane 10c. Because second stopper 10e has a length that does not reach the tip of vibrating membrane 10c, even when the vibration of vibrating membrane 10c reaches the vibration range limited by second stopper 10e and touches second stopper 10e, the speed of vibrating membrane 10c is slower than the tip of vibrating membrane 10c, so the impact applied from second stopper 10e to vibrating membrane 10c is small, and potential damage to vibrating membrane 10c due to the impact is also suppressed.

[0058] (Appendix 8) The semiconductor device 1 according to any one of Supplementary Notes 1 to 7 may further include a piezoelectric element stacked on the vibration membrane 10c and configured by sandwiching the piezoelectric film between a pair of electrode plates. The piezoelectric element can drive the vibration membrane 10c to vibrate.

[0059] (Appendix 9) The manufacturing method of the semiconductor device 1 includes the steps of stacking a piezoelectric element on a first semiconductor substrate 10, the piezoelectric element being formed by sandwiching a piezoelectric layer 18 between a first metal layer 17 and a second metal layer 19; forming, on a second semiconductor substrate 30, a frame-shaped second side wall 30a and a first stopper 30c protruding inward from the second side wall 30a; stacking the second semiconductor substrate 30 on the first semiconductor substrate 10 so that the piezoelectric element is surrounded by the second side wall 30a; and forming, on the first semiconductor substrate 10, a cantilever-shaped vibration membrane 10c on which the piezoelectric element is stacked, and a first side wall 10a that surrounds the vibration membrane 10c and supports the base of the vibration membrane 10c, the first stopper 30c facing the vibration membrane 10c and extending parallel to the direction from the base of the vibration membrane 10c to the tip.

[0060] (Appendix 10) In the method for manufacturing the semiconductor device 1 described in Supplementary Note 9, the first stopper 30c may have a predetermined gap width between it and the vibrating membrane 10c. The vibration range of the vibrating membrane 10c can be limited depending on the gap width.

[0061] (Appendix 11) The manufacturing method of semiconductor device 1 described in Supplementary Note 9 or 10 may further include a step of forming a sealing portion 30d that is surrounded by vibrating membrane 10c and second sidewall 30a, is open upward, and closes space 30b that is partially covered by first stopper 30c. Sealing portion 30d allows closed space 30b to be formed above vibrating membrane 10c.

[0062] (Appendix 12) In the method for manufacturing semiconductor device 1 described in Appendix 11, the step of forming sealing portion 30d may further include the step of forming through-hole 30e that suppresses air passing through sealing portion 30d. Through-hole 30e, which communicates closed space 30b with the outside, is configured to suppress the flow of passing air, thereby suppressing fluctuations in pressure in space 30b and also suppressing vibration of vibrating membrane 10c.

[0063] (Appendix 13) The manufacturing method of semiconductor device 1 described in Supplementary Notes 9 to 12 may further include a step of forming second stopper 10e that protrudes from first sidewall 10a so as to face diaphragm 10c and extends parallel to diaphragm 10c in a direction from the base to the tip, thereby limiting the vibration range of diaphragm 10c. The vibration range of diaphragm 10c can be limited not only in the direction toward the upper surface of diaphragm 10c but also in the direction toward the lower surface of diaphragm 10c.

[0064] (Appendix 14) In the method for manufacturing the semiconductor device 1 described in Supplementary Note 13, the second stopper 10e may have a predetermined gap width between it and the vibrating membrane 10c. The vibration range of the vibrating membrane 10c can be limited depending on the gap width.

[0065] (Appendix 15) In the method for manufacturing the semiconductor device 1 described in Supplementary Note 13 or 14, the first semiconductor substrate 10 is configured by laminating a first semiconductor layer 11, a first insulator layer 12, and a second semiconductor layer 13 in this order, the second stopper 10e and the vibrating membrane 10c are configured by the first semiconductor layer 11 and the second semiconductor layer 13, respectively, and the gap between the second stopper 10e and the vibrating membrane 10c may be formed by removing the first insulator layer 12. An SOI (silicon on insulator) wafer configured by laminating the first semiconductor layer 11, the first insulator layer 12, and the second semiconductor layer 13 can be effectively used. [Explanation of symbols]

[0066] 1. Semiconductor device 10 First semiconductor substrate 10a 1st side wall 10b First recess 10c vibrating membrane 10d through groove 10e Second stopper 11 First semiconductor layer 12 First insulating layer 13 Second semiconductor layer 14 Second insulating layer 15 1st protective layer 16 Second protective layer 17 1st metal layer 18 Piezoelectric layer 19 Second metal layer 30 second semiconductor substrate 30a 2nd side wall 30b space 30c First stopper 30d Sealing part 30e through hole 30f cutout 41 Adhesive layer

Claims

1. a first semiconductor substrate including a cantilevered diaphragm and a first sidewall surrounding a lower surface of the diaphragm, the first sidewall supporting a base of the diaphragm; a second semiconductor substrate stacked on the first semiconductor substrate, the second semiconductor substrate including a second side wall surrounding an upper surface of the vibration membrane, and a first stopper protruding from the second side wall so as to face the vibration membrane and extending parallel to the vibration membrane in a direction from a base portion to a tip portion of the vibration membrane to limit a vibration range of the vibration membrane; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the first stopper has a predetermined gap width between it and the vibration membrane.

3. The semiconductor device according to claim 1 , wherein the first stopper has a length that does not reach the tip of the vibration membrane.

4. 2. The semiconductor device according to claim 1, further comprising a sealing portion that is formed by being surrounded by the vibration membrane and the second side wall, is open upward, and closes a space that is partially covered by the first stopper, and the sealing portion has a through hole that suppresses the flow of air passing through.

5. 2. The semiconductor device according to claim 1, wherein the first semiconductor substrate further includes a second stopper that protrudes from the first side wall so as to face the vibration membrane and extends parallel to the vibration membrane in a direction from the base of the vibration membrane toward the tip thereof to limit the vibration range of the vibration membrane.

6. The semiconductor device according to claim 5 , wherein the second stopper has a predetermined gap width between it and the vibration membrane.

7. The semiconductor device according to claim 5 , wherein the second stopper has a length that does not reach the tip of the vibration membrane.

8. The semiconductor device according to claim 1 , further comprising a piezoelectric element laminated on the vibration film and configured by sandwiching a piezoelectric film between a pair of electrode plates.

9. a step of laminating a piezoelectric element, which is formed by sandwiching a piezoelectric film between a pair of electrode plates, on a first semiconductor substrate; forming a frame-shaped second sidewall and a first stopper protruding inward from the second sidewall on a second semiconductor substrate; stacking the second semiconductor substrate on the first semiconductor substrate such that the piezoelectric element is surrounded by the second sidewall; forming, on the first semiconductor substrate, a cantilever-shaped vibration membrane on which the piezoelectric element is laminated, and a first side wall surrounding the vibration membrane and supporting a base of the vibration membrane; Including, The first stopper faces the vibration membrane and extends parallel to the vibration membrane in a direction from a base portion to a tip portion of the vibration membrane.

10. The method for manufacturing a semiconductor device according to claim 9 , wherein the first stopper forms a predetermined gap width between the first stopper and the vibration membrane.

11. 10. The method for manufacturing a semiconductor device according to claim 9, further comprising forming a sealing portion that closes a space that is surrounded by the vibration membrane and the second side wall, is open upward, and is partially covered by the first stopper.

12. The method for manufacturing a semiconductor device according to claim 11 , wherein the step of forming the sealing portion further comprises the step of forming a through hole that prevents air from passing through the sealing portion.

13. 10. The method for manufacturing a semiconductor device according to claim 9, further comprising the step of forming a second stopper that protrudes from the first side wall so as to face the vibration membrane and extends parallel to the vibration membrane in a direction from the base to the tip, thereby limiting the vibration range of the vibration membrane.

14. The method for manufacturing a semiconductor device according to claim 13 , wherein the second stopper forms a predetermined gap width between the second stopper and the vibration membrane.

15. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the first semiconductor substrate is configured by sequentially stacking a first semiconductor layer, an insulator layer, and a second semiconductor layer, the second stopper and the vibration membrane are configured by the first semiconductor layer and the second semiconductor layer, respectively, and the gap between the second stopper and the vibration membrane is formed by removing the insulator layer.

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