Differential current-mode driver for microwave assisted magnetic recording

Abstract

To provide an apparatus and method for enabling rapid transitions during microwave assisted magnetic recording (MAMR) of a storage medium.SOLUTION: In the differential vMode driver for MAMR, the MAMR sensor related circuitry 310 includes a MAMR _ P node 312, a MAMR _ N node 314, a damping element 316, a capacitive element 318, and a resistive element 320. The MAMR _ P and MAMR _ N nodes establish direct connection points between the MAMR sensor driver circuitry and the MAMR sensor. The MAMR _ P node serves as the field inflow terminal through which current ultimately flows from the power supply into the MAMR sensor (resistive element). The MAMR _ N node functions as a field drain terminal, where current drains away from the MAMR sensor and eventually towards ground. These nodes receive a controlled differential voltage produced by the MAMR sensor driver circuitry, which in turn establishes current flow for proper MAMR operation.SELECTED DRAWING: Figure 3

Description

[Background technology]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This disclosure claims priority to U.S. Provisional Patent Application No. 63 / 662,954, filed June 21, 2024, the disclosure of which is incorporated herein by reference in its entirety.

[0002] In the field of data storage technology, some hard disk drives (HDDs) utilize microwave-assisted magnetic recording (MAMR) using MAMR sensors (e.g., spin torque oscillators) to generate microwave fields when writing or erasing data. These microwave fields provide supplemental energy during the write / erase process, thereby temporarily reducing the energy barrier for magnetic switching. As a result, MAMR-enabled HDDs can use smaller write heads while magnetizing increasingly dense storage media that would be difficult to alter using conventional recording methods. Furthermore, MAMR technology enables HDDs to continue increasing areal densities while maintaining data integrity and readability.

[0003] HDDs using MAMR technology write data throughout their operation by positioning the head over a defined track on the rotating disk platter. First, the write head, assisted by a microwave field from the MAMR sensor, generates a magnetic field to align magnetic domains on the disk surface into a pattern representing binary data. Meanwhile, as the disk rotates at high speed, the head alternates between data sectors and servo sectors containing positioning information. Additionally, each rotation requires the read / write head to transition between writing data and reading servo sectors multiple times, which occurs frequently (e.g., approximately every 50–100 microseconds). MAMR circuitry controls the timing of magnetic field generation during these transitions, requiring only a few microseconds to complete the transition from write mode to servo read mode for the next sector. Because the MAMR sensor's demagnetization period can take up to 20 nanoseconds, the MAMR circuitry often cannot complete the demagnetization before the next transition to servo mode, resulting in additional read attempts and associated delays. Summary of the Invention

[0004] This Summary is provided to introduce subject matter that is further described in the Detailed Description and Drawings. As such, this Summary itself should not be considered to describe essential features, nor should it be used to limit the scope of the claimed subject matter.

[0005] In various embodiments, an apparatus facilitates high-speed transitions during microwave-assisted magnetic recording (MAMR). The apparatus includes a driver circuit coupled to a power connection. The driver circuit is configured to provide a controlled differential bias current and has separate source and sink output terminals. A MAMR sensor is coupled between the source and sink output terminals of the driver circuit. The MAMR sensor receives the controlled differential bias current provided by the driver circuit through field-in and field-out terminals. These terminals generate a microwave field for the recording process. The apparatus further includes a common-mode feedback (CMFB) loop coupled to the field-in and field-out terminals of the MAMR sensor. The CMFB loop forms a feedback path with the driver circuit. The feedback path enables the CMFB loop to detect a common-mode voltage (CMV) and adjust the controlled differential bias current. These adjustments maintain CMV regulation of the MAMR sensor during operation.

[0006] In some embodiments, a hard disk drive system facilitates high-speed transitions during microwave-assisted magnetic recording (MAMR). The hard disk drive system includes a write head that utilizes a MAMR sensor. The hard disk drive system includes current-mode (iMode) driver circuitry configured to drive a controlled differential bias current through a field-input terminal and a field-output terminal of the MAMR sensor. The iMode driver circuitry includes a driver circuit coupled to a power supply connection. The driver circuit has separate source and sink output terminals through which the MAMR sensor receives the controlled differential bias current provided by the driver circuit. The iMode driver circuitry further includes a common-mode feedback (CMFB) loop coupled to the field-input and field-output terminals of the MAMR sensor. The CMFB loop forms a feedback path with the driver circuit. The CMFB loop detects a common-mode voltage (CMV) and adjusts the controlled differential bias current to maintain CMV regulation of the MAMR sensor.

[0007] In another aspect, a method facilitates high-speed transitions during magnetic recording in microwave-assisted magnetic recording (MAMR). The method includes providing, by a driver circuit, a controlled differential bias current to a MAMR sensor of a magnetic media read / write channel. The method includes maintaining common-mode voltage (CMV) regulation of the MAMR sensor by a common-mode feedback (CMFB) loop coupled to the field-in and field-out terminals of the MAMR sensor. The CMFB loop detects voltage conditions at both terminals and generates a correction signal through a feedback path. The method further incorporates switching the controlled differential bias current through the MAMR sensor with precise timing parameters. These parameters include a rise time of 10 nanoseconds or less and a fall time of 10 nanoseconds or less. This switching capability enables precise timing control during write-to-servo transitions, which prevents data corruption in servo positioning information of a hard disk drive.

[0008] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims. [Brief explanation of the drawings]

[0009] The details of one or more implementations of a differential iMode driver for MAMR are set forth in the accompanying figures and the detailed description below. In the figures, the left-most digit of a reference number indicates the figure in which the reference number first appears. When the same reference number is used in different places in the description and figures, it refers to the same element. [Figure 1] 1 illustrates an exemplary operating environment having devices in which a differential iMode driver may be implemented. [Figure 2] An exemplary configuration of a hard disk drive is illustrated in FIG. 1 with a MAMR-enabled write head. [Figure 3] 3 is an example schematic diagram of the circuitry of the MAMR-enabled write head of FIG. 2, including an example implementation of a differential iMode driver for MAMR. [Figure 4] 1 depicts an example method for a differential iMode driver driving a MAMR sensor, according to one or more embodiments. [Figure 5] 1 illustrates an exemplary system-on-chip (SoC) that may implement various aspects of a differential iMode driver for MAMR. [Figure 6] 1 illustrates an exemplary storage media controller in accordance with one or more aspects of a differential iMode driver for MAMR. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hard disk drive (HDD) systems using microwave-assisted magnetic recording (MAMR) technology typically exhibit operational issues related to MAMR sensor deactivation or transition timing. Generally, HDDs using MAMR technology write data throughout their operation by positioning the head over a defined track on a rotating disk platter. First, the write head, assisted by a microwave field from the MAMR sensor, generates a magnetic field to align magnetic domains on the disk surface into a pattern representing binary data. Meanwhile, as the disk rotates at high speed, the head alternates between data sectors and servo sectors containing positioning information. Additionally, each rotation requires the read / write head to transition between writing data and reading servo sectors multiple times, which occurs frequently (e.g., approximately every 50–100 microseconds). MAMR circuitry controls the timing of magnetic field generation during these transitions, requiring only a few microseconds to complete the transition from write mode to servo read mode for the next sector.

[0011] In some cases, MAMR sensors in hard disk drive write heads fail to fully deactivate before the write head moves to a new location. This failure can result in residual magnetic fields that persist during head movement, which can alter data stored on the disk surface as the head advances. Furthermore, servo pattern corruption reduces track location accuracy in drive system addressability, such as in high-density storage configurations with minimal track spacing that are susceptible to positioning errors. These positioning inaccuracies can initially cause isolated data corruption and ultimately lead to drive failure due to the system's inability to accurately locate tracks.

[0012] These deactivation timing issues are most evident during the write-to-servo transition, during which, after a write operation is completed, the write head must be deactivated to read servo positioning information from a dedicated disk area. Typically, this servo read process can take approximately 20 nanoseconds (ns) to complete, and each rotation requires the read / write head to transition between writing data and reading servo sectors multiple times, which occurs frequently (e.g., approximately every 50-100 microseconds). Because the MAMR sensor demagnetization period can take up to 20 ns, the MAMR circuitry often cannot complete demagnetization before the next transition to servo mode, resulting in corrupted servo patterns and positioning errors.

[0013] For example, in hard disk drives utilizing previous versions of MAMR technology, operational issues can occur during write head transition periods as the write head moves from one location to another on the media disk. Prior to this transition period, the write head should be fully deactivated to remove any residual magnetic fields. Without full deactivation, the write head retains lingering, unwanted residual magnetism that unintentionally alters data on the media disk. As a result, this alteration potentially corrupts data that was not intended to be altered.

[0014] This unwanted residual magnetism leads to a phenomenon known as pole erasure, in which a magnetic field exists even in the absence of an active write signal, gradually corrupting data on the media disk. Additionally, pole erasure creates problems when it affects the servo area because the servo pattern provides positioning information for the entire hard disk drive system. Repeated exposure to these residual fields degrades the servo positioning data as the magnetic pattern changes. Because the positioning system relies on accurate servo patterns to locate tracks, errors accumulate over time. Ultimately, the hard disk drive system cannot reliably locate specific data tracks, thereby leading to complete drive failure rather than isolated data corruption.

[0015] Sensor write heads in previous versions of MAMR technology typically use a closed-loop voltage system with a voltage feedback circuit that maintains voltage levels. These previous versions of write heads require longer deactivation times (e.g., hundreds of nanoseconds) than the time required to read / write servo positioning information (e.g., approximately 20 nanoseconds). As a result, this timing mismatch means that previous versions of MAMR write heads continue to generate residual magnetic fields long after they have been triggered to deactivate. The timing mismatch issue compromises the drive system's addressing mechanism, which enables the hard disk drive system to locate and access specific data, thereby creating reliability and data integrity issues. This impact is particularly acute in high-density recording scenarios, where track spacing is minimal and positioning accuracy specifications are very stringent.

[0016] In contrast to previous techniques, this disclosure describes aspects of a differential iMode driver for MAMR of magnetic storage media. In various aspects, the MAMR control circuitry may include an iMode driver with a common-mode feedback (CMFB) loop configured to maintain common-mode voltage (CMV) regulation of the MAMR sensor. As described herein, the iMode driver and associated circuitry enable rapid MAMR sensor deactivation and / or transition with shorter demagnetization periods (e.g., less than 10 ns), which reduces residual magnetic fields that persist during head movement and prevents corruption of the servo pattern.

[0017] In various aspects, the iMode driver circuitry is configured to drive a controlled differential bias current through terminals of the MAMR sensor of the write head. The iMode driver circuitry includes a driver circuit (e.g., a high-speed switching driver circuit) coupled to a power supply connection. Depending on the implementation, the power supply connection may include a power and ground pair or a positive and negative power supply pair.

[0018] The driver circuit can have separate source and sink output terminals through which the driver circuit provides a controlled differential bias current to the MAMR sensor. The iMode driver circuitry also includes a CMFB loop coupled to the terminals of the MAMR sensor. The CMFB loop is configured to maintain CMV regulation of the MAMR sensor. In various embodiments, the iMode driver circuitry enables control of the magnetic recording process of the MAMR sensor with very fast transition times.

[0019] The following discussion describes the operating environment, techniques that may be employed in the operating environment, and hard disk drive systems in which components of the operating environment may be embodied. In the context of this disclosure, references to the operating environment are made by way of example only.

[0020] 1 illustrates an exemplary operating environment 100 having a computing device 102 (e.g., a host device) that can store or access data on various storage devices, such as magnetic media-based drives. Examples of computing device 102 may include a laptop computer 104, a desktop computer 106, and a server 108, any of which may be configured as part of a storage network or cloud storage. Additionally, examples of computing device 102 (not shown) may include tablet computers, set-top boxes, data storage appliances, wearable smart devices, televisions, content streaming devices, high-definition multimedia interface (HDMI®) media sticks, smart appliances, home automation controllers, smart thermostats, Internet-of-Things (IoT) devices, mobile-internet devices (MIDs), network-attached-storage (NAS) drives, aggregate storage systems, game consoles, automotive entertainment devices, automotive computing systems, and automotive control modules (e.g., engine or powertrain control modules), among others.

[0021] In general, computing device 102 may provide, communicate, or store data for any suitable purpose, such as contributing to the functionality of a particular type of device, providing a user interface, enabling network access, implementing gaming applications, playing media, providing navigation, editing content, or providing data storage. Alternatively or additionally, computing device 102 may store a variety of data, such as databases, user data, multimedia, applications, operating systems, etc. One or more computing devices 102 may be configured to provide remote data storage or services, such as cloud storage, archiving, backup, client services, record keeping, etc.

[0022] In an implementation, the computing device 102 includes a processor 110 and a computer-readable storage medium 112. The processor 110 may be implemented as any suitable type or number of processors, either single-core or multi-core (e.g., ARM or x86 processor cores), for executing instructions or commands of the computing device's 102 operating system or other programs. The computer-readable storage medium 112 (CRM 112) includes a memory medium 114 and a media drive 116. The memory medium or system memory of the computing device 102 may include any suitable type or combination of volatile or non-volatile memory. For example, the volatile memory of the computing device 102 may include various types of random-access memory (RAM), dynamic RAM (DRAM), or static RAM (SRAM), etc. Non-volatile memory may include read-only memory (ROM), electronically erasable programmable ROM (EEPROM), or flash memory (e.g., NOR flash or NAND flash), which, alone or in combination, may store data associated with applications and / or the operating system of computing device 102.

[0023] The media drive 116 of the computing device 102 may include one or more media drives or may be implemented as part of a data storage system associated with the computing device 102. In this example, the media drive 116 includes a hard disk drive system 118 (HDD system 118), which can store data and is described with reference to various aspects of a differential iMode driver. Alternatively or additionally, the media drive 116 may be configured as any suitable type of data storage drive or system, such as a storage device, storage drive, storage array, or storage volume. As described with reference to the computing device 102, the media drive 116 may also be implemented separately as a standalone device or as part of a larger storage collection, such as a data center, server farm, or virtualized storage system (e.g., for cloud-based storage or services), in an aspect in which a differential iMode driver is implemented.

[0024] Computing device 102 may also include I / O ports 120, a graphics processing unit (GPU, not shown), and a data interface 122. Generally, I / O ports 120 allow computing device 102 to interact with other devices, peripherals, or a user. For example, I / O ports 120 may include or be coupled to a universal serial bus, a human interface device, audio input, or audio output, etc. The GPU processes and renders graphics-related data for computing device 102, such as user interface elements of an operating system or applications. In some cases, the GPU accesses a portion of local memory to render graphics or includes dedicated memory (e.g., video RAM) for rendering graphics for computing device 102.

[0025] The data interface 122 of the computing device 102 provides a connection to one or more networks and other devices connected to these networks. The data interface 122 may include a wired interface, such as an Ethernet or fiber optic interface, for communicating data over a local network, an intranet, or the Internet. Alternatively or additionally, the data interface 122 may include a wireless interface that facilitates communication over a wireless network, such as a wireless LAN, a wide-area wireless network (e.g., a cellular network), and / or a wireless personal-area network (WPAN). Any data communicated through the I / O port 120 or the data interface 122 may be written to or read from a storage system of the computing device 102 in accordance with one or more aspects of a differential iMode driver for MAMR of the storage medium.

[0026] Returning to the media drive 116, the computing device 102 may include the illustrated hard disk drive system 118 and / or other types of storage media devices in which a differential iMode driver may be implemented. Although not shown, other configurations of the media drive 116 are also contemplated, such as solid-state drives (SSDs), magnetic tape drives, optical media drives, HDD / SSD hybrid drives, and other storage systems that write data to storage media (e.g., magnetic or optical storage media). Alternatively or additionally, the computing device 102 may include an array of media drives or may function as a media drive aggregate device or host for multiple media drives in an embodiment in which a differential iMode driver may be implemented.

[0027] In this example, the hard disk drive system 118 includes a head-disk assembly 124 (HDA 124) and a drive control module 126 for implementing or enabling the functionality of the hard disk drive system 118. In some cases, the drive control module 126 is implemented as a printed circuit board assembly (PCBA) with semiconductor devices, logic, or other circuitry. The HDA 124 includes one or more media disks 128 mounted on an integrated spindle and motor assembly 130. The spindle and motor assembly 130 may rotate the media disks 128 below (or above) read / write heads 132 coupled to a head assembly (not shown) of the HDA 124. The media disks 128 may be coated with a magnetically hard material (e.g., a particulate or thin-film surface) and may be written to or read from on one or both sides.

[0028] The read / write heads 132 of the hard disk drive system 118 function as magnetic transducers that write and read data to and from magnetic storage media. These heads operate in conjunction with associated amplification and control circuitry to perform data transfer operations across the disk surface. The read / write heads 132 integrate with other system components to enable advanced recording technologies, including microwave-assisted magnetic recording capabilities, which enhance storage density and performance. In various implementations, the read / write heads 132 may include a MAMR sensor 134.

[0029] The read / write head 132 may be operatively coupled to a preamplifier / writer module 138 (preamp / writer 138 ) of the HDA 124 , which includes preamplifier circuitry for amplifying the write or read signal of the read / write head 132 . Preamplifier / writer 138 may receive or store head selection, amplification, and sense current values ​​useful for writing data to or reading data from magnetic media. Read / write head 132 and / or preamplifier / writer 138 may be configured to function in concert with other components of hard disk drive system 118 to implement aspects of a differential iMode driver for MAMR of storage media.

[0030] In embodiments, the preamplifier / writer 138 can include MAMR sensor drive circuitry 136 for implementing MAMR, which generates a microwave field when writing or erasing data. The MAMR sensor drive circuitry 136 can be configured to drive a controlled differential bias current through terminals of the MAMR sensor 134 of the write head. In some embodiments, the MAMR sensor drive circuitry 136 includes a driver circuit (e.g., a high-speed switching driver circuit) coupled to a power connection. Depending on the implementation, the power connection can include a power and ground pair or a positive and negative power pair.

[0031] The driver circuitry includes separate source and sink output terminals through which the driver circuitry provides a controlled differential bias current to the MAMR sensor 134. The MAMR sensor drive circuitry 136 also includes common-mode feedback (CMFB) loops independently coupled to the terminals of the MAMR sensor, the CMFB loops configured to maintain common-mode voltage (CMV) regulation of the MAMR sensor.

[0032] 1 , an exemplary drive control module 126 of hard disk drive system 118 includes a storage media controller 140, a servo control unit 142, and a read / write channel 144 (R / W channel 144). Generally, storage media controller 140 enables computing device 102 to access the contents of the magnetic storage media of media drive 116, such as data or other services for the operating system, applications, or applications. Storage media controller 140 may also write data for computing device 102 to and read data from the magnetic storage media of media drive 116. In some cases, drive control module 126 directs or uses servo control unit 142 to control mechanical operations, such as positioning of read / write head 132 through HDA 124 and rotational speed control through spindle and motor assembly 130.

[0033] The servo control unit 142 directs the mechanical positioning of the read / write head 132 over a particular track on the media disk 128. The servo control unit 142 moves the read / write head 132 to a location across the magnetic media in the HDA 124. Additionally, the servo control unit 142 adjusts the rotational speed of the media disk 128 through the spindle and motor assembly 130. The read / write channel 144 may include digital-to-analog and analog-to-digital paths for converting write data into write signals or read signals into read data, respectively. For example, the read / write channel 144 may process and encode signals when data, such as sectors of user data, is written to the media disk 128 as a pattern of code words or bits. Alternatively or additionally, the read / write channel 144 may process and decode signals when encoded data, such as code words or bits, is read from multiple sectors of the media disk 128.

[0034] This signal processing, encoding, and / or decoding of the write or read signals may include signal conditioning, sampling, equalization, phase adjustment, detection, or error correction, etc. Drive control module 126 or components thereof may be implemented as one or more IC chips, a system-on-a-chip, a system-in-package, or a microprocessor with or implementing a hard disk drive controller. Drive control module 126 may also include drive electronics (not shown) and / or various interfaces, such as a host bus interface, a storage media interface, a spindle interface, or a preamp / writer interface.

[0035] The read / write channel 144 converts digital computer data into analog magnetic patterns and vice versa. When writing, the read / write channel 144 converts digital data into code words with error correction capabilities. The read / write channel 144 converts these digital code words into analog electrical signals that create magnetic patterns across a magnetic medium consisting of multiple disk sectors. Each sector of the disk medium may contain partitions that hold specific code words or data blocks according to the pattern of bits written to the magnetic medium. Digital-to-analog conversion involves timing to create the correct magnetic patterns. When reading, magnetic changes on the disk generate analog electrical signals. These signals undergo amplification before processing. The analog signals undergo a detection process that converts them into a digital bit stream. During analog-to-digital conversion, the read / write channel 144 uses synchronization marks to identify code word or block boundaries. After conversion, the read / write channel 144 then decodes these code words into the original user data.

[0036] Figure 2 illustrates at 200 an exemplary configuration of the hard disk drive system 118 shown in Figure 1. As shown in Figure 2, in an implementation, the HDA 124 of the hard disk drive system 118 includes an integrated spindle and motor assembly 130, by which a media disk 128 of a magnetic medium 202 is supported and / or moved. A servo control unit 142 directs the movement of the arm 204, thus positioning the read / write head 132 (or multiple read / write heads 132) over a desired track 206 of the magnetic medium 202 on the media disk 128.

[0037] Media disk 128 includes dedicated servo areas 210 (e.g., servo area 210) with positioning information recorded on magnetic medium 202. These servo areas (e.g., servo area 210) appear at intervals around each track 206 and provide reference markers that help read / write head 132 maintain alignment. The servo areas store patterns that encode track numbers, sector identifiers, and positioning offsets. When read / write head 132 passes over these servo areas, the resulting signals go to preamplifier / writer 138 for processing. Servo control unit 142 uses this position data (e.g., servo information) to calculate corrections and / or track the location of sectors across the disk surface. Accurate interpretation of the servo positioning information allows the system to access the specific sectors 208 where data resides.

[0038] Write-to-servo transitions occur periodically as read / write channel 144 converts data into error-corrected code words (or bits) that are written to sectors 208 of the magnetic media. While writing along track 206, servo control unit 142 temporarily suspends writing to evaluate position, so that write current to read / write heads 132 stops as they move over the servo area. During this pause, timing recovery circuitry can adjust the sampling phase to read the servo signals, which allows servo control unit 142 to reposition actuator arm 204 before continuing writing in subsequent sectors 208.

[0039] In general, the read / write head 132 may include various numbers of head elements with combined or separate functions (e.g., dedicated R / W functions). For example, the read / write head 132 may include one or more readers (read heads / elements) and one writer (write head / element). In other cases, the read / write head 132 may include a dedicated write head (element) and one or more separate, additional, dedicated read head elements. Alternatively or additionally, although multiple arms 204 are shown in FIG. 2 , the HDA 124 or spindle and motor assembly may be implemented with a single arm 204 or other suitable structure for positioning the read / write head 132. The HDA 124 and the drive control module 126 may be implemented separately, on separate boards, and / or as separate PCBAs in the media drive. Signals or data communicated between HDA 124 and drive control module 126 may be carried through flexible printed cables or other suitable connection structures, such as traces, connectors, bond wires, or solder balls.

[0040] During operation, the hard disk drive system 118 alternates between two main functions: track seeking and track following. During track seeking, the read / write head 132 moves from a current track (e.g., track 206) to a destination track. Subsequently, during track following, the read / write head 132 maintains a position as close as possible to the track center while reading or writing information. Furthermore, by comparing the amplitude balancing between the inner and outer bits in the servo pattern, a positioning error signal (PES) is produced, which determines how accurately the read / write head 132 is centered over track 206.

[0041] Writing data involves applying a magnetic field through write head 220 of read / write head 132 to align magnetic domains on media disk 128 into a pattern representing binary data. Additionally, erasing data acts as a special form of data writing in which existing data receives a new pattern that resets the magnetic domains to a different state. In Perpendicular Magnetic Recording (PMR) technology, the magnetic domains are aligned perpendicular to the disk surface, thus increasing storage density.

[0042] 2 also includes an illustration of exemplary sectors 208 configured to store data to be written to the magnetic medium 202 of the media disk 128. One or more of the read / write heads 132 may write data (e.g., user data or codewords) to respective sectors 208 of the tracks 206 of the media disk 128 (e.g., sectors of the tracks 206). For purposes of illustration, the media disk 128 is shown including the tracks 206 after the sectors 208 of data have been written thereto by, for example, the read / write heads 132.

[0043] Generally, during a write operation, the read / write head 132 may be driven by a write current provided by the preamplifier / writer 138, whereby an electrical signal is used to generate and / or transfer to the media disk 128 a magnetic field having an associated polarity of the encoded bits. In response to the application of the magnetic or write field, the read / write head 132 may form a plurality of magnetizations corresponding to the encoded data (e.g., user data) within the magnetic grains of the sectors 208 of the media disk 128. The HDA 124 of the hard disk drive system 118 may be configured to perform write operations according to any suitable recording technology, such as perpendicular magnetic recording (PMR), shingled magnetic recording (SMR), heat-assisted magnetic recording (HAMR), or microwave-assisted magnetic recording (MAMR).

[0044] One or more implementations of the techniques described herein use MAMR technology in conjunction with a write head 220 and / or a preamplifier / writer 138 of a read / write head 132 to write and erase data on a media disk 128. The MAMR-based write head 220 includes a write head assembly 222, a write coil 224, a write gap 226 (or opening), and a MAMR sensor 134. In an aspect, a MAMR sensor drive circuitry 136 is connected to the MAMR sensor 134 and is either part of or connected to the preamplifier / writer 138.

[0045] The write head assembly 222 may provide a structural framework that houses all other elements of the write head 220. Additionally, the write head assembly 222 may also provide mechanical stability while ensuring proper alignment of the magnetic components with respect to the surface of the media disk 128. In some cases, the write head assembly 222 incorporates shielding to prevent electromagnetic interference between adjacent components.

[0046] The write head assembly's write coil 224 can be configured as a tightly wound conductive structure (e.g., typically copper) that generates a primary magnetic field in response to the application of an electric current. When an electric current flows through the write coil 224, the resulting electromagnetic field propagates through the write gap 226. The write coil 224 then converts electrical energy into magnetic energy that changes magnetic domains on the disk surface during the writing process. The strength of the magnetic field generated by the write coil 224 varies proportionally with the amount of electric current applied.

[0047] The write gap 226 (or opening) creates a controlled discontinuity between the magnetic pole structures of the write head 220. This allows magnetic flux to escape from the internal components. The write gap 226 allows the magnetic field generated by the write coil 224 to extend outward toward the magnetic media 202 beneath the write head 220. During operation, the magnetic field projects through the write gap 226 with sufficient strength to magnetize domains on the media disk 128 below.

[0048] The dimensions of the write gap 226 can directly affect the field strength, concentration, and recording accuracy on the magnetic media 202. Therefore, the write gap 226 can be configured to balance several factors, including field projection characteristics and mechanical stability, while maintaining a constant distance from the recording surface of the media disk 128. When a current flows through the write coil 224, the resulting electromagnetic field 212 extends through the write gap 226 to the sector 208 of the media disk 128.

[0049] The MAMR sensor 134 functions as the microwave-generating element in the MAMR-based write head 220. The MAMR sensor 134 operates as a spin-torque oscillator, utilizing electron spin properties to generate a high-frequency assist field. Additionally, the MAMR sensor 134 can generate oscillations in the 20-40 GHz range when appropriately excited by a differential current from a current-mode (iMode) driver implementation of the MAMR sensor drive circuitry. Furthermore, the MAMR sensor 134 provides supplemental energy to the magnetic field from the write coil 224, enabling higher-density recording on magnetic media 202 that would otherwise resist magnetization. The MAMR sensor 134 includes a resistive element with microwave field generation in response to current flow.

[0050] Within the write gap 226, the MAMR sensor 134 can be positioned to optimize or control field interaction with the disk surface. The write gap 226 positions the MAMR sensor 134 so that both the main magnetic field and the microwave field can effectively couple before reaching the magnetic medium 202. Thus, during a write operation, fields from both the write coil 224 and the MAMR sensor 134 project simultaneously through the write gap 226. When the read / write head 132 transitions between writing data and reading servo areas 210, both the write coil 224 and the MAMR sensor 134 need to be quickly turned off to prevent residual fields from affecting the positioning information stored in these servo areas 210. However, with conventional approaches, the transition or demagnetization time between write and read modes of the MAMR sensor may not be fast enough.

[0051] In an embodiment, the MAMR sensor driver circuitry 136 functions as an electronic control system for the MAMR sensor 134. The MAMR sensor driver circuitry 136 can drive the sensor by delivering a controlled current or voltage to the MAMR sensor 134. As a result, the MAMR sensor 134 generates microwave oscillations, and the MAMR sensor driver circuitry 136 coordinates the timing of activation and deactivation with write operations. Various implementations of the MAMR sensor driver circuitry 136 can include a power conditioning component 232, a signal generation circuit 234, a control logic section 236, an interface circuit 238, and a feedback mechanism 240. The power conditioning component 232 can be configured to provide a stable electrical input to the MAMR sensor 134. The signal generation circuit 234 generates specific electrical patterns used for proper operation of the sensor. The control logic section 236 manages the timing of various operations of the MAMR-based write head 220.

[0052] The interface circuits 238 may serve as a communication pathway that translates control signals (e.g., write enable signals) from the drive control module 126 into specific electrical commands for the MAMR sensor 134. Additionally, these interface circuits establish connections with multiple systems, including the preamplifier / writer 138, the servo control unit 142, and timing systems, contributing to synchronized operation across the entire hard disk drive system 118. The MAMR sensor driver circuitry 136 may also incorporate feedback mechanisms 240 that continuously monitor performance parameters. These feedback systems facilitate maintaining improved operation under varying conditions.

[0053] The architecture of the MAMR sensor driver circuitry 136 typically follows either a voltage-mode (e.g., vMode) or current-mode (e.g., iMode) approach. In a voltage-mode configuration, the circuitry controls a specific voltage level across the MAMR sensor 134. Conversely, a current-mode approach adjusts the amount of current flowing through the MAMR sensor 134. Each approach offers different characteristics in terms of response time, stability, and power efficiency. Regardless of the approach, the MAMR sensor driver circuitry 136 enables writing to magnetic materials while deactivating fast enough to prevent residual magnetic fields that could otherwise corrupt data on the magnetic media 202 of the media disk 128.

[0054] 3 is a schematic diagram of an example circuitry for a MAMR-based write head 220 and MAMR sensor driver circuitry 136. As shown, the MAMR sensor 134 is part of the write head 220. The MAMR sensor driver circuitry 136 is part of or connected to a preamp / writer 138. FIG. 3 also shows MAMR sensor-related circuitry 310, which may be part of the write head 220, the preamp / writer 138, and / or some other component, in whole or in part.

[0055] 3, represented as a resistive element coupled between a MAMR_P node 312 and a MAMR_N node 314. This resistive element functions as a spin torque oscillator, generating microwave oscillations when excited by a differential current from the MAMR sensor driver circuitry 136. The physical resistive properties of this element determine the voltage-current relationship developed across the MAMR sensor 134 during operation.

[0056] As shown in FIG. 3 , MAMR sensor-related circuitry 310 is connected to the MAMR sensor 134. The MAMR sensor-related circuitry 310 includes several interconnected components, such as a MAMR_P node 312, a MAMR_N node 314, a damping element 316, a capacitive element 318, and a resistive element 320. The MAMR_P node 312 and the MAMR_N node 314 establish a direct connection between the MAMR sensor driver circuitry 136 and the MAMR sensor 134. The MAMR_P node 312 serves as a field input terminal through which current ultimately flows from the power source into the MAMR sensor 134. Conversely, the MAMR_N node 314 serves as a field output terminal through which current ultimately flows out of the MAMR sensor 134 toward ground. These nodes receive a controlled differential voltage created by the MAMR sensor driver circuitry 136, which in turn establishes the current flow for proper MAMR operation.

[0057] Adjacent or adjacent to the MAMR sensor 134 is a damping element 316, which is a resistive element that suppresses high-frequency oscillations or resonances that would otherwise occur within the MAMR sensor driver circuitry 136. By placing a controlled impedance in the current path, the damping element 316 suppresses ringing effects during fast transitions, thereby preserving signal integrity during fast switching transitions. The damping element 316 also aids in overall system stability by suppressing unwanted parasitic oscillations that would otherwise degrade write performance.

[0058] The MAMR sensor-related circuitry 310 may further include a single-ended capacitor on capacitive element 318 connected to all terminals of the MAMR sensor 134. The capacitive element 318 performs frequency compensation by creating a predetermined time constant for signal processing. Additionally, the single-ended capacitor also stabilizes the feedback signal by filtering out transient noise and passes the intended differential signal with minimal attenuation. Based on coupling location and proper sizing, these capacitive devices can help improve overall system stability not only under steady-state conditions but also when transient switching events occur.

[0059] As depicted, resistive element 320 is positioned between attenuation element 316 and terminals 312 / 314. Resistive element 320 serves to establish a voltage divider network that maintains appropriate signal levels throughout the sensor's operating range. Capacitive element 318 and resistive element 320 together create a combined resistive-capacitive effect that produces a well-defined frequency response characteristic at the interface of MAMR sensor 134 with MAMR sensor driver circuitry 136. This can enable signal integrity throughout the fast switching events used for proper MAMR operation while rejecting unwanted interference or noise components.

[0060] The MAMR sensor driver circuitry 136 includes a driver circuit 330, e.g., a driver circuit, and a common-mode feedback (CMFB) loop 340. In an embodiment, the driver circuit 330 functions as a power management component that delivers a controlled differential bias current to the MAMR sensor 134. The driver circuit 330 establishes direct current flow through the sensor while maintaining the rapid switching capability necessary to prevent residual magnetic fields during HDD operation. The driver circuit 330 includes polarity control switches 322A and 322B, a write / read enable signal (WR enable signal) 324, a MAMR current digital-to-analog converter (MAMR_IDAC) 326, a startup bias integrated digital-to-analog converter (IDAC) 328, a positive-negative driver (PNP driver) 332, a negative-negative driver (NPN driver) 334, a source output terminal 336, and a sink output terminal 338.

[0061] Polarity control switches 322A and 322B provide configurable paths within driver circuit 330 connecting source output terminal 336 and sink output terminal 338 to MAMR sensor 134. These switches allow for reversal of current direction through MAMR sensor 134 when operational requirements change. This feature accommodates alternative bias configurations without physical circuit modifications.

[0062] The driver circuit 330 is composed of two complementary sections, a PNP driver 332 and an NPN driver 334, positioned in the upper and lower portions, respectively, as depicted in the schematic diagram of Figure 3. These drivers help establish direct current flow through the MAMR sensor 134 while maintaining the rapid switching speeds necessary for proper operation. The PNP driver 332 occupies the top section of the schematic diagram in FIG. 3 and is connected to a power supply (not shown). The PNP driver 332 has a source output terminal 336 that delivers current to the MAMR_P node 312. As depicted, the configuration of the PNP driver 332 includes transistor elements arranged in a topology that allows operation at a fully controlled differential bias current, which is the maximum specified current magnitude for improved operating conditions of the MAMR sensor 134. The fully controlled differential bias current provides maximum drive capability for the MAMR sensor 134 with minimal response delay. As shown in FIG. 3, the PNP driver 332 includes current sourcing components that establish a current flow to the MAMR_P node 312.

[0063] The PNP driver 332 also incorporates a startup bias IDAC 328 attached directly to the source output terminal 336. The startup bias IDAC 328 functions as an initialization component that establishes the startup conditions for the MAMR sensor 134 during the power-up sequence. The startup bias IDAC 328 enables the PNP driver 332 to quickly and reliably reach its improved operating point before the feedback loop is fully engaged. The startup bias IDAC 328 delivers a precisely calibrated current setting through a digital control input. It converts the digital value to an analog current reference that establishes the initial operating conditions for the fully controlled differential bias current path. By preconditioning the source output terminal 336 with the appropriate current level, the startup bias IDAC 328 minimizes settling time during the transition from an inactive to an active state, contributing to overall circuit performance.

[0064] The NPN driver 334 is present in the lower portion of the schematic diagram in FIG. 3 and forms a direct path to the negative power supply or ground (not shown). The NPN driver 334 has a sinking output terminal 338 that draws current from the MAMR_N node 314. As depicted, the NPN driver 334 has transistor elements configured to provide controlled current sinking capability. In contrast to the PNP driver 332, the NPN driver 334 utilizes only a partial amount (e.g., a portion) of the total controlled differential bias current through a technique known as fractional biasing. Specifically, the NPN driver 334 operates on a complementary portion, mathematically expressed as a fraction of the full controlled differential bias current, where “fraction” represents a deliberately selected percentage of the total current diverted from the main current path. As discussed below, this diverted current segment or portion corresponds to a “fractional” value and flows into the CMFB loop 340, which helps provide high-bandwidth sensing of common-mode voltage without loading the main signal path.

[0065] Through this strategic current-splitting approach, driver circuit 330 achieves superior performance characteristics compared to conventional architectures that maintain the same current magnitude in both the source and sink paths. The reduced current load on NPN driver 334 creates a smaller capacitive load at the node. This helps provide faster transition times of approximately 5 nanoseconds while providing sufficient current for common-mode regulation at approximately zero volts. Together, PNP driver 332 and NPN driver 334 create a current-mode (iMode) configuration that directly controls the current flowing through MAMR sensor 134 while maintaining accurate common-mode regulation. The asymmetric biasing approach, with full current flowing through PNP driver 332 and partial current flowing through NPN driver 334, establishes electrical conditions that facilitate extremely fast transition times while ensuring stability over a variety of operating conditions.

[0066] FIG. 3 illustrates two digital control components as inputs to the driver circuit 330. The digital control components include a write / read enable signal (WR_EN) 324 and a MAMR current digital-to-analog converter (MAMR_IDAC) 326. The digital control components establish a connection between the drive control module 126 and the analog MAMR sensor driver circuitry 136, which powers the MAMR sensor 134. The WR_EN signal 324 serves as the primary control input that synchronizes the MAMR sensor 134 with servo operation. The WR_EN signal 324 accurately indicates when the write head should be activated or deactivated. Thus, the WR_EN signal 324 triggers the driver circuit 330 to quickly adjust the current through the MAMR sensor 134 within a fast transition time window. In some implementations, the fast transition time window is less than 50 ns. In other implementations, it may be 20 ns or less. In yet other implementations, the fast transition time window is 10 ns or less. Still other implementations have fast transition time windows of 5 ns or less.

[0067] In an aspect, the MAMR_IDAC 326 provides a configurable or programmable current level to the driver circuit 330. In this manner, digital control over the magnitude of the current flowing through the MAMR sensor 134 is enabled. The MAMR_IDAC 326 facilitates calibration and adjustment of the microwave field strength generated by the MAMR sensor 134. Additionally, in the case of an iMode driver, the MAMR_IDAC 326 helps establish an appropriate current limit based on the resistance measurement of the MAMR sensor to prevent potential sensor damage.

[0068] The CMFB loop 340 occupies the lower left section of FIG. 3 and establishes common-mode current regulation across the MAMR sensor 134. The CMFB loop 340 maintains the common-mode voltage (CMV) near zero volts. This creates balanced operating conditions for proper MAMR function. With direct connections to both the MAMR_P node 312 and the MAMR_N node 314, the CMFB loop 340 implements partial current sampling rather than monitoring the entire signal path. Through this approach, it prevents operational drift while enabling extremely fast transitions between write and servo operations. The CMFB loop 340 includes a voltage common-mode (VCM) gain stage 342, a current sampling circuit 344, a fractional bias circuit 346, a dominant frequency pole 348, and a feedback path 350.

[0069] VCM gain stage 342 functions as the main amplifying element in CMFB loop 340. In addition to ground 356, this gain stage connects at its input to current sampling circuit 344 and at its output to dominant frequency pole 348. VCM gain stage 342 amplifies the difference between the detected common-mode voltage and a target reference level of approximately zero volts. Through the application of controlled gain, VCM gain stage 342 converts small voltage deviations into a substantial correction signal that drives the feedback. The amount of gain directly affects loop response.

[0070] A current sampling circuit 344 establishes a connection between the MAMR sensor nodes, MAMR_P node 312 and MAMR_N node 314, and the VCM gain stage 342. The current sampling circuit 344 extracts a representative portion of the current flowing through the MAMR sensor 134 without significantly loading the main signal path. Using a current mirror and scale technique, the current sampling circuit 344 provides an accurate representation of common-mode conditions while consuming minimal power. The partial sampling approach minimizes the effect of capacitive loading on the main signal path. This maintains signal integrity during high-speed transitions.

[0071] Fractional bias circuit 346 is integrated with NPN driver 334 and current sampling circuit 344 to implement a calculated current division. Fractional bias circuit 346 shunts a mathematically defined portion of the controlled differential bias current away from NPN driver 334 toward CMFB loop 340, thereby creating a reduced capacitive load at a critical node. Through a reduction in the current-dependent time constant, fractional bias circuit 346 significantly increases the available bandwidth compared to conventional approaches. The fractional value results from an optimization between the competing requirements of stability, power consumption, and transition speed.

[0072] A dominant frequency pole 348 exists at the junction connecting the VCM gain stage 342, fractional bias circuit 346, and NPN driver 334. The dominant frequency pole 348 establishes an intentional low-frequency cutoff point in the feedback path. This forces a controlled frequency response with, for example, approximately a 20 dB / decade rolloff. Based on its location, the dominant frequency pole 348 facilitates secondary poles occurring significantly beyond the unity gain bandwidth. This maintains sufficient phase margin across operating conditions. This frequency compensation approach eliminates the need for complex multi-pole networks while providing robust stability during rapid transitions.

[0073] Feedback path 350 establishes an interface connection between the CMFB loop 340 and driver circuit 330 of MAMR sensor driver circuitry 136. Feedback path 350 carries a correction signal that modulates current flow in response to sensed common-mode conditions. Low-impedance signal routing with minimal parasitic effects allows feedback path 350 to maintain signal integrity while providing feedback. The continuous compensation provided by this relationship allows the common-mode voltage to be maintained near zero volts, regardless of changing operating conditions or component characteristics. This allows for a stable reference structure required for accurate current-mode control.

[0074] In one or more implementations, the CMFB loop 340 also includes a polarity switch 354 that interfaces between the VCM gain stage 342 and the feedback path 350 within the CMFB loop 340. The polarity switch 354 implements complementary metal-oxide-semiconductor transmission gates that connect to both the positive and negative signal paths. Through an activation control signal, the polarity switch 354 reverses the direction of the correction signal when needed. This accommodates alternative bias configurations or compensates for manufacturing variations in the MAMR sensor 134. During standard operation, the switch maintains the default signal routing, providing configuration flexibility without requiring physical circuit modifications.

[0075] To enhance long-term operational reliability, hard disk drive systems 118 implementing iMode drivers may use one-time calibration by measuring the resistance of the MAMR sensor 134. The iMode driver directly controls current flow, which can damage the MAMR sensor 134 if excessive current is applied to a highly resistive sensor. This calibration process typically occurs during manufacturing and involves applying a known, small current to the MAMR sensor 134 and measuring the resulting voltage across the MAMR_P node 312 and the MAMR_N node 314. Using Ohm's law (V = IR), a resistance value is calculated and stored. The MAMR_IDAC 326 then uses this resistance value to determine an appropriate current limit that provides improved microwave field generation without risking sensor damage. This resistance measurement circuit (not shown) includes a low-current source, precision voltage measurement components, and digital storage for the calculated resistance value. This one-time calibration allows the iMode driver to safely achieve extremely fast transition times of approximately 5 ns or less.

[0076] 2, various components of the MAMR sensor driver circuitry 136 were shown and briefly described. In the context of the MAMR sensor driver circuitry 136 shown in FIG. 3 and described above, the components with their respective descriptions are provided below. The power conditioning component 232 supplies current to the MAMR sensor 134. The power conditioning component 232 includes a MAMR_IDAC 326, a startup bias IDAC 328, a PNP driver 332, an NPN driver 334, a source output terminal 336, and a sink output terminal 338.

[0077] The power conditioning component 232 delivers a controlled current to the MAMR sensor 134. The MAMR_IDAC 326 programs the current magnitude based on the sensor's calibrated resistance. The startup bias IDAC 328 preconditions the source terminals during initialization. The PNP driver 332 operates with a fully controlled differential bias current. The NPN driver 334 operates with a complementary (fractional) bias level. This asymmetric current distribution creates a smaller capacitive load at critical nodes. These components work together to establish a direct current flow through the MAMR sensor, with switching capabilities of approximately 50, 30, 20, 10, and / or 5 nanoseconds between active and inactive states.

[0078] The signal generation circuitry 234 generates the electrical pattern for sensor operation. The signal generation circuitry 234 includes the MAMR_IDAC 326 and resistance measurement circuitry for sensor calibration. The signal generation circuitry 234 produces the electrical pattern for MAMR sensor operation. The MAMR_IDAC 326 converts digital signals into precisely controlled current levels. The resistance measurement circuitry applies a small, known current during manufacturing calibration to determine the resistance of the MAMR sensor. This resistance value then establishes a safe operating current limit. These components collectively determine the operating conditions for microwave field generation by the MAMR sensor.

[0079] The control logic section 236 manages the operational timing. The control logic section 236 includes a WR enable signal 324, polarity control switches 322A / B, and a polarity switch 354. The control logic section 236 can coordinate the operational timing of the MAMR sensor driver circuitry 136. The WR enable signal 324 synchronizes the MAMR sensor with servo operation by indicating when the write head should be activated or deactivated. The polarity switches 322A / B and 354 enable reversal of current direction through the MAMR sensor without physical circuit modifications. These control elements work together to achieve an extremely fast switching time of approximately 5 nanoseconds. This timing aligns the MAMR field with HDD servo timing requirements.

[0080] The interface circuit 238 forms the communication path. The interface circuit 238 includes a driver circuit 330. The interface circuit 238 establishes the communication path between the subsystems. The driver circuit 330 connects the source and sink terminals to the MAMR sensor. These interface components convert high-level control signals from the drive control module into specific electrical commands to the MAMR sensor 134. They form the connections between the functional blocks. This configuration maintains signal integrity throughout the path.

[0081] In various aspects, the feedback mechanism 240 monitors performance parameters. The feedback mechanism 240 includes a CMFB loop 340, a VCM gain stage 342, a current sampling circuit 344, a fractional bias circuit 346, a feedback path 350, and a dominant frequency pole 348. The feedback mechanism 240 can monitor and make adjustments to system parameters, which can include the CMFB loop 340 regulating the common-mode voltage to approximately zero volts. The VCM gain stage 342 can amplify the difference between the detected voltage and a target level, and the current sampling circuit 344 can extract a portion of the current from the MAMR sensor without loading the main signal path. The dominant pole 348 establishes controlled attenuation of the high-frequency signal. These feedback components form a single closed-loop system that continuously senses conditions, compares them to a reference, and makes corrections. This continuous adjustment ensures stable common-mode regulation during transitions between write operations and servo positioning. The transition time is approximately 5 nanoseconds. Differential iMode Drive Techniques

[0082] The following discussion describes differential iMode driver techniques for MAMR applications in HDDs that may reduce or prevent the possibility of on-disk data corruption due to slow write-activation / deactivation transitions of the write head's MAMR sensor. These techniques may be implemented using any of the environments and entities described herein, such as the MAMR-based write head 220, MAMR sensor drive circuitry 136, MAMR sensor-related circuitry 310, and drive control module 126. These techniques include the method illustrated in FIG. 4, which is shown as a set of operations performed by one or more entities.

[0083] These methods are not necessarily limited to the order of operations shown in the associated figures. Rather, any of the operations may be repeated, skipped, replaced, or reordered to implement various aspects described herein. Furthermore, these methods may be used in combination with each other, in whole or in part, regardless of whether performed by the same entity, separate entities, or any combination thereof. For example, aspects of the described methods may be combined to implement a differential iMode driver for MAMR applications in HDDs. In the following description, reference is made to the operating environment 100 of FIG. 1 and entities of FIGS. 2 and 3. Such references should not be construed to limit the described aspects to the operating environment 100, entities, configurations, or implementations, but rather as illustrating one of various examples. Alternatively or additionally, the operations of the methods may also be implemented by or in conjunction with the entities described with reference to the system-on-chip of FIG. 5 and / or the storage media controller of FIG. 6.

[0084] FIG. 4 depicts an exemplary method 400 for implementing a differential iMode driver for MAMR applications in an HDD, including operations performed by or in conjunction with the MAMR-based write head 220, the MAMR sensor drive circuitry 136, the MAMR sensor-related circuitry 310, and the drive control module 126.

[0085] At 402, a resistance measurement is obtained for the MAMR sensor 134. This value may be determined by a resistance measurement circuit that performs a calibration of the MAMR sensor 134. The calibration process may apply a small, known current through the MAMR sensor 134. The resulting voltage is measured across the MAMR_P node 312 and the MAMR_N node 314. The resistance value is calculated using Ohm's Law. This calibration may occur once during manufacturing or at any suitable time when the MAMR sensor 134 requires calibration or recalibration. The measured resistance value may be stored in memory for use by the MAMR_IDAC 326. Using the measured resistance value may ensure a safe current level for the particular MAMR sensor 134.

[0086] At 404, the driver circuit 330 provides a controlled differential bias current to the MAMR sensor 134. The controlled differential bias current is based, at least in part, on the resistance measurement for the MAMR sensor 134. This allows for operation and fast switching. The circuit delivers current through two sections. The PNP driver 332 operates with the full controlled differential bias current through the source output terminal 336. The NPN driver 334 operates with a fraction of the full controlled differential bias current through the sink output terminal 338. This creates a smaller capacitive load at the node. The start-up bias IDAC 328 preconditions the source output terminal 336 with an appropriate current level. The MAMR_IDAC 326 controls the magnitude of the current flowing through the MAMR sensor 134 based on the calibrated resistance value.

[0087] At 406, the CMFB loop 340 maintains common-mode voltage regulation of the MAMR sensor 134. This helps provide stability around a near-zero volt reference point. A VCM gain stage 342 amplifies the difference between the detected common-mode voltage and zero volts. A current sampling circuit 344 extracts a portion of the current flowing through the MAMR sensor 134. A fractional bias circuit 346 shunts a controlled portion of the differential bias current from the NPN driver 334 to the CMFB loop 340. A dominant frequency pole 348 establishes a low-frequency cutoff point in the feedback path. A feedback path 350 sends a correction signal to adjust the current flow based on the detected common-mode condition.

[0088] At 408, the driver circuit 330 directly controls the current flowing through the MAMR sensor 134 based on the calibrated resistance value. The MAMR_IDAC 326 establishes the current levels. These current levels generate the appropriate microwave field from the MAMR sensor 134. With direct current control, there is no need for a voltage feedback loop.

[0089] At 410, the driver circuit 330 switches the current through the MAMR sensor 134 with very fast rise and fall times. This is a change in direction of the current from one side of the differential pair to the other. The transition time window can be 50 nanoseconds or less, 30 nanoseconds or less, 20 nanoseconds or less, 10 nanoseconds or less, and / or 5 nanoseconds or less. This provides timing control during write operations. The driver circuit 330 achieves these fast transitions through asymmetric biasing. The PNP driver 332 uses the full current. The NPN driver 334 uses a partial current. Single-ended capacitors in the capacitive element 318 connect to each terminal of the MAMR sensor 134 for frequency compensation, and the damping element 316 can provide damping of high-frequency oscillations.

[0090] At 412, the driver circuit 330 synchronizes the switching of the MAMR sensor 134 with the received write / read enable signal. The WR EN signal 324 serves as a control input. The driver circuit 330 can synchronize the MAMR sensor 134 with servo operation. The signal triggers the driver circuit 330 to adjust the current through the MAMR sensor 134 within a transition time window. This ensures that the MAMR sensor 134 is deactivated before the read / write head 132 moves from writing data to reading servo positioning information. The MAMR_IDAC 326 works in conjunction with the WR EN signal 324. It provides the appropriate current level during the active phase based on the calibrated MAMR sensor resistance. System-on-Chip

[0091] 5 illustrates an exemplary system-on-chip (SoC) 500 that may implement various aspects of a differential iMode driver for MAMR of storage media. SoC 500 may be implemented in any suitable device, such as a smartphone, netbook, tablet computer, access point, network-attached storage, camera, smart appliance, printer, set-top box, server, solid-state drive (SSD), magnetic tape drive, hard disk drive (HDD), storage drive, array, memory module, storage media controller, storage media interface, head-disk assembly, magnetic media pre-amplifier, automotive computing system, or any other suitable type of device (e.g., others described herein). Although described with reference to an SoC, the entities in FIG. 5 may also be implemented as other types of integrated circuits or embedded systems, such as an application-specific integrated-circuit (ASIC), a memory controller, a storage controller, a communications controller, an application-specific standard product (ASSP), a digital signal processor (DSP), a programmable SoC (PSoC), a system-in-package (SiP), or a field-programmable gate array (FPGA).

[0092] SoC 500 may be integrated with electronic circuitry, microprocessors, memory, input-output (I / O) control logic, communication interfaces, firmware, and / or software useful for providing the functionality of a computing device or magnetic storage system, such as any of the devices or components described herein (e.g., a hard disk drive). SoC 500 may also include an integrated data bus or interconnect fabric (not shown) that couples various components of the SoC for data communication or routing between the components. The integrated data bus, interconnect fabric, or other components of SoC 500 may be exposed or accessible through an external port, a parallel data interface, a serial data interface, a peripheral component interface, or any other suitable data interface. For example, components of SoC 500 may access or control external storage media or magnetic writing circuitry through an external interface or an off-chip data interface.

[0093] In this example, SoC 500 is shown with various components, including input / output (I / O) control logic 502 and a hardware-based processor 504 (processor 504), such as a microprocessor, processor core, application processor, or DSP. SoC 500 also includes memory 506, which may include any type and / or combination of RAM, SRAM, DRAM, non-volatile memory, ROM, one-time programmable (OTP) memory, multiple-time programmable (MTP) memory, flash memory, and / or other suitable electronic data storage. In some embodiments, processor 504 and code stored on memory 506 are implemented as part of a storage media controller or storage media interface. They provide various functions related to a differential iMode driver for MAMR of a storage media. These functions include read / write channel functions and resistance measurement calibration. In the context of the present disclosure, memory 506 stores data, code, instructions, or other information via non-transitory signals. It does not include carrier waves or transitory signals. SoC 500 may include a data interface for accessing additional or expandable off-chip storage media, including magnetic or solid-state memory (e.g., flash memory or NAND memory).

[0094] The SoC 500 may also include firmware 508, applications, programs, software, and / or an operating system, which may be embodied as processor-executable instructions maintained on the memory 506 for execution by the processor 504 to implement the functions of the SoC 500. The SoC 500 may also include other communication interfaces, such as a transceiver interface, for controlling or communicating with local on-chip (not shown) or off-chip communication transceiver components. Alternatively or additionally, the transceiver interface may also include or implement a signal interface for communicating radio frequency (RF), intermediate frequency (IF), or baseband frequency signals off-chip to facilitate wired or wireless communication through a transceiver, physical layer transceiver (PHY), or media access controller (MAC) coupled to the SoC 500. For example, SoC 500 may include a transceiver interface configured to provide differential iMode driver functionality to a network attached storage (NAS) device, for example, that contributes storage over a wired or wireless network.

[0095] In this example, SoC 500 also includes read / write channel 144, storage media controller 140, servo control unit 142, and MAMR sensor drive circuitry 136, which may be implemented separately as shown or combined with the storage components or data interface. Alternatively or additionally, SoC 500 may include an interface to a preamplifier and / or spindle / motor assembly of a magnetic media disk drive. Any of these entities may be embodied as separate or combined components, as described with reference to various aspects described herein. Examples of these components and / or entities, or corresponding functionality, are described with reference to the respective components or entities of environment 100 of FIG. 1 or the respective configurations illustrated in FIGS. 2 and / or 3.

[0096] The MAMR sensor drive circuitry 136 may be implemented independently or in combination with any suitable component or circuitry to implement aspects described herein. For example, the MAMR sensor drive circuitry may be implemented as part of a DSP, processor / storage bridge, I / O bridge, graphics processing unit, memory controller, storage controller, or arithmetic logic unit (ALU), etc. The MAMR sensor drive circuitry 136 may also be provided integrated with other entities of the SoC 500, such as the processor 504, memory 506, storage medium interface, or firmware 508 of the SoC 500. Alternatively or additionally, the MAMR sensor drive circuitry 136 and / or other components of the SoC 500 may be implemented as hardware, firmware, fixed logic circuitry, or any combination thereof.

[0097] As another example, consider Figure 6, which illustrates an exemplary storage media controller 600 in accordance with one or more aspects of a differential iMode driver for MAMR applications in HDDs. Generally, storage media controller 600 enables computing device 102 to access the contents of magnetic storage media, e.g., data or other services for an operating system, an application, or an application. The storage media controller may also write and read data for computing device 102 to and from the magnetic storage media with which the controller is associated.

[0098] In various aspects, storage media controller 600 or any combination of its components may be implemented as a storage drive controller (e.g., an HDD controller or HDD chipset), a storage media controller, a NAS controller, a storage media interface, a storage media endpoint, a storage media target, or a storage aggregate controller for magnetic storage media, solid-state storage media, or the like (e.g., a hybrid SSD / HDD storage system).

[0099] In some cases, storage media controller 600 is implemented similarly to or together with components of SoC 500, as described with reference to FIG. 5 . In other words, an instance of SoC 500 may be configured as a storage media controller, e.g., storage media controller 600, for managing magnetic storage media. In this example, storage media controller 600 includes input / output (I / O) control logic 602 and a processor 604, e.g., a microprocessor, microcontroller, processor core, application processor, or DSP. The storage media controller also includes a host interface 606 (e.g., a SATA, PCIe, NVMe, or fabric interface) and a storage media interface 608 (e.g., a magnetic media interface or a head-disk assembly (HDA) interface), which enable access to a host system (or fabric) and the storage media, respectively. In this example, the storage media interface includes separate instances of spindle interface 610 and preamp interface 612, which facilitate communication with, e.g., a head-disk assembly of a media drive.

[0100] In some embodiments, storage media controller 600 implements aspects of a differential iMode driver for MAMR applications in HDDs when managing or enabling access to a storage medium coupled to storage media interface 608. Storage media controller 600 may provide a storage interface for a host system via host interface 606. Storage access commands are received from the host system through this interface. These commands include commands to write data to or read data from a magnetic storage medium. iMode driver implementations achieve transition times of approximately 50, 30, 20, 10, and / or 5 nanoseconds for enhanced servo operation. As shown in FIG. 6 , storage media controller 600 includes servo control unit 142, read / write channel 144, and MAMR sensor drive circuitry 136. These components implement aspects of a differential iMode driver.

[0101] The servo control unit 142 is operatively coupled to the spindle interface 610, which may provide spindle or voice coil control for the magnetic media drive. The firmware or logic of the processor 604 and storage media controller 600 is implemented to provide multiple functions. These include MAMR sensor resistance measurement calibration, MAMR sensor current level adjustment, and various data writing or processing functions. All these functions are in conjunction with a differential iMode driver for the MAMR of the storage media.

[0102] The MAMR sensor drive circuitry 136 of the storage media controller 600 may also be implemented separately as shown, or in combination with the processor 604, the read / write channel 144, or the storage media interface 608. Examples of these components and / or entities, or corresponding functionality, are described with reference to the respective components or entities of the environment 100 of FIG. 1 or the respective configurations illustrated in FIG. 2 and / or FIG. 3. The MAMR sensor drive circuitry 136 may be implemented, either in whole or in part, as processor-executable instructions maintained by the controller's memory and executed by the processor 604 to implement various aspects and / or functionality of a differential iMode driver for MAMR applications in HDDs.

[0103] Although the subject matter described herein is described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific examples, features, or acts (including the order in which they are performed) described herein.

Claims

1. 1. An apparatus for facilitating high speed transitions during magnetic recording in microwave assisted magnetic recording (MAMR), the apparatus comprising: a driver circuit configured to provide a controlled differential bias current, said driver circuit having separate source and sink output terminals; a MAMR sensor coupled between the source output terminal and the sink output terminal, the MAMR sensor receiving the controlled differential bias current provided by the driver circuit therethrough, the MAMR sensor having a field input terminal and a field output terminal for generating a microwave field; and a common-mode feedback (CMFB) loop coupled to the field input terminal and the field output terminal of the MAMR sensor, the CMFB loop forming a feedback path with the driver circuit, the CMFB loop configured to detect a common-mode voltage (CMV) and adjust the controlled differential bias current to maintain CMV regulation of the MAMR sensor; An apparatus comprising:

2. 2. The apparatus of claim 1, wherein the source output terminal of the driver circuit comprises a positive-negative-positive (PNP) driver operating with a full controlled differential bias current, and the sink output terminal comprises a negative-negative-positive (NPN) driver operating with a portion of the controlled differential bias current.

3. The device of claim 1 , wherein the field inflow terminal and the field outflow terminal include a single-ended capacitor for frequency compensation that stabilizes a feedback signal of the feedback path including the CMFB loop.

4. 2. The apparatus of claim 1, wherein the CMFB loop is further configured to detect the CMV by sampling only a portion of a current through the MAMR sensor coupled between the source output terminal and the sink output terminal of the driver circuit.

5. The apparatus of claim 1 , wherein the CMFB loop is further configured to maintain the CMV tuning of the MAMR sensor at approximately zero volts.

6. 2. The apparatus of claim 1, wherein the CMFB loop is further configured to sample a fraction of the controlled differential bias current through the MAMR sensor to maintain CMV regulation at approximately zero volts while enabling direct current control of the MAMR sensor.

7. 7. The apparatus of claim 1, wherein the driver circuit is further configured to switch the controlled differential bias current through the MAMR sensor with a rise or fall time of 10 nanoseconds or less.

8. 7. The apparatus of claim 1, wherein the driver circuit is further configured to switch the controlled differential bias current through the MAMR sensor with a rise or fall time of 5 nanoseconds or less.

9. 7. The apparatus of claim 1, wherein the driver circuit is further configured to switch the controlled differential bias current through the MAMR sensor based on a write / read (WR) enable signal.

10. The apparatus of claim 1 , wherein the driver circuit is further configured to determine a value of the controlled differential bias current based on a resistance measurement calibration of the MAMR sensor.

11. 1. A hard disk drive system that facilitates high speed transitions during microwave assisted magnetic recording (MAMR) magnetic recording, the hard disk drive system comprising: A write head using a MAMR sensor; and current-mode (iMode) driver circuitry configured to drive a controlled differential bias current through the field-in and field-out terminals of the MAMR sensor; and the iMode driver circuit configuration comprises: a driver circuit configured to provide a controlled differential bias current, the driver circuit including separate source and sink output terminals through which the MAMR sensor receives the controlled differential bias current; and a common-mode feedback (CMFB) loop coupled to the field-input terminal and the field-output terminal of the MAMR sensor, the CMFB loop forming a feedback path with the driver circuit, the CMFB loop configured to detect a common-mode voltage (CMV) and adjust the controlled differential bias current to maintain CMV regulation of the MAMR sensor; A hard disk drive system comprising:

12. 12. The hard disk drive system of claim 11, wherein the source output terminal of the driver circuit includes a positive-negative-positive (PNP) driver based on a complete controlled differential bias current, and the sink output terminal includes a negative-negative-positive (NPN) driver based on a portion of the controlled differential bias current.

13. 12. The hard disk drive system of claim 11, wherein the CMFB loop is further configured to detect the CMV by sampling only a portion of a current through the MAMR sensor coupled between the source output terminal and the sink output terminal of the driver circuit.

14. 12. The hard disk drive system of claim 11, wherein the CMFB loop is further configured to maintain the CMV adjustment of the MAMR sensor at approximately zero volts.

15. 12. The hard disk drive system of claim 11, wherein the driver circuitry is further configured to switch the controlled differential bias current through the MAMR sensor with a rise or fall time of 5 nanoseconds or less.

16. 12. The hard disk drive system of claim 11, wherein the driver circuit is further configured to switch the controlled differential bias current through the MAMR sensor synchronously with a write / read (WR) enable signal.

17. 17. The hard disk drive system of claim 11, wherein the driver circuit is further configured to determine a value of the controlled differential bias current based on a resistance measurement calibration of the MAMR sensor.

18. 1. A method for facilitating fast transitions during magnetic recording in microwave-assisted magnetic recording (MAMR), the method comprising: providing, by a driver circuit, a controlled differential bias current to a MAMR sensor of the magnetic media read / write channel; maintaining common mode voltage (CMV) regulation of the MAMR sensor by a common mode feedback (CMFB) loop coupled to field in and field out terminals of the MAMR sensor; and The controlled differential bias current through the MAMR sensor is A rise time of 10 nanoseconds or less; and Fall times of 10 nanoseconds or less Switching stage A method comprising:

19. The switching of the controlled differential bias current across the MAMR sensor comprises: A rise time of 5 nanoseconds or less; and Fall times of 5 nanoseconds or less; The method of claim 18, wherein

20. receiving a write / read (WR) enable signal; and synchronizing the switching of the controlled differential bias current with the WR enable signal; 20. The method of claim 18 or 19, further comprising:

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