Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device and a method of manufacturing the same, capable of achieving both suppression of reduction in breakdown voltage and reduction in on-resistance.SOLUTION: A first semiconductor layer 3 located on the substrate 2 and having a first conductivity type, an insulator 4 located in a recess provided in the first semiconductor layer, a second semiconductor layer 5 located at least in the recess and having a first conductivity type, an insulating layer 6 located on the first semiconductor layer and the insulator, a gate 7 located on the insulating layer, a source region 11 and a drain region 13 having the first conductivity type, and a first impurity region 12 located around the source region; And a second impurity region 14 which is in contact with the bottom surface of the second semiconductor layer and has the first conductivity type, wherein the diffusion coefficient of the impurity in the second semiconductor layer is higher than the diffusion coefficient of the impurity in the first semiconductor layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor chip having a main surface, a high-potential region formed in a surface layer portion of the main surface, a low-potential region formed in the surface layer portion of the main surface at a distance from the high-potential region, a first conductivity type drift region formed in a region between the high-potential region and the low-potential region in the surface layer portion of the main surface, and a first conductivity type resurf region partially formed in the surface layer portion of the drift region so as to expose from the main surface a region that serves as a current path in the drift region, the first conductivity type resurf region having an impurity concentration higher than that of the drift region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2021 / 161835

[0004] [overview] An object according to one aspect of the present disclosure is to provide a semiconductor device that can achieve both a high breakdown voltage and a reduced on-resistance, and a method for manufacturing the semiconductor device.

[0005] A semiconductor device according to one aspect of the present disclosure comprises a first semiconductor layer located on a substrate and having a first conductivity type; an insulator located within a recess provided in the first semiconductor layer; a second semiconductor layer located within the recess at least directly below the insulator and having the first conductivity type; an insulating layer located on the first semiconductor layer and on the insulator; and a gate located on the insulating layer, wherein the first semiconductor layer includes a source region and a drain region having the first conductivity type, a first impurity region located around the source region, and a second impurity region in contact with a bottom surface of the second semiconductor layer and having the first conductivity type, and the diffusion coefficient of the impurity in the second semiconductor layer is higher than the diffusion coefficient of the impurity in the first semiconductor layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is an enlarged view of the device region containing the LDMOS. [Figure 3] FIG. 3 is a schematic cross-sectional view taken along line III-III in FIG. [Figure 4A] FIG. 4A is an enlarged view of a main part of the area surrounded by the dashed line shown in FIG. [Figure 4B] FIG. 4B is an enlarged cross-sectional view of a main part of the semiconductor device according to the first modification. [Figure 4C] FIG. 4C is an enlarged cross-sectional view of a main part of a semiconductor device according to a second modification. [Figure 4D] FIG. 4D is an enlarged cross-sectional view of a main part of a semiconductor device according to a third modification. [Figure 4E] FIG. 4E is an enlarged cross-sectional view of a main part of a semiconductor device according to a fourth modification. [Figure 4F] FIG. 4F is an enlarged cross-sectional view of a main part of a semiconductor device according to a fifth modification. [Figure 5] FIG. 5 is a schematic cross-sectional view for explaining a method for manufacturing an LDMOS included in a semiconductor device according to a fifth modification. [Figure 6] FIG. 6 is a schematic cross-sectional view for explaining a method for manufacturing an LDMOS included in a semiconductor device according to the fifth modification. [Figure 7] FIG. 7 is a schematic cross-sectional view for explaining a method for manufacturing an LDMOS included in a semiconductor device according to the fifth modification. [Figure 8] FIG. 8 is a schematic cross-sectional view for explaining a method for manufacturing an LDMOS included in a semiconductor device according to the fifth modification. [Figure 9] FIG. 9 is a schematic cross-sectional view for explaining a method for manufacturing an LDMOS included in a semiconductor device according to the fifth modification. [Figure 10] FIG. 10 is a schematic cross-sectional view for explaining a method for manufacturing an LDMOS included in a semiconductor device according to the fifth modification. [Figure 11] FIG. 11 is a schematic cross-sectional view for explaining a method for manufacturing an LDMOS included in a semiconductor device according to the fifth modification. [Figure 12] FIG. 12 is a schematic cross-sectional view for explaining a method for manufacturing an LDMOS included in a semiconductor device according to the fifth modification. [Figure 13] FIG. 13 is a schematic cross-sectional view for explaining a part of the method for manufacturing the semiconductor device according to the embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view for explaining a part of the method for manufacturing a semiconductor device according to the second modification. [Figure 15] FIG. 15 is a schematic cross-sectional view for explaining a part of a method for manufacturing a semiconductor device according to the third modification. [Figure 16] FIG. 16 is a schematic cross-sectional view for explaining a part of a method for manufacturing a semiconductor device according to the third modification. [Figure 17] FIG. 17 is a schematic cross-sectional view for explaining a part of a method for manufacturing a semiconductor device according to the fourth modification.

[0007] [Detailed explanation] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, identical elements or elements having the same functions will be designated by the same reference numerals, and duplicate explanations will be omitted. In this specification, the term "same" and similar words are not limited to "completely identical." Furthermore, since the drawings are intended to conceptually explain the embodiments, the dimensions and ratios of the components shown may differ from the actual dimensions.

[0008] FIG. 1 is a schematic plan view showing a semiconductor device according to this embodiment. As shown in FIG. 1, the semiconductor device 100 includes, for example, a chip-shaped integrated circuit (IC) device. The semiconductor device 100 may be referred to as an SSI (Small Scale IC), an MSI (Middle Scale IC), an LSI (Large Scale IC), a VLSI (Very Large Scale IC), an ULSI (Ultra Large Scale IC), or the like based on the number of circuit elements integrated therein. The semiconductor device 100 is used as, for example, an LSI on which a reference voltage circuit (VREF circuit) is mounted. In this embodiment, the semiconductor device 100 includes a rectangular parallelepiped chip 101 (semiconductor chip).

[0009] The chip 101 has a first main surface 103, which is the main surface, and a second main surface 104, which is the back surface. The chip 101 has a first side surface 105A, a second side surface 105B, a third side surface 105C, and a fourth side surface 105D, which connect the first main surface 103 and the second main surface 104. Hereinafter, the thickness direction of the chip 101 corresponds to the Z-axis direction, the direction perpendicular to the thickness direction corresponds to the X-axis direction, and the direction perpendicular to the Z-axis direction and the X-axis direction corresponds to the Y-axis direction. Hereinafter, the view from the Z-axis direction will be referred to as a planar view, and the directions extending in the X-axis and Y-axis directions will be referred to as planar directions. Note that the direction toward the first main surface 103 in the Z-axis direction will be referred to as the upward direction, and the direction toward the second main surface 104 in the Z-axis direction will be referred to as the downward direction. Hereinafter, the view from the Z-axis direction will also be simply referred to as a planar view.

[0010] Each of the first main surface 103 and the second main surface 104 is a surface that extends perpendicular to the Z-axis direction. In a plan view, the planar shape of each of the first main surface 103 and the second main surface 104 is quadrangular, but is not limited to this. Each of the first side surface 105A and the second side surface 105B extends along the X-axis direction in a plan view. Each of the third side surface 105C and the fourth side surface 105D extends along the Y-axis direction in a plan view.

[0011] The semiconductor device 100 includes multiple device regions 10. A gap is provided between each device region 10 and each side surface (first side surface 105A to fourth side surface 105D) of the chip 101. The number, arrangement, and shape of the device regions 10 are arbitrary and are not limited to a specific number, arrangement, or shape. Various devices are formed within each device region 10. The devices may include, for example, at least one of a semiconductor switching device such as a high-side switch or a low-side switch, a semiconductor rectifier device, and a passive device. The semiconductor switching device may include at least one of a JFET (Junction Field Effect Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), and an IGBT (Insulated Gate Bipolar Junction Transistor).

[0012] A metal-oxide-semiconductor field-effect transistor (MOSFET) can be used as the MISFET. The MOSFET may be an enhancement type or a depletion type. The MOSFET may have a planar structure or a vertical structure. The MISFET can also be a power transistor. MISFETs with drain-source voltages of high voltage (HV: e.g., 100 V to 1000 V), medium voltage (MV: e.g., 30 V to 100 V), and low voltage (LV: e.g., 1 V to 30 V) are also known. Additionally, the device region 10 may include optical devices such as a light-emitting element and a light-receiving element.

[0013] In this embodiment, the semiconductor material constituting the chip 101 is silicon (Si), but is not limited to this. Compound semiconductors can also be used as the semiconductor material constituting the chip 101. Compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and alloy semiconductors using these semiconductors. III-V compound semiconductors are, for example, Ga-containing semiconductors such as GaAs and GaN. IV-IV compound semiconductors are, for example, Si-containing semiconductors such as SiC and SiGe.

[0014] An LDMOS 102 (Lateral double-diffused MOS) is formed in at least one of the plurality of device regions 10. The structure of the LDMOS 102 will be described below.

[0015] FIG. 2 is an enlarged view of a device region 10 including an LDMOS 102, and FIG. 3 is a schematic cross-sectional view taken along line III-III in FIG. 2. FIG. 4A is an enlarged view of a region surrounded by a dashed line in FIG. 3. As shown in FIGS. 2, 3, and 4A, the LDMOS 102 includes a substrate 2, a first semiconductor layer 3 having a first conductivity type located on the substrate 2, an insulator 4 located on the first semiconductor layer 3, a second semiconductor layer 5 located directly below the insulator 4, an insulating layer 6 located on the first semiconductor layer 3 and the insulator 4, and a gate 7 located on the insulating layer 6. Although not shown, the LDMOS 102 is surrounded by an element isolation structure. In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but this is not limiting. The first conductivity type may be p-type and the second conductivity type may be n-type. Note that the insulating layer 6 is omitted from FIG. 2.

[0016] Although not shown, a buried region having the second conductivity type may be formed at or near the boundary between the substrate 2 and the first semiconductor layer 3. When such a buried region is formed, in one example, the buried region is formed so as to straddle the boundary between the substrate 2 and the first semiconductor layer 3. The thickness of the buried region is, for example, not less than 1 μm and not more than 3 μm. The buried region is separated from the body region, the resurf region, etc., which will be described later.

[0017] In this embodiment, the substrate 2 is a high-resistivity silicon substrate having the second conductivity type. The impurity concentration of the substrate 2 is set to a relatively low value. In this embodiment, the impurity concentration of the substrate 2 is set to, for example, 1.0×10 13 cm -3 Over 1.0 x 10 14 cm -3 The following is the result.

[0018] The first semiconductor layer 3 is a crystalline layer formed on the substrate 2. In one example, the first semiconductor layer 3 is an epitaxial layer (single crystalline layer) using the substrate 2 as a seed. The impurity concentration of the first semiconductor layer 3 is, for example, 1.0×10 15 cm -3 Over 1.0 x 10 16 cm -3 The thickness of the first semiconductor layer 3 is, for example, not less than 1 μm and not more than 10 μm. The first semiconductor layer 3 is provided with a recess 3 a in which the insulator 4 and the second semiconductor layer 5 are located. The recess 3 a has a substantially oval ring shape in a plan view. The recess depth of the recess 3 a along the Z-axis direction is, for example, not less than 100 nm and not more than 1000 nm.

[0019] The first semiconductor layer 3 has a source region 11 (first contact region), a body region 12 (first impurity region), a drain region 13 (second contact region), a first resurf region 14 (second impurity region), and a second resurf region 15 (third impurity region). When the buried region is formed in the first semiconductor layer 3, the source region 11, the body region 12, the drain region 13, the first resurf region 14, and the second resurf region 15 are each separated from the buried region.

[0020] The source region 11 is a region that forms part of the current path of the LDMOS 102 and functions as the source of the LDMOS 102, and has a first conductivity type. The source region 11 is provided at least on the surface of the first semiconductor layer 3, and is a contact region that comes into contact with wiring (not shown). For example, a source potential is applied to the source region 11 from outside the semiconductor device 100 via the wiring. In one example, the source region 11 has an oval shape in a plan view. The dimension of the source region 11 along the Z-axis direction is, for example, 0.1 μm or more and 0.5 μm or less. The impurity concentration of the source region 11 is, for example, 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The following is the result.

[0021] The body region 12 is a region (well region) covering the bottom and sides of the source region 11, and has the second conductivity type. In one example, the body region 12 has an oval ring shape located around the source region 11 in a plan view, and is in contact with the source region 11. Therefore, a portion 12a of the body region 12 is located closer to the drain region 13 than the source region 11. The portion 12a is provided on at least the surface of the first semiconductor layer 3 and overlaps the gate 7 in the Z-axis direction, and can form part of the current path of the LDMOS 102. The portion 12a can function as a channel of the LDMOS 102. The dimension of the body region 12 along the Z-axis direction is, for example, 0.1 μm or more and 3 μm or less. The impurity concentration of the body region 12 is, for example, 1.0×10 16 cm -3 Over 1.0 x 10 18 cm -3 The body region 12 may have an elliptical ring shape or a polygonal ring shape such as a square ring shape in a plan view.

[0022] The drain region 13 is a region that forms part of the current path of the LDMOS 102 and functions as the drain of the LDMOS 102, and has the first conductivity type. The drain region 13 is provided at least on the surface of the first semiconductor layer 3, and is a contact region that comes into contact with wiring (not shown). For example, a drain potential is applied to the drain region 13 from outside the semiconductor device 100 via the wiring. In one example, the drain region 13 has a square ring shape surrounding the source region 11 and the gate 7 in a plan view, but is not limited to this. The drain region 13 may have an oval ring shape in a plan view. The dimension of the drain region 13 along the Z-axis direction is, for example, 0.1 μm or more and 0.5 μm or less. The impurity concentration of the drain region 13 is, for example, 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The following is the result.

[0023] The first resurf region 14 is a region located around the drain region 13 and in contact with at least the bottom surface 5a of the second semiconductor layer 5, and has a first conductivity type. In this embodiment, the first resurf region 14 is in contact with a portion of the drain region 13, but this is not limiting. The first resurf region 14 may overlap the gate 7 in the Z-axis direction. Like the drain region 13, the first resurf region 14 can form a portion of the current path of the LDMOS 102. The first resurf region 14 is formed by impurities in the second semiconductor layer 5 diffusing into the first semiconductor layer 3 (details will be described later). Therefore, the first resurf region 14 is formed around the second semiconductor layer 5. The impurity concentration of the first resurf region 14 is higher than the impurity concentration of the second resurf region 15, and is, for example, 1.0×10 17 cm -3 Over 1.0 x 10 20 cm -3 The following is the result.

[0024] In this embodiment, the first RESURF region 14 has a first impurity portion 14a in contact with the bottom surface 5a of the second semiconductor layer 5 in the Z-axis direction, and a second impurity portion 14b located closer to the source region 11 than the first impurity portion 14a in the Y-axis direction. The first impurity portion 14a is in contact with the drain region 13. The second impurity portion 14b is in contact with the side surface 5b of the second semiconductor layer 5 and is located between the source region 11 and the second semiconductor layer 5. A part of the second impurity portion 14b may be in contact with the insulator 4. The second impurity portion 14b is separated from the insulating layer 6, but this is not limiting.

[0025] The second resurf region 15 is a region located around the first resurf region 14 and in contact with at least the drain region 13, and has the first conductivity type. In this embodiment, the second resurf region 15 is in contact with the bottom surface 13a of the drain region 13 and the first resurf region 14, and surrounds the first resurf region 14. The second resurf region 15 is separated from the body region 12. Like the drain region 13 and the first resurf region 14, the second resurf region 15 can form part of the current path of the LDMOS 102. A part 15a of the second resurf region 15 is located closer to the source region 11 than the insulator 4 in the Y-axis direction, and overlaps with the gate 7 in the Z-axis direction. The impurity concentration of the second resurf region 15 is lower than the impurity concentration of the first resurf region 14, and is, for example, 1.0×10 15 cm -3 Over 1.0 x 10 18 cm -3 The following is the result.

[0026] The insulator 4 is located within the recess 3a of the first semiconductor layer 3 and overlaps the second semiconductor layer 5 in the Z-axis direction. In this embodiment, the entire insulator 4 is a buried insulator (STI: Shallow Trench Isolation) located on the second semiconductor layer 5 in the Z-axis direction. The insulator 4 may be, for example, an insulating oxide such as silicon oxide or aluminum oxide, or an insulating nitride such as silicon nitride. The thickness of the insulator 4 is adjusted appropriately depending on the depth of the recess 3a and the thickness of the second semiconductor layer 5, and is, for example, 100 nm or more and 800 nm or less.

[0027] The second semiconductor layer 5 is a semiconductor layer located in the recess 3a of the first semiconductor layer 3 and directly below the insulator 4, and has the first conductivity type. The second semiconductor layer 5 covers the entire bottom surface of the recess 3a, but is not limited to this. In this embodiment, the second semiconductor layer 5 is a semiconductor layer having a lower crystallinity than the first semiconductor layer 3, such as a polysilicon layer. In other words, the crystallinity of the second semiconductor layer 5 is lower than that of the first semiconductor layer 3. Therefore, the diffusion coefficient of impurities and the like present in the second semiconductor layer 5 is higher than the diffusion coefficient of impurities and the like present in the first semiconductor layer 3. In one example, the diffusion coefficient of the impurities in the second semiconductor layer 5 is 5 to 500 times the diffusion coefficient of the impurities in the first semiconductor layer 3. The second semiconductor layer 5 is deposited in the recess 3a by a known method, such as chemical vapor deposition (CVD). The thickness of the second semiconductor layer 5 is, for example, 10 to 500 nm. The impurity concentration of the second semiconductor layer 5 is, for example, 1.0×10 17 cm -3 Over 1.0 x 10 20 cm -3 The following is the result.

[0028] The insulating layer 6 is an insulating layer (gate insulating film) provided on the surface of the first semiconductor layer 3, and is located between the first semiconductor layer 3 and the gate 7. The insulating layer 6 may have a single-layer structure or a multilayer structure. The insulating layer 6 may be formed of an insulating oxide such as silicon oxide or aluminum oxide, or an insulating nitride such as silicon nitride. The insulating layer 6 may include a LOCOS (Local Oxidation of Silicon) film formed by selective oxidation of the first semiconductor layer 3. Although not shown, the insulating layer 6 is provided with an opening for exposing a portion of the source region 11, an opening for exposing a portion of the drain region 13, and the like.

[0029] The gate 7 is a conductor located on the insulating layer 6 and has a frame shape surrounding the source region 11 in a plan view. The gate 7 includes, for example, a metal film, an alloy film, or conductive polysilicon. When the gate 7 includes conductive polysilicon, the conductive polysilicon may include either a first conductivity type impurity or a second conductivity type impurity in terms of the conductivity of the gate 7. A portion of the gate 7 is located between the source region 11 and the drain region 13 in the Y-axis direction in a plan view. At least a portion of the first semiconductor layer 3 overlapping the gate 7 functions as a channel region of the LDMOS 102. The channel region is located, for example, between the body region 12 and the second RESURF region 15 in the first semiconductor layer 3. In the channel region, conduction and non-conduction of the current path between the source region 11 and the drain region 13 are controlled depending on the potential applied to the gate 7.

[0030] In the LDMOS 102 included in the semiconductor device 100 according to this embodiment described above, the second semiconductor layer 5 is located directly below the insulator 4, which is an STI. The diffusion coefficient of impurities in the second semiconductor layer 5 is higher than that of impurities in the first semiconductor layer 3. As a result, during the fabrication of the semiconductor device 100, the impurities in the second semiconductor layer 5 diffuse into the first semiconductor layer 3 (details will be described later). Therefore, the first RESURF region 14, which has a high impurity concentration, is selectively provided below and in the vicinity of the insulator 4. That is, the first RESURF region 14 can be selectively formed thinly directly below the recess 3a. This enables the LDMOS 102 to achieve both a high breakdown voltage and a reduced on-resistance.

[0031] Typically, the first resurf region is formed by the same method as the second resurf region 15 described above (i.e., by introducing impurities into the first semiconductor layer 3). In this case, the shape, depth, etc. of the first resurf region tend to vary depending on the shape, quality, etc. of the insulator 4. On the other hand, with the LDMOS 102 included in the semiconductor device 100 according to this embodiment, variations in the shape, etc. of the first resurf region 14 are effectively suppressed even if the shape, quality, etc. of the insulator 4 vary. Furthermore, the performance and shape of the first resurf region 14 can be adjusted by adjusting the shape, impurity concentration, formation position, thickness, etc. of the second semiconductor layer 5. Therefore, according to this embodiment, the characteristics of the first resurf region 14, and therefore the breakdown voltage and on-resistance of the LDMOS 102, can be easily stabilized and adjusted.

[0032] Next, a semiconductor device according to a modification will be described with reference to Figures 4B to 4F. In the following, descriptions of parts that overlap with the above embodiment will be omitted.

[0033] FIG. 4B is an enlarged cross-sectional view of a main portion of a semiconductor device according to a first modification. As shown in FIG. 4B, the semiconductor device according to the first modification differs from the above embodiment in that an insulator 4A and a second semiconductor layer 5A are formed in the recess 3a of the first semiconductor layer 3. The second semiconductor layer 5A covers the entire surface of the recess 3a. The second semiconductor layer 5A has a first portion 51 located directly under the insulator 4A, a second portion 52 located between the insulator 4A and the body region 12 in the Y-axis direction, and a third portion 53 located between the insulator 4A and the drain region 13 in the Y-axis direction. The second portion 52 and the third portion 53 each contact the insulating layer 6. In addition, the third portion 53 and the drain region 13 contact each other. The insulator 4A is surrounded by the second semiconductor layer 5A within the recess 3a. Therefore, the insulator 4A is separated from the first semiconductor layer 3.

[0034] In the first modified example, the second semiconductor layer 5A is formed in the recess 3a, and therefore the second impurity portion 14b included in the first RESURF region 14A is in contact with the insulating layer 6. Therefore, the second impurity portion 14b is located between the source region 11 and the second portion 52 of the second semiconductor layer 5A. It can also be said that the second impurity portion 14b in the first modified example is wider than that in the above embodiment.

[0035] The first modified example described above also achieves the same effects as the above embodiment. In addition, in the first modified example, the second semiconductor layer 5A has the third portion 53, which makes it easier for current to flow from the drain region 13 to the first resurf region 14A via the second semiconductor layer 5A. Furthermore, compared to the above embodiment, the first resurf region 14A (particularly the second impurity portion 14b) is wider. Therefore, in the first modified example, the on-resistance of the LDMOS can be effectively reduced.

[0036] FIG. 4C is an enlarged cross-sectional view of a main portion of a semiconductor device according to a second modification. As shown in FIG. 4C, the semiconductor device according to the second modification differs from the above embodiment in that the side surface of the second semiconductor layer 5B is spaced apart from the recess 3a of the first semiconductor layer 3. In other words, an insulator (second insulator) different from that of the above embodiment is provided between the inner surface of the second semiconductor layer 5B and the side surface 3a1 of the recess 3, and between the outer surface of the second semiconductor layer 5B and the side surface 3a2 of the recess 3. In the second modification, the second semiconductor layer 5B covers a portion of the bottom surface of the recess 3a, and the insulator 4B has a first insulating portion 4a located between the second semiconductor layer 5B and the side surface 3a1 of the recess 3a, and a second insulating portion 4b located between the second semiconductor layer 5B and the side surface 3a2 of the recess 3a. The first insulating portion 4a and the second insulating portion 4b each constitute a component corresponding to the second insulator. The first insulating portion 4a is a portion that covers the inner surface of the second semiconductor layer 5B and has an oval ring shape that follows the side surface 3a1. The first insulating portion 4a is a portion that covers the outer surface of the second semiconductor layer 5B and has an oval ring shape that follows the side surface 3a1. From the viewpoint of the on-resistance of the LDMOS 102, the width of the first insulating portion 4a and the width of the second insulating portion 4b are each, for example, 2% to 15% of the width of the recess 3a.

[0037] In the second modification, by forming the insulator 4B and the second semiconductor layer 5B, the first resurf region 14B is formed only directly below the recess 3a, but this is not limited to this. Depending on the degree of impurity diffusion from the second semiconductor layer 5B, a portion of the first resurf region 14B may be located between the recess 3a and the source region 11. In other words, the portion of the first resurf region 14B may be located between the side surface 3a1 and the source region 11.

[0038] The second modification described above also achieves the same effects as the above embodiment. In addition, in the second modification, the first resurf region 14B is not formed, or is less likely to be formed, between the source region 11 and the second semiconductor layer 5B. This makes it possible to effectively achieve a high breakdown voltage for the LDMOS according to the second modification.

[0039] 4D is an enlarged cross-sectional view of a main portion of a semiconductor device according to a third modification. As shown in FIG. 4D, the semiconductor device according to the third modification differs from the first modification in that the side surfaces 3a1 and 3a2 of the recess 3a in the first semiconductor layer 3 are covered with a second insulator 4D. Therefore, in the third modification, similar to the first modification, a second semiconductor layer 5C including a first portion 51A, a second portion 52A, and a third portion 53A, and an insulator 4C surrounded by the second semiconductor layer 5C within the recess 3a, are formed. However, in the third modification, the second portion 52A and the third portion 53A are spaced apart from the first semiconductor layer 3.

[0040] The second insulator 4D includes a first insulating portion 4D1 located between a side surface 3a1 of the recess 3a and the second portion 52A of the second semiconductor layer 5C, and a second insulating portion 4D2 located between a side surface 3a2 of the recess 3a and the third portion 53A of the second semiconductor layer 5C. The first insulating portion 4D1 and the second insulating portion 4D2 are formed simultaneously, for example, by selective etching of the insulating film covering the recess 3a. In one example, the first insulating portion 4D1 has a shape similar to that of the first insulating portion 4a of the second modified example, and the second insulating portion 4D2 has a shape similar to that of the second insulating portion 4b of the second modified example.

[0041] In the third modification, the second insulator 4D and the second semiconductor layer 5C are formed, so that the first resurf region 14C is formed only directly below the recess 3a, but this is not limitative. Depending on the degree of impurity diffusion from the second semiconductor layer 5C, a part of the first resurf region 14C may be located between the recess 3a and the source region 11.

[0042] The third modification described above also achieves the same effects as the second modification. Additionally, in the third modification, a large amount of impurities can be contained in the second semiconductor layer 5C, thereby effectively increasing the impurity concentration in the first RESURF region 14C. Therefore, the on-resistance of the LDMOS according to the third modification can be effectively reduced.

[0043] FIG. 4E is an enlarged cross-sectional view of a main portion of a semiconductor device according to a fourth modification. As shown in FIG. 4E, the semiconductor device according to the fourth modification differs from the above embodiment in that the entire second semiconductor layer 5D is separated from the first semiconductor layer 3. Specifically, an insulating layer 4E1 included in the insulator 4E is located between the first semiconductor layer 3 and the second semiconductor layer 5D. The insulating layer 4E1 is a layered insulator located on the surface of the recess 3a. In one example, the insulating layer 4E1 is formed by CVD, oxidation, or the like before the formation of the second semiconductor layer 5D. To ensure good impurity diffusion from the second semiconductor layer 5D to the first semiconductor layer 3, the insulating layer 4E1 has a thickness of, for example, 5 nm or more and 50 nm or less. The insulating portion 4E2 included in the insulator 4E corresponds to the insulator 4 in the above embodiment. In the fourth modification, the insulating layer 4E1 and the insulating portion 4E2 are integrated to form the insulator 4E in the recess 3a.

[0044] In the fourth modification, the insulator 4E (particularly, the insulating layer 4E1) and the second semiconductor layer 5D are formed, so that the first resurf region 14D is formed only directly below the recess 3a, but this is not limited to this. Depending on the degree of impurity diffusion from the second semiconductor layer 5D, a portion of the first resurf region 14D may be located between the recess 3a and the source region 11. Note that the thickness of the insulating layer 4E1 may be partially adjusted, so that the first resurf region 14D is formed only directly below the recess 3a.

[0045] The fourth modified example described above also achieves the same effects as the above embodiment. In addition, in the fourth modified example, there is no contact between the second semiconductor layer 5D and the first semiconductor layer 3, so that problems in the LDMOS caused by such contact do not occur. Furthermore, in the fourth modified example, the first RESURF region 14D can be thinned effectively.

[0046] FIG. 4F is an enlarged cross-sectional view of a main portion of a semiconductor device according to a fifth modification. As shown in FIG. 4F, the semiconductor device according to the fifth modification differs from the above embodiment in that, like the fourth modification, the entire second semiconductor layer 5E is separated from the first semiconductor layer 3. In the fifth modification, an insulating layer 4F is located between the first semiconductor layer 3 and the second semiconductor layer 5E. The insulating layer 4F is a layered insulator similar to the insulating layer 4E1 of the fourth modification. The second semiconductor layer 5E has a first portion 51B, a second portion 52B, and a third portion 53B, similar to the third modification. Similarly to the third modification, an insulating layer 4F is located between the side surface 3a1 of the recess 3a and the second portion 52B of the second semiconductor layer 5E, and between the side surface 3a2 of the recess 3a and the third portion 53B of the second semiconductor layer 5E. Also, similar to the third modification, an insulator 4G surrounded by the second semiconductor layer 5E is formed within the recess 3a.

[0047] In the fifth modification, the insulating layer 4F and the second semiconductor layer 5E are formed, so that the first resurf region 14E is formed only directly below the recess 3a, but this is not limiting. Depending on the degree of impurity diffusion from the second semiconductor layer 5E, a portion of the first resurf region 14E may be located between the recess 3a and the source region 11. Note that the thickness of the insulating layer 4F may be partially adjusted so that the first resurf region 14E is formed only directly below the recess 3a.

[0048] The fifth modified example described above can also achieve the same effects as the fourth modified example.

[0049] Next, an example of a method for manufacturing the LDMOS included in the semiconductor device according to the fifth modification will be described with reference to Figures 5 to 12. Each of Figures 5 to 12 is a schematic cross-sectional view for explaining the method for manufacturing the LDMOS included in the semiconductor device according to the fifth modification.

[0050] First, as shown in FIG. 5 , a recess 3a is formed in a first semiconductor layer 3 located on a substrate 2 and having a first conductivity type (first step). In the first step, for example, the first semiconductor layer 3 is formed as a single-crystal semiconductor layer by epitaxially growing the first semiconductor layer 3 on the substrate 2. Here, the formation of the first semiconductor layer 3 may be performed after doping a portion of the substrate 2 with impurities of a second conductivity type. In this case, a buried region (not shown) may be formed. Next, the recess 3a is formed in the first semiconductor layer 3. For example, a mask (not shown) is selectively formed on the first semiconductor layer 3, and then the recess 3a is formed by selectively etching the first semiconductor layer 3 using the mask. The mask is, for example, a silicon oxide film, but is not limited to this. The etching of the first semiconductor layer 3 may be dry etching or wet etching.

[0051] Next, as shown in FIGS. 6 and 7, an insulating layer 4F and a second semiconductor layer 5E are formed in the recess 3a of the first semiconductor layer 3 (second step), and then an insulator 4G is formed in the recess 3a to cover at least a portion of the second semiconductor layer 5E (third step). In the second step, as shown in FIG. 6, an insulating layer 21 and a semiconductor layer 22 are first formed in this order on the first semiconductor layer 3. The insulating layer 21 is a layered insulator that will later become the insulating layer 4F (second insulating layer) and covers the surface of the recess 3a. The semiconductor layer 22 is a layered semiconductor that will later become the second semiconductor layer 5E and is located on the insulating layer 21. The diffusion coefficient of impurities in the semiconductor layer 22 is higher than the diffusion coefficient of impurities in the first semiconductor layer 3. Next, although not shown, portions of the insulating layer 21 and the semiconductor layer 22 that are located outside the recess 3a are removed. For example, these portions are removed by selective etching using a mask (not shown). As a result, the insulating layer 4F and the second semiconductor layer 5E are formed as shown in FIG. 7.

[0052] Next, in the third step, an insulator 4G is selectively formed to fill the recess 3a. Then, a cover film 31 is formed on the first semiconductor layer 3, the insulating layer 4F, the second semiconductor layer 5E, and the insulator 4G. The cover film 31 is an insulating film formed to protect the surface of the first semiconductor layer 3. The cover film 31 is formed by a known method such as CVD. In one example, the cover film 31 is a silicon oxide film, but is not limited to this.

[0053] Next, as shown in FIG. 8 , an impurity region 41 having the second conductivity type is formed in the first semiconductor layer 3 (fourth step). In the fourth step, a mask (not shown) is used to introduce (do) an impurity having the second conductivity type into a portion of the first semiconductor layer 3, thereby forming the impurity region 41. The impurity region 41 is a region that will later become the body region 12 and is separated from the recess 3a. The cover film 31 makes it difficult for the surface of the first semiconductor layer 3 to be damaged when the impurity is introduced into the first semiconductor layer 3. Immediately before or after the fourth step, an impurity region 42 having the second conductivity type is formed in the first semiconductor layer 3. Using another mask (not shown), an impurity having the first conductivity type is introduced into another portion of the first semiconductor layer 3, thereby forming the impurity region 42. The impurity region 42 is a region that will later become the second RESURF region 15 and is provided around the recess 3a.

[0054] Next, as shown in FIG. 9, an impurity E1 (second impurity) having the first conductivity type is introduced into the second semiconductor layer 5E. In one example, the introduction of the impurity E1 is performed after the fourth step and before the fifth step described below. The second impurity is introduced into the second semiconductor layer 5E by, for example, ion implantation. The second impurity may be contained in the semiconductor layer 22. In one example, the second semiconductor layer 5E containing the second impurity may be formed in the second step. By providing the cover film 31, the surface of the first semiconductor layer 3 and the like are less likely to be damaged when the second impurity is introduced into the second semiconductor layer 5E.

[0055] Next, as shown in FIG. 10, an insulating layer 6 is formed on the first semiconductor layer 3 and the insulator 4G (step 5), and then a gate 7 is formed on the insulating layer 6 (step 6). In step 5, first, the cover film 31 is removed. For example, the cover film 31 is removed by wet etching or the like. Then, the insulating layer 6 is formed on the exposed first semiconductor layer 3, the insulator 4G, the insulating layer 4F, and the second semiconductor layer 5E. Next, in step 6, first, a conductive layer is formed on the insulating layer 6. In one example, a polysilicon layer is formed as the conductive layer. Next, a mask (not shown) is formed on the conductive layer, and then the conductive layer is selectively etched using the mask. This forms the gate 7.

[0056] 11, impurities E2 and E3 (first impurities) having the first conductivity type are introduced into the first semiconductor layer 3 (seventh step). In the seventh step, a mask (not shown) is first formed to selectively expose the insulating layer 6. In one example, a portion of the insulating layer 6 that overlaps the impurity region 41 but does not overlap the gate 7, and a portion that overlaps the impurity region 42 but does not overlap at least one of the insulating layer 4F, the second semiconductor layer 5E, the insulator 4G, and the gate 7 are exposed through the mask. Subsequently, impurities E2 and E3 are introduced into the above-mentioned portions using the mask. The impurity E2 is introduced into the impurity region 41, and the impurity E3 is introduced into the impurity region 42.

[0057] Next, as shown in FIG. 12 , the first semiconductor layer 3 and the second semiconductor layer 5E are heat-treated to form a source region 11 having the first conductivity type and surrounded by the body region 12, a drain region 13 having the first conductivity type and located on the opposite side of the source region 11 across the recess 3a, and a first resurf region 14 having the first conductivity type and located at least directly below the recess 3a in the first semiconductor layer 3 (step 8). In step 8, for example, the substrate 2 is placed in a chamber of a heating device, and the first semiconductor layer 3 and the second semiconductor layer 5E are heat-treated. In one example, rapid thermal annealing (RTA) is performed for several tens of minutes to several hours. This diffuses the impurities E1 to E3 into the first semiconductor layer 3. Specifically, the first resurf region 14E is formed by diffusing the impurity E1 contained in the second semiconductor layer 5E into the first semiconductor layer 3. At this time, the impurity E1 passes through the insulating layer 4F and diffuses into the first semiconductor layer 3, thereby forming the first resurf region 14E. Similarly, the impurities E2 and E3 contained in the first semiconductor layer 3 are diffused to form the source region 11 and the drain region 13, respectively. The source region 11 is formed in a part of the impurity region 41, and the drain region 13 is formed in a part of the impurity region 42, thereby forming the body region 12 and the second resurf region 15.

[0058] Subsequently, an interlayer insulating film, wiring, vias, etc. (not shown) are formed on the first semiconductor layer 3, the insulating layer 6, the gate 7, etc. Through the above steps, a semiconductor device including an LDMOS according to the fifth modification is manufactured.

[0059] The LDMOS included in the semiconductor device according to the above embodiment and the first to fourth modifications can be manufactured by a method similar to the method for manufacturing the semiconductor device according to the fifth modification described above.

[0060] The manufacturing method of the semiconductor device 100 including the LDMOS 102 according to the embodiment differs from the manufacturing method of the semiconductor device according to the fifth modification in the second step. FIG. 13 is a schematic cross-sectional view illustrating a portion of the manufacturing method of the semiconductor device according to the embodiment. As shown in FIG. 13, in the embodiment, after the first step, a semiconductor layer 22A is formed in contact with the bottom surface of the recess 3a. That is, the embodiment differs from the fifth modification in that the insulating layer 21 (see FIG. 5) is not formed. Also, in the embodiment, the semiconductor layer 22A is selectively etched so as to cover only the bottom surface of the recess 3a. This forms a second semiconductor layer 5 in contact with the bottom surface of the recess 3a. Subsequently, steps similar to the third to eighth steps of the fifth modification are performed to manufacture the semiconductor device 100 including the LDMOS 102 according to the embodiment.

[0061] The method for manufacturing a semiconductor device including an LDMOS according to the first modification differs from the method for manufacturing a semiconductor device according to the fifth modification in the second step. In the first modification, similar to the above embodiment, after the first step, a semiconductor layer 22A is formed directly above the recess 3a (see FIG. 13). Subsequently, in the first modification, the semiconductor layer 22A is selectively etched to cover the entire recess 3a. This forms a second semiconductor layer 5A that contacts the entire surface of the recess 3a. Subsequently, steps similar to the third to eighth steps of the fifth modification are performed to manufacture the semiconductor device including an LDMOS according to the first modification.

[0062] FIG. 14 is a schematic cross-sectional view illustrating a portion of the method for manufacturing a semiconductor device according to the second modification. The method for manufacturing a semiconductor device including an LDMOS according to the second modification differs from the method for manufacturing a semiconductor device according to the fifth modification in the second step. In the second modification, similar to the embodiment, after the first step, a semiconductor layer 22A is formed directly above the recess 3a (see FIG. 13). In the second modification, the semiconductor layer 22A is selectively etched so as to cover a portion of the bottom surface of the recess 3a. As a result, as shown in FIG. 14, a second semiconductor layer 5B is formed that is spaced apart from the side surfaces 3a1 and 3a2 of the recess 3a. Subsequently, steps similar to the third to eighth steps of the fifth modification are performed to manufacture a semiconductor device including an LDMOS according to the second modification.

[0063] 15 and 16 are schematic cross-sectional views illustrating a portion of a method for manufacturing a semiconductor device according to the third modification. The method for manufacturing a semiconductor device including an LDMOS according to the third modification differs from the method for manufacturing a semiconductor device according to the fifth modification in the second step. In the third modification, as shown in FIG. 15, after the first step, a second insulator 4D is formed in the recess 3a. For example, an insulating layer 21 (see FIG. 6) is formed as in the second step, and then the insulating layer 21 is selectively etched. This leaves portions of the insulating layer 21 covering the side surfaces 3a1 and 3a2 of the recess 3a, forming the second insulator 4D including the first insulating portion 4D1 and the second insulating portion 4D2. Next, as shown in FIG. 16, a semiconductor layer 22B is formed. Next, the semiconductor layer 22B is selectively etched to form a second semiconductor layer 5C (see FIG. 4D) located in the recess 3a. Next, steps similar to the third to eighth steps of the fifth modification are performed to manufacture a semiconductor device including an LDMOS according to the third modification.

[0064] FIG. 17 is a schematic cross-sectional view illustrating a portion of the method for manufacturing a semiconductor device according to the fourth modification. The method for manufacturing a semiconductor device including an LDMOS according to the fourth modification differs from the method for manufacturing a semiconductor device according to the fifth modification in the second step. In the fourth modification, as shown in FIG. 17, after the first step, an insulating layer 4F and a second semiconductor layer 5D (see FIG. 4E) are formed. In the fourth modification, the second semiconductor layer 5D is formed by changing the etching conditions for the semiconductor layer 22 compared to the fifth modification. Subsequently, a step similar to the third step of the fifth modification is performed, thereby integrating the insulating layer 4F with the insulator deposited in the recess 3a. This forms an insulator 4E (see FIG. 4E). Subsequently, steps similar to the fourth to eighth steps of the fifth modification are performed to manufacture a semiconductor device including an LDMOS according to the fourth modification.

[0065] Although the embodiments and modifications of the present disclosure have been described above, the present disclosure can also be embodied in other forms.

[0066] In the above embodiment and each of the above modifications, in addition to the first resurf region, a second resurf region surrounding the first resurf region is formed in the first semiconductor layer, but this is not limiting. For example, the second resurf region does not have to be formed in the first semiconductor layer.

[0067] In the above embodiments and modifications, the semiconductor device can be applied to a power module used in an inverter circuit that drives an electric motor used as a power source for, for example, automobiles (including electric vehicles), trains, industrial robots, air conditioners, air compressors, fans, vacuum cleaners, dryers, refrigerators, etc. The semiconductor device can also be applied to a power module used in an inverter circuit for a solar cell, a wind power generator, or other power generation device. Alternatively, the semiconductor device can be applied to a circuit module that constitutes an analog control power supply, a digital control power supply, a gate driver, etc.

[0068] The above describes in detail embodiments and variations relating to one aspect of the present disclosure, but these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be interpreted as being limited to these specific examples, and the scope of the present disclosure is limited only by the appended claims.

[0069] Below, examples of features extracted from the description of this specification and the drawings are shown.

[0070] [A1] a first semiconductor layer overlying the substrate and having a first conductivity type; an insulator located in a recess provided in the first semiconductor layer; a second semiconductor layer located at least directly below the insulator in the recess and having the first conductivity type; an insulating layer located on the first semiconductor layer and on the insulator; a gate located on the insulating layer; Equipped with the first semiconductor layer includes a first contact region and a second contact region having the first conductivity type, a first impurity region located around the first contact region and having the second conductivity type, and a second impurity region in contact with a bottom surface of the second semiconductor layer and having the first conductivity type; the diffusion coefficient of the impurity in the second semiconductor layer is higher than the diffusion coefficient of the impurity in the first semiconductor layer; Semiconductor device.

[0071] [A2] The semiconductor device according to [A1], wherein the second semiconductor layer has a first portion located directly below the insulator and a second portion located between the insulator and the first impurity region.

[0072] [A3] The semiconductor device described in [A2], wherein the second impurity region has a first impurity portion located directly below the first portion, and a second impurity portion located between the first contact region and the second portion.

[0073] [A4] The semiconductor device according to any one of [A1] to [A3], wherein the second semiconductor layer and the second contact region are in contact with each other.

[0074] [A5] The semiconductor device according to any one of [A1] to [A4], further comprising a second insulator located between the second semiconductor layer and a side surface of the depression.

[0075] [A6] The semiconductor device according to [A1], wherein the second semiconductor layer is covered with the insulator.

[0076] [A7] the first semiconductor layer further includes a third impurity region located around the second impurity region and having the first conductivity type; The semiconductor device according to any one of [A1] to [A6], wherein the second impurity region has a higher impurity concentration than the third impurity region.

[0077] [A8] a first semiconductor layer overlying the substrate and having a first conductivity type; an insulating layer located on a surface of a recess provided in the first semiconductor layer; a second semiconductor layer located in the recess and on the insulating layer, both of which have the first conductivity type; an insulator located within the recess and on the second semiconductor layer; a second insulating layer located on the first semiconductor layer and the insulator; a gate located on the second insulating layer; Equipped with the first semiconductor layer includes a first contact region and a second contact region having the first conductivity type, a first impurity region located around the first contact region, and a second impurity region in contact with at least a bottom surface of the insulating layer and having the first conductivity type; the diffusion coefficient of the impurity in the second semiconductor layer is higher than the diffusion coefficient of the impurity in the first semiconductor layer; Semiconductor device.

[0078] [A9] The semiconductor device according to [A8], wherein the second semiconductor layer has a first portion located directly below the insulator and a second portion located between the insulator and the first impurity region.

[0079] [A10] The semiconductor device described in [A9], wherein the second impurity region has a first impurity portion located directly below the first portion, and a second impurity portion located between the first contact region and the second portion.

[0080] [A11] the first semiconductor layer further includes a third impurity region located around the second impurity region and having the first conductivity type; The semiconductor device according to any one of [A8] to [A10], wherein the second impurity region has a higher impurity concentration than the third impurity region.

[0081] [A12] a first step of forming a recess in a first semiconductor layer located on a substrate and having a first conductivity type; a second step of forming a second semiconductor layer in the recess; a third step of forming an insulator in the recess and covering at least a portion of the second semiconductor layer; a fourth step of forming a first impurity region having a second conductivity type different from the first conductivity type in the first semiconductor layer; a fifth step of forming an insulating layer on the first semiconductor layer and the insulator; a sixth step of forming a gate on the insulating layer; a seventh step of introducing a first impurity having the first conductivity type into the first semiconductor layer; an eighth step of forming, in the first semiconductor layer, a first contact region having the first conductivity type and surrounded by the first impurity region, a second contact region having the first conductivity type and located on the opposite side of the first contact region across the recess, and a second impurity region having the first conductivity type and located at least directly below the recess by heat treating the first semiconductor layer and the second semiconductor layer; Equipped with In the eighth step, the second impurity region is formed by diffusing a second impurity that is contained in the second semiconductor layer and has a first conductivity type; the diffusion coefficient of the impurity in the second semiconductor layer is higher than the diffusion coefficient of the impurity in the first semiconductor layer; A method for manufacturing a semiconductor device.

[0082] [A13] The method for manufacturing a semiconductor device according to [A12], wherein in the second step, the second semiconductor layer containing a second impurity having the first conductivity type is formed.

[0083] [A14] The method for manufacturing a semiconductor device according to [A12], further comprising the step of introducing a second impurity into the second semiconductor layer after the fourth step and before the fifth step.

[0084] [A15] The method for manufacturing a semiconductor device according to any one of [A12] to [A14], wherein in the second step, a second insulating layer is formed to cover the surface of the recess, and then a second semiconductor layer is formed on the second insulating layer.

[0085] [A16] The method further includes a step of forming a third impurity region having the first conductivity type in the first semiconductor layer immediately before or immediately after the fourth step, The method for manufacturing a semiconductor device according to any one of [A12] to [A15], wherein in the eighth step, the second impurity region is formed to be surrounded by the third impurity region.

[0086] [A17] The method for manufacturing a semiconductor device according to any one of [A12] to [A16], wherein in the second step, the second semiconductor layer is formed so as to be in contact with at least a bottom surface of the depression. [Explanation of symbols]

[0087] 2...Substrate 3...First semiconductor layer 3a...depression 3a1,3a2…side 4, 4A to 4E, 4G...Insulator 4a...First insulating part 4b...Second insulating part 4D1...First insulating part 4D2...Second insulating part 4E1...insulating layer 4E2...insulating part 4F: Insulation layer (second insulation layer) 5, 5A~5E...Second semiconductor layer 5a…Bottom surface 5b...side 6...Insulating layer 7...Gate 10...Device area 11...Source region (first contact region) 12...body region (first impurity region) 13...Drain region (second contact region) 13a…Bottom surface 14,14A~14E...First RESURF region (second impurity region) 14a...First impurity portion 14b...Second impurity portion 15...Second RESURF region (third impurity region) 21...insulating layer 22, 22A, 22B...Semiconductor layers 41...Impurity region 42…Impurity region 100...Semiconductor device 102...LDMOS E1...Impurity (second impurity) E2...Impurity (first impurity) E3...impurities

Claims

1. a first semiconductor layer overlying the substrate and having a first conductivity type; an insulator located in a recess provided in the first semiconductor layer; a second semiconductor layer located at least directly below the insulator in the recess and having the first conductivity type; an insulating layer located on the first semiconductor layer and on the insulator; a gate located on the insulating layer; Equipped with the first semiconductor layer includes a first contact region and a second contact region having the first conductivity type, a first impurity region located around the first contact region and having the second conductivity type, and a second impurity region in contact with a bottom surface of the second semiconductor layer and having the first conductivity type; a diffusion coefficient of the impurity in the second semiconductor layer is higher than a diffusion coefficient of the impurity in the first semiconductor layer; Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein said second semiconductor layer has a first portion located directly below said insulator and a second portion located between said insulator and said first impurity region.

3. 3. The semiconductor device according to claim 2, wherein the second impurity region has a first impurity portion located directly below the first portion, and a second impurity portion located between the first contact region and the second portion.

4. 4. The semiconductor device according to claim 1, wherein the second semiconductor layer and the second contact region are in contact with each other.

5. 4. The semiconductor device according to claim 1, further comprising a second insulator located between said second semiconductor layer and a side surface of said recess.

6. The semiconductor device according to claim 1 , wherein the second semiconductor layer is covered with the insulator.

7. the first semiconductor layer further includes a third impurity region located around the second impurity region and having the first conductivity type; 7. The semiconductor device according to claim 1, wherein the second impurity region has a higher impurity concentration than the third impurity region.

8. a first semiconductor layer overlying the substrate and having a first conductivity type; an insulating layer located on a surface of a recess provided in the first semiconductor layer; a second semiconductor layer located within the recess and on the insulating layer, the second semiconductor layer having the first conductivity type; an insulator located within the recess and on the second semiconductor layer; a second insulating layer located on the first semiconductor layer and the insulator; a gate located on the second insulating layer; Equipped with the first semiconductor layer includes a first contact region and a second contact region having the first conductivity type, a first impurity region located around the first contact region, and a second impurity region in contact with at least a bottom surface of the insulating layer and having the first conductivity type; a diffusion coefficient of the impurity in the second semiconductor layer is higher than a diffusion coefficient of the impurity in the first semiconductor layer; Semiconductor device.

9. 9. The semiconductor device according to claim 8, wherein the second semiconductor layer has a first portion located directly below the insulator and a second portion located between the insulator and the first impurity region.

10. 10. The semiconductor device according to claim 9, wherein the second impurity region has a first impurity portion located directly below the first portion, and a second impurity portion located between the first contact region and the second portion.

11. the first semiconductor layer further includes a third impurity region located around the second impurity region and having the first conductivity type; 11. The semiconductor device according to claim 8, wherein the second impurity region has a higher impurity concentration than the third impurity region.

12. a first step of forming a recess in a first semiconductor layer overlying a substrate and having a first conductivity type; a second step of forming a second semiconductor layer in the recess; a third step of forming an insulator in the recess and covering at least a portion of the second semiconductor layer; a fourth step of forming a first impurity region having a second conductivity type different from the first conductivity type in the first semiconductor layer; a fifth step of forming an insulating layer on the first semiconductor layer and the insulator; a sixth step of forming a gate on the insulating layer; a seventh step of introducing a first impurity having the first conductivity type into the first semiconductor layer; an eighth step of heat-treating the first semiconductor layer and the second semiconductor layer to form, in the first semiconductor layer, a first contact region having the first conductivity type and surrounded by the first impurity region, a second contact region having the first conductivity type and located on the opposite side of the first contact region across the recess, and a second impurity region having the first conductivity type and located at least directly below the recess; Equipped with In the eighth step, the second impurity region is formed by diffusing a second impurity that is contained in the second semiconductor layer and has a first conductivity type; a diffusion coefficient of the impurity in the second semiconductor layer is higher than a diffusion coefficient of the impurity in the first semiconductor layer; A method for manufacturing a semiconductor device.

13. The method for manufacturing a semiconductor device according to claim 12 , wherein the second step forms the second semiconductor layer containing the second impurity.

14. 13. The method for manufacturing a semiconductor device according to claim 12, further comprising the step of doping said second semiconductor layer with a second impurity after said fourth step and before said fifth step.

15. 15. The method for manufacturing a semiconductor device according to claim 12, wherein in the second step, a second insulating layer is formed to cover the surface of the recess, and then a second semiconductor layer is formed on the second insulating layer.

16. The method further includes a step of forming a third impurity region having the first conductivity type in the first semiconductor layer immediately before or immediately after the fourth step, 15. The method for manufacturing a semiconductor device according to claim 12, wherein in said eighth step, said second impurity region is formed so as to be surrounded by said third impurity region.

17. 15. The method for manufacturing a semiconductor device according to claim 12, wherein in the second step, the second semiconductor layer is formed so as to be in contact with at least a bottom surface of the recess.

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