Power supply device and radio wave emission device

Abstract

To prevent an excessive rush current without increasing the size of a power supply for a load which performs pulse operation.SOLUTION: A power supply device according to an embodiment includes a capacitor, a time constant circuit that adjusts a charging / discharging current of the capacitor, a power switch that selectively supplies a charging current from a main power supply to the capacitor, an output switch that intermittently connects an output terminal of the capacitor and a load in response to a pulse signal and outputs a pulse voltage to the load, a comparison circuit that compares a terminal voltage of the capacitor with a reference voltage after the start of supply of the charging current from the main power supply by the power switch, and a control circuit that determines whether or not the voltage difference exceeds a threshold value, interrupts supply of the pulse voltage to the load in a period in which the voltage difference exceeds the threshold value, and controls the output switch so as to detect completion of charging of the capacitor and supply the pulse voltage to the load in a period in which it is determined that the voltage difference does not exceed the threshold value.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present embodiment relates to a power supply device and a radio wave emitting device. [Background technology]

[0002] Conventional pulse radar devices are equipped with a capacitor in the output stage of the power supply so that current can flow instantaneously to a load (transmission signal amplifier) ​​in response to the transmission of a pulse signal, and during operation, they wait until the capacitor is charged after the power supply is turned on before transmitting a pulse signal (see Patent Document 1).In addition, because power supply devices have a limit to the amount of current they can supply, they are equipped with a current-limiting resistor to prevent inrush current (see Patent Document 2).

[0003] However, in conventional power supply devices that supply power to loads that perform high-output pulse operations, such as radio wave emission devices such as the pulse radar device, the main power supply (the primary power source) must be able to supply a large amount of current to handle the inrush current, which forces the main power supply to be large. To solve this problem, it is necessary to limit the charge current by providing a current-limiting resistor in the charge path from the main power supply, but this takes time for the capacitor to accumulate charge. If a pulse signal is transmitted before the capacitor has accumulated enough charge, the transmitted waveform will be distorted and sufficient output will not be obtained. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4444057 [Patent Document 2] Japanese Patent Application Laid-Open No. 2005-198357 [Patent Document 3] Japanese Patent Application Publication No. 10-197620 [Patent Document 4] Japanese Patent Application Laid-Open No. 2006-287718 [Patent Document 5] Japanese Patent Application Laid-Open No. 2015-213405 Summary of the Invention [Problem to be solved by the invention]

[0005] As described above, conventional power supply devices that supply power to loads that perform high-output pulse operations, such as radio wave emission devices such as pulse radar, have had problems such as an increase in the size of the power supply due to measures to deal with inrush current, an increase in the time it takes for charge to be stored in the capacitor due to current limiting, and distortion of the transmitted waveform when a pulse signal is transmitted when the capacitor is not charged.

[0006] The object of this embodiment is to provide a power supply device that can prevent excessive inrush current without increasing the size of the power supply for a load that performs high-output pulse operation, can shorten the charge storage time by limiting the current in the capacitor, and can reliably stop the power supply to the load when the charge is insufficient, and a radio wave emission device that uses this power supply device. [Means for solving the problem]

[0007] In order to solve the above problems, a power supply device according to an embodiment includes a capacitor, a time constant circuit that adjusts the charge / discharge current of the capacitor, a power switch that selectively supplies a charging current from a main power supply to the capacitor, an output switch that connects and disconnects the output terminal of the capacitor and a load in response to a pulse signal to output a pulse voltage to the load, a comparison circuit that compares the terminal voltage of the capacitor with a reference voltage after the power switch starts supplying charging current from the main power supply and outputs the voltage difference between the terminal voltage and the reference voltage, and a control circuit that determines whether the voltage difference exceeds a threshold value and controls the output switch so that the supply of pulse voltage to the load is cut off during a period when it is determined that the voltage difference exceeds the threshold value, and the supply of pulse voltage to the load is continued during a period when it is determined that the voltage difference does not exceed the threshold value. This prevents excessive inrush current for a load that operates in a pulsed manner without increasing the size of the power supply, shortens the charge storage time by limiting the current in the capacitor, and stops the power supply to the load when there is insufficient charge, thereby achieving stable operation of a pulse signal processing device that uses this power supply device. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing a first configuration of a pulse radar device to which a power supply device according to an embodiment is applied. [Figure 2] FIG. 2 is a circuit diagram showing the configuration of the power supply device according to the embodiment shown in FIG. [Figure 3] FIG. 3 is a waveform diagram showing output waveforms (calculated results) of voltages or currents at main points in the power supply device shown in FIG. [Figure 4] FIG. 4 is a circuit diagram showing the configuration of a first modification of the power supply device according to the embodiment. [Figure 5] FIG. 5 is a waveform diagram showing output waveforms (calculated results) of voltages or currents at key points in the power supply device shown in FIG. 2 when the pulse period is short. [Figure 6]FIG. 6 is a waveform diagram showing output waveforms (calculation results) of voltages or currents at key points in the power supply device of Modification 1 shown in FIG. 4 when the pulse period is short. [Figure 7] FIG. 7 is a circuit diagram showing the configuration of the power supply device according to the second modification of the embodiment. [Figure 8] FIG. 8 is a waveform diagram showing output waveforms (calculation results) of voltages or currents at key points in the power supply device of Modification 2 shown in FIG. 7 when the pulse period is short. [Figure 9] FIG. 9 is a circuit diagram showing the configuration of a third modification of the power supply device according to the embodiment. [Figure 10] FIG. 10 is a block diagram showing a second configuration of a pulse radar device to which the power supply device according to the embodiment is applied, as a fourth modification. [Figure 11] FIG. 11 is a block diagram showing a third configuration of a pulse radar device to which the power supply device according to the embodiment is applied, as a fifth modification. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings.

[0010] FIG. 1 is a block diagram showing a first configuration of a transmission system, a reception system, and a power supply system of a pulse radar device to which a power supply device according to an embodiment is applied.

[0011] In Figure 1, in the transmission system, a transmission signal for pulse compression (e.g., a chirp signal) is generated by transmission signal generator 11, converted into an analog signal by D / A converter 12, mixed with a local signal generated by local signal generator 14 by frequency converter 13 to convert into a radio frequency transmission signal, power amplified by transmission signal amplifier 15, and sent via circulator 16 to antenna 17, where it is transmitted into space.

[0012] In the receiving system, the reflected wave of the transmitted signal is received by antenna 17, and the received signal is sent via circulator 16 to received signal amplifier 18 where it is amplified with low noise. It is then mixed with the local signal generated by local signal generator 14 in frequency converter 19 and converted to a baseband signal, which is then converted to a digital signal in A / D converter 20, pulse compressed in pulse compressor 21, converted to a frequency domain signal in discrete Fourier transform processor 22, and finally a target detection processor 23 generates and outputs a target signal indicating the direction and distance of the target.

[0013] In the power supply system, a pulse signal of a predetermined period generated by a pulse signal generator 24 is sent to a power supply device 25, which generates a pulse voltage corresponding to the pulse signal and sends it as a power supply output to a transmission signal amplifier 15. Furthermore, when the power supply device 25 detects that the charging of the output capacitor is complete, it sends a charge completion signal to the transmission signal generator 11 and the pulse compression processor 21, causing them to start their respective operations.

[0014] Fig. 2 is a circuit diagram showing the configuration of power supply device 25 shown in Fig. 1. In Fig. 2, when current from main power supply 2512 is turned on by power switch (SW0) 2513, capacitor 2511 is charged with electric charge due to the characteristics of a time constant circuit formed by inductor 2514 and power supply limiting resistor 2515, which suppresses inrush current. When capacitor 2511 is sufficiently charged with electric charge, AND gate circuit 2516 is opened by a charge completion signal described below, output switch (SW1) 2518 is turned on and off by a pulse waveform signal supplied to terminal T1, and cutoff switch (SW2) 2519 is turned on and off by an inverted signal of the pulse signal by inverter 2517, whereby a pulse voltage is supplied as power from terminal T2 to load (transmission signal amplifier) ​​15 via a time constant circuit formed by inductor 2520.

[0015] Meanwhile, the terminal voltage of the capacitor 2511 is compared by a first comparator 2522 with a first reference voltage Vref1 from a first reference power supply 2521. The first comparator 2522 outputs a first voltage difference between the capacitor terminal voltage and the first reference voltage Vref1 to a first binarized inverter 2523. The first binarized inverter 2523 determines whether the first voltage difference exceeds a first threshold (charge completion value), and when the first voltage difference becomes equal to or less than the first threshold, outputs a charge completion signal from terminal T3 to the outside and also to an AND gate circuit 2516. Specifically, the output switch (SW1) 2518 and the cutoff switch (SW2) 2519 are controlled to be turned on and off via an AND gate circuit 2516 and an inverter 2517 so that the supply of the pulse voltage to the load 15 is cut off during the period in which it is determined that the first voltage difference exceeds the first threshold, and the completion of charging of the capacitor 2511 is detected and the pulse voltage is supplied to the load 15 during the period in which it is determined that the first voltage difference is equal to or less than the first threshold. In addition, a charge completion signal is output from a terminal T3 to the transmission signal generator 11 and the pulse compression processor 21, making it possible to perform transmission after the charge has accumulated in the capacitor 2511.

[0016] Here, a Schmitt trigger circuit is used for the first binarized inverter 2523. When a pulse voltage is supplied to the load 15, the charge stored in the capacitor 2511 is finite, so the terminal voltage of the capacitor 2511 gradually decreases, resulting in a significant decrease in the pulse voltage. If only a normal comparator 2522 were used at that time, the first voltage difference between the terminal voltage and the first reference voltage Vref1 would quickly increase and exceed the first threshold even after charging was complete, stopping the supply of the pulse voltage to the load 15. For this reason, a Schmitt trigger circuit with hysteresis for the first voltage difference is provided. When the first voltage difference falls below the first threshold, a charge completion signal is used to control the switch to maintain the supply of the pulse voltage to the load 15 until the first voltage difference exceeds a second threshold higher than the first threshold, thereby stably continuing the supply of the pulse voltage. The hysteresis characteristic may be realized by a method other than a Schmitt trigger circuit, such as an FPGA (Field Programmable Gate Array).

[0017] Figure 3 is a waveform diagram showing the signal waveforms of each part of the power supply device 25 shown in Figure 2, where (a) is the pulse signal supplied to terminal T1, (b) the dotted line is the capacitor terminal voltage, the solid line is the pulse voltage supplied from terminal T2 to load 15, (c) the charge current supplied from the main power supply 2512, (d) the first voltage difference output from the first comparator 2521, and (e) the charge completion signal output from the first binary inverter 2523.

[0018] 3, while the first voltage difference between the terminal voltage of capacitor 2511 and first reference voltage Vref1 exceeds the first threshold, the charge completion signal is at the off level, and the pulse voltage to load 15 is cut off. When the first voltage difference between the terminal voltage of capacitor 2511 and first reference voltage Vref1 becomes equal to or less than the first threshold, the charge completion signal becomes at the on level, and the pulse voltage begins to be supplied to load 15.

[0019] Therefore, the power supply device according to the above embodiment keeps the output of the pulse-operated load 15 cut off until the charging of the capacitor 2511 is completed, thereby making it possible to stop the supply of power to the load 15 when the charge is insufficient.

[0020] (Variation 1) In power supply device 25 according to the above embodiment, when the supply of pulse voltage is started when the period of the pulse signal is short, the charging of capacitor 2511 between pulses cannot keep up, causing a phenomenon in which the terminal voltage of capacitor 2511 drops and the voltage to load 15 drops. A first modified example of a configuration that addresses this phenomenon will be described with reference to FIGS.

[0021] Figure 4 is a block diagram showing the configuration of power supply device 25 according to Modification 1. In Figure 4, the same parts as in Figure 2 are designated by the same reference numerals, and duplicated explanations will be omitted here. Figure 4 differs from Figure 2 in that a first resistor 2524, which has a smaller resistance value than current limiting resistor 2515, is selectively connected in parallel to current limiting resistor 2515 by a first on / off switch 2525.

[0022] In the power supply device 25 of this first modification, as shown in FIG. 4, during the period in which it is determined that the first voltage difference between the terminal voltage of the capacitor 2511 and the first reference voltage Vref1 exceeds the first threshold, that is, when the charge completion signal is at the off level, the first on-off switch (SW3) 2525 disconnects the first resistor 2524 from the current limiting resistor 2515, and the charge current is limited only by the current limiting resistor 2515, and during the period in which it is determined that the first threshold is not exceeded, that is, when the charge completion signal is at the on level, the first on-off switch (SW3) 2525 connects the first resistor 2524 in parallel to the current limiting resistor 2515, thereby relaxing the limitation on the charge current.

[0023] Figure 5 is a waveform diagram showing the signal waveforms of each part when the period of the pulse signal is short in the power supply device 25 of the first embodiment shown in Figure 2, and Figure 6 is a waveform diagram showing the signal waveforms of each part when the period of the pulse signal is short in the power supply device 25 of variant example 1 shown in Figure 4, in which (a) shows the pulse signal supplied to terminal T1, (b) the dotted line shows the capacitor terminal voltage, the solid line shows the pulse voltage supplied from terminal T2 to the load 15, (c) shows the charge current supplied from the main power supply 2512, (d) shows the first voltage difference output from the first comparator 2521, and (e) shows the charge completion signal output from the first binary inverter 2523.

[0024] In the configuration shown in FIG. 2, if the pulse period is short, charging does not occur in time after the pulse voltage is output, resulting in a drop in the pulse voltage output to load 15, as shown in FIG. 5. However, in the configuration of the present modification 1, as shown in FIG. 6, after the pulse voltage is output, first resistor 2524 is connected in parallel to current-limiting resistor 2515, easing the current limitation, thereby increasing the charge current and speeding up the charging of capacitor 2511. As a result, even if the pulse period is shortened, the charging completion state continues after the pulse voltage is output, and the pulse voltage supplied to load 15 can be stably maintained. Furthermore, because the current limitation of current-limiting resistor 2515 is mitigated after the pulse voltage is supplied, the charge storage time due to the current limitation of capacitor 2511 can be shortened, while preventing excessive inrush current without increasing the power supply size of main power supply 2512.

[0025] (Variation 2) A second modification of the power supply device 25 according to the first modification, which is provided with a configuration for further shortening the time required for charging to be completed, will be described with reference to FIGS.

[0026] FIG. 7 is a block diagram showing the configuration of a power supply device 25 according to Modification 2. In FIG. 7, the same components as those in FIG. 4 are designated by the same reference numerals, and redundant description will be omitted here. FIG. 7 differs from FIG. 4 in that, in addition to a first resistor 2524 and a first on-off switch (SW3) 2525 connected in parallel to a current-limiting resistor 2515, a second resistor 2529 having a smaller resistance value than the current-limiting resistor 2515 is selectively connected in parallel to the current-limiting resistor 2515 by a second on-off switch (SW4) 2530, and in addition to a first reference power supply 2521, a first comparator 2522, and a first binarization inverter 2523, a second reference power supply 2526, a second comparator 2527, and a second binarization inverter 2528 are provided. The second reference power supply 2526 generates a second reference voltage Vref2 that is lower than the first reference voltage Vref1. If the resistance value of the current limiting resistor 2515 is R0, the resistance value of the first resistor 2524 is R1, and the resistance value of the second resistor 2529 is R2, then the relationship is R0≧R2>R1.

[0027] In the above configuration, the second comparator 2527 compares the terminal voltage of the capacitor 2511 with the second reference voltage Vref2 of the second reference power supply 2526 to calculate a second voltage difference. After the charging current is supplied, the second binarization inverter 2528 keeps the on-off switch (SW4) 2530 in an off state until the second voltage difference reaches a second threshold. When the second voltage difference reaches or exceeds the second threshold, the second binarization inverter 2528 turns on the on-off switch (SW4) 2530, connecting a resistor 2529 in parallel with the current-limiting resistor 2515 to relax the current limit. This increases the charging current and shortens the charging time. Thereafter, when the first voltage difference obtained by the first comparator 2522 exceeds the first threshold, the first on-off switch (SW3) 2525 is turned on, connecting a first resistor 2524 in parallel with the current-limiting resistor 2515 to further relax the current limit.

[0028] Figure 8 is a waveform diagram showing the signal waveforms of each part in the power supply device 25 relating to variant example 2 shown in Figure 7, where (a) is the pulse signal supplied to terminal T1, (b) the dotted line is the capacitor terminal voltage, the solid line is the pulse voltage supplied from terminal T2 to the load 15, (c) the charge current supplied from the main power supply 2512, (d) the voltage difference output from the second comparator 2527, and (e) the SW3 control signal (charge completion signal) and SW4 control signal output from the first and second binary inverters 2528.

[0029] In Modification 2, once the second voltage difference reaches the second threshold after the charging current is applied, there is a margin for current consumption in main power supply 2512. For this reason, second resistor 2529 is added to second on / off switch SW4 and connected in parallel with current limiting resistor 2515, thereby reducing the effect of current limiting resistor 2514 and increasing the charging current, allowing capacitor 2511 to be charged more quickly, making the charging time shorter than in Modification 1. Therefore, with the configuration of Modification 2, the time until the start of output of pulse voltage to load 15 can be shortened compared to Modification 1.

[0030] In the configuration of the second modification, it is also desirable to use a Schmitt trigger circuit (or FPGA or the like) in the second binarized inverter 2528 to stabilize switch control.

[0031] (Variation 3) 2, the terminal voltage of capacitor 2511 is monitored, but it is also possible to monitor the charge current to capacitor 2511. Modification 3 in this case will be described with reference to FIG.

[0032] Fig. 9 is a block diagram showing the configuration of power supply device 25 according to Modification 3. In Fig. 9, the same parts as in Fig. 2 are denoted by the same reference numerals, and duplicated explanations will be omitted here. In Fig. 9, shunt resistor 2531 is interposed in the charge current path, and the voltage difference between both ends of shunt resistor 2531 is detected by a differential amplifier made up of operational amplifier 2532 and resistors 2533 (R1), 2534 (R2), 2535 (R3), and 2536 (R4), and the shunt resistor voltage difference detected by the differential amplifier is supplied to first comparator 2522 instead of the terminal voltage of capacitor 2511.

[0033] That is, in the third modification, a shunt resistor 2531 is used to monitor the current from the main power supply 2512, and when the voltage difference due to the shunt current detected by the differential amplifier becomes equal to or less than a certain level, a high-level charge completion signal is output from the binary inverter 2523, and the output switch (SW1) 2518 and the cutoff switch (SW2) 2519 are opened and closed according to the pulse signal via the AND gate circuit 2516 and the inverter 2517, thereby supplying a pulse voltage (current) to the load 15.

[0034] In addition, the shunt resistor 2531 (R ST ) current I L and the output V0 of the differential amplifier have the following relationship: V0=(R2 / R1)×R ST ×I L According to this configuration, when the capacitor 2511 and the main power supply 2512 are physically separated, monitoring the current rather than monitoring the terminal voltage of the capacitor 2511 makes it possible to complete the monitoring near the main power supply.

[0035] It is also possible to apply the contents of the first and second modifications to the configuration for monitoring the current.

[0036] (Variation 4) Figure 10 is a block diagram showing a second configuration of a pulse radar device to which the power supply device according to the embodiment is applied, as Modification 4. Note that in Figure 10, the same parts as in Figure 1 are denoted by the same reference numerals, and duplicated statements will be omitted here.

[0037] 1, the charge completion signal output from power supply device 25 is sent directly to transmission signal generator 11 and pulse compression processor 21, but in modification 4, the charge completion signal output from power supply device 25 is sent to controller 26, which generates a transmission timing signal (TX) and a reception timing signal (RX) and sends them to transmission signal generator 11 and pulse compression processor 21. This configuration makes it possible to individually and highly accurately control the timing of pulse compression processing in the transmission system and the reception system.

[0038] (Variation 5) FIG. 11 is a block diagram showing a third configuration of a pulse radar device to which a power supply device according to an embodiment of the present invention is applied, as a fifth modification. Note that in FIG. 11, the same components as in FIG. 10 are designated by the same reference numerals, and redundant description will be omitted here. In a pulse radar device, in order to strictly manage pulse transmission, activation is controlled by inputting an interlock release signal by the user to prevent inadvertent transmission. Therefore, in the fifth modification, a charge completion signal output from power supply device 25 is input to AND gate circuit 27 together with an interlock release signal, and the output of AND gate circuit 27 is sent to controller 26 as a transmission enable / disable signal. With this configuration, even if a charge completion signal is output from power supply device 25, transmission is not enabled unless an interlock release signal is input. Transmission is enabled only when both signals are input, which contributes to improving the safety of the pulse radar device.

[0039] In the above embodiment, the power supply device applied to a pulse radar device has been described, but the power supply device can also be applied to a radio wave emitting device that processes high-output pulse signals.

[0040] Furthermore, the present invention is not limited to the above-described embodiments, and the components can be modified and embodied in practice without departing from the spirit of the invention. Furthermore, various inventions can be formed by appropriately combining multiple components disclosed in the above-described embodiments. For example, some components may be omitted from all the components shown in the embodiments. Furthermore, components from different embodiments may be appropriately combined. [Explanation of symbols]

[0041] 11...Transmitting signal generator, 12...D / A converter, 13...Frequency converter, 14...Local signal generator, 15...Transmitting signal amplifier (load), 16...Circulator, 17...Antenna, 18...Receiving signal amplifier, 19...Frequency converter, 20...A / D converter, 21...Pulse compression processor, 22...Discrete Fourier transform processor, 23...Target detection processor, 24...Pulse signal generator, 25...Power supply, 2511...Capacitor, 2516...AND gate circuit, 2517...Inverter, 25 18...output switch (SW1), 2519...shutoff switch (SW2), 2520...inductor, 2521...first reference power supply, 2522...first comparator, 2523...first binary inverter, 2524...first resistor, 2525...first on-off switch, 2526...second reference power supply, 2527...second comparator, 2528...second binary inverter, 2529...second resistor, 2530...second on-off switch (SW4), 2531...shunt resistor (R ST ), 2532...operational amplifier, 2533...resistor (R1), 2534...resistor (R2), 2535...resistor (R3), 2536...resistor (R4), 26...controller, 27...AND gate circuit.

Claims

1. A capacitor, a time constant circuit for adjusting the charge / discharge current of the capacitor; a power switch for selectively supplying charging current from a main power supply to the capacitor; an output switch that connects and disconnects the output terminal of the capacitor and a load in response to a pulse signal to output a pulse voltage to the load; a comparison circuit that compares a terminal voltage of the capacitor with a first reference voltage after the power switch starts supplying a charging current from the main power supply, and outputs a first voltage difference between the terminal voltage and the first reference voltage; a control circuit that determines whether the first voltage difference exceeds a first threshold value, and controls the output switch so as to cut off supply of a pulse voltage to the load during a period when it is determined that the first voltage difference exceeds the first threshold value, and to supply a pulse voltage to the load during a period when it is determined that the first voltage difference does not exceed the first threshold value, assuming that charging of the capacitor has been completed; A power supply device comprising:

2. The control circuit has a second threshold value greater than the first threshold value, determines whether the first voltage difference exceeds the first threshold value and the second threshold value, and has hysteresis in control of the output switch so as to cut off supply of a pulse voltage to the load during a period when it is determined that the first voltage difference exceeds the second threshold value, supply a pulse voltage to the load during a period when it is determined that the first voltage difference does not exceed the first threshold value when it is determined that the first voltage difference does not exceed the second threshold value, and continue supplying a pulse voltage to the load during a period when it is determined that the first voltage difference exceeds the first threshold value when it is determined that the first voltage difference exceeds the first threshold value until it is determined that the first voltage difference exceeds the second threshold value. The power supply device according to claim 1.

3. the time constant circuit includes a first resistor that limits the charging current from the main power supply, a second resistor having a resistance value smaller than that of the first resistor, and a first on-off switch that selectively connects the second resistor in parallel to the first resistor; The control circuit disconnects the second resistor from the first resistor by the first on-off switch during a period when it is determined that the first voltage difference exceeds the first threshold, and connects the second resistor in parallel to the first resistor by the first on-off switch during a period when it is determined that the first voltage difference does not exceed the threshold. The power supply device according to claim 1.

4. the time constant circuit includes a first resistor that limits the charging current from the main power supply, a second resistor having a resistance value smaller than that of the first resistor, a first on-off switch that selectively connects the second resistor in parallel to the first resistor, a third resistor having a resistance value equal to or smaller than that of the first resistor and larger than that of the second resistor, and a second on-off switch that selectively connects the third resistor in parallel to the first resistor, the comparison circuit further compares the terminal voltage of the capacitor with a second reference voltage lower than the first reference voltage after the power switch starts supplying a charging current from the main power supply, and outputs a second voltage difference between the terminal voltage and the second reference voltage; The control circuit keeps the second on-off switch in an off state during a period until it is determined that the second voltage difference does not exceed a third threshold, connects the third resistor in parallel to the first resistor by the second on-off switch during a period during which it is determined that the second voltage difference does not exceed the third threshold, keeps the first on-off switch in an off state during a period until it is determined that the first voltage difference does not exceed the first threshold, and further connects the second resistor in parallel to the first resistor by the first on-off switch during a period during which it is determined that the first voltage difference does not exceed the first threshold. The power supply device according to claim 1.

5. A capacitor, a time constant circuit for adjusting the charge / discharge current of the capacitor; a power switch for selectively supplying charging current from a main power supply to the capacitor; an output switch that connects and disconnects the output terminal of the capacitor and a load in response to a pulse signal to output a pulse voltage to the load; a shunt resistor provided on a path of the charging current; a comparison circuit that monitors a shunt current based on a voltage difference across the shunt resistor, compares a shunt voltage corresponding to the shunt current with a first reference voltage after the power switch starts supplying a charging current from the main power supply, and outputs a first voltage difference between the shunt voltage and the first reference voltage; a control circuit that determines whether the first voltage difference exceeds a first threshold value, and controls the output switch so as to cut off supply of a pulse voltage to the load during a period when it is determined that the first voltage difference exceeds the first threshold value, and to supply a pulse voltage to the load during a period when it is determined that the first voltage difference does not exceed the first threshold value, assuming that charging of the capacitor has been completed; A power supply device comprising:

6. The power supply device according to any one of claims 1 to 5, a pulse signal processor that generates a transmission pulse; Equipped with The power supply device outputs a charge completion signal when it detects that the capacitor is fully charged, and sends the signal to the pulse signal processor to control the timing of processing the pulse signal. Radio wave emitting device.

7. The power supply device according to any one of claims 1 to 5, a pulse signal processor that generates a transmission pulse; a controller that drives and controls the pulse signal processor; Equipped with When the power supply device detects that the capacitor has been fully charged, it outputs a charge completion signal to the controller, and the controller controls the processing timing of the pulse signal processor. Radio wave emitting device.

8. The power supply device according to any one of claims 1 to 5, a pulse signal processor for generating a transmission pulse; a controller that drives and controls the pulse signal processor in accordance with an interlock release instruction; a gate that sends an instruction to release the interlock to the controller during a period when a charge completion signal that detects completion of charging of the capacitor is being output from the power supply device; A radio wave emitting device comprising:

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