Memory system and operation thereof

Abstract

To provide a memory system and a method for compensating for shortage of a host memory.SOLUTION: The memory system 102 includes a memory device and a memory controller. The memory device comprises a first memory cell and a second memory cell. The memory controller is coupled to the host and the memory device, and writes first data to the first memory cells and / or second data to the second memory cells. The first data comprises user data and the second data comprises swap data from the host memory.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to memory systems and their operation. [Background technology]

[0002] Although the demand for storage capacity of host memory, e.g., DRAM, is increasing, the cost of host memory is still high. Using external memory, e.g., a part of SSD, to make up for the shortage of host memory is a viable solution. It is worth paying attention to how to design external memory to fit additional functions. Summary of the Invention [Means for solving the problem]

[0003] In one embodiment, a memory system coupled to a host memory comprises: a memory device comprising a first memory cell and a second memory cell; and a memory controller coupled to the host and the memory device and configured to write first data to a first memory cell and / or second data to a second memory cell, wherein the first data comprises user data and the second data comprises swap data from the host memory.

[0004] In some implementations, the memory controller: a cache configured to receive the first data and / or the second data; and a processor configured to, in response to a write command, write first data to a first memory cell according to a first address signal and / or write second data to a second memory cell according to a second address signal.

[0005] In some implementations, the processor: The address signal processor is further configured to convert the logical address of the first address signal and / or the second address signal into a physical address based on a logical-to-physical address mapping table.

[0006] In some implementations, the processor: further configured to count the cycle time of the second memory cell; When the cycle time is equal to or greater than the lifetime threshold, an operation to write the second data to the second memory cell is inhibited.

[0007] In some implementations, the processor is further configured to write second data to the first memory cell.

[0008] In some implementations, the memory cells of the second memory cells are single-level cells (SLC).

[0009] In some implementations, the memory cell of the first memory cell is a multi-level cell (MLC), a trinary level cell (TLC), or a quad-level cell (QLC).

[0010] In another aspect, there is provided a method for operating a memory system, the memory system being coupled to a host memory, the method comprising: receiving first data and / or second data, the first data comprising user data and the second data comprising swap data from the host memory; and writing the first data to a first memory cell of the memory device and / or the second data to a second memory cell of the memory device.

[0011] In some implementations, receiving a write command, a first address signal, and / or a second address signal; The method further includes, in response to a write command, writing first data to a first memory cell according to a first address signal and / or writing second data to a second memory cell according to a second address signal.

[0012] In some implementations, The method further includes converting the logical address of the first address signal and / or the second address signal into a physical address based on a logical-physical address mapping table.

[0013] In some implementations, further comprising counting the cycle time of the second memory cell; When the cycle time is equal to or greater than the lifetime threshold, an operation to write the second data to the second memory cell is inhibited.

[0014] In some implementations, The method further includes writing second data to the first memory cell.

[0015] In another aspect, a memory system coupled to a host memory comprises: a memory device comprising a first memory cell and a second memory cell; and a memory controller coupled to the host and the memory device and configured to read first data from the first memory cell and / or second data from the second memory cell, wherein the first data comprises user data and the second data comprises swap data from the host memory.

[0016] In some implementations, the memory controller: The memory device includes a processor configured to, in response to a read command, read first data from a first memory cell according to a first address signal and / or read second data from a second memory cell according to a second address signal.

[0017] In some implementations, the processor: The address signal processor is further configured to convert the logical address of the first address signal and / or the second address signal into a physical address based on a logical-to-physical address mapping table.

[0018] In some implementations, the processor: further configured to count the cycle time of the second memory cell; When the cycle time is equal to or greater than the lifetime threshold, an operation to read the second data from the second memory cell is inhibited.

[0019] In some implementations, the memory cells of the second memory cells are single-level cells (SLC).

[0020] In some implementations, the memory cell of the first memory cell is a multi-level cell (MLC), a trinary level cell (TLC), or a quad-level cell (QLC).

[0021] In another aspect, there is provided a method for operating a memory system, the memory system being coupled to a host memory, the method comprising: receiving a read command, a first address signal, and / or a second address signal; reading first data from a first memory cell of the memory device and / or second data from a second memory cell of the memory device, wherein the first data comprises user data and the second data comprises swap data from the host memory.

[0022] In some implementations, The method further includes converting the logical address of the first address signal and / or the second address signal into a physical address based on a logical-physical address mapping table.

[0023] The above method is further comprising counting the cycle time of the second memory cell; When the cycle time is equal to or greater than the lifetime threshold, an operation to read the second data from the second memory cell is inhibited.

[0024] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the disclosure and to enable one skilled in the art to make and use the disclosure. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a block diagram of an exemplary system having a host and a memory system in accordance with some aspects of the present disclosure. [Figure 2A] FIG. 1 is a diagram of an exemplary memory card having a memory device in accordance with some aspects of the present disclosure. [Figure 2B] FIG. 1 is a diagram of an exemplary solid-state drive (SSD) having a memory device, in accordance with some aspects of the present disclosure. [Figure 3] FIG. 1 is a schematic diagram of an exemplary memory device including peripheral circuitry in accordance with some aspects of the present disclosure. [Figure 4] FIG. 1 is a block diagram of an exemplary memory system including a memory controller and a memory device, in accordance with some aspects of the present disclosure. [Figure 5] FIG. 1 is a block diagram of an exemplary host including a host memory and a host processor, in accordance with some aspects of the present disclosure. [Figure 6] FIG. 1 is a block diagram of an exemplary memory device including a memory cell array in accordance with some aspects of the present disclosure. [Figure 7] FIG. 1 is a block diagram of an exemplary memory system including a memory controller and a memory device, in accordance with some aspects of the present disclosure. [Figure 8] 1 is a flowchart of an exemplary method for operating a memory system in accordance with some aspects of the present disclosure. [Figure 9] 1 is a flowchart of an exemplary method for operating a memory system in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0026] Aspects of the present disclosure will now be described with reference to the accompanying drawings.

[0027] While specific configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. The present disclosure can also be utilized in a variety of other applications. The functional and structural features as described in this disclosure can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, and these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0028] In general, terms may be understood, at least in part, from their usage in context. For example, as used herein, the term "one or more" may be used in a singular sense to describe any feature, structure, or characteristic, or in a plural sense to describe a combination of features, structures, or characteristics, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may also be understood to convey a singular usage or a plural usage, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but instead may allow for the presence of additional factors not necessarily explicitly recited, also depending at least in part on the context.

[0029] 1 shows a block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG. 1, system 100 can include a host 108 having a host memory 110 and a host processor 112, and a memory system 102 having one or more memory devices 104 and a memory controller 106.

[0030] The host 108 can be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 108 can be coupled to the memory controller 106 and configured to send or receive data to or from the memory device 104 through the memory controller 106. For example, the host 108 may send program data in a program operation or receive read data in a read operation. The host processor 112 can be a control unit (CU) or an arithmetic logic unit (ALU). The host memory 110 can be a memory unit including registers or cache memory. The host 108 receives and sends instructions and commands to and from the memory controller 106 of the memory system 102 and is configured to perform or carry out multiple functions and operations provided in this disclosure, as will be described below.

[0031] The memory device 104 can be any memory device disclosed in this disclosure, such as a NAND flash memory device that includes a page buffer having multiple portions, for example, four quarters. It is noted that NAND flash is merely an example of a memory device for illustrative purposes. It can include any suitable solid-state, non-volatile memory, such as NOR flash, ferroelectric RAM (FeRAM), phase-change memory (PCM), magnetoresistive random access memory (MRAM), spin-transfer-write magnetic random access memory (STT-RAM), or resistive random access memory (RRAM). In some implementations, the memory device 104 includes a three-dimensional (3D) NAND flash memory device.

[0032] The memory controller 106 may be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gate logic, discrete hardware circuits, and other suitable hardware, firmware, and / or software configured to perform various functions described in detail below.

[0033] According to some implementations, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, CompactFlash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some implementations, the memory controller 106 is designed to operate in high-duty-cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage for mobile devices such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. The memory controller 106 can be configured to control operations of the memory device 104, such as read, erase, and program operations, by providing instructions, such as read instructions, to the memory device 104. For example, memory controller 106 may be configured to provide read instructions to peripheral circuits of memory device 104 to control read operations. Memory controller 106 may also be configured to manage various functions related to data stored or to be stored in memory device 104, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, memory controller 106 is further configured to process error correcting codes (ECC) related to data read from or written to memory device 104. Any other suitable functions, such as formatting memory device 104, may also be performed by memory controller 106.

[0034] The memory controller 106 can communicate with external devices (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 may communicate with external devices through at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0035] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices that are included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and packaged into different types of end electronic products. In one example, as illustrated in FIG. 2A , the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a Memory Stick, a MultiMediaCard (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can further include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG. 1 ). In another example, as illustrated in FIG. 2B , the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 may further include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG. 1). In some implementations, the storage capacity and / or operating speed of the SSD 206 are greater than those of the memory card 202.

[0036] The memory controller 106 is configured to receive and send commands to and from the host 108 and to perform or carry out multiple functions and operations provided in this disclosure, as will be described below.

[0037] FIG. 3 shows a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some embodiments of the present disclosure. The memory device 300 may be an example of the memory device 104 in FIG. 1 . It is noted that the NAND flash disclosed herein is merely an example of a memory device for illustrative purposes. It may include any suitable solid-state, non-volatile memory, such as NOR flash, FeRAM, PCM, MRAM, STT-RAM, or RRAM. The memory device 300 may include a memory cell array 301 and peripheral circuits 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array in which the memory cells 306 are arranged in the form of an array of NAND memory strings 308, each extending vertically above a substrate (not shown). In some implementations, each NAND memory string 308 includes multiple memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog quantity, such as a voltage or charge, depending on the number of electrons captured within the region of the memory cell 306. Each memory cell 306 can be either a floating gate type memory cell including a floating gate transistor or a charge trap type memory cell including a charge trap transistor.

[0038] In some implementations, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) that can store two or more bits of data in four or more memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erased state to one of three possible programming levels by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0039] As shown in FIG. 3 , each NAND memory string 308 can include a source select gate (SSG) transistor 310 at its source end and a drain select gate (DSG) transistor 312 at its drain end. The SSG transistor 310 and the DSG transistor 312 can be configured to activate a selected NAND memory string 308 (a column of the array) during read and program operations. In some implementations, the sources of the NAND memory strings 308 in the same block 304 are coupled through the same source line (SL) 314, e.g., a common SL. In other words, all NAND memory strings 308 in the same block 304 have an array common source (ACS), according to some implementations. The drains of the DSG transistors 312 of each NAND memory string 308 are coupled to respective bit lines 316, from which data can be read or written via an output bus (not shown), according to some implementations. In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the DSG transistor 312) or a deselect voltage (e.g., 0V) to the gate of each DSG transistor 312 through one or more DSG lines 313 and / or by applying a select voltage (e.g., above the threshold voltage of the SSG transistor 310) or a deselect voltage (e.g., 0V) to the gate of each SSG transistor 310 through one or more SSG lines 315.

[0040] As shown in FIG. 3 , NAND memory strings 308 can be organized into multiple blocks 304, each of which can have a common source line 314 coupled to, for example, an ACS. In some implementations, each block 304 is the basic data unit for erase operations, i.e., all memory cells 306 in the same block 304 are erased simultaneously. To erase memory cells 306 in a selected block 304, the source lines 314 coupled to the selected block 304 as well as unselected blocks 304 in the same plane as the selected block 304 can be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20 V or greater). Memory cells 306 in adjacent NAND memory strings 308 can be coupled through word lines 318 that select which row of memory cells 306 is affected by read and program operations. In some implementations, each word line 318 is coupled to a page 320 of memory cells 306, which is the basic data unit for program and read operations. The bit size of one page 320 may relate to the number of NAND memory strings 308 coupled by word lines 318 in one block 304. Each word line 318 may include multiple control gates (gate electrodes) in each memory cell 306 in the respective page 320 and gate lines coupling the control gates. The peripheral circuitry 302 may be coupled to the memory cell array 301 through bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of the memory cell array 301 by applying and sensing voltage and / or current signals to and from each target memory cell 306 through the bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuitry 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology.

[0041] FIG. 4 illustrates a block diagram of an exemplary memory system 102 including a memory controller 106 and a memory device 104 according to some embodiments of the present disclosure. As illustrated in FIG. 4, the memory controller 106 may include a controller processor 408, such as a memory chip controller (MCC) or memory controller unit (MCU). The controller processor 408 is configured to control modules that execute commands or instructions to perform the functions disclosed in the present disclosure. The controller processor 408 may also be configured to control the operation of each peripheral circuit by generating and sending various control signals, such as a read command for a read operation. The controller processor 408 may also send clock signals with a desired frequency, period, and duty cycle to the other peripheral circuits 302 to regulate the operation of each peripheral circuit 302, for example, for synchronization. The memory controller 106 may further include a volatile controller memory 411 and a non-volatile controller memory. The volatile controller memory 411 may include registers or cache memory, allowing for faster access and processing speeds to read, write, or erase data stored therein, while not retaining stored information after power is removed. In some implementations, the volatile controller memory 411 includes dynamic random access memory (DRAM) or static random access memory (SRAM). The nonvolatile controller memory 413 can retain stored information even after power is removed. In some implementations, the nonvolatile controller memory 413 includes NAND, NOR, FeRAM, PCM, MRAM, STT-RAM, or RRAM. The memory device 104 may include a memory cell array, such as memory cell array 301 in FIG. 3. In some implementations, the nonvolatile controller memory 413 may not be provided in the memory controller 106; for example, the nonvolatile controller memory 413 may be external to but coupled to the memory controller 106.In some implementations, the controller memory (eg, 411 or 413) is configured to store an L2P address mapping table (eg, 4271, 4273) corresponding to a file (eg, 129).

[0042] FIG. 5 illustrates a block diagram of an exemplary host 108 including a host memory 110 and a host processor 112, according to some embodiments of the present disclosure. The host memory 110 can be a volatile memory such as random access memory (RAM), e.g., DRAM, SRAM, or the like. The host memory 110 can also be a non-volatile memory such as NAND, NOR, FeRAM, PCM, MRAM, STT-RAM, or RRAM. The host memory 110 includes a main RAM 502 and a ZRAM 504. In some implementations, the main RAM 502 and the ZRAM 504 can be different logical zones of the host memory 110. In other words, the memory cells of the main RAM 502 and the ZRAM 504 can be distinguished by the logical addresses of the memory cells. In some implementations, the main RAM 502 and the ZRAM 504 can be separate memories. For example, the main RAM 502 may belong to a first host memory 110, and the ZRAM 504 may belong to a second host memory 110 that is independent of the first host memory 110. The first host memory 110 and the second host memory 110 may be the same or different types of memory. In some implementations, the host processor 112 may be a control unit (CU) or an arithmetic logic unit (ALU).

[0043] In some implementations, data in the main RAM 502 can be transferred to the ZRAM 504, and the transferred data can be a software program. Furthermore, the data transfer operation can be triggered when the main RAM 502 is full or at any time depending on the host processor 112. In some implementations, the data transfer operation can be controlled by the host processor 112. In some implementations, the data transferred to the ZRAM 504 can be compressed data. The data compression operation can be performed at any time, for example, before the data is sent out from the main RAM 502, or during the transfer process (after the data is sent out from the main RAM 502 and before the data is received by the ZRAM 504), or after the data is received by the ZRAM 504. The compression operation can be controlled by the host processor 112. In some implementations, the operation process can be such that when the main RAM 502 is full, the host processor 112 controls the main RAM 502 to transfer the data in the main RAM 502 to the ZRAM 504, and the transferred data is compressed before it is received by the ZRAM 504. In some implementations, data transferred from main RAM 502 may be less frequently accessed than data remaining in main RAM 502. In this case, inactive data can be compressed, saving storage space in host memory 110. For example, in a smartphone implementation, assume that five applications are running and the programs for the five applications are stored in main RAM 502. If two of the five applications are inactive, the programs for the two inactive applications can be compressed and stored in ZRAM 504. This frees up some of the storage space in main RAM 502, allowing more programs to be stored in host memory 110 and more apps to run simultaneously. In this case, the two inactive applications are still running in the background, and when they are invoked, the programs for the two inactive applications can be expanded.

[0044] Data in the host memory 110 can also be transferred to the memory device 104, and data can be transferred from the ZRAM 504 or the main RAM 502. Furthermore, the data transfer operation can be triggered when the main RAM 502 or the ZRAM 504 is full, or at any time depending on the host processor 112. In some implementations, the data transfer operation can be controlled by the host processor 112. In some implementations, the ZRAM 504 transfers swap data to a memory system (e.g., SSD, UFS, eMMC), and the swap data can be a compressed software program. The memory system can store the swap data, and the memory system can also send the swap data back to the host memory 110 (e.g., ZRAM 504), so that the memory system can be complementary to the host memory 110. In some implementations, after the ZRAM 504 transfers the swap data to the memory system, the swap data in the ZRAM 504 can be deleted to free up storage space in the ZRAM 504. In some implementations, when storage capacity of ZRAM 504 is tight, swap data corresponding to inactive software or applications can be transferred from ZRAM 504 to the memory system, and when the inactive software or applications are invoked, the corresponding swap data can be transferred from the memory system to ZRAM 504. In this case, more software or applications can be run simultaneously.

[0045] The host processor 112 can send a command to the memory system to instruct the memory system to input or output swap data. Furthermore, the memory system can include a memory controller 106 and a memory device 104, which can be a NAND flash memory. The command and the swap data can be sent to the memory controller 106, and the memory controller 106 can write the swap data to the memory device 104 according to the command. In some implementations, the host processor 112 can also send an address signal to the memory controller, which can include a logical address, and the controller can translate the logical address into a physical address based on an L2P address mapping table. The L2P address mapping table can be stored in the DRAM, NAND flash, or host memory 110 of the memory system. The physical address refers to a memory cell in the memory device 104, so that the memory controller 106 can write the swap data to the target memory cell, and the memory controller 106 can read the swap data from the target memory cell. In some implementations, when storage capacity of ZRAM 504 is tight, swap data corresponding to inactive software or applications can be transferred from ZRAM 504 to memory device 104, and when the inactive software or applications are invoked, the corresponding swap data can be transferred from memory device 104 to ZRAM 504. In this case, more software or applications can be run simultaneously.

[0046] 6 illustrates a block diagram of an exemplary memory device 104 including a memory cell array 301 according to some aspects of the disclosure. The memory cell array 301 can be divided into multiple logical units according to the logical addresses of the memory cells, such as a big LUN 606 (logical unit number), a swap LUN 608, BOOT A 602, and BOOT B 604. In some implementations, the host 108 can access the big LUN 606, the swap LUN 608, BOOT A 602, or BOOT B 604 by sending a command and an address signal of the memory cell. Furthermore, the address signal includes the logical address of the memory cell, and the memory controller 106 translates the logical address into a physical address according to an L2P mapping table.

[0047] In some implementations, the big LUN 606, BOOT A 602, and BOOT B 604 can store user data, and the swap LUN 608 can store swap data. User data can be data received by the host 108 or data generated within the host 108. For example, in a smartphone with a UFS (memory system), user data can be data input by a computer user or data generated during operation of the host 108. In some implementations, BOOT A 602 and BOOT B 604 can also store system data, which can be system programs for an operating system. For example, in a smartphone with a UFS (memory system), the system data stored in the SSD's BOOT A 602 or BOOT B 604 can be a Windows system program. The memory controller 106 can write user data to memory cells corresponding to the big LUN 606, BOOT A 602, and BOOT B 604, and the memory controller 106 can read user data from memory cells corresponding to the big LUN 606, BOOT A 602, and BOOT B 604. The memory controller 106 can write swap data to memory cells corresponding to the swap LUN 608, and the memory controller 106 can read swap data from memory cells corresponding to the swap LUN 608. In other words, the memory cells for storing swap data are separate from the memory cells for storing user data. Because the swap data is accessed more frequently than the user data, the memory cells corresponding to the swap LUN 608 wear out faster than the memory cells corresponding to the big LUN 606, BOOT A 602, or BOOT B 604. Because the swap LUN 608 is separate from the big LUN 606 , BOOT A 602 , or BOOT B 604 , the big LUN 606 , BOOT A 602 , and BOOT B 604 are not affected by the frequent access of the swap LUN 608 .Even if the memory cells corresponding to the swap LUN 608 are worn out, the memory cells corresponding to the big LUN 606, BOOT A 602 and BOOT B 604 are still programmable and readable.

[0048] 7 illustrates a block diagram of an exemplary memory system including a memory controller 106 and a memory device 104 according to some embodiments of the present disclosure. In some implementations, the memory device 104 may include a first memory cell 704 and a second memory cell 706. The first memory cell 704 is configured to store first data, where the first data is user data. The second memory cell 706 is configured to store second data, where the second data is swap data from the host memory 110. Furthermore, the memory controller 106 is coupled between the host 108 and the memory device 104, and the memory controller 106 is configured to write the first data to the first memory cell 704 and / or the second data to the second memory cell 706. In some implementations, the first memory cell 704 may be a memory cell corresponding to the big LUN 606, BOOT A 602, and BOOT B 604, and the second memory cell 706 may be a memory cell corresponding to the swap LUN 608. Because the swap data is accessed more frequently than the user data, the second memory cell 706 wears out faster than the first memory cell 704. Because the second memory cell 706 is isolated from the first memory cell 704, the first memory cell 704 is not affected by the frequent access of the second memory cell 706. Even as the second memory cell 706 wears out, the first memory cell 704 can still be programmed and read.

[0049] In some implementations, the second memory cells 706 can be single-level cells (SLC). Because each memory cell stores one bit of data, SLC can have better performance than multi-level cells (MLC), trinary-level cells (TLC), and quad-level cells (QLC), for example, shorter program times, shorter read times, and more program / erase cycle times. Because the swap LUN 608 is accessed more frequently than the big LUN 606, BOOT A 602, and BOOT B 604, the second memory cells 706 require better performance than the first memory cells 704. Thus, SLC can meet the performance requirements of the second memory cells 706.

[0050] In some implementations, the first memory cells 704 can be MLC, TLC, or QLC. Because each memory cell stores 2 / 3 / 4 bits of data, MLC, TLC, and QLC can have larger storage capacities than SLC. Because the big LUN 606, BOOT A 602, and BOOT B 604 are accessed less frequently than the swap LUN 608 and require larger storage capacities, the first memory cells 704 require lower costs than the second memory cells 706. Therefore, MLC, TLC, and QLC can meet the low cost requirements of the first memory cells 704.

[0051] In some implementations, the memory controller 106 includes a cache 702 and a controller processor 408. The cache 702 can be an SRAM, a DRAM, a NAND flash, a NOR flash, or any other type of memory or electrical device. The controller processor 408 can be a control unit (CU) or an arithmetic logic unit (ALU). For a write operation, based on a write command, the cache 702 is configured to receive first data and / or second data, and the controller processor 408 is configured to write the first data to a first memory cell 704 according to a first address signal and / or write the second data to a second memory cell 706 according to a second address signal. In some implementations, the first address signal can include a first logical address pointing to the big LUN 606, BOOT A 602, and BOOT B 604. The controller processor 408 can translate the first logical address into a first physical address based on the L2P address mapping table, and the first physical address corresponds to the first memory cell 704. Therefore, the memory controller 106 writes the user data to the first memory cell 704 according to the first address signal. In some implementations, the second address signal can comprise a second logical address that points to the swap LUN 608. The controller processor 408 can translate the second logical address into a second physical address based on the L2P address mapping table, and the second physical address corresponds to the second memory cell 706. Therefore, the memory controller 106 writes the swap data to the second memory cell 706 according to the second address signal. For a read operation, based on a read command, the cache 702 is configured to receive first data and / or second data, and the controller processor 408 is configured to read the first data from the first memory cell 704 according to a second address signal and / or read the second data from the second memory cell 706 according to a second address signal.In some implementations, the second address signal may comprise a first logical address pointing to the big LUN 606, BOOT A 602, and BOOT B 604. The controller processor 408 may translate the first logical address into a first physical address based on the L2P address mapping table, and the first physical address corresponds to the first memory cell 704. Therefore, the memory controller 106 reads the user data from the first memory cell 704 according to the second address signal. In some implementations, the second address signal may comprise a second logical address pointing to the swap LUN 608. The controller processor 408 may translate the second logical address into a second physical address based on the L2P address mapping table, and the second physical address corresponds to the second memory cell 706. Therefore, the memory controller 106 reads the swap data from the second memory cell 706 according to the second address signal.

[0052] In some implementations, for a write operation, the memory processor can count the cycle time of the second memory cell 706 and compare the cycle time with a lifetime threshold. When the write time reaches the lifetime threshold, the processor can prohibit writing the second data to the second memory cell 706. The cycle time can be a program / erase time. The swap LUN 608 is accessed more frequently than the big LUN 606, BOOT A 602, and BOOT B 604, and as a result, the second memory cell 706 can wear out faster than the first memory cell 704. By counting the cycle time of the SLC, the remaining lifetime of the second memory cell 706 can be monitored. When the second memory cell 706 wears out, the second memory cell 706 will be disabled in preparation for swap data loss. In some implementations, after the second memory cell 706 is disabled, the host 108 does not transfer swap data to the memory system. In other implementations, after the second memory cell 706 is disabled, the host 108 will still transfer swap data to the memory system, and the memory controller 106 will write the swap data to the first memory cell 704 according to a command provided by the host 108. In some implementations, for a read operation, the memory processor can count the cycle time of the second memory cell 706 and compare the cycle time with a lifetime threshold. When the read time reaches the lifetime threshold, the processor can prohibit reading the second data from the second memory cell 706. The cycle time can be a program / erase time. The swap LUN 608 is accessed more frequently than the big LUN 606, BOOT A 602, and BOOT B 604, and as a result, the second memory cell 706 may wear out faster than the first memory cell 704. By counting the cycle time of the SLC, the remaining lifetime of the second memory cell 706 can be monitored. When the second memory cell 706 wears out, the second memory cell 706 is disabled in preparation for swap data loss. In some implementations, after the second memory cell 706 is disabled, the host 108 does not transfer the swap data to the memory system.In another implementation, after the second memory cell 706 is disabled, the host 108 will still transfer the swap data to the memory system, and the memory controller 106 will read the swap data from the first memory cell 704 according to a command provided by the host 108.

[0053] 8 shows a flowchart of an exemplary method for operating a memory system according to some aspects of the present disclosure. The memory system may be any suitable memory system disclosed herein, such as memory system 102 in FIGS. 4 and 7. Method 800 may be implemented partially or completely by memory system 102 as in FIGS. 4 and 7. It is understood that the operations shown in the method may not be exhaustive, and that other operations may occur before, after, or between any of the illustrated operations. Furthermore, some of the operations may occur simultaneously or in a different order than shown in FIG. 8.

[0054] 8, method 800 begins at operation 802, in which a memory system (e.g., memory system 102 as in FIGS. 4 and 7) receives first data and / or second data from a host (e.g., host 108 in FIGS. 1 and 5). In some implementations, the first data is user data and the second data is swap data from the host memory.

[0055] In some implementations, the memory system may include a memory controller and a memory device, and the memory device may be a NAND flash memory. The memory device may include a first memory cell and a second memory cell.

[0056] In operation 804, as shown in FIG. 8, first data is written to a first memory cell of the memory device and / or second data is written to a second memory cell of the memory device.

[0057] In some implementations, the memory controller is coupled between the host and the memory device, and the memory controller is configured to write first data to the first memory cells and / or second data to the second memory cells. In some implementations, the first memory cells can be memory cells corresponding to the big LUN, BOOT A, and BOOT B, and the second memory cells can be memory cells corresponding to the swap LUN.

[0058] In some implementations, a command and swap data can be sent to a memory controller, and the memory controller can write the swap data to the memory device according to the write command. In some implementations, the host processor can also send an address signal to the memory controller, where the address signal can comprise a logical address, and the controller can translate the logical address into a physical address based on an L2P address mapping table. The L2P address mapping table can be stored in DRAM, NAND flash, or host memory of the memory system. The physical address refers to a memory cell in the memory device, so that the memory controller can write the swap data to the target memory cell, and the memory controller can read the swap data from the target memory cell. In some implementations, when the storage capacity of the ZRAM is low, swap data corresponding to inactive software or applications can be transferred from the ZRAM to the memory device, and when the inactive software or application is called, the corresponding swap data can be transferred from the memory device to the ZRAM. In this case, more software or applications can be run simultaneously.

[0059] In some implementations, the memory controller includes a cache and a controller processor. The cache can be an SRAM, a DRAM, a NAND flash, a NOR flash, or any other type of memory or electrical device. The controller processor can be a control unit (CU) or an arithmetic logic unit (ALU). The cache is configured to receive first data and / or second data, and the controller processor is configured to write the first data to the first memory cell according to a first address signal and / or write the second data to the second memory cell according to the address signal. In some implementations, the address signal can include a first logical address pointing to a big LUN, BOOT A, and BOOT B. The controller processor can translate the first logical address into a first physical address based on an L2P address mapping table, and the first physical address corresponds to the first memory cell. Therefore, the memory controller writes user data to the first memory cell according to the address signal. In some implementations, the address signal can include a second logical address pointing to a swap LUN. The controller processor can translate the second logical address into a second physical address based on the L2P address mapping table, and the second physical address corresponds to the second memory cell, so that the memory controller writes the swap data to the second memory cell according to the address signal.

[0060] In some implementations, the memory processor can count the cycle time of the second memory cell and compare the cycle time with a lifetime threshold. When the write time reaches the lifetime threshold, the processor can prohibit writing the second data to the second memory cell. The cycle time can be a program / erase time. The swap LUN is accessed more frequently than the big LUNs, BOOT A, and BOOT B, and as a result, the second memory cell may wear out faster than the first memory cell. By counting the cycle time of the SLC, the remaining lifetime of the second memory cell can be monitored. When the second memory cell wears out, the second memory cell will be disabled in preparation for swap data loss. In some implementations, after the second memory cell is disabled, the host will not transfer swap data to the memory system. In other implementations, after the second memory cell is disabled, the host will still transfer swap data to the memory system, and the memory controller will write the swap data to the first memory cell according to a command provided by the host.

[0061] 9 shows a flowchart of an exemplary method for operating a memory system according to some aspects of the present disclosure. The memory system may be any suitable memory system disclosed herein, such as memory system 102 in FIGS. 4 and 7. Method 900 may be implemented partially or fully by memory system 102 as in FIGS. 4 and 7. It is understood that the operations shown in the method may not be exhaustive, and that other operations may occur before, after, or between any of the operations shown. Furthermore, some of the operations may occur simultaneously or in a different order than shown in FIG. 8.

[0062] Referring to FIG. 9, method 900 begins at operation 902, in which a memory system (e.g., memory system 102 as in FIGS. 4 and 7) receives a read command, a first address signal, and / or a second address signal from a host (e.g., host 108 in FIGS. 1 and 5).

[0063] In some implementations, the memory system may include a memory controller and a memory device, and the memory device may be a NAND flash memory. The memory device may include a first memory cell and a second memory cell.

[0064] In operation 904, as shown in FIG. 9, first data is read from a first memory cell of the memory device and / or second data is read from a second memory cell of the memory device, where the first data is user data and the second data is swap data from the host memory.

[0065] In some implementations, the memory controller is coupled between the host and the memory device, and the memory controller is configured to read first data from the first memory cells and / or second data from the second memory cells. In some implementations, the first memory cells can be memory cells corresponding to the big LUN, BOOT A, and BOOT B, and the second memory cells can be memory cells corresponding to the swap LUN.

[0066] In some implementations, a command and swap data can be sent to a memory controller, and the memory controller can read the swap data from the memory device according to the read command. In some implementations, the host processor can also send an address signal to the memory controller, where the address signal can comprise a logical address, and the controller can translate the logical address into a physical address based on an L2P address mapping table. The L2P address mapping table can be stored in DRAM, NAND flash, or host memory of the memory system. The physical address points to a memory cell in the memory device, so that the memory controller can read the swap data from the target memory cell, and the memory controller can read the swap data from the target memory cell. In some implementations, when the storage capacity of the ZRAM is low, swap data corresponding to inactive software or applications can be transferred from the ZRAM to the memory device, and when the inactive software or applications are called, the corresponding swap data can be transferred from the memory device to the ZRAM. In this case, more software or applications can be run simultaneously.

[0067] In some implementations, the memory controller includes a cache and a controller processor. The cache can be an SRAM, a DRAM, a NAND flash, a NOR flash, or any other type of memory or electrical device. The controller processor can be a control unit (CU) or an arithmetic logic unit (ALU). The cache is configured to receive first data and / or second data, and the controller processor is configured to read the first data from the first memory cell according to a first address signal and / or read the second data from the second memory cell according to the address signal. In some implementations, the address signal can include a first logical address that points to a big LUN, BOOT A, and BOOT B. The controller processor can translate the first logical address into a first physical address based on an L2P address mapping table, and the first physical address corresponds to the first memory cell. Therefore, the memory controller reads user data from the first memory cell according to the address signal. In some implementations, the address signal can include a second logical address that points to a swap LUN. The controller processor can translate the second logical address into a second physical address based on the L2P address mapping table, and the second physical address corresponds to the second memory cell, so that the memory controller reads the swap data from the second memory cell according to the address signal.

[0068] In some implementations, the memory processor can count the cycle time of the second memory cell and compare the cycle time with a lifetime threshold. When the read time reaches the lifetime threshold, the processor can prohibit reading the second data from the second memory cell. The cycle time can be a program / erase time. The swap LUN is accessed more frequently than the big LUN, BOOT A, and BOOT B, and as a result, the second memory cell may wear out faster than the first memory cell. By counting the cycle time of the SLC, the remaining lifetime of the second memory cell can be monitored. When the second memory cell wears out, the second memory cell will be disabled in preparation for swap data loss. In some implementations, after the second memory cell is disabled, the host will not transfer swap data to the memory system. In other implementations, after the second memory cell is disabled, the host will still transfer swap data to the memory system, and the memory controller will read the swap data from the first memory cell according to a command provided by the host.

[0069] The above description of specific implementations may be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

[0070] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0071] 100 systems 102 Memory System 104 Memory Devices 106 Memory Controller 108 Host 110 host memory 112 Host Processor 129 files 202 Memory Card 204 memory card connector 206 SSD 208 SSD connector 300 memory devices 301 Memory Cell Array 302 Peripheral Circuit 304 Block 306 memory cells 308 NAND memory strings 310 Source Select Gate (SSG) Transistor 312 Drain Select Gate (DSG) Transistor 313 DSG line 314 Common Source Line 315 SSG Line 316 bit lines 318 Word Line 320 pages 408 Controller Processor 411 Volatile Controller Memory 413 Non-volatile Controller Memory 4271 L2P Address Mapping Table 4273 L2P Address Mapping Table 502 Main RAM 504 ZRAM 602 BOOT A 604 BOOT B 606 Big LUN 608 swap LUNs 702 Cache 704 first memory cell 706 second memory cell

Claims

1. A memory system that is coupled to a host, A memory device comprising a NAND flash memory cell array and peripheral circuits coupled to the NAND flash memory cell array, wherein the memory cells of the NAND flash memory cell array are configured to store one or more bits of data; A memory controller coupled to the host and the memory device, It is configured to write user data, including data generated by an application or data entered by a user via the host, to the first memory cell of the NAND flash memory cell array. The NAND flash memory array is configured to write swap data to a second memory cell, the swap data being from the host's random access memory (RAM), and each of the second memory cells is configured to store one bit of data. A memory controller configured to read the swap data from the second memory cell and transmit the swap data to the host, A memory system that includes this.

2. The memory system according to claim 1, wherein the RAM includes ZRAM, and the swap data includes compressed data from the ZRAM.

3. The memory system according to claim 1, wherein the memory controller is further configured to prohibit the second memory cell in response to the cycle time of the second memory cell being greater than or equal to a threshold.

4. The cycle time of the second memory cell includes the program / erase cycle time. The aforementioned threshold includes a lifetime threshold. The memory system according to claim 3, wherein the second memory cell is consumed based on the fact that the cycle time of the second memory cell is equal to or greater than the lifetime threshold.

5. Prohibiting the second memory cell means To prohibit reading the swap data stored in the second memory cell from the second memory cell, or The memory system according to claim 3, further comprising prohibiting the writing of second swap data stored in the NAND flash memory array to the second memory cell.

6. The aforementioned memory controller The memory system according to claim 3, further configured to write the third swap data to the first memory cell in response to a write command instructing the host to write the third swap data from the RAM and the second memory cell being prohibited.

7. The aforementioned memory controller The memory system according to claim 6, further configured to read the third swap data from the first memory cell in response to a read command instructing to read the third swap data.

8. The memory controller is The memory system according to claim 3, further configured not to receive swap data transferred from the RAM of the host to the memory system in response to the second memory cell being prohibited.

9. The NAND flash memory cell array is divided into a plurality of memory regions, the first memory cell corresponds to a first memory region, the second memory cell corresponds to a second memory region, and the memory controller is It is configured to receive a first write command and the user data, The system is configured to write the user data to the first memory cell corresponding to the first memory area, It is configured to receive a second write command, an address signal, and the swap data, wherein the address signal includes a logical address pointing to the second memory area. The memory system according to claim 1, configured to write the swap data to the second memory cell based on the address signal in response to the second write command.

10. The memory system according to claim 1, wherein each of the first memory cells is configured to store multiple bits of data.

11. The memory system according to claim 10, wherein each of the first memory cells is configured to store 2 bits of data, 3 bits of data, or 4 bits of data.

12. The memory system according to claim 1, wherein the swap data corresponds to inactive software or applications.

13. A method for operating a memory system coupled to a host, the memory system comprising a memory device, wherein the memory device comprises a NAND flash memory cell array and peripheral circuits coupled to the NAND flash memory cell array, the memory cells of the NAND flash memory cell array are configured to store one or more bits of data, and the method is The steps include writing user data, including data generated by an application or data entered by a user via the host, to a first memory cell of the NAND flash memory cell array, A step of receiving swap data from the host's random access memory (RAM) and writing the swap data to a second memory cell of the NAND flash memory cell array, wherein each of the second memory cells is configured to store 1 bit of data. A method comprising the steps of reading the swap data from the second memory cell and transmitting the swap data to the host.

14. The method according to claim 13, wherein the RAM includes ZRAM, and the swap data includes compressed data stored from the ZRAM.

15. The method of claim 13, further comprising the step of prohibiting the second memory cell in response to the cycle time of the second memory cell being greater than or equal to a threshold.

16. The cycle time of the second memory cell includes the program / erase cycle time. The aforementioned threshold includes a lifetime threshold. The method according to claim 15, wherein the second memory cell is consumed based on the fact that the cycle time of the second memory cell is equal to or greater than the lifetime threshold.

17. The step of prohibiting the second memory cell is: A step of prohibiting the reading of the first swap data stored in the second memory cell from the second memory cell, or The method according to claim 15, further comprising the step of prohibiting the writing of second swap data stored in the NAND flash memory array to the second memory cell.

18. The step of prohibiting the second memory cell is: A step of prohibiting the reading of the first swap data stored in the second memory cell from the second memory cell, or The method according to claim 15, further comprising the step of prohibiting the writing of second swap data stored in the NAND flash memory array to the second memory cell.

19. The method of claim 15, further comprising the steps of writing the third swap data to the first memory cell in response to a write command instructing the host to write the third swap data from the RAM and the second memory cell being prohibited.

20. The method according to claim 19, further comprising the step of reading the third swap data from the first memory cell in response to a read command instructing to read the third swap data.

21. The method of claim 15, further comprising the step of not receiving swap data transferred from the RAM of the host to the memory system in response that the second memory cell is prohibited.

22. The NAND flash memory cell array is divided into a plurality of memory regions, the first memory cell corresponds to the first memory region, and the second memory cell corresponds to the second memory region. The step of writing the user data to the first memory cell is, The steps include receiving a first write command and the user data, The process includes the step of writing the user data to the first memory cell corresponding to the first memory area, The steps of receiving the swap data and writing the swap data to the second memory cell are: A step of receiving a second write command, an address signal, and the swap data, wherein the address signal includes a logical address pointing to the second memory area. The method according to claim 13, comprising the step of writing the swap data to the second memory cell based on the address signal in response to the second write command.

23. The method according to claim 13, wherein each of the first memory cells is configured to store multiple bits of data.

24. The method according to claim 13, wherein each of the first memory cells is configured to store 2 bits of data, 3 bits of data, or 4 bits of data.

25. The method according to claim 13, wherein the swap data corresponds to inactive software or applications.

26. It is a system, A host including RAM, A memory system comprising a memory device and a memory controller, wherein the memory device comprises a NAND flash memory cell array and peripheral circuits coupled to the NAND flash memory cell array, the memory cells of the NAND flash memory cell array are configured to store one or more bits of data, and the memory controller is coupled to the host and the memory device, It is configured to write user data, including data generated by an application or data entered by a user via the host, to the first memory cell of the NAND flash memory cell array. The NAND flash memory array is configured to write swap data to a second memory cell, the swap data being from the host's random access memory (RAM), and each of the second memory cells is configured to store one bit of data. A memory system configured to read the swap data from the second memory cell and transmit the swap data to the host, A system that includes this.

27. The system according to claim 26, wherein the RAM includes ZRAM, and the swap data includes compressed data from the ZRAM.

28. The system according to claim 27, wherein the swap data corresponds to inactive software or applications.

29. The host further includes a host processor, and the host processor is The system according to claim 27, configured to transfer the swap data corresponding to inactive software or applications from the ZRAM to the memory controller in response to the limited storage capacity of the ZRAM, and to instruct the memory controller to write the swap data corresponding to the inactive software or applications to the second memory cell.

30. The host further includes a host processor, and the host processor is Call one inactive software or application, The read command is sent to the memory controller, which instructs the memory controller to read the swap data corresponding to the called inactive software or application from the second memory cell, and transfers the swap data corresponding to the called inactive software or application to the ZRAM. The system according to claim 29, configured as follows.

31. The system according to claim 26, wherein the memory controller is further configured to prohibit the second memory cell in response to the cycle time of the second memory cell being greater than or equal to a threshold.

32. The cycle time of the second memory cell includes the program / erase cycle time, The aforementioned threshold includes a lifetime threshold. The system according to claim 31, wherein the second memory cell is consumed based on the fact that the cycle time of the second memory cell is equal to or greater than the lifetime threshold.

33. Prohibiting the second memory cell means To prohibit reading the first swap data stored in the second memory cell from the second memory cell, or The system according to claim 31, further comprising prohibiting the writing of second swap data stored in the NAND flash memory array to the second memory cell.

34. The system according to claim 31, wherein the host is configured not to send swap data to the memory controller in response to the second memory cell being prohibited.

35. The aforementioned memory controller The system according to claim 31, further configured to receive write commands from the host instructing the memory controller to write a third swap data from the RAM of the host and to write the third swap data to the first memory cell in response to the second memory cell being prohibited.

36. The memory controller is The system according to claim 35, further configured to read the third swap data from the first memory cell in response to a read command instructing to read the third swap data.

37. The NAND flash memory cell array is divided into a plurality of memory regions, the first memory cell corresponds to the first memory region, the second memory cell corresponds to the second memory region, and the memory controller is It is configured to receive a first write command and the user data, The system is configured to write the user data to the first memory cell corresponding to the first memory area, It is configured to receive a second write command, an address signal, and the swap data, wherein the address signal includes a logical address pointing to the second memory area. The system according to claim 26, configured to write the swap data to the second memory cell based on the address signal in response to the second write command.

38. The system according to claim 26, wherein each of the first memory cells is configured to store multiple bits of data.

39. The system according to claim 38, wherein each of the first memory cells is configured to store 2 bits of data, 3 bits of data, or 4 bits of data.

Images