Power supply control device and power supply device

Abstract

To suppress overshoot and undershoot of an output voltage.SOLUTION: The power supply control device 1 is a main controller of a power supply device X that generates an output voltage Vout from an input voltage Vin. The power control device 1 includes a reference voltage generation circuit 20 that generates a first reference voltage Vref having a variable voltage, a filter circuit 40 that performs low pass filter processing and high pass filter processing on the first reference voltage Vref to generate a second reference voltage Vref2, and a control circuit 30 that performs feedback control of the power supply device X so that the voltage Vout or a feedback voltage Vfb corresponding to the voltage Vout matches the second reference voltage Vref2.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a power supply control device and a power supply device. [Background technology]

[0002] Power supply devices that generate an output voltage from an input voltage are used in a variety of applications.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-089043

[0005] [overview] In conventional power supply devices, particularly in the power supply control device that serves as the main controller, there is room for improvement in variable control of the output voltage.

[0006] For example, a power supply control device according to the present disclosure is configured to be the main controller of a power supply device that generates an output voltage from an input voltage, and includes a reference voltage generation circuit configured to generate a first reference voltage having a variable voltage value, a filter circuit configured to generate a second reference voltage by performing low-pass filtering and high-pass filtering on the first reference voltage, and a control circuit configured to perform output feedback control of the power supply device so that the output voltage or a feedback voltage corresponding thereto matches the second reference voltage. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a first embodiment of a power supply device. [Figure 2] FIG. 2 is a diagram showing how overshoot and undershoot occur in the output voltage when the reference voltage is changed. [Figure 3] FIG. 3 is a diagram showing a first method for suppressing overshoot and undershoot in the first embodiment. [Figure 4] FIG. 4 is a diagram showing a second method for suppressing overshoot and undershoot in the first embodiment. [Figure 5] FIG. 5 is a diagram showing a second embodiment of the power supply device. [Figure 6] FIG. 6 is a diagram illustrating a first configuration example of a filter circuit. [Figure 7] FIG. 7 is a diagram showing how overshoot and undershoot of the output voltage are suppressed by introducing a filter circuit. [Figure 8] FIG. 8 is a diagram showing the relationship between the change amount of the reference voltage and the output slew rate. [Figure 9] FIG. 9 is a diagram illustrating a second configuration example of the filter circuit.

[0008] [Detailed explanation] <Power Supply Device (First Embodiment)> FIG. 1 is a diagram showing a first embodiment of a power supply device X (corresponding to a comparative example to be compared with a second embodiment described later). The power supply device X of this embodiment may be a switching power supply that generates a desired output voltage Vout from an input voltage Vin. However, the power supply device X is not limited to a switching power supply, and may also be a linear power supply, for example, an LDO (low drop out) regulator.

[0009] Referring to this figure, the power supply device X comprises a power supply control device 1, and an inductor L1 and a capacitor C1 that are externally connected to the power supply control device 1.

[0010] The power supply control device 1 may be a semiconductor integrated circuit device, a so-called power supply control IC (integrated circuit), that serves as the main controller of the power supply device X. The power supply control device 1 may include external terminals T1 to T4 as means for establishing electrical connection with the outside of the device.

[0011] The external terminal T1 is a power supply terminal and can be connected to the application terminal of the input voltage Vin. The external terminal T2 is a switch terminal and is connected to the first terminal of the inductor L1. The external terminal T3 is a ground terminal and is connected to the application terminal of the ground voltage GND. The external terminal T4 is a feedback terminal and is connected to the application terminal of the output voltage Vout. The second terminal of the inductor L1 and the first terminal of the capacitor C1 are both connected to the application terminal of the output voltage Vout. The second terminal of the capacitor C1 is connected to the application terminal of the ground voltage GND.

[0012] The inductor L1 and the capacitor C1 function as a rectifying and smoothing circuit that rectifies and smoothes the switch voltage Vsw appearing at the external terminal T2 to generate the output voltage Vout.

[0013] <Power supply control device> 1, the configuration and operation of the power supply control device 1 will be described. The power supply control device 1 includes an output circuit 10, a reference voltage generating circuit 20, and a control circuit 30.

[0014] The output circuit 10 generates a switch voltage Vsw that is pulse-driven between an input voltage Vin and a ground voltage GND and outputs the switch voltage Vsw from an external terminal T2. Referring to the figure, the output circuit 10 includes transistors 11 and 12. The transistor 11 may be, for example, a P-channel type, while the transistor 12 may be, for example, an N-channel type.

[0015] The source and back gate of transistor 11 are both connected to external terminal T1. The source and back gate of transistor 12 are both connected to external terminal T3. The drains of transistors 11 and 12 are both connected to external terminal T2. The gate of transistor 11 is connected to an application terminal of gate signal G1. The gate of transistor 12 is connected to an application terminal of gate signal G2.

[0016] The transistor 11 is in an off state when the gate signal G1 is at a high level. The transistor 11 is in an on state when the gate signal G1 is at a low level. The transistor 12 is in an on state when the gate signal G2 is at a high level. The transistor 12 is in an off state when the gate signal G2 is at a low level.

[0017] When transistor 11 is turned on and transistor 12 is turned off, the switch voltage Vsw is at a high level (≈Vin). On the other hand, when transistor 12 is turned off and transistor 12 is turned on, the switch voltage Vsw is at a low level (≈GND). In this way, the switch voltage Vsw can be pulse-driven between the input voltage Vin and the ground voltage GND.

[0018] In this figure, a step-down output circuit 10 is shown as an example. However, the output format of the output circuit 10 is not limited to step-down, and may be step-up, step-down, or inverting. Furthermore, in accordance with a change in the output format, the discrete components externally attached to the power supply control device 1 (inductor L1 and capacitor C1 in this figure) may also be changed as appropriate.

[0019] The reference voltage generation circuit 20 generates a reference voltage Vref and outputs it to the control circuit 30. The reference voltage Vref corresponds to a target value of the output voltage Vout. The reference voltage generation circuit 20 may have a function of variably controlling the voltage value of the reference voltage Vref, and therefore the target value of the output voltage Vout, in response to, for example, a control signal externally input to the power supply control device 1 or a control signal read from an internal memory (not shown), a so-called VID (voltage identification) function.

[0020] The control circuit 30 performs output feedback control of the power supply X, specifically, duty control of the gate signals G1 and G2, so that the output voltage Vout or a feedback voltage Vfb corresponding thereto coincides with the reference voltage Vref. Note that any known technology (such as voltage mode control, current mode control, or hysteresis control) can be applied to the topology of the control circuit 30.

[0021] In this diagram, the output voltage Vout is input directly to the control circuit 30 as the feedback voltage Vfb. However, the feedback voltage Vfb may be a divided voltage of the output voltage Vout. In this case, a voltage divider circuit that divides the output voltage Vout to generate the feedback voltage Vfb may be built into or external to the power supply control device 1.

[0022] 2 is a diagram showing how overshoot and undershoot occur in the output voltage Vout when the reference voltage Vref is changed. In this diagram, from top to bottom, the output voltage Vout and the reference voltage Vref are depicted.

[0023] As shown in the figure, the power supply control device 1 can change the target value of the output voltage Vout by switching the reference voltage Vref. For example, when the application incorporating the power supply device X is in high-performance mode, the reference voltage Vref and therefore the target value of the output voltage Vout may be increased. On the other hand, when the application incorporating the power supply device X is in power-saving mode, the reference voltage Vref and therefore the target value of the output voltage Vout may be decreased. This type of power supply control can achieve both high performance and low power consumption for the application.

[0024] For example, a power supply device X for an SoC (system on chip) application is required to change the target value of the output voltage Vout as quickly as possible. To meet this requirement, for example, it is possible to change the reference voltage Vref sharply, that is, to design the slew rate SR of the reference voltage Vref to a large value. The slew rate SR can be understood as the rate of change (slope) of the reference voltage Vref.

[0025] However, if the reference voltage Vref is changed abruptly, an overshoot and an undershoot may occur in the output voltage Vout, as shown by dashed lines α1 and α2, respectively.

[0026] FIG. 3 is a diagram illustrating a first suppression technique for overshoot and undershoot in the first embodiment. In this diagram, as in FIG. 2, the output voltage Vout and the reference voltage Vref are depicted from top to bottom. The solid lines represent waveforms when the first suppression technique is applied. On the other hand, the dashed lines represent behavior when the first suppression technique is not applied, i.e., waveforms similar to those in FIG. 2.

[0027] In the first suppression method shown in the figure, the slew rate SR of the reference voltage Vref is reduced when the output voltage Vout approaches the changed target value. This slew rate control can suppress overshoot and undershoot of the output voltage Vout, as shown by dashed lines β1 and β2, respectively.

[0028] However, as the slew rate SR is reduced, the monotonicity of the output voltage Vout may be lost during the change. For example, when focusing on the dashed-line frame β1, the output voltage Vout changes from increasing to decreasing, then increases again and converges to the changed target value. In other words, the output voltage Vout no longer increases monotonically to the changed target value. On the other hand, when focusing on the dashed-line frame β2, the output voltage Vout changes from decreasing to increasing, then decreases again and converges to the changed target value. In other words, the output voltage Vout no longer decreases monotonically to the changed target value. Therefore, with the first suppression method shown in this figure, it is difficult to quickly switch the target value of the output voltage Vout.

[0029] 4 is a diagram showing a second method for suppressing overshoot and undershoot in the first embodiment. In the second suppression method shown in this figure, the slew rate SR of the reference voltage Vref is reduced in stages as the reference voltage Vref approaches the changed set value.

[0030] For example, consider the case where the reference voltage Vref is raised from the set value VrefL to the set value VrefH. In this case, the slew rate SR of the reference voltage Vref is switched to one of the set values SR1 to SR5 according to the voltage value of the reference voltage Vref. However, it is assumed that the set values SR1 to SR5 satisfy SR1 > SR2 >... > SR5 > 0. That is, when the slew rate SR is set to the set value SR1, the reference voltage Vref rises with the steepest positive slope. On the other hand, each time the slew rate SR is sequentially switched to the set values SR2 to SR5, the slope of the reference voltage Vref gradually becomes gentler step by step.

[0031] Speaking in accordance with this figure, when VrefL ≤ Vref < VrefH - x (for example, x = 200 mV), the slew rate SR is set to the set value SR1. When VrefH - x ≤ Vref < VrefH - x / 2, the slew rate SR is set to the set value SR2. When VrefH - x / 2 ≤ Vref < VrefH - x / 4, the slew rate SR is set to the set value SR3. When VrefH - x / 4 ≤ Vref < VrefH - x / 8, the slew rate SR is set to the set value SR4. When VrefH - x / 8 ≤ Vref < VrefH, the slew rate SR is set to the set value SR5.

[0032] Also, for example, consider the case where the reference voltage Vref is lowered from the set value VrefH to the set value VrefL. In this case, the slew rate SR of the reference voltage Vref is switched to one of the set values SR6 to SR10 according to the voltage value of the reference voltage Vref. However, it is assumed that the set values SR6 to SR10 satisfy SR6 < SR7 <... < SR10 < 0. That is, when the slew rate SR is set to the set value SR6, the reference voltage Vref drops with the steepest negative slope. On the other hand, each time the slew rate SR is sequentially switched to the set values SR7 to SR10, the slope of the reference voltage Vref gradually becomes gentler step by step.

[0033] Referring to this figure, when VrefL + y < Vref ≤ VrefH (for example, y = 200 mV), the slew rate SR is set to the set value SR6. When VrefL + x / 2 < Vref ≤ VrefL + y, the slew rate SR is set to the set value SR7. When VrefL + x / 4 < Vref ≤ VrefL + x / 2, the slew rate SR is set to the set value SR8. When VrefL + x / 8 < Vref ≤ VrefL + x / 4, the slew rate SR is set to the set value SR9. When VrefL < Vref ≤ VrefL + y / 8, the slew rate SR is set to the set value SR10.

[0034] However, in the second suppression method, the time required for the output voltage Vout to reach the target value becomes longer. As a result, the mode transition of the application is delayed. In particular, when the switching step width of the reference voltage Vref is small, that is, when the set values VrefH and VrefL before and after switching are close, the absolute value of the slew rate SR is initially small, so the above-mentioned excess is more likely to become apparent.

[0035] <Power supply device (Second embodiment)> FIG. 5 is a diagram showing a second embodiment of the power supply device X. In the power supply device X of this embodiment, while being based on the above-described first embodiment (FIG. 1), the power control device 1 has been modified. Referring to this figure, the power control device 1 further includes a filter circuit 40.

[0036] The filter circuit 40 performs low-pass filter processing and high-pass filter processing on the reference voltage Vref to generate a reference voltage Vref2.

[0037] The cut-off frequency fc1 of the low-pass filter processing and the cut-off frequency fc2 of the high-pass filter processing can be appropriately set in consideration of the inductance value of the inductor L1, the capacitance value of the capacitor C1, the feedback loop gain of the control circuit 30, and the like.

[0038] For example, if the switching frequency fsw of the power supply device X is several hundred kHz, the cutoff frequency fc2 of the high-pass filtering may be set to, for example, several tens of kHz. That is, the cutoff frequency f2 may be set to about 1 / 10 of the switching frequency fsw, or, from another perspective, near the unity gain frequency of the feedback loop. On the other hand, the cutoff frequency fc1 of the low-pass filtering may be set to, for example, several kHz. That is, the cutoff frequency fc1 may be set to a value lower than the cutoff frequency fc2.

[0039] When the switching frequency fsw is several MHz, the cutoff frequencies fc1 and fc2 may be set in a frequency band higher than the above setting example.

[0040] A filtered reference voltage Vref2 is input to the control circuit 30 instead of the reference voltage Vref. The control circuit 30 then performs output feedback control of the power supply device X so that the feedback voltage Vfb coincides with the reference voltage Vref2.

[0041] <Filter circuit (first configuration example)> 6 is a diagram showing a first configuration example of the filter circuit 40. The filter circuit 40 of this configuration example includes a resistor 41 and capacitors 42 and 43.

[0042] The resistor 41 and the capacitor 42 are connected in parallel between the application terminal of the reference voltage Vref and the application terminal of the reference voltage Vref2. The resistance value of the resistor 41 may be, for example, 2 MΩ. The capacitance value of the capacitor 42 may be, for example, 5 pF. The capacitor 43 is connected between the application terminal of the reference voltage Vref2 and the ground terminal.

[0043] FIG. 7 is a diagram showing how the introduction of the filter circuit 40 suppresses overshoot and undershoot of the output voltage Vout.

[0044] The upper part of this figure depicts the output voltage Vout. The solid line represents the waveform when the filter circuit 40 is introduced. On the other hand, the dashed line represents the behavior when the filter circuit 40 is not introduced, i.e., the waveform is the same as that shown in Figure 2 above.

[0045] In addition, the lower part of the figure depicts the reference voltage Vref (dashed line) before filtering and the reference voltage Vref2 (solid line) after filtering.

[0046] As shown in this figure, the reference voltage Vref2 changes gradually with respect to the reference voltage Vref1 without requiring the switching control of the slew rate SR introduced in the first suppression method (FIG. 3) and the second suppression method (FIG. 4) described above.

[0047] By introducing the filter circuit 40, as shown by dashed lines γ1 and γ2, overshoot and undershoot of the output voltage Vout can be suppressed without slowing down the change speed of the output voltage Vout. Furthermore, when the output voltage Vout is changed, linearity can be improved over the entire variable range.

[0048] 8 is a diagram showing the relationship between the amount of change in the reference voltage Vref2 and the output slew rate. In this diagram, from top to bottom, the output voltage Vout and the reference voltage Vref are depicted. The solid line, small dashed line, large dashed line, dashed-dotted line, double-dashed line, and dashed-dotted-double-dashed line for the output voltage Vout can be understood as representing the change behavior corresponding to the solid line, small dashed line, large dashed line, dashed-dotted line, double-dashed line, and dashed-dotted-double-dashed line for the reference voltage Vref, respectively.

[0049] As is clear from this figure, by introducing the filter circuit 40, the slew rate SR of the output voltage Vout can be maintained almost constant regardless of the switching step width of the reference voltage Vref. In other words, unlike the second suppression method (FIG. 4) mentioned above, even if the switching step width of the reference voltage Vref is small, the slew rate SR of the output voltage Vout is unlikely to decrease. Therefore, the time required for the output voltage Vout to reach the target value can be shortened. As a result, quick mode transitions in applications are possible.

[0050] <Filter circuit (second configuration example)> 9 is a diagram showing a second configuration example of the filter circuit 40. The filter circuit 40 of this configuration example includes a low-pass filter processing circuit 44 and an averaging processing circuit 45.

[0051] The low-pass filtering circuit 44 performs low-pass filtering on the digital signal D1 to generate a digital signal D2. The digital signal D1 has a digital value corresponding to the voltage value (analog value) of the reference voltage Vref. In other words, the digital signal D1 can be understood as a signal equivalent to the reference voltage Vref. An ADC (analog to digital converter) may be provided between the reference voltage generating circuit 20 and the low-pass filtering circuit 44.

[0052] The averaging circuit 45 averages the digital signals D1 and D2 to generate a digital signal D3. The digital signal D3 has a digital value corresponding to the voltage value (analog value) of the reference voltage Vref2. In other words, the digital signal D3 can be understood as a signal equivalent to the reference voltage Vref2. A DAC (digital-to-analog converter) may be provided between the averaging circuit 45 and the control circuit 30.

[0053] In this way, the filter circuit 40 may be implemented as a digital filter, unlike the first configuration example (FIG. 6).

[0054] <Additional Notes> The power supply control device according to the present disclosure makes it possible to suppress overshoot and undershoot of the output voltage that may occur when the reference voltage (corresponding to the target value of the output voltage) is changed.

[0055] [Appendix 1] A power supply control device configured to be a main controller of a power supply device (X) that generates an output voltage (Vout) from an input voltage (Vin), a reference voltage generating circuit (20) configured to generate a first reference voltage (Vref) having a variable voltage value; a filter circuit (40) configured to generate a second reference voltage (Vref2) by performing low-pass filtering and high-pass filtering on the first reference voltage (Vref); a control circuit (30) configured to perform output feedback control of the power supply device (X) so that the output voltage (Vout) or a feedback voltage (Vfb) corresponding thereto coincides with the second reference voltage (Vref2); A power supply control device (1) comprising:

[0056] [Appendix 2] The power supply control device (1) according to appendix 1, wherein a first cutoff frequency (fc1) of the low-pass filtering is lower than a second cutoff frequency (fc2) of the high-pass filtering.

[0057] [Appendix 3] The filter circuit (40) a resistor (41) and a first capacitor (42) connected in parallel between an application terminal of the first reference voltage (Vref) and an application terminal of the second reference voltage (Vref2); a second capacitor (43) connected between the application terminal of the second reference voltage (Vref2) and a ground terminal; The power supply control device (1) according to appendix 1 or 2, comprising:

[0058] [Appendix 4] The filter circuit (40) a low-pass filter processing circuit (44) configured to generate a second digital signal (D2) by performing low-pass filtering on a first digital signal (D1) corresponding to the first reference voltage (Vref); an averaging circuit (45) configured to perform averaging on the first digital signal (D1) and the second digital signal (D2) to generate a third digital signal (D3) corresponding to the second reference voltage (Vref2); The power supply control device (1) according to appendix 1 or 2, comprising:

[0059] [Appendix 5] A power supply device (X) comprising the power supply control device (1) according to any one of appendices 1 to 4.

[0060] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0061] 1 Power supply control device 10 Output circuit 11, 12 Transistors 20 Reference voltage generation circuit 30 Control circuit 40 Filter Circuit 41 Resistance 42, 43 Capacitor 44 Low-pass filter processing circuit 45 Averaging processing circuit C1 capacitor L1 inductor T1~T4 external terminals X Power supply

Claims

1. A power supply control device configured to be a main controller of a power supply device that generates an output voltage from an input voltage, a reference voltage generating circuit configured to generate a first reference voltage having a variable voltage value; a filter circuit configured to perform low-pass filtering and high-pass filtering on the first reference voltage to generate a second reference voltage; a control circuit configured to perform output feedback control of the power supply device so that the output voltage or a feedback voltage corresponding thereto coincides with the second reference voltage; A power supply control device comprising:

2. 2. The power supply control device according to claim 1, wherein a first cutoff frequency of the low-pass filtering is lower than a second cutoff frequency of the high-pass filtering.

3. The filter circuit comprises: a resistor and a first capacitor connected in parallel between the application terminal of the first reference voltage and the application terminal of the second reference voltage; a second capacitor connected between the application terminal of the second reference voltage and a ground terminal; The power control device of claim 1 , comprising:

4. The filter circuit comprises: a low-pass filtering circuit configured to perform low-pass filtering on a first digital signal corresponding to the first reference voltage to generate a second digital signal; an averaging circuit configured to perform averaging on the first digital signal and the second digital signal to generate a third digital signal corresponding to the second reference voltage; The power control device of claim 1 , comprising:

5. A power supply device comprising the power supply control device according to any one of claims 1 to 4.

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