Display device

Abstract

To provide a display device which can be driven at high speed.SOLUTION: The display device includes a first transistor whose switching is controlled using a first control signal and which is connected between an image data signal line and a first node, a second transistor whose switching is controlled using a second control signal and which is connected between a power supply line and the first node, a third transistor whose gate electrode is connected to the second node and which is connected between the power supply line and the second node, a fourth transistor whose switching is controlled using a third control signal and which is connected between the reference voltage power supply line and the second node, a fifth transistor whose switching is controlled using a fourth control signal and which is connected between the initialization voltage power supply line and the third node, and a sixth transistor electrically connected between the pre-charge voltage power supply line and the first node.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices equipped with light-emitting elements that emit light in a self-luminous manner (self-luminous display devices) have become widespread. For example, the light-emitting elements are light-emitting diodes (LEDs), tiny light-emitting diodes (micro LEDs), or organic electroluminescence (EL) elements. The self-luminous display device includes a plurality of pixels and a control circuit for driving the plurality of pixels. When the control circuit supplies a voltage to each of the plurality of pixels, a current corresponding to the supplied voltage value flows through the light-emitting element included in each of the plurality of pixels. Each of the light-emitting elements emits light at a brightness corresponding to the current flowing through the light-emitting element, and the pixel including the light-emitting element can display an image with a gradation corresponding to the brightness.

[0003] For example, Patent Document 1 discloses a display device that includes an organic light-emitting element and is capable of suppressing display defects such as display unevenness by using a precharge voltage generated by a source driver IC. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-37844 Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, display devices including organic light-emitting elements have been required to operate at higher speeds in order to accommodate higher resolutions, larger screens, or higher frequencies. Furthermore, when display devices including organic light-emitting elements are required to accommodate higher resolutions, larger screens, or higher frequencies, it is expected that the power consumption of the display devices will increase, and therefore there is a demand for reducing the power consumption of the display devices.

[0006] In view of the above, an object of one embodiment of the present invention is to provide a display device that can be driven at high speed and that can reduce power consumption. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention includes a first transistor whose switching is controlled by a first control signal and electrically connected between an image data signal line to which a data voltage is supplied and a first node; a third transistor whose switching is controlled by a second control signal different from the first control signal and electrically connected between the first node and a second node; a second transistor whose gate electrode is electrically connected to the second node and electrically connected between a power supply line to which a constant voltage is supplied and the third node; and a third transistor whose switching is controlled by a third control signal different from the first control signal and the second control signal and electrically connected between a reference voltage power supply line to which a reference voltage is supplied and the second node. a fourth transistor whose switching is controlled by a fourth control signal different from the first control signal, the second control signal, and the third control signal, and whose first node is electrically connected to an initialization voltage power supply line to which an initialization voltage is supplied; a fifth transistor whose switching is controlled by a fifth control signal different from the first control signal, the second control signal, the third control signal, and the fourth control signal, and whose first node is electrically connected to a precharge voltage power supply line to which a precharge voltage is supplied; a light-emitting element electrically connected to the third node; and a capacitive element electrically connected between the first node and the third node.

[0008] a third transistor whose switching is controlled by a second control signal different from the first control signal and electrically connected between the first node and a second node; a second transistor whose gate electrode is electrically connected to the second node and electrically connected between a power supply line to which a constant voltage is supplied and the third node; a fourth transistor whose switching is controlled by a third control signal different from the first control signal and the second control signal and electrically connected between the second node and a scan voltage signal line to which an initialization voltage, a reference voltage, and a precharge voltage are supplied; a fifth transistor whose switching is controlled by a fourth control signal different from the first control signal, the second control signal, and the third control signal and electrically connected between the scan voltage signal line and the third node; a light-emitting element electrically connected to the third node; [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram illustrating a configuration of a display device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a schematic diagram showing input signals to a pixel circuit according to the first embodiment of the present invention. [Figure 3] 1 is a circuit diagram showing a configuration of a pixel circuit according to a first embodiment of the present invention. [Figure 4] 3 is a timing chart of the display device according to the first embodiment of the present invention. [Figure 5] 3 is a timing chart of the display device according to the first embodiment of the present invention. [Figure 6] 3 is a timing chart of the display device according to the first embodiment of the present invention. [Figure 7] 3 is a timing chart of the display device according to the first embodiment of the present invention. [Figure 8] 3 is a timing chart of the display device according to the first embodiment of the present invention. [Figure 9] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 10] FIG. 10 is an end view showing an end surface cut along A1-A2 in the layout shown in FIG. 9. [Figure 11] FIG. 3 is a sequence diagram showing a manufacturing method of the display device according to the first embodiment of the present invention. [Figure 12] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 13] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 14] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 15] FIG. 10 is a schematic diagram showing input signals to a pixel circuit according to a second embodiment of the present invention. [Figure 16] FIG. 4 is a circuit diagram showing a configuration of a pixel circuit according to a second embodiment of the present invention. [Figure 17] 10 is a timing chart of a display device according to a second embodiment of the present invention. [Figure 18] 10 is a timing chart of a display device according to a second embodiment of the present invention. [Figure 19] 10 is a timing chart of a display device according to a second embodiment of the present invention. [Figure 20] 10 is a timing chart of a display device according to a second embodiment of the present invention. [Figure 21] FIG. 10 is a schematic diagram showing input signals to a pixel circuit according to a third embodiment of the present invention. [Figure 22] FIG. 10 is a circuit diagram showing a configuration of a pixel circuit according to a third embodiment of the present invention. [Figure 23] 10 is a timing chart of a display device according to a third embodiment of the present invention. [Figure 24] 10 is a timing chart of a display device according to a third embodiment of the present invention. [Figure 25]10 is a timing chart of a display device according to a third embodiment of the present invention. [Figure 26] 10 is a timing chart of a display device according to a third embodiment of the present invention. [Figure 27] 10 is a timing chart of a display device according to a third embodiment of the present invention. [Figure 28] FIG. 10 is a schematic diagram showing input signals to a pixel circuit according to a fourth embodiment of the present invention. [Figure 29] FIG. 10 is a circuit diagram showing a configuration of a pixel circuit according to a fourth embodiment of the present invention. [Figure 30] 10 is a timing chart of a display device according to a fourth embodiment of the present invention. [Figure 31] 10 is a timing chart of a display device according to a fourth embodiment of the present invention. [Figure 32] 10 is a timing chart of a display device according to a fourth embodiment of the present invention. [Figure 33] 10 is a timing chart of a display device according to a fourth embodiment of the present invention. [Figure 34] FIG. 10 is a diagram illustrating the setting of an input signal according to the fourth embodiment of the present invention. [Figure 35] FIG. 11 is a schematic diagram showing input signals to a pixel circuit according to a fifth embodiment of the present invention. [Figure 36] FIG. 10 is a circuit diagram showing a configuration of a pixel circuit according to a fifth embodiment of the present invention. [Figure 37] 10 is a timing chart of a display device according to a fifth embodiment of the present invention. [Figure 38] 10 is a timing chart of a display device according to a fifth embodiment of the present invention. [Figure 39] 10 is a timing chart of a display device according to a fifth embodiment of the present invention. [Figure 40] 10 is a timing chart of a display device according to a fifth embodiment of the present invention. [Figure 41] FIG. 13 is a schematic diagram showing input signals to a pixel circuit according to a sixth embodiment of the present invention. [Figure 42]FIG. 10 is a circuit diagram showing the configuration of a pixel circuit according to a sixth embodiment of the present invention. [Figure 43] 10 is a timing chart of a display device according to a sixth embodiment of the present invention. [Figure 44] 10 is a timing chart of a display device according to a sixth embodiment of the present invention. [Figure 45] 10 is a timing chart of a display device according to a sixth embodiment of the present invention. [Figure 46] 10 is a timing chart of a display device according to a sixth embodiment of the present invention. [Figure 47] FIG. 13 is a schematic diagram showing input signals to a pixel circuit according to a seventh embodiment of the present invention. [Figure 48] FIG. 12 is a circuit diagram showing a configuration of a pixel circuit according to a seventh embodiment of the present invention. [Figure 49] 13 is a timing chart of a display device according to a seventh embodiment of the present invention. [Figure 50] 13 is a timing chart of a display device according to a seventh embodiment of the present invention. [Figure 51] 10 is a timing chart of a display device according to a seventh embodiment of the present invention. [Figure 52] 13 is a timing chart of a display device according to a seventh embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different forms, and should not be construed as being limited to the description of the embodiments exemplified below. Furthermore, in order to clarify the explanation, the drawings may show the width, thickness, shape, configuration, etc. of each part schematically compared to the actual form, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, the letters "first" and "second" attached to each element are convenient labels used to distinguish each element, and have no other meaning unless otherwise specified.

[0011] Furthermore, in this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0012] In one embodiment of the present invention, when the expressions "same," "identical," and "match" are used, the expressions "same," "identical," and "match" may include a tolerance within the design range. In addition, in one embodiment of the present invention, when a tolerance within the design range is included, the expressions "approximately identical" and "approximately match" may be used.

[0013] For example, a display device according to one embodiment of the present invention is a display device that uses EL elements as light-emitting elements that emit light in a self-luminous manner. For example, a display device that uses EL elements may be called a self-luminous display device, an EL display device, or the like.

[0014] 1. First Embodiment <1-1. Overview of the display device 10> An overview of a display device 10 according to a first embodiment will be described with reference to Fig. 1. Fig. 1 is a schematic diagram showing the configuration of the display device 10. The configuration of the display device 10 shown in Fig. 1 is an example, and the configuration of the display device 10 is not limited to the configuration shown in Fig. 1.

[0015] The display device 10 includes an array substrate 100, a flexible printed circuit board 200 (FPC 200), and an IC chip 110. The display device 10 also includes a display area 22 provided on the array substrate 100, a peripheral area 24 surrounding the display area 22, and a terminal area 26.

[0016] The display region 22 includes a plurality of pixels 180. For example, the plurality of pixels 180 are arranged in a matrix along a first direction D1 (column direction) and a second direction D2 (row direction) intersecting the first direction D1. The pixel 180 is the smallest unit that constitutes part of an image displayed in the display region 22. For example, each of the plurality of pixels 180 may correspond to a sub-pixel R, a sub-pixel G, and a sub-pixel B. One pixel may also be formed by three sub-pixels. There are no limitations on the arrangement of the pixels 180, and the arrangement of the pixels 180 may be a stripe arrangement, a delta arrangement, a pentile arrangement, or the like. For example, the arrangement of the plurality of pixels 180 is a stripe arrangement.

[0017] The subpixels R, G, and B are configured to display images of different colors. For example, each of the subpixels R, G, and B includes a light-emitting element including a light-emitting layer that emits red, green, and blue, respectively. When any voltage or current is supplied to each of the three subpixels, the display device 10 can display an image.

[0018] The peripheral area 24 includes the IC chip 110 and two control circuits 120. The IC chip 110 is connected to the terminal portion 150 using a connection wiring 341. Each of the two control circuits 120 is connected to the IC chip 110 using a connection wiring 342. The peripheral area 24 is sometimes referred to as a frame area. The connection wiring 341 may be referred to individually as the connection wiring 341, and a bundle of multiple connection wirings 341 may be referred to as the connection wiring 341. Like the connection wiring 341, the connection wiring 342 may be referred to individually as the connection wiring 342, and a bundle of multiple connection wirings 342 may be referred to as the connection wiring 342.

[0019] The terminal area 26 includes a terminal portion 150 and an FPC 200 electrically connected to the terminal portion 150. The terminal area 26 is an area on the opposite side of the peripheral area 24 from the area in which the display area 22 is provided in the first direction D1.

[0020] The FPC 200 is connected to a plurality of terminal units 150. The display device 10 is connected to an external device (not shown) via the FPC 200 and the plurality of terminal units 150. Control signals and voltages are transmitted from the external device to the display device 10 via the FPC 200 and the plurality of terminal units 150. The display device 10 drives each pixel 180 provided on the display device 10 using the control signals and voltages transmitted by the external device. As a result, the display device 10 can display an image in the display area 22.

[0021] The IC chip 110 supplies signals, voltages, etc. for driving each pixel 180 to the two control circuits 120 and each pixel 180 (pixel circuit 181) via the FPC 200, the plurality of terminal parts 150, and the connection wiring 341.

[0022] In this specification and drawings, IC chip 110, each of the two control circuits 120, and each of IC chip 110 may be referred to individually as a control circuit, and a group of circuits including IC chip 110, each of the two control circuits 120, and part or all of IC chip 110 may be referred to as a control circuit.

[0023] <1-2. Configuration of IC chip 110> 1, an overview of the IC chip 110 will be described. The IC chip 110 is provided at a position adjacent to the display area 22 in the first direction D1. Image data signal lines 321, 322, and 323 are electrically connected to the IC chip 110, extend along the first direction D1, and are connected to a plurality of pixels 180 arranged along the first direction D1.

[0024] For example, the IC chip 110 includes a plurality of selection circuits (not shown). For example, each of the plurality of selection circuits is a switch controlled based on an on signal and an off signal supplied to a selection signal line. The selection circuit is selected by an on signal supplied to the selection signal line, and supplies an image data signal SL(m) to the image data signal line 321 and the pixels 180 electrically connected to the image data signal line 321. The selection signal and the image data signal SL(m) are transmitted from an external device to the IC chip 110 via the FPC 200 and the plurality of terminal units 150. For example, the image data signal SL(m) includes a data signal VDATA, and the data signal VDATA includes a data voltage that is equal to or greater than a voltage VSIGL (see FIG. 5) and equal to or less than a voltage VSIGH (see FIG. 5).

[0025] For example, an on signal is a signal including a voltage that turns on a selection circuit (switch), and an off signal is a signal including a voltage that turns off the selection circuit (switch). In the present invention, the on signal may be a high-level voltage (potential) (high, High, HI) and the off signal may be a low-level voltage (potential) (low, Low, LO), or the on signal may be a low-level voltage (potential) (low, Low, LO) and the off signal may be a high-level voltage (potential) (high, High, HI). A high-level voltage is greater (higher) than a low-level voltage. In addition, in a display device according to one embodiment of this specification, as an example, the on signal is a high-level voltage and the off signal is a low-level voltage.

[0026] <1-3. Configuration of Control Circuit 120> An overview of the control circuit 120 will be described with reference to FIG. 1. Two control circuits 120 are provided adjacent to each other on both sides (left and right) of the display area 22 along the second direction D2. Scan signal lines 330, 331, 332, 333, and 334 are electrically connected to the control circuits 120, extend along the second direction D2, and are connected to a plurality of pixels 180 arranged along the second direction D2. As an example, each scan signal line of the display device 10 shown in FIG. 1 is connected to both of the two control circuits 120. Each scan signal line may be connected to one of the control circuits 120. For example, the n-th scan signal line may be electrically connected to the control circuit 120 on the right side of the display area 22 in the second direction D2, and the n+1-th scan signal line may be electrically connected to the control circuit 120 on the left side of the display area 22 in the second direction D2. The number n is a positive integer.

[0027] The control circuit 120 includes a shift register circuit 130 and a scan driver circuit 160. For example, the control circuit 120 is a gate driver, and receives control signals including a clock signal, a start pulse, and a plurality of enable signals, as well as voltages such as a drive voltage VDDEL (see FIG. 2) and a reference voltage VSSEL (see FIG. 2). The control circuit 120 can sequentially select scan lines based on the input of the control signals and power supply.

[0028] The shift register circuit 130 is electrically connected to the scan driver circuit 160. The shift register circuit 130 includes a plurality of shift registers (not shown). The shift register circuit 130 is also supplied with the above-mentioned control signals via a plurality of connection wirings 342, a drive voltage VDDEL via a drive power supply line PVDD (see FIG. 2), and a reference voltage VSSEL via a reference voltage line PVSS (see FIG. 2). The shift register circuit 130 has a role of generating a plurality of output signals (not shown) shifted at different timings based on the above-mentioned control signals, and sequentially outputting the output signals to the scan driver circuit 160.

[0029] The scan driver circuit 160 includes multiple scan drivers. For example, the multiple scan drivers receive multiple output signals from the shift register circuit 130, the multiple enable signals from the IC chip 110 via multiple connection lines 342, the drive voltage VDDEL via a drive power supply line PVDD, and the reference voltage VSSEL via a reference voltage line PVSS. Based on the multiple output signals and the multiple enable signals, the multiple scan drivers sequentially supply scan signals (e.g., a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), and a fifth scan signal SC5(n)) with different timings to each scan signal line, and drive the pixels 180 (pixel circuits 181) electrically connected to each scan signal line. For example, the fifth scan signal SC5(n) and the scan signal line 334 to which the fifth scan signal SC5(n) is supplied are so-called scan signals and scan signal lines.

[0030] <1-4. Configuration of pixel 180> An overview of the pixel 180 and the pixel circuit 181 will be described with reference to FIGS. 1 to 3. FIG. 2 is a schematic diagram showing an input signal to the pixel circuit 181 included in the pixel 180. FIG. 3 is a circuit diagram showing the configuration of the pixel circuit 181. FIGS. 2 and 3 show, as an example, the configuration of the pixel circuit 181 of the pixel 180 shown in FIG. 1. The configurations of the pixel 180 and the pixel circuit 181 are not limited to the configurations shown in FIGS. 1 to 3.

[0031] The pixel circuit 181 is a circuit for driving the pixel 180. The pixel circuits of the subpixels R, G, and B included in the pixel 180 are similar to the pixel circuit 181. The subpixels R, G, and B have light-emitting elements OLED that emit different colors. In the following description, a light-emitting element OLED that emits red light will be described as an example.

[0032] 2, the pixel circuit 181 is supplied with an image data signal SL(m), a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), a fifth scan signal SC5(n), a pre-charge voltage VPRC, a reference voltage VREF, and an initialization voltage VINI. Furthermore, the pixel circuit 181 is supplied with a drive voltage VDDEL and a reference voltage VSSEL as power supplies for driving the pixel 180. For example, the pre-charge voltage VPRC, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the reference voltage VSSEL may be constant voltages or variable voltages that vary according to the timing of each signal.

[0033] The precharge voltage VPRC is supplied to the precharge voltage power line SVP, the reference voltage VREF is supplied to the reference voltage power line SVR, the initialization voltage VINI is supplied to the initialization voltage power line SVI, the drive voltage VDDEL is supplied to the drive power line PVDD, and the standard voltage VSSEL is supplied to the reference voltage line PVSS. For example, the precharge voltage VPRC, the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the standard voltage line PVSS are each electrically connected to a different connection wiring 342. Also, for example, the precharge voltage VPRC, the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the standard voltage line PVSS may each be a different connection wiring 342. For example, the precharge voltage VPRC is an intermediate voltage (potential) between the voltage VSIGL and the voltage VSIGH.

[0034] For example, the precharge voltage VPRC, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the reference voltage VSSEL are supplied from an external device to the IC chip 110 via the FPC 200, the terminal unit 150, and the connection wiring 341. Also, for example, the precharge voltage VPRC, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the reference voltage VSSEL are supplied from the IC chip 110 to the plurality of pixels 180 (pixel circuits 181) via the connection wiring 342, the precharge voltage power supply line SVP, the reference voltage power supply line SVR, the initialization voltage power supply line SVI, the drive power supply line PVDD, and the reference voltage line PVSS. Although not shown, the precharge voltage VPRC, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the standard voltage VSSEL may be connected to the precharge voltage power line SVP, the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the standard voltage line PVSS from an external device via the FPC 200, the terminal unit 150, and the connection wiring 341, without passing through the IC chip 110 and the connection wiring 342, and may be supplied to a plurality of pixels 180 (pixel circuits 181). For example, the precharge voltage VPRC, the reference voltage VREF, the initialization voltage VINI, and the standard voltage VSSEL are smaller than the drive voltage VDDEL.

[0035] 3, the pixel circuit 181 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a capacitance element CS, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (a source electrode and a drain electrode) consisting of a first electrode and a second electrode. Each of the capacitance element CS and the light-emitting element OLED includes a pair of electrodes consisting of a first electrode and a second electrode.

[0036] For example, the first transistor T1 is a selection transistor. The first transistor T1 has a function of supplying an image data signal SL(m) to the first node N1.

[0037] For example, the second transistor T2 is a drive transistor. The gate voltage applied to the gate electrode 622 of the second transistor T2 is a voltage in which variations in the threshold voltage VTH are corrected based on at least the reference voltage VREF and the initialization voltage VINI. Furthermore, the second transistor T2 controls the amount of current flowing from the drive power line PVDD to the light-emitting element OLED based on the gate voltage in which the threshold voltage VTH is corrected and the input image data signal SL(m). That is, the second transistor T2 has the function of flowing a current corresponding to the display gradation (brightness) from the drive voltage VDDEL to the light-emitting element OLED, causing the light-emitting element OLED to emit light. The gate voltage is a potential difference Vgs between the voltage supplied to the gate electrode 622 and the voltage supplied to the first electrode (source) 624. The potential difference Vgs is also a potential difference between the voltage supplied to the second node N2 and the voltage supplied to the third node N3.

[0038] The third transistor T3 has a function of connecting the first node N1 and the second node N2 to each other and supplying the image data signal SL(m) (data signal VDATA) to the second node N2.

[0039] The fourth transistor T4 has a function of connecting the second node N2 and the reference voltage power supply line SVR to each other, supplying the reference voltage VREF to the second node N2, and initializing the second node N2.

[0040] The fifth transistor T5 has a function of connecting the third node N3 and the initialization voltage power supply line SVI to each other, supplying the initialization voltage VINI to the third node N3, and initializing the third node N3.

[0041] The sixth transistor T6 has a function of connecting the first node N1 and the precharge voltage power supply line SVP to each other, supplying the precharge voltage VPRC to the first node N1, and supplying an intermediate potential to the first node N1.

[0042] The capacitance element CS has a function of holding a charge equivalent to the threshold voltage VTH of the second transistor T2, and a function of holding a charge equivalent to the data voltage (a voltage equal to or greater than the voltage VSIGL (see Figure 9) and equal to or less than the voltage VSIGH (see Figure 9)) included in the image data signal SL(m) supplied to the first node N1.

[0043] The light-emitting element OLED has diode characteristics and emits light based on the current flowing through the light-emitting element OLED, which is the drain current (current Ion) of the second transistor T2.

[0044] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the scan signal line 334. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the first node N1, the first electrode 634 of the third transistor T3, the second electrode 666 of the sixth transistor T6, and the second electrode 694 of the capacitor CS. As described above, the fifth scan signal SC4(n) is supplied to the scan signal line 334. The switching of the first transistor T1 is controlled using the fifth scan signal SC5(n). In other words, the conductive state (on state) and non-conductive state (off state) of the first transistor T1 are controlled by the fifth scan signal SC5(n). When the signal supplied to the fifth scan signal SC5(n) is LO, the first transistor T1 is in a non-conductive state. When the signal supplied to the fifth scan signal SC5(n) is HI, the first transistor T1 is in a conductive state.

[0045] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to the second node N2, the second electrode 636 of the third transistor T3, and the second electrode 646 of the fourth transistor T4. The first electrode 624 is electrically connected to the third node N3, the second electrode 656 of the fifth transistor T5, the first electrode 692 of the capacitor CS, and the second electrode 684 of the light-emitting element OLED. The second electrode 626 is electrically connected to the driving power line PVDD. The threshold voltage of the second transistor T2 is a threshold voltage VTH. The second transistor T2 controls the amount of current flowing through the light-emitting element OLED in accordance with the potential difference Vgs, the potential difference Vds between the voltage supplied to the second electrode 626 and the voltage supplied to the first electrode 624 (third node N3), and the threshold voltage VTH. For example, when the potential difference Vgs is smaller than the threshold voltage VTH and the potential difference Vds is equal to or smaller than 0 V, the second transistor T2 is in a non-conductive state, no current flows to the light-emitting element OLED, and black display is produced. For example, when the potential difference Vgs is equal to or larger than the threshold voltage VTH and the potential difference Vds is larger than 0 V, the second transistor T2 is in a conductive state, causes a current Ion to flow, and causes the light-emitting element OLED to emit light with a brightness corresponding to the amount of current.

[0046] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The switching of the third transistor T3 is controlled using a first scan signal SC1(n). The third transistor T3 is controlled between a conductive state (ON state) and a non-conductive state (OFF state) by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the third transistor T3 is in a non-conductive state. When the signal supplied to the first scan signal SC1(n) is HI, the third transistor T3 is in a conductive state.

[0047] The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the scan signal line 331. A second scan signal SC2(n) is supplied to the scan signal line 331. The first electrode 644 is electrically connected to the reference voltage power supply line SVR. The switching of the fourth transistor T4 is controlled using the second scan signal SC2(n). In other words, the conductive state (on state) and non-conductive state (off state) of the fourth transistor T4 are controlled by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is LO, the fourth transistor T4 is in a non-conductive state. When the signal supplied to the second scan signal SC2(n) is HI, the fourth transistor T4 is in a conductive state.

[0048] The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the scan signal line 332. A third scan signal SC3(n) is supplied to the scan signal line 332. The first electrode 654 is electrically connected to the initialization voltage power supply line SVI. The switching of the fifth transistor T5 is controlled using the third scan signal SC3(n). In other words, the fifth transistor T5 is controlled between a conductive state (ON state) and a non-conductive state (OFF state) by the third scan signal SC3(n). When the signal supplied to the third scan signal SC3(n) is LO, the fifth transistor T5 is in a non-conductive state. When the signal supplied to the third scan signal SC3(n) is HI, the fifth transistor T5 is in a conductive state.

[0049] The sixth transistor T6 includes a gate electrode 662, a first electrode 664, and a second electrode 666. The gate electrode 662 is electrically connected to the scan signal line 333. A fourth scan signal SC4(n) is supplied to the scan signal line 333. The first electrode 664 is electrically connected to the precharge voltage power supply line SVP. The sixth transistor T6 has its switching controlled by the fourth scan signal SC4(n). In other words, the sixth transistor T6 is controlled between a conductive state (ON state) and a non-conductive state (OFF state) by the fourth scan signal SC4(n). When the signal supplied to the fourth scan signal SC4(n) is LO, the sixth transistor T6 is in a non-conductive state. When the signal supplied to the fourth scan signal SC4(n) is HI, the sixth transistor T6 is in a conductive state.

[0050] The first electrode 682 of the light-emitting element OLED is electrically connected to the reference voltage line PVSS. As described above, the reference voltage VSSEL is supplied to the reference voltage line PVSS. The first electrode 682 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 684 of the light-emitting element OLED is, for example, an anode electrode.

[0051] For example, the conductive state of a transistor in the display device 10 means that the source electrode and drain electrode of the transistor are conductive and the transistor is in an on (ON) state, and the non-conductive state of a transistor in the display device 10 means that the source electrode and drain electrode of the transistor are non-conductive and the transistor is in an off (OFF) state. Note that in each transistor, the source electrode and drain electrode may be interchanged depending on the voltage or potential supplied to each electrode. Furthermore, it is easily understood by those skilled in the art that even when a transistor is in an off state, a small amount of current, such as leakage current, still flows.

[0052] Each transistor shown in FIG. 3 may have a group 14 element such as silicon or germanium in its channel region, or an oxide exhibiting semiconducting properties. For example, a metal oxide exhibiting semiconducting properties can be used as the oxide exhibiting semiconducting properties. As an example, the metal oxide exhibiting semiconducting properties is an oxide semiconductor containing two or more metals including indium (In). Furthermore, the metal oxide exhibiting semiconducting properties may be gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), or a lanthanide in addition to indium. Furthermore, the metal oxide exhibiting semiconducting properties may be amorphous, crystalline, or a mixed phase of amorphous and crystalline. When the display device 10 includes both a transistor having a group 14 element in its channel region and a transistor having an oxide exhibiting semiconducting properties in its channel region, the manufacturing method of the display device 10 includes forming a semiconductor layer containing a group 14 element and forming a semiconductor layer (e.g., an oxide semiconductor layer) containing an oxide exhibiting semiconducting properties.

[0053] For example, the leakage current of a transistor having a metal oxide with semiconducting properties is extremely small. Therefore, a charge corresponding to a voltage (potential) written to a capacitor using a transistor having a metal oxide with semiconducting properties is unlikely to escape from the capacitor. As a result, using a transistor having a metal oxide with semiconducting properties enables the charge written to the capacitor to be retained for a long period of time. Furthermore, under the same conditions of gate-source voltage (potential difference between the gate electrode and the source electrode (Vgs)) and source-drain voltage (e.g., potential difference between the source electrode and the drain electrode (Vds)), the drain current of a transistor having a metal oxide with semiconducting properties may be larger than the drain current of a transistor having low-temperature polysilicon (LTPS). As a result, under the same conditions of drain current, the gate-source voltage and source-drain voltage of a transistor having a metal oxide with semiconducting properties can be smaller than those of a transistor having LTPS. Therefore, using a transistor having a metal oxide with semiconducting properties can reduce the power consumption of the display device 10.

[0054] For example, the channel region of the first transistor T1 or the channel region of the fourth transistor T4 may be formed using a metal oxide having semiconducting properties. Also, the channel region of the second transistor T2 or the channel region of the fifth transistor T5 may be formed using a metal oxide having semiconducting properties. For example, when the channel region of the first transistor T1 is formed using a metal oxide, the charge corresponding to the voltage included in the data signal VDATA held in the first node N1 and the second electrode 694 of the capacitor CS is less likely to be discharged, and the first node N1 and the second electrode 694 of the capacitor CS can hold the charge for a long time.

[0055] For example, the channel region of each transistor may have crystalline silicon. For example, the crystalline silicon may be low-temperature polysilicon (LTPS) or single-crystal silicon. For example, each transistor in the display device 10 is formed using a thin-film transistor (TFT). The channel region of each transistor may also be formed using single-crystal silicon such as a silicon wafer or SOI substrate. The transistor configuration, storage capacitor connection, power supply voltage, etc. of the display device 10 may be appropriately adapted depending on the application and specifications.

[0056] In the first embodiment, the first transistor T1 to the sixth transistor T6 are n-channel field effect transistors, and the channel region of each of the first transistor T1 to the sixth transistor T6 is formed using a metal oxide having semiconductor properties.

[0057] <1-5. Driving method of the display device 10> A method for driving the display device 10 will be described with reference to Figs. 4 to 8. Figs. 4 to 8 are schematic diagrams showing timing charts of the display device 10. The driving methods shown in Figs. 4 to 8 are examples, and the driving methods of the display device 10 are not limited to the driving methods shown in Figs. 4 to 8. Configurations that are the same as or similar to those in Figs. 1 to 3 will be described as necessary. The horizontal axis of the timing chart represents time.

[0058] For example, the display device 10 is driven at a frequency of 60 Hz, and one frame (1 FRAME) is driven at 60 Hz. Fig. 4 shows the current frame (Kth FRAME), a portion of the frame immediately before the current frame (K-1st FRAME), and a portion of the frame immediately after the current frame (K+1st FRAME). Figs. 5 to 8 show the light-emitting period PEM of the frame immediately before the current frame (K-1st FRAME), and the periods PIP, PWR, and PVH of the current frame (Kth FRAME). Figs. 5 to 8 also show one horizontal period (horizontal period HRP) for one pixel 180 (pixel circuit 181).

[0059] First, an overview of a method for driving the display device 10 will be described with reference to Fig. 4. As shown in Fig. 4, the method for driving the display device 10 includes, in one frame, at least an initialization and precharge period PIP (period PIP), a write period PWR (period PWR), a threshold acquisition and retention period PVH (period PVH), and an emission period PEM. In a pixel 180 (pixel circuit 181) included in the display device 10, the period PWR and period PVH are executed after the period PIP. Furthermore, after the emission period PEM of the frame immediately before the current frame, the period PIP, period PWR, and period PVH of the current frame are executed, and after the emission period PEM of the current frame, the period PIP, period PWR, and period PVH of the frame immediately after the current frame are executed.

[0060] The period PIP is a period during which a precharge voltage is supplied to the first node N1 and the second node N2 and the third node N3 are initialized. The period PWR is a period during which a data signal VDATA is written to the pixel 180 (pixel circuit 181). The period PVH is a period during which the threshold voltage of the second transistor T2 is acquired by adjusting the potential difference Vgs to be equal to the threshold voltage VTH, and a charge corresponding to the threshold voltage is held at the third node N3 (the first electrode 692 of the capacitive element CS). Furthermore, the light-emitting period PEM is a period during which the pixel 180 emits light based on the written (supplied) data signal VDATA and the acquired threshold voltage of the second transistor T2 (threshold voltage correction). In FIG. 4, for convenience of explanation, the period PWR overlaps with the period PVH. However, the actual period PVH starts after the period PWR starts and ends after the period PWR ends. That is, a portion of the period PWR overlaps with the period PVH.

[0061] Next, the horizontal period HRP in the method of driving the pixel 180 (pixel circuit 181) of the display device 10 will be described with reference to FIGS.

[0062] In the driving method of the display device 10, the horizontal period HRP includes a period PWR and a period PVH. During the horizontal period HRP, a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), a fifth scan signal SC5(n), an image data signal SL(m), an initialization voltage VINI, a reference voltage VREF, and a precharge voltage VPRC are input to the pixel 180 (pixel circuit 181). For example, the pixel 180 (pixel circuit 181) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the fifth scan signal SC5(n). The image data signal SL(m), the initialization voltage VINI, the reference voltage VREF, and the precharge voltage VPRC are input to the selected pixel 180 (pixel circuit 181) according to the timing of each signal. A similar operation is performed for all pixels 180 (pixel circuits 181), and based on the image data signals SL(m) input to all pixels 180 (pixel circuits 181), the image of the frame corresponding to one frame is displayed in the display area 22 of the display device 10.

[0063] For example, Table 1 shows the voltages (potentials) supplied to each signal in each period of each frame in the timing charts shown in FIGS.

[0064] [Table 1]

[0065] <1-5-1. First Example of Driving Method of Display Device 10> A first example of a method for driving the display device 10 will be described with reference to Fig. 5. The driving method shown in the first example involves the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH in the frame (K-1stFRAME) immediately before the current frame (KthFRAME), and then the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGL in the KthFRAME. In other words, the driving method shown in the first example involves displaying images of different colors in successive frames.

[0066] A data signal VDATA is input to each pixel 180 (pixel circuit 181) in accordance with each period (period PIN, horizontal period HRP (period PWR and period PVH)). The data signal VDATA is analog data (video signal) including a voltage greater than or equal to voltage VSIGL and less than or equal to voltage VSIGH. In FIG. 5, only the data signal VDATA (video signal voltage greater than or equal to voltage VSIGL and less than or equal to voltage VSIGH) written in the horizontal period HRP is shown in the image data signal SL(m). For the data signal VDATA in periods other than the horizontal period HRP, a video signal voltage greater than or equal to voltage VSIGL and less than or equal to voltage VSIGH is continuously supplied to the image data signal SL(m) based on the data signal VDATA written to the pixel circuit 181 of the corresponding row, but this is omitted in FIG. 5 and indicated by horizontal lines. As shown in Table 1, for example, the voltage VSIGL is −0.5V, and the pixel 180 to which the voltage VSIGL is supplied does not emit light and is black. Furthermore, for example, the voltage VSIGH is 3.5 V, and the pixel 180 to which the voltage VSIGH is supplied emits each color. Furthermore, for example, as shown in Table 1 or Figures 5 to 8, the voltage VH (HI) is 10 V, the voltage VL (LO) is -4 V, the initialization voltage VINI is -2 V, the reference voltage VREF is 0 V, the precharge voltage VPRC is 1.5 V, the drive voltage VDDEL is 8 V, the reference voltage VSSEL is 0 V, the voltage VM is 5 V, and the voltage VN is -5 V.

[0067] The light emission period PEM of the K-1st FRAME is a period during which the pixel 180 (pixel circuit 181) emits light based on the potential difference Vgs (the voltage (voltage V(N2)) supplied to the second node N2 minus the voltage (voltage V(N3)) supplied to the third node N3). For example, the pixel 180 (pixel circuit 181) emits red light, and three pixels, a pixel 180 that emits red light, a pixel 180 that emits blue light, and a pixel 180 that emits green light, emit white light.

[0068] For example, during the light emission period PEM of the (K-1st) frame, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180 (pixel circuit 181), the first scan signal SC1(n) is supplied with HI, and the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the fifth scan signal SC5(n) are supplied with LO. The third transistor T3 is in an ON state, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are in an OFF state. Furthermore, for example, the voltage Vna supplied to the first node N1 and the second node N2 is 7 V, the voltage Vnb supplied to the third node N3 is 2.5 V, and the potential difference Vgs is 4.5 V. Therefore, the second transistor T2 can pass a current Ion based on the potential difference Vgs and the potential difference Vds according to the voltage VSIGH input during the horizontal period HRP of the (K-1st) frame. Also, the current Ion flows from the driving power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, causing the light-emitting element OLED to emit light.

[0069] During the period between the light-emitting period PEM of the (K-1st) FRAME and the period PIP, the image data signal SL(m) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180 (pixel circuit 181). The second scan signal SC2(n) changes from a state in which LO is supplied to a state in which HI is supplied. When the second scan signal SC2(n) changes to a state in which HI is supplied, the first scan signal SC1(n) changes from a state in which HI is supplied to a state in which LO is supplied, and the third scan signal SC3(n) changes from a state in which LO is supplied to a state in which HI is supplied. The fourth scan signal SC4(n) and the fifth scan signal SC5(n) are in a state in which LO is supplied.

[0070] Therefore, the fourth transistor T4 and the fifth transistor T5 change from an off state to an on state, the third transistor T3 changes from an on state to an off state, and the first transistor T1 and the sixth transistor T6 maintain the off state.

[0071] As a result, the voltage supplied to the first node N1 remains at voltage Vna, and the voltage supplied to the second node N2 gradually drops from voltage Vna toward 0 V (reference voltage VREF). Also, the voltage supplied to the third node N3 gradually drops from voltage Vnb toward voltage Vnc (initialization voltage VINI, −2 V). Because the second transistor T2 and the fifth transistor T5 are on and a current flows from the driving power line PVDD to the initial voltage power line SVI, the light-emitting element OLED does not emit light.

[0072] During the period PIP following the period between the light emission period PEM and the period PIP of the (K-1st) FRAME, for example, the image data signal SL(m) maintains a state in which the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180 (pixel circuit 181) is supplied, the second scan signal SC2(n) and the third scan signal SC3(n) maintain a state in which HI is supplied, the first scan signal SC1(n) and the fifth scan signal SC5(n) maintain a state in which LO is supplied, and the fourth scan signal SC4(n) changes from a state in which LO is supplied to a state in which HI is supplied.

[0073] Therefore, the sixth transistor T6 changes from an off state to an on state, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 remain on, and the first transistor T1 and the third transistor T5 remain off.

[0074] As a result, the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage Vnd (pre-charge voltage VPRC, 1.5V) and reaches voltage Vnd. The voltage supplied to the second node N2 gradually drops from voltage Vna toward 0V (reference voltage VREF) and reaches 0V. The voltage supplied to the third node N3 gradually drops from voltage Vnb toward voltage Vnc (initialization voltage VINI, -2V) and reaches voltage Vnc. The potential difference Vgs becomes 2V (0V - -2V), and the potential difference Vds becomes 10V (8V - -2V). As in the period between the light-emitting period PEM and period PIP of the K-1st FRAME, the second transistor T2 and the fifth transistor T5 are in the on state, and a current Ion flows from the drive power supply line PVDD to the initialization voltage power supply line SVI, so the light-emitting element OLED does not emit light.

[0075] As described above, during the period PIP, the first node N1 is supplied with a precharge voltage (intermediate potential), the second node N2 is initialized by the reference voltage VREF (0 V), and the third node N3 is initialized by the initialization voltage VINI (-2 V). Note that, for example, after the period PIP, the initialization of the third node N3 continues until the third scan signal SC3(n) changes from a state in which HI is supplied to it to a state in which LO is supplied.

[0076] During the initial period of the horizontal period HRP of KthFRAME following the period PIP, the image data signal SL(m) is supplied with the data signal VDATA of the voltage VSIGL input to the selected pixel 180 (pixel circuit 181), the second scan signal SC2(n) and the third scan signal SC3(n) maintain a HI state, the first scan signal SC1(n) and the fifth scan signal SC5(n) maintain a LO state, and the fourth scan signal SC4(n) changes from a HI state to a LO state.

[0077] Therefore, the sixth transistor T6 changes from the on state to the off state, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 remain on, and the first transistor T1 and the third transistor T5 remain off.

[0078] As a result, the voltage supplied to the first node N1 is maintained at voltage Vnd, the voltage supplied to the second node N2 is maintained at 0 V, and the voltage supplied to the third node N3 is maintained at voltage Vnc. Also, similar to the period PIP, the light-emitting element OLED does not emit light.

[0079] During the period PWR following the beginning of the horizontal period HRP, the image data signal SL(m) maintains a state in which the data signal VDATA of the voltage VSIGL is supplied, the second scan signal SC2(n) and the third scan signal SC3(n) maintain a state in which HI is supplied, the first scan signal SC1(n) and the fourth scan signal SC4(n) maintain a state in which LO is supplied, and the fifth scan signal SC5(n) changes from a state in which LO is supplied to a state in which HI is supplied.

[0080] Therefore, the first transistor T1 changes from an off state to an on state, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 maintain their on states, and the third transistor T2 and the sixth transistor T6 maintain their off states.

[0081] As a result, the voltage supplied to the first node N1 gradually drops from voltage Vnd toward voltage Vnf (voltage VSIGL, −0.5 V), the voltage supplied to the second node N2 maintains 0 V, and the voltage supplied to the third node N3 maintains voltage Vnc. Also, similar to the period PIP, the light-emitting element OLED does not emit light.

[0082] During the period PWR, in the period PVH that is parallel to (overlaps with) the period PWR, the image data signal SL(m) maintains a state in which the data signal VDATA of the voltage VSIGL is supplied, the second scan signal SC2(n) and the fifth scan signal SC5(n) maintain a state in which HI is supplied, the first scan signal SC1(n) and the fourth scan signal SC4(n) maintain a state in which LO is supplied, and the third scan signal SC3(n) changes from a state in which HI is supplied to a state in which LO is supplied.

[0083] Therefore, the fifth transistor T5 changes from an on state to an off state, the first transistor T1 and the fourth transistor T4 maintain the on state, and the third transistor T1 and the sixth transistor T6 maintain the off state.

[0084] The voltage supplied to the first node N1 continues to gradually drop toward the voltage Vnf and reaches the voltage Vnf, while the voltage supplied to the second node N2 remains at 0V.

[0085] Immediately after the start of the period PVH, the potential difference Vgs is 2V (0V - voltage Vnc (-2V)), and the potential difference Vds is 10V. Because the potential differences Vgs and Vds are larger than the threshold voltage VTH, the second transistor T2 is in the ON state. Therefore, a current Ion flows from the second electrode 626 to the first electrode 624 of the second transistor T2. Because the fifth transistor T5 is in the OFF state and the node N3 is released, and the second transistor T2 is in the ON state, the current Ion flows from the driving power line PVDD (the second electrode 626 side) to the third node N3 (the first electrode 624 side), and the voltage supplied to the third node N3 gradually rises from the voltage Vnc.

[0086] When the potential difference Vgs becomes the threshold voltage VTH, the second transistor T2 changes from the ON state to the OFF state, and the current Ion stops flowing. At this time, the voltage supplied to the third node N3 increases from the voltage Vnc (-2 V) to the voltage Vne (-1 V), the potential difference Vgs is 1 V (0 V - voltage Vne (-1 V)), the potential difference Vds is 9 V, and the potential difference Vgs is equal to the threshold voltage VTH (1 V). That is, during the period PVH, the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, thereby acquiring the threshold voltage VTH of the second transistor T2, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitor CS). Furthermore, the second transistor T2 is in the OFF state, and the current Ion does not flow from the driving power supply line PVDD to the reference voltage line PVSS, so that the light-emitting element OLED does not emit light.

[0087] At the end of the period PVH, the image data signal SL(m) maintains a state in which the data signal VDATA of the voltage VSIGL is supplied, and the third scan signal SC3(n) and the fourth scan signal SC4(n) maintain a state in which LO is supplied. The fifth scan signal SC5(n) changes from a state in which HI is supplied to a state in which LO is supplied. When the fifth scan signal SC5(n) changes to a state in which LO is supplied, the second scan signal SC2(n) changes from a state in which HI is supplied to a state in which LO is supplied. When the second scan signal SC2(n) changes to a state in which LO is supplied, the first scan signal SC1(n) changes from a state in which LO is supplied to a state in which HI is supplied.

[0088] Therefore, the third transistor changes from an off state to an on state, the first transistor T1 and the fourth transistor change from an on state to an off state, and the second transistor T2, the fifth transistor T5 and the sixth transistor T6 remain in the off state.

[0089] As a result, the first node N1 becomes conductive with the second node N2, the voltage supplied to the second node N2 gradually drops toward voltage Vnf and reaches voltage Vnf, the voltage supplied to the first node N1 maintains voltage Vnf, and the voltage supplied to the third node N3 maintains voltage Vne. Note that the potential difference Vgs is voltage Vnf (-0.5V) - voltage Vne (-1V), which is smaller than the threshold voltage VTH, so no current Ion flows from the driving power line PVDD to the reference voltage line PVSS. Therefore, the light-emitting element OLED does not emit light.

[0090] In this way, during the period PWR, the data signal VDATA is written to the pixel 180 (pixel circuit 181). During the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0091] The light emission period PEM of the KthFRAME following the horizontal period HRP of the KthFRAME is a period during which the pixel 180 emits light based on the voltage VSIGL supplied to the first node N1 and the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3.

[0092] For example, during the light emission period PEM of the Kth FRAME, the image data signal SL(m) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180 (pixel circuit 181). Also, the first scan signal SC1(n) maintains a state in which HI is supplied, and the second scan signal SC2(n) to the fifth scan signal SC5(n) maintain a state in which LO is supplied.

[0093] Therefore, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 remain in an off state, and the third transistor T3 remains in an on state. Because the second transistor T2 is in an off state and no current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS, the light-emitting element OLED does not emit light. As a result, for example, the pixel 180 (pixel circuit 181) that emits red light turns black. Similarly to the pixel 180 that emits red light, the pixel 180 that emits blue light and the pixel 180 that emits green light also do not emit light, so the three pixels that use the pixel 180 that emits red light, the pixel 180 that emits blue light, and the pixel 180 that emits green light turn black.

[0094] The display device 10 includes a sixth transistor T6 for supplying a precharge voltage VPRC (an intermediate potential) to the first node N1, and a first transistor T1 for supplying a data signal VDATA to the first node N1. A driving method for the display device 10 includes supplying the precharge voltage VPRC to the first node N1 by the sixth transistor T6, and supplying the data signal VDATA to the first node N1 by the first transistor T1 after supplying the precharge voltage VPRC to the first node N1. That is, the display device 10 can supply the intermediate potential to the first node N1, and then supply the data signal VDATA to the first node N1.

[0095] As explained above in "1-5-1. First Example of the Method for Driving the Display Device 10," when a white image is displayed based on the voltage VSIGH in the K-1st FRAME and then a black image is displayed based on the voltage VSIGL in the Kth FRAME, the first node N1 is supplied with the voltage VSIGH (3.5 V), then with the intermediate potential (1.5 V), and then with the voltage VSIGL (-0.5 V). That is, when writing a data voltage, the fluctuation in the potential of the first node N1 is 2 V (1.5 V - (-0.5 V)).

[0096] On the other hand, for example, in a display device including a configuration that supplies the data signal VDATA without supplying an intermediate potential to the first node N1, when displaying a white image based on the voltage VSIGH in the K-1st FRAME and then displaying a black image based on the voltage VSIGL in the Kth FRAME, the display device first supplies the voltage VSIGH (3.5 V) to the pixel (pixel circuit) and then supplies the voltage VSIGL (-0.5 V). As a result, in a display device including a configuration that supplies the data signal VDATA without supplying the intermediate potential to the first node N1, the fluctuation in the potential in the pixel (pixel circuit) is 4 V (3.5 V - (-0.5 V)), which is larger than that of the display device 10.

[0097] Therefore, the fluctuation in the potential of the first node N1 in the display device 10 is smaller than the fluctuation in the potential of the first node N1 in a display device that supplies a data voltage without supplying an intermediate potential to the first node N1.

[0098] A reduction in the fluctuation in the potential of the first node N1 is equivalent to a reduction in the fluctuation in the potential of the image data signal line 321 to which the data signal VDATA is supplied. If the fluctuation in the potential of the image data signal line 321 is large, the unwanted electromagnetic interference (EMI) caused by the fluctuation in the potential of the image data signal line 321 increases. The display device 10 can reduce the fluctuation in the potential of the image data signal line 321, and therefore can reduce the unwanted electromagnetic interference (EMI) caused by the fluctuation in the potential of the image data signal line 321.

[0099] Furthermore, because the display device 10 can reduce fluctuations in the potential of the first node N1, the time required to write data to the first node N1 in the display device 10 (write speed) can be made shorter than that of a display device that supplies the data signal VDATA without supplying an intermediate potential to the first node N1. In other words, the write speed of the display device 10 can be made faster than that of a display device that supplies the data signal VDATA without supplying an intermediate potential to the first node N1.

[0100] Furthermore, the display device 10 can increase the speed at which data is written to the first node N1, thereby shortening the time required for the horizontal period HRP. As a result, for example, the display device 10 can increase the number of pixels that can be written in a shortened time. Therefore, the display device 10 can provide a high-resolution display device and a large-screen display device.

[0101] Furthermore, the driving method of the display device 10 includes a configuration in which the period PVH starts after the period PWR starts and ends after the period PWR ends. That is, a portion of the period PWR overlaps with the period PVH, and the period PVH is offset from the period PWR. On the other hand, for example, in a driving method in which the offset between the periods PWR and PVH is small, when the second transistor T2 is turned on, the voltage supplied to the third node N3 becomes an unintended voltage due to the influence of potential fluctuations in the data voltage (first node N1). This necessitates setting the initialization voltage VINI (Vnc) deeper (to a lower potential), leading to increased power consumption. As described above, the driving method of the display device 10 includes a configuration in which the period PVH is offset from the period PWR, thereby shortening the write time and suppressing an increase in power consumption.

[0102] <1-5-2. Second Example of the Method for Driving the Display Device 10> A second example of a method for driving the display device 10 will be described with reference to FIG. 6. The driving method shown in the second example of the method for driving the display device 10 involves the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH of the data signal VDATA in the frame (K-1st FRAME) immediately before the current frame (Kth FRAME), and then the pixel 180 (pixel circuit 181) also displaying a white image based on the voltage VSIGH of the data signal VDATA in the Kth FRAME. In other words, the driving method shown in the second example involves displaying images of the same color (white) in consecutive frames. Configurations that are the same as or similar to those in FIGS. 1 to 5 will be described as necessary.

[0103] The configuration of the first scan signal SC1(n) to the fifth scan signal SC5(n) is the same as the configuration described in "1-5-1. First Example of the Method for Driving the Display Device 10." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during periods other than the horizontal period HRP of the KthFRAME and the light emission period PEM of the KthFRAME are the same as the configuration described in "1-5-1. First Example of the Method for Driving the Display Device 10." Furthermore, the operation of each transistor during each period is the same as the configuration described in "1-5-1. First Example of the Method for Driving the Display Device 10." Therefore, configurations similar to those described in "1-5-1. First Example of the Method for Driving the Display Device 10" will be explained as necessary. In addition, the image data signal SL(m) is supplied with a data signal VDATA of VSIGH corresponding to white during the horizontal period HRP, and is supplied with a data signal VDATA similar to the configuration described in "1-5-1. First example of the method for driving the display device 10" during periods other than the horizontal period HRP.

[0104] The second example driving method of display device 10 during the light emitting period PEM of K-1stFRAME, the period between the light emitting period PEM of K-1stFRAME following the light emitting period PEM of K-1stFRAME and the period PIP of KthFRAME, the period PIP of KthFRAME, and the initial period of the horizontal period HRP of KthFRAME following the period PIP of KthFRAME is the same as the driving method described in "1-5-1. First example of driving method of display device 10".

[0105] During the period PWR following the initial period of the horizontal period HRP in the second example of the method for driving the display device 10, the configuration of each control signal, the operation of each transistor, etc. are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." The voltage supplied to the first node N1 gradually rises from voltage Vnd toward voltage Vng (voltage VSIGH, 3.5V), the voltage supplied to the second node N2 maintains 0V (reference voltage VREF), and the voltage supplied to the third node N3 maintains voltage Vnc (initialization voltage VINI, -2V). Also, as in the period PIP, the light-emitting element OLED does not emit light.

[0106] In the period PVH that is parallel to (overlaps with) the period PWR midway through the period PWR in the second example of the method for driving the display device 10, the configuration of each control signal, the operation of each transistor, etc. are the same as those described in "1-5-1. First example of the method for driving the display device 10." The voltage supplied to the first node N1 gradually increases toward voltage Vng and becomes voltage Vng, and the voltage supplied to the second node N2 remains at 0V.

[0107] Also, immediately after the start of the period PVH in the second example of the driving method of the display device 10, the potential difference Vgs is 2 V, the potential difference Vds is 10 V, and the potential difference Vgs and the potential difference Vds are greater than the threshold voltage VTH, so the second transistor T2 is in the ON state. Therefore, a current Ion flows from the second electrode 626 of the second transistor T2 to the first electrode 624. Although the fifth transistor T5 is in the OFF state, the second transistor T2 is in the ON state, so the current Ion flows from the driving power line PVDD (the second electrode 626 side) to the third node N3 (the first electrode 624 side), and the voltage supplied to the third node N3 gradually rises from the voltage Vnc.

[0108] When the potential difference Vgs becomes the threshold voltage VTH, the second transistor T2 changes from the ON state to the OFF state, and the current Ion stops flowing. At this time, the voltage supplied to the third node N3 increases from the voltage Vnc to the voltage Vne (-1 V), and the potential difference Vgs (0 V - (-1 V)) is equal to the threshold voltage VTH (1 V). That is, during the period PVH, the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, thereby acquiring the threshold voltage VTH of the second transistor T2, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitor CS). Furthermore, the second transistor T2 is in the OFF state, and no current flows from the drive power supply line PVDD to the reference voltage line PVSS, so that the light-emitting element OLED does not emit light.

[0109] During the final period of the period PVH in the second example of the driving method for the display device 10, the configuration of each control signal, the operation of each transistor, and the like are the same as those described in "1-5-1. First Example of the Driving Method for the Display Device 10." The first node N1 becomes conductive with the second node N2, and the voltage supplied to the second node N2 gradually increases. As a result, the second transistor T2 becomes conductive, and a current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS. Therefore, the voltage supplied to the first node N1 and the voltage supplied to the third node N3 increase in accordance with the increase in the voltage supplied to the second node N2. Due to the increase in the voltage supplied to the third node N3, the voltage supplied to the first node N1 and the voltage supplied to the second node N2 further increase.

[0110] Furthermore, for example, in the light emission period PEM of the Kth FRAME following the horizontal period HRP of the Kth FRAME in the second example of the driving method of the display device 10, the voltage supplied to the first node N1 and the voltage supplied to the second node N2 rise to voltage Vna, and the voltage supplied to the third node N3 rises to voltage Vnb. As a result, the potential difference Vgs becomes 4.5 V (voltage Vna (7 V) - voltage Vnb (2.5 V)). The potential difference Vgs is greater than the threshold voltage VTH, the second transistor T2 is on, a current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS, and the light emitting element OLED emits light. For example, the pixel 180 (pixel circuit 181) emits red light, and three pixels, one for emitting red light, one for emitting blue light, and one for emitting green light, emit white light.

[0111] As described above, during the period PWR in the second example of the method for driving the display device 10, the data signal VDATA is written to the pixel 180 (pixel circuit 181). During the period PVH in the second example of the method for driving the display device 10, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitive element CS). During the light emission period PEM of the KthFRAME in the second example of the method for driving the display device 10, three pixels emit white light.

[0112] <1-5-3. Third Example of the Method for Driving the Display Device 10> A third example of a method for driving the display device 10 will be described with reference to FIG. 7. The driving method shown in the third example of the method for driving the display device 10 involves the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGL of the data signal VDATA in the frame (K-1st FRAME) immediately before the current frame (Kth FRAME), and then the pixel 180 (pixel circuit 181) also displaying a black image based on the voltage VSIGL of the data signal VDATA in the Kth FRAME. In other words, the driving method shown in the third example involves displaying images of the same color (black) in consecutive frames. Configurations that are the same as or similar to those in FIGS. 1 to 6 will be described as necessary.

[0113] The configuration of the first scan signal SC1(n) to the fifth scan signal SC5(n) is the same as the configuration described in "1-5-1. First Example of the Method for Driving the Display Device 10." The voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the horizontal period HRP of the Kth FRAME and the light emission period PEM of the Kth FRAME are the same as the configuration described in "1-5-1. First Example of the Method for Driving the Display Device 10." The operation of each transistor during each period is the same as the configuration described in "1-5-1. First Example of the Method for Driving the Display Device 10." Therefore, configurations similar to those described in "1-5-1. First Example of the Method for Driving the Display Device 10" will be described as necessary. During the horizontal period HRP, the image data signal SL(m) is supplied with a data signal VDATA of VSIGH corresponding to black, and during periods other than the horizontal period HRP, a data signal VDATA similar to the configuration described in "1-5-1. First Example of the Method for Driving the Display Device 10" is supplied.

[0114] The light-emitting period PEM of the K-1st FRAME is a period during which the pixel 180 (pixel circuit 181) emits light in accordance with the potential difference Vgs (voltage V(N2) - voltage V(N3) = Vnf (-0.5 V) - voltage Vne (-1 V). For example, the potential difference Vgs is 0.5 V, which is smaller than the threshold voltage VTH. Therefore, the second transistor T2 is in the off state, and no current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS, so the light-emitting element OLED does not emit light. As a result, for example, the pixel 180 (pixel circuit 181) turns black.

[0115] During the period between the light-emitting period PEM of the (K-1st) FRAME and the period PIP of the Kth FRAME, the voltage supplied to the first node N1 remains at voltage Vnf, and the voltage supplied to the second node N2 gradually increases from voltage Vnf toward the reference voltage VREF. Furthermore, the voltage supplied to the third node N3 gradually decreases from voltage Vnb toward voltage Vnc. The second transistor T2 and the fifth transistor T5 are on, and a current flows from the driving power line PVDD to the initialization voltage power line SVI, so the light-emitting element OLED does not emit light.

[0116] During the period PIP of the Kth FRAME, which follows the period between the light-emitting period PEM of the K-1st FRAME and the period PIP of the Kth FRAME, the voltage supplied to the first node N1 gradually increases from voltage Vnf toward voltage Vnd (pre-charge voltage VPRC, 1.5V) and reaches voltage Vnd. The voltage supplied to the second node N2 gradually increases from voltage Vnf toward 0V (reference voltage VREF) and reaches 0V. The voltage supplied to the third node N3 gradually decreases from voltage Vne toward voltage Vnc (initialization voltage VINI, -2V) and reaches voltage Vnc. The potential difference Vgs becomes 2V (0V - -2V), and the potential difference Vds becomes 10V (8V - -2V). Because the second transistor T2 and the fifth transistor T5 are on and a current flows from the drive power supply line PVDD to the initialization voltage power supply line SVI, the light-emitting element OLED does not emit light.

[0117] As described above, during the period PIP in the third example of the driving method for the display device 10, a precharge voltage (intermediate potential) is supplied to the first node N1, the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI (-2V).

[0118] As described above, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, as well as the operation of each transistor, during the horizontal period HRP and the light emission period PEM of KthFRAME following the period PIP are the same as those in "1-5-1. First example of the method for driving the display device 10."

[0119] During the period PWR in the third example, a data signal VDATA (voltage VSIGL in the third example) is written to the pixel 180 (pixel circuit 181) as in "1-5-1. First example of the method for driving the display device 10." During the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (first electrode 692 of the capacitance element CS).

[0120] Furthermore, during the light emission period PEM of KthFRAME, as in "1-5-1. First example of the driving method of the display device 10", the pixel 180 that emits red light, the pixel 180 that emits blue light, and the pixel 180 that emits green light do not emit light, so the three pixels using the pixel 180 that emits red light, the pixel 180 that emits blue light, and the pixel 180 that emits green light are black.

[0121] <1-5-4. Fourth Example of the Method for Driving the Display Device 10> A fourth example of a method for driving the display device 10 will be described with reference to FIG. 8. The driving method shown in the fourth example of the method for driving the display device 10 involves the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGL of the data signal VDATA in the frame (K-1st FRAME) immediately before the current frame (Kth FRAME), and then the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH of the data signal VDATA in the Kth FRAME. In other words, the driving method shown in the fourth example involves displaying images of different colors in successive frames. Configurations that are the same as or similar to those in FIGS. 1 to 7 will be described as necessary.

[0122] The configuration of the first scan signal SC1(n) to the fifth scan signal SC5(n) is the same as the configuration described in "1-5-1. First example of the method for driving the display device 10." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light emission period PEM of the K-1th FRAME and the period PIP of the Kth FRAME are the same as those in "1-5-3. Third example of the method for driving the display device 10." The voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the horizontal period HRP of the Kth FRAME and the light emission period PEM of the Kth FRAME are the same as those in "1-5-2. Second example of the method for driving the display device 10." Configurations similar to those of "1-5-1. First example of a method for driving the display device 10," "1-5-2. Second example of a method for driving the display device 10," and "1-5-3. Third example of a method for driving the display device 10" will be explained as necessary. Note that, in the horizontal period HRP, the data signal VDATA of VSIGH corresponding to white is supplied to the image data signal SL(m), and in periods other than the horizontal period HRP, the data signal VDATA similar to the configuration explained in "1-5-1. First example of a method for driving the display device 10" is supplied.

[0123] The driving method of the fourth example of display device 10 during the light-emitting period PEM of K-1stFRAME, the period between the light-emitting period PEM of K-1stFRAME following the light-emitting period PEM of K-1stFRAME and the period PIP of KthFRAME, and the period PIP of KthFRAME is the same as the driving method described in "1-5-3. Third example of driving method of display device 10."

[0124] The fourth example of the driving method for the display device 10 during the horizontal period HRP of the K-1st FRAME and the light emission period PEM of the Kth FRAME is the same as the driving method described in "1-5-2. Second example of the driving method for the display device 10."

[0125] <1-6. End surface structure of pixel 180 along line A1-A2> The end face structure of pixel 180 taken along line A1-A2 will be described with reference to FIGS. 9, 10, and 12 to 14. FIGS. 9 and 12 to 14 are layout diagrams of pixel 180. FIG. 10 is an end face diagram showing an end face cut along A1-A2 in the planar layout of pixel 180 shown in FIG. 9. The configurations of pixel 180 shown in FIGS. 9, 10, and 12 to 14 are examples, and the configuration of pixel 180 is not limited to the examples shown in FIGS. 9, 10, and 12 to 14. Configurations that are the same as or similar to those in FIGS. 1 to 8 will be described as necessary.

[0126] 10 is an example of an end face of the pixel 180, and includes the drive power supply line PVDD (first wiring 132A), the contact hole opening 147 for the anode electrode, the second electrode 694 (first wiring 132C) of the capacitance element CS, the first electrode 692 (second wiring 140A) of the capacitance element CS, the gate electrode 622 (gate wiring 127A) of the second transistor T2, the channel region 123 of the semiconductor layer 122, the organic insulating film opening 138A for the capacitance element CS, the first contact hole opening 135E, the first wiring 132G, the second contact The end face is along the hole opening portion 138G, the scan signal line 331 (gate wiring 127C), the first contact hole opening portion 135F, the semiconductor layer 122B, the scan signal line 330 (gate wiring 127B), the second electrode 694 (first wiring 132C) of the capacitance element CS, the second wiring 140E, the first wiring 132F, the first contact hole opening portion 135K, the semiconductor layer 122C, the gate wiring 127J, the drive power supply line PVDD (first wiring 132A), the reference voltage power supply line SVR (first wiring 132K), and the first contact hole opening portion 135B.

[0127] The substrate 101 includes a first surface 101A and a second surface 101B opposite to the first surface 101A. A semiconductor layer 122 is provided on the first surface 101A of the substrate 101 via an underlayer 121. The semiconductor layer 122 includes semiconductor layers 122A, 122B, and 122C. The semiconductor layer 122A includes a channel region 123 and an impurity region 124A. For example, the impurity region is called a source region or a drain region. Also, for example, the second transistor T2 and the fifth transistor T5 include the semiconductor layer 122A, and the first electrode 624 and the second electrode 656 include the impurity region 124A. In other words, the semiconductor layer 122A includes the channel region of the second transistor T2 and the channel region of the fifth transistor T5. Similar to the semiconductor layer 122A, the first transistor T1 and the third transistor T3 include the semiconductor layer 122B, the fourth transistor T4 includes the semiconductor layer 122C, and the first electrode 614, the second electrode 616, the first electrode 634, the second electrode 636, the first electrode 644, and the second electrode 646 include impurity regions.

[0128] A gate insulating layer 125, a conductive layer 126, an insulating layer 128, and a conductive layer 132 are provided on the semiconductor layer 122 in this order. The conductive layer 126 includes a gate wiring 127A (gate electrode 622), a gate wiring 127B (scan signal line 330), a gate wiring 127C (scan signal line 331), and a gate wiring 127J (reference voltage power supply line SVR). The conductive layer 132 includes a first wiring 132A (drive power supply line PVDD), a first wiring 132C (second electrode 694), a first wiring 132G, a first wiring 132F, and a first wiring 132K (reference voltage power supply line SVR). The region where the conductive layer 126 and the semiconductor layer 122 overlap is a channel region. In other words, the region where the gate electrode and the semiconductor layer of each transistor overlap is a channel region.

[0129] Each of the transistors of the pixel 180 is formed using a semiconductor layer 122 (channel region 123 and impurity region 124A), a gate insulating layer 125, and a conductive layer 126 (for example, gate wiring 127A).

[0130] A first contact hole opening 135 reaching the semiconductor layer 122 is provided in the gate insulating layer 125 and the insulating layer 128. The first contact hole opening 135E exposes the gate wiring 127A. The first contact hole opening 135F exposes the gate wiring 127J and the semiconductor layer 122B. The first contact hole opening 135K exposes the semiconductor layer 122C. The first contact hole opening 135B exposes the gate wiring 127J.

[0131] The conductive layer 132 is electrically connected to the semiconductor layer 122 or the conductive layer 126 through the first contact hole opening 135. For example, the first wiring 132G is electrically connected to the gate wiring 127A through the first contact hole opening 135E, and is also electrically connected to the semiconductor layer 122B through the first contact hole opening 135F. That is, the first wiring 132G has a function of electrically connecting the gate wiring 127A and the semiconductor layer 122B. Furthermore, for example, the first wiring 132F is electrically connected to the gate wiring 127J and the semiconductor layer 122C through the first contact hole opening 135K. That is, the first wiring 132F has a function of electrically connecting the gate wiring 127J and the semiconductor layer 122C through one opening (the first contact hole opening 135K).

[0132] An insulating layer 131 is provided to cover the conductive layer 132. An insulating layer 136 is provided to cover the insulating layer 131.

[0133] A second contact hole opening 138G is provided in the insulating layer 131 and the insulating layer 136. An organic insulating film opening 138A for the capacitor element CS is provided in the insulating layer 136. A conductive layer 139 is provided on the insulating layer 136, in the organic insulating film opening 138A for the capacitor element CS and the second contact hole opening 138G. The conductive layer 139 includes a second wiring 140A (first electrode 692), a second wiring 140B, and a second wiring 140E (reference voltage power supply line SVR). The second contact hole opening 138G exposes the conductive layer 132 (e.g., the first wiring 132G). For example, the second contact hole opening 138G electrically connects the second wiring 140B and the first wiring 132G. The organic insulating film opening 138A for the capacitor element CS exposes the insulating layer 136. For example, the capacitance element CS is formed using the first wiring 132C (second electrode 694) and the second wiring 140A (first electrode 692) with the insulating layer 131 as a dielectric. For example, the second wiring 140A also serves as a pixel electrode. Although not shown, the second contact hole opening 138 exposes some of the multiple terminals (not shown) included in the terminal section 150. Some of the exposed terminals are electrically connected to the FPC 200 using a conductive film such as an anisotropic conductive film (not shown).

[0134] An insulating layer 141 is provided over the conductive layer 139 .

[0135] The base layer 121 , the semiconductor layer 122 , the gate insulating layer 125 , the conductive layer 126 , the insulating layer 128 , the conductive layer 132 , the insulating layer 131 , the insulating layer 136 , the conductive layer 139 , and the insulating layer 141 are collectively referred to as an array section 170 .

[0136] Next, a description will be given of layers above the insulating layer 141. An anode electrode contact hole opening 147 is provided in the insulating layer 141. The anode electrode contact hole opening 147 exposes the conductive layer 139 (for example, the second wiring 140A).

[0137] An anode electrode 143 is provided to cover the exposed conductive layer 139, the anode electrode contact hole opening 147, and the insulating layer 141. A functional layer 148 is provided on the anode electrode 143. A common electrode 149 is provided on the functional layer 148. The common electrode 149 is a cathode electrode (first electrode 682 of the light-emitting element OLED). Here, the light-emitting element OLED is composed of the anode electrode 143, the functional layer 148, and the common electrode 149.

[0138] The configuration of the functional layer 148 can be selected as appropriate. For example, the functional layer 148 can be configured by combining a carrier injection layer, a carrier transport layer, an emission layer, a carrier blocking layer, an exciton blocking layer, etc. For example, the functional layer 148 shown in Fig. 10 includes a first layer 144, a second layer 145, and a third layer 146. For example, the first layer 144 is a carrier (hole) injection and transport layer, the second layer 145 is a emission layer, and the third layer 146 is a carrier (electron) injection and transport layer.

[0139] A sealing film 165 is provided on the common electrode 149. For example, the sealing film 165 includes a first inorganic insulating layer 152, an organic insulating layer 154, and a second inorganic insulating layer 156. The first inorganic insulating layer 152 and the second inorganic insulating layer 156 are formed so as to cover at least the display region 22. A cover film 158 is disposed on the second inorganic insulating layer 156.

[0140] For example, the first layer 144, the second layer 145 (light-emitting layer), and the third layer 146 included in the functional layer 148, as well as the common electrode 149, are not disposed on the IC chip 110 and the control circuit 120. A sealing film 165 and a cover film 158 are disposed on the IC chip 110 and the control circuit 120. The sealing film 165 and the cover film 158 prevent impurities (water, oxygen, etc.) from entering the light-emitting element OLED, the transistors, etc. from the outside of the display device 10.

[0141] Common metal materials are used for the conductive layer 126, the conductive layer 132, the conductive layer 139, and the common electrode 149. For example, common metal materials include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof.

[0142] For example, the semiconductor layer 122 may include LTPS, and may include a metal oxide.

[0143] A general insulating material can be used as the material for forming the base layer 121, the gate insulating layer 125, the insulating layer 131, the first inorganic insulating layer 152, and the second inorganic insulating layer 156. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y Inorganic insulating layers such as the above are used.

[0144] For example, an organic compound material with excellent surface flatness can be used as the material for forming the insulating layer 128, the insulating layer 136, the insulating layer 141, and the organic insulating layer 154. The insulating layer 128, the insulating layer 136, and the insulating layer 141 may be referred to as organic insulating layers.

[0145] <1-7. Manufacturing method of display device 10> A method for manufacturing the display device 10 (pixel 180) will be described with reference to Figures 9 to 14. Figure 11 is a sequence diagram showing the method for manufacturing the display device 10. Configurations that are the same as or similar to those in Figures 1 to 8 will be described as necessary.

[0146] As shown in FIG. 10, when the manufacturing of the display device 10 (pixel 180) starts, the underlayer 121 is formed on the first surface 101A of the substrate 101.

[0147] As shown in FIG. 10 or 12, a semiconductor layer 122 is formed on the base layer 121 (step 10 (S10) of FIG. 11). The semiconductor layer 122 includes semiconductor layers 122A, 122B, 122C, and 122D. The semiconductor layer 122A serves as the semiconductor layer of both the second transistor T2 and the fifth transistor T5. The semiconductor layer 122B serves as the semiconductor layer of both the first transistor T1 and the third transistor T3. The semiconductor layer 122C is the semiconductor layer of the fourth transistor T4. The semiconductor layer 122D is the semiconductor layer of the sixth transistor T6. In other words, the semiconductor layer 122B includes the channel region of the first transistor T1 and the channel region of the third transistor T3, the semiconductor layer 122C includes the channel region of the fourth transistor T4, and the semiconductor layer 122D includes the channel region of the sixth transistor T6.

[0148] For example, the manufacturing method of the display device 10 includes forming the semiconductor layer 122 using a metal oxide. Therefore, the first transistor T1 to the sixth transistor T6 can all be n-channel field effect transistors. For example, the manufacturing method of the display device 10 can reduce the number of manufacturing steps compared to when the semiconductor layer 122 is formed using crystalline silicon or the like and n-channel field effect transistors and p-channel field effect transistors are formed. Furthermore, the manufacturing method of the display device 10 can suppress a decrease in yield and reduce manufacturing costs by reducing the number of manufacturing steps.

[0149] A gate insulating layer 125 (see FIG. 10) is formed on the semiconductor layer 122 and on the underlying layer 121 where the semiconductor layer 122 is not formed (step 11 (S11) in FIG. 11).

[0150] A conductive layer 126 (see FIG. 10 ) is formed on the gate insulating layer 125 (step 12 (S12) of FIG. 11 ). As shown in FIG. 10 or FIG. 12 , the conductive layer 126 includes a gate wiring 127A (gate electrode 622), a gate wiring 127B (scan signal line 330), a gate wiring 127C (scan signal line 331), a gate wiring 127D (scan signal line 332), a gate wiring 127E (scan signal line 333), a gate wiring 127F (scan signal line 334), a gate wiring 127G (initialization voltage power line SVI), a gate wiring 127H (precharge voltage power line SVP), and a gate wiring 127J (reference voltage power line SVR). The gate wiring 127B includes a gate electrode 632, and the gate wiring 127C includes a gate electrode 642. The gate wiring 127D includes a gate electrode 652, and the gate wiring 127E includes a gate electrode 662. The gate wiring 127F includes a gate electrode 612.

[0151] The overlapping region between the gate electrode 622 and the semiconductor layer 122A of the second transistor T2 is the channel region 123, which corresponds to the channel length of the second transistor T2. Similarly, the overlapping region between the gate electrode 612 and the semiconductor layer 122B of the first transistor T1 is the channel region and the channel length of the first transistor T1. The overlapping region between the third transistor T3 and the semiconductor layer 122B is the channel region and the channel length of the third transistor T3. The overlapping region between the fourth transistor T4 and the semiconductor layer 122C is the channel region and the channel length of the fourth transistor T4. The overlapping region between the fifth transistor T5 and the semiconductor layer 122A is the channel region and the channel length of the fifth transistor T5. The overlapping region between the sixth transistor T6 and the semiconductor layer 122D is the channel region and the channel length of the sixth transistor T6.

[0152] As shown in FIG. 12 , in a plan view, the channel region 123 of the second transistor T2 is larger (longer) than the channel regions of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. That is, the channel length of the second transistor T2 is longer than the channel lengths of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. Because the second transistor T2 operates in the saturation region, it is necessary to suppress the kink effect. Furthermore, the hot carrier resistance of the second transistor T2 must be higher than that of the other transistors in the pixel 180. To suppress the kink effect and ensure reliability (hot carrier resistance), the channel length of the second transistor T2 is longer than that of the other transistors in the pixel 180.

[0153] An insulating layer 128 (see FIG. 10) is formed on the conductive layer 126 and on the gate insulating layer 125 where the conductive layer 126 is not formed (step 13 (S13) in FIG. 11).

[0154] As shown in FIG. 10 or FIG. 12, first contact hole openings 135, 135A, 135B, 135C, 135D, 135E, 135F, 135G, 135H, 135J, 135K, 135L, 135M, and 135N are opened (step 14 (S14)). Each opening opens the gate insulating layer 125 and the insulating layer 128, exposing the corresponding wiring, semiconductor layer, or electrode. For example, first contact hole opening 135 exposes the semiconductor layer 122A (e.g., impurity region 124A), and first contact hole opening 135A exposes the gate wiring 127G. The other openings also expose the corresponding wiring, semiconductor layer, or electrode.

[0155] The conductive layer 132 (see FIG. 10) is formed on the insulating layer 128 (step 15 (S15)). As shown in FIG. 10 or 13, the conductive layer 132 includes a first wiring 132A (drive power supply line PVDD), a first wiring 132B, a first wiring 132C (second electrode 694), a first wiring 132D, a first wiring 132E, a first wiring 132F, a first wiring 132G, a first wiring 132H (image data signal line 321), a first wiring 132J, and a first wiring 132K (reference voltage power supply line SVR).

[0156] As shown in FIG. 13, in a planar view, the first wiring 132A is electrically connected to the semiconductor layer 122A via the first contact hole opening 135D, the second electrode 694 is electrically connected to the first electrode 644 via the first contact hole opening 135J, the second electrode 694 is electrically connected to the second electrode 616 and the first electrode 634 via the first contact hole opening 135G and is electrically connected to the second electrode 666 via the first contact hole opening 135L, and the first wiring 132D is electrically connected to the second electrode 656 and the first electrode 624 via the first contact hole opening 135. 13, in plan view, first wiring 132E is electrically connected to initialization voltage power supply line SVI through first contact hole opening 135A and is electrically connected to first electrode 654 through first contact hole opening 135C, first wiring 132F is electrically connected to second electrode 646 through first contact hole opening 135K, and first wiring 132G is electrically connected to second electrode 636 through first contact hole opening 135F and is electrically connected to gate electrode 622 through first contact hole opening 135E. The image data signal line 321 is electrically connected to the first electrode 614 through the first contact hole opening 135H, the first wiring 132J is electrically connected to the first electrode 664 through the first contact hole opening 135M and is electrically connected to the precharge voltage power supply line SVP through the first contact hole opening 135N, and the reference voltage power supply line SVR is electrically connected to the gate wiring 127C through the first contact hole opening 135B and is electrically connected to the second electrode 646 through the first contact hole opening 135K.

[0157] 13, the second electrode 694, the gate electrode 622, and the semiconductor layer 122A (channel region 123) overlap with each other. That is, the second transistor T2 (its channel region and gate electrode 622) overlaps with the second electrode 694 of the capacitance element CS.

[0158] An insulating layer 131 (see FIG. 10) is formed on the conductive layer 132 and on the insulating layer 128 where the conductive layer 132 is not formed (step 16 (S16) in FIG. 11).

[0159] As shown in FIG. 10 or 14, second contact hole openings 138B, 138C, 138D, 138E, 138F, 138G, and 138H are opened (step 17 (S17)). Each opening opens the insulating layer 131 and exposes the corresponding wiring, semiconductor layer, or electrode. For example, second contact hole opening 138B exposes the first wiring 132D, and second contact hole opening 138G exposes the first wiring 132G. The other openings also expose the corresponding wiring, semiconductor layer, or electrode.

[0160] An insulating layer 136 (organic insulating layer) (see FIG. 10) is formed on the insulating layer 131 (step 18 (S18) in FIG. 11).

[0161] As shown in FIG. 10 or 14, holes are opened in the insulating layer 136 (organic insulating layer) (step 19 (S20)). In the opening of S19, an organic insulating film opening 138A for the capacitor element CS is opened. In addition, in the opening of S19, second contact hole openings 138B, 138C, 138D, 138E, 138F, 138G, and 138H are opened, similar to the opening of S17. That is, the second contact hole openings 138B, 138C, 138D, 138E, 138F, 138G, and 138H are opened twice. Each opening opens the insulating layer 136, exposing the corresponding insulating layer, wiring, or electrode. For example, organic insulating film opening 138A for capacitor element CS removes only insulating layer 136 on second electrode 694, exposing insulating layer 131. On the other hand, second contact hole opening 138G removes only insulating layer 136 on first wiring 132G, exposing first wiring 132G. Other openings also expose the corresponding insulating layer, wiring, or electrode.

[0162] A conductive layer 139 (see FIG. 110) is formed on the insulating layer 136, on the insulating layer 131 exposed by the organic insulating film opening 138A for the capacitor element CS (step 20 (S20)). As shown in FIG. 9 or 10, the conductive layer 139 includes a second wiring 140A (first electrode 692), a second wiring 140B, a second wiring 140C, and a second wiring 140D. The conductive layer 139 also includes a second wiring 140A (first electrode 692), a second wiring 140B, a second wiring 140C, a second wiring 140D, and a second wiring 140E (reference voltage power supply line SVR).

[0163] 9 or 10, in a plan view, the first electrode 692 is electrically connected to the second transistor T2 and the fifth transistor T5 via the second contact hole opening 138B and the first contact hole opening 135. The second wiring 140B is electrically connected to the third transistor T3 via the second contact hole opening 138G, the first wiring 132G, and the first contact hole opening 135F, electrically connected to the fourth transistor T4 via the second contact hole opening 138E, the first wiring 132B, and the first contact hole opening 135J, and electrically connected to the gate electrode 622 via the second contact hole opening 138E, the first wiring 132B, and the first contact hole opening 135E. The second wiring 140C is electrically connected to the first wiring 132E and the initialization voltage power supply line SVI via the second contact hole opening 138C and the first contact hole opening 135A. The second wiring 140D is electrically connected to the first wiring 132J and the precharge voltage power supply line SVP via the second contact hole opening 138H and the first contact hole opening 135N. The second wiring 140E is electrically connected to the gate wiring 127C and the fourth transistor T4 via the second contact hole opening 138F, the first wiring 132F, and the first contact hole opening 135K, and is electrically connected to the first wiring 132K (reference voltage power supply line SVR) via the second contact hole opening 138D.

[0164] 9, the second wiring 140C is connected to and overlaps with the gate wiring 127G (initialization voltage power line SVI), and extends parallel to the gate wiring 127G in the second direction D2. Since the initializing voltage power line SVI is formed using two layers of metal wiring, it has a lower wiring resistance than a voltage line formed using a single layer of metal wiring. As a result, the initializing voltage power line SVI has a high current supply capability and can supply a stable voltage to each transistor. The second wiring 140D is connected to and overlaps with the gate wiring 127H (precharge voltage power line SVP), and extends parallel to the gate wiring 127G in the second direction D2. Since the precharge voltage power line SVP is formed using two layers of metal wiring, similar to the initializing voltage power line SVI, it provides the same effects as the initializing voltage power line SVI.

[0165] 9, the first electrode 692, the second electrode 694, the gate electrode 622, and the semiconductor layer 122A (channel region 123) overlap with each other. That is, the second transistor T2 overlaps with the capacitor CS.

[0166] An insulating layer 141 (organic insulating layer) (see FIG. 10) is formed on the conductive layer 139 and on the insulating layer 136 where the conductive layer 139 is not formed (step 21 (S21) in FIG. 11).

[0167] As shown in FIG. 9 or 10, an opening is made in the insulating layer 141 (organic insulating layer) (step 22 (S22)). In the opening of S22, a contact hole opening 147 for the anode electrode is opened. The contact hole opening 147 for the anode electrode removes the insulating layer 141 above the second wiring 140A, exposing the second wiring 140A. The contact hole opening 147 for the anode electrode is sometimes called an organic insulating layer opening. Note that, as shown in FIG. 9, the contact hole opening 147 overlaps the second wiring 140A and the first wiring 132A in a plan view.

[0168] An anode electrode 143 is provided on the exposed second wiring 140A, on the anode electrode contact hole opening 147, and on the insulating layer 141. A functional layer 148 is provided on the anode electrode 143. A common electrode 149 is provided on the functional layer 148 (step 23 (S23)). Note that, for example, the anode electrode 143 and the functional layer 148 are provided for each pixel, and the common electrode 149 is provided so as to overlap the display region 22.

[0169] After S24, the sealing film 165 and the cover film 158 are provided on the common electrode 149 in this order.

[0170] In this manner, the manufacturing of the display device 10 (pixel 180) is completed.

[0171] 2. Second Embodiment An overview of the display device according to the second embodiment will be described with reference to Fig. 1, Fig. 4, and Fig. 15 to Fig. 20. Fig. 15 is a schematic diagram showing an input signal to a pixel 180A (pixel circuit 181A) according to the second embodiment, Fig. 16 is a circuit diagram showing the configuration of the pixel circuit 181A, and Fig. 17 to Fig. 20 are timing charts of the display device according to the second embodiment.

[0172] The display device according to the second embodiment includes a pixel 180A and a pixel circuit 181A. Specifically, the pixel 180A and the pixel circuit 181A include the configurations shown in the following (1) to (3). The configurations shown in (1) to (3) are mainly different from the configurations of the pixel 180 and the pixel circuit 181 of the display device 10 according to the first embodiment.

[0173] (1) The scan voltage power supply line SVIR to which the scan voltage power supply SIR(n) is supplied is included. (2) The scan voltage power supply line SVIR is a common signal line that serves as both the reference voltage power supply line SVR to which the reference voltage power supply VREF is supplied and the initialization voltage power supply line SVI to which the initialization voltage VINI is supplied. That is, the scan voltage power supply line SVIR has a configuration that serves as both the reference voltage power supply line SVR and the initialization voltage power supply line SVI. (3) The scan voltage power supply SIR(n) includes a voltage that alternates with time, which is an initialization voltage VINI2 and an initialization voltage VINI1.

[0174] The configurations of the pixel 180A and the pixel circuit 181A shown in (1) to (3), and the configurations other than those related to the configurations of the pixel 180A and the pixel circuit 181A shown in (1) to (3), are the same as those of the display device 10 according to the first embodiment. Therefore, differences from the display device 10 according to the first embodiment will be mainly described here. In describing the configuration and functions of the display device according to the second embodiment, configurations and functions that are the same as those of the display device 10 according to the first embodiment will be described as necessary. Furthermore, configurations that are the same as or similar to those in FIGS. 1 to 14 will be described as necessary.

[0175] <2-1. Configuration of pixel 180A> The pixel 180A and pixel circuit 181A will be outlined with reference to FIGS.

[0176] The pixel circuit 181A is connected to a scan voltage power line SVIR. The scan voltage power line SVIR functions as a power line that supplies voltage to the pixel 180A and the pixel circuit 181A, and also functions as a signal line whose voltage (potential) changes over time.

[0177] In the pixel circuit 181A, a first electrode 644 of the fourth transistor T4 and a first electrode 654 of the fifth transistor T5 are electrically connected to the scan voltage power supply line SVIR. The first electrode 644 of the fourth transistor T4 and the first electrode 654 of the fifth transistor T5 are supplied with the initialization voltage VINI2 or the initialization voltage VINI1 depending on time.

[0178] For example, the scan voltage power supply line SVIR is electrically connected to a connection wiring 342 that is different from the precharge voltage power supply line SVP, the drive power supply line PVDD, and the reference voltage line PVSS among the connection wirings 342. Also, for example, the scan voltage power supply line SVIR may be one of the connection wirings 342.

[0179] For example, the scan voltage power supply SIR(n) may be supplied from an external device to the IC chip 110, similar to the initialization voltage VINI, or may be supplied from the IC chip 110 to the plurality of pixels 180A (pixel circuits 181A) via the connection wiring 342 and the scan voltage power supply line SVIR. Although not shown, the scan voltage power supply SIR(n) may be connected from an external device to the scan voltage power supply line SVIR via the FPC 200, the terminal unit 150, and the connection wiring 341, similar to the initialization voltage VINI, without going through the IC chip 110 and the connection wiring 342.

[0180] The fourth transistor T4 has a function of connecting the second node N2 and the scan voltage power supply line SVIR and supplying the initialization voltage VINI1 or VINI2 to the second node N2, thereby initializing the second node N2. For example, the initialization voltages VINI1 and VINI2 are constant voltages.

[0181] The fifth transistor T5 has a function of connecting the third node N3 and the scan voltage power supply line SVIR to each other, supplying the initialization voltage VINI1 to the third node N3, and initializing the third node N3.

[0182] The configuration and functions of the pixel circuit 181A other than those described in "2-1. Configuration of the pixel 180A" are the same as those of the pixel circuit 181.

[0183] <2-2. Driving Method of Pixel Circuit 181A> A method for driving a display device according to the second embodiment will be described with reference to Figures 17 to 20. Configurations that are the same as or similar to those in Figures 1 to 16 will be described as necessary. As in the first embodiment, the horizontal axis of the timing chart represents time.

[0184] The method for driving the display device according to the second embodiment differs from the method for driving the display device 10 according to the first embodiment in the configuration related to the configurations shown in (1) to (3) described in "2-1. Configuration of pixel 180A." The configurations and functions other than the configurations related to (1) to (3) described in "2-1. Configuration of pixel 180A" are the same as those of the method for driving the display device 10 according to the first embodiment.

[0185] The method for driving the display device according to the second embodiment includes the same period as the method for driving the display device 10 according to the first embodiment shown in FIG.

[0186] During one horizontal period (horizontal period HRP) in the driving method of the display device according to the second embodiment, the pixel 180A (pixel circuit 181A) receives a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), a fifth scan signal SC5(n), an image data signal SL(m), and a scan voltage power supply SIR(n). For example, the pixel 180A (pixel circuit 181A) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), the fifth scan signal SC5(n), and the scan voltage power supply SIR(n). The image data signal SL(m) and the scan voltage power supply SIR(n) are input to the selected pixel 180A (pixel circuit 181A) according to the timing of each signal. A similar operation is performed for all pixels 180A (pixel circuits 181A), and based on the image data signals SL(m) input to all pixels 180A (pixel circuits 181A), an image of the frame corresponding to one frame is displayed in the display area 22 of the display device 10.

[0187] For example, the voltages (potentials) supplied to each signal in each frame in the timing charts shown in FIGS.

[0188] [Table 2]

[0189] For example, as shown in Table 2, the initialization voltage VINI2 is 0 V and the initialization voltage VINI1 is −2 V. The initialization voltage VINI2 is the same as the reference voltage VREF, and the initialization voltage VINI1 is the same as the initialization voltage VINI. The setting values ​​of the other voltages are the setting values ​​shown in Table 1 described in “1-5. Method of driving the display device 10.”

[0190] <2-2-1. First Example of Method for Driving Pixel Circuit 181A> A first example of a method for driving the pixel circuit 181A will be described with reference to Fig. 17. The first example of the method for driving the pixel circuit 181A includes displaying images of different colors in successive frames, similar to the first example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 16 will be described as necessary.

[0191] The scan voltage power supply SIR(n) supplies an initialization voltage VINI2 during the light emission period PEM of the K-1st FRAME, an initialization voltage VINI1 during the period PIP of the Kth FRAME, and an initialization voltage VINI2 during the period PVH of the Kth FRAME and the light emission period PEM.

[0192] The configurations of the first scan signal SC1(n) to the fifth scan signal SC5(n) are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Furthermore, the operation of each transistor in each period is the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Therefore, configurations similar to those described in "1-5-1. First Example of the Method for Driving the Display Device 10" will be described as necessary.

[0193] In the light emitting period PEM of the K-1st FRAME, the light emitting element OLED emits light in the same manner as in the configuration described in "1-5-1. First example of the method for driving the display device 10."

[0194] In the period between the light emission period PEM of the (K-1st) FRAME and the period PIP, the scan voltage power supply SIR(n) changes from a state in which 0 V (initialization voltage VINI2) is supplied to a state in which voltage Vnc (initialization voltage VINI1, -2 V) is supplied. The configurations of the first scan signal SC1(n) to the fifth scan signal SC5(n) are the same as those described in "1-5-1. First example of the method for driving the display device 10."

[0195] As a result, the voltage supplied to the second node N2 gradually drops from voltage Vna toward voltage Vnc, the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage Vnd (precharge voltage VPRC, 1.5V), and the voltage supplied to the third node N3 maintains voltage Vnb.

[0196] During the period PIP following the period between the light emission period PEM and the period PIP of the (K-1st) FRAME, the scan voltage power supply SIR(n) maintains a state in which the voltage Vnc (initialization voltage VINI1, -2V) is supplied. The configurations of the first scan signal SC1(n) to the fifth scan signal SC5(n) are the same as those described in "1-5-1. First example of the method for driving the display device 10."

[0197] As a result, the voltage supplied to the first node N1 gradually drops from voltage Vna to voltage Vnd and becomes voltage Vnd. The voltage supplied to the second node N2 gradually drops from voltage Vna to voltage Vnc and becomes voltage Vnc. The voltage supplied to the third node N3 gradually drops from voltage Vnb to voltage Vnc and becomes voltage Vnc. The potential difference Vgs becomes 0 V (-2 V - -2 V), and the potential difference Vds becomes 10 V (8 V - -2 V). Because the potential difference Vgs is smaller than the threshold voltage VTH, the second transistor T2 is in an off state, and the current Ion does not flow from the driving power line PVDD to the scan voltage power line SVIR or the reference voltage line PVSS, so the light-emitting element OLED does not emit light.

[0198] As described above, during the period PIP, the precharge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-2V).

[0199] During the initial period of the horizontal period HRP of the KthFRAME following the period PIP, the scan voltage power supply SIR(n) maintains a state in which the voltage Vnc (initialization voltage VINI1, -2V) is supplied. The configurations of the first scan signal SC1(n) to the fifth scan signal SC5(n) are the same as those described in "1-5-1. First example of the method for driving the display device 10."

[0200] As a result, the voltage supplied to the first node N1 is the voltage Vnd, and the voltages supplied to the second node N2 and the third node N3 are the voltage Vnc. Also, similar to the period PIP, the light-emitting element OLED does not emit light.

[0201] In the period PWR following the beginning of the horizontal period HRP, when the third scan signal SC3(n) changes from being supplied with HI to being supplied with LO, the scan voltage power supply SIR(n) changes from being supplied with the initialization voltage VINI1 (-2V) to being supplied with the initialization voltage VINI2 (0V). The configurations of the first scan signal SC1(n) to the fifth scan signal SC5(n) are the same as those described in "1-5-1. First example of the method for driving the display device 10."

[0202] As a result, the voltage supplied to the first node N1 gradually drops from voltage Vnd toward voltage VSIGL (voltage Vnf, −0.5V), the voltage supplied to the second node N2 gradually rises from voltage Vnc toward 0V (initialization voltage VINI2), and the voltage supplied to the third node N3 maintains voltage Vnc. Also, similar to the period PIP, the light-emitting element OLED does not emit light.

[0203] In the middle of the period PWR, during the period PVH that is parallel to (overlaps with) the period PWR, the scan voltage power supply SIR(n) changes from a state in which the initialization voltage VINI1 (-2V) is supplied to a state in which the initialization voltage VINI2 (0V) is supplied. The configurations of the first scan signal SC1(n) to the fifth scan signal SC5(n) are the same as those described in "1-5-1. First example of the method for driving the display device 10."

[0204] As a result, the voltage supplied to the second node N2 gradually rises from the voltage Vnc toward 0V and reaches 0V.

[0205] Immediately after the start of the period PVH, the potential difference Vgs is 0 V, the potential difference Vds is 10 V, and the second transistor T2 is in the off state. The fifth transistor T5 is also in the off state. Meanwhile, the fourth transistor T4 is in the on state, and the voltage supplied to the second node N2 increases from the voltage Vnc toward the initialization voltage VINI2 (0 V). When the voltage supplied to the second node N2 increases to 0 V, the potential difference Vgs becomes larger than the threshold voltage VTH.

[0206] As a result, the second transistor T2 is turned on, and the voltage supplied to the third node N3 gradually rises from the voltage Vnc. When the potential difference Vgs reaches the threshold voltage VTH, the second transistor T2 is turned off from the on state, and the voltage supplied to the second node N2 and the voltage supplied to the third node N3 return to the voltages supplied at that time. For example, as shown in FIG. 17, the voltage supplied to the second node N2 is 0 V, and the voltage supplied to the third node N3 is the voltage Vne (-1 V). The potential difference Vgs is 1 V (0 V - voltage Vne (-1 V)), the potential difference Vds is 9 V, and the potential difference Vgs is the same as the threshold voltage VTH (1 V). That is, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitive element CS). Also, since the second transistor T2 is in the off state, the current Ion does not flow from the driving power supply line PVDD to the reference voltage line PVSS, and the light-emitting element OLED does not emit light.

[0207] At the end of the period PVH, the scan voltage power supply SIR(n) maintains the state in which the initialization voltage VINI2 (0V) is supplied, and the configurations of the first scan signal SC1(n) to the fifth scan signal SC5(n) are the same as those described in "1-5-1. First example of the method for driving the display device 10."

[0208] As a result, the first node N1 becomes conductive with the second node N2, the voltage supplied to the first node N1 gradually drops toward voltage Vnf and becomes voltage Vnf, the voltage supplied to the second node N2 gradually drops toward voltage Vnf and becomes voltage Vnf, and the voltage supplied to the third node N3 remains at voltage Vne. Since the potential difference Vgs is voltage Vnf-voltage Vne and is smaller than the threshold voltage VTH, no current Ion flows from the driving power line PVDD to the reference voltage line PVSS. Therefore, the light-emitting element OLED does not emit light.

[0209] In this way, during the period PWR, the data signal VDATA is written to the pixel 180 (pixel circuit 181). During the period PVH, the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, thereby acquiring the threshold voltage VTH of the second transistor T2 and holding a charge equivalent to the threshold voltage VTH at the third node N3 (the first electrode 692 of the capacitance element CS).

[0210] During the light emission period PEM of the KthFRAME following the horizontal period HRP of the KthFRAME, the display becomes black with three pixels: a pixel 180A that emits red light, a pixel 180A that emits blue light, and a pixel 180A that emits green light, similar to the configuration described in "1-5-1. First example of the driving method of the display device 10."

[0211] The first example of the method for driving the pixel circuit 181A including the configuration described above has the same effects as the method for driving the display device 10 according to the first embodiment.

[0212] Furthermore, pixel circuit 181A includes a scan voltage power supply line SVIR that also serves as the reference voltage power supply line SVR and the initialization voltage power supply line SVI supplied to pixel circuit 181. Thus, pixel circuit 181A has a configuration that allows the number of signal lines to be reduced, and a display device including pixel circuit 181A can reduce the pixel size. As a result, a display device including pixel circuit 181A can increase the number of pixels, and can achieve higher definition and a larger screen.

[0213] <2-2-2. Second Example of Method for Driving Pixel Circuit 181A> A second example of a method for driving the pixel circuit 181A will be described with reference to Fig. 18. The driving method shown in the second example of the pixel circuit 181A includes displaying images of the same color (white) in consecutive frames, similar to the second example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 17 will be described as necessary.

[0214] The configurations of the first scan signal SC1(n) to the fifth scan signal SC5(n) are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during periods other than the horizontal period HRP of the KthFRAME and the light emission period PEM of the KthFRAME are the same as those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." Furthermore, the operation of each transistor during each period is the same as those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." Therefore, configurations similar to those described in "1-5-1. First Example of the Method for Driving the Display Device 10" and "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A" will be described as necessary. In addition, the image data signal SL(m) is supplied with a data signal VDATA of VSIGH corresponding to white during the horizontal period HRP, and is supplied with a data signal VDATA similar to the configuration described in "1-5-1. First example of the method for driving the display device 10" during periods other than the horizontal period HRP.

[0215] The second example of the driving method for pixel circuit 181A during the light-emitting period PEM of K-1stFRAME, the period between the light-emitting period PEM of K-1stFRAME following the light-emitting period PEM of K-1stFRAME and the period PIP of KthFRAME, the period PIP of KthFRAME, and the initial period of the horizontal period HRP of KthFRAME following the period PIP of KthFRAME is the same as the driving method described in "2-2-1. First example of the driving method for pixel circuit 181A."

[0216] During the period PWR following the initial period of the horizontal period HRP in the second example of the method for driving the pixel circuit 181A, the configuration of each control signal, the operation of each transistor, and the like are the same as those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." The voltage supplied to the first node N1 gradually increases from voltage Vnd toward voltage Vng (voltage VSIGH, 3.5V), the voltage supplied to the second node N2 gradually increases from -2V (initialization voltage VINI1) toward 0V (initialization voltage VINI2), and the voltage supplied to the third node N3 gradually increases from -2V (initialization voltage VINI1) toward voltage Vne (-1V). Also, as in the period PIP, the light-emitting element OLED does not emit light.

[0217] In the middle of the period PWR in the second example of the method for driving the pixel circuit 181A, during the period PVH that is parallel to (overlaps with) the period PWR, the configuration of each control signal, the operation of each transistor, etc. are the same as the configuration explained in "2-2-1. First example of the method for driving the pixel circuit 181A." The voltage supplied to the first node N1 gradually increases toward voltage Vng and becomes voltage Vng, the voltage supplied to the second node N2 gradually increases from -2V toward 0V and becomes 0V, and the voltage supplied to the third node N3 gradually increases from -2V toward voltage Vne and becomes voltage Vne.

[0218] As a result, the potential difference Vgs becomes equal to the threshold voltage VTH. That is, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitor CS). Also, since the second transistor T2 is in the off state and no current flows from the drive power supply line PVDD to the reference voltage line PVSS, the light-emitting element OLED does not emit light.

[0219] During the final period of the period PVH in the second example of the method for driving the pixel circuit 181A, the configuration of each control signal, the operation of each transistor, and the like are the same as those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." The first node N1 becomes conductive with the second node N2, and the voltage supplied to the second node N2 gradually increases. As a result, the second transistor T2 changes from an OFF state to an ON state, and a current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS. Therefore, the voltage supplied to the first node N1 and the voltage supplied to the third node N3 increase to follow the increase in the voltage supplied to the second node N2. Due to the increase in the voltage supplied to the third node N3, the voltage supplied to the first node N1 and the voltage supplied to the second node N2 further increase.

[0220] Furthermore, in the second example of the driving method for pixel circuit 181A, during the light emission period PEM of KthFRAME following the horizontal period HRP of KthFRAME, the voltage supplied to the first node N1 and the voltage supplied to the second node N2 rise to voltage Vna, and the voltage supplied to the third node N3 rises to voltage Vnb.

[0221] As a result, the potential difference Vgs becomes 4.5V (voltage Vna (7V) - voltage Vnb (2.5V)). The potential difference Vgs is larger than the threshold voltage VTH, the second transistor T2 is in the on state, a current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS, and the light-emitting element OLED emits light. For example, the pixel 180A (pixel circuit 181A) emits red light, and three pixels, one for the red-emitting pixel 180A, one for the blue-emitting pixel 180A, and one for the green-emitting pixel 180A, emit white light.

[0222] As described above, during the period PWR in the second example of the method for driving the pixel circuit 181A, the data signal VDATA is written to the pixel 180A (pixel circuit 181A). Furthermore, during the period PVH in the second example of the method for driving the pixel circuit 181A, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS). Furthermore, during the light emission period PEM of the KthFRAME in the second example of the method for driving the pixel circuit 181A, the three pixels emit white light.

[0223] <2-2-3. Third Example of Method for Driving Pixel Circuit 181A> A third example of a method for driving the pixel circuit 181A will be described with reference to Fig. 19. The third example of the method for driving the pixel circuit 181A includes displaying images of the same color (black) in consecutive frames, similar to the third example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 18 will be described as necessary.

[0224] The configurations of the first scan signal SC1(n) to the fifth scan signal SC5(n) are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light emission period of the K-1st FRAME are the same as those described in "1-5-3. Third Example of the Method for Driving the Display Device 10." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light emission period of the K-1st FRAME to the period PIP of the Kth FRAME are the same as those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." The configurations described in "1-5-3. Third Example of Method for Driving Display Device 10," the configurations described in "2-2-1. First Example of Method for Driving Pixel Circuit 181A," and the configurations similar to the configurations described in "2-2-2. Second Example of Method for Driving Pixel Circuit 181A" will be described as necessary. Note that, for example, in the horizontal period HRP, the data signal VDATA of VSIGL corresponding to black is supplied to the image data signal SL(m), and in periods other than the horizontal period HRP, the data signal VDATA similar to the configuration described in "1-5-3. Third Example of Method for Driving Display Device 10" is supplied.

[0225] During the light emission period PEM of the K-1st FRAME, similar to the configuration described in "1-5-3. Third example of the method for driving the display device 10", the light emitting element OLED does not emit light and the pixel 180A (pixel circuit 181A) turns black.

[0226] During the period between the light-emitting period PEM of the K-1st FRAME and the period PIP of the Kth FRAME, which follows the light-emitting period PEM of the K-1st FRAME, the configuration of each control signal and the operation of each transistor are the same as those described in "2-2-1. First Example of the Method for Driving Pixel Circuit 181A." The voltage supplied to the first node N1 gradually increases from voltage Vnf toward voltage Vnd (pre-charge voltage VPRC, 1.5V), the voltage supplied to the second node N2 gradually decreases from voltage Vnf toward initialization voltage VINI1 (Vnc, -2V), and the voltage supplied to the third node N3 gradually decreases from voltage Vne toward initialization voltage VINI1 (Vnc, -2V). In addition, the light-emitting element OLED does not emit light.

[0227] During the period PIP of the Kth FRAME following the period between the light-emitting period PEM and the period PIP of the K-1st FRAME, the voltage supplied to the first node N1 gradually increases from voltage Vnf to voltage Vnd and becomes voltage Vnd (pre-charge voltage VPRC). The voltage supplied to the second node N2 gradually decreases from voltage Vnf to voltage Vnc and becomes voltage Vnc (initialization voltage VINI1). The voltage supplied to the third node N3 gradually decreases from voltage Vne to voltage Vnc and becomes voltage Vnc. The potential difference Vgs becomes 0V, and the potential difference Vds becomes 8V. The light-emitting element OLED does not emit light. As described above, during the period PIP, the pre-charge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-2V).

[0228] From the beginning of the horizontal period HRP of KthFRAME following the period PIP to the light emission period PEM of KthFRAME, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor, are the same as the configuration and operation described in "2-2-1. First example of the driving method of the pixel circuit 181A."

[0229] During the period PWR, similar to the configuration described in "2-2-1. First Example of Method for Driving Pixel Circuit 181A", a data signal VDATA (voltage VSIGL in the third example) is written to the pixel 180A (pixel circuit 181A).

[0230] Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitive element CS).

[0231] Furthermore, during the light emission period PEM of KthFRAME, similar to the configuration described in "2-2-1. First example of driving method for pixel circuit 181A", three pixels, using pixel 180A that emits red light, pixel 180A that emits blue light, and pixel 180A that emits green light, produce black.

[0232] <2-2-4. Fourth Example of Method for Driving Pixel Circuit 181A> A fourth example of a method for driving the pixel circuit 181A will be described with reference to Fig. 20. The fourth example of the method for driving the pixel circuit 181A includes displaying images of different colors in successive frames, similar to the fourth example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 19 will be described as necessary.

[0233] The configuration of the first scan signal SC1(n) to the fifth scan signal SC5(n) is the same as the configuration described in "1-5-1. First Example of the Method for Driving the Display Device 10." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light-emitting period of the K-1st FRAME to the period PIP of the Kth FRAME, are the same as the configuration and operation described in "2-2-3. Third Example of the Method for Driving the Pixel Circuit 181A." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the initial period of the horizontal period HRP of the Kth FRAME to the light-emitting period PEM of the Kth FRAME, which follows the period PIP of the Kth FRAME, are the same as the configuration and operation described in "2-2-2. Second Example of the Method for Driving the Pixel Circuit 181A." Configurations similar to those described in "1-5-1. First Example of a Method for Driving the Display Device 10," "2-2-1. First Example of a Method for Driving the Pixel Circuit 181A," "2-2-2. Second Example of a Method for Driving the Pixel Circuit 181A," and "2-2-3. Third Example of a Method for Driving the Pixel Circuit 181A" will be described as necessary. Note that, as for the image data signal SL(m), a data signal VDATA including a voltage VSIGH corresponding to white is supplied during the period between the light emission period PEM of the K-1st FRAME and the light emission period PEM of the Kth FRAME.

[0234] In the light emission period PEM of the (K-1st) FRAME, the pixel 180 (pixel circuit 181) turns black, as in "2-2-3. Third example of the method for driving the pixel circuit 181A."

[0235] During the period between the light-emitting period PEM of the K-1st FRAME and the period PIP of the Kth FRAME following the light-emitting period PEM of the K-1st FRAME, the voltage supplied to the first node N1 gradually rises from voltage Vnf toward voltage Vnd (pre-charge voltage VPRC, 1.5V), the voltage supplied to the second node N2 gradually drops from voltage Vnf toward the initialization voltage VINI1 (Vnc, -2V), and the voltage supplied to the third node N3 gradually drops from voltage Vne toward the initialization voltage VINI1 (Vnc, -2V). Also, the light-emitting element OLED does not emit light.

[0236] During the period PIP of the KthFRAME, which follows the period between the light emission period PEM of the K-1stFRAME and the period PIP of the KthFRAME, a precharge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI2 (-2V), as in "2-2-3. Third example of the driving method of the pixel circuit 181A."

[0237] During the initial period of the horizontal period HRP of the KthFRAME following the period PIP of the KthFRAME, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor, are the same as the configuration and operation described in "2-2-1. First example of the driving method for the pixel circuit 181A."

[0238] During the period PWR, similar to the configuration described in "2-2-2. Second Example of Method for Driving Pixel Circuit 181A", a data signal VDATA (voltage VSIGH in the third example) is written to the pixel 180A (pixel circuit 181A).

[0239] Also, during the period PVH, similar to the configuration described in "2-2-2. Second example of driving method for pixel circuit 181A," the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (first electrode 692 of the capacitance element CS).

[0240] Furthermore, during the light emission period PEM of KthFRAME, similar to the configuration described in "2-2-2. Second example of the driving method for pixel circuit 181A", white is produced by three pixels using pixel 180A that emits red light, pixel 180A that emits blue light, and pixel 180A that emits green light.

[0241] 3. Third Embodiment An overview of the display device according to the third embodiment will be described with reference to Fig. 1 and Fig. 21 to Fig. 27. Fig. 21 is a schematic diagram showing an input signal to a pixel 180B (pixel circuit 181B) according to the third embodiment, Fig. 22 is a circuit diagram showing the configuration of the pixel circuit 181B, and Fig. 23 to Fig. 27 are timing charts of the display device according to the third embodiment.

[0242] The display device according to the third embodiment includes a pixel 180B and a pixel circuit 181B. Specifically, the pixel 180B and the pixel circuit 181B include the configurations shown in the following (1) to (5). Mainly, the configurations shown in (1) to (5) are different from the configurations of the pixel 180 and the pixel circuit 181 of the display device 10 according to the first embodiment.

[0243] (1) Includes the fourth scan signal SC4(n-1) and the fifth scan signal SC4. (2) The fourth scan signal SC4(n-1) is a signal that replaces the fourth scan signal SC4(n) supplied to the pixel circuit 181, and the fifth scan signal SC4 is a signal that replaces the fifth scan signal SC5(n) supplied to the pixel circuit 181. (3) The fourth scan signal SC4(n) is a signal obtained by shifting the fourth scan signal SC4(n-1) within the shift register circuit 130 and the scan driver circuit 160 using a plurality of output signals and a plurality of enable signals output by the shift register circuit 130. (4) The timing of the fourth scan signal SC4(n-1) and the fifth scan signal SC4(n) is different from the timing of the fourth scan signal SC4(n) and the fifth scan signal SC5(n) supplied to the pixel circuit 181. (5) The fifth scan signal SC4(n) and the scan signal line 334 to which the fifth scan signal SC4(n) is supplied are so-called scan signals and scan signal lines.

[0244] The configurations of the pixel 180B and the pixel circuit 181B shown in (1) to (5) and the configurations of the pixel 180B and the pixel circuit 181B related to the configurations shown in (1) to (5) are the same as those of the display device 10 according to the first embodiment. Therefore, differences from the display device 10 according to the first embodiment will be mainly described here. In describing the configuration and functions of the display device according to the third embodiment, configurations and functions that are the same as those of the display device 10 according to the first embodiment and the display device according to the second embodiment will be described as necessary. Furthermore, configurations that are the same as or similar to those in FIGS. 1 to 12 will be described as necessary.

[0245] <3-1. Configuration of pixel 180B> The pixel 180B and pixel circuit 181B will be outlined with reference to FIGS.

[0246] As described above, pixel 180B and pixel circuit 181B are configured such that the fourth scan signal SC4(n) supplied to pixel circuit 181 is replaced with the fourth scan signal SC4(n-1), and the fifth scan signal SC5(n) supplied to pixel circuit 181 is replaced with the fifth scan signal SC4(n).

[0247] The gate electrode 612 of the first transistor T1 is electrically connected to the scan signal line 334 to which a fifth scan signal SC4(n) is supplied. The switching of the first transistor T1 of the pixel 180B and the pixel circuit 181B is controlled using the fifth scan signal SC4(n). In other words, the conductive state (on state) and non-conductive state (off state) of the first transistor T1 are controlled by the fifth scan signal SC4(n). When the signal supplied to the fifth scan signal SC4(n) is LO, the first transistor T1 is in a non-conductive state. When the signal supplied to the fifth scan signal SC4(n) is HI, the first transistor T1 is in a conductive state.

[0248] The gate electrode 662 of the sixth transistor T6 is electrically connected to the scan signal line 333 to which the fourth scan signal SC4(n-1) is supplied. The sixth transistor T6 has its switching controlled using the fourth scan signal SC4(n-1). In other words, the sixth transistor T6 has its conductive state (ON state) and non-conductive state (OFF state) controlled by the fourth scan signal SC4(n-1). When the signal supplied to the fourth scan signal SC4(n-1) is LO, the first transistor T1 is non-conductive. When the signal supplied to the fourth scan signal SC4(n-1) is HI, the first transistor T1 is conductive.

[0249] The configuration and functions of the pixel circuit 181B other than those described in "3-1. Configuration of the pixel 180B" are the same as those of the pixel circuit 181.

[0250] <3-2. Driving method of pixel circuit 181B> A method for driving a display device according to the third embodiment will be described with reference to Figures 23 to 26. Configurations that are the same as or similar to those in Figures 1 to 22 will be described as necessary. As in the first embodiment, the horizontal axis of the timing chart represents time.

[0251] As described above, the timing of the fourth scan signal SC4(n-1) and the fifth scan signal SC4(n) in the display device according to the third embodiment is different from the timing of the fourth scan signal SC4(n) and the fifth scan signal SC4(n) in the display device according to the second embodiment. The configuration and functions other than the timing of the fourth scan signal SC4(n-1) and the fifth scan signal SC4(n) in the third embodiment are the same as those in the driving method of the display device 10 according to the first embodiment.

[0252] As shown in Fig. 23, the method for driving the display device according to the third embodiment differs from the method for driving the display device 10 according to the first embodiment shown in Fig. 4 in that it includes the execution of a period PVH after a period PWR. The configuration of each period shown in Fig. 23 other than that is the same as the configuration described in "1-5. Method for driving the display device 10" with reference to Fig. 4. Note that the horizontal period HRP includes a period PWR and a period PVH.

[0253] During one horizontal period (horizontal period HRP) in the driving method of the display device according to the third embodiment, the pixel 180B (pixel circuit 181B) receives the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n-1), the fifth scan signal SC4(n), the image data signal SL(m), the initialization voltage VINI, the reference voltage VREF, and the precharge voltage VPRC. For example, the pixel 180B (pixel circuit 181B) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n-1), and the fifth scan signal SC4(n). The image data signal SL(m), the initialization voltage VINI, the reference voltage VREF, and the precharge voltage VPRC are input to the selected pixel 180B (pixel circuit 181B) according to the timing of each signal. A similar operation is performed for all pixels 180B (pixel circuits 181B), and based on the image data signals SL(m) input to all pixels 180B (pixel circuits 181B), an image of the frame corresponding to one frame is displayed in the display area 22 of the display device 10.

[0254] For example, Table 3 shows the voltages (potentials) supplied to each signal in each period of each frame in the timing charts shown in FIGS.

[0255] [Table 3]

[0256] For example, as shown in Table 3, the initialization voltage VINI is −1.5 V and the voltage VL(LO) is −3.5 V. The setting values ​​of the other voltages are the same as the setting values ​​shown in Table 1 described in “1-5. Method of driving the display device 10.”

[0257] <3-2-1. First Example of Method for Driving Pixel Circuit 181B> A first example of a method for driving the pixel circuit 181B will be described with reference to Fig. 24. The first example of the method for driving the pixel circuit 181B includes displaying images of different colors in successive frames, similar to the first example of the method for driving the display device according to the second embodiment. Configurations that are the same as or similar to those in Figs. 1 to 23 will be described as necessary.

[0258] During the light emission period PEM of the K-1st FRAME, the voltages and timings supplied to the image data signal SL(m), the first scan signal SC1(n), the second scan signal SC2(n), and the third scan signal SC3(n) are the same as those in "1-5-1. First example of the method for driving the display device 10." In addition, the fourth scan signal SC4(n-1) and the fifth scan signal SC4(n) are supplied with LO.

[0259] Therefore, during the light emission period PEM of the K-1st FRAME, the states of each of the first transistor T1 to the sixth transistor T6 and the voltages supplied to each of the first node N1 to the third node N3 are the same as the states and voltages in "1-5-1. First example of the method for driving the display device 10."

[0260] As a result, the second transistor T2 can pass a current Ion based on the potential difference Vgs and the potential difference Vds according to the voltage VSIGH input during the horizontal period HRP of the (K-1st) frame. Also, the current Ion flows from the driving power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, causing the light-emitting element OLED to emit light.

[0261] During the period PIP of the Kth FRAME following the light emission period PEM of the K-1st FRAME, the voltages and timings of the image data signal SL(m), the first scan signal SC1(n), the second scan signal SC2(n), and the third scan signal SC3(n) are the same as those in "1-5-1. First Example of the Driving Method of the Display Device 10." Furthermore, when the third scan signal SC3(n) is supplied with LO, the fourth scan signal SC4(n-1) changes from being supplied with LO to being supplied with HI. The fifth scan signal SC4(n) maintains its LO state.

[0262] Therefore, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 change from an off state to an on state, the third transistor T3 changes from an on state to an off state, the second transistor T2 maintains its on state, and the first transistor T1 maintains its off state. As a result, the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage Vnd (pre-charge voltage VPRC, 1.5V) and reaches voltage Vnd. The voltage supplied to the second node N2 gradually drops from voltage Vna toward 0V (reference voltage VREF) and reaches 0V. Furthermore, the voltage supplied to the third node N3 gradually drops from voltage Vnb toward voltage Vnn (initialization voltage VINI, −1.5V) and reaches voltage Vnn. Because the second transistor T2 and the fifth transistor T5 are on and a current flows from the drive power supply line PVDD to the initialization voltage power supply line SVI, the light-emitting element OLED does not emit light.

[0263] At the end of the period PIP of the Kth FRAME, the voltages and timings of the image data signal SL(m), first scan signal SC1(n), second scan signal SC2(n), third scan signal SC3(n), and fifth scan signal SC4(n) are the same as those of the period PIP of the Kth FRAME following the light emission period PEM of the (K-1st) FRAME. The fourth scan signal SC4(n-1) changes from a state in which HI is supplied to a state in which LO is supplied.

[0264] Therefore, the sixth transistor T6 changes from an ON state to an OFF state, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 maintain their ON states, and the first transistor T1 and the third transistor T3 maintain their OFF states. As a result, the voltage supplied to the first node N1 maintains the voltage Vnd, the voltage supplied to the second node N2 maintains 0 V, and the voltage supplied to the third node N3 maintains the voltage Vnn. Because the second transistor T2 and the fifth transistor T5 are ON and a current flows from the driving power line PVDD to the initialization voltage power line SVI, the light-emitting element OLED does not emit light.

[0265] In this way, during the period PIP of KthFRAME, a precharge voltage (intermediate potential) is supplied to the first node N1, the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI (-1.5V).

[0266] During the KthFRAME period PWR following the KthFRAME period PIP, the image data signal SL(m) is supplied with the data signal VDATA (-0.5V) of the voltage VSIGL input to the selected pixel 180B (pixel circuit 181B), the second scan signal SC2(n) and the third scan signal SC3(n) maintain a HI state, the first scan signal SC1(n) and the fourth scan signal SC4(n-1) maintain a LO state, and the fifth scan signal SC4(n) changes from a LO state to a HI state.

[0267] Therefore, the first transistor T1 changes from an off state to an on state, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 maintain their on states, and the third transistor T2 and the sixth transistor T6 maintain their off states.

[0268] As a result, the voltage supplied to the first node N1 gradually drops from voltage Vnd toward voltage Vnf (voltage VSIGL, -0.5V) and reaches voltage Vnf, the voltage supplied to the second node N2 remains at 0V, and the voltage supplied to the third node N3 remains at voltage Vnn. The potential difference Vgs is 1.5V (0-(-1.5V)). As in the period PIP, the potential difference Vgs is greater than the threshold voltage VTH, the second transistor T2 and the fifth transistor T5 are in the on state, and a current flows from the driving power line PVDD to the initialization voltage power line SVI, so the light-emitting element OLED does not emit light.

[0269] In this manner, during the period PWR of KthFRAME, the data signal VDATA (here, the voltage VSIGL) is written to the pixel 180B (pixel circuit 181B).

[0270] During the KthFRAME period PVH following the KthFRAME period PWR, the image data signal SL(m) maintains the state in which the data signal VDATA of the voltage VSIGL is supplied, the second scan signal SC2(n) and the fifth scan signal SC4(n) maintain the state in which HI is supplied, the first scan signal SC1(n) and the fourth scan signal SC4(n-1) maintain the state in which LO is supplied, and the third scan signal SC3(n) changes from the state in which HI is supplied to the state in which LO is supplied.

[0271] Therefore, the fifth transistor T5 changes from an ON state to an OFF state, the first transistor T1 and the fourth transistor T4 remain ON, and the third transistor T2 and the sixth transistor T6 remain OFF. With the fifth transistor T5 OFF, the node N3 is released, and the second transistor T2 remains ON, as it was during the KthFRAME period PWR. Therefore, a current Ion flows from the drive power supply line PVDD (the second electrode 626 side) to the third node N3 (the first electrode 624 side), and the voltage supplied to the third node N3 gradually rises from voltage Vnn. When the potential difference Vgs reaches the threshold voltage VTH, the second transistor T2 changes from an ON state to an OFF state, and the current Ion stops flowing. At this time, the voltage supplied to the third node N3 rises from voltage Vnn (-1.5V) to voltage Vne (-1V), and the potential difference Vgs is equal to the threshold voltage VTH (1V).

[0272] That is, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS). Also, since the second transistor T2 is in the off state, the current Ion does not flow from the drive power supply line PVDD to the reference voltage line PVSS, and therefore the light-emitting element OLED does not emit light.

[0273] At the end of the period PVH, the image data signal SL(m) maintains the state in which the data signal VDATA of the voltage VSIGL is supplied, and the third scan signal SC3(n) and the fourth scan signal SC4(n-1) maintain the state in which LO is supplied. The fifth scan signal SC4(n) changes from a state in which HI is supplied to a state in which LO is supplied. When the fifth scan signal SC4(n) changes to a state in which LO is supplied, the second scan signal SC2(n) changes from a state in which HI is supplied to a state in which LO is supplied. When the second scan signal SC2(n) changes to a state in which LO is supplied, the first scan signal SC1(n) changes from a state in which LO is supplied to a state in which HI is supplied.

[0274] Therefore, the third transistor changes from an off state to an on state, the first transistor T1 and the fourth transistor change from an on state to an off state, and the second transistor T2, the fifth transistor T5 and the sixth transistor T6 remain in the off state.

[0275] As a result, the first node N1 becomes conductive with the second node N2, the voltage supplied to the second node N2 gradually drops toward voltage Vnf and reaches voltage Vnf, the voltage supplied to the first node N1 maintains voltage Vnf, and the voltage supplied to the third node N3 maintains voltage Vne. Note that the potential difference Vgs is voltage Vnf-voltage Vne, which is smaller than the threshold voltage VTH, so no current Ion flows from the driving power line PVDD to the reference voltage line PVSS. Therefore, the light-emitting element OLED does not emit light.

[0276] In this way, during the period PVH of KthFRAME, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitive element CS).

[0277] During the light emission period PEM of the Kth FRAME following the horizontal period HRP of the Kth FRAME, the image data signal SL(m) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180B (pixel circuit 181B). Also, the first scan signal SC1(n) maintains a state in which HI is supplied, and the second scan signal SC2(n) to the fifth scan signal SC4(n) maintain a state in which LO is supplied.

[0278] Therefore, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 remain in an off state, and the third transistor T3 remains in an on state. Because the second transistor T2 is in an off state and no current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS, the light-emitting element OLED does not emit light. As a result, for example, the pixel 180B (pixel circuit 181B) that emits red light turns black. Similarly to the pixel 180 that emits red light, the pixel 180 that emits blue light and the pixel 180 that emits green light also do not emit light, so the three pixels that use the pixel 180 that emits red light, the pixel 180 that emits blue light, and the pixel 180 that emits green light turn black.

[0279] The first example of the method for driving the pixel circuit 181B including the configuration described above can supply the data signal VDATA after supplying an intermediate potential to the first node N1.

[0280] Furthermore, the first example of the driving method for the pixel circuit 181B includes executing the period PVH after the period PWR. That is, charging of the third node N3 begins after the potential of the data voltage (first node N1) is determined, so that the third node N3 does not malfunction due to the influence of potential fluctuations of the data voltage (first node N1), and the initialization voltage VINI (Vnc) can be set shallow. As a result, power consumption can be further reduced.

[0281] Furthermore, the driving method of the pixel circuit 181B, like "1-5-1. First Example of the Driving Method of the Display Device 10," can increase the writing speed and increase the number of pixels that can be written in a time period in which the writing speed is shortened. As a result, a display device including the pixel circuit 181B can provide a high-resolution display device and a large-screen display device. Furthermore, a display device including the pixel circuit 181B can reduce (suppress) power consumption.

[0282] Furthermore, the fourth scan signal SC4(n-1) in a display device including the pixel circuit 181B is the signal before the fifth scan signal SC4(n) is shifted. That is, the fourth scan signal SC4(n-1) is a signal supplied to the pixel circuit 181B electrically connected to the row immediately preceding in the row direction. Therefore, a display device including the pixel circuit 181B can share a control signal in the row direction with an adjacent pixel. Therefore, for example, a display device including the pixel circuit 181B can simplify the configuration of the control circuit for generating the fourth scan signal SC4(n-1) and the fifth scan signal SC4(n).

[0283] <3-2-2. Second Example of Method for Driving Pixel Circuit 181B> A second example of a method for driving the pixel circuit 181B will be described with reference to Fig. 25. The driving method shown in the second example of the pixel circuit 181B includes displaying images of the same color (white) in consecutive frames, similar to the second example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 24 will be described as necessary.

[0284] The configuration of the first scan signal SC1(n) to the fifth scan signal SC4(n) is the same as the configuration described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light emission period PEM of the K-1st FRAME and the period PIP of the Kth FRAME are the same as the configuration described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B." Furthermore, the operation of each transistor during each period is the same as the configuration described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B." Therefore, configurations similar to those described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B" will be explained as necessary. In addition, the image data signal SL(m) is supplied with a data signal VDATA of VSIGH corresponding to white during the horizontal period HRP, and is supplied with a data signal VDATA similar to the configuration described in "3-2-1. First example of the driving method for pixel circuit 181B" during periods other than the horizontal period HRP.

[0285] In the light emitting period PEM of the K-1st FRAME, the light emitting element OLED emits light in the same manner as in the configuration described in "3-2-1. First example of the method for driving the pixel circuit 181B".

[0286] During the KthFRAME period PIP following the light-emitting period PEM of the K-1stFRAME, similar to the configuration described in "3-2-1. First Example of the Method for Driving Pixel Circuit 181B," the voltage supplied to the first node N1 becomes voltage Vnd, the voltage supplied to the second node N2 becomes reference voltage VREF (0V), and the voltage supplied to the third node N3 becomes voltage Vnn (initialization voltage VINI1, -1.5V). The potential difference Vgs becomes less than 1V, and the potential difference Vds becomes less than 9.5V. As a result, the light-emitting element OLED does not emit light.

[0287] As described above, during the period PIP, a precharge voltage (intermediate potential) is supplied to the first node N1, the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI (-1.5V).

[0288] In the period PWR following the period PIP, the voltage supplied to the first node N1 gradually rises from voltage Vnd toward voltage Vng (voltage VSIGH, 3.5 V), the voltage supplied to the second node N2 remains at 0 V, and the voltage supplied to the third node N3 remains at voltage Vnn. As a result, similar to the configuration described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B," the light-emitting element OLED does not emit light.

[0289] In this manner, during the period PWR, the data signal VDATA (here, the voltage VSIGH) is written to the pixel 180B (pixel circuit 181B).

[0290] During the period PVH following the period PWR, the voltage supplied to the first node N1 gradually increases from voltage Vnd to voltage Vng, and the voltage supplied to the second node N2 remains at 0 V. The voltage supplied to the third node N3 increases from voltage Vnn (−1.5 V) to voltage Vne (−1 V), similar to the configuration during the period PVH described in “3-2-1. First Example of the Driving Method of the Pixel Circuit 181B.” As a result, the potential difference Vgs is equal to the threshold voltage VTH (1 V). That is, during the period PVH, the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, thereby acquiring the threshold voltage VTH of the second transistor T2, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitor CS). Furthermore, because the second transistor T2 is in the off state, no current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS, and the light-emitting element OLED does not emit light.

[0291] At the end of the period PVH, the first node N1 becomes conductive with the second node N2, and the voltage supplied to the second node N2 gradually rises. As a result, the second transistor T2 becomes conductive, and a current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS. Therefore, the voltage supplied to the first node N1 and the voltage supplied to the third node N3 rise to follow the rise in the voltage supplied to the second node N2. Due to the rise in the voltage supplied to the third node N3, the voltage supplied to the first node N1 and the voltage supplied to the second node N2 further rise.

[0292] As a result, the voltage supplied to the first node N1 and the voltage supplied to the second node N2 rise to voltage Vna, and the voltage supplied to the third node N3 rises to voltage Vnb. The potential difference Vgs becomes 4.5 V (voltage Vna (7 V) - voltage Vnb (2.5 V)). The potential difference Vgs is larger than the threshold voltage VTH, the second transistor T2 is in the on state, a current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS, and the light-emitting element OLED emits light. For example, the pixel 180 (pixel circuit 181) emits red light, and three pixels, one for emitting red light, one for emitting blue light, and one for emitting green light, emit white light.

[0293] <3-2-3. Third Example of Method for Driving Pixel Circuit 181B> A third example of a method for driving the pixel circuit 181B will be described with reference to Fig. 26. The third example of a method for driving the pixel circuit 181B includes displaying images of the same color (black) in consecutive frames, similar to the third example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 25 will be described as necessary.

[0294] The configuration of the first scan signal SC1(n) to the fifth scan signal SC4(n) is the same as the configuration described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light-emitting period PEM of the K-1st FRAME are the same as the configuration described in "1-5-3. Third Example of Method for Driving Display Device 10." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the period PVH of the Kth FRAME to the light-emitting period PEM are the same as the configuration described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B." Furthermore, the operation of each transistor during each period is the same as the configuration described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B." Therefore, the configuration described in "1-5-3. Third example of the method for driving the display device 10" and the configuration similar to that described in "3-2-1. First example of the method for driving the pixel circuit 181B" will be described as necessary. Note that, for the image data signal SL(m), the data signal VDATA of VSIGL corresponding to black is supplied during the horizontal period HRP, and the data signal VDATA similar to the configuration described in "3-2-1. First example of the method for driving the pixel circuit 181B" is supplied during periods other than the horizontal period HRP.

[0295] During the light emission period PEM of the K-1st FRAME, similar to the configuration described in "1-5-3. Third example of the method for driving the display device 10", the light emitting element OLED does not emit light and the pixel 180B (pixel circuit 181B) turns black.

[0296] During the Kth FRAME period PIP following the light-emitting period PEM of the K-1st FRAME, the voltage supplied to the first node N1 gradually increases from voltage Vnf toward the precharge voltage VPRC (voltage Vnd, 1.5V) and reaches voltage Vnd. The voltage supplied to the second node N2 gradually decreases from voltage Vnf toward 0V (reference voltage VREF) and reaches 0V. The voltage supplied to the third node N3 gradually decreases from voltage Vne toward Vnn (initialization voltage VINI, −1.5V) and reaches −1.5V. Although the potential difference VTH is 1.5V, as in the configuration described in “1-5-3. Third Example of the Driving Method of the Display Device 10,” the second transistor T2 and the fifth transistor T5 are in the on state, and a current flows from the drive power supply line PVDD to the initialization voltage power supply line SVI, so the light-emitting element OLED does not emit light.

[0297] As described above, during the period PIP, a precharge voltage (intermediate potential) is supplied to the first node N1, the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI (-1.5V).

[0298] During the period PWR following the period PIP, a data signal VDATA (voltage VSIGL in the third example) is written to the pixel 180B (pixel circuit 181B) in the same manner as in the configuration described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B." Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation in which the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (first electrode 692 of the capacitance element CS).

[0299] Furthermore, during the light emission period PEM of KthFRAME, similar to the configuration described in "3-2-1. First example of driving method for pixel circuit 181B", three pixels, using pixel 180B that emits red light, pixel 180B that emits blue light, and pixel 180B that emits green light, produce black.

[0300] <3-2-4. Fourth Example of Method for Driving Pixel Circuit 181B> A fourth example of a method for driving the pixel circuit 181B will be described with reference to Fig. 27. The fourth example of the method for driving the pixel circuit 181B includes displaying images of different colors in successive frames, similar to the fourth example of the method for driving the display device according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 26 will be described as necessary.

[0301] The configuration of the first scan signal SC1(n) to the fifth scan signal SC4(n) is the same as the configuration described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light-emitting period PEM of the K-1st FRAME and the period PIP of the Kth FRAME are the same as the configuration described in "3-2-3. Third Example of the Method for Driving the Pixel Circuit 181B." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the period PVH of the Kth FRAME to the light-emitting period PEM are the same as the configuration described in "3-2-2. Second Example of the Method for Driving the Pixel Circuit 181B." Furthermore, the operation of each transistor during each period is the same as the configuration described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B." Therefore, configurations similar to those described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B" to "3-2-3. Third Example of Method for Driving Pixel Circuit 181B" will be described as necessary. Note that, for the image data signal SL(m), a data signal VDATA of VSIGH corresponding to white is supplied during the horizontal period HRP, and a data signal VDATA similar to the configuration described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B" is supplied during periods other than the horizontal period HRP.

[0302] In the light emission period PEM of the (K-1st) frame, the pixel 180B (pixel circuit 181B) turns black, as in "3-2-3. Third example of the method for driving the pixel circuit 181B."

[0303] During the period PIP, as in "3-2-3. Third example of driving method for pixel circuit 181B," a precharge voltage (intermediate potential) is supplied to the first node N1, the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI (-1.5V).

[0304] During the period PWR, as in "3-2-2. Second Example of Method for Driving Pixel Circuit 181B," a data signal VDATA (voltage VSIGH in the fourth example) is written to the pixel 180B (pixel circuit 181B). Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation in which the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (first electrode 692 of the capacitance element CS).

[0305] Furthermore, during the light emission period PEM of KthFRAME, as in "3-2-2. Second example of driving method for pixel circuit 181B", white light is emitted by three pixels using pixel 180B that emits red light, pixel 180B that emits blue light, and pixel 180B that emits green light.

[0306] 4. Fourth Embodiment An overview of a display device according to the fourth embodiment will be described with reference to Fig. 1, Fig. 23, and Fig. 28 to Fig. 34. Fig. 28 is a schematic diagram showing an input signal to a pixel 180C (pixel circuit 181C) according to the fourth embodiment, Fig. 29 is a circuit diagram showing the configuration of the pixel circuit 181C, and Figs. 30 to 33 are timing charts of the display device according to the fourth embodiment. Fig. 34 is a diagram for explaining the setting of an input signal according to the fourth embodiment of the present invention.

[0307] The display device according to the fourth embodiment includes a pixel 180C and a pixel circuit 181C. Specifically, the pixel 180C and the pixel circuit 181C include the configurations shown in the following (1) to (3). The configurations shown in (1) to (3) are mainly different from the configurations of the pixel 180B and the pixel circuit 181B of the display device according to the third embodiment.

[0308] (1) The scan voltage power supply line SVIR to which the scan voltage power supply SIR(n) is supplied is included. (2) The scan voltage power supply line SVIR is a common signal line that serves as both the reference voltage power supply line SVR to which the reference voltage power supply VREF is supplied and the initialization voltage power supply line SVI to which the initialization voltage VINI is supplied. That is, the scan voltage power supply line SVIR has a configuration that serves as both the reference voltage power supply line SVR and the initialization voltage power supply line SVI. (3) The scan voltage power supply SIR(n) includes a voltage that alternates with time, which is an initialization voltage VINI2 and an initialization voltage VINI1.

[0309] The configuration of the pixel 180C and the pixel circuit 181C other than those shown in (1) to (3) and those related to those shown in (1) to (3) are the same as those of the display device according to the third embodiment. Furthermore, the configuration and functions related to the scan voltage power supply line SVIR and the scan voltage power supply SIR(n) are the same as those of the scan voltage power supply line SVIR and the scan voltage power supply SIR(n) described in "2. Second Embodiment." Therefore, differences from the display device according to the second embodiment and the display device according to the third embodiment will be mainly described here. In describing the configuration and functions of the display device according to the fourth embodiment, configurations and functions similar to those of the display device according to the second embodiment and the display device according to the third embodiment will be described as needed. Furthermore, configurations that are the same as or similar to those in FIGS. 1 to 27 will be described as needed.

[0310] <4-1. Configuration of pixel 180C> The pixel 180C and pixel circuit 181C will be outlined with reference to FIGS.

[0311] The pixel circuit 181C is connected to a scan voltage power supply line SVIR to which a scan voltage power supply SIR(n) is supplied. In the pixel circuit 181C, a first electrode 644 of the fourth transistor T4 and a first electrode 654 of the fifth transistor T5 are electrically connected to the scan voltage power supply line SVIR. The configuration and functions, including the electrical connections of the scan voltage power supply line SVIR, the scan voltage power supply SIR(n), the fourth transistor T4, and the fifth transistor T5, are the same as those of the display device according to the second embodiment.

[0312] The configuration and functions of the pixel circuit 181C other than those described in "4-1. Configuration of pixel 180C" are the same as those of the display device according to the second embodiment (pixel circuit 181A) and the display device according to the third embodiment (pixel circuit 181B).

[0313] <4-2. Driving method of pixel circuit 181C> A method for driving a display device according to the fourth embodiment will be described with reference to Figures 30 to 33. Configurations that are the same as or similar to those in Figures 1 to 29 will be described as necessary. As in the first embodiment, the horizontal axis of the timing chart represents time.

[0314] The method for driving the display device according to the fourth embodiment differs from the method for driving the display device according to the third embodiment in the configuration related to the configurations shown in (1) to (3) described in "4-1. Configuration of pixel 180C." The configurations and functions other than the configuration related to (1) to (3) described in "4-1. Configuration of pixel 180C" are the same as those of the method for driving the display device according to the third embodiment. Furthermore, as described in "4-1. Configuration of pixel 180C," the configurations and functions related to the scan voltage power supply line SVIR and the scan voltage power supply SIR(n) are the same as those of the display device according to the second embodiment.

[0315] The method for driving a display device according to the fourth embodiment includes the same period as the method for driving a display device according to the third embodiment shown in FIG.

[0316] In one horizontal period (horizontal period HRP) in the driving method of the display device according to the fourth embodiment, the pixel 180C (pixel circuit 181C) receives the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n-1), the fifth scan signal SC4(n), the image data signal SL(m), the scan voltage power supply SIR(n), and the precharge voltage VPRC. For example, the pixel 180C (pixel circuit 181C) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n-1), the fifth scan signal SC4(n), and the scan voltage power supply SIR(n). The image data signal SL(m), the scan voltage power supply SIR(n), and the precharge voltage VPRC are input to the selected pixel 180C (pixel circuit 181C) in accordance with the timing of each signal. Similar operations are performed for all pixels 180C (pixel circuits 181C), and an image of the frame corresponding to one frame is displayed in the display area 22 of the display device 10 based on the image data signal SL(m) input to all pixels 180C (pixel circuits 181C).

[0317] For example, the voltages (potentials) supplied to the signals in each frame in the timing charts shown in FIGS.

[0318] [Table 4]

[0319] For example, as shown in Table 4, the initialization voltage VINI2 is 0 V, and the initialization voltage VINI1 is −1.5 V. The initialization voltage VINI2 is the same as the reference voltage VREF in the driving method of pixel circuit 181B, and the initialization voltage VINI1 is the same as the initialization voltage VINI in the driving method of pixel circuit 181B. The setting values ​​of the other voltages are the setting values ​​shown in Table 3 described in "3-2. Driving method of pixel circuit 181B."

[0320] <4-2-1. First Example of Method for Driving Pixel Circuit 181C> A first example of a method for driving the pixel circuit 181C will be described with reference to Fig. 30. The first example of the method for driving the pixel circuit 181C includes displaying images of different colors in successive frames, similar to the first example of the method for driving the pixel circuit 181B according to the third embodiment. Configurations that are the same as or similar to those in Figs. 1 to 29 will be described as necessary.

[0321] As explained in "2-2-1. First example of the driving method for pixel circuit 181A," the scan voltage power supply SIR(n) supplies the initialization voltage VINI2 during the light emission period PEM of the K-1stFRAME, supplies the initialization voltage VINI1 during the period PIP of the KthFRAME, and supplies the initialization voltage VINI2 during the period PVH of the KthFRAME and the light emission period PEM.

[0322] The configurations of the first scan signal SC1(n) to the fifth scan signal SC4(n) are the same as those described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B." Furthermore, the operation of each transistor in each period is the same as that described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B." Therefore, configurations similar to those described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B" will be described as necessary.

[0323] In the light emitting period PEM of the K-1st FRAME, the light emitting element OLED emits light in the same manner as in the configuration described in "3-2-1. First example of the method for driving the pixel circuit 181B".

[0324] During the period between the light-emitting period PEM of the (K-1st) FRAME and the period PIP, the scan voltage power supply SIR(n) changes from a state in which 0 V (initialization voltage VINI2) is supplied to a state in which voltage Vnn (initialization voltage VINI1, -1.5 V) is supplied. As a result, the voltage supplied to the second node N2 gradually drops from voltage Vna toward voltage Vnn (initialization voltage VINI1, -1.5 V), the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage Vnd (pre-charge voltage VPRC, 1.5 V), and the voltage supplied to the third node N3 maintains voltage Vnb.

[0325] During the period PIP following the period between the light-emitting period PEM and the period PIP of the (K-1st) frame, the scan voltage power supply SIR(n) maintains a state in which voltage Vnn (initialization voltage VINI1, -1.5V) is supplied. The voltage supplied to the first node N1 gradually drops from voltage Vna to voltage Vnd and becomes voltage Vnd. The voltage supplied to the second node N2 gradually drops from voltage Vna to voltage Vnn and becomes voltage Vnn. The voltage supplied to the third node N3 gradually drops from voltage Vnb to voltage Vnn and becomes voltage Vnn. The potential difference Vgs becomes 0V (-1.5V - -1.5V), and the potential difference Vds becomes 9.5V (8V - -1.5V). Because the potential difference Vgs is smaller than the threshold voltage VTH, the second transistor T2 is in an off state, and the current Ion does not flow from the driving power supply line PVDD to the scan voltage power supply line SVIR or the reference voltage line PVSS, so the light-emitting element OLED does not emit light.

[0326] Furthermore, during the final period of the KthFRAME period PIP, the scan voltage power supply SIR(n) maintains a state in which voltage Vnn (initialization voltage VINI1, -1.5V) is supplied. The voltage supplied to the first node N1 maintains voltage Vnd, the voltage supplied to the second node N2 maintains -1.5V (Vnn), and the voltage supplied to the third node N3 maintains voltage Vnn. Since the second transistor T2 is in an off state and no current flows from the driving power supply line PVDD to the reference voltage line PVSS, the light-emitting element OLED does not emit light.

[0327] As described above, during the period PIP of KthFRAME, the precharge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI (-1.5V).

[0328] During the period PWR of the KthFRAME following the period PIP of the KthFRAME, the scan voltage power supply SIR(n) maintains a state in which voltage Vnn (initialization voltage VINI1, -1.5V) is supplied. The voltage supplied to the first node N1 gradually drops from voltage Vnd toward voltage VSIGL (voltage Vnf, -0.5V), and the voltages supplied to the second node N2 and the third node N3 maintain Vnn (-1.5V). Also, similar to the period PIP, the light-emitting element OLED does not emit light.

[0329] In this manner, during the period PWR of KthFRAME, the data signal VDATA (here, the voltage VSIGL) is written to the pixel 180B (pixel circuit 181B).

[0330] During the KthFRAME period PVH following the KthFRAME period PWR, the image data signal SL(m) maintains a state in which the data signal VDATA of voltage VSIGL is supplied, and the scan voltage power supply SIR(n) changes from a state in which the initialization voltage VINI1 (-1.5V) is supplied to a state in which the initialization voltage VINI2 (0V) is supplied. The voltage supplied to the second node N2 increases from Vnn (-1.5V) toward VINI2 (0V), and when this voltage exceeds the threshold voltage VTH of the second transistor T2, the second transistor T2 is turned on. When the fifth transistor T5 is turned off and the third node N3 is released, after the second transistor T2 is turned on, a current Ion flows from the drive power line PVDD (second electrode 626 side) to the third node N3 (first electrode 624 side), and the voltage supplied to the third node N3 gradually increases from voltage Vnn. When the potential difference Vgs becomes the threshold voltage VTH, the second transistor T2 changes from the ON state to the OFF state, and the current Ion stops flowing. At this time, the voltage supplied to the third node N3 increases from voltage Vnn (-1.5 V) to voltage Vne (-1 V), and the potential difference Vgs is equal to the threshold voltage VTH (1 V). That is, during the period PVH, the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, thereby acquiring the threshold voltage VTH of the second transistor T2, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitor CS). Furthermore, because the second transistor T2 is in the OFF state, the current Ion does not flow from the driving power supply line PVDD to the reference voltage line PVSS, and the light-emitting element OLED does not emit light.

[0331] At the end of the period PVH, the image data signal SL(m) maintains a state in which the data signal VDATA of voltage VSIGL is supplied, and the scan voltage power supply SIR(n) maintains a state in which the initialization voltage VINI2 (0V) is supplied. The first node N1 is electrically connected to the second node N2, the voltage supplied to the second node N2 becomes voltage Vnf, the voltage supplied to the first node N1 maintains voltage Vnf, and the voltage supplied to the third node N3 maintains voltage Vnn. Since the potential difference Vgs is voltage Vnf (-0.5V) - voltage Vne (-1V) and is lower than the threshold voltage VTH, no current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS. Therefore, the light-emitting element OLED does not emit light.

[0332] In this way, during the period PVH of KthFRAME, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitive element CS).

[0333] During the light emission period PEM of the KthFRAME following the horizontal period HRP of the KthFRAME, the display becomes black with three pixels, using pixel 180C that emits red light, pixel 180C that emits blue light, and pixel 180C that emits green light, similar to the configuration described in "3-2-1. First example of the driving method of pixel circuit 181B."

[0334] The first example of the method for driving the pixel circuit 181C including the configuration described above has the same effects as the method for driving the display device according to the third embodiment.

[0335] Furthermore, like the pixel circuit 181A according to the second embodiment, the pixel circuit 181C includes a scan voltage power supply line SVIR that doubles as the reference voltage power supply line SVR and the initialization voltage power supply line SVI that were supplied to the pixel circuit 181. Thus, the pixel circuit 181C has a configuration that allows the number of signal lines to be reduced, and a display device including the pixel circuit 181C can reduce the pixel size. As a result, a display device including the pixel circuit 181C can increase the number of pixels, and can achieve higher resolution and a larger screen.

[0336] <4-2-2. Second Example of Method for Driving Pixel Circuit 181C> A second example of a method for driving the pixel circuit 181C will be described with reference to Fig. 31. The driving method shown in the second example of the pixel circuit 181C includes displaying images of the same color (white) in consecutive frames, similar to the second example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 30 will be described as necessary.

[0337] The configurations of the first scan signal SC1(n) to the fifth scan signal SC4(n) and the scan voltage power supply SIR(n) are the same as those described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C." Furthermore, the operation of each transistor in each period is the same as that described in "3-2-2. Second Example of the Method for Driving the Pixel Circuit 181B." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 in periods other than the horizontal period HRP of the KthFRAME and the light emission period PEM of the KthFRAME are the same as those described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C." Furthermore, the operation of each transistor in each period is the same as that described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C." Therefore, configurations similar to those described in "3-2-2. Second Example of Method for Driving Pixel Circuit 181B" and configurations similar to those described in "4-2-1. First Example of Method for Driving Pixel Circuit 181C" will be described as necessary. Note that, for the image data signal SL(m), a data signal VDATA of VSIGH corresponding to white is supplied during the horizontal period HRP, and a data signal VDATA similar to the configuration described in "4-2-1. First Example of Method for Driving Pixel Circuit 181C" is supplied during periods other than the horizontal period HRP.

[0338] The driving method of the second example of the driving method for pixel circuit 181C during the light-emitting period PEM of K-1stFRAME, the period between the light-emitting period PEM of K-1stFRAME following the light-emitting period PEM of K-1stFRAME and the period PIP of KthFRAME, and the period PIP of KthFRAME is the same as the driving method described in "4-2-1. First example of the driving method for pixel circuit 181C."

[0339] During the period PWR of the KthFRAME following the period PIP of the KthFRAME, the voltage supplied to the first node N1 gradually increases from voltage Vnd toward voltage Vng (voltage VSIGH, 3.5V), the voltage supplied to the second node N2 gradually increases from voltage Vnn (initialization voltage VINI1, -1.5V) toward 0V (initialization voltage VINI2), and the voltage supplied to the third node N3 gradually increases from voltage Vnn (initialization voltage VINI1, -1.5V) toward voltage Vne (-1V). Also, similar to the period PIP, the light-emitting element OLED does not emit light.

[0340] In this manner, during the period PWR of KthFRAME, the data signal VDATA (here, the voltage VSIGH) is written to the pixel 180B (pixel circuit 181B).

[0341] During the light-emitting period of the KthFRAME period PVH to KthFRAME following the KthFRAME period PWR, similar to the configuration during the light-emitting period of the KthFRAME period PVHPVH to KthFRAME described in "3-2-2. Second Example of Driving Method of Pixel Circuit 181B," the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and after a charge equivalent to the threshold voltage VTH is held at the third node N3 (first electrode 692 of the capacitive element CS), the voltage supplied to the first node N1 and the voltage supplied to the second node N2 rises to voltage Vna, and the voltage supplied to the third node N3 rises to voltage Vnb. The potential difference Vgs is greater than the threshold voltage VTH, the second transistor T2 is on, and a current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, pixel 180 (pixel circuit 181) emits red light, and three pixels, one for emitting red light, one for emitting blue light, and one for emitting green light, emit white light.

[0342] <4-2-3. Third Example of Driving Method of Pixel Circuit 181C> A third example of a method for driving the pixel circuit 181C will be described with reference to Fig. 32. The third example of the method for driving the pixel circuit 181C includes displaying images of the same color (black) in consecutive frames, similar to the third example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 31 will be described as necessary.

[0343] The configurations of the first scan signal SC1(n) to the fifth scan signal SC4(n) and the scan voltage power supply SIR(n) are the same as those described in "4-2-1. First Example of Method for Driving Pixel Circuit 181C." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during periods other than the KthFRAME period PIP, and the operation of each transistor during each period, are the same as those described in "3-2-3. Third Example of Method for Driving Pixel Circuit 181B." Therefore, configurations similar to those described in "3-2-3. Third Example of Method for Driving Pixel Circuit 181B" and "4-2-1. First Example of Method for Driving Pixel Circuit 181C" will be described as necessary. In addition, the image data signal SL(m) is supplied with the data signal VDATA of VSIGL corresponding to black during the horizontal period HRP, and is supplied with the data signal VDATA similar to the configuration described in "4-2-1. First example of the driving method of the pixel circuit 181C" during periods other than the horizontal period HRP.

[0344] During the light emission period PEM of the K-1st FRAME, similar to the configuration described in "3-2-3. Third example of the method for driving the pixel circuit 181B", the light emitting element OLED does not emit light and the pixel 180C (pixel circuit 181C) turns black.

[0345] During the period between the light-emitting period PEM of the K-1st FRAME and the period PIP of the Kth FRAME following the light-emitting period PEM of the K-1st FRAME, the voltage supplied to the first node N1 gradually rises from voltage Vnf toward voltage Vnd (pre-charge voltage VPRC, 1.5V), the voltage supplied to the second node N2 gradually drops from voltage Vnf toward the initialization voltage VINI1 (Vnn, -1.5V), and the voltage supplied to the third node N3 gradually drops from voltage Vne toward the initialization voltage VINI1 (Vnn, -1.5V). In addition, the light-emitting element OLED does not emit light.

[0346] During the period PIP of the Kth FRAME following the period between the light-emitting period PEM and the period PIP of the K-1st FRAME, the voltage supplied to the first node N1 gradually increases from voltage Vnf to voltage Vnd and becomes voltage Vnd (pre-charge voltage VPRC). The voltage supplied to the second node N2 gradually decreases from voltage Vnf to voltage Vnn and becomes voltage Vnn (initialization voltage VINI1). The voltage supplied to the third node N3 gradually decreases from voltage Vne to voltage Vnn and becomes voltage Vnn. The potential difference Vgs becomes 0V, and the potential difference Vds becomes 8V. The light-emitting element OLED does not emit light. As described above, during the period PIP, the pre-charge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-1.5V).

[0347] The KthFRAME period PWR, period PVH, and light-emitting period PEM following the KthFRAME period PIP are configured similarly to the configuration described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C." During the PWR period, a data signal VDATA (voltage VSIGL in the third example) is written to the pixel 180C (pixel circuit 181C). During the PVH period, the potential difference Vgs of the second transistor T2 is made equal to the threshold voltage VTH, thereby acquiring the threshold voltage VTH of the second transistor T2, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (first electrode 692 of the capacitor CS). During the light-emitting period PEM, three pixels, including the pixel 180C that emits red, the pixel 180C that emits blue, and the pixel 180C that emits green, are black.

[0348] <4-2-4. Fourth Example of Driving Method of Pixel Circuit 181C> A fourth example of a method for driving the pixel circuit 181C will be described with reference to Fig. 33. The fourth example of a method for driving the pixel circuit 181C includes displaying images of different colors in successive frames, similar to the fourth example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 32 will be described as necessary.

[0349] The configurations of the first scan signal SC1(n) to the fifth scan signal SC4(n) and the scan voltage power supply SIR(n) are the same as those described in "4-2-1. First Example of a Method for Driving a Pixel Circuit 181C." Furthermore, the voltages (potentials) of the nodes and the operation of the transistors during the light-emitting period PEM of the K-1st FRAME and the period PIP of the Kth FRAME are the same as those described in "4-2-3. Third Example of a Method for Driving a Pixel Circuit 181C." Furthermore, the voltages (potentials) of the nodes and the operation of the transistors during the horizontal period HRP (period PWR and period PVH) and light-emitting period PEM of the Kth FRAME are the same as those described in "4-2-2. Second Example of a Method for Driving a Pixel Circuit 181C." Therefore, configurations similar to those described in "4-2-1. First Example of a Method for Driving a Pixel Circuit 181C" to "4-2-3. Third Example of a Method for Driving a Pixel Circuit 181C" will be described as necessary. In addition, the image data signal SL(m) is supplied with a data signal VDATA of VSIGH corresponding to white during the horizontal period HRP, and is supplied with a data signal VDATA similar to the configuration described in "4-2-1. First example of the driving method of the pixel circuit 181C" during periods other than the horizontal period HRP.

[0350] In the light emission period PEM of the (K-1st) frame, the pixel 180 (pixel circuit 181) turns black, as in "4-2-3. Third example of the method for driving the pixel circuit 181C."

[0351] During the period between the light-emitting period PEM of the K-1st FRAME and the period PIP of the Kth FRAME following the light-emitting period PEM of the K-1st FRAME, the voltage supplied to the first node N1 gradually rises from voltage Vnf toward voltage Vnd (pre-charge voltage VPRC, 1.5V), the voltage supplied to the second node N2 gradually drops from voltage Vnf toward the initialization voltage VINI1 (Vnn, -1.5V), and the voltage supplied to the third node N3 gradually drops from voltage Vne toward the initialization voltage VINI1 (Vnn, -1.5V). In addition, the light-emitting element OLED does not emit light.

[0352] During the period PIP of the KthFRAME, which follows the period between the light emission period PEM of the K-1stFRAME and the period PIP of the KthFRAME, a precharge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-1.5V), as in "4-2-3. Third example of the driving method of the pixel circuit 181C."

[0353] During the period PWR following the period PIP of KthFRAME, a data signal VDATA (in the third example, voltage VSIGH) is written to pixel 180C (pixel circuit 181C), similar to the configuration described in "4-2-2. Second example of driving method for pixel circuit 181C."

[0354] During the period PVH following the period PWR of KthFRAME, similar to the configuration described in "4-2-2. Second example of driving method for pixel circuit 181C", the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (first electrode 692 of the capacitance element CS).

[0355] During the light emission period PEM of KthFRAME, similar to the configuration described in "4-2-2. Second example of driving method for pixel circuit 181C", white is produced by three pixels using pixel 180C that emits red light, pixel 180C that emits blue light, and pixel 180C that emits green light.

[0356] <4-3. Setting values ​​of initialization voltages VINI1 and VINI2> The set values ​​of the initialization voltages VINI1 and VINI2 will be described with reference to Fig. 34. Fig. 34 is a diagram for explaining the set values ​​of the initialization voltages VINI1 and VINI2 of the scan voltage power supply line SVIR to which the scan voltage power supply SIR(n) is supplied. Configurations that are the same as or similar to those in Figs. 1 to 33 will be described as necessary.

[0357] For example, as shown in FIG. 34, between the period PWR and the period PVH, in accordance with the timing of the second scan signal SC2(n), the scan voltage power supply SIR(n) changes from a state in which the initialization voltage VINI2 is supplied to a state in which the initialization voltage VINI1 is supplied.

[0358] During the period PWR, in the pixel circuit 181C, the scan voltage power supply SIR(n) (initialization voltage VINI1) is supplied from the scan voltage power supply line SVIR to the second node N2 and the third node N3, and the second node N2 and the third node N3 are initialized. The pixel 180C including the pixel circuit 181C does not emit light during the period PWR. The condition for the light-emitting element OLED not to emit light is that the initialization voltage VINI1 supplied to the third node N3 is smaller than the threshold voltage VTHEL of the light-emitting element OLED. In other words, the initialization voltage VINI1<threshold voltage VTHEL.

[0359] Furthermore, during the period PVH, the pixel circuit 181C corrects the threshold voltage VTH and holds a charge equivalent to the threshold voltage VTH. The pixel 180C including the pixel circuit 181C does not emit light during the period PVH. The condition for the light-emitting element OLED not to emit light is that the voltage Vne supplied to the third node N3 is smaller than the threshold voltage VTHEL of the light-emitting element OLED. In other words, the voltage Vne<the threshold voltage VTHEL.

[0360] Furthermore, for example, when the pixel circuit 181C emits light based on the voltage VSIGH corresponding to white, the second node N2 is supplied with the initialization voltage VINI2, and the third node N3 is supplied with the voltage Vne. The potential difference Vgs is the difference between the voltage supplied to the second node N2 and the voltage supplied to the third node N3, and the potential difference Vgs = initialization voltage VINI2 - voltage Vne. Furthermore, since the potential difference Vgs is equal to the threshold voltage VTH, the initialization voltage VINI2 - voltage Vne = threshold voltage VTH.

[0361] The condition for the initialization voltage VINI2 calculated using the above formula is initialization voltage VINI2<threshold voltage VTHEL+threshold voltage VTH, as shown in Fig. 34. Also, the condition for the initialization voltage VINI1 is initialization voltage VINI1<threshold voltage VTHEL.

[0362] 5. Fifth Embodiment An overview of a display device according to a fifth embodiment will be described with reference to Figs. 1, 4, and 35 to 40. Fig. 35 is a schematic diagram showing input signals to a pixel 180D (pixel circuit 181D) according to a fifth embodiment of the present invention. Fig. 36 is a circuit diagram showing the configuration of the pixel circuit 181D. Figs. 37 to 40 are timing charts of the display device according to the fifth embodiment of the present invention.

[0363] The display device according to the fifth embodiment includes a pixel 180D and a pixel circuit 181D. Specifically, the pixel 180D and the pixel circuit 181D include the configurations shown in (1) and (2) below. The configurations shown in (1) and (2) are mainly different from the configurations of the pixel 180 and the pixel circuit 181 of the display device 10 according to the first embodiment.

[0364] (1) The scan signal line 333 to which the pixel 180D is connected is a common signal line that combines the scan signal line 332 and the scan signal line 333 to which the pixel circuit 181 is connected. That is, the third scan signal SC3(n) supplied to the pixel 180D has a configuration that combines the third scan signal SC3(n) and the fourth scan signal SC3(n) supplied to the pixel circuit 181. (2) The voltage LO (LO) is −5.5V, and the initialization voltage VINI is −3.5V.

[0365] The configurations of the pixel 180D and the pixel circuit 181D shown in (1) and (2), and the configurations other than those related to the configurations of the pixel 180D and the pixel circuit 181D shown in (1) and (2), are the same as those of the display device 10 according to the first embodiment. Therefore, differences from the display device 10 according to the first embodiment will be mainly described here. In describing the configurations and functions of the display device according to the fifth embodiment, configurations and functions that are the same as those of the display device 10 according to the first embodiment will be described as necessary. Furthermore, configurations that are the same as or similar to those in FIGS. 1 to 34 will be described as necessary.

[0366] <5-1.Configuration of pixel 180D> The pixel 180D and pixel circuit 181D will be outlined with reference to FIGS.

[0367] In the pixel circuit 181A, the gate electrode 652 of the fifth transistor T5 and the gate electrode 662 of the sixth transistor T6 are electrically connected to a scan signal line 333 to which a fourth scan signal SC4(n) is supplied. The fifth transistor T5 and the sixth transistor T6 have their switching controlled using the fourth scan signal SC4(n). In other words, the fifth transistor T5 and the sixth transistor T6 have their conductive state (on state) and non-conductive state (off state) controlled by the fourth scan signal SC4(n). When the signal supplied to the fourth scan signal SC4(n) is LO, the fifth transistor T5 and the sixth transistor T6 are non-conductive. When the signal supplied to the fourth scan signal SC4(n) is HI, the fifth transistor T5 and the sixth transistor T6 are conductive.

[0368] The configuration and functions of the pixel circuit 181D other than those described in "5-1. Configuration of the pixel 180B" are the same as those of the pixel circuit 181.

[0369] <5-2. Driving method of pixel circuit 181D> A method for driving a display device according to the fifth embodiment will be described with reference to Figures 37 to 40. Configurations that are the same as or similar to those in Figures 1 to 36 will be described as necessary. As in the first embodiment, the horizontal axis of the timing chart represents time.

[0370] The method for driving the display device according to the fifth embodiment differs from the method for driving the display device 10 according to the first embodiment in the configuration related to the configurations shown in (1) and (2) described in "5-1. Configuration of pixel 180D." The configurations and functions other than the configuration related to (1) and (2) described in "5-1. Configuration of pixel 180D" are the same as those of the method for driving the display device 10 according to the first embodiment.

[0371] The method for driving the display device according to the fifth embodiment includes the same period as the method for driving the display device 10 according to the first embodiment shown in FIG.

[0372] In one horizontal period (horizontal period HRP) in the driving method of the display device according to the fifth embodiment, the pixel 180D (pixel circuit 181D) receives the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n), the fifth scan signal SC5(n), the image data signal SL(m), the initialization voltage VINI, the reference voltage VREF, and the precharge voltage VPRC. For example, the pixel 180D (pixel circuit 181D) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n), and the fifth scan signal SC5(n). The image data signal SL(m), the initialization voltage VINI, the reference voltage VREF, and the precharge voltage VPRC are input to the selected pixel 180D (pixel circuit 181D) according to the timing of each signal. A similar operation is performed for all pixels 180D (pixel circuits 181D), and based on the image data signals SL(m) input to all pixels 180D (pixel circuits 181D), the image of the frame corresponding to one frame is displayed in the display area 22 of the display device.

[0373] For example, Table 5 shows the voltages (potentials) supplied to each signal in each period of each frame in the timing charts shown in FIGS.

[0374] [Table 5]

[0375] For example, as shown in Table 5, the initialization voltage VINI is −3.5 V and the voltage VL(LO) is −5.5 V. The setting values ​​of the other voltages are the same as the setting values ​​shown in Table 1 described in “1-5. Driving method of the display device 10.”

[0376] <5-2-1. First Example of Method for Driving Pixel Circuit 181D> A first example of a method for driving the pixel circuit 181D will be described with reference to Fig. 37. The first example of the method for driving the pixel circuit 181D includes displaying images of different colors in successive frames, similar to the first example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 36 will be described as necessary.

[0377] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n), the fifth scan signal SC5(n), and the image data signal SL(m) are the same as those described in "1-5-1. First example of the method for driving the display device 10." Therefore, configurations similar to those described in "1-5-1. First example of the method for driving the display device 10" will be described as necessary.

[0378] During the light emission period PEM of the K-1st FRAME, the light emitting element OLED emits light in the same manner as in the configuration described in "1-5-1. First Example of the Driving Method of the Display Device 10." Note that the fifth transistor T5, to which the fourth scan signal SC4(n) is supplied, is in the off state.

[0379] During the period between the light-emitting period PEM of the (K-1st) FRAME and the period PIP, similar to the configuration described in "1-5-1. First Example of the Driving Method of the Display Device 10," the voltage supplied to the first node N1 remains at voltage Vna, and the voltage supplied to the second node N2 gradually drops from voltage Vna toward 0 V (reference voltage VREF). Furthermore, the voltage supplied to the third node N3 gradually drops from voltage Vnb toward voltage Vnh (initialization voltage VINI, −3.5 V). Because the second transistor T2 and the fifth transistor T5 are on and a current flows from the drive power supply line PVDD to the initialization voltage power supply line SVI, the light-emitting element OLED does not emit light.

[0380] During the period PIP following the period between the light-emitting period PEM and the period PIP of the (K-1st) FRAME, the fourth scan signal SC4(n) changes from LO to HI. The fifth transistor T5 and the sixth transistor T6 change from OFF to ON, the second transistor T2 and the fourth transistor T4 maintain the ON state, and the first transistor T1 and the third transistor T2 maintain the OFF state.

[0381] As a result, the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage Vnd (precharge voltage VPRC, 1.5V) and reaches voltage Vnd. The voltage supplied to the second node N2 gradually drops from voltage Vna toward 0V (reference voltage VREF) and reaches 0V. The voltage supplied to the third node N3 gradually drops from voltage Vnb toward voltage Vnh (initialization voltage VINI, −3.5V) and reaches voltage Vnh. The potential difference Vgs becomes 3.5V (0V−(−3.5V)), and the potential difference Vds becomes 11.5V (8V−(−3.5V)). As in the period between the light-emitting period PEM and period PIP of the K-1st FRAME, the second transistor T2 and the fifth transistor T5 are in the on state, and a current Ion flows from the drive power supply line PVDD to the initialization voltage power supply line SVI, so the light-emitting element OLED does not emit light.

[0382] As described above, during the period PIP, a precharge voltage (intermediate potential) is supplied to the first node N1, the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI (-3.5V).

[0383] In the initial period of the horizontal period HRP of the KthFRAME following the period PIP, the fourth scan signal SC4(n) changes from a state in which HI is supplied to a state in which LO is supplied, the fifth transistor T5 and the sixth transistor T6 change from an on state to an off state, the second transistor T2 and the fourth transistor T4 maintain the on state, and the first transistor T1 and the third transistor T2 maintain the off state.

[0384] As a result, the voltage supplied to the first node N1 remains at voltage Vnd, the voltage supplied to the second node N2 remains at 0V, and the voltage supplied to the third node N3 remains at voltage Vnd. When the fifth transistor T5 is turned off and the third node N3 is released, the third node N3 begins to charge due to Ion of the second transistor T2, which is in the on state, and the potential of the third node N3 begins to rise. At this time, the potential difference Vgs is 3.5V (0V - voltage Vnh (-3.5V)), and the potential difference Vds is 11.5V. Because the potential difference Vgs is greater than the threshold voltage VTH, the second transistor T2 is in the on state. A current Ion flows from the driving power line PVDD (the second electrode 626 side) to the third node N3 (the first electrode 624 side), and the voltage supplied to the third node N3 gradually rises from voltage Vnh. Similarly to the period PIP, the light-emitting element OLED does not emit light.

[0385] During the period PWR following the initial period of the horizontal period HRP, the first transistor T1 changes from an off state to an on state, the second transistor T2 and the fourth transistor T4 maintain their on states, and the third transistor, the fifth transistor T5 and the sixth transistor T6 maintain their off states.

[0386] As a result, the voltage supplied to the first node N1 gradually drops from voltage Vnd toward voltage Vnf (voltage VSIGL, −0.5 V), the voltage supplied to the second node N2 maintains 0 V, and the voltage supplied to the third node N3 maintains voltage Vnh. Also, similar to the period PIP, the light-emitting element OLED does not emit light.

[0387] During the period PVH that is parallel to (overlaps with) the period PWR, the first transistor T1 and the fourth transistor T4 remain on, and the third transistor T5 and the sixth transistor T6 remain off.

[0388] As a result, the voltage supplied to the first node N1 gradually drops toward the voltage Vnf and reaches the voltage Vnf, while the voltage supplied to the second node N2 remains at 0V.

[0389] When the potential difference Vgs becomes the threshold voltage VTH, the second transistor T2 changes from the ON state to the OFF state, and the current Ion stops flowing. At this time, the voltage supplied to the third node N3 increases from voltage Vnh (-3.5V) to voltage Vne (-1V), and the potential difference Vgs is equal to the threshold voltage VTH (1V). That is, during the period PVH, the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, thereby acquiring the threshold voltage VTH of the second transistor T2, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitor CS). Furthermore, the second transistor T2 is in the OFF state, and the current Ion does not flow from the driving power supply line PVDD to the reference voltage line PVSS, so that the light-emitting element OLED does not emit light.

[0390] At the end of the period PVH, similar to the configuration described in "1-5-1. First Example of the Method for Driving the Display Device 10," the first node N1 is electrically connected to the second node N2, the voltage supplied to the second node N2 becomes voltage Vnf, the voltage supplied to the first node N1 remains at voltage Vnf, and the voltage supplied to the third node N3 remains at voltage Vne. Because the potential difference Vgs is lower than the threshold voltage VTH, no current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS. Therefore, the light-emitting element OLED does not emit light.

[0391] In this way, during the period PWR, the data signal VDATA is written to the pixel 180D (pixel circuit 181D). During the period PVH, the potential difference Vgs of the second transistor T2 is made equal to the threshold voltage VTH, thereby obtaining the threshold voltage VTH of the second transistor T2, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0392] In the description of the method for driving the display device according to the fifth embodiment, the difference between the timing at which the fourth scan signal SC4(n) changes from a state in which HI is supplied to a state in which LO is supplied to the fourth scan signal SC4(n) and the timing at which the fifth scan signal SC5(n) changes from a state in which LO is supplied to a state in which HI is supplied to the fourth scan signal SC4(n) is exaggerated in order to make it easier to see the voltage (potential) supplied to the first node N1, the voltage (potential) supplied to the second node N2, and the voltage (potential) supplied to the third node N3 shown in Fig. 37 etc. In reality, the difference between the timing at which the fourth scan signal SC4(n) changes from a state in which HI is supplied to a state in which LO is supplied to the fifth scan signal SC5(n) and the timing at which LO is supplied to the fifth scan signal SC5(n) is changed from a state in which LO is supplied to the fifth scan signal SC5(n) is only slight, and may be, for example, substantially the same. 37 and the like, the timing at which the fourth scan signal SC4(n) changes from a state in which HI is supplied to a state in which LO is supplied, and the timing at which the fifth scan signal SC5(n) changes from a state in which LO is supplied to a state in which HI is supplied, cause a slight time difference in the change in the voltage (potential) supplied to the first node N1, the change in the voltage (potential) supplied to the second node N2, and the change in the voltage (potential) supplied to the third node N3. Therefore, the time difference between the period PWR and the period PVH is slight, and they may be considered to be substantially the same or the same.

[0393] During the light emission period PEM of the KthFRAME following the horizontal period HRP of the KthFRAME, the display becomes black with three pixels, using pixel 180D that emits red light, pixel 180D that emits blue light, and pixel 180D that emits green light, similar to the configuration described in "1-5-1. First example of the driving method of the display device 10."

[0394] The first example of the method for driving the pixel circuit 181D including the configuration described above has the same effects as the method for driving the display device 10 according to the first embodiment.

[0395] Furthermore, the scan signal line 333 in the pixel circuit 181D also serves as the scan signal lines 332 and 333 in the pixel circuit 181. Therefore, the pixel circuit 181D has a configuration that allows for a reduction in the number of signal lines, and a display device including the pixel circuit 181D can reduce the pixel size. As a result, a display device including the pixel circuit 181D can increase the number of pixels, and can achieve higher definition and a larger screen. Furthermore, although power consumption increases because the initialization voltage VINI (-3.5V) is deep (because it is a low voltage), the period PWR overlaps with the period PVH, making it possible to minimize the period PWR.

[0396] <5-2-2. Second Example of Method for Driving Pixel Circuit 181D> A second example of a method for driving the pixel circuit 181D will be described with reference to Fig. 38. The driving method shown as the second example of the method for driving the pixel circuit 181D includes displaying images of the same color (white) in consecutive frames, similar to the second example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 37 will be described as necessary.

[0397] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n), the fifth scan signal SC5(n), and the image data signal SL(m) are the same as those described in "5-2-1. First Example of a Method for Driving a Pixel Circuit 181D." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during periods other than the horizontal period HRP of the Kth FRAME and the light-emitting period PEM of the Kth FRAME are the same as those described in "5-2-1. First Example of a Method for Driving a Pixel Circuit 181D." Furthermore, the operation of each transistor during each period is the same as those described in "5-2-1. First Example of a Method for Driving a Pixel Circuit 181D." Therefore, configurations similar to those described in "5-2-1. First Example of a Method for Driving a Pixel Circuit 181D" will be described as necessary. In addition, the image data signal SL(m) is supplied with a data signal VDATA of VSIGH corresponding to white during the horizontal period HRP, and is supplied with a data signal VDATA similar to the configuration described in "5-2-1. First example of the driving method for pixel circuit 181D" during periods other than the horizontal period HRP.

[0398] The second example driving method for pixel circuit 181D during the light-emitting period PEM of K-1stFRAME, the period between the light-emitting period PEM of K-1stFRAME following the light-emitting period PEM of K-1stFRAME and the period PIP of KthFRAME, the period PIP of KthFRAME, and the initial period of the horizontal period HRP of KthFRAME following the period PIP of KthFRAME is the same as the driving method described in "5-2-1. First example of driving method for pixel circuit 181D".

[0399] During the period PWR following the initial period of the horizontal period HRP in the second example of the method for driving the pixel circuit 181D, the configuration of each control signal, the operation of each transistor, and the like are the same as those described in "5-2-1. First Example of the Method for Driving the Display Device 10." The voltage supplied to the first node N1 gradually increases from voltage Vnd toward voltage Vng (voltage VSIGH, 3.5V), the voltage supplied to the second node N2 remains at 0V (reference voltage VREF), and the voltage supplied to the third node N3 gradually increases from Vnh (-3.5V). Also, as in the period PIP, the light-emitting element OLED does not emit light.

[0400] In the second example of the method for driving the pixel circuit 181D, during the period PWR, the period PVH that is parallel to (overlaps with) the period PWR, the period at the end of the period PVH, and the light-emitting period PEM of the KthFRAME, the configuration of each control signal, the operation of each transistor, the voltage supplied to each node, etc. are the same as the configuration described in "5-2-1. First example of the method for driving the pixel circuit 181D."

[0401] As described above, during the period PWR in the second example of the method for driving the pixel circuit 181D, the data signal VDATA is written to the pixel 180 (pixel circuit 181). Furthermore, during the period PVH in the second example of the method for driving the pixel circuit 181D, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS). Furthermore, during the light emission period PEM of the KthFRAME in the second example of the method for driving the pixel circuit 181D, three pixels emit white light.

[0402] <5-2-3. Third Example of Method for Driving Pixel Circuit 181D> A third example of a method for driving the pixel circuit 181D will be described with reference to Fig. 39. The driving method shown as the third example of the method for driving the pixel circuit 181D includes displaying images of the same color (black) in consecutive frames, similar to the third example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 38 will be described as necessary.

[0403] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n), the fifth scan signal SC5(n), and the image data signal SL(m) are the same as those described in "5-2-1. First Example of Method for Driving Pixel Circuit 181D." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light-emitting period of the K-1st FRAME, are the same as those described in "1-5-3. Third Example of Method for Driving Display Device 10." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the periods other than the light-emitting period of the K-1st FRAME through the period PIP of the Kth FRAME, are the same as those described in "5-2-1. First Example of Method for Driving Pixel Circuit 181D." Therefore, the configuration described in "1-5-3. Third example of the method for driving the display device 10" and the configuration similar to that described in "5-2-1. First example of the method for driving the pixel circuit 181D" will be described as necessary. Note that, for the image data signal SL(m), the data signal VDATA of VSIGL corresponding to black is supplied during the horizontal period HRP, and the data signal VDATA similar to the configuration described in "5-2-1. First example of the method for driving the pixel circuit 181D" is supplied during periods other than the horizontal period HRP.

[0404] During the light emission period PEM of the K-1st FRAME, similar to the configuration described in "1-5-3. Third example of the method for driving the display device 10", the light emitting element OLED does not emit light and the pixel 180D (pixel circuit 181D) turns black.

[0405] During the period between the light-emitting period PEM of the K-1st FRAME and the period PIP of the Kth FRAME, which follows the light-emitting period PEM of the K-1st FRAME, the configuration of each control signal and the operation of each transistor are the same as those described in "5-2-1. First Example of the Driving Method of Pixel Circuit 181A." The voltage supplied to the first node N1 gradually increases from voltage Vnf toward voltage Vnd (pre-charge voltage VPRC, 1.5V), the voltage supplied to the second node N2 gradually increases from voltage Vnf toward reference voltage VREF (0V), and the voltage supplied to the third node N3 gradually decreases from voltage Vne toward initialization voltage VINI (Vnh, -3.5V). In addition, the light-emitting element OLED does not emit light.

[0406] During the period PIP of the Kth FRAME, which follows the period between the light-emitting period PEM and the period PIP of the K-1st FRAME, the voltage supplied to the first node N1 gradually increases from voltage Vnf toward voltage Vnd and reaches voltage Vnd. The voltage supplied to the second node N2 gradually increases from voltage Vnf toward 0V and reaches 0V. The voltage supplied to the third node N3 gradually decreases from voltage Vne toward voltage Vnh and reaches voltage Vnh. The potential difference Vgs becomes 3.5V, and the potential difference Vds becomes 11.5V. Because the second transistor T2 and the fifth transistor T5 are on and a current flows from the drive power line PVDD to the initialization voltage power line SVI, the light-emitting element OLED does not emit light.

[0407] As described above, during the period PIP, a precharge voltage (intermediate potential) is supplied to the first node N1, the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI1 (-3.5V).

[0408] From the beginning of the horizontal period HRP of KthFRAME following the period PIP to the light emission period PEM of KthFRAME, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor, are the same as the configuration and operation described in "5-2-1. First example of the driving method of the pixel circuit 181A."

[0409] During the period PWR, similar to the configuration described in "5-2-1. First Example of Method for Driving Pixel Circuit 181A", a data signal VDATA (voltage VSIGL in the third example) is written to the pixel 180D (pixel circuit 181D).

[0410] Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitive element CS).

[0411] Furthermore, during the light emission period PEM of KthFRAME, similar to the configuration described in "5-2-1. First example of driving method for pixel circuit 181A", three pixels, using pixel 180A that emits red light, pixel 180A that emits blue light, and pixel 180A that emits green light, produce black.

[0412] <5-2-4. Fourth Example of Method for Driving Pixel Circuit 181D> A fourth example of a method for driving the pixel circuit 181D will be described with reference to Fig. 40. The fourth example of a method for driving the pixel circuit 181A includes displaying images of different colors in successive frames, similar to the fourth example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 39 will be described as necessary.

[0413] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n), the fifth scan signal SC5(n), and the image data signal SL(m) are the same as those described in "5-2-1. First Example of Method for Driving Pixel Circuit 181D." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light emission period PEM of the K-1th FRAME and the period PIP of the Kth FRAME are the same as those described in "5-2-3. Third Example of Method for Driving Pixel Circuit 181D." The voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the horizontal period HRP of the Kth FRAME and the light emission period PEM of the Kth FRAME are the same as those described in "5-2-2. Second Example of Method for Driving Pixel Circuit 181D." Configurations similar to those in "5-2-1. First Example of Method for Driving Pixel Circuit 181D," "5-2-2. Second Example of Method for Driving Pixel Circuit 181D," and "5-2-3. Third Example of Method for Driving Pixel Circuit 181D" will be explained as necessary. Note that, for the image data signal SL(m), a data signal VDATA of VSIGH corresponding to white is supplied during the horizontal period HRP, and a data signal VDATA similar to the configuration explained in "5-2-1. First Example of Method for Driving Pixel Circuit 181D" is supplied during periods other than the horizontal period HRP.

[0414] The driving method of the fourth example of the display device 10 during the light-emitting period PEM of the K-1st FRAME, the period between the light-emitting period PEM of the K-1st FRAME following the light-emitting period PEM of the K-1st FRAME and the period PIP of the Kth FRAME, and the period PIP of the Kth FRAME is the same as the driving method described in "5-2-3. Third example of the driving method of the pixel circuit 181D."

[0415] The driving method of the fourth example of the display device 10 during the horizontal period HRP of the K-1st FRAME and the light emission period PEM of the Kth FRAME is the same as the driving method described in "5-2-2. Second example of the driving method of the pixel circuit 181D."

[0416] 6. Sixth Embodiment An overview of a display device according to a sixth embodiment will be described with reference to Figs. 1, 4, and 41 to 46. Fig. 41 is a schematic diagram showing input signals to a pixel 180E (pixel circuit 181E) according to a sixth embodiment of the present invention. Fig. 42 is a circuit diagram showing the configuration of the pixel circuit 181E. Figs. 43 to 46 are timing charts of the display device according to the sixth embodiment of the present invention.

[0417] The display device according to the sixth embodiment includes a pixel 180E and a pixel circuit 181E. Specifically, the pixel 180E and the pixel circuit 181E include the configurations shown in the following (1) to (3). The configurations shown in (1) to (3) are mainly different from the configurations of the pixel 180D and the pixel circuit 181D of the display device according to the fifth embodiment.

[0418] (1) The scan voltage power supply line SVIR to which the scan voltage power supply SIR(n) is supplied is included. (2) The scan voltage power supply line SVIR is a common signal line that serves as both the reference voltage power supply line SVR to which the reference voltage power supply VREF is supplied and the initialization voltage power supply line SVI to which the initialization voltage VINI is supplied. That is, the scan voltage power supply line SVIR has a configuration that serves as both the reference voltage power supply line SVR and the initialization voltage power supply line SVI. (3) The scan voltage power supply SIR(n) includes a voltage that alternates with time, which is an initialization voltage VINI2 and an initialization voltage VINI1.

[0419] The configurations of the pixel 180E and the pixel circuit 181E shown in (1) to (3), and the configurations of the pixel 180E and the pixel circuit 181E other than those related to those shown in (1) to (3), are the same as those of the display device according to the second embodiment. Furthermore, the configurations of the pixel 180E and the pixel circuit 181E shown in (1) to (3), and the configurations of the pixel 180E and the pixel circuit 181E other than those related to those shown in (1) to (3), are the same as those of the display device according to the fifth embodiment. Therefore, differences from the display device according to the second embodiment and the display device according to the fifth embodiment will be mainly described here. In describing the configuration and functions of the display device according to the sixth embodiment, configurations and functions similar to those of the display device according to the second embodiment and the display device according to the fifth embodiment will be described as needed. Furthermore, configurations identical to or similar to those in FIGS. 1 to 40 will be described as needed.

[0420] <6-1. Configuration of pixel 180E> The pixel 180E and pixel circuit 181E will be outlined with reference to FIGS.

[0421] The pixel circuit 181E is connected to the scan voltage power supply line SVIR. The configuration and function of the scan voltage power supply line SVIR according to the sixth embodiment are similar to those of the scan voltage power supply line SVIR according to the second embodiment.

[0422] In addition, the configurations and functions related to the fourth transistor T4, the fifth transistor T5, and the scan voltage power supply line SVIR are similar to the configurations and functions of the fourth transistor T4, the fifth transistor T5, and the scan voltage power supply line SVIR in the second embodiment.

[0423] The configuration and functions of the pixel circuit 181E other than those described in "6-1. Configuration of the pixel 180E" are the same as those of the pixel circuit 181D.

[0424] <6-2. Driving Method of Pixel Circuit 181E> A method for driving a display device according to the sixth embodiment will be described with reference to Figures 43 to 46. Configurations that are the same as or similar to those in Figures 1 to 42 will be described as necessary. As in the first embodiment, the horizontal axis of the timing chart represents time.

[0425] The method for driving the display device according to the sixth embodiment differs from the method for driving the display device 10 according to the fifth embodiment in the configuration related to the configurations shown in (1) to (3) described in "6-1. Configuration of pixel 180E." The configurations and functions other than the configurations related to (1) to (3) described in "6-1. Configuration of pixel 180E" are the same as those of the method for driving the display device according to the fifth embodiment.

[0426] The method for driving the display device according to the sixth embodiment includes the same period as the method for driving the display device 10 according to the first embodiment shown in FIG.

[0427] During one horizontal period (horizontal period HRP) in the driving method of the display device according to the sixth embodiment, the pixel 180E (pixel circuit 181E) receives a first scan signal SC1(n), a second scan signal SC2(n), a fourth scan signal SC4(n), a fifth scan signal SC5(n), an image data signal SL(m), and a scan voltage power supply SIR(n). For example, the pixel 180E (pixel circuit 181E) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n), and the fifth scan signal SC5(n). The image data signal SL(m) and the scan voltage power supply SIR(n) are input to the selected pixel 180E (pixel circuit 181E) according to the timing of each signal. A similar operation is performed for all pixels 180E (pixel circuits 181E), and based on the image data signals SL(m) input to all pixels 180E (pixel circuits 181E), the image of the frame corresponding to one frame is displayed in the display area 22 of the display device.

[0428] For example, Table 6 shows the voltages (potentials) supplied to each signal in each period of each frame in the timing charts shown in FIGS.

[0429] [Table 6]

[0430] For example, as shown in Table 6, the initialization voltage VINI2 is 0 V, and the initialization voltage VINI1 is −3.5 V. The initialization voltage VINI2 is the same as the reference voltage VREF, and the initialization voltage VINI1 is the same as the initialization voltage VINI. The setting values ​​of the other voltages are the same as the setting values ​​shown in Table 5 described in “5-2. Driving method of pixel circuit 181D.”

[0431] <6-2-1. First Example of Method for Driving Pixel Circuit 181E> A first example of a method for driving the pixel circuit 181E will be described with reference to Fig. 43. The first example of the method for driving the pixel circuit 181E includes displaying images of different colors in successive frames, similar to the first example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 42 will be described as necessary.

[0432] The scan voltage power supply SIR(n) supplies an initialization voltage VINI2 during the light emission period PEM of the K-1st FRAME, an initialization voltage VINI1 during the period PIP of the Kth FRAME, and an initialization voltage VINI2 during the period PVH of the Kth FRAME and the light emission period PEM.

[0433] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n), the fifth scan signal SC5(n), and the image data signal SL(m) are the same as those described in "5-2-1. First example of method for driving pixel circuit 181D." Therefore, configurations similar to those described in "5-2-1. First example of method for driving pixel circuit 181D" will be described as necessary.

[0434] In the light emitting period PEM of the K-1st FRAME, the light emitting element OLED emits light in the same manner as in the configuration described in "5-2-1. First example of the method for driving the display device 10."

[0435] During the period between the light-emitting period PEM of the (K-1st) FRAME and the period PIP following the light-emitting period PEM of the (K-1st) FRAME, similar to the configuration shown in "5-2-1. First Example of the Method of Driving the Pixel Circuit 181D," the voltage supplied to the first node N1 is maintained at Vna, and the scan voltage power supply SIR(n) changes from a state in which 0 V (initialization voltage VINI2) is supplied to a state in which voltage Vnh (initialization voltage VINI1, -3.5 V) is supplied, so that the voltage supplied to the second node N2 gradually drops from voltage Vna toward voltage Vnh (initialization voltage VINI, -3.5 V), and the voltage supplied to the third node N3 gradually drops from voltage Vnb toward voltage Vnh (initialization voltage VINI, -3.5 V). In addition, the light-emitting element OLED does not emit light.

[0436] During the period PIP following the period between the light-emitting period PEM and the period PIP of the K-1st FRAME, similar to the configuration described in "5-2-1. First Example of the Method for Driving the Pixel Circuit 181D," the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage Vnd (pre-charge voltage VPRC, 1.5V) and reaches voltage Vnd. The scan voltage power supply SIR(n) maintains a state in which voltage Vnh is supplied, the voltage supplied to the second node N2 becomes Vnh, and the voltage supplied to the third node N3 becomes Vnh. As with the period between the light-emitting period PEM and the period PIP of the K-1st FRAME, the light-emitting element OLED does not emit light.

[0437] As described above, during the period PIP, the precharge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI (-3.5V).

[0438] During the initial period of the horizontal period HRP of the KthFRAME following the period PIP, similar to the configuration described in "5-2-1. First Example of the Method for Driving the Pixel Circuit 181D," the voltage supplied to the first node N1 remains at voltage Vnd, and the voltage supplied to the second node N2 and the voltage supplied to the third node N3 remain at voltage Vnh. The light-emitting element OLED does not emit light. The scan voltage power supply SIR(n) remains at voltage Vnh.

[0439] During the period PWR following the beginning of the horizontal period HRP, the scan voltage power supply SIR(n) changes from a state in which the initialization voltage VINI1 (-3.5V) is supplied to a state in which the initialization voltage VINI2 (0V) is supplied. The voltage supplied to the first node N1 gradually drops from voltage Vnd toward voltage Vnf (voltage VSIGL, -0.5V), and the voltage supplied to the second node N2 gradually rises from voltage Vnh toward 0V. As the voltage supplied to the second node N2 gradually rises from voltage Vnh toward 0V, the second transistor T2 exceeds the threshold voltage VTH and enters an ON state. This causes the third node N3 to start being charged, and the voltage supplied to the third node N3 rises. Furthermore, the light-emitting element OLED does not emit light.

[0440] During the period PWR, during the period PVH that is parallel to (overlaps with) the period PWR, and immediately after the start of the period PVH, similar to the configuration described in "5-2-1. First Example of the Driving Method of the Pixel Circuit 181D," the voltage supplied to the first node N1 becomes voltage Vnf, the voltage supplied to the second node N2 becomes 0 V, the voltage supplied to the third node N3 rises from voltage Vnh to voltage Vne, and charging stops when the voltage supplied to the third node N3 reaches the threshold voltage VTH of the second transistor T2, and the third node N3 becomes voltage Vne. As a result, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by the operation in which the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitor CS). Furthermore, the light-emitting element OLED does not emit light. The scan voltage power supply SIR(n) maintains the state in which the initialization voltage VINI2 (0V) is supplied.

[0441] At the end of the period PVH, similar to the configuration described in "5-2-1. First Example of the Method for Driving the Pixel Circuit 181D," the voltage supplied to the first node N1 remains at voltage Vnf, and the voltage supplied to the third node N3 remains at voltage Vne. The light-emitting element OLED does not emit light. The scan voltage power supply SIR(n) remains at the initialization voltage VINI2 (0V).

[0442] As described above, during the period PWR, the data signal VDATA is written to the pixel 180E (pixel circuit 181E). Also, during the period PVH, as described above, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0443] During the light emission period PEM of the Kth FRAME following the horizontal period HRP of the Kth FRAME, three pixels, one emitting red light, one emitting blue light, and one emitting green light, are used to produce black, as in the configuration described in "5-2-1. First Example of the Method for Driving the Pixel Circuit 181D." Note that the scan voltage power supply SIR(n) maintains the state in which the initialization voltage VINI2 (0V) is supplied.

[0444] The first example of the method for driving the pixel circuit 181E including the configuration described above provides the same effects as the method for driving the display device according to the fifth embodiment. Moreover, the first example of the method for driving the pixel circuit 181E including the configuration described above provides the same effects as the method for driving the display device according to the second embodiment.

[0445] <6-2-2. Second Example of Method for Driving Pixel Circuit 181E> A second example of a method for driving the pixel circuit 181E will be described with reference to Fig. 44. The driving method shown in the second example of the method for driving the pixel circuit 181E includes displaying images of the same color (white) in consecutive frames, similar to the second example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 43 will be described as necessary.

[0446] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n), the fifth scan signal SC5(n), the image data signal SL(m), and the scan voltage power supply SIR(n) are the same as those described in "6-2-1. First Example of the Method for Driving the Pixel Circuit 181E." The voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the horizontal period HRP of the KthFRAME and the light-emitting period PEM of the KthFRAME are the same as those described in "6-2-1. First Example of the Method for Driving the Pixel Circuit 181E." The image data signal SL(m) is supplied with a data signal VDATA of VSIGH corresponding to white during the horizontal period HRP, and is supplied with a data signal VDATA similar to that described in "6-2-1. First Example of the Method for Driving the Pixel Circuit 181E" during the periods other than the horizontal period HRP.

[0447] The second example driving method of pixel circuit 181E during the light emitting period PEM of K-1stFRAME, the period between the light emitting period PEM of K-1stFRAME following the light emitting period PEM of K-1stFRAME and the period PIP of KthFRAME, the period PIP of KthFRAME, and the initial period of the horizontal period HRP of KthFRAME following the period PIP of KthFRAME is the same as the driving method described in "6-2-1. First example of driving method of pixel circuit 181E."

[0448] During the period PWR following the initial period of the horizontal period HRP in the second example of the method for driving the pixel circuit 181E, the configuration of each control signal, the operation of each transistor, etc. are the same as those described in "6-2-1. First Example of the Method for Driving the Display Device 10." The voltage supplied to the first node N1 gradually rises from voltage Vnd toward voltage Vng (voltage VSIGH, 3.5V), while the voltage supplied to the second node N2 and the voltage supplied to the third node N3 maintain voltage Vnh (initialization voltage VINI, -3.5V). In addition, the light-emitting element OLED does not emit light.

[0449] In the second example of the driving method for the pixel circuit 181E, during the period PWR, in a period PVH that is parallel to (overlaps with) the period PWR, the voltage supplied to the first node N1 gradually increases from voltage Vnd toward voltage Vng and reaches voltage Vng, the voltage supplied to the second node N2 increases from voltage Vnh toward voltage VNI2 (0 V), and when the voltage supplied to the second node N2 exceeds the threshold voltage VTH of the second transistor T2, the second transistor T2 is turned on. Because the fifth transistor T5 is off and the third node N3 is released, the current Ion of the second transistor T2 charges the third node N3, and the voltage supplied to the third node N3 increases from Vnh and stops increasing at the potential (Vne) of the threshold voltage VTH. That is, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitive element CS). Also, the light-emitting element OLED does not emit light.

[0450] At the end of the period PVH in the second example of the method for driving the pixel circuit 181E, the configuration of each control signal, the operation of each transistor, and the like are the same as those described in "6-2-1. First Example of the Method for Driving the Display Device 10." The first node N1 becomes conductive with the second node N2, the voltage supplied to the second node N2 gradually increases, the second transistor T2 becomes conductive, and a current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS. Therefore, the voltage supplied to the first node N1 and the voltage supplied to the third node N3 increase in accordance with the increase in the voltage supplied to the second node N2. Due to the increase in the voltage supplied to the third node N3, the voltage supplied to the first node N1 and the voltage supplied to the second node N2 further increase.

[0451] Furthermore, during the light emission period PEM of KthFRAME in the second example of the driving method for pixel circuit 181E, the voltage supplied to the first node N1 and the voltage supplied to the second node N2 rise to voltage Vna, and the voltage supplied to the third node N3 rises to voltage Vnb. The potential difference Vgs is greater than the threshold voltage VTH, the second transistor T2 is on, a current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS, and the light emitting element OLED emits light. For example, pixel 180 (pixel circuit 181) emits red light, and three pixels, one for emitting red light, one for emitting blue light, and one for emitting green light, emit white light.

[0452] As described above, during the period PWR in the second example of the method for driving the pixel circuit 181E, the data signal VDATA is written to the pixel 180 (pixel circuit 181). Furthermore, during the period PVH in the second example of the method for driving the pixel circuit 181E, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS). Furthermore, during the light emission period PEM of the KthFRAME in the second example of the method for driving the pixel circuit 181E, the three pixels emit white light.

[0453] <6-2-3. Third Example of Method for Driving Pixel Circuit 181E> A third example of a method for driving the pixel circuit 181E will be described with reference to Fig. 45. The driving method shown in the third example of the method for driving the pixel circuit 181E includes displaying images of the same color (black) in consecutive frames, similar to the third example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 44 will be described as necessary.

[0454] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n), the fifth scan signal SC5(n), the image data signal SL(m), and the scan voltage power supply SIR(n) are the same as those described in "6-2-1. First Example of the Method for Driving the Pixel Circuit 181E." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light-emitting period of the K-1st FRAME, are the same as those described in "5-2-3. Third Example of the Method for Driving the Display Device 10." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the periods other than the light-emitting period of the K-1st FRAME through the period PIP of the Kth FRAME, are the same as those described in "6-2-1. First Example of the Method for Driving the Pixel Circuit 181E." Therefore, configurations similar to those described in "5-2-3. Third example of method for driving display device 10" and "6-2-1. First example of method for driving pixel circuit 181E" will be described as necessary. Note that, for the image data signal SL(m), a data signal VDATA of VSIGL corresponding to black is supplied during the horizontal period HRP, and a data signal VDATA similar to the configuration described in "6-2-1. First example of method for driving pixel circuit 181E" is supplied during periods other than the horizontal period HRP.

[0455] During the light emission period PEM of the K-1st FRAME, similar to the configuration described in "5-2-3. Third Example of the Method for Driving the Display Device 10", the light emitting element OLED does not emit light and the pixel 180E (pixel circuit 181E) turns black.

[0456] During the period between the light-emitting period PEM of the K-1st FRAME and the period PIP of the Kth FRAME, which follows the light-emitting period PEM of the K-1st FRAME, the configuration of each control signal and the operation of each transistor are the same as those described in "6-2-1. First Example of the Driving Method of the Pixel Circuit 181A." The voltage supplied to the first node N1 gradually increases from voltage Vnf toward voltage Vnd (pre-charge voltage VPRC, 1.5V), and the voltage supplied to the second node N2 gradually decreases from voltage Vnf toward the initialization voltage VINI1 (Vnh, -3.5V). The voltage supplied to the third node N3 gradually decreases from voltage Vne toward the initialization voltage VINI1 (Vnh, -3.5V). In addition, the light-emitting element OLED does not emit light.

[0457] During the period PIP of the Kth FRAME, which follows the period between the light-emitting period PEM and the period PIP of the K-1st FRAME, the voltage supplied to the first node N1 gradually increases from voltage Vnf toward voltage Vnd and reaches voltage Vnd. The voltage supplied to the second node N2 gradually decreases from voltage Vnf toward voltage Vnh (initialization voltage VINI1, -3.5V) and reaches voltage Vnh. The voltage supplied to the third node N3 gradually decreases from voltage Vne toward voltage Vnh and reaches voltage Vnh. The potential difference Vgs becomes 0V, and the potential difference Vds becomes 8V. Since the second transistor T2 and the fifth transistor T5 are on and a current flows from the drive power supply line PVDD to the initialization voltage power supply line SVI, the light-emitting element OLED does not emit light.

[0458] As described above, during the period PIP, the precharge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-3.5V).

[0459] From the beginning of the horizontal period HRP of KthFRAME following the period PIP to the light emission period PEM of KthFRAME, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor, are the same as the configuration and operation described in "6-2-1. First example of the driving method for pixel circuit 181A."

[0460] During the period PWR, similar to the configuration described in "6-2-1. First Example of Method for Driving Pixel Circuit 181A", a data signal VDATA (voltage VSIGL in the third example) is written to the pixel 180E (pixel circuit 181E).

[0461] Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitive element CS).

[0462] Furthermore, during the light emission period PEM of KthFRAME, similar to the configuration described in "6-2-1. First example of driving method for pixel circuit 181A", three pixels, using pixel 180A that emits red light, pixel 180A that emits blue light, and pixel 180A that emits green light, produce black.

[0463] <6-2-4. Fourth Example of Method for Driving Pixel Circuit 181E> A fourth example of a method for driving the pixel circuit 181E will be described with reference to Fig. 46. The driving method shown as the fourth example of the method for driving the pixel circuit 181A includes displaying images of different colors in successive frames, similar to the fourth example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 45 will be described as necessary.

[0464] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n), the fifth scan signal SC5(n), the image data signal SL(m), and the scan voltage power supply SIR(n) are the same as those described in "6-2-1. First Example of Method for Driving Pixel Circuit 181E." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light emission period PEM of the K-1th FRAME and the period PIP of the Kth FRAME, are the same as those described in "6-2-3. Third Example of Method for Driving Pixel Circuit 181E." The voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the horizontal period HRP of the Kth FRAME and the light emission period PEM of the Kth FRAME, are the same as those described in "6-2-2. Second Example of Method for Driving Pixel Circuit 181E." Configurations similar to those in "6-2-1. First Example of Method for Driving Pixel Circuit 181E," "6-2-2. Second Example of Method for Driving Pixel Circuit 181E," and "6-2-3. Third Example of Method for Driving Pixel Circuit 181E" will be explained as necessary. Note that, for the image data signal SL(m), a data signal VDATA of VSIGH corresponding to white is supplied during the horizontal period HRP, and a data signal VDATA similar to the configuration explained in "6-2-1. First Example of Method for Driving Pixel Circuit 181E" is supplied during periods other than the horizontal period HRP.

[0465] The driving method of the fourth example of the display device 10 during the light-emitting period PEM of the K-1st FRAME, the period between the light-emitting period PEM of the K-1st FRAME following the light-emitting period PEM of the K-1st FRAME and the period PIP of the Kth FRAME, and the period PIP of the Kth FRAME is the same as the driving method described in "6-2-3. Third example of the driving method of the pixel circuit 181E."

[0466] The driving method of the fourth example of the display device 10 during the horizontal period HRP of the K-1st FRAME and the light emission period PEM of the Kth FRAME is the same as the driving method described in "6-2-2. Second example of the driving method of the pixel circuit 181E."

[0467] 7. Seventh Embodiment An overview of the display device according to the seventh embodiment will be described with reference to Fig. 1, Fig. 23, and Fig. 47 to Fig. 52. Fig. 47 is a schematic diagram showing an input signal to a pixel 180F (pixel circuit 181F) according to the seventh embodiment, Fig. 48 is a circuit diagram showing the configuration of the pixel circuit 181F, and Fig. 49 to Fig. 52 are timing charts of the display device according to the seventh embodiment.

[0468] The display device according to the seventh embodiment includes a pixel 180F and a pixel circuit 181F. Specifically, the pixel 180F and the pixel circuit 181F include the following configurations (1) to (5). The configurations (1) to (5) are mainly different from the configurations of the pixel 180A and the pixel circuit 181A of the display device according to the second embodiment.

[0469] (1) It includes a scan voltage power supply line SVIRP to which a scan voltage power supply SIRP(n) is supplied. (2) The scan voltage power supply line SVIRP is a common signal line that serves as both the precharge voltage power supply line SVP to which the precharge voltage VPRC is supplied and the scan voltage power supply line SVIR to which the initialization voltages VINI1 and VINI2 are supplied. In other words, the scan voltage power supply line SVIRP has a configuration that serves both as the precharge voltage power supply line SVP and the scan voltage power supply line SVIR. (3) The scan voltage power supply line SVIRP includes voltages that change with time. The voltages that change with time are a precharge voltage VPRC, an initialization voltage VINI2, and an initialization voltage VINI1. (4) The fourth scan signal SC4(n) and the sixth transistor T6 are not included. (5) The timing of the first scan signal SC1(n) is different.

[0470] The configurations of the pixel 180F and the pixel circuit 181F shown in (1) to (5), and the configurations other than those related to the configurations of the pixel 180F and the pixel circuit 181F shown in (1) to (5), are the same as those of the display device according to the second embodiment. Therefore, differences from the display device according to the second embodiment will be mainly described here. In describing the configurations and functions of the display device according to the seventh embodiment, configurations and functions that are the same as those of the display device according to the second embodiment will be described as necessary. Furthermore, configurations that are the same as or similar to those in FIGS. 1 to 46 will be described as necessary.

[0471] <7-1.Configuration of pixel 180F> An overview of the pixel 180F and pixel circuit 181F will be described with reference to FIGS.

[0472] The pixel circuit 181F is connected to the scan voltage power line SVIRP. The scan voltage power line SVIRP is a signal line that serves both as the precharge voltage power line SVR supplied to the pixel circuit 181A and the scan voltage power line SVIR. In other words, the scan voltage power line SVIRP is a signal line that combines the precharge voltage power line SVR supplied to the pixel circuit 181A and the scan voltage power line SVIR. The scan voltage power line SVIRP functions as a power line that supplies voltage to the pixel 180F and the pixel circuit 181F, and also functions as a signal line whose voltage (potential) changes over time.

[0473] A scan voltage power supply SIRP(n) is supplied to the scan voltage power supply line SVIRP. In the pixel circuit 181F, a first electrode 644 of the fourth transistor T4 and a first electrode 654 of the fifth transistor T5 are electrically connected to the scan voltage power supply line SVIRP.

[0474] For example, the scan voltage power supply line SVIRP is electrically connected to a connection line 342 that is different from the drive power supply line PVDD and the reference voltage line PVSS among the connection lines 342. Also, for example, the scan voltage power supply line SVIRP may be one of the connection lines 342.

[0475] For example, the scan voltage power supply SIRP(n) may be supplied from an external device to the IC chip 110 (see FIG. 1), similar to the precharge voltage VPRC, the initialization voltage VINI1, and the initialization voltage VINI2, or may be supplied from the IC chip 110 to the plurality of pixels 180F (pixel circuits 181F) via the connection wiring 342 and the scan voltage power supply line SVIRP. Although not shown, the scan voltage power supply SIRP(n) may be connected to the scan voltage power supply line SVIR from the external device via the FPC 200, the terminal unit 150, and the connection wiring 341, similar to the precharge voltage VPRC, the initialization voltage VINI1, and the initialization voltage VINI2, without passing through the IC chip 110 and the connection wiring 342, and may be supplied to the plurality of pixels 180F (pixel circuits 181F).

[0476] When the third transistor T3 is in a conductive state, the fourth transistor T4 is in a conductive state, and the third transistor T3 makes the second node N2 and the first node N1 conductive, electrically connecting the second node N2 and the first node N1 to the fourth transistor T4 and the scan voltage power supply line SVIRP. As a result, the third transistor T3 has the function of supplying the precharge voltage VPRC (intermediate potential) to the second node N2 and supplying the intermediate potential to the second node N2.

[0477] The fourth transistor T4 has a function of connecting the second node N2 and the scan voltage power supply line SVIRP to supply the initialization voltage VINI1 or VINI2 to the second node N2, thereby initializing the second node N2. For example, the initialization voltages VINI1 and VINI2 are constant voltages.

[0478] The fifth transistor T5 has a function of connecting the third node N3 and the scan voltage power supply line SVIRP to each other, supplying the initialization voltage VINI1 or VINI2 to the second node N2, and initializing the third node N3.

[0479] The configuration and functions of the pixel circuit 181F other than those described in "2-1. Configuration of the pixel 180F" are the same as those of the pixel circuit 181A.

[0480] <7-2. Driving method of pixel circuit 181F> A method for driving a display device according to the seventh embodiment will be described with reference to Figures 49 to 52. Configurations that are the same as or similar to those in Figures 1 to 48 will be described as necessary. As in the first embodiment, the horizontal axis of the timing chart represents time.

[0481] The method for driving a display device according to the seventh embodiment has a configuration and functions in which the operations related to the precharge voltage power supply line SVP (precharge voltage VPRC) and the scan voltage power supply line SVIR (initialization voltage VINI1 and initializing voltage VINI2) in the method for driving a display device according to the second embodiment are replaced with operations related to the scan voltage power supply SIRP(n) without including the sixth transistor T6. The configuration and functions other than the operations related to the scan voltage power supply SIRP(n) without including the sixth transistor T6 are the same as those of the method for driving a display device according to the second embodiment.

[0482] The method for driving a display device according to the seventh embodiment includes the same period as the method for driving a display device according to the third embodiment shown in FIG.

[0483] During one horizontal period (horizontal period HRP) in the driving method of the display device according to the seventh embodiment, the pixel 180F (pixel circuit 181F) receives the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fifth scan signal SC5(n), the image data signal SL(m), and the scan voltage power supply SIRP(n). For example, the pixel 180F (pixel circuit 181F) is selected in accordance with the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fifth scan signal SC5(n). The image data signal SL(m) and the scan voltage power supply SIRP(n) are input to the selected pixel 180F (pixel circuit 181F) in accordance with the timing of each signal. A similar operation is performed for all pixels 180F (pixel circuits 181F), and based on the image data signals SL(m) input to all pixels 180F (pixel circuits 181F), the image of the frame corresponding to one frame is displayed in the display area 22 of the display device according to the seventh embodiment.

[0484] For example, the voltages (potentials) supplied to the signals in each frame in the timing charts shown in FIGS.

[0485] [Table 7]

[0486] <7-2-1. First Example of Driving Method of Pixel Circuit 181F> A first example of a method for driving the pixel circuit 181F will be described with reference to Fig. 49. The first example of the method for driving the pixel circuit 181F includes displaying images of different colors in successive frames, similar to the first example of the method for driving the display device 10 according to the first embodiment.

[0487] For example, as shown in Table 7, the voltage VSIGL corresponding to black (non-emitting) is −2 V, the voltage VSIGH corresponding to emitting light is 2.0 V, the voltage VL(LO) is −5 V, the initialization voltage VINI2 (reference voltage VREF) is −1.5 V, the initialization voltage VINI1 is −3 V, and the pre-charge voltage VPRC is 0 V. The setting values ​​of the other voltages are the setting values ​​shown in Table 2 described in “2-2. Driving method of pixel circuit 181A.”

[0488] The scan voltage power supply SIRP(n) supplies a precharge voltage VPRC during the light emission period PEM of the K-1st FRAME, the period PIP of the Kth FRAME, part of the period PWR of the Kth FRAME, and the light emission period PEM of the Kth FRAME, supplies an initialization voltage VINI2 during the period PWR of the Kth FRAME, and supplies an initialization voltage VINI1 during the period PVH of the Kth FRAME.

[0489] The first scan signal SC1(n) is supplied with LO during the horizontal period HRP of the Kth FRAME, and is supplied with HI during periods other than the horizontal period HRP.

[0490] The configurations of the second scan signal SC2(n), the third scan signal SC3(n), and the fifth scan signal SC4(n) are the same as those described in "2-2-1. First example of the method for driving the pixel circuit 181A."

[0491] The configurations of the first scan signal SC1(n) to the third scan signal SC3(n) and the image data signal SL(m) in the light emission period PEM of the K-1st FRAME to the light emission period PEM of the Kth FRAME are the same as those described in "2-2-1. First example of the method of driving the pixel circuit 181A." Configurations similar to those described in "2-2-1. First example of the method of driving the pixel circuit 181A" will be explained as necessary.

[0492] During the light emission period PEM of the (K-1st) frame, the scan voltage power supply SIRP(n) is supplied with the precharge voltage VPRC (0V), and the first scan signal SC1(n) is supplied with HI. Similar to the configuration described in "2-2-1. First Example of the Driving Method of the Pixel Circuit 181A," the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are in the OFF state, and the third transistor T3 is in the ON state. Furthermore, the voltage Vna supplied to the first node N1 and the second node N2 is 7V, the voltage Vnb supplied to the third node N3 is 2.5V, and the potential difference Vgs is 4.5V. Therefore, the second transistor T2 is in the ON state, and a current Ion based on the potential difference Vgs and the potential difference Vds corresponding to the voltage VSIGH (2.0V) input during the horizontal period HRP of the (K-1st) frame can flow. Furthermore, a current Ion flows from the driving power supply line PVDD to the light emitting element OLED and the reference voltage line PVSS, causing the light emitting element OLED to emit light.

[0493] During the period PIP of the Kth FRAME following the light-emitting period PEM of the (K-1st) FRAME, the scan voltage power supply SIRP(n) maintains the state in which the precharge voltage VPRC(0V) is supplied, and the first scan signal SC1(n) maintains the state in which HI is supplied. The fourth transistor T4 and the fifth transistor T5 change from an off state to an on state, the third transistor T3 changes from an on state to an off state, and the first transistor T1 maintains the off state. As a result, the voltage supplied to the first node N1 and the voltage supplied to the second node N2 gradually drop from voltage Vna toward the precharge voltage VPRC(0V) and reach 0V, and the voltage supplied to the third node N3 gradually drops from voltage Vnb toward the precharge voltage VPRC(0V) and reach 0V. Because the potential difference Vgs is 0V and is smaller than the threshold voltage VTH, the second transistor T2 is turned off. Therefore, the current Ion does not flow from the driving power supply line PVDD to the initialization voltage power supply line SVI or the reference voltage line PVSS, and the light-emitting element OLED does not emit light.

[0494] As described above, during the period PIP, the first node N1, the second node N2, and the third node N3 are supplied with an intermediate potential by the precharge voltage VPRC (0V). Therefore, during the period PIP, the precharge voltage (intermediate potential) is supplied to the first node N1, and the second node N2 and the third node N3 are initialized by the precharge voltage VPRC (0V).

[0495] During the period PWR of the horizontal period HRP of the Kth FRAME, which follows the period PIP of the Kth FRAME, the image data signal SL(m) is supplied with the data signal VDATA of voltage VSIGL. When the fifth scan signal SC5(n) changes from LO to HI, the scan voltage power supply SIRP(n) changes from a state in which the precharge voltage VPRC (0V) is supplied to a state in which the initialization voltage VINI1 (-3V) is supplied. The first transistor T1 changes from an OFF state to an ON state, the third transistor T3 remains OFF, and the fourth transistor T4 and the fifth transistor T5 remain ON. As a result, the voltage supplied to the first node N1 gradually drops from 0V toward voltage Vnc (voltage VSIGL, -2V) and reaches voltage Vnc. The voltages supplied to the second node N2 and the third node N3 gradually drop from 0V toward voltage Vnk (initialization voltage VINI1, -3V). Also, similarly to the period PIP, the potential difference Vgs is 0 V, the second transistor T2 is in an off state, and the light-emitting element OLED does not emit light.

[0496] As described above, during the period PWR, the data signal VDATA is written to the pixel 180F (pixel circuit 181F), and the voltage supplied to the second node N2 and the voltage supplied to the third node N3 become the initialization voltage VINI1 (−3 V).

[0497] During the period PVH of the Kth FRAME following the period PWR of the horizontal period HRP of the Kth FRAME, the fourth scan signal SC4(n) changes from a HI state to a LO state. When the fourth scan signal SC4(n) changes from a HI state to a LO state, the scan voltage power supply SIRP(n) changes from an initialization voltage VINI1 (-3V) to an initialization voltage VINI2 (-1.5V). When the fifth scan signal SC5(n) changes from a HI state to a LO state, the second scan signal SC2(n) changes from a HI state to a LO state. The fifth transistor T5 changes from an ON state to an OFF state, and when the fifth transistor T5 changes from an OFF state, the first transistor T1 changes from an ON state to an OFF state. The third transistor T3 remains OFF, and the fourth transistor T4 remains ON. As a result, the voltage supplied to the first node N1 remains at voltage Vnc (voltage VSIGL, -2V), and the voltage supplied to the second node N2 gradually rises from voltage Vnk toward voltage Vnn (initialization voltage VINI2, -1.5V) and becomes initialization voltage VINI2 (voltage Vnn, -1.5V).

[0498] Immediately after the start of the period PVH, the potential difference Vgs is 0 V, the potential difference Vds is 11 V, and the second transistor T2 is in the off state. The fifth transistor T5 is also in the off state. Meanwhile, the fourth transistor T4 is in the on state, and the voltage supplied to the second node N2 increases from the voltage Vnk toward the voltage Vnn. As the voltage supplied to the second node N2 approaches −1.5 V, the potential difference Vgs exceeds the threshold voltage VTH. As a result, the second transistor T2 is turned on, and the voltage supplied to the third node N3 gradually increases.

[0499] When the potential difference Vgs becomes the threshold voltage VTH, the voltage supplied to the second node N2 and the voltage supplied to the third node N3 maintain their respective voltages at that time. For example, as shown in FIG. 49, the voltage supplied to the second node N2 is voltage Vnn, and the voltage supplied to the third node N3 is voltage Vnm (-2.5 V). Here, the potential difference Vgs is 1 V, the potential difference Vds is 10.5 V, and the potential difference Vgs is equal to the threshold voltage VTH. That is, by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, the threshold voltage VTH of the second transistor T2 is acquired, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitor CS). Furthermore, the second transistor T2 is in an off state, and no current flows from the driving power line PVDD to the reference voltage line PVSS, so that the light-emitting element OLED does not emit light.

[0500] At the end of the period PVH, the second scan signal SC2(n) changes from HI to LO, the fourth transistor T4 changes from ON to OFF, the third transistor T3 changes from OFF to ON, and the first transistor T1 and the fifth transistor T5 remain OFF.

[0501] In this way, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitive element CS).

[0502] During the light emission period PEM of the Kth FRAME following the horizontal period HRP of the Kth FRAME, when the first scan signal SC1(n) changes from HI to LO, the scan voltage power supply SIRP(n) changes from the initialization voltage VINI2 (-1.5V) to the precharge voltage VPRC (0V). The third transistor T3 remains on, while the first transistor T1, the fourth transistor T4, and the fifth transistor T5 remain off. The voltage supplied to the third node N3 rises slightly from Vnm to voltage Vne (-1V) due to capacitive coupling. As the voltage supplied to the third node N3 rises, the voltage supplied to the first node N1 and the voltage supplied to the second node N2 gradually rises toward voltage Vnf (-0.5V). Therefore, the potential difference Vgs is −0.5 V, the second transistor T2 is in an off state, and no current flows from the driving power supply line PVDD to the reference voltage line PVSS, so the light-emitting element OLED does not emit light. As a result, during the light-emitting period PEM of KthFRAME, the three pixels, which are the pixel 180F emitting red, the pixel 180F emitting blue, and the pixel 180F emitting green, are black.

[0503] The first example of the method for driving the pixel circuit 181F including the configuration described above has the same effects as the method for driving the display device according to the third embodiment.

[0504] Furthermore, pixel circuit 181F has a configuration and function in which the precharge voltage SVP and scan voltage power supply SIR(n) supplied to pixel circuit 181A are replaced with a scan voltage power supply SIRP(n) that also serves as the precharge voltage SVP and scan voltage power supply SIR(n). Furthermore, pixel circuit 181F does not include a fourth scan signal SC4(n) or a sixth transistor T6. Therefore, pixel circuit 181F has a configuration that allows for a reduction in the number of signal lines and a reduction in the number of transistors, and thus a display device including pixel circuit 181F can reduce the pixel size. As a result, a display device including pixel circuit 181F can increase the number of pixels and achieve higher resolution and larger screens.

[0505] <7-2-2. Second Example of Driving Method of Pixel Circuit 181F> A second example of a method for driving the pixel circuit 181F will be described with reference to Fig. 50. The driving method shown in the second example of the pixel circuit 181F includes displaying images of the same color (white) in consecutive frames, similar to the second example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 49 will be described as necessary.

[0506] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fifth scan signal SC5(n), the image data signal SL(m), and the scan voltage power supply SIRP(n) during the light emission period PEM of the K-1st FRAME to the light emission period PEM of the Kth FRAME are the same as those described in "7-2-1. First Example of the Method for Driving the Pixel Circuit 181F." The voltages (potentials) of each node and each transistor, as well as the operation of each transistor, during the light emission period PEM of the K-1st FRAME and the period PIP of the Kth FRAME are the same as those described in "7-2-1. First Example of the Method for Driving the Pixel Circuit 181F." Configurations similar to those described in "7-2-1. First Example of the Method for Driving the Pixel Circuit 181F" will be explained as necessary. During the horizontal period HRP, the image data signal SL(m) is supplied with a data signal VDATA including VSIGH (3.5V) corresponding to white.

[0507] In the light emitting period PEM of the K-1st FRAME, the light emitting element OLED emits light in the same manner as in the configuration described in "7-2-1. First example of the method for driving the pixel circuit 181F".

[0508] During the period PIP of the Kth FRAME following t...

Claims

1. a first transistor whose switching is controlled using a first control signal and electrically connected between an image data signal line to which a data voltage is supplied and a first node; a third transistor whose switching is controlled using a second control signal different from the first control signal, the third transistor being electrically connected between the first node and a second node; a second transistor having a gate electrode electrically connected to the second node, the second transistor being electrically connected between a power supply line to which a constant voltage is supplied and a third node; a fourth transistor whose switching is controlled using a third control signal different from the first control signal and the second control signal, and which is electrically connected between a reference voltage power supply line to which a reference voltage is supplied and the second node; a fifth transistor whose switching is controlled using a fourth control signal different from the first control signal, the second control signal, and the third control signal, and which is electrically connected between an initialization voltage power supply line to which an initialization voltage is supplied and the third node; a sixth transistor whose switching is controlled using a fifth control signal different from the first control signal, the second control signal, the third control signal, and the fourth control signal, and which is electrically connected between a precharge voltage power supply line to which a precharge voltage is supplied and the first node; a light emitting element electrically connected to the third node; a capacitance element electrically connected between the first node and the third node; Including, Display device.

2. a sixth control signal line; the sixth control signal line serves as both the reference voltage power supply line and the initialization voltage power supply line; The display device according to claim 1 .

3. the first control signal is a shifted version of the fifth control signal; The display device according to claim 1 or 2.

4. a seventh control signal line; the seventh control signal line serves as both a fourth control signal line to which the fourth control signal is supplied and a fifth control signal line to which the fifth control signal is supplied; The display device according to claim 1 or 2.

5. a control circuit that outputs the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal; The control circuit After a period in which a low-level voltage is supplied to the first control signal, the first transistor is turned off, a low-level voltage is supplied to the second control signal, the third transistor is turned off, a high-level voltage is supplied to the fifth control signal, the sixth transistor is turned on, and the precharge voltage is supplied to the first node, supplying a high-level voltage to the first control signal to turn on the first transistor, supplying a low-level voltage to the second control signal to keep the third transistor in an off state, supplying a low-level voltage to the fifth control signal to turn off the sixth transistor, and controlling the first transistor to supply the data voltage to the first node; The display device according to claim 1 .

6. The control circuit supplying a high level voltage to the third control signal and a low level voltage to the fourth control signal while supplying a high level voltage to the first control signal; maintaining the first transistor and the fourth transistor in an on state and maintaining the sixth transistor in an off state; the first transistor supplies the data voltage to the first node; the fourth transistor supplies the initialization voltage to the second node; controlling the third node to hold a charge equivalent to a threshold voltage of the second transistor; The display device according to claim 5 .

7. the first to sixth transistors are n-channel field effect transistors; The display device according to claim 1 .

8. a channel length of the second transistor is longer than a channel length of the first transistor, a channel length of the third transistor, a channel length of the fourth transistor, a channel length of the fifth transistor, and a channel length of the sixth transistor; The display device according to claim 1 .

9. a channel region of each of the first to sixth transistors includes an oxide semiconductor; The display device according to claim 1 .

10. a first conductive layer and a second conductive layer different from the first conductive layer; the initialization voltage power supply line and the precharge voltage power supply line include the first conductive layer and the second conductive layer which are different from each other; In a plan view, the first conductive layer and the second conductive layer included in the initialization voltage power supply line overlap each other, and the first conductive layer and the second conductive layer included in the precharge voltage power supply line overlap each other. The display device according to claim 1 .

11. In a plan view, the gate electrode overlaps with the capacitance element. The display device according to claim 1 .

12. a first transistor whose switching is controlled using a first control signal and electrically connected between an image data signal line to which a data voltage is supplied and a first node; a third transistor whose switching is controlled using a second control signal different from the first control signal, the third transistor being electrically connected between the first node and a second node; a second transistor having a gate electrode electrically connected to the second node, the second transistor being electrically connected between a power supply line to which a constant voltage is supplied and a third node; a fourth transistor whose switching is controlled using a third control signal different from the first control signal and the second control signal, and which is electrically connected between a scan voltage signal line to which an initialization voltage, a reference voltage, and a precharge voltage are supplied and the second node; a fifth transistor whose switching is controlled using a fourth control signal different from the first control signal, the second control signal, and the third control signal, and which is electrically connected between the scan voltage signal line and the third node; a light emitting element electrically connected to the third node; a capacitance element electrically connected between the first node and the third node; Including, Display device.

13. a control circuit that outputs the first control signal, the second control signal, the third control signal, and the fourth control signal; The control circuit After a period in which a low-level voltage is supplied to the first control signal, the first transistor is turned off, a low-level voltage is supplied to the second control signal, the third transistor is turned off, a high-level voltage is supplied to the fourth control signal, the fifth transistor is turned on, and the precharge voltage is supplied to the third node, supplying a high-level voltage to the first control signal to turn on the first transistor, supplying a low-level voltage to the second control signal to cause the third transistor to maintain an off state, supplying a high-level voltage to the fourth control signal to cause the fifth transistor to maintain an on state, and controlling the first transistor to supply the data voltage to the first node; The display device according to claim 12.

14. The control circuit supplying a high level voltage to the third control signal and a low level voltage to the fourth control signal while supplying a high level voltage to the first control signal; maintaining the first transistor and the fourth transistor in an on state and maintaining the fifth transistor in an off state; the first transistor supplies the data voltage to the first node; the fourth transistor supplies the initialization voltage to the second node; controlling the third node to hold a charge equivalent to a threshold voltage of the second transistor; The display device according to claim 13.

15. the first to fifth transistors are n-channel field effect transistors; The display device according to claim 12.

16. a channel region of each of the first to fifth transistors includes an oxide semiconductor; The display device according to claim 12.

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