Display device

Abstract

To provide a display device capable of performing appropriate display without converting an image signal.SOLUTION: In the case of high-resolution display, individual data is supplied to each pixel through the first signal line and the first transistor included in each pixel. In the case where display is performed at low resolution, the same data is supplied to the plurality of pixels through the second transistor electrically connected to the second signal line and the plurality of pixels. In a case where there are a plurality of image signals to be displayed and the corresponding resolutions are different, by switching the supply path of the image signal as described above, display can be performed without up-conversion or down-conversion.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the invention disclosed herein more specifically relates to The technical field of one aspect of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, driving method thereof, or manufacturing method thereof One example can be mentioned.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] A technology for constructing a transistor using a metal oxide formed on a substrate has been attracting attention. For example, a transistor using zinc oxide or In-Ga-Zn oxide is used for the display of a display device. The technology used for the basic switching elements is disclosed in Patent Document 1 and Patent Document 2. .

[0005] In addition, a memory device having a structure in which a transistor with extremely low off-state current is used as a memory cell is disclosed in a patent document. This is disclosed in reference 3. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-119674 Summary of the Invention [Problem to be solved by the invention]

[0007] Display devices are becoming increasingly high-resolution, with 8K4K (pixel count: 7680 x 4320) resolution or Hardware capable of displaying at higher resolutions is being developed. Since the image data for high resolution is huge, in order to popularize high resolution display devices, It is also necessary to prepare peripheral technologies such as imaging devices, storage devices, and communication devices.

[0008] In order to display the image appropriately on the display device, the image data must be adjusted to the resolution of the display device. For example, if the resolution of the display device is 8K4K and the image data is 4K2K (pixel If the image size is 3840 x 2160, you must convert the data size to 4 times the original size to display it in full screen. On the other hand, if the resolution of the display device is 4K2K and the image data is 8K4K, If it is for K, the number of data must be converted to 1 / 4.

[0009] This type of data conversion requires a dedicated circuit, which results in high power consumption. It is desirable to be able to input image data to the pixels of a display device without any conversion.

[0010] Furthermore, up-conversion is a technique for generating high-resolution image data. By converting, a low-resolution image is converted into a pseudo-high-resolution image. can be done.

[0011] However, devices that perform upconversion analyze huge amounts of image data to generate new image data. However, since the data is generated, the circuit scale and power consumption are large. The processing may not be able to keep up, resulting in display delays.

[0012] Up-conversion has such problems, but for example, By distributing the functions across multiple devices, it may be possible to mitigate issues such as power consumption and latency. do.

[0013] Therefore, in one aspect of the present invention, a display device capable of appropriately displaying image data without converting the image data is provided. Another object of the present invention is to provide a display device capable of image processing. One of the purposes is to provide a display device that can perform up-conversion. Another object of the present invention is to provide a display device that can display two images in an overlapping manner. One of the objectives is to

[0014] Another object is to provide a display device with low power consumption. One of the purposes is to provide a new display device. Another object of the present invention is to provide a method for driving the display device. Another object is to provide a novel semiconductor device or the like.

[0015] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0016] One aspect of the present invention relates to a display device that can appropriately display image data without converting the image data. The present invention relates to a display device capable of performing image processing.

[0017] One embodiment of the present invention is a display device including a first transistor and first to fourth circuits. Each of the first to fourth circuits includes a second transistor and a first capacitor. The second transistor has a source and a drain. The first capacitor element is electrically connected to one electrode of the first capacitor element. The other electrode of the first capacitor is electrically connected to the first transistor. The display device is electrically connected to either the source or the drain.

[0018] The second transistor has a metal oxide in a channel formation region, and the metal oxide contains In and Zn and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf) , preferably having

[0019] The gate of the second transistor included in the first circuit and the gate of the second transistor included in the second circuit are connected to each other. the gate of the second transistor in the third circuit is electrically connected to the gate of the first transistor in the third circuit; The gates of the second transistors included in the circuit of No. 4 can be electrically connected.

[0020] The other of the source and the drain of the second transistor included in the first circuit is connected to the third The other of the source and the drain of the second transistor included in the circuit is electrically connected to The other of the source or drain of the second transistor included in the circuit and the The other of the source and the drain of the second transistor can be electrically connected.

[0021] Each of the first to fourth circuits has a function of a pixel arranged in a matrix, The first circuit is placed in the nth row and ith column (n and i are natural numbers), and the second circuit is placed in the nth row (i+x) The third circuit is placed in the (n+1)th row and the i-th column, and the fourth circuit is placed in the (n+1)th row and the i-th column. can be placed in the (n+1)th row and (i+x)th column.

[0022] The circuit block includes a third transistor, a fourth transistor, a second capacitive element, and a and an organic EL element, one electrode of which is connected to the source or is electrically connected to one of the drains of the fourth transistor and the other of the source or drain of the fourth transistor. The first electrode is electrically connected to one electrode of the second capacitor element. , electrically connected to one of the source and drain of the third transistor, The gate of the transistor is electrically connected to the other electrode of the second capacitor element. The other electrode may be electrically connected to one electrode of the first capacitor. can.

[0023] In the above configuration, the fifth transistor and the fifth circuit are further included. One of the source or drain of the first transistor is connected to the source or drain of the fourth transistor. The other of the source and drain of the fifth transistor is electrically connected to the fifth transistor. It may be electrically connected to the circuit.

[0024] The fifth circuit can have the function of supplying a constant potential or reading a current value. The function may include generating correction data.

[0025] The circuit block also includes a sixth transistor, a third capacitor, and a liquid crystal element. One electrode of the liquid crystal element is electrically connected to one electrode of the capacitor element. The electrode of the sixth transistor is electrically connected to one of the source and drain of the sixth transistor. The other of the source and the drain of the transistor is electrically connected to one electrode of the first capacitor. The configuration may be such that the signal is connected to the

[0026] The sixth transistor has a metal oxide in a channel formation region, and the metal oxide contains In and Zn and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf) , preferably having

[0027] Another embodiment of the present invention is a semiconductor device including a first transistor, a first circuit, a second circuit, and a third circuit. A display device having three circuits, a first wiring, a second wiring, and a third wiring, Each of the first to third circuits includes a second transistor, a first capacitor, and a a first capacitance element, and one of the source and drain of the second transistor is connected to the first capacitance element. One electrode of the first capacitor element is electrically connected to one electrode of the display element. The first to third circuits are connected to each other in one direction, and the first to third circuits are arranged adjacent to each other in one direction. A first wiring is provided between the first circuit and the second circuit, and a second wiring is provided between the second circuit and the third circuit. The second wiring and the third wiring are provided in the second circuit. The first wiring is connected to the second the second wiring is electrically connected to the other of the source and drain of the third transistor, the other of the source and the drain of the second transistor included in the circuit; the third wiring is electrically connected to one of the source and the drain of the first transistor; The other of the source and the drain of the first transistor is connected to any one of the first to third circuits. The display device is one in which the other electrode of the first capacitor is electrically connected to the other electrode of the first capacitor.

[0028] Another embodiment of the present invention is a semiconductor device including a first transistor, a first circuit, a second circuit, and a third circuit. A display having three circuits, a first wiring, a second wiring, a third wiring, and a fourth wiring. The device, wherein each of the first circuit to the third circuit includes a second transistor and a first a capacitor element, a second capacitor element, and a display element; One of the drains is electrically connected to one electrode of the first capacitor element. One electrode of the second capacitor is electrically connected to one electrode of the second capacitor. The first electrode is electrically connected to the display element, and the first to third circuits are arranged in one direction. The first circuit and the second circuit are arranged adjacent to each other, and a first wiring and a second wiring are provided between the first circuit and the second circuit. A wiring is provided, and a third wiring and a fourth wiring are provided between the second circuit and the third circuit. The first wiring is connected to the source or drain of a second transistor included in the second circuit. the second wiring is electrically connected to the other of the second capacitor elements included in the first circuit, The second wiring is electrically connected to the other of the second capacitors included in the second circuit. The third wiring is connected to the source or drain of the second transistor included in the third circuit. The fourth wiring is electrically connected to the source or drain of the first transistor. The other of the source and drain of the first transistor is electrically connected to the second transistor. The other electrode of the first capacitor included in any of the first to third circuits is electrically connected to the other electrode of the first capacitor included in any of the first to third circuits. It is a display device. [Effects of the Invention]

[0029] By using one embodiment of the present invention, a display device that can appropriately display image data without converting the image data can be provided. Alternatively, a display device capable of performing image processing can be provided. Alternatively, a display device capable of up-conversion can be provided. can provide a display device that can display two images superimposed on each other.

[0030] Alternatively, a display device with low power consumption can be provided. Alternatively, a novel display device or the like can be provided. Furthermore, a method for driving the display device can be provided. Alternatively, a novel semiconductor device or the like can be provided. It can be provided. [Brief explanation of the drawings]

[0031] [Figure 1] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 2] 4 is a timing chart illustrating the operation of the pixel circuit. [Figure 3] FIG. 1 is a diagram illustrating up-conversion. [Figure 4] FIG. 2 is a diagram illustrating a circuit block. [Figure 5] FIG. 2 is a diagram illustrating a circuit block. [Figure 6] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 7] FIG. 1 is a block diagram illustrating a display device. [Figure 8] FIG. 1 is a diagram illustrating an example of the configuration of a neural network. [Figure 9] FIG. 1 is a block diagram illustrating a display device. [Figure 10] FIG. 2 is a diagram illustrating the configuration of a pixel used in a simulation. [Figure 11] FIG. 10 is a diagram illustrating the results of a simulation. [Figure 12] FIG. 10 is a diagram illustrating the results of a simulation. [Figure 13] FIG. 10 is a diagram illustrating the results of a simulation. [Figure 14] FIG. 2 is a diagram illustrating the configuration of a pixel. [Figure 15] FIG. 2 is a diagram illustrating the configuration of a pixel. [Figure 16] 1A and 1B are diagrams illustrating a display device. [Figure 17] FIG. 2 is a diagram illustrating a touch panel. [Figure 18] 1A and 1B are diagrams illustrating a display device. [Figure 19] 1A and 1B are diagrams illustrating a transistor. [Figure 20] 1A and 1B are diagrams illustrating a transistor. [Figure 21] 1A and 1B are diagrams illustrating a transistor. [Figure 22] 1A and 1B are diagrams illustrating a transistor. [Figure 23] 1A to 1C illustrate electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0032] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0033] (Embodiment 1) In this embodiment, a display device which is one embodiment of the present invention will be described with reference to drawings.

[0034] One aspect of the present invention is to perform upconversion for two image data sets, one for high resolution and one for low resolution. This is a display device that can display properly without up-conversion or down-conversion. When displaying at a high resolution, the first data line and the first transistor of each pixel are connected via a path. For lower resolutions, the second data line and and a second transistor electrically connected to the plurality of pixels, and Provides data for:

[0035] When there are multiple image data to be displayed and the corresponding resolutions are different, By switching the data supply path, you can up-convert or down-convert. It is possible to display without any problems.

[0036] Here, high resolution image data is, for example, 8K4K (pixel count: 7680 x 4320 ) In addition, low-resolution image data corresponds to, for example, 4K2K This corresponds to data with an amount of information corresponding to (number of pixels: 3840 x 2160). The number of effective data for high-resolution image data and low-resolution image data (corresponding to the number of effective pixels) ) is assumed to be in a 4:1 ratio.

[0037] If the ratio of the number of data (number of pixels) is 4:1, it is not limited to the above example, and can be used for high-resolution images. The image data corresponds to 4K2K, and the image data for low resolution is FullHD (number of pixels It may also be data corresponding to a high resolution image (1920 x 1080). The data corresponds to 16K8K (pixel count: 15360 x 8640), and the image data is for low resolution. The image data may be data corresponding to 8K4K.

[0038] Each pixel is provided with a storage node, and the storage node can store first data. The first data is generated by an external device and can be written to each pixel. The data can be added to the second data by capacitive coupling and supplied to the display element. writes second data to the storage node and then adds first data by capacitive coupling. It is also possible.

[0039] Therefore, the display device can display a corrected image. Even when displaying at a low resolution as described above, it is possible to upconvert the image within the pixel. Or, you can correct a part or the whole image in the display area to achieve a wide dynamic range. Alternatively, different values ​​can be displayed as the first data and the second data. By using the image data, any image can be displayed in an overlapping manner.

[0040] FIG. 1 shows a part of a pixel array arranged in a matrix in a display device according to one embodiment of the present invention. A pixel 10 includes a transistor 102 and a capacitance element 103. 03 and a circuit block 110. The circuit block 110 includes transistors, capacitors, and The details will be described later. In the parentheses, n and m represent specific rows, and i and j represent specific columns.

[0041] The pixels 10 are arranged in a matrix, and are arranged in the nth row and the ith column (n and i are natural numbers equal to or greater than 1). , nth row (i+x)th column (x is a natural number greater than or equal to 1), (n+1)th row i-th column and (n+1)th row It can be placed in the (i+x)th column. In Figure 1, the placement when x=1 is shown. There are.

[0042] The pixel array also includes transistors 101 electrically connected to the four pixels 10. The transistor 101 is arranged differently from the pixel 10, and is located in the mth row and jth column (m and j are 1 or greater). The mth row is placed between the nth row and the n+1th row. It is also preferable that the Jth column is provided between the ith column and the (i+x)th column. The transistor 101 is an element of each pixel 10 and is shared by each pixel. It can also be said that.

[0043] One of the source and drain of the transistor 102 is connected to one electrode of the capacitor 103. One electrode of the capacitor 103 is electrically connected to the circuit block 110. The other electrode of the capacitor 103 is connected to the source or drain of the transistor 101. One is electrically connected to the other.

[0044] Here, one of the source and drain of the transistor 102 and one of the voltages of the capacitor 103 The pole and the wiring to which the circuit block are connected are called nodes NM. The elements of the circuit block 110 that control the node NM can float.

[0045] The gate of the transistor 102 is electrically connected to the wiring 121. The gate of the transistor 102 is electrically connected to a wiring 122. The other input is electrically connected to a wiring 124. The other end of the drain is electrically connected to the wiring 125 .

[0046] The wirings 121 and 122 function as signal lines for controlling the operation of the transistors. The wirings 124 and 125 are signal lines for supplying image data or correction data. The wiring 124 can also function as a It can also be said to be a signal line.

[0047] The node NM is a storage node, and when the transistor 102 is turned on, a The supplied data can be written to the node NM. By using a transistor with a low current, the potential of the node NM can be maintained for a long time. The transistor may include, for example, a transistor using a metal oxide for a channel formation region. An OS transistor can be used.

[0048] In addition to the transistor 102, other transistors constituting the pixel may be subjected to OS transistors. Alternatively, the transistor 102 may have Si in a channel formation region. Alternatively, an OS transistor may be used. It is also possible to use both a silicon transistor and a silicon transistor. Amorphous silicon transistors, crystalline silicon (typically low-temperature poly Examples include transistors using silicon (silicon, single crystal silicon).

[0049] The semiconductor material used for the OS transistor has an energy gap of 2 eV or more. Metal oxides having a specific resistance of 2.5 eV or more, more preferably 3 eV or more, can be used. A typical example is an oxide semiconductor containing indium, for example, a CAAC -OS or CAC-OS can be used. CAAC-OS forms a crystal. The atoms are stable, making it suitable for transistors where reliability is important. Because it exhibits high mobility, it is suitable for use in transistors that operate at high speed.

[0050] OS transistors have a large energy gap and therefore exhibit extremely low off-state current. In addition, OS transistors have the following drawbacks: impact ionization, avalanche breakdown, and short-channel It has characteristics different from Si transistors, such as no effects, and can form highly reliable circuits. It can be achieved.

[0051] The semiconductor layer of the OS transistor is made of, for example, indium, zinc, and M (aluminum). , titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium In-M-Zn oxides containing metals such as tin, neodymium, or hafnium The film can be made of a material such as a silicon dioxide film.

[0052] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn oxide, The atomic ratio of the metal elements in the sputtering target used to form a film is In≧M It is preferable that Zn≧M is satisfied. The atomic ratios were In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In :M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4. 1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5: The atomic ratio of the semiconductor layers to be formed is preferably 1:8 or the like. This includes a ±40% variation in the atomic ratio of metal elements contained in the ring target.

[0053] The semiconductor layer is made of an oxide semiconductor with a low carrier density. Carrier density is 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3 Further details are as follows: Preferably 1 x 10 13 / cm 3 Less than 1×10, more preferably 11 / cm 3 Below, further Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than career secrets Such an oxide semiconductor can be a highly pure intrinsic or The oxide semiconductor is called a substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and It can be said that this is an oxide semiconductor with stable characteristics.

[0054] However, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (e.g., the mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer must be carefully considered. It is preferable to appropriately set the density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. stomach.

[0055] In the oxide semiconductor that constitutes the semiconductor layer, silicon and carbon, which are group 14 elements, If oxygen is contained, oxygen vacancies increase, causing the semiconductor layer to become n-type. The concentrations of phosphate and carbon (obtained by secondary ion mass spectrometry) were measured at 2 × 10 18 atom s / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0056] In addition, alkali metals and alkaline earth metals generate carriers when bonded with oxide semiconductors. This may result in an increase in the off-state current of the transistor. The concentration of alkali metals or alkaline earth metals in the conductor layer (measured by secondary ion mass spectrometry) The concentration obtained is 1 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 a toms / cm 3 Do the following:

[0057] In addition, if nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, electrons, which are carriers, This increases the carrier density and makes it easier to become n-type. Transistors using conductors tend to be normally-on. The nitrogen concentration (obtained by secondary ion mass spectrometry) was 5 x 10 18 atoms / cm 3 It is preferable to do the following:

[0058] The semiconductor layer may also have a non-single crystal structure, for example. The non-single crystal structure may have a c-axis orientation. CAAC-OS (C-Axis Aligned Crystalline ne Oxide Semiconductor), polycrystalline, microcrystalline, or non-crystalline Among non-single crystalline structures, the amorphous structure has the highest defect level density and CAA C-OS has the lowest density of defect states.

[0059] An amorphous oxide semiconductor film has, for example, a disordered atomic arrangement and does not contain crystalline components. Alternatively, the amorphous oxide film may have a completely amorphous structure and no crystalline portion. stomach.

[0060] The semiconductor layer may have an amorphous structure, a microcrystalline structure, a polycrystalline structure, or a CAAC structure. The film may be a mixed film having two or more of the -OS region and the single crystal structure region. The film may have a single layer structure including two or more of the above-mentioned regions, or a laminated structure. It may have a structure.

[0061] Hereinafter, we will discuss CAC (Cloud-Aligned C), which is one type of non-single-crystal semiconductor layer. This section explains the structure of the .NET composite OS.

[0062] CAC-OS is a type of oxide semiconductor in which the elements constituting the oxide semiconductor are 0.5 nm to 10 nm thick. Preferably, the material is unevenly distributed in a size range of 1 nm to 2 nm or in the vicinity thereof. In the following, it is assumed that one or more metal elements are contained in the oxide semiconductor. The region containing the metal element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm A mixed state of particles with sizes of 2 nm or less or close to that size is called a mosaic or patch state. It is also called.

[0063] Note that the oxide semiconductor preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Contains one or more selected from tantalum, tungsten, magnesium, etc. It may be included.

[0064] For example, CAC-OS made of In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS) α-Zn oxide may be specifically referred to as CAC-IGZO. (Hereinafter, InO X1 (X1 is a real number greater than 0) or indium zinc oxide In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) . ), or gallium zinc oxide (Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 is a real number greater than 0.) The material is separated into two parts, forming a mosaic pattern. Mosaic InO X1 , or In X2 Zn Y2 O Z2is uniformly distributed in the film This is a cloud-like configuration (hereinafter also referred to as "cloud-like").

[0065] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Compared to region 2, the concentration of In is higher.

[0066] IGZO is a common name and refers to a compound of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include:

[0067] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0068] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. In a material composition containing Ga, Zn, and O, some nanoparticles with Ga as the main component were observed. The region where the In nanoparticles are observed is shown in part. This refers to a structure in which the pixels are randomly distributed in a mosaic pattern. The crystal structure is a secondary factor.

[0069] It should be noted that the CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, is not included. do not have.

[0070] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the main component region and the main component region cannot be observed.

[0071] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected elements such as sodium are included, CAC-OS will The nanoparticle-like regions are observed in the region where the metal element is the main component, and the region where In is the main component. The nanoparticle-like regions are randomly dispersed in a mosaic pattern. say.

[0072] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas is The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. One or more of these may be used. The lower the flow rate ratio of the gas, the more preferable. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. It is more preferable to set the content to 0% or more and 10% or less.

[0073] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, from the X-ray diffraction, the measurement region It can be seen that no orientation in the ab plane direction or the c axis direction is observed.

[0074] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron diffraction pattern obtained by irradiating the sample, a ring-shaped region with high brightness and the corresponding Several bright spots are observed in the ring region. Therefore, the electron diffraction pattern indicates that the CAC- The crystal structure of OS is nc(nan It can be seen that the crystalline structure is o-crystal.

[0075] For example, in the CAC-OS of In-Ga-Zn oxide, energy dispersive X Energy Dispersive X-ray spectroscopy (EDX) EDX mapping obtained using scopy revealed that GaO X3 The region where is the principal component And, In X2 Zn Y2 O Z2 , or InO X1 The area where the main component is unevenly distributed and mixed It can be confirmed that the compound has a structure similar to that of the compound shown in FIG.

[0076] CAC-OS has a structure different from that of IGZO compounds, in which metal elements are uniformly distributed. CAC-OS has different properties from ZO compounds. X3 The main ingredients are In a certain area, X2 Zn Y2 O Z2 , or InO X1 The region where is the principal component and The phases are separated into two, and the regions containing each element as the main component are arranged in a mosaic pattern.

[0077] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y 2O Z2 , or InO X1 The carriers flow through the region where the main component is oxidized. Therefore, the conductivity of In is expressed as a semiconductor. X2 Zn Y2 O Z2 , or In O X1 The region where the main component is distributed in a cloud-like shape in the oxide semiconductor allows for a high electric field. Effective mobility (μ) can be achieved.

[0078] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InO X This region has higher insulating properties than the region where GaO is the main component. X3 etc. The distribution of the main component in the oxide semiconductor suppresses leakage current and provides good switching. Switching operation can be realized.

[0079] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by And, In X2 Zn Y2 O Z2 , or InO X1 The conductivity caused by the This results in a high on-state current (I on ) and high field-effect mobility (μ) This can be done.

[0080] Furthermore, semiconductor devices using CAC-OS have high reliability. , and is suitable as a constituent material for various semiconductor devices.

[0081] First, using the timing charts shown in FIGS. 2(A1) and 2(A2), This operation is performed, for example, when the number of pixels is 8K4. It is a display device that supports 8K and inputs high-resolution image data (8K4K data). Although the explanation will be given for one pixel 10, the same applies to the other pixels 10. The following behavior can be applied.

[0082] In the following explanation, high potential is referred to as "H", low potential as "L", and a specific voltage between high potential and low potential is referred to as "L". The potential is expressed as "M". Note that "M" is a reference potential such as 0V or GND. However, other potentials may be used. ", and the correction data for high resolution is "Vp1". Note that "VsH" is an arbitrary first data. The data "Vp1" can also be called any second data.

[0083] First, the operation of writing image data (VsH) to the node NM will be explained using FIG. 2(A1). In this case, the distribution, coupling, or loss of potential is affected by the circuit configuration and operation timing. The detailed changes due to the capacitive coupling are not taken into account. Although it depends on the capacitance ratio on the supply side, for clarity of explanation, the capacitance value of node NM is assumed to be sufficiently small. Assume a low value.

[0084] At time T1, the potential of the wiring 121 is set to "H", the potential of the wiring 122 is set to "H", and the potential of the wiring 124 is set to "H". When the potential of the wiring 125 is set to "M", the transistor 101 is turned on. The potential of the other electrode of the element 103 becomes "M." This operation is performed as a correction operation (capacitive coupling operation) later. ) is a reset operation to perform

[0085] Furthermore, the transistor 102 is turned on, and the potential of the wiring 124 (image data “Vs H”) is written.

[0086] At time T2, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", and the potential of the wiring 124 is set to "L". When the potential of the wiring 125 is “M”, the transistor 101 and the transistor 1 02 becomes non-conductive, and image data "VsH" is held at node NM.

[0087] This is the write operation of the image data "VsH". Next, using FIG. 2(A2), , the correction operation of the image data “VsH” and the display on the display element of the circuit block 110 The operation will be explained.

[0088] The operations of (A1) and (A2) in FIG. 2 can be performed continuously within one horizontal period. The action in Fig. 2(A1) is performed in the kth frame (k is a natural number), and the action in Fig. 2(A2) is performed in the kth frame. You can also do this with a +1 frame.

[0089] At time T11, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "H", and the potential of the wiring 124 is set to "H". When the potential of the wiring 125 is "Vp1", the transistor 101 is turned on. The potential "Vp1" of the wiring 125 is added to the potential of the node NM by the capacitive coupling of the element 103. Here, "Vp1" is the correction data, and the node NM is the data corrected to the image data "VsH". The potential becomes "VsH+Vp1" to which positive data "Vp1" is added.

[0090] At time T12, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", and the potential of the wiring 124 is set to "L". When the potential of the wiring 125 is set to "M", the transistor 101 is turned off. The potential of the node NM is maintained at "VsH+Vp1."

[0091] Thereafter, the display element included in the circuit block 110 displays a display according to the potential of the node NM. Depending on the configuration of the circuit block, the display may start from time T1 or time T11. Sometimes it performs an action.

[0092] By performing correction on selected pixels in this way, it is possible to display images with a wide dynamic range. The correction data "Vp1" has the same value for all four pixels, but the difference in brightness and darkness can be Furthermore, if no correction is made, the wiring Alternatively, the potential of the wiring 122 may be set to "L" and the potential of the wiring 125 may be set to "M". The transistor 101 should not be conductive.

[0093] Next, using the timing charts shown in FIGS. 2(B1) and 2(B2), the four pixels 10 are simultaneously This operation is performed, for example, when the number of pixels corresponds to 8K4K. A display device that corresponds to the case where low-resolution image data (4K2K data) is input. do.

[0094] First, the operation of writing the correction data (Vp2) to the node NM will be explained using FIG. 2(B1). In the following, the image data for low resolution is called "VsL" and the correction data for low resolution is called "Vp 2". Note that "VsL" is any first data, and "Vp2" is any second data. It is also possible to say this.

[0095] At time T1, the potential of the wiring 121 is set to "H", the potential of the wiring 122 is set to "H", and the potential of the wiring 124 is set to "H". When the potential of the wiring 125 is set to "M", the transistor 101 is turned on. The potential of the other electrode of the element 103 becomes "M." This operation is performed as a correction operation (capacitive coupling operation) later. ) is a reset operation to perform

[0096] Also, the transistor 102 is turned on, and the potential of the wiring 124 (correction data “Vp 2") is written.

[0097] At time T2, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", and the potential of the wiring 124 is set to "L". When the potential of the wiring 125 is “M”, the transistor 101 and the transistor 1 02 becomes non-conductive, and image data "Vp2" is held at node NM.

[0098] This completes the write operation of the correction data "Vp2". Next, using Figure 2 (B2), , the correction operation of the image data “VsL” and the display on the display element of the circuit block 110 The operation will be explained.

[0099] The operations of (B1) and (B2) in FIG. 2 can be performed continuously within one horizontal period. 2(B1) is performed in the kth frame, and the operation of Fig. 2(B2) is performed in the k+1th frame. You may go.

[0100] At time T11, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "H", and the potential of the wiring 124 is set to "H". When the potential of the wiring 125 is set to "VsL", the transistor 101 is turned on. The potential "VsL" of the wiring 125 is added to the potential of the node NM by the capacitive coupling of the element 103. Here, "VsL" is the image data, and the node NM is the image data to be corrected by "Vp2". The potential becomes "Vp2+VsL" to which the image data "VsL" is added.

[0101] At time T12, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", and the potential of the wiring 124 is set to "L". When the potential of the wiring 125 is set to "M", the transistor 101 is turned off. The potential of the node NM is maintained at "Vp2+VsL."

[0102] Thereafter, the display element included in the circuit block 110 displays a display according to the potential of the node NM. Depending on the configuration of the circuit block, the display operation may start from time T11. There are also.

[0103] As the correction data "Vp2", different values ​​can be input to each pixel 10. Even if the image data "VsL" is the same, different displays can be performed at each pixel 10. If no correction is performed, the wiring Alternatively, at time T11, the potential of the wiring 125 may be maintained at "M". Alternatively, the potential of the wiring 122 may be set to "L" to turn on the transistor If correction is not performed, the same image can be displayed using four pixels. This can be done.

[0104] By operating in this way, the original image data can be up-converted or down-converted. The data can be input to the display device without having to be transferred, and the appropriate display can be performed. In addition, appropriate correction can be made to the image display.

[0105] Here, the up-conversion operation when low-resolution image data is input is shown in Figure 3. This will be explained using (A) and (B).

[0106] For example, the number of pixels on an 8K4K display device is four times that of a 4K2K display device. In other words, image data displayed in one pixel on a 4K2K display device is simply displayed on an 8K4K display device. When you try to display it, the same image data will be displayed using four pixels in the horizontal and vertical directions.

[0107] FIG. 3A is a diagram illustrating images with and without upconversion. From the left, the original image (image Data S1) displayed on one pixel for a 4K2K display device, without upconversion Image data S1 is displayed on four pixels for an 8K4K display device. This is a diagram showing image data S0 to S2 displayed on four pixels for an 8K4K display device. .

[0108] As shown in FIG. 3(A), before up-conversion, image data S1 is After up-conversion, the image data S0 to S10 are displayed in each pixel. S2 can be applied to improve resolution.

[0109] FIG. 3B is a diagram illustrating the up-conversion operation in the pixel 10. As mentioned above, any correction data can be added to the image data. The original image data S1 is supplied to each pixel as is.

[0110] Furthermore, W1 to W3 are supplied to each pixel as correction data. The method of generating the correction data is not limited. The correction data can be generated in real time using an external device. Alternatively, the correction data stored in the recording medium may be read out and synchronized with the image data S1. It is also acceptable to do so.

[0111] Then, by performing the above-described operation of the pixel 10, the image data S1 supplied to each pixel Each correction data (W1, W2, or W3) is added to the new image data S0 to S2. Therefore, the original image data S1 is up-converted and displayed. can be done.

[0112] Conventional up-conversion using external correction generates new image data itself. On the other hand, in one aspect of the present invention, the image data to be supplied is The external data is not changed, and new image data is generated using the pixels to which the correction data is supplied. This reduces the burden on the device. Also, the new image data can be generated by pixels. The operation can be performed in a few steps, and it is compatible with display devices with a large number of pixels and a short horizontal period. It is possible.

[0113] Although up-conversion has been described above as an example, this operation can also be performed by converting two pieces of image data. This can be applied to all operations that add and display. For example, It may be applied to the operation of displaying overlapping images. It may also be applied to the operation of overlapping different images. It may also be used.

[0114] 4A to 4C are applicable to the circuit block 110 and include an EL element as a display element. This is an example of a configuration that includes:

[0115] The structure shown in FIG. 4A includes a transistor 111, a capacitor 113, and an EL element 114. One of the source and drain of the transistor 111 is connected to one of the EL elements 114. One electrode of the EL element 114 is electrically connected to one electrode of the capacitor 113. The other electrode of the capacitor 113 is electrically connected to the gate of the transistor 111. The gate of the transistor 111 is electrically connected to the node NM. .

[0116] The other of the source and the drain of the transistor 111 is electrically connected to a wiring 128. The other electrode of the EL element 114 is electrically connected to a wiring 129. For example, the wiring 128 can supply high potential power. In addition, the wiring 129 can supply a low potential power supply.

[0117] In this configuration, when the potential of the node NM becomes equal to or higher than the threshold voltage of the transistor 111, Therefore, a current flows through the EL element 114 at the timing shown in FIGS. In some cases, the EL element 114 starts emitting light at time T1 in the timing chart. It is preferable to use it for fast operations.

[0118] FIG. 4B shows a configuration in which a transistor 112 is added to the configuration of FIG. 4A. One of the source or drain of transistor 112 is connected to the source or drain of transistor 111. The other of the source and drain of the transistor 112 is electrically connected to The gate of the transistor 112 is electrically connected to the wiring 126. The wiring 126 serves as a signal line for controlling the conduction of the transistor 112. It can have a function.

[0119] In this configuration, regardless of the potential of the node NM, the EL element Therefore, a current flows through 114. The EL element 114 can start emitting light after time T12, which is suitable for operation involving correction. are.

[0120] FIG. 4C shows a configuration in which a transistor 115 is added to the configuration of FIG. 4B. One of the source or drain of transistor 115 is connected to the source or drain of transistor 111. The other of the source and drain of the transistor 115 is electrically connected to The gate of the transistor 115 is electrically connected to the wiring 131. The wiring 131 functions as a signal line that controls the conduction of the transistor 115. Note that the gate of the transistor 115 is electrically connected to the wiring 122. This may continue.

[0121] The wiring 130 can be connected to the circuit 120 and can acquire the electrical characteristics of the transistor 111. In addition, the wiring 130 functions as a monitor line for detecting the voltage Vcc of the transistor 115. By supplying a specific potential to either the source or the drain of the transistor 111, This also makes it possible to stabilize the writing of image data.

[0122] When the wiring 130 is made to function as a monitor line, the above-mentioned correction data (Vp2) is A potential for correcting the threshold voltage of the transistor 111 can be generated by the circuit 120 .

[0123] 5A to 5C are applicable to the circuit block 110 and include a liquid crystal element as a display element. This is an example of a configuration that includes:

[0124] The structure shown in FIG. 5A includes a capacitor 116 and a liquid crystal element 117. One electrode of the capacitor 7 is electrically connected to one electrode of the capacitor 116. One electrode of the transistor is electrically connected to a node NM.

[0125] The other electrode of the capacitor 116 is electrically connected to the wiring 132. One electrode is electrically connected to a wiring 133. The wirings 132 and 133 function to supply power. For example, the wirings 132 and 133 may be connected to a reference potential such as GND or 0V or to an arbitrary potential. can be supplied.

[0126] In this configuration, when the potential of the node NM becomes equal to or higher than the threshold voltage for operating the liquid crystal element 117, the liquid crystal element The operation of the crystal element 117 is started. Therefore, the timing shown in FIG. The display operation may start at time T1 in the timing chart, and it is used for operations without correction. However, in the case of a transmission type liquid crystal display device, the By combining this with other operations such as turning off the backlight until time T12, unnecessary display operations can be avoided. Even if an operation is performed, it can be prevented from being seen.

[0127] FIG. 5B shows a configuration in which a transistor 118 is added to the configuration of FIG. 5A. One of the source and drain of the capacitor 118 is electrically connected to one electrode of the capacitor element 116. The other of the source and drain of the transistor 118 is electrically connected to the node NM. The gate of the transistor 118 is electrically connected to the wiring 126. 26 can function as a signal line that controls the conduction of the transistor 118. .

[0128] In this configuration, when the transistor 118 is turned on, the potential of the node NM is applied to the liquid crystal element 117. Therefore, at time T1 in the timing chart shown in FIGS. The liquid crystal element can start operating after 2, making it suitable for operation with correction.

[0129] When the transistor 118 is off, the voltage supplied to the capacitor element 116 and the liquid crystal element 117 is Since the supplied potential is maintained, the capacitor element 116 and the It is preferable to reset the potential supplied to the liquid crystal element 117. For example, a reset potential is supplied to the wiring 124, and the transistors 102 and 118 are turned on. are simultaneously made conductive.

[0130] FIG. 5C shows a configuration in which a transistor 119 is added to the configuration of FIG. 5B. One of the source and drain of the transistor 119 is electrically connected to one electrode of the liquid crystal element 117. The other of the source and the drain of the transistor 119 is electrically connected to a wiring 130. The gate of the transistor 119 is electrically connected to a wiring 131. 1 can function as a signal line for controlling the conduction of the transistor 119. The gate of the transistor 119 may be electrically connected to the wiring 122.

[0131] The circuit 120 electrically connected to the wiring 130 is the same as that described above with reference to FIG. In addition, the potential supplied to the capacitor element 116 and the liquid crystal element 117 is reset. It may be possible.

[0132] As shown in FIGS. 6A and 6B, the transistors 101 and 102 have back gates. FIG. 6(A) shows a configuration in which the back gate is electrically connected to the front gate. This has the effect of increasing the on-state current. The transistor is electrically connected to a wiring 134 that can supply a constant potential. The threshold voltage of the capacitor can be controlled. The transistors included in the circuit blocks 110 shown in (a) to (c) are also provided with back gates. Good too.

[0133] FIG. 7 is an example of a block diagram of a display device according to one embodiment of the present invention. A pixel array 11 in which pixels 0 are arranged in a matrix, row drivers 12 and 13, and column drivers The circuit has drivers 14 and 15, a circuit 16, and selection circuits 17 and 18.

[0134] The row drivers 12 and 13 and the column drivers 14 and 15 are each provided with, for example, a shift register circuit. The circuit 16 has a function of generating correction data. The circuit 16 can also be considered an external device for generating correction data.

[0135] The row driver 12 is electrically connected to the wiring 121 and controls the conduction of the transistor 102. The row driver 13 is electrically connected to the wiring 122, and the transistor 10 The column driver 14 is electrically connected to the wiring 124. The column driver 15 is electrically connected to the wiring 125 .

[0136] The circuit 16 receives image data for high resolution "VsH" (for example, 8K4K data) or low Image data for resolution "VsL" (for example, 4K2K data) is input via When the data "VsH" is input, the correction data "Vp1" is generated and the selection circuit 18 When the image data "VsL" is input, the correction The data “Vp2” is generated and output to the column driver 14 via the selection circuit 17.

[0137] The image data "VsH" is input to the column driver 14 via the selection circuit 17. The image data "VsL" is input to the column driver 15 via the selection circuit 18. In addition, the correction data Vp1 and Vp2 can be input from the outside. In this case, the column driver 14 or the column driver 15 is connected to the selection circuit 17 or the selection circuit 18. This can be entered into Iba 15.

[0138] The circuit 16 may include a neural network. For example, a large number of images may be used as a training data. By using a deep neural network trained as data, highly accurate correction data can be obtained. Data can be generated.

[0139] As shown in Figure 8(A), the neural network NN consists of an input layer IL, an output layer OL, and an intermediate layer OL. It can be composed of an input layer IL, an output layer OL, and an intermediate layer HL. Each layer has one or more neurons (units). The neural network may have two or more hidden layers HL. The network can also be called a DNN (deep neural network), and Learning using neural networks can also be called deep learning.

[0140] Input data is input to each neuron in the input layer IL, and previous data is input to each neuron in the hidden layer HL. The output signal of the neurons in the layer OL or the subsequent layer is input, and each neuron in the output layer OL receives the signal of the neurons in the previous layer. The output signal of each neuron is input. Each neuron is connected to all the neurons in the previous and next layers. It may be connected to all neurons (fully connected) or to a portion of neurons.

[0141] Figure 8(B) shows an example of a neuron operation. Here, we consider a neuron N and a neuron B. The figure shows two neurons in the previous layer that output signals to neuron N. Neuron N has a The output of the neuron x1 and the output of the neuron in the previous layer x2 are input. In case N, the multiplication result of output x1 and weight w1 (x1w1) and the multiplication result of output x2 and weight w2 After the sum of the results (x2w2) x1w1+x2w2 is calculated, the bias b is The value a is then calculated by the activation function h. and the neuron N outputs an output signal y=h(a).

[0142] In this way, the operation of a neuron involves adding the product of the output of the previous layer neuron and the weight. This multiplication and addition operation is called multiplication and addition (x1w1+x2w2 above). This may be done on software using a program, or on hardware. When the multiply-and-accumulate operation is performed by hardware, a multiply-and-accumulate circuit can be used. This product-sum operation circuit may be a digital circuit or an analog circuit. Good too.

[0143] The sum-of-products operation circuit may be configured using Si transistors or OS transistors. In particular, since the off-state current of an OS transistor is extremely small, it is possible to It is suitable as a transistor for composing an analog memory of a circuit. A product-sum circuit may be configured using both an OS transistor and an OS transistor.

[0144] Also, the function of the row driver 13 may be integrated into the row driver 12 as shown in FIG. The function of the column driver 15 may be integrated into the column driver 14. The normal data and image data, as well as the output data of the circuit 16, are input to a selection circuit 19; Either data is output to the column driver 14 at an appropriate timing.

[0145] The row driver 12 is, for example, a combination of a shift register 20 and a buffer circuit 21. By controlling the conduction of the buffer circuit 21, the Data can be output to the line 121 or the wiring 122. For example, the shift register 22 and the selection circuit 23 may be combined. The selection circuit 23 can selectively output data to the wiring 124 or the wiring 125. This can be done.

[0146] In the configuration shown in Figure 7, different drivers are used depending on the resolution of the image data. For example, when performing a display operation without correction at low resolution, the row driver 13 and the column driver 15, and the row driver 12 and the column driver 14 can be stopped. In addition, each of the used wirings 122 and 125 can be connected to the unused wiring 12. This is half the power consumed by data charging and discharging. In addition, in the configuration shown in FIG. 8, when performing the same display operation, the number of output stages of the driver is halved. This can reduce power consumption.

[0147] Next, a configuration in which the circuit block shown in FIG. 4(A) is applied to the pixel array shown in FIG. 1 (see FIG. 10) will be described. The simulation results for the above (reference) are explained below. The parameters are as follows: The size is L / W=6 μm / 6 μm (transistor 102), L / W=4 μm / 4 μm (other other transistors), the capacitance of the capacitor 103 is 150 fF, the capacitance of the capacitor 113 is 5 0fF, EL element 114 is an FN diode model, and wiring 128 is an anode potential of +1 The potential of the wiring 129 was set to 0V, and the potential of the wiring 129 was set to -5V as a cathode potential. SPICE was used as the software.

[0148] Figures 11(A) to 11(C) show the simulation results for verifying high resolution display (without correction). Figure 11(A) is a timing chart used for the verification. By turning on the transistor 102 at times T1 and T2, the image Image data (V DATA ) is written.

[0149] FIG. 11(B) shows the image data (VDATA ) the current (I LE D ) is the result of simulating the pixel. As a result of the simulation, it was found that any pixel (pix1 to pix4) can display gradation. It has been confirmed.

[0150] Also, FIG. 11(C) shows the image data (V DATA ) to the potential of node NM (V NM ) The figure shows the results of simulating the change in the potential (V NM ) is the image data “V DATA It has been confirmed that it is proportional to

[0151] That is, the high resolution image data (V DATA ) can be displayed It was confirmed that...

[0152] 12(A) to 12(C) show the simulation results for verifying low-resolution display (without correction). Figure 12(A) and (B) show the timing charts used for the verification. The potential of the node NM is reset between times T1 and T2 in FIG. 2(B) from time T3 to time T4, the transistor 101 is turned on. Image data (V DATA ) is written.

[0153] FIG. 12(C) shows the image data (V DATA ) the current (I LE D ) is the result of simulating the pixel. Although this is a result of the pixel shift, any pixel (pix1 to pix4) can be displayed in gradation. has been confirmed.

[0154] Also, FIG. 12(D) shows the image data (V DATA ) to the potential of node NM (V NM ) The figure shows the results of simulating the change in the potential (V NM ) is the image data (V DATA ) has been confirmed to be proportional to

[0155] That is, the low-resolution image data (V DATA ) can be displayed It was confirmed that...

[0156] 13(A) to 13(C) show the simulation results for verifying low-resolution display (with correction). Figures 13(A) and 13(B) are timing charts used for the verification. In FIG. 13(A), the correction data (Vp) is input to the node NM from the wiring 124 at the time T1 to T2. After that, at times T3 and T4 shown in FIG. 1 is turned on, the image data (V DATA ) is written.

[0157] FIG. 13C shows the current (I LED ) corrected data The results are the results of simulations for each data. Image data (V DATA ) and combined with either It has been confirmed that:

[0158] Also, FIG. 13(D) shows the image data (V DATA ) to the potential of node NM (VNM ) The results are the results of simulating the change in Vp for each correction data (Vp). ) and write 1V to 8V as image data (V DATA ) and combined with Even when NM ) is the image data (V DATA ) + correction data (Vp ) has been confirmed to be proportional to

[0159] That is, the correction data (Vp) supplied from the wiring 124 is converted into the low-resolution data (Vp) supplied from the wiring 125. Image data for the degree (V DATA ) can be combined and displayed.

[0160] FIG. 14 shows an example in which a pixel according to one embodiment of the present invention is applied to an EL display device capable of color display. This is an example. Generally, the pixels of a display device that can display color are R (red), G (green), and B (blue). In FIG. 14, the sub-pixels arranged in the horizontal direction are Three sub-pixels, sub-pixel 10R, sub-pixel 10G, and sub-pixel 10B, constitute one pixel. This shows four pixels in the horizontal and vertical directions. Note that wiring such as power lines is omitted in Figure 14. There are.

[0161] As described above, in one embodiment of the present invention, the transistors 101 are arranged in a matrix. The four pixels (corresponding to four sub-pixels emitting the same color in this case) are supplied with correction data Vp1 or image data Vp2. The data VsL can be input. Here, the wiring 124 electrically connecting each sub-pixel are provided for each column, but the wiring 125 electrically connected to the transistor 101 is A subpixel is provided for every two subpixels.

[0162] In this configuration, for example, in the pixel (PIX1) in the upper left of FIG. 14, the subpixel 10R and the subpixel 1 A wiring 124[i+1] is provided between the subpixel 10G and the subpixel 10B. Two wires, 124[i+2] and 125[j+1], are provided between them. When the layout of each element is made as dense as possible, the spacing between each sub-pixel (the same function) It becomes difficult to keep the spacing between elements (spacing between elements with

[0163] Therefore, the pixel electrodes connected to the subpixels 10R, 10G, and 10B are When the electrodes are 25R, 25G, and 25B, as shown in FIG. It is preferable to arrange the pixel electrodes 25B at equal intervals. However, for clarity, they are treated as separate elements. This is effective for emission-type EL display devices or reflection-type liquid crystal display devices.

[0164] FIG. 15 shows an example in which a pixel according to one embodiment of the present invention is applied to a liquid crystal display device capable of color display. In order to make the intervals between sub-pixels constant in a liquid crystal display device, for example, the pixel (P In IX2, the wiring 132[j] to which the other electrode of the capacitor 116 is electrically connected is The wiring 132 may be provided between the pixel 10R and the sub-pixel 10G. The capacitive elements 116 of the subpixel 10G are electrically connected to each other. The capacitance element 116 of the sub-pixel 10R of the adjacent pixel is connected to the wiring 132[j +1] can be electrically connected.

[0165] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0166] (Embodiment 2) In this embodiment, a configuration example of a display element using a liquid crystal element and a display device using an EL element are described. In this embodiment, the display described in the first embodiment is Description of the elements, operations and functions of the device will be omitted.

[0167] 16A to 16C show the structure of a display device to which one embodiment of the present invention can be applied. Figure.

[0168] In FIG. 16A, a display portion 215 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided, and the display portion 215 is disposed between the first substrate 4001 and the sealant 4005. 5 and is sealed by a second substrate 4006.

[0169] The display unit 215 is provided with the pixel array 11 shown in FIG. 7 or FIG. 9 of the first embodiment. The scanning line driving circuit described below is a row driver, and the signal line driving circuit is a column driver. Equivalent to Ba.

[0170] In FIG. 16A, a scanning line driving circuit 221a, a signal line driving circuit 231a, and a signal line driving circuit 232a and the common line driver circuit 241a are provided on a printed circuit board 4041. The integrated circuits 4042 are made of a single crystal semiconductor or a polycrystalline The signal line driving circuit 231a and the signal line driving circuit 232a are formed of semiconductors. The scanning line driving circuit 221a has the function of the column driver shown in the first embodiment. The common line driver circuit 241a has the function of the row driver shown in the first embodiment. It has the function of supplying a specified potential to the wiring that supplies the power supply and Vref shown in do.

[0171] The scanning line driving circuit 221a, the common line driving circuit 241a, the signal line driving circuit 231a, and the signal Various signals and potentials are applied to the signal line driver circuit 232a via a flexible printed circuit (FPC). The power supply is supplied via a 4018 printed circuit.

[0172] The integrated circuit 4042 included in the scanning line driver circuit 221a and the common line driver circuit 241a is The signal line driver circuit 231a and the signal line driver The integrated circuit 4042 included in the drive circuit 232a has a function of supplying image data to the display unit 215. The integrated circuit 4042 is surrounded by a sealant 4005 on the first substrate 4001. It is implemented in a different area from the area where it is installed.

[0173] The method of connecting the integrated circuit 4042 is not particularly limited, and may be wire bonding. COG (Chip On Glass) method, TCP (Tape Carrier Package method, COF (Chip On Film) method, etc. can be used. .

[0174] FIG. 16B shows an integrated circuit included in the signal line driver circuit 231a and the signal line driver circuit 232a. The circuit 4042 is implemented by the COG method. The body is integrally formed on the same first substrate 4001 as the display unit 215 to form a system-on-panel. It can be achieved.

[0175] In FIG. 16B, the scanning line driving circuit 221a and the common line driving circuit 241a are connected to the display unit 2. 15. The driving circuit is formed on the same substrate as the pixel circuit in the display unit 215. By forming the parts at the same time, the number of parts can be reduced, which increases productivity. can.

[0176] In FIG. 16B, the display portion 215 provided on the first substrate 4001 and the scanning line driver A sealant 4005 is provided to surround the common line driving circuit 221a and the common line driving circuit 241a. In addition, a display unit 215, a scanning line driving circuit 221a, and a common line driving circuit The second substrate 4006 is provided on the display unit 215, the scanning line driver 241a. The driving circuit 221a and the common line driving circuit 241a are mounted on the first substrate 4001 and the sealing material 40. The display element is sealed by the second substrate 4005 and the second substrate 4006 .

[0177] In addition, in FIG. 16B, the signal line driver circuit 231a and the signal line driver circuit 232a are separately 4001 and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line driver circuit may be formed separately and mounted, or may be mounted as part of the signal line driver circuit or the scanning line driver circuit. A part of the driving circuit may be formed separately and mounted. The signal line driving circuit 231a and the signal line driving circuit 232a are formed on the same substrate as the display unit 215. That's fine.

[0178] The display device also includes a panel in which a display element is sealed, and a controller for the panel. This may also include a module in which an IC or the like including the above is mounted.

[0179] The display portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistor described in the above embodiment can be used as the transistor. can be done.

[0180] The structure of the transistors in the peripheral driver circuits and the pixel circuits in the display area is The transistors in the peripheral driver circuit may be the same or different. They may have the same structure, or two or more types of structures may be used in combination. The transistors in the pixel circuit may all have the same structure, or may have two or more types of structures. may also be used in combination.

[0181] An input device 4200 can be provided on the second substrate 4006. A display device provided with an input device 4200 can function as a touch panel. .

[0182] There is no limitation on the detection elements (also referred to as sensor elements) included in the touch panel of one embodiment of the present invention. We offer a variety of sensors that can detect the proximity or contact of a finger, stylus, or other object. , can be applied as a sensing element.

[0183] The sensor type may be, for example, a capacitance type, a resistive film type, a surface acoustic wave type, or an infrared type. Various methods can be used, such as a pressure-sensitive method, an optical method, or the like.

[0184] In this embodiment, a touch panel having a capacitance type detection element will be described as an example. .

[0185] The capacitance type includes a surface capacitance type, a projected capacitance type, etc. The capacitance type includes the self-capacitance type and the mutual capacitance type. This is preferable because it enables simultaneous multi-point detection.

[0186] The touch panel of one embodiment of the present invention is formed by bonding a display device and a sensing element that are separately manufactured. A detector element is formed on one or both of a substrate supporting a display element and an opposing substrate. Various configurations can be applied, such as a configuration in which electrodes or the like are provided.

[0187] 17(A) and (B) show examples of touch panels. FIG. 17(A) shows a touch panel 4 17(B) is a perspective view of the input device 4200. For clarity, only representative components are shown.

[0188] The touch panel 4210 is made by bonding a display device and a sensing element that are separately manufactured. be.

[0189] The touch panel 4210 has an input device 4200 and a display device, which are stacked on top of each other. It is being done.

[0190] The input device 4200 includes a substrate 4263, an electrode 4227, an electrode 4228, and a plurality of wirings 4237. , a plurality of wirings 4238 and a plurality of wirings 4239. For example, the electrode 4227 is The electrode 4228 can be electrically connected to the wiring 4237 or the wiring 4239. The FPC 4272b can be electrically connected to the wires 4239. and electrically connects to each of the plurality of wirings 4238. 3b can be provided.

[0191] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. In the case where a touch sensor is provided between the first substrate 4001 and the second substrate 4006, In this case, in addition to capacitive touch sensors, optical touch sensors using photoelectric conversion elements are also available. may be applied.

[0192] 18(A) and 18(B) show the structure of the region indicated by the chain line N1-N2 in FIG. 16(B). The display device shown in FIG. 18(A) and FIG. 18(B) has an electrode 4015. The electrode 4015 is electrically connected to a terminal of the FPC 4018 via an anisotropic conductive layer 4019. 18(A) and 18(B), the electrode 4015 is Wiring is formed in openings formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110. It is electrically connected to 4014.

[0193] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030. The source and drain electrodes of the transistor 4010 and the transistor 4011 are the same. The same conductive layer is used.

[0194] The display portion 215 and the scanning line driver circuit 221a provided on the first substrate 4001 are 18(A) and 18(B), the display unit 215 The included transistor 4010 and the transistor included in the scanning line driver circuit 221a 18(A) and 18(B), the transistor 4 010 and a bottom-gate transistor is shown as an example of a transistor 4011. However, it may be a top-gate transistor.

[0195] In FIG. 18(A) and FIG. 18(B), the transistor 4010 and the transistor 401 18(B), an insulating layer 4112 is provided on the insulating layer 4112. A partition wall 4510 is formed.

[0196] The transistor 4010 and the transistor 4011 are provided over an insulating layer 4102. The transistor 4010 and the transistor 4011 are formed by insulating layers 4111. The electrode 4017 is formed on the semiconductor substrate 401. The electrode 4017 functions as a back gate electrode. It is possible.

[0197] 18A and 18B includes a capacitor 4020. The display device shown in FIG. The capacitor 4020 has an electrode 4 formed in the same process as the gate electrode of the transistor 4010. 021 and electrodes formed in the same process as the source electrode and drain electrode. The electrodes overlap with each other with an insulating layer 4103 interposed therebetween.

[0198] Generally, the capacitance of a capacitor provided in a pixel portion of a display device is determined by the capacitance of a transistor disposed in the pixel portion. The capacitance is set to be able to hold charge for a predetermined period, taking into consideration factors such as leakage current of the capacitor. The capacitance of the capacitor may be set in consideration of the off-state current of the transistor.

[0199] The transistor 4010 provided in the display portion 215 is electrically connected to a display element. (A) is an example of a liquid crystal display device using a liquid crystal element as a display element. In the liquid crystal display device, a liquid crystal element 4013 is a display element. 31, and a liquid crystal layer 4008. The liquid crystal layer 4008 is sandwiched between alignment films. The second electrode layer 4031 is provided with an insulating layer 4032 and an insulating layer 4033 which function as a second electrode layer. The first electrode layer 4030 and the second electrode layer 4031 are disposed on the second substrate 4006 side. Overlapping through layer 4008.

[0200] The spacers 4035 are columnar spacers obtained by selectively etching an insulating layer. The distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031 is controlled. A spherical spacer may also be used.

[0201] If necessary, a black matrix (light-shielding layer), a colored layer (color filter), a polarizing Optical members (optical substrates) such as a member, a phase difference member, an anti-reflection member, etc. may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. A backlight, a sidelight, or the like may be used. Micro LEDs or the like may be used as the light.

[0202] In the display device shown in FIG. 18A, the following is provided between the second substrate 4006 and the second electrode layer 4031: A light-shielding layer 4132, a colored layer 4131, and an insulating layer 4133 are provided.

[0203] Materials that can be used for the light-shielding layer include carbon black, titanium black, gold, Examples of the light-shielding layer include metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The film may be a film containing a resin material, or may be a thin film made of an inorganic material such as a metal. For example, a laminated film of a film containing a material of a colored layer may be used as the light-shielding layer. A film containing a material used for a color layer that transmits light of a certain color and a material used for a color layer that transmits light of another color are used. By using the same material for the colored layer and the light-shielding layer, This is preferable because it allows the equipment to be standardized and the process to be simplified.

[0204] Materials that can be used for the coloring layer include metal materials, resin materials, pigments, and dyes. The method for forming the light-shielding layer and the colored layer is the same as the method for forming each layer described above. For example, the ink jet method may be used.

[0205] In addition, the display device shown in FIGS. 18(A) and 18(B) has an insulating layer 4111 and an insulating layer 41 The insulating layer 4111 and the insulating layer 4104 are insulating layers that are difficult for impurity elements to penetrate. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, It is possible to prevent impurities from entering from the outside.

[0206] Furthermore, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. An EL element can be applied. An EL element is a device that has a light-emitting compound between a pair of electrodes. The EL element has a layer (also referred to as an "EL layer") containing a voltage lower than the threshold voltage of the EL element between a pair of electrodes. When a large potential difference is generated, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes recombine in the EL layer, and the light-emitting material contained in the EL layer The quality glows.

[0207] EL elements are also classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0208] When a voltage is applied to an organic EL element, electrons are emitted from one electrode and holes are emitted from the other electrode. are injected into the EL layer, and then the carriers (electrons and holes) recombine. By this, the light-emitting organic compound forms an excited state, and the excited state returns to the ground state. Due to this mechanism, such a light-emitting element is called a current-excited light-emitting element. It is called a child.

[0209] In addition to the light-emitting compound, the EL layer may contain a material having a high hole injection property and a material having a high hole transport property. , hole blocking material, material with high electron transporting ability, material with high electron injecting ability, or bipolar The layer may contain a highly functional substance (a substance having high electron-transporting and hole-transporting properties).

[0210] The EL layer can be formed by a variety of methods, including vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating. It can be formed in any way.

[0211] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light emitting element is an organic EL element. do.

[0212] The light emitting element only needs to have at least one of the pair of electrodes transparent in order to extract light. The transistor and the light emitting element are formed on the substrate, and light is emitted from the surface opposite to the substrate. Top emission structure, which emits light from the top surface, and bottom emission structure, which emits light from the surface of the substrate. (bottom emission) structure and double-sided emission (dual emission) structure There are light emitting elements with a light-emitting structure, and any light emitting element with an emission structure can be applied.

[0213] FIG. 18(B) shows a light-emitting display device (also called an "EL display device") that uses light-emitting elements as display elements. The light-emitting element 4513 is an example of a display element. The light-emitting element 4513 is electrically connected to the transistor 4010. The electrode layer 4030, the light-emitting layer 4511, and the second electrode layer 4031 are laminated together. The light emitting element 4513 may be arranged in accordance with the direction of light to be extracted from the light emitting element 4513. The configuration of 13 can be changed as appropriate.

[0214] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. An opening is formed on the first electrode layer 4030 using a resin material, and the side of the opening is It is preferable to form the inclined surface with a curvature.

[0215] The light-emitting layer 4511 may be composed of a single layer or a plurality of layers stacked. Either way is fine.

[0216] The light emitting element 4513 emits light in a variety of colors, including white, red, green, and blue, depending on the material that makes up the light emitting layer 4511. , cyan, magenta, or yellow, etc.

[0217] To achieve color display, a white light-emitting element 4513 is combined with a colored layer. There are two methods: one is to combine the two and the other is to provide a light emitting element 4513 with a different luminescent color for each pixel. The first method has higher productivity than the latter method. However, the latter method is less productive than the former method because it requires separate production. In addition to the latter method, it is possible to obtain an emission color with higher color purity than the former method. By adding a microcavity structure to the element 4513, color purity can be further improved. can be done.

[0218] The light-emitting layer 4511 may contain an inorganic compound such as quantum dots. By using the child dots in the light-emitting layer, they can also function as a light-emitting material.

[0219] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513. A protective layer may be formed on the insulating layer 4031 and the partition wall 4510. The protective layer may be formed of silicon nitride. silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, Forming aluminum oxide nitride, DLC (Diamond Like Carbon), etc. In addition, the first substrate 4001, the second substrate 4006, and the sealing material 4 The space sealed by 005 is sealed with a filler 4514. In addition, a protective film (laminating film) with high airtightness and low outgassing is used to prevent exposure to the outside air. It is preferable to package (enclose) the product in a protective film (film, ultraviolet curing resin film, etc.) or a cover material. I wish.

[0220] Filler 4514 can be an inert gas such as nitrogen or argon, or an ultraviolet curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resins, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or Ethylene vinyl acetate (EVA) can also be used. may contain a desiccant.

[0221] The sealing material 4005 is made of glass materials such as glass frit, or ordinary materials such as two-component mixed resin. Resin materials such as heat-curable resin, photo-curable resin, and thermosetting resin can be used. The sealing material 4005 may also contain a desiccant.

[0222] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be attached to the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be provided as needed. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to further diffuse reflected light and reduce glare.

[0223] In addition, by using a microcavity structure for the light-emitting element, it is possible to extract light with high color purity. In addition, by combining a microcavity structure with a color filter, This reduces congestion and improves the visibility of the displayed image.

[0224] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, In the case of the counter electrode layer, the direction of the light to be extracted, the location of the electrode layer, and The light transmission property or reflectivity can be selected depending on the pattern structure of the electrode layer.

[0225] The first electrode layer 4030 and the second electrode layer 4031 are made of an indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide A conductive material having light-transmitting properties, such as indium tin oxide doped with silicon oxide, may be used. This can be done.

[0226] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag) or its alloy, or metal nitride thereof. .

[0227] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer can be formed using a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives or a copolymer consisting of two or more of aniline, pyrrole and thiophene, or Its derivatives are also included.

[0228] In addition, since transistors are easily damaged by static electricity, a protection circuit for protecting the drive circuit is required. It is preferable that the protection circuit is configured using a non-linear element.

[0229] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0230] (Embodiment 3) In this embodiment mode, the transistors described in the above embodiment modes can be replaced with An example of a transistor that can be used will be described with reference to the drawings.

[0231] The display device of one embodiment of the present invention includes a bottom-gate transistor and a top-gate transistor. The present invention can be fabricated using various types of transistors, such as a transistor having a MOSFET. The semiconductor layer materials and transistor structures used can be easily replaced to suit the production line. It is possible.

[0232] [Bottom-gate transistor] FIG. 19(A1) shows a channel protection transistor, which is a type of bottom gate transistor. 19(A1) is a cross-sectional view of the transistor 810 in the channel length direction. The transistor 810 is formed on the substrate 771. The electrode 746 is provided with an insulating layer 772 interposed therebetween. The semiconductor layer 742 is provided. The electrode 746 can function as a gate electrode. The insulating layer 726 is provided as a gate electrode. It can function as a gate insulating layer.

[0233] In addition, an insulating layer 741 is provided on a channel formation region of the semiconductor layer 742. Electrodes 744a and 744b are provided on the insulating layer 726 in contact with a portion of the insulating layer 726. 744a can function as either a source or drain electrode. It can function as the other of the source electrode and the drain electrode. A portion of the pole 744 b is formed on the insulating layer 741 .

[0234] The insulating layer 741 can function as a channel protection layer. By providing the electrode 744a and the electrode 744b, the exposure of the semiconductor layer 742 that occurs when the electrode 744a and the electrode 744b are formed can be prevented. Therefore, when the electrodes 744a and 744b are formed, the semiconductor layer This can prevent the channel formation region 742 from being etched. According to this, a transistor with good electrical characteristics can be realized.

[0235] The transistor 810 includes an electrode 744a, an electrode 744b, and an insulating layer 741. The insulating layer 729 is disposed on the insulating layer 728 .

[0236] When an oxide semiconductor is used for the semiconductor layer 742, at least one of the electrodes 744a and 744b At least in the area in contact with the semiconductor layer 742, oxygen is taken from a part of the semiconductor layer 742, and oxygen vacancies are formed. It is preferable to use a material that can generate oxygen vacancies in the semiconductor layer 742. The carrier concentration in the resulting region increases, and the region becomes n-type. + layer). Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the conductor layer 742, oxygen is taken from the semiconductor layer 742, and oxygen vacancies are eliminated. Examples of materials that can be used include tungsten and titanium. do.

[0237] The source and drain regions are formed in the semiconductor layer 742, forming an electrode 744a In addition, the contact resistance between the electrode 744b and the semiconductor layer 742 can be reduced. The electrical characteristics of the transistor, such as the effective mobility and threshold voltage, can be improved. can.

[0238] When a semiconductor such as silicon is used for the semiconductor layer 742, the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b, as an n-type semiconductor or a p-type semiconductor. It is preferable to provide a layer that functions as an n-type semiconductor or a p-type semiconductor. It can function as a source or drain region of a transistor.

[0239] The insulating layer 729 has a function of preventing or reducing diffusion of impurities into the transistor from the outside. It is preferable to form the insulating layer 729 using a material having the above structure. You can also do this.

[0240] The transistor 811 shown in FIG. 19A2 has a back gate electrode over the insulating layer 729. The transistor 810 differs from the transistor 810 in that it has a functioning electrode 723. The electrode 723 is an electrode It can be formed using the same materials and methods as 746.

[0241] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is disposed so as to sandwich the channel forming region of the layer. The back gate electrode can be made to function in the same manner as the gate electrode. Alternatively, the potential may be set to ground potential (GND potential) or any other potential. By changing the potential of the gate electrode independently of the gate electrode, the threshold voltage of the transistor can be controlled. The voltage can be varied to any desired value.

[0242] Both the electrode 746 and the electrode 723 can function as gate electrodes. The insulating layer 726, the insulating layer 728, and the insulating layer 729 each serve as a gate insulating layer. The electrode 723 can function as a gate electrode. That's fine.

[0243] When one of the electrodes 746 and 723 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 811, the electrode 723 is called a "gate electrode." When the term "electrode" is used, the electrode 746 is referred to as a "back gate electrode." When the transistor 811 is used as a top gate electrode, In addition, either the electrode 746 or the electrode 723 can be considered as a "first The first gate electrode is sometimes referred to as the "first gate electrode" and the other as the "second gate electrode."

[0244] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, the electrode 74 6 and the electrode 723 are set to the same potential, the region where carriers flow in the semiconductor layer 742 The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 811 increases, the field effect mobility also increases.

[0245] Therefore, the transistor 811 is a transistor having a large on-state current relative to its area. That is, the area occupied by the transistor 811 is set to According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized. It is possible.

[0246] In addition, since the gate electrode and back gate electrode are formed from a conductive layer, they can be The function of preventing the electric field generated from acting on the semiconductor layer where the channel is formed (especially static electricity The back gate electrode has an electric field shielding function against the semiconductor layer. By forming a back gate electrode and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be improved. .

[0247] In addition, by forming the back gate electrode using a conductive film having a light-shielding property, This prevents light from entering the semiconductor layer from the side. This can prevent degradation of electrical characteristics such as a shift in the threshold voltage of the transistor. .

[0248] According to one embodiment of the present invention, a highly reliable transistor can be provided. A highly reliable semiconductor device can be realized.

[0249] FIG. 19(B1) shows a channel protection transistor 82 having a different configuration from that shown in FIG. 19(A1). 8 is a cross-sectional view of the transistor 820 in the channel length direction. It has a similar structure, but differs in that an insulating layer 741 covers the edge of a semiconductor layer 742. In addition, an opening formed by selectively removing a part of the insulating layer 741 that overlaps the semiconductor layer 742 In this portion, the semiconductor layer 742 and the electrode 744a are electrically connected. In another opening formed by selectively removing a portion of the insulating layer 741 that overlaps with the semiconductor layer 42, The insulating layer 741 is electrically connected to the electrode 744b. The overlapping region can function as a channel protection layer.

[0250] The transistor 821 shown in FIG. 19B2 has a back gate electrode over the insulating layer 729. It differs from transistor 820 in that it has a functioning electrode 723 .

[0251] By providing the insulating layer 741, the semiconductor generated when the electrodes 744a and 744b are formed can be prevented. Therefore, when forming the electrode 744a and the electrode 744b, the layer 742 can be prevented from being exposed. In addition, the semiconductor layer 742 can be prevented from becoming thin.

[0252] Also, the transistors 820 and 821 are the same as the transistors 810 and 821. The distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 are smaller than the distance between the electrode 744a and the electrode 746 and the electrode 744b. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 is In addition, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized. Cut.

[0253] Figure 19(C1) shows a channel-etched type transistor, which is one of the bottom-gate type transistors. 1 is a cross-sectional view of a transistor 825 in the channel length direction. Electrodes 744a and 744b are formed without using 41. In addition, a part of the semiconductor layer 742 that is exposed during the formation of the electrode 744b may be etched. On the other hand, since the insulating layer 729 is not provided, productivity of the transistor can be increased.

[0254] The transistor 826 shown in FIG. 19C2 has a back gate electrode over the insulating layer 729. It differs from transistor 825 in that it has a functioning electrode 723 .

[0255] In FIGS. 20(A1) to 20(C2), transistors 810, 811, 820, 821, 825, 826 are cross-sectional views in the channel width direction.

[0256] In the structures shown in FIGS. 20(B2) and (C2), the gate electrode and the back gate electrode are connected. The gate electrode and the back gate electrode have the same potential. The gate electrode is sandwiched between the gate electrode and the back gate electrode.

[0257] The length of each of the gate electrode and the back gate electrode in the channel width direction is 2 in the channel width direction, and the entire channel width direction of the semiconductor layer 742 is 726, 741, 728, and 729 are sandwiched between the gate electrode or the back gate electrode. It is a structure that

[0258] With this structure, the semiconductor layer 742 included in the transistor can be formed between the gate electrode and the buffer layer. The gate electrode can be electrically surrounded by the electric field of the gate electrode.

[0259] Like the transistor 821 or the transistor 826, the gate electrode and the back gate The electric field of the electrode electrically surrounds the semiconductor layer 742 in which the channel region is formed. The device structure of the transistor is surrounded by a channel (S-channel ) structure.

[0260] By using an S-channel structure, one or both of the gate electrode and the back gate electrode can be By this method, an electric field for inducing a channel can be effectively applied to the semiconductor layer 742. This improves the current driving capability of the transistor, making it possible to obtain high on-current characteristics. In addition, since it is possible to increase the on-current, miniaturization of the transistor is also possible. In addition, the S-channel structure improves the mechanical strength of the transistor. The degree can be increased.

[0261] [Top-gate transistor] The transistor 842 illustrated in FIG. 21A1 is a top-gate transistor. The electrode 744a and the electrode 744b are formed on the insulating layer 728 and the insulating layer 729. The insulating film 742 is electrically connected to the semiconductor layer 742 in the opening.

[0262] In addition, a part of the insulating layer 726 that does not overlap with the electrode 746 is removed, and the electrode 746 and the remaining insulating layer 726 as a mask, an impurity 755 is introduced into the semiconductor layer 742, The impurity region can be formed in a self-aligned manner in 742. Transistor 842 has an area where insulating layer 726 extends beyond the edge of electrode 746 . The impurity concentration in the region of the semiconductor layer 742 into which the impurity 755 is introduced via the insulating layer 726 is The region where the impurity 755 is introduced without the insulating layer 726 interposed therebetween is smaller than the region where the impurity 755 is introduced without the insulating layer 726 interposed therebetween. 2 is a lightly doped drain (LDD) in an area that does not overlap with the electrode 746. ) region is formed.

[0263] The transistor 843 shown in FIG. 21A2 has the electrode 723. 2. The transistor 843 has an electrode 723 formed on a substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 with the insulating layer 772 interposed therebetween. , can function as a back gate electrode.

[0264] In addition, the transistor 844 shown in FIG. 21B1 and the transistor 845 shown in FIG. 21B2 As in the case of the electrode 845, the insulating layer 726 in the area that does not overlap with the electrode 746 may be entirely removed. In addition, the transistor 846 shown in FIG. 21(C1) and the transistor 848 shown in FIG. 21(C2) The insulating layer 726 may remain, as may the insulating layer 847.

[0265] The transistors 842 to 847 are also formed with the electrode 746. As a result, the semiconductor layer 742 is doped with impurities 755 using the mask. According to one aspect of the present invention, an impurity region can be formed in a self-aligned manner. Furthermore, according to one aspect of the present invention, a transistor with good integration properties can be realized. Therefore, a highly reliable semiconductor device can be realized.

[0266] Transistors 842, 843, 844, 845, and 846 are shown in FIGS. 847 are cross-sectional views in the channel width direction.

[0267] The transistors 843, 845, and 847 are respectively However, the present invention is not limited to this, and the transistor 84 may have an S-channel structure. 3. Transistor 845 and transistor 847 should not be of S-channel structure. That's fine.

[0268] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0269] (Fourth embodiment) Examples of electronic devices that can use the display device according to one embodiment of the present invention include display devices, personal computers, and the like. a personal computer, an image storage device or image reproduction device equipped with a recording medium, a mobile phone, a mobile phone Game consoles, including those with a camcorder, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copying machines, fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include vending machines. Specific examples of these electronic devices are shown in Figure 23.

[0270] FIG. 23A shows a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, and a microphone 964. 63, speaker 967, display unit 965, operation keys 966, zoom lever 968, lens 9 By using the display device of one embodiment of the present invention for the display portion 965, various images can be displayed. The following display can be performed.

[0271] FIG. 23B shows a digital signage with a large display unit 922. For example, When the display device of one embodiment of the present invention is used for the display portion 922, A high-quality display can be achieved.

[0272] FIG. 23C shows a mobile phone, which includes a housing 951, a display unit 952, an operation button 953, and an external The mobile phone has a connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The telephone has a touch sensor on the display 952. All operations such as the above can be performed by touching the display unit 952 with a finger or a stylus. The housing 901 and the display portion 952 are flexible and can be folded as shown in the figure. By using the display device of one embodiment of the present invention for the display portion 952, various It is possible to display a clear image.

[0273] FIG. 23D shows a portable data terminal, which includes a housing 911, a display portion 912, a speaker 913, a camera, and the like. The display unit 912 has a touch panel function for inputting and outputting information. By using the display device of one embodiment of the present invention for the display portion 912, various images can be displayed. The following display can be performed.

[0274] FIG. 23E shows a television set, which includes a housing 971, a display unit 973, operation keys 974, and a speaker 975. The display unit 973 has a touch sensor 975, a communication connection terminal 976, an optical sensor 977, etc. The display device of one embodiment of the present invention is provided in the display portion 973. By using this, various images can be displayed.

[0275] FIG. 23(F) shows an information processing terminal, which includes a housing 901, a display portion 902, a display portion 903, a sensor The display unit 902 and the display unit 903 are each made up of a single display panel, and are flexible. The housing 901 is also flexible and can be folded as shown in the figure. It can also be used in a flat form like a tablet device. 4 can sense the shape of the housing 901, for example, when the housing is bent, the display 9 The display of the display unit 902 and the display unit 903 can be switched. By using the display device of one embodiment of the present invention in 03, various images can be displayed. .

[0276] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible. [Explanation of symbols]

[0277] 10: pixel, 10B: sub-pixel, 10G: sub-pixel, 10R: sub-pixel, 11: pixel array, 1 2: Row driver, 13: Row driver, 14: Column driver, 15: Column driver ,16: Circuit, 17: Selection circuit, 18: Selection circuit, 19: Selection circuit, 20: Shift register 21: buffer circuit, 22: shift register, 23: selection circuit, 25B: electrode, 25 G: electrode, 25R: electrode, 101: transistor, 102: transistor, 103: capacitor Element, 110: circuit block, 111: transistor, 112: transistor, 113: Capacitor element, 114: EL element, 115: transistor, 116: capacitor element, 117: liquid crystal Element, 118: transistor, 119: transistor, 120: circuit, 121: wiring, 1 22: Wiring, 124: Wiring, 125: Wiring, 126: Wiring, 128: Wiring, 129: Wiring ,130: Wiring, 131: Wiring, 132: Wiring, 133: Wiring, 134: Wiring, 215: Display unit, 221a: scanning line driving circuit, 231a: signal line driving circuit, 232a: signal line driving Circuit, 241a: common line driving circuit, 723: electrode, 726: insulating layer, 728: insulating layer, 7 29: insulating layer, 741: insulating layer, 742: semiconductor layer, 744a: electrode, 744b: electrode, 746: electrode, 755: impurity, 771: substrate, 772: insulating layer, 810: transistor , 811: transistor, 820: transistor, 821: transistor, 825: transistor Transistor, 826: Transistor, 830: Transistor, 840: Transistor, 84 2: transistor, 843: transistor, 844: transistor, 845: transistor 846: transistor, 847: transistor, 901: housing, 902: display unit, 9 03: Display unit, 904: Sensor, 911: Housing, 912: Display unit, 913: Speaker, 9 19: Camera, 921: Pillar, 922: Display, 951: Housing, 952: Display, 953: Operation buttons, 954: External connection port, 955: Speaker, 956: Microphone, 957: Camera Mela, 961: Housing, 962: Shutter button, 963: Microphone, 965: Display, 9 66: Operation keys, 967: Speaker, 968: Zoom lever, 969: Lens, 971: Housing, 973: display unit, 974: operation keys, 975: speaker, 976: communication connection terminal , 977: optical sensor, 4001: substrate, 4005: sealing material, 4006: substrate, 4008 : liquid crystal layer, 4010: transistor, 4011: transistor, 4013: liquid crystal element, 4 014: Wiring, 4015: Electrode, 4017: Electrode, 4018: FPC, 4019: Anisotropy Conductive layer, 4020: capacitance element, 4021: electrode, 4030: electrode layer, 4031: electrode layer, 4032: insulating layer, 4033: insulating layer, 4035: spacer, 4041: printed circuit board, 4042: Integrated circuit, 4102: Insulating layer, 4103: Insulating layer, 4104: Insulating layer, 411 0: insulating layer, 4111: insulating layer, 4112: insulating layer, 4131: colored layer, 4132: light-shielding layer layer, 4133: insulating layer, 4200: input device, 4210: touch panel, 4227: electrode , 4228: Electrode, 4237: Wiring, 4238: Wiring, 4239: Wiring, 4263: Substrate , 4272b: FPC, 4273b: IC, 4510: partition wall, 4511: light-emitting layer, 451 3: Light emitting element, 4514: Filler

Claims

1. A display device including a first transistor and first to fourth circuits, each of the first circuit to the fourth circuit includes a second transistor, a first capacitance element, and a circuit block; the circuit block includes a third transistor, a fourth transistor, a fifth transistor, and a display element; In the first circuit to the fourth circuit, the display elements of the circuit blocks all correspond to the same color, one of a source electrode and a drain electrode of the second transistor is always electrically connected to one electrode of the first capacitor element; one electrode of the first capacitance element is always electrically connected to a gate electrode of the third transistor; one of a source electrode or a drain electrode of the third transistor is always electrically connected to one of a source electrode or a drain electrode of the fourth transistor and one of a source electrode or a drain electrode of the fifth transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to a pixel electrode of the display element; a first potential is supplied to the other of the source electrode and the drain electrode of the fifth transistor; the other electrode of the first capacitor element is always electrically connected to one of the source electrode and the drain electrode of the first transistor; Display device.

2. A display device including a first transistor and first to fourth circuits, each of the first circuit to the fourth circuit includes a second transistor, a first capacitance element, and a circuit block; the circuit block includes a third transistor, a fourth transistor, a fifth transistor, and a display element; In the first circuit to the fourth circuit, the display elements of the circuit blocks all correspond to the same color, one of a source electrode and a drain electrode of the second transistor is always electrically connected to one electrode of the first capacitor element; one electrode of the first capacitance element is always electrically connected to a gate electrode of the third transistor; one of a source electrode or a drain electrode of the third transistor is always electrically connected to one of a source electrode or a drain electrode of the fourth transistor and one of a source electrode or a drain electrode of the fifth transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to a pixel electrode of the display element; a first potential is supplied to the other of the source electrode and the drain electrode of the fifth transistor; the other electrode of the first capacitor element is always electrically connected to one of the source electrode and the drain electrode of the first transistor; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a signal line; Display device.

Images