Semiconductor device

Abstract

To provide a method for manufacturing a display having a threshold-controlled and highly reliable thin film transistor.SOLUTION: A gate insulating film is formed over a gate electrode, a microcrystalline semiconductor film is formed over the gate insulating film, an impurity element for controlling a threshold value is added to the microcrystalline semiconductor film by an ion implantation method, and then, crystallinity of the microcrystalline semiconductor film is improved by irradiation with a laser beam. Then, a buffer layer is formed over the microcrystalline silicon film, and a channel-etched thin film transistor is formed. A display apparatus having the thin film transistor is manufactured.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device having a circuit configured with thin film transistors (hereinafter referred to as TFTs). The present invention relates to electro-optical devices such as liquid crystal display panels and photonic devices, and methods for manufacturing such devices. The present invention relates to an electronic device that incorporates a light-emitting display device having a light-emitting element as a component.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term "semiconductor device" refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all semiconductor devices. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used. The technology for constructing thin film transistors (TFTs) is attracting attention. It is widely used in electronic devices such as ICs and electro-optical devices, especially in switches for image display devices. Development is being rushed for this technology as a semiconductor device.

[0004] Thin film transistors using amorphous semiconductor films are used as switching elements in image display devices. Alternatively, thin film transistors using polycrystalline semiconductor films or the like are used.

[0005] Thin film transistors using amorphous semiconductor films are made of amorphous silicon films such as hydrogenated amorphous silicon films. Because a high-quality semiconductor film is used, the process temperature is limited to 400°C, at which point hydrogen is released from the film. The above heating and laser light irradiation with an intensity that would cause surface roughness due to hydrogen in the film are not performed.

[0006] In addition, as a method for forming a polycrystalline semiconductor film, amorphous silicon is used in advance to prevent surface roughness. After dehydrogenation treatment to reduce the hydrogen concentration in the silicon film, a pulsed excimer laser was used. The laser beam is processed into a linear shape by an optical system, and then applied to the dehydrogenated amorphous silicon film. On the other hand, a technique is known in which a linear beam is scanned and irradiated to crystallize the material.

[0007] Thin film transistors using polycrystalline semiconductor films are thin film transistors using amorphous semiconductor films. The mobility is two orders of magnitude higher than that of the conventional MOSFETs, and the pixel section of the display device and its peripheral driving circuitry can be mounted on the same substrate. However, when an amorphous semiconductor film is used, In comparison, the process is more complicated due to the crystallization of the semiconductor film, which reduces the yield and There is a problem of increasing strikes.

[0008] In addition, FETs (FETs) are semiconductors whose channel formation region is a mixture of crystalline and amorphous structures. A field effect transistor is disclosed in Patent Document 1.

[0009] Furthermore, a thin film transistor using a microcrystalline semiconductor film is used as a switching element of an image display device. In this regard, a heater is used (Patent Documents 2 and 3).

[0010] The conventional method for fabricating thin-film transistors involves depositing an amorphous silicon film on a gate insulating film. After the film is formed, a metal film is formed on the top surface of the film, and the metal film is irradiated with a diode laser to form an A technology to convert amorphous silicon film into microcrystalline silicon film (Non-Patent Document 1) According to this method, the metal film formed on the amorphous silicon film is It is used to convert the light energy of a diode laser into thermal energy. This was to be removed later to complete the transistor. The amorphous silicon film is heated only by induction heating, and the microcrystalline silicon film This is a method for forming a [Prior art documents] [Patent documents]

[0011] [Patent Document 1] U.S. Patent No. 5,591,987 [Patent Document 2] Japanese Patent Application Publication No. 4-242724 [Patent Document 3] Japanese Patent Application Laid-Open No. 2005-49832 [Non-patent literature]

[0012] [Non-Patent Document 1] Toshiaki Arai et al., SID 07 DIGEST, 2007, pp. 1370-1373 Summary of the Invention [Problem to be solved by the invention]

[0013] A thin-film transistor operates when a certain voltage value (called the threshold voltage (Vth)) is applied to the gate. A switch that is turned on when a voltage is applied to the electrode and turned off when the voltage is less than that value. This threshold voltage (Vth) is a thin film transistor current-voltage characteristic graph. The voltage at the rising point of the obtained curve corresponds to the threshold voltage (Vt h) is better the closer it is to 0V. A transistor can be said to be an ideal switching element.

[0014] Due to unspecified factors in the manufacturing process of thin film transistors, the threshold voltage may shift to the negative side. If the value shifts from 0V is large, the drive This leads to an increase in dynamic voltage, resulting in an increase in power consumption of the semiconductor device.

[0015] Even in a thin film transistor using a microcrystalline semiconductor film, the threshold voltage may be increased due to unspecified factors. The voltage may shift to the negative or positive side.

[0016] In view of the above-mentioned problems, a thin film using a microcrystalline semiconductor film in which the threshold voltage is controlled to a desired value is An object of the present invention is to propose a method for manufacturing a display device including a transistor. [Means for solving the problem]

[0017] After forming the gate electrode, a gate insulating film is formed, and a 10 nm thick film is formed on the gate insulating film. A microcrystalline semiconductor film having a thickness of about 50 nm is formed. In order to control the conductivity, impurity elements (p-type impurity elements or n-type impurity elements) are added. ) is added to the microcrystalline semiconductor film by ion implantation or the like. After the addition, laser processing is performed to activate the added boron and to separate the gate insulating film and the microcrystalline semiconductor. The crystallinity of the microcrystalline semiconductor film at the interface with the semiconductor film is improved in the same process. Laser Processing (hereinafter referred to as "LP") is a method of forming microcrystals by radiant heating. This is a solid-phase crystal growth process that does not melt the semiconductor film. It utilizes the critical region where the film does not become liquid, and in that sense it is also called "critical growth." It can be said that.

[0018] In this way, a microcrystalline semiconductor film that functions as a channel formation region is formed on the gate insulating film. The microcrystalline semiconductor film obtained by performing LP processing on the formed microcrystalline semiconductor film is called LPSAS ( Laser Process Semi Amorphous Semiconductor After laser irradiation, an amorphous semiconductor film is formed on the microcrystalline semiconductor film. A buffer layer is then laminated on the buffer layer, and a pair of source and drain regions is formed on the buffer layer. and forming a source region and a drain region so as to expose a portion of the source region and the drain region. A pair of source and drain electrodes are formed in contact with the region.

[0019] In the thin film transistor having the above structure, a channel formation region is formed using a microcrystalline semiconductor film. Therefore, the field effect mobility is higher than that of a thin film transistor using a conventional amorphous semiconductor film.

[0020] A small amount of boron is added to the microcrystalline semiconductor film that functions as a channel formation region. The threshold voltage of the thin film transistor is controlled, and oxidation of the microcrystalline semiconductor film is prevented. The buffer layer functions as a high-resistance region, reducing the leakage current of thin-film transistors. Low noise and high pressure resistance.

[0021] Furthermore, a thin film transistor (TFT) is manufactured using a microcrystalline semiconductor film. A display device is manufactured by using the microcrystalline semiconductor film in the pixel portion and further in the driver circuit. The thin film transistor used in the filter formation region has a mobility of 1 to 20 cm 2 / V·sec and It has a mobility 2 to 20 times higher than that of thin-film transistors that use amorphous semiconductor films in the channel formation region. Therefore, a part or the whole of the driver circuit is formed on the same substrate as the pixel section, and the system A moon panel can be formed.

[0022] The present invention, which relates to a method for manufacturing a semiconductor device, is configured by forming a gate electrode on a substrate. forming a second insulating film on the gate electrode; forming a second insulating film on the gate electrode; a first semiconductor film is formed, and a p-type impurity element or an n-type impurity element is added to the first semiconductor film; a second semiconductor film is formed by irradiating the second semiconductor film with laser light, and a third semiconductor film is formed by irradiating the second semiconductor film with laser light. a buffer layer is formed on the third semiconductor film, and an n-type impurity source is deposited on the buffer layer; a fourth semiconductor film containing a semiconductor element; and a source electrode or a drain electrode formed on the fourth semiconductor film. This is a method for manufacturing a display device that forms a pole.

[0023] In the above manufacturing method, the first semiconductor film is a microcrystalline semiconductor film, and the third semiconductor film is a The term "highly crystalline" used in this specification means that the crystallinity of the semiconductor film is higher than that of the semiconductor film of the first embodiment. This refers to a high crystalline / amorphous peak intensity ratio (hereinafter referred to as Ic / Ia).

[0024] The present invention solves at least one of the above problems.

[0025] Microcrystalline semiconductor films are formed using high-frequency plasma CVD equipment with frequencies ranging from several tens to several hundreds of MHz. can be formed by a microwave plasma CVD apparatus with a frequency of 1 GHz or more. Typically, it can be formed by diluting silicon hydride such as SiH4 or Si2H6 with hydrogen. In addition to silicon hydride and hydrogen, it can also be produced from helium, argon, krypton, and neon. A microcrystalline semiconductor film can be formed by diluting the semiconductor with one or more selected rare gas elements. In these cases, the flow rate ratio of hydrogen to silicon hydride is preferably 12 times or more and 1000 times or less. Preferably, it is 50 times or more and 200 times or less, and more preferably 100 times. Instead, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. can be used. .

[0026] In addition, the amount of hydrogen in the microcrystalline semiconductor film obtained by the above film formation method is usually Since the amount of hydrogen in the amorphous silicon film is less than that of the hydrogenated amorphous silicon film, no heat treatment for dehydrogenation is required. Both can be subjected to LP processing.

[0027] When forming a microcrystalline semiconductor film with a thickness of 10 nm to 50 nm on a gate insulating film, Therefore, it is difficult to obtain a highly crystalline film immediately after film formation. Therefore, even if half of the film is amorphous, there will be at least some fine crystals in the film after film formation that will act as nuclei for growth. Therefore, it is possible to widen the margin of the film formation conditions of the microcrystalline semiconductor film. This can be done.

[0028] In addition, mass separation is performed on a microcrystalline semiconductor film that becomes a channel formation region of a thin film transistor. The threshold voltage is intentionally increased by adding impurity elements that give conductivity using an ion implantation method. The impurity elements that give the conductivity are phosphorus, arsenic, and boron. The dopant gas used in the mass-separated ion implantation method is phosphatide. Examples include fin and diborane. Impurity elements that give one conductivity by ion implantation. By adding , even if the crystallinity decreases compared to immediately after film formation, LP processing is performed, Ultimately, the crystallinity can be improved.

[0029] Furthermore, the present invention is not limited to an ion implantation device, and may be applied to a microcrystalline semiconductor film having a film thickness of 10 nm to 50 nm. If the threshold can be controlled by adding impurity elements that give electrical conductivity, it is possible to An on-doping device or the like may also be used.

[0030] Impurities that give one conductivity to a microcrystalline semiconductor film of 10 nm to 50 nm by ion implantation. In order to add a desired amount of element, for example, a silicon nitride film having a desired thickness is formed and then ion implanted. The LP treatment may be performed after the silicon nitride film is removed. The thickness of the silicon nitride film used for adjustment is determined by the concentration profile of the dopant ion-implanted into the sample. In addition, the dopant gas used in the mass-separated ion implantation method can be calculated from the Do B 10 H 14 , B 18 H 22 If ion implantation is performed using The amount of boron added can be reduced, and the desired amount of boron can be added to a microcrystalline semiconductor film of 10 nm to 50 nm. It can be done.

[0031] Doping is performed to control the threshold value using an ion implantation device or ion doping device. However, by performing LP treatment after doping, the damage to the microcrystalline semiconductor film can be reduced. Furthermore, depending on the LP processing conditions, the microcrystalline semiconductor film can be more uniform than the one before doping. Furthermore, the crystallinity can be improved.

[0032] The microcrystalline semiconductor film may be heated while being irradiated with a laser beam. Typically, the substrate is heated to a temperature between 300°C and 400°C and irradiated with a laser beam. By irradiating the microcrystalline semiconductor film with light, the crystallinity of the microcrystalline semiconductor film can be improved. The temperature of the microcrystalline semiconductor film is instantaneously increased by irradiating the film with a laser beam and intense light. A typical example of strong light is infrared light, especially light with a peak at 1 μm to 2 μm. Infrared light (preferably halogen light (1.3 μm)) can be used.

[0033] Also, if a thin oxide film is formed during LP processing, it can be removed by wet etching. By removing the oxide film, it is preferable to form a film at the interface between the LPSAS film and the buffer layer. It is possible to reduce the obstruction of carrier movement caused by the oxide film. The thickness of the LPSAS film can be reduced by etching. By setting the upper thickness to 50 nm or less, a fully depleted thin film transistor can be fabricated.

[0034] In addition, it is preferable to clean the surface of the microcrystalline semiconductor film before the LP treatment. By cleaning, impurities attached to the surface of the microcrystalline semiconductor film are removed by laser beam irradiation. This can prevent the crystalline semiconductor film from being contaminated.

[0035] In addition, after LP processing, ion implantation is performed, and then a second LP processing or heat treatment is performed. Another aspect of the present invention is to form a gate electrode on a substrate, and an insulating film on the gate electrode. a first semiconductor film overlapping the gate electrode is formed on the insulating film; A semiconductor film is irradiated with a first laser beam to form a second semiconductor film, and p a third semiconductor film is formed by adding a n-type impurity element or an n-type impurity element to the third semiconductor film; A fourth semiconductor film is formed by irradiating the semiconductor film with a second laser beam, and a backing is formed on the fourth semiconductor film. a fifth semiconductor film containing an n-type impurity element is formed on the buffer layer; The fifth aspect is a method for manufacturing a display device, in which a source electrode or a drain electrode is formed on the semiconductor film. do.

[0036] In the above manufacturing method, the first semiconductor film is a microcrystalline semiconductor film, and the fourth semiconductor film is a The semiconductor film is a microcrystalline semiconductor film having higher crystallinity than the semiconductor film of 1.

[0037] The present invention solves at least one of the above problems.

[0038] If the crystallinity of the microcrystalline semiconductor film is improved by performing LP treatment in advance, the crystallinity of the microcrystalline semiconductor film can be improved by ion implantation. It is possible to prevent the semiconductor film from becoming completely amorphous. The second LP treatment does not have to be performed under the same conditions. It is preferable to remove the ion implantation layer before forming the ion implantation layer. Since an oxide film is formed on the surface even in the case of a silicon dioxide film, it is preferable to remove it before forming the buffer layer. I wish.

[0039] In addition, the present invention is not limited to ion implantation after film formation, but may be applied to control the threshold value of thin film transistors. A microcrystalline semiconductor film is formed by adding a small amount of boron or phosphorus element to the film during film formation, and after film formation, The LP process may be performed. Another aspect of the present invention is to form a gate electrode on a substrate, An insulating film is formed on the electrode, and a second impurity layer containing a p-type impurity element or an n-type impurity element is formed on the insulating film. forming a first semiconductor film, and irradiating the first semiconductor film with laser light to form a second semiconductor film; a buffer layer is formed on the second semiconductor film, and an n-type impurity element is doped on the buffer layer; a third semiconductor film containing a source electrode or a drain electrode on the third semiconductor film; This is a manufacturing method of a display device.

[0040] In the above manufacturing method, the first semiconductor film is a microcrystalline semiconductor film, and the second semiconductor film is a The semiconductor film is a microcrystalline semiconductor film having higher crystallinity than the semiconductor film of 1.

[0041] The present invention solves at least one of the above problems.

[0042] When a microcrystalline semiconductor film is formed by adding a small amount of boron during film formation and then performing LP processing after film formation Unlike ion implantation after film formation, there is no need to add a separate process to activate boron. The LP process improves the crystallinity of the film because it contains a small amount of boron. When LP processing is performed after film formation, ion implantation and ion This process is suitable for mass production because it eliminates the need for processes such as cleaning before implantation. A method for incorporating a small amount of boron is to use diborane gas as one of the deposition gases during deposition. This can be done by introducing a trace amount of phosphorus into the film chamber. For example, a method for forming a microcrystalline semiconductor film by mixing a small amount of fluorine with a gas containing fluorine is used as one of the deposition gases during film formation. This can be done by introducing phosphine gas into the film formation chamber.

[0043] A display device obtained by using the above-described manufacturing method is also one aspect of the present invention. A gate electrode is formed on the substrate, an insulating film is formed on the gate electrode, and a p-type A first semiconductor film containing an impurity element or an n-type impurity element, and a buffer layer formed on the first semiconductor film. a buffer layer, a second semiconductor film containing an n-type impurity element on the buffer layer, and a second semiconductor film on the second semiconductor film. and a source electrode or a drain electrode.

[0044] The display device also includes a light-emitting device and a liquid crystal display device. The liquid crystal display device includes a liquid crystal element. The light-emitting element has a luminance controlled by a current or a voltage. This category includes elements that emit light, specifically inorganic EL (Electro Luminescence) These include organic EL, etc.

[0045] The display device includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, the present invention also includes a module in which an IC including a laser is mounted. In the process of manufacturing the display element, the element substrate corresponds to one form before the display element is completed, The element substrate includes means for supplying a current to each of the plurality of pixels. Specifically, only the pixel electrodes of the display element may be formed, or the pixel electrodes and After forming a conductive film, the state before etching to form a pixel electrode is shown. is fine, and all forms apply.

[0046] In this specification, the term "display device" refers to an image display device, a light-emitting device, or a light It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted. [Effects of the Invention]

[0047] A microcrystalline semiconductor film containing a p-type impurity element or an n-type impurity element is used as a channel formation region. The microcrystalline semiconductor film is intentionally doped with p-type impurity elements or n-type impurity elements. It is possible to realize a thin film transistor whose threshold voltage is controlled to a desired value. [Brief explanation of the drawings]

[0048] [Figure 1] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Figure 2] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Figure 3] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Figure 4] 1A to 1C are top views showing manufacturing steps of the present invention; [Figure 5] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Figure 6] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Figure 7] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Figure 8] 1A and 1B are diagrams illustrating a multi-tone mask applicable to the present invention. [Figure 9] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Figure 10] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Figure 11] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Figure 12] 1A to 1C are top views showing manufacturing steps of the present invention; [Figure 13] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 14] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 15] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 16] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 17] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 18] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 19] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 20] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 21] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 22] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 23] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 24] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 25] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 26] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 27] 1A to 1C are cross-sectional views illustrating a method for manufacturing a light-emitting device of the present invention. [Figure 28] 1 is a cross-sectional view illustrating a pixel applicable to a light-emitting device of the present invention. [Figure 29] FIG. 1 is a perspective view illustrating a display panel of the present invention. [Figure 30] 1 is a perspective view illustrating an electronic device using a light-emitting device of the present invention. [Figure 31] 1A to 1C are diagrams illustrating electronic devices using light-emitting devices of the present invention. [Figure 32] FIG. 1 is a block diagram illustrating a configuration of a light emitting device according to the present invention. [Figure 33] FIG. 2 is an equivalent circuit diagram illustrating the configuration of a drive circuit for the light emitting device of the present invention. [Figure 34] FIG. 2 is an equivalent circuit diagram illustrating the configuration of a drive circuit for the light emitting device of the present invention. [Figure 35] FIG. 2 is a top view illustrating the layout of a drive circuit of a light emitting device according to the present invention. [Figure 36] 1A and 1B are a top view and a cross-sectional view illustrating a display panel of the present invention. [Figure 37] 1A and 1B are a top view and a cross-sectional view illustrating a display panel of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0049] Although the present invention can be embodied in many different ways, the following description of the preferred embodiments of the present invention is provided. and the embodiments described herein may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications can be made to the details of the present embodiment. It should not be construed as being limited to the contents described.

[0050] (Embodiment 1) In this embodiment mode, a manufacturing process of a thin film transistor used in a liquid crystal display device will be described with reference to FIGS. 1 to 3 are cross-sectional views showing a manufacturing process of a thin film transistor. FIG. 4 is a top view of a connection region of a thin film transistor and a pixel electrode in one pixel. be.

[0051] Thin film transistors with microcrystalline semiconductor films have higher mobility when they are n-type than when they are p-type. It is more suitable for use in operating circuits. It is desirable to have the same polarity in order to reduce the number of processes. This will be explained using a thin film transistor of this type.

[0052] As shown in FIG. 1A, a gate electrode 51 is formed on a substrate 50. The substrate 50 is aluminoborosilicate glass, aluminoborosilicate glass, or aluminosilicate glass Alkali-free glass substrates and ceramic substrates manufactured by the fusion method or float method. In addition, a plastic substrate or the like that has heat resistance that can withstand the processing temperature of this manufacturing process should be used. It is also possible to use a substrate in which an insulating film is provided on the surface of a metal substrate such as a stainless steel alloy. If the substrate 50 is a mother glass, the size of the substrate is 1st generation (320mm x 40 0mm), 2nd generation (400mm x 500mm), 3rd generation (550mm x 650mm) , 4th generation (680mm x 880mm or 730mm x 920mm), 5th generation (1 000mm x 1200mm or 1100mm x 1250mm, 6th generation (1500m m x 1800mm), 7th generation (1900mm x 2200mm), 8th generation (2160m m×2460mm), 9th generation (2400mm×2800mm, 2450mm×3050 mm), 10th generation (2950mm x 3400mm), etc. can be used.

[0053] The gate electrode 51 is made of titanium, molybdenum, chromium, tantalum, tungsten, or aluminum. The gate electrode 51 is formed by sputtering. A conductive film is formed on the substrate 50 by a coating method or a vacuum deposition method, and a photolithography is performed on the conductive film. A mask is formed by a technique or an inkjet method, and the conductive film is etched using the mask. It can be formed by coating. Also, conductive nanopaste such as silver, gold, or copper can be used. The gate electrode 51 can also be formed by discharging the material by an ink jet method and baking it. The above gold is used as a barrier metal to improve the adhesion of the gate electrode 51 and to prevent diffusion to the underlying layer. A nitride film of a metal material may be provided between the substrate 50 and the gate electrode 51. A conductive film formed on the substrate 50 using a resist mask formed using the photomask The gate electrode is formed by etching.

[0054] As a specific example of a gate electrode structure, a molybdenum film is laminated on an aluminum film. It may be possible to use a structure that prevents hillocks and electromigration that are specific to aluminum. Alternatively, a three-layer structure may be used in which an aluminum film is sandwiched between molybdenum films. Examples of structures include a molybdenum film stacked on a copper film, a titanium nitride film stacked on a copper film, and a Examples include lamination of a tantalum nitride film.

[0055] Since a semiconductor film and wiring are formed on the gate electrode 51, the edge is It is desirable to process it so that it has a tapered shape. Wiring connected to the electrodes can also be formed at the same time.

[0056] Next, gate insulating films 52a, 52b, and 52c and a microcrystalline semiconductor film 2 are formed on the gate electrode 51. The cross-sectional view after completing the steps up to this point corresponds to FIG. 1(A). The gate insulating films 52a, 52b, and 52c and the microcrystalline semiconductor film 23a are not exposed to the air. It is preferable to form the film continuously. By forming the film continuously, the air components and the airborne particles can be prevented from being dispersed. Since each layer interface can be formed without being contaminated by contaminating impurity elements, thin film transistors The variation in the transistor characteristics can be reduced.

[0057] The gate insulating films 52a, 52b, and 52c are formed by using a CVD method, a sputtering method, or the like. The insulating film can be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. In order to prevent interlayer short circuits due to pinholes or the like formed in the gate insulating film 52, It is preferable to form a multilayer structure using insulating layers such as gate insulating films 52a and 52b. , 52c, a silicon nitride film, a silicon oxynitride film, and a silicon nitride film are laminated in this order. Shows.

[0058] Here, the silicon oxynitride film is a film whose composition contains more oxygen than nitrogen. Rutherford Backscattering (RBS) ering spectrometry and hydrogen forward scattering (HFS) n Forward Scattering) as the concentration range Oxygen 50-70 atomic %, Nitrogen 0.5-15 atomic %, Si 25-35 atomic %, Hydrogen The silicon nitride oxide film is a film containing silicon dioxide in a range of 0.1 to 10 atomic percent. The nitrogen content is higher than the oxygen content, and the measurement is performed using RBS and HFS. In this case, the concentration ranges are 5 to 30 atomic % for oxygen, 20 to 55 atomic % for nitrogen, and 25 atomic % for Si. % to 35 atomic %, and hydrogen in the range of 10 to 30 atomic %.

[0059] The thickness of each of the first and second layers of the gate insulating film 52 is set to be greater than 50 nm. The first layer of the insulating film is made of nitrogen to prevent the diffusion of impurities (such as alkali metals) from the substrate. The first layer of the gate insulating film 52 is preferably a silicon nitride film or a silicon nitride oxide film. In addition to preventing oxidation of the electrode, it can also prevent hillocks when aluminum is used for the gate electrode. The third layer of the gate insulating film 52 in contact with the microcrystalline semiconductor film is thicker than 0 nm and less than 10 nm. The third layer of the gate insulating film 52 is made of a metal in order to improve adhesion with the microcrystalline semiconductor film. In addition, by forming the third layer of the gate insulating film 52 as a silicon nitride film, the subsequent The microcrystalline semiconductor film can be prevented from being oxidized by heat treatment or laser irradiation. When heat treatment is performed in a state where an insulating film with a high oxygen content is in contact with a microcrystalline semiconductor film, the microcrystalline semiconductor There is a risk of the conductive film being oxidized.

[0060] Furthermore, a gate insulating film 52 is formed using a microwave plasma CVD apparatus with a frequency of 1 GHz. It is preferable to form a silicon oxynitride film, a nitride film, etc., formed by a microwave plasma CVD apparatus. The silicon oxide film has a high breakdown voltage and can improve the reliability of the thin film transistor.

[0061] The microcrystalline semiconductor film 23a has an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal). This semiconductor has a third state that is stable in terms of free energy. It is a semiconductor that has a short-range order and crystalline lattice distortion, and has a grain size of 0 Columnar or needle-like crystals of 0.5 to 20 nm grow in the normal direction to the substrate surface. A typical example of a microcrystalline semiconductor is a microcrystalline semiconductor. Silicon has a Raman spectrum of 520.5 cm, which is indicative of single-crystal silicon. -1 lower than The wave number shifts to 520.5 cm, which indicates single crystal silicon. -1 and Amorph 480cm showing the as-silicon -1 The Raman spectrum of microcrystalline silicon has a peak between In addition, hydrogen or halogen is used to terminate dangling bonds. It contains at least 1 atomic percent or more of helium, argon, krypton, etc. By adding rare gas elements such as neon to further increase the lattice distortion, the stability is increased. A good microcrystalline semiconductor film can be obtained. Such a microcrystalline semiconductor film can be described, for example, in Disclosed in U.S. Patent No. 4,409,134.

[0062] This microcrystalline semiconductor film 23a is formed by high-frequency plasma CV with a frequency of several tens to several hundreds of MHz. It is formed by a microwave plasma CVD device or a microwave plasma CVD device with a frequency of 1 GHz or more. Typically, silicon hydrides such as SiH4 and Si2H6 are diluted with hydrogen to form In addition to silicon hydride and hydrogen, helium, argon, krypton, etc. and diluting the gas with one or more rare gas elements selected from neon to form a microcrystalline semiconductor film. In these cases, the flow rate ratio of hydrogen to silicon hydride is 12 times or more, i.e., 1000 times or more. 100 times or less, preferably 50 times or more and 200 times or less, and more preferably 100 times. Instead of silicon hydride, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. are used. It is possible.

[0063] The oxygen concentration of the microcrystalline semiconductor film 23a is set to 5×10 19 atoms / cm 3 Below is good Preferably 1 x 10 19 atoms / cm 3 In the following, the concentrations of nitrogen and carbon are 3×10 18 atoms / cm 3 It is preferable that oxygen, nitrogen, and carbon are contained in the microcrystalline semiconductor. By reducing the concentration of the impurities mixed into the semiconductor film, it is possible to prevent the microcrystalline semiconductor film from becoming n-type. This can be done.

[0064] The thickness of the microcrystalline semiconductor film 23a is 1 nm or more and 20 nm or less, preferably 2 nm or more and 10 nm or less. In the LP treatment to be performed later, the thickness of the microcrystalline semiconductor film 23a is set to 4 nm to 8 nm. m, the absorption rate of the laser beam can be increased. By setting the thickness of the microcrystalline semiconductor film 23a within the above range, it is possible to The thin film transistor is a fully depleted type. The deposition speed is 1 / 10 to 1 / 100 of that of amorphous semiconductor films, so by making the film thinner, This can improve the investment.

[0065] Before the microcrystalline semiconductor film 23a is formed, the surface of the gate insulating film 52c is irradiated with hydrogen plasma. By performing hydrogen plasma treatment, the gate insulating film and the microcrystalline semiconductor film It is possible to reduce the lattice distortion at the interface, and the interface between the gate insulating film and the microcrystalline semiconductor film This improves the electrical characteristics of the thin film transistors that will be formed later. It can improve the performance.

[0066] Next, in order to control the threshold voltage, an impurity element that imparts one conductivity is intentionally implanted by ion implantation. The microcrystalline semiconductor film 23a immediately after deposition exhibits weak n-type electrical conductivity. Here, a small amount of boron is added to perform channel doping for controlling the threshold voltage. In this way, a microcrystalline semiconductor film 23b containing boron is obtained as shown in FIG. By implanting ions, the microcrystalline semiconductor film 23a containing boron becomes larger than the microcrystalline semiconductor film 23a immediately after the film formation. The crystallinity of the crystalline semiconductor film 23b decreases.

[0067] Next, in order to improve the crystallinity of the microcrystalline semiconductor film 23a as soon as it is formed, The laser beam is irradiated from the surface side of the microcrystalline semiconductor film. Since the gate electrode 51 is located below, it is not irradiated with the laser beam. The energy range should be determined taking into consideration the diffusion of heat generated by the laser beam. Depending on the energy of the beam, the microcrystalline semiconductor film in the region not overlapping with the gate electrode 51 may melt. On the other hand, the area overlapping with the gate electrode 51 may not melt. Since the film quality formed in the region where the gate electrode is not overlapped is different from that in the region where the gate electrode is not overlapped, In the semiconductor layer used as a thin film transistor, preferably, only the region overlapping with the gate electrode is The area overlapping the gate electrode is used, excluding the tapered portion of the gate electrode. By using a semiconductor film as the channel formation region, the characteristic variations among multiple thin film transistors can be reduced. can be reduced.

[0068] The laser beam can reach the interface between the microcrystalline semiconductor film and the gate insulating film 52c. As a result, the crystals on the surface side of the microcrystalline semiconductor film are used as seeds, and the gate insulating film is formed from the surface. A microcrystalline semiconductor film with improved crystallinity due to solid phase crystal growth at the interface of the insulating film, known as LPSA. The S film 53 can be formed (see FIG. 1(C)). The solid phase crystal growth by the LP process is It does not increase the grain size, but rather improves the crystallinity in the thickness direction of the film. That is, the LP treatment improves the crystallinity of the microcrystalline semiconductor film near the gate insulating film. This has the effect of improving the electrical characteristics of a thin film transistor having a bottom gate structure.

[0069] Furthermore, the LP treatment here can also activate boron added to the microcrystalline semiconductor film. The boron contained in the microcrystalline semiconductor film controls the threshold voltage to a desired value. For example, a thin film transistor can be obtained by using boron contained in a microcrystalline semiconductor film. If the threshold voltage can be controlled to 0V or the negative threshold voltage, a thin-film transistor When the gate voltage applied to the gate of the thin film transistor is set to 0V, the thin film transistor is in the off state. The switching element can be a normally-off switching element.

[0070] When using an excimer laser as the laser beam, the pulse oscillation frequency must be 1Hz or more and 10M Hz, preferably 100 Hz to 10 kHz, and the laser energy is 0.2 to 0.3 5J / cm 2 (Typically 0.2-0.3J / cm 2 ) Also, YAG laser is used. If the third harmonic is used, the pulse oscillation frequency should be 1 Hz or more and less than 10 MHz. Laser energy: 0.2 to 0.35 J / cm 2 (Typically 0.2-0.3J / cm 2 ) It would be good to say so.

[0071] The laser oscillator that emits the laser beam can be pulsed or continuously oscillated. In addition, the laser wavelength can be set to a value that efficiently transmits laser light to the semiconductor film. The visible to ultraviolet region (800 nm or less) is preferably in the ultraviolet region ( The wavelength is 300nm to 400nm. The laser oscillator is KrF, Excimer laser oscillators such as ArF, XeCl, XeF, N2, He, He-Cd, Ar, Gas laser oscillators such as He-Ne, HF, CO2, YAG, GdVO4, YVO4, YL F, YAlO3, ScO3, Lu2O3, Y2O3 crystals with Cr, Nd, Er, Ho Solid-state laser oscillator using a crystal doped with Ce, Co, Ti, Yb, or Tm, KG Solid-state lasers such as W laser, KYW laser, Alexandrite laser, Ti: sapphire laser, etc. A metal vapor laser oscillator such as a helium cadmium laser can be used. In a solid-state laser oscillator, it is preferable to use the second to fifth harmonics of the fundamental wave. It's nice.

[0072] Typically, the laser beam has a wavelength of 400 nm or less, typically 308 nm. A laser beam or the third harmonic (355 nm) of a YAG laser is used.

[0073] LP processing is performed by focusing the light into a long rectangular shape and making it into a linear laser beam, for example, 730mm x 9 The microcrystalline semiconductor film 23b on the 20 mm glass substrate is processed by one laser beam scan. In this case, the overlap rate of the linear laser beams is The treatment is carried out at a rate of 0 to 95% (preferably 0 to 67%). This reduces the time required and improves productivity. The shape of the laser beam is not limited to a linear shape. The LP treatment can be carried out on the glass surface as well. The size of the substrate is not limited, and the present invention can be applied to a variety of substrates.

[0074] In addition, when a continuous wave laser beam is used as the laser beam, a polygon mirror or a glass A laser beam is scanned at high speed by placing a mirror between the oscillator and the substrate. It is possible to improve the throughput of the process, for example, LP processing of microcrystalline semiconductor films formed on glass substrates or larger glass substrates. It is possible.

[0075] In addition, laser beams can be generated in an argon atmosphere, a hydrogen atmosphere, an argon and hydrogen atmosphere, a nitrogen atmosphere, etc. In this way, the microcrystalline semiconductor film 23b may be irradiated with a laser beam in an inert atmosphere. By irradiating the microcrystalline semiconductor film with the laser beam, an oxide film is formed on the surface of the LPSAS film 53. Stake.

[0076] In addition, before the microcrystalline semiconductor film 23b is irradiated with a laser beam, the surface of the microcrystalline semiconductor film 23b is By cleaning the surface, the surface of the microcrystalline semiconductor film 23b is free from the metals that adhere to the surface of the microcrystalline semiconductor film 23b during channel doping or the like. Therefore, impurities can be prevented from being mixed into the microcrystalline semiconductor film by laser beam irradiation. do.

[0077] The microcrystalline semiconductor film may be heated while being irradiated with a laser beam. Typically, the substrate 50 is heated to 300°C to 400°C and irradiated with a laser beam. By doing so, the crystallinity of the microcrystalline semiconductor film 23b can be improved. The conductor film 23b is irradiated with a laser beam and strong light, and the microcrystalline semiconductor The temperature of the film 23b may be increased. A typical example of strong light is infrared light, particularly light of 1 μm to 2 μm. Infrared light having a peak at 1.3 μm (preferably halogen light (1.3 μm)) can be used. do.

[0078] Next, as shown in FIG. 1(D), a buffer layer 54 and a one-conductivity type are formed on the LPSAS film 53. A semiconductor film 55 to which the impurity to be added is formed. If an oxide film is formed on the surface of the AS film 53, it is removed before forming the buffer layer 54. It is preferable.

[0079] The buffer layer 54 is formed using an amorphous semiconductor film containing hydrogen, nitrogen, or halogen. The flow rate of the silicon hydride is 1 to 10 times, more preferably 1 to 5 times. Using hydrogen, an amorphous semiconductor film containing hydrogen can be formed. A nitrogen-containing amorphous semiconductor film is formed by using hydrogen and nitrogen or ammonia. In addition, the silicon hydride and a gas containing fluorine, chlorine, bromine, or iodine (F 2, Cl2, Br2, I2, HF, HCl, HBr, HI, etc.) to An amorphous semiconductor film containing chlorine, bromine, or iodine can be formed. Instead of silicon, use SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. can be done.

[0080] The buffer layer 54 is formed by sputtering with hydrogen or a rare gas using an amorphous semiconductor as a target. An amorphous semiconductor film can be formed by pulverizing the ammonium, nitrogen, Alternatively, by including N2O in the atmosphere, an amorphous semiconductor film containing nitrogen can be formed. In addition, if the atmosphere contains gases containing fluorine, chlorine, bromine, or iodine (F2, C By incorporating fluorine, An amorphous semiconductor film containing chlorine, bromine, or iodine can be formed.

[0081] In addition, a buffer layer 54 is formed on the surface of the LPSAS film 53 by plasma CVD or sputtering. After forming an amorphous semiconductor film by a deposition method, the surface of the amorphous semiconductor film is irradiated with hydrogen plasma, The surface of the amorphous semiconductor film is hydrogenated and nitrogenated by treating it with nitrogen plasma or halogen plasma. Alternatively, the surface of the amorphous semiconductor film may be irradiated with helium plasma. The treatment may be carried out with argon plasma, neon plasma, krypton plasma, or the like.

[0082] The buffer layer 54 is preferably formed of an amorphous semiconductor film that does not contain crystal grains. Therefore, high frequency plasma CVD method with a frequency of several tens to several hundreds of MHz or microwave plasma CVD method is used. When forming the film using the Zuma CVD method, the film formation conditions are adjusted so that the film becomes an amorphous semiconductor film that does not contain crystal grains. It is preferable to control the conditions.

[0083] The buffer layer 54 is partially etched in the subsequent process of forming the source and drain regions. At this time, a part of the buffer layer 54 is formed so that the LPSAS film 53 is not exposed. It is preferable to form the remaining thickness. Typically, it is 100 nm or more and 400 nm or less. It is preferable to form the thin film transistor with a thickness of 200 nm or more and 300 nm or less. In display devices with high applied voltages to the transistor (for example, about 15 V), typically liquid crystal display devices Therefore, when the buffer layer 54 is formed to have a thickness within the above range, the breakdown voltage increases. Even if a high voltage is applied to the thin film transistor, the thin film transistor is prevented from deteriorating. It is possible.

[0084] The buffer layer 54 is doped with impurities such as phosphorus or boron that impart one conductivity type. The LPSAS film 53 contains a small amount of boron to control the threshold voltage. Impurities are diffused from the semiconductor film 55, which is doped with impurities that give one conductivity type, into the LPSAS film. The buffer layer 54 functions as a barrier layer to prevent this. In this case, the LPSAS film and the semiconductor film 55 doped with an impurity that gives one conductivity type come into contact with each other. If this is done, impurities will move during subsequent etching and heat treatment, making it difficult to control the threshold voltage. There is a risk.

[0085] Furthermore, a buffer layer 54 is formed on the surface of the LPSAS film 53. It is possible to prevent natural oxidation of the surface of the crystal grains contained in the amorphous semiconductor. In the area where the fine crystal grains contact, cracks are likely to occur due to local stress. When these cracks come into contact with oxygen, The crystal grains are oxidized and silicon oxide is formed.

[0086] The energy gap of the buffer layer 54, which is an amorphous semiconductor film, is smaller than that of the LPSAS film 53. The energy gap of the amorphous semiconductor film is 1.6 to 1.8 eV, and the LPSAS film is 53 The energy gap of LPS is 1.1-1.5 eV, and the resistance is high, the mobility is low, and the LPS This is 1 / 5 to 1 / 10 of the AS film 53. In this case, a buffer layer is formed between the source and drain regions and the LPSAS film 53. The LPSAS film 53 functions as a channel forming region. Therefore, the off-current of the thin film transistor can be reduced. When used as a switching element of a display device, the contrast of the display device can be improved. can be done.

[0087] A buffer layer 54 is formed on the LPSAS film 53 by plasma CVD at 300° C. to 40° C. It is preferable to form the film at a temperature of 0° C. This film forming process allows hydrogen to be absorbed into the LPSAS film 53. The same effect as hydrogenating the LPSAS film 53 can be obtained. By depositing a buffer layer 54 on the LPSAS film 53, hydrogen is diffused into the LPSAS film 53. In this way, dangling bonds can be terminated.

[0088] The semiconductor film 55 to which an impurity that imparts one conductivity type is added is an n-channel thin film transistor. When forming a transistor, phosphorus is added as a typical impurity element, and hydrogenation All you need to do is add impurity gases such as PH3 to silicon. Also, p-channel thin film transistors In the case of forming silicon hydride, boron may be added as a typical impurity element. The impurity gas such as B2H6 can be added. The semiconductor film 55 can be formed of a microcrystalline semiconductor or an amorphous semiconductor. The semiconductor film 55 to which the impurity is added is formed to a thickness of 2 nm to 50 nm. By thinning the thickness of the semiconductor film to which impurities that give the conductivity type are added, throughput can be improved. It can be improved.

[0089] Next, as shown in FIG. 2(A), a semiconductor film 55 to which an impurity that imparts one conductivity type is added is formed. A resist mask 56 is formed on the resist mask 56 by photolithography or In this case, the second photomask is used to form the conductive film. The resist coated on the semiconductor film 55 to which the impurity for providing a pattern is added is exposed and developed. A resist mask 56 is formed.

[0090] Next, a resist mask 56 is used to form the LPSAS film 53, the buffer layer 54, and the conductive type The semiconductor film 55 to which the impurity is added is etched and separated, as shown in FIG. 2(B). As shown in the figure, the LPSAS film 61, the buffer layer 62, and the silicon dioxide film 63 doped with impurities that give one conductivity type are A semiconductor film 63 is formed, and then the resist mask 56 is removed.

[0091] The side surfaces of the LPSAS film 61 and the buffer layer 62 are inclined, so that the buffer layer 6 A leakage current occurs between the source and drain regions formed on the LPSAS film 61 and the LPSAS film 62. In addition, it is possible to prevent the occurrence of the problem by forming a source electrode, a drain electrode, and an LPS It is possible to prevent the occurrence of leakage current between the LPSAS film 61 and the LPSAS film 6. The inclination angle of the end side surface of the buffer layer 62 is 90° to 30°, preferably 80° to 40°. By setting the angle at this angle, the source electrode or drain electrode due to the step shape can be This can prevent the poles from breaking off.

[0092] Next, as shown in FIG. 2(C), a semiconductor film 63 and a semiconductor film 64 are doped with an impurity that gives one conductivity type. Conductive films 65a to 65c are formed to cover the gate insulating film 52c. 5c is aluminum, copper, or silicon, titanium, neodymium, scandium, molybdenum A single layer of aluminum alloy containing heat-resistant elements such as arsenic or hillock prevention elements. It is also preferable to form the semiconductor layer by lamination. The film on the side in contact with the conductive film is made of titanium, tantalum, molybdenum, tungsten, or any of these. A laminate formed of nitrides of the above elements and aluminum or aluminum alloy formed on top of them. Furthermore, the upper and lower surfaces of the aluminum or aluminum alloy may be Laminated layers sandwiched between tantalum, molybdenum, tungsten, or nitrides of these elements Here, the conductive film may have a structure in which three conductive films 65a to 65c are stacked. The conductive films 65a and 65c are made of molybdenum, and the conductive film 65b is made of aluminum. The conductive films 65a and 65c are made of titanium films, and the conductive film 65b is made of aluminum films. The conductive films 65a to 65c are formed by sputtering or vacuum deposition. Formed by law.

[0093] Next, as shown in FIG. 2(D), a third photomask is used to apply a photoresist to the conductive films 65a to 65c. A resist mask 66 is formed, and a part of the conductive films 65a to 65c is etched to form a pair of saw blades. The source and drain electrodes 71a to 71c are formed. When etching is performed, the conductive films 65a to 65c are selectively etched. In order to etch the resist mask 66 isotropically, the source electrode and the drain electrode, which have a smaller area than the resist mask 66, are The rain electrodes 71a to 71c can be formed.

[0094] Next, as shown in FIG. 3A, a resist mask 66 is used to apply an impurity to impart one conductivity type. The semiconductor film 63 doped with Zn is etched to form a pair of source and drain regions 72. Furthermore, in this etching step, a part of the buffer layer 62 is also etched. The buffer layer in which the recess (groove) is formed after being partially etched is shown as buffer layer 73. The source and drain regions are formed in the same process as the recesses (grooves) in the buffer layer. The depth of the recess (groove) in the buffer layer can be adjusted by adjusting the thickness of the thickest part of the buffer layer. By setting the distance between the source and drain regions to 1 / 2 to 1 / 3 of the above, it is possible to increase the distance between the source and drain regions. Therefore, the leakage current between the source region and the drain region can be reduced. Thereafter, the resist mask 66 is removed.

[0095] In particular, when exposed to plasma used in dry etching, the resist mask changes in quality and The buffer layer is not completely removed in the substrate removal process, and a 50 nm thick layer is added to prevent residues from remaining. The resist mask 66 is removed by etching a portion of the conductive films 65a to 65c. and an etching process for forming the source and drain regions 72. In both cases, dry etching tends to leave residue, so it is necessary to completely remove the residue. It is effective to form a thick buffer layer that can be etched when the layer is removed. In addition, the buffer layer 73 is formed so that plasma damage is prevented from being caused to the LPSAS film during dry etching. It is also possible to prevent it from being given to 61.

[0096] Next, as shown in FIG. 3(B), the source and drain electrodes 71a to 71c, the source region the source and drain regions 72, the buffer layer 73, the LPSAS film 61, and the gate insulating film 52c. The insulating film 76 is formed to cover the gate insulating films 52a, 52b, and 52c. The insulating film 76 can be formed by the same film formation method. It is used to prevent the intrusion of contaminating impurities such as metals, particles, and water vapor, and a dense membrane is preferred. In addition, by using a silicon nitride film for the insulating film 76, the oxygen concentration in the buffer layer 73 can be reduced to 5× 10 19 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 The following It is possible.

[0097] As shown in FIG. 3B, the ends of the source and drain electrodes 71a to 71c and the source The ends of the source electrode and the drain region 72 are not aligned but are misaligned. Since the distance between the ends of the drain electrodes 71a to 71c is large, It is possible to prevent leakage current and short circuits. The ends of the regions a to 71c and the ends of the source and drain regions 72 are not aligned but are shifted. Therefore, the source and drain electrodes 71a to 71c and the source and drain regions 7 2, the electric field is not concentrated at the end of the gate electrode 51 and the source and drain electrodes 71a to 7 This prevents leakage current between the transistor 1c and the transistor 1b. This results in high reliability and a high breakdown voltage. Furthermore, channel doping is performed, and It is possible to fabricate a thin film transistor with a controlled threshold value.

[0098] Through the above steps, a channel-etch type thin film transistor 74 can be formed. .

[0099] The thin film transistor shown in this embodiment has a gate insulating film, an LPSAS film, A buffer layer, a source region, a drain region, a source electrode, and a drain electrode are laminated. The surface of the LPSAS film, which functions as a channel formation region, is covered with a buffer layer. A recess (groove) is formed in a part of the layer, and the area other than the recess is the source region and the drain region. That is, the source and drain regions are covered by the recesses formed in the buffer layer. The distance between the regions reduces leakage current between the source and drain regions. In addition, a recess can be formed by etching a part of the buffer layer. Therefore, etching residues generated in the process of forming the source and drain regions are removed. Therefore, leakage current (parasitic channel) flows through the residue to the source and drain regions. This can prevent the occurrence of

[0100] In addition, the LPSAS film that functions as the channel forming region and the source and drain regions are A buffer layer is formed between the LPSAS film and the LPSAS layer. The high-resistance buffer layer is placed between the LPSAS film and the source and drain regions. Since the wiring extends in this manner, it is possible to reduce the occurrence of leakage current in the thin film transistor. Furthermore, the buffer layer and the The LPSAS film, source region, and drain region are all formed on the area that overlaps with the gate electrode. Therefore, it can be said that the structure is not affected by the edge shape of the gate electrode. In this structure, if aluminum is used as the lower layer, aluminum will be attached to the side of the gate electrode. Although there is a risk of hillocks being formed, the source and drain regions are further exposed to the gate. By configuring it so that it does not overlap with the electrode edge, a short circuit does not occur in the area where it overlaps with the side of the gate electrode. In addition, the surface of the LPSAS film is terminated with hydrogen, which prevents the formation of non-metallic compounds. The amorphous semiconductor film is formed as a buffer layer, which prevents oxidation of the LPSAS film. In addition, etching residues generated in the process of forming the source and drain regions can be eliminated. This prevents the intrusion of residue into the LPSAS film, resulting in excellent electrical properties and durability. Therefore, a thin film transistor with excellent voltage can be formed.

[0101] In addition, the channel length of the thin film transistor can be shortened, and the plane area of ​​the thin film transistor can be reduced. can be reduced.

[0102] Next, a resist mask is formed on the insulating film 76 using a fourth photomask. A contact hole is formed by etching a part of 76, and A pixel electrode 77 is formed in contact with the source electrode or drain electrode 71c. ) corresponds to the cross section taken along the chain line AB in FIG.

[0103] As shown in FIG. 4, the ends of the source and drain regions 72 are connected to the source and drain electrodes. It can be seen that the edge of the buffer layer 73 is located outside the edge of the electrode 71c. The electrode and drain electrode 71c and the source and drain regions 72 are located outside the edge of the electrode and drain electrode 71c. In addition, one of the source electrode and the drain electrode surrounds the other of the source electrode and the drain electrode. Therefore, the surface area of ​​the area where the carriers move is It is possible to increase the product, which allows for a larger current flow. The area of ​​the gate electrode can be reduced. Since the source electrode and drain electrode are overlapped, the influence of the unevenness of the gate electrode is small, and the coating The source electrode or the drain electrode can be formed by the same method. One of the electrodes also functions as a source wiring or a drain wiring.

[0104] The pixel electrode 77 is made of indium oxide containing tungsten oxide. Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium tin oxide, indium zinc oxide, indium with silicon oxide A light-transmitting conductive material such as indium tin oxide can be used.

[0105] The pixel electrode 77 is made of a conductive composition containing a conductive macromolecule (also called a conductive polymer). The pixel electrode formed using the conductive composition can be formed using a sheet resistor. It is preferable that the resistance is 10000Ω / □ or less and the light transmittance at a wavelength of 550 nm is 70% or more. It is also preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm or less. It is preferable that

[0106] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0107] Here, the pixel electrode 77 is formed by depositing an indium tin oxide film by sputtering. After that, a resist is applied onto the indium tin oxide film. The resist is exposed and developed to form a resist mask. The indium tin oxide film is then etched to form the pixel electrode 77 .

[0108] In this manner, an element substrate that can be used in a display device can be formed.

[0109] (Embodiment 2) In this embodiment, the steps that are partially different from those in the first embodiment will be described below. Since only the parts are different, the same reference numerals are used in FIG. 5 for the same parts as in FIG. 1, and the same processes are Detailed explanation will be omitted.

[0110] First, the state shown in Fig. 5(A) is obtained in the same manner as in the first embodiment. Fig. 5(A) is the same as Fig. 1(A). After forming a gate electrode 51 on a substrate 50, a gate electrode 52 is formed on the gate electrode 51. Insulating films 52a, 52b, and 52c and a microcrystalline semiconductor film 23a are formed in this order.

[0111] As shown in FIG. 5B, the microcrystalline semiconductor film is subjected to the first LP treatment, and then the LPSA The S film 33a is formed by performing LP processing in advance to improve the crystallinity of the microcrystalline semiconductor film. This can prevent the semiconductor film from becoming completely amorphous due to ion implantation.

[0112] Next, as shown in FIG. 5(C), boron is implanted into the LPSAS film 33a by ion implantation. By ion implantation, the boron content is increased compared to the LPSAS film 33a. The crystallinity of the microcrystalline semiconductor film 33b containing the laser beam is reduced. If an oxide film is formed on the surface of the LPSAS film 33a due to irradiation of the ion beam, the ion implantation is continued. It is preferable to perform the ion implantation and remove it after the ion implantation. This oxide film functions as a surface protection film. It is possible.

[0113] Next, the second LP process is performed as shown in FIG. 5(D). The crystallinity is improved and the boron in the film is activated. The second LP treatment does not have to be performed under the same conditions. 3b It is preferable to clean the surface.

[0114] Alternatively, a heat treatment may be carried out instead of the second LP treatment. If the temperature is lower than the temperature that melts the conductive film and higher than the temperature that activates the boron in the film, That's fine.

[0115] Next, as shown in FIG. 5(E), a buffer layer 54 and one conductivity type are formed on the LPSAS film 53. A semiconductor film 55 is formed by adding impurities to the semiconductor film 55. FIG. 5(E) is the same as FIG. 1(D). The oxide film formed during the second LP process is removed before the buffer layer 54 is formed. It is preferable to remove it.

[0116] Although the number of steps increases compared to the first embodiment, the crystallinity is improved more than in the first embodiment. A LPSAS membrane can be obtained.

[0117] The subsequent steps are the same as those in the first embodiment, and therefore will be omitted here.

[0118] This embodiment mode can be freely combined with Embodiment Mode 1.

[0119] (Embodiment 3) In this embodiment, the steps that are partially different from those in the first embodiment will be described below. Since only the parts are different, the same reference numerals are used in FIG. 6 for the same parts as in FIG. 1, and the same steps are Detailed explanation will be omitted.

[0120] In this embodiment, an impurity element that imparts p-type conductivity is added at the same time as the film is formed. A process of performing LP treatment after forming a microcrystalline semiconductor film containing a trace amount of pure element will be described.

[0121] First, a gate electrode 51 is formed on a substrate 50 in the same manner as in the first embodiment. Gate insulating films 52a, 52b, and 52c are formed on the electrode 51. Then, as shown in FIG. As shown in the figure, the microcrystalline semiconductor film 4 intentionally contains an impurity element for the purpose of threshold voltage control. 3 is deposited.

[0122] The typical impurity element that gives the p-type is boron, and impurities such as B2H6 and BF3 are also used. The pure gas is added with silicon hydride at a ratio of 1 ppm to 1000 ppm, preferably 1 to 100 ppm. The concentration of boron contained in the microcrystalline semiconductor film 43 (measured by SIMS) concentration), e.g., 1 x 10 14 ~6×10 16 atoms / cm 3 It would be good to say so.

[0123] Next, in order to improve the crystallinity of the microcrystalline semiconductor film 43 as soon as it is formed, The laser beam is irradiated from the surface side. The energy of the laser beam melts the microcrystalline semiconductor film. By irradiating the laser beam, the result is as shown in Figure 6(B). It is possible to form an LPSAS film 53 with improved crystallinity.

[0124] When a microcrystalline semiconductor film is formed by adding a small amount of boron during film formation and then performing LP processing after film formation In this case, it is not necessary to activate boron, so the LP treatment here does not improve the crystallinity. The laser beam irradiation conditions may be set to be such that the laser beam is irradiated under the conditions described above.

[0125] In this experiment, a microcrystalline semiconductor film is formed by adding a small amount of boron during film formation, and LP processing is performed after film formation. By adopting this embodiment, the number of steps can be reduced, and therefore it can be said that this process is suitable for mass production.

[0126] In addition, when using an ion implantation device or ion doping device, depending on the doping conditions, When ions are added, the microcrystalline semiconductor film is damaged, and further, the gate insulating film is damaged. A small amount of boron is added during film formation to form a microcrystalline semiconductor film. If the device is fabricated using a thin film transistor, it will be possible to fabricate the thin film transistor without inflicting damage on the device. can.

[0127] Next, as shown in FIG. 6(C), a buffer layer 54 and a one-conductivity type are formed on the LPSAS film 53. A semiconductor film 55 containing the impurity to be added is formed. In addition, the oxide film formed during the LP process is removed before forming the buffer layer 54. It is preferable.

[0128] The subsequent steps are the same as those in the first embodiment, and therefore will be omitted here.

[0129] This embodiment mode can be freely combined with Embodiment Mode 1.

[0130] (Fourth embodiment) In this embodiment, the steps that are partially different from those in the first embodiment will be described below. Since only the parts are different, the same reference numerals are used in FIG. 7 for the same parts as in FIG. 1, and the same steps are Detailed explanation will be omitted.

[0131] First, the state shown in Fig. 7(A) is obtained in the same manner as in embodiment 1. Fig. 7(A) is the same as Fig. 1(C). After forming a gate electrode 51 on a substrate 50, a gate electrode 52 is formed on the gate electrode 51. Insulating films 52a, 52b, and 52c and a microcrystalline semiconductor film are formed in this order. For this purpose, an impurity element that imparts one conductivity to the microcrystalline semiconductor film is intentionally implanted by ion implantation. Next, in order to improve the crystallinity of the microcrystalline semiconductor film as soon as it is formed, The laser beam is irradiated from the surface side of the conductive film. Form.

[0132] Next, as shown in FIG. 7(B), the surface of the LPSAS film 53 is irradiated with hydrogen plasma and nitrogen plasma. or halogen plasma treatment. The LPSAS film 53 surface is irradiated with a laser beam. If an oxide film is formed on the surface, it must be removed before forming the buffer layer. Here, after removing the oxide film on the surface of the LPSAS film 53, the LPSAS film 5 3. Hydrogen plasma treatment is performed on the surface. The interface with the buffer layer to be formed later is clean. To achieve this, the surface is treated with hydrogen plasma, nitrogen plasma, or halogen plasma. LP by treating with hydrogen plasma, nitrogen plasma, or halogen plasma. The surface of the SAS film 53 can be made to be a surface on which an oxide film is less likely to form.

[0133] By preventing the formation of an oxide film on the surface of the LPSAS film 53, the threshold voltage increases. can be suppressed.

[0134] Next, as shown in FIG. 7(C), a buffer layer 54 and a one-conductivity type SiO 2 film are formed on the LPSAS film 53. A semiconductor film 55 containing the impurity to be added is formed. be.

[0135] The subsequent steps are the same as those in the first embodiment, and therefore will be omitted here.

[0136] This embodiment mode can be freely combined with any one of Embodiment Modes 1 to 3. Cut.

[0137] (Embodiment 5) A manufacturing method of a thin film transistor different from that in Embodiment 1 will be described with reference to FIGS. Here, a process that can reduce the number of photomasks compared to the first embodiment will be described. The process for fabricating a thin film transistor using this process will be described.

[0138] As in FIG. 1(A) shown in the first embodiment, a conductive film is formed on a substrate 50, and a laser is applied to the conductive film. A resist was applied to the substrate, and a resist was formed by a photolithography process using a first photomask. A resist mask is used to etch a portion of the conductive film to form a gate electrode 51. On the gate electrode 51, gate insulating films 52a, 52b, and 52c and a microcrystalline semiconductor film 23a are formed. Form in order.

[0139] Next, as in FIG. 1(B) shown in the first embodiment, a small amount of boron is added for the purpose of threshold control. Ion implantation is performed to form a microcrystalline semiconductor film 23b.

[0140] Next, in the same manner as in FIG. 1C shown in the first embodiment, a laser beam is irradiated to form an LPSAS Next, in the same manner as in FIG. 1(D) shown in the first embodiment, the LPSAS film 53 is formed. A buffer layer 54 and a semiconductor film 55 doped with impurities that impart one conductivity type are formed in this order on top of the semiconductor film 54. do.

[0141] Next, conductive films 65a to 65c are formed on the semiconductor film 55 to which an impurity imparting one conductivity type is added. Next, as shown in Fig. 9(A), a resist 80 is applied onto the conductive film 65a.

[0142] The resist 80 can be a positive resist or a negative resist. , shown using a positive resist.

[0143] Next, the resist 80 is irradiated with light using the multi-tone mask 59 as a second photomask. The resist 80 is exposed to light.

[0144] Here, exposure using the multi-tone mask 59 will be described with reference to FIG.

[0145] A multi-tone mask has three exposure levels: exposed, intermediately exposed, and unexposed. It is a mask that can be used in a single exposure and development process, and multiple (typically two types) ) thickness area. By using a mask, it is possible to reduce the number of photomasks.

[0146] Typical examples of multi-tone masks include a gray-tone mask 59a as shown in FIG. 8(C) shows a half-tone mask 59b.

[0147] As shown in FIG. 8(A), the gray-tone mask 59a is made of a light-transmitting substrate 163 and a The light-shielding portion 164 and the diffraction grating 165 are formed thereon. On the other hand, the diffraction grating 165 has slits, dots, meshes, etc. By making the intervals between the light transmitting portions such as the above equal to or less than the resolution limit of the light used for exposure, The transmittance can be controlled. The diffraction grating 165 has periodic slits, dots, Either a mesh or a non-periodic slits, dots, or mesh can be used.

[0148] The light-transmitting substrate 163 can be a light-transmitting substrate such as quartz. The portion 164 and the diffraction grating 165 are made of a light-shielding material that absorbs light, such as chromium or chromium oxide. It can be formed.

[0149] When the gray-tone mask 59a is irradiated with exposure light, the light-shielding portion 1 In the case of 64, the light transmittance 166 is 0%, and the light blocking portion 164 and the diffraction grating 165 are provided. In the unmodified area, the light transmittance 166 is 100%. The light transmittance of the diffraction grating 165 can be adjusted in the range of 10 to 70%. This is possible by adjusting the spacing and pitch of the slits, dots, or meshes of the diffraction grating. do.

[0150] As shown in FIG. 8C, the halftone mask 59b is formed on a light-transmitting substrate 163 and The semi-transmitting portion 167 and the light-shielding portion 168 are formed thereon. , MoSiN, MoSi, MoSiO, MoSiON, CrSi, etc. can be used. The light-shielding portion 168 is preferably formed using a light-shielding material that absorbs light, such as chromium or chromium oxide. This can be done.

[0151] When the halftone mask 59b is irradiated with exposure light, the light-shielding portion 1 In the case of 68, the light transmittance 169 is 0%, and the light blocking portion 168 and the semi-transmitting portion 167 are provided. In the non-transparent area, the light transmittance 169 is 100%. The light transmittance of the semi-transparent portion 167 can be adjusted in the range of 10 to 70%. This can be adjusted by adjusting the material of the semi-transparent portion 167.

[0152] After exposure using a multi-tone mask, development is performed to obtain a film with different film thicknesses, as shown in Figure 9(B). A resist mask 81 having the following regions can be formed.

[0153] Next, the resist mask 81 is used to form the LPSAS film 53, the buffer layer 54, and the layer 55 having one conductivity type. The semiconductor film 55 to which the impurity is added and the conductive films 65a to 65c are etched and separated. As a result, as shown in FIG. 10(A), a LPSAS film 61, a buffer layer 62, and a conductive film are formed. By forming the semiconductor film 63 to which an impurity for imparting a type is added and the conductive films 85a to 85c, It should be noted that FIG. 10(A) corresponds to a cross-sectional view taken along line AB in FIG. 12(A) (however, (excluding resist mask 86).

[0154] Next, the resist mask 81 is ashed. As a result, the area of ​​the resist is reduced and the thickness is At this time, the resist in the thin film region (which overlaps with a part of the gate electrode 51) The resist mask 86 is then removed to form a separate resist mask 86, as shown in FIG. 10(A). It is possible.

[0155] Next, the conductive films 85a to 85c are etched and separated using the resist mask 86. As a result, pairs of source and drain electrodes 92a to 92c are formed as shown in FIG. 10(B). The conductive films 85a to 85c are formed by wet etching using the resist mask 86. When etching is performed, the conductive films 85a to 85c are selectively etched. Since the film is isotropically etched, the source electrode and the Drain electrodes 92a to 92c can be formed.

[0156] Next, using a resist mask 86, a semiconductor film doped with an impurity that gives one conductivity type is 63 is etched to form a pair of source and drain regions 88. In the etching process, a part of the buffer layer 62 is also etched. The buffer layer is referred to as a buffer layer 87. A recess is formed in the buffer layer 87. The source and drain regions are formed in the same process as the recess (groove) in the buffer layer. Here, a part of the buffer layer 87 is formed on the surface of the resist mask 81. The resist mask 86 has been partially etched away, so that the source and drain regions The buffer layer 87 is formed to protrude outside the region 88. After this, the resist mask 86 is removed. Also, the ends of the source and drain electrodes 92a to 92c and the source and drain regions are removed. The ends of the drain region 88 are not aligned but are offset, and the source and drain electrodes 92a to 92c are aligned. Outside the ends of 2c, the ends of the source and drain regions 88 are formed.

[0157] 10(C) corresponds to a cross-sectional view taken along line AB in FIG. 12(B). Thus, the ends of the source and drain regions 88 are connected to the source and drain electrodes 92c. It can be seen that the edge of the buffer layer 87 is located outside the edge of the source electrode and the drain electrode. The drain electrode 92c is located outside the ends of the source and drain regions 88. One of the source and drain electrodes is shaped to surround the other of the source and drain regions (specifically, Specifically, it is U-shaped or C-shaped. Therefore, the area of ​​the region where carriers move is increased. It is possible to increase the amount of current, and the area of ​​the thin film transistor In addition, the microcrystalline semiconductor film, the source electrode, and the Since the gate electrode and drain electrode are overlapped, the influence of the unevenness of the gate electrode is small, and the coverage rate is reduced. The occurrence of leakage current can be suppressed. One of them also functions as a source wiring or a drain wiring.

[0158] As shown in FIG. 10(C), the ends of the source and drain electrodes 92a to 92c and the source The ends of the source and drain regions 88 are not aligned but are offset, so that the source electrode and Since the distance between the ends of the drain electrodes 92a to 92c is large, In addition, the source electrode and the drain electrode 9 can be prevented from leaking current or shorting. The ends of the electrodes 2a to 92c and the ends of the source and drain regions 88 are not aligned but are shifted. Therefore, the source and drain electrodes 92a to 92c and the source and drain regions The electric field is not concentrated at the end of the gate electrode 51 and the source and drain electrodes 92a to 88. Therefore, it is possible to prevent leakage current between the terminals 92c and 92d. High-voltage thin film transistors can be fabricated.

[0159] Through the above steps, a channel-etch type thin film transistor 83 can be formed. Also, a thin film transistor can be formed using two photomasks.

[0160] Next, as shown in FIG. 11(A), the source and drain electrodes 92a to 92c, the source the drain region 88, the buffer layer 87, the LPSAS film 90, and the gate insulating film 52. An insulating film 76 is formed on the gate insulating films 52a, 52b, and 52c. The same manufacturing method can be used to form the same.

[0161] Next, a resist mask formed using a third photomask is used to remove a portion of the insulating film 76. Then, a contact hole is formed by etching. A pixel electrode 77 is formed in contact with the source electrode or drain electrode 92c. As for 77, an indium tin oxide film is formed by sputtering, and then indium A resist is applied onto the tin oxide film. Then, the resist is exposed using a fourth photomask. and developing to form a resist mask. The oxide film is etched to form the pixel electrode 77. Note that FIG. 11(B) is similar to FIG. 12(C). This corresponds to the cross section of AB.

[0162] As a result, the number of masks can be reduced by using a multi-tone mask, and a device that can be used in a display device can be obtained. A daughter board can be formed.

[0163] This embodiment mode can be freely combined with any one of Embodiment Modes 1 to 4. Cut.

[0164] (Embodiment 6) In this embodiment mode, the thin film transistor described in Embodiment 1 is used as one mode of a display device. The liquid crystal display device having the above structure will be described below.

[0165] First, we will explain the VA (Vertical Alignment) type liquid crystal display device. VA type LCD devices are a type of LCD panel that controls the alignment of liquid crystal molecules. In VA type LCD devices, the liquid crystal molecules are aligned with the panel surface when no voltage is applied. In this embodiment, pixels are divided into several regions. The molecules are divided into sub-pixels (sub-pixels) and tilted in different directions. This is called multi-domain or multi-domain design. In the following explanation, multi-domain design A liquid crystal display device that takes into consideration the above will be described.

[0166] 14 and 15 show the pixel electrode and the counter electrode, respectively. 1 is a plan view of the substrate side on which the element electrodes are formed, and shows a cross-sectional structure corresponding to the cutting line AB shown in the figure. This is shown in FIG. 13. Also, FIG. 15 is a plan view of the substrate side on which the counter electrode is formed. The following description will refer to these figures.

[0167] FIG. 13 shows a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor 630. The substrate 600 on which the counter electrode 640 and the like are formed is superimposed on the counter substrate 601. The figure shows the state after the liquid crystal is injected.

[0168] The opposing substrate 601 has a light-shielding film 632 and a first adhesive film 642 formed at a position where the spacer 642 is to be formed. A color film 634, a second color film 636, a third color film 638, and a counter electrode 640 are formed. This structure allows the heights of the protrusions 644 and spacers 642 to be different for controlling the alignment of the liquid crystal. An alignment film 648 is formed on the pixel electrode 624, and similarly, an alignment film 648 is formed on the counter electrode 640. An alignment film 646 is also formed on the first and second electrodes 642. A liquid crystal layer 650 is formed between them.

[0169] Although the spacers 642 are shown as columnar spacers here, bead spacers may also be scattered. Furthermore, the spacers 642 are formed on the pixel electrodes 624 formed on the substrate 600. Good too.

[0170] On the substrate 600, a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor 63 are provided. The pixel electrode 624 covers the TFT 628, the wiring, and the storage capacitor 630. A contact hole 62 penetrates the insulating film 620 and a third insulating film 622 covering the insulating film. The TFT 628 is connected to the wiring 618 by a line 3. The thin film transistor shown in Embodiment Mode 1 is suitably used for the TFT 628. The storage capacitor 630 can be connected to the gate wiring 602 of the TFT 628. Similarly, a first capacitor wiring 604, a gate insulating film 606, and wirings 616 and 618 are formed. It is composed of a second capacitance wiring 617 formed in the same manner.

[0171] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a liquid crystal element. It is being done.

[0172] 14 shows the structure on the substrate 600. The pixel electrode 624 is made of the material shown in the first embodiment. The pixel electrode 624 is provided with a slit 625. The slit 625 is formed by This is to control the

[0173] The TFT 629 and the pixel electrode 626 and storage capacitor 631 connected thereto shown in FIG. The TFT 628, the pixel electrode 624, and the storage capacitor 630 can be formed in the same manner. Both TFT 628 and TFT 629 are connected to wiring 616. A pixel is composed of a pixel electrode 624 and a pixel electrode 626. 624 and pixel electrode 626 are sub-pixels.

[0174] 15 shows the structure on the opposing substrate side. An opposing electrode 640 is formed on a light-shielding film 632. The counter electrode 640 is preferably formed using the same material as the pixel electrode 624. On the counter electrode 640, a protrusion 644 for controlling the alignment of the liquid crystal is formed. A spacer 642 is formed in accordance with the position of 32.

[0175] The equivalent circuit of this pixel structure is shown in Figure 16. TFT628 and TFT629 are both gate The wiring 602 and the wiring 616 are connected. In this case, the capacitance wiring 604 and the capacitance wiring 605 are connected. By making the potentials different, the liquid crystal element 651 and the liquid crystal element 652 can be made to operate differently. That is, by individually controlling the potentials of the capacitance wiring 604 and the capacitance wiring 605, The viewing angle is widened by precisely controlling the orientation of the crystals.

[0176] When a voltage is applied to the pixel electrode 624 in which the slit 625 is provided, The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (oblique electric field). By arranging the 644 in an alternating interdigitated pattern, a diagonal electric field is effectively generated, By controlling the orientation, the direction in which the liquid crystal is oriented varies depending on the location. The multi-domain technology widens the viewing angle of the LCD panel.

[0177] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 17 to 20. do.

[0178] 17 and 18 show the pixel structure of a VA type liquid crystal panel. FIG. 17 is a plan view showing a cross-sectional structure corresponding to the cutting line YZ shown in the figure. The explanation will be given with reference to these two figures.

[0179] This pixel structure has multiple pixel electrodes in one pixel, and each pixel electrode has a TFT. Each TFT is configured to be driven by a different gate signal. That is, in a pixel designed in a multi-domain, the signal applied to each pixel electrode is independently controlled. It has a configuration that controls it independently.

[0180] The pixel electrode 624 is connected to the TFT 628 through the contact hole 623 by the wiring 618. The pixel electrode 626 is connected to the wiring 619 through the contact hole 627. The gate wiring 602 of the TFT 628 and the gate wiring 603 of the TFT 629 are connected. The line 603 is separated so that different gate signals can be applied. The wiring 616 functioning as a data line is used in common by the TFT 628 and the TFT 629. The thin film transistors shown in Embodiment Mode 1 can be used as the TFTs 628 and 629. This can be done.

[0181] The pixel electrodes 624 and 626 have different shapes and are separated by a slit 625. A pixel electrode 626 is formed so as to surround the outside of the pixel electrode 624 that spreads in a V shape. The timing of applying voltages to the pixel electrodes 624 and 626 is controlled by the TFT 62. The orientation of the liquid crystal is controlled by varying the polarity of the TFT 629. The equivalent circuit is shown in FIG. 20. The TFT 628 is connected to the gate wiring 602, and the TFT 629 is The gate wiring 602 and the gate wiring 603 are connected to different gates. By giving a signal, the operation timing of TFT628 and TFT629 can be made different. can.

[0182] On the counter substrate 601, a light-shielding film 632, a second colored film 636, and a counter electrode 640 are formed. In addition, a flattening film 637 is formed between the second colored film 636 and the counter electrode 640. This prevents the alignment of the liquid crystal from being disturbed. FIG. 19 shows the structure of the opposing substrate side. The opposing electrode 640 is This electrode is shared between the pixels, but a slit 641 is formed in it. The slits 641 and the slits 625 on the pixel electrode 624 and pixel electrode 626 sides are alternately interlocked. By arranging the liquid crystals so that they match, an oblique electric field can be generated effectively, allowing the liquid crystal orientation to be controlled. This allows the liquid crystal to be oriented in different directions depending on the location, resulting in a wide viewing angle. is spreading.

[0183] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a first liquid crystal element. In addition, the pixel electrode 626, the liquid crystal layer 650, and the counter electrode 640 are overlapped with each other. The first liquid crystal element and the second liquid crystal element are formed in one pixel. It is a multi-domain structure with multiple children.

[0184] Next, we will explain about the in-plane switching type liquid crystal display device. In the in-plane switching type, the liquid crystal molecules in the cell This method applies an electric field in the horizontal direction to drive the liquid crystal and express gradation. If this is done, the viewing angle can be widened to approximately 180 degrees. The liquid crystal display device used will be described below.

[0185] FIG. 21 shows a substrate 600 on which a TFT 628 and a pixel electrode 624 connected thereto are formed, The opposing substrate 601 is placed on top of the other substrate and liquid crystal is injected. A light-emitting film 632, a second coloring film 636, a flattening film 637, etc. are formed. It is located on the plate 600 side, and is not provided on the opposing substrate 601 side. A liquid crystal layer 650 is formed between the layers 601 .

[0186] On the substrate 600, a first pixel electrode 607 and a capacitance wiring connected to the first pixel electrode 607 are provided. 604, and the TFT 628 shown in the first embodiment are formed. The first electrode 7 can be made of the same material as that of the pixel electrode 77 shown in the first embodiment. The pixel electrode 607 is formed in a shape that is partitioned into approximately the shape of a pixel. A gate insulating film 606 is formed on the gate insulating film 607 and the capacitance wiring 604 .

[0187] The wiring 616 and wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is the data line that carries the video signal in the LCD panel and is a wiring that extends in one direction. At the same time, it is connected to the source region 610 and serves as one of the source and drain electrodes. 8 is the other electrode of the source and drain, and is a wiring connected to the second pixel electrode 624. do.

[0188] A second insulating film 620 is formed on the wiring 616 and the wiring 618. In the contact hole formed in the insulating film 620, a second electrode connected to the wiring 618 is formed. The pixel electrode 624 is formed in the same manner as the pixel electrode 77 shown in the first embodiment. It is formed using the same material.

[0189] In this way, the TFT 628 and the first pixel electrode 624 connected thereto are formed on the substrate 600. The storage capacitor is formed between the first pixel electrode 607 and the second pixel electrode 624. It is completed.

[0190] 22 is a plan view showing the configuration of the pixel electrode. The pixel electrode 624 has a slit 625. The slits 625 are provided to control the orientation of the liquid crystal. occurs between the first pixel electrode 607 and the second pixel electrode 624. A gate insulating film 606 is formed between the first pixel electrode 624 and the second pixel electrode 624. The thickness of 606 is 50 to 200 nm, which is sufficiently large compared with the thickness of the liquid crystal layer, which is 2 to 10 μm. Since the liquid is thin, an electric field is generated in a direction parallel to the substrate 600 (horizontal direction). The orientation of the liquid crystal is controlled by using an electric field parallel to the substrate. In this case, the liquid crystal molecules are horizontal in any state, so the contrast changes depending on the viewing angle. The influence of the first pixel electrode 607 and the second pixel electrode 608 is small, and the viewing angle is widened. Since both of the pixel electrodes 624 are light-transmitting electrodes, the aperture ratio can be improved.

[0191] Next, another example of a liquid crystal display device of the lateral electric field type will be described.

[0192] 23 and 24 show the pixel structure of an IPS type liquid crystal display device. The cross-sectional structure corresponding to the cutting line AB shown in the figure is shown in FIG. The following description will be given with reference to these two figures.

[0193] FIG. 23 shows a substrate 600 on which a TFT 628 and a pixel electrode 624 connected thereto are formed, The opposing substrate 601 is placed on top of the other substrate and liquid crystal is injected. A light-emitting film 632, a second coloring film 636, a flattening film 637, etc. are formed. Since it is on the plate 600 side, it is not provided on the counter substrate 601 side. A liquid crystal layer 650 is formed between the layers 601 .

[0194] On the substrate 600, a common potential line 609 and the TFT 628 shown in the first embodiment are formed. The common potential line 609 is formed at the same time as the gate wiring 602 of the thin film transistor 628. The pixel electrode 624 is formed in a shape that is partitioned into approximately the shape of a pixel.

[0195] The wiring 616 and wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is the data line that carries the video signal in the LCD panel and is a wiring that extends in one direction. At the same time, it is connected to the source region 610 and serves as one of the source and drain electrodes. Reference numeral 8 denotes a wiring that serves as the other electrode of the source and drain and is connected to the pixel electrode 624 .

[0196] A second insulating film 620 is formed on the wiring 616 and the wiring 618. In this case, a contact hole 623 formed in the insulating film 620 is connected to the wiring 618. The pixel electrode 624 is the same as the pixel electrode 77 shown in the first embodiment. As shown in FIG. 24, the pixel electrode 624 is formed of the same material. The wire 609 is formed so as to generate a horizontal electric field together with the comb-shaped electrode formed at the same time. The comb-teeth of the electrode 624 are alternately interdigitated with the comb-shaped electrode formed at the same time as the common potential line 609. It is formed like this.

[0197] When an electric field is generated between the potential applied to the pixel electrode 624 and the potential of the common potential line 609, The orientation of the liquid crystal is controlled by this electric field. The molecules are rotated horizontally. In this case, the liquid crystal molecules are horizontal in any state, so the viewing angle This has little effect on contrast and results in a wider viewing angle.

[0198] In this way, the TFT 628 and the pixel electrode 624 connected thereto are formed on the substrate 600. The storage capacitor is formed by providing a gate insulating film 606 between a common potential line 609 and a capacitor electrode 615. The capacitor electrode 615 and the pixel electrode 624 are formed by the contact hole 633. are connected via

[0199] Next, the configuration of a TN type liquid crystal display device will be described.

[0200] 25 and 26 show the pixel structure of a TN type liquid crystal display device. The cross-sectional structure corresponding to the cutting line AB shown in the figure is shown in FIG. The following description will be made with reference to these two figures.

[0201] The pixel electrode 624 is connected to the TFT 628 via the wiring 618 through the contact hole 623. The wiring 616, which functions as a data line, is connected to the TFT 628. Any of the TFTs shown in the first embodiment can be applied to 28.

[0202] The pixel electrode 624 is formed using the pixel electrode 77 shown in the first embodiment.

[0203] On the counter substrate 601, a light-shielding film 632, a second colored film 636, and a counter electrode 640 are formed. In addition, a flattening film 637 is formed between the second colored film 636 and the counter electrode 640. The liquid crystal layer 650 is disposed between the pixel electrode 624 and the counter electrode 640. It is formed.

[0204] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a liquid crystal element. It is being done.

[0205] In addition, the substrate 600 or the counter substrate 601 may have a color filter or a disclination. A shielding film (black matrix) or the like may be formed on the substrate 60 to prevent the A polarizing plate is attached to the surface opposite to the surface on which the thin film transistor of 0 is formed, and the opposing substrate A polarizing plate is attached to the surface of the plate 601 opposite to the surface on which the counter electrode 640 is formed. .

[0206] The counter electrode 640 can be made of the same material as the pixel electrode 77. 24, liquid crystal 650, and counter electrode 640 are overlapped to form a liquid crystal element.

[0207] Through the above steps, a liquid crystal display device can be manufactured. The device uses thin film transistors with low off-state current, excellent electrical characteristics, and high reliability. Therefore, the liquid crystal display device has high contrast and high visibility. The thin film transistor has a threshold voltage controlled by using a microcrystalline semiconductor film containing a small amount of silicon. Therefore, a liquid crystal display device with high visibility can be manufactured with good productivity.

[0208] (Embodiment 7) In this embodiment mode, a light-emitting device, which is one mode of a display device, will be described with reference to FIGS. 28. The light emitting device is an electroluminescent The light-emitting element that uses electroluminescence is shown. Optical materials are classified according to whether they are organic or inorganic compounds. Generally, the former are The former is called an organic EL element, and the latter is called an inorganic EL element.

[0209] In an organic EL element, when a voltage is applied to the light-emitting element, electrons and positive electrodes are released from a pair of electrodes. The holes are then injected into a layer containing a light-emitting organic compound, allowing a current to flow. The recombination of carriers (electrons and holes) causes light-emitting organic compounds to form excited states. The excited state is formed, and light is emitted when the excited state returns to the ground state. Such a light-emitting element is called a current-excited light-emitting element.

[0210] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. In addition, a channel-etched thin film transistor is used as a thin film transistor for controlling the driving of the light-emitting element. This is shown using a transistor.

[0211] 9 to 11, a thin film transistor is formed on the substrate 50 as shown in FIG. 27(A). 85 and 86 are formed, and an insulating film 87 which functions as a protective film on the thin film transistors 85 and 86 is formed. Next, a planarizing film 111 is formed on the insulating film 87, and a thin film transistor is formed on the planarizing film 111. A pixel electrode 112 is formed to connect to the source electrode or the drain electrode of the transistor 86 .

[0212] The planarization film 111 is made of an organic resin such as acrylic, polyimide, or polyamide, or a silicon dioxide. It is preferable to form it using a son.

[0213] In FIG. 27(A), the thin film transistor of the pixel is an n-type, so the pixel electrode 112 is It is desirable to use a cathode, but conversely, in the case of p-type, it is desirable to use an anode. The cathode is made of a known material having a small work function, such as calcium, aluminum, or fluorine. Calcium fluoride, magnesium silver alloy, lithium aluminum alloy, etc. can be used. do.

[0214] Next, as shown in FIG. 27(B), a partition wall is formed on the end of the planarizing film 111 and the pixel electrode 112. The partition wall 113 has an opening, and the pixel electrode 112 is formed in the opening. The partition wall 113 is made of an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the pixel electrode, and the side of the opening is It is preferable that the wall be formed as an inclined surface having a continuous curvature.

[0215] Next, the light-emitting layer 114 is formed so as to contact the pixel electrode 112 in the opening of the partition wall 113. The light-emitting layer 114 may be composed of a single layer or a plurality of layers stacked together. It doesn't matter whether it's done or not.

[0216] Then, a common electrode 115 using an anode is formed so as to cover the light-emitting layer 114. 115 is made of the conductive material having light transmission property listed as the pixel electrode 77 in the first embodiment. The common electrode 115 can be formed of a transparent conductive film. In FIG. 27(B), a titanium nitride film or a titanium film may be used as the common electrode 115. In the opening of the partition wall 113, the pixel electrode 112 and the light emitting element 114 are connected. The light emitting layer 114 and the common electrode 115 are overlapped to form a light emitting element 117. After that, in order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 117, It is preferable to form a protective film 116 on the barrier ribs 115 and the barrier ribs 113. It is possible to form a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like.

[0217] Furthermore, in practice, once the construction is completed up to Figure 27(B), it is necessary to make the structure airtight to prevent further exposure to the outside air. Highly durable and low outgassing protective film (laminate film, UV curable resin film) It is preferable to package (enclose) the product in a protective covering such as a protective film or a cover material.

[0218] Next, the configuration of the light-emitting element will be described with reference to FIG. 28. Here, the driving TFT The cross-sectional structure of a pixel will be described using an n-type pixel as an example.

[0219] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite to the substrate. There are two types of emission: top emission, which extracts light from the surface on the substrate side, bottom emission, which extracts light from the surface on the substrate side, and There are light emitting devices with a double-sided emission structure in which light is emitted from the opposite surface. The present invention can also be applied to a light emitting device having a light emitting structure.

[0220] A light emitting element with a top emission structure will be described with reference to FIG.

[0221] In FIG. 28(A), a driving TFT 7001 is an n-type, and light emitted from a light emitting element 7002 is 28A shows a cross-sectional view of a pixel in which the light emitting element 7 The cathode 7003 of the TFT 7002 is electrically connected to the driving TFT 7001. On top of that, a light-emitting layer 7004 and an anode 7005 are laminated in this order. Any known material can be used as long as it is a thin, light-reflecting conductive film. Calcium, aluminum, calcium fluoride, magnesium silver alloy, lithium aluminum The light-emitting layer 7004 may be made of a single layer or a plurality of layers. It may be configured so that the layers are stacked. On the cathode 7003, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are formed in this order. It is not necessary to provide all of these layers. The anode 7005 is a light-transmitting The conductive material is formed using a conductive material having a high conductivity, for example, indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium dioxide, indium tin oxide, indium zinc oxide, acid Alternatively, a light-transmitting conductive film such as indium tin oxide to which silicon dioxide is added may be used. stomach.

[0222] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in FIG. 28(A), the light emitted from the light emitting element 7002 corresponds to The light is emitted toward the anode 7005 as indicated by the white arrow.

[0223] Next, a light emitting element with a bottom emission structure will be described with reference to Figure 28(B). When 7011 is n-type and light emitted from the light emitting element 7012 is emitted to the cathode 7013 side FIG. 28(B) shows a cross-sectional view of the pixel. A cathode 7013 of the light-emitting element 7012 is formed on the light-transmitting conductive material 7017. A light-emitting layer 7014 and an anode 7015 are stacked in this order on the cathode 7013. When the anode 7015 is light-transmitting, a light-reflecting or light-shielding layer is formed on the anode. The cathode 7013 may be formed in the same manner as in FIG. In addition, any known material can be used as long as it is a conductive film with a small work function. The thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, The cathode 7013 can be made of Al having a thickness of 1000 nm. As in FIG. 28(A), even if it is composed of a single layer, it is composed of a plurality of layers stacked together. The anode 7015 does not need to transmit light, but it may be formed as shown in FIG. ) can be formed using a light-transmitting conductive material. For example, a light-reflecting metal or the like can be used for 016, but the material is not limited to a metal film. For example, a resin to which a black pigment is added may be used.

[0224] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 701 In the case of the pixel shown in FIG. 28(B), the light emitted from the light emitting element 7012 is , and is emitted toward the cathode 7013 as indicated by the white arrow.

[0225] Next, a light emitting device with a dual emission structure will be described with reference to FIG. 28(C). ) a transparent conductive material 7027 electrically connected to a driving TFT 7021 A cathode 7023 of the light-emitting element 7022 is formed on the cathode 7023. 24 and an anode 7025 are laminated in this order. The cathode 7023 is the same as in the case of FIG. In addition, any known material can be used as long as it is a conductive film with a small work function. For example, Al having a thickness of 20 nm is used as the cathode 7023. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 7 may be formed of a single layer or a plurality of layers stacked together. 025 is formed using a conductive material having light transmitting properties, similar to FIG. 28(A). It is possible.

[0226] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 is the light-emitting element 7 In the case of the pixel shown in FIG. 28(C), the light emitted from the light emitting element 7022 Light is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the white arrows.

[0227] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0228] In this embodiment, a thin film transistor (driving TFT) for controlling the driving of a light emitting element In the example shown, the light emitting element is electrically connected to the driving TFT. A current control TFT may be connected.

[0229] Note that the light-emitting device shown in this embodiment mode is not limited to the configuration shown in FIG. Various modifications based on the technical concept of the present invention are possible.

[0230] Through the above steps, a light-emitting device can be manufactured. The use of thin-film transistors with low current, excellent electrical properties, and high reliability makes it This light-emitting device has high reliability and high visibility. Since a thin film transistor with a threshold voltage controlled by using a microcrystalline semiconductor film containing A highly efficient light-emitting device can be manufactured with high productivity.

[0231] (Embodiment 8) A structure of a display panel, which is one mode of a display device of the present invention, will be described below.

[0232] In FIG. 29(A), only a signal line driver circuit 6013 is separately formed on a substrate 6011. 6 shows a configuration of a display panel connected to a pixel portion 6012. The driver circuit 6014 is formed using a thin film transistor using a microcrystalline semiconductor film. A transistor that can achieve higher mobility than a thin-film transistor using a crystalline semiconductor film. By forming a driving circuit, it is possible to realize a signal line driving circuit which requires a driving frequency higher than that of the scanning line driving circuit. The signal line driver circuit 6013 is made of a single crystal semiconductor. Transistors using conductors, thin film transistors using polycrystalline semiconductors, or SOI The pixel portion 6012, the signal line driver circuit 6013, and the driving circuit 6014 may be the same. The power supply potential and various signals are transmitted to the scanning line driving circuit 6014 via the FPC 6015. are supplied.

[0233] The signal line driver circuit and the scanning line driver circuit may both be formed on the same substrate as the pixel portion. stomach.

[0234] In addition, when a driver circuit is formed separately, the substrate on which the driver circuit is formed is not necessarily the same as the substrate on which the pixel portion is formed. It is not necessary to attach it to the substrate on which it is formed, but it can be attached to, for example, an FPC. In FIG. 29(B), only a signal line driver circuit 6023 is separately formed on a substrate 6021. The liquid crystal display panel connected to the formed pixel portion 6022 and the scanning line driver circuit 6024 The pixel portion 6022 and the scanning line driver circuit 6024 are formed using a microcrystalline semiconductor film. The signal line driver circuit 6023 is formed using a thin film transistor. The pixel portion 6022 and the signal line driver circuit 6023 are connected to each other. The scanning line driver circuit 6024 is connected to the power supply potential and various signals via the FPC 6025. and supplied.

[0235] In addition, only a part of a signal line driver circuit or a part of a scanning line driver circuit may be formed using a microcrystalline semiconductor film. The remaining thin film transistors are formed on the same substrate as the pixel section, and the remaining thin film transistors are formed separately. 29C shows an analog signal line driver circuit. The switch 6033a is connected to the same substrate 6031 as the pixel portion 6032 and the scanning line driver circuit 6034. The shift register 6033b of the signal line driver circuit is formed on a separate substrate. The pixel portion 6032 and the scanning line driver circuit are shown. The signal line driver circuit 6034 is formed using a thin film transistor using a microcrystalline semiconductor film. The shift register 6033b of the circuit is connected to the pixel section 6032 via the FPC 6035. The pixel portion 6032, the signal line driver circuit, and the scanning line driver circuit 6034 are The power supply potential, various signals, etc. are supplied via FPC6035.

[0236] As shown in FIG. 29, the liquid crystal display device of the present invention has a structure in which a part or all of the driving circuit is provided in the pixel section. It can be formed on the same substrate as the above by using a thin film transistor using an LPSAS film. .

[0237] The method for connecting the separately formed substrate is not particularly limited, and may be a known COG method. The method of connection may be a wire bonding method, a TAB method, or the like. The position is not limited to the position shown in FIG. 29, as long as electrical connection is possible. Alternatively, a controller, a CPU, a memory, etc. may be separately formed and connected.

[0238] The signal line driver circuit used in the present invention has only a shift register and an analog switch. In addition to shift registers and analog switches, buffers, level shifters, It may have other circuits such as a gate, a source follower, etc. It is not necessary to provide a switching switch. For example, a decoder circuit may be used instead of a shift register. You can use another circuit that can select the signal line like this, or instead of an analog switch A latch or the like may also be used.

[0239] A block diagram of a liquid crystal display device of the present invention is shown in Fig. 32. The display device shown in Fig. 32 has a display element a pixel section 701 having a plurality of pixels each having a scanning line driver circuit 702 for selecting each pixel; and a signal line driver circuit 703 for controlling input of a video signal to a selected pixel.

[0240] In FIG. 32, a signal line driving circuit 703 includes a shift register 704 and an analog switch 707. The shift register 704 has a clock signal (CLK), a start pulse The clock signal (CLK) and start pulse signal (SP) are input. ) is input, a timing signal is generated in the shift register 704, and an analog The signal is input to switch 705 .

[0241] A video signal is also applied to the analog switch 705. The analog switch 705 outputs the video signal in accordance with the input timing signal. The signal is sampled and supplied to the signal line of the subsequent stage.

[0242] Next, the configuration of the scanning line driving circuit 702 will be described. The device has a level shifter 706 and a buffer 707. In the scanning line driver circuit 702, a clock signal is input to the shift register 706. The selection signal is generated by inputting the (CLK) and start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer 707 and is applied to the corresponding scanning line. The gates of the transistors of one line of pixels are connected to the scan line. And because the transistors of the pixels in one line must all be turned on at once, The ferroelectric capacitor 707 is capable of passing a large current.

[0243] A full-color LCD display device receives video signals corresponding to R (red), G (green), and B (blue). , and supplies the samples to the corresponding signal lines. The number of terminals for connecting the analog switch 705 to the pixel section 7 This is equivalent to about one-third of the number of terminals required to connect the signal lines of the analog switch. By forming the analog switch 705 on the same substrate as the pixel section 701, the analog switch 705 can be connected to the pixel Compared to when the terminals are formed on a substrate different from the portion 701, the terminals are formed separately and are used to connect the substrate. This reduces the number of connections, reduces the probability of connection failure, and increases yield.

[0244] The scanning line driving circuit 702 in FIG. 32 includes a shift register 706 and a buffer 707. However, the scanning line driver circuit 702 may be configured with a shift register 706 .

[0245] It should be noted that the configuration shown in FIG. 32 is merely one mode of the display device of the present invention, and is not intended to be a signal line drive The configuration of the circuit and the scanning line driver circuit is not limited to this.

[0246] Next, a shift register containing thin film transistors using LPSAS films with the same polarity was developed. An embodiment of this will be described with reference to Figs. 33 and 34. Fig. 33 shows the shift The shift register shown in FIG. 33 is made up of a plurality of flip-flops 701. _i (any one of the flip-flops 701_1 to 701_n). , the first clock signal, the second clock signal, the start pulse signal, and the reset signal are input. It works as it is.

[0247] The connection relationship of the shift register in Fig. 33 will be explained. The shift register in Fig. 33 has i-stage The first flip-flop 701_i (one of the flip-flops 701_1 to 701_n) In either case, the first wiring 501 shown in FIG. 34 is connected to the seventh wiring 717_i-1, The second wiring 502 shown in FIG. 34 is connected to the seventh wiring 717_i+1, and the The third wiring 503 is connected to the seventh wiring 717_i, and the sixth wiring 50 shown in FIG. 6 is connected to the fifth wiring 715.

[0248] In addition, the fourth wiring 504 shown in FIG. 34 is connected to the second wiring 7 in the odd-numbered flip-flops. 12, and in the even-numbered flip-flops, it is connected to the third wiring 713, and The fifth wiring 505 shown in FIG.

[0249] However, the first wiring 501 shown in FIG. 34 of the first stage flip-flop 701_1 is The second wiring 711 is connected to the n-th stage flip-flop 701_n shown in FIG. 502 is connected to the sixth wiring 716 .

[0250] The first wiring 711, the second wiring 712, the third wiring 713, and the sixth wiring 716 are They may be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fourth wiring 714 and the fifth wiring 715 are respectively connected to the first power supply line and the second power supply line. You can call.

[0251] Next, the details of the flip-flop shown in FIG. 33 are shown in FIG. 34. The flip-flop includes a first thin film transistor 171, a second thin film transistor 172, a third thin film transistor 173, and a the first thin film transistor 173, the fourth thin film transistor 174, the fifth thin film transistor 1 75, the sixth thin film transistor 176, the seventh thin film transistor 177 and the eighth thin film transistor In this embodiment, the first thin film transistor 171 and the second thin film transistor 178 are The second thin film transistor 172, the third thin film transistor 173, and the fourth thin film transistor 174, the fifth thin film transistor 175, the sixth thin film transistor 176, the seventh thin film transistor The eighth thin film transistor 177 and the eighth thin film transistor 178 are n-channel transistors. When the gate-source voltage (Vgs) exceeds the threshold voltage (Vth), the transistor becomes conductive. It shall be as follows.

[0252] Next, the connection configuration of the flip-flop shown in FIG. 33 will be described below.

[0253] The first electrode (either the source electrode or the drain electrode) of the first thin film transistor 171 is The second electrode (source electrode) of the first thin film transistor 171 is connected to the fifth wiring 504. The other of the drain electrodes is connected to a third wiring 503 .

[0254] The first electrode of the second thin film transistor 172 is connected to the sixth wiring 506, and the second thin film A second electrode of the transistor 172 is connected to a third wiring 503 .

[0255] The first electrode of the third thin film transistor 173 is connected to the fifth wiring 505, and the The second electrode of the transistor 173 is connected to the gate electrode of the second thin film transistor 172. The gate electrode of the third thin film transistor 173 is connected to a fifth wiring 505 .

[0256] The first electrode of the fourth thin film transistor 174 is connected to the sixth wiring 506, and the fourth thin film The second electrode of the transistor 174 is connected to the gate electrode of the second thin film transistor 172. The gate electrode of the fourth thin film transistor 174 is connected to the gate electrode of the first thin film transistor 171. connected to the ground electrode.

[0257] The first electrode of the fifth thin film transistor 175 is connected to the fifth wiring 505, and the fifth thin film The second electrode of the transistor 175 is connected to the gate electrode of the first thin film transistor 171. The gate electrode of the fifth thin film transistor 175 is connected to the first wiring 501 .

[0258] The first electrode of the sixth thin film transistor 176 is connected to the sixth wiring 506, and the sixth thin film The second electrode of the transistor 176 is connected to the gate electrode of the first thin film transistor 171. The gate electrode of the sixth thin film transistor 176 is connected to the gate electrode of the second thin film transistor 172. connected to the ground electrode.

[0259] The first electrode of the seventh thin film transistor 177 is connected to the sixth wiring 506, and the The second electrode of the transistor 177 is connected to the gate electrode of the first thin film transistor 171. The gate electrode of the seventh thin film transistor 177 is connected to the second wiring 502. The first electrode of the thin film transistor 178 is connected to the sixth wiring 506, and the eighth thin film transistor a second electrode of the second thin film transistor 178 connected to the gate electrode of the second thin film transistor 172; The gate electrode of the eighth thin film transistor 178 is connected to the first wiring 501 .

[0260] The gate electrode of the first thin film transistor 171 and the gate electrode of the fourth thin film transistor 174 are a first electrode of the fifth thin film transistor 175; a second electrode of the sixth thin film transistor 176; The connection point of the second electrode of the seventh thin film transistor 177 and the second electrode of the seventh thin film transistor 178 is the node 143. Furthermore, the gate electrode of the second thin film transistor 172, the gate electrode of the third thin film transistor The second electrode of the fourth thin film transistor 173, the second electrode of the sixth thin film transistor 174, The connection point of the gate electrode of the eighth thin film transistor 176 and the second electrode of the eighth thin film transistor 178 is The code is 144.

[0261] The first wiring 501, the second wiring 502, the third wiring 503, and the fourth wiring 504 are , may be referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fifth wiring 505 may be called a first power supply line, and the sixth wiring 506 may be called a second power supply line. stomach.

[0262] FIG. 35 shows an example of a top view of the flip-flop shown in FIG.

[0263] The conductive film 901 includes a portion that functions as a first electrode of the first thin film transistor 171. , and is connected to the fourth wiring 504 via a wiring 951 formed at the same time as the pixel electrode.

[0264] The conductive film 902 includes a portion that functions as a second electrode of the first thin film transistor 171. The pixel electrode is connected to the third wiring 503 via a wiring 952 formed at the same time as the pixel electrode.

[0265] The conductive film 903 is a gate electrode of the first transistor and a gate electrode of the fourth thin film transistor 174. The gate electrode includes a portion that functions as the gate electrode.

[0266] The conductive film 904 is a first electrode of the second thin film transistor 172, a second electrode of the sixth thin film transistor a first electrode of the fourth thin film transistor 174; a first electrode of the eighth thin film transistor 176; The sixth wiring 506 includes a portion that functions as the first electrode of the transistor 178. .

[0267] The conductive film 905 includes a portion that functions as a second electrode of the second thin film transistor 172. The pixel electrode is connected to the third wiring 503 via a wiring 954 formed at the same time as the pixel electrode.

[0268] The conductive film 906 is a gate electrode of the second thin film transistor 172 and a gate electrode of the sixth thin film transistor 173. It includes a portion that functions as a gate electrode.

[0269] The conductive film 907 includes a portion that functions as a first electrode of the third thin film transistor 173. , and is connected to the fifth wiring 505 via wiring 955.

[0270] The conductive film 908 is a second electrode of the third thin film transistor 173 and a second electrode of the fourth thin film transistor 174. The wiring 9 includes a portion that functions as the second electrode of the pixel electrode 174 and is formed at the same time as the pixel electrode. It is connected to the conductive film 906 via 56.

[0271] The conductive film 909 includes a portion that functions as a gate electrode of the third thin film transistor 173. , and is connected to the fifth wiring 505 via wiring 955.

[0272] The conductive film 910 includes a portion that functions as a first electrode of the fifth thin film transistor 175. , and is connected to the fifth wiring 505 via a wiring 959 formed at the same time as the pixel electrode.

[0273] The conductive film 911 is a second electrode of the fifth thin film transistor 175 and a second electrode of the seventh thin film transistor 176. The wiring 9 includes a portion that functions as the second electrode of the pixel electrode 177 and is formed at the same time as the pixel electrode. It is connected to the conductive film 903 via 58.

[0274] The conductive film 912 includes a portion that functions as a gate electrode of the fifth thin film transistor 175. , and is connected to the first wiring 501 via a wiring 960 formed at the same time as the pixel electrode.

[0275] The conductive film 913 includes a portion that functions as a second electrode of the sixth thin film transistor 176. The pixel electrode is connected to the conductive film 903 via a wiring 957 formed at the same time as the pixel electrode.

[0276] The conductive film 914 includes a portion that functions as a gate electrode of the seventh thin film transistor 177. , and is connected to the second wiring 502 via a wiring 962 formed at the same time as the pixel electrode.

[0277] The conductive film 915 includes a portion that functions as a gate electrode of the eighth thin film transistor 178. The pixel electrodes are connected to the conductive film 912 via wirings 961 formed at the same time as the pixel electrodes.

[0278] The conductive film 916 includes a portion that functions as a second electrode of the eighth thin film transistor 178. The pixel electrode is connected to the conductive film 906 via a wiring 953 formed at the same time as the pixel electrode.

[0279] The circuits shown in FIGS. 32 to 34 are configured using transistors using microcrystalline semiconductors. The liquid crystal display device can operate the circuit at high speed. For example, When comparing the case where the LPSAS membrane was used with the case where the LPSAS membrane was used, Since the mobility of the transistor is high, the transistor can be used in a driver circuit (for example, a shift register of the scanning line driver circuit 702). The driving frequency of the scanning line driving circuit 702 can be increased. Since it can be operated at high frame rate, it is possible to increase the frame frequency or insert black screens. It is also possible to make things happen.

[0280] When increasing the frame frequency, the screen data is generated according to the direction of the image movement. In other words, it is desirable to perform motion compensation and interpolate the data. In addition, by increasing the frame frequency and interpolating image data, the display characteristics of moving images are improved. For example, double the frequency (for example, 120 Hz, 100 Hz) and display a smoother image. Hz) or more, and more preferably four times (for example, 480 Hz, 400 Hz) or more. This reduces blurring and afterimages in moving images. The circuit 702 can also be operated at a higher drive frequency to increase the frame frequency. This can be done.

[0281] When inserting a black screen, image data or data for black display is supplied to the pixel unit 701. As a result, it becomes similar to impulse driving, and afterimages can be reduced. In this case, the scanning line driving circuit 702 is also operated at a higher driving frequency. This allows you to insert a black screen.

[0282] Furthermore, the channel width of the transistor of the scanning line driver circuit 702 is increased, and By arranging a scanning line driving circuit, a higher frame frequency can be achieved. For example, if the frame frequency is 8 times higher (for example, 960 Hz, 800 Hz), When multiple scanning line driving circuits are arranged, the number of scanning line driving circuits is set to 1. The scanning line driving circuit for driving the odd-numbered scanning lines is arranged on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is arranged on the other side. By placing it on the opposite side of the For example, the channel width of the second thin film transistor 172 is 300 μm or more. Preferably, it is 1000 μm or more.

[0283] Note that the circuits shown in FIGS. 32 to 34 may be constructed using transistors using microcrystalline semiconductors. By forming the display device, the layout area can be reduced. For example, the frame of a liquid crystal display device can be made smaller. When comparing the case where the LPSAS membrane was used with the case where the LPSAS membrane was used, The high mobility of the transistor makes it possible to reduce the channel width of the transistor. As a result, it is possible to narrow the frame of the liquid crystal display device. The channel width of the thin film transistor 172 is 3000 μm or less, more preferably 2000 μm or less. It is desirable that the thickness is less than μm.

[0284] 34, the second thin film transistor 172 is connected to the third wiring 503 at a low level. During this period, the second thin film transistor 172 is always in an on state. Therefore, a strong stress is applied to the second thin film transistor 172. This makes the transistor characteristics more susceptible to deterioration. The voltage gradually increases, and as a result, the current decreases. A second thin-film transistor is used to ensure sufficient current can be supplied even if the first transistor deteriorates. It is desirable that the channel width of the transistor 172 is large. It is desirable that the second thin film transistor is compensated for so as not to impede the circuit operation. A transistor is arranged in parallel with the second thin film transistor 172 and is connected to the second thin film transistor 172. It is desirable to make them less susceptible to deterioration by making them turn on at the same time. stomach.

[0285] However, when comparing the case where an amorphous semiconductor film is used with the case where an LPSAS film is used, Therefore, when using an LPSAS membrane, deterioration is less likely to occur. In this case, the channel width of the transistor can be reduced. This allows the device to operate normally without the need for a compensation circuit. This allows the planar area of ​​each transistor to be reduced.

[0286] (Embodiment 9) The appearance and cross section of a liquid crystal display panel corresponding to one embodiment of the display device of the present invention are shown in FIG. FIG. 36(A) shows a structure having an LPSAS film formed on a first substrate 4001. A thin film transistor 4010 and a liquid crystal element 4013 are shielded between the second substrate 4006 and the 36(A) is a top view of the panel sealed with sealing material 4005, and FIG. 36(B) is a top view of the panel sealed with sealing material 4005. ) corresponds to a cross-sectional view taken along line A-A'.

[0287] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. A sealing material 4005 is provided so as to cover the pixel portion 4002. A second substrate 4006 is provided on the circuit 4004. The scanning line driving circuit 4004 is a circuit board including a first substrate 4001, a sealing material 4005, and a second substrate 400. 6, the liquid crystal 4008 is sealed together with the sealant 4001. In a region different from the region surrounded by the material 4005, a polycrystalline silicon layer is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film is mounted. A signal line driver circuit having a thin film transistor using a polycrystalline semiconductor film is formed on the first substrate 40. 01 is an example of bonding a signal line using a transistor made of single crystal semiconductor. A signal line driving circuit 400 may be formed on the substrate and then bonded to the substrate. 4 illustrates a thin film transistor 4009 formed of a polycrystalline semiconductor film included in the semiconductor device 3.

[0288] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 36(B), the thin film transistor included in the pixel portion 4002 The thin film transistor 4010 is an LPSAS film. This corresponds to the thin film transistor used.

[0289] The pixel electrode 4030 of the liquid crystal element 4013 is a thin film. The counter electrode of the liquid crystal element 4013 is electrically connected to the membrane transistor 4010. 4031 is formed on the second substrate 4006. The pixel electrode 4030 and the counter electrode 403 The portion where the liquid crystal 4008 overlaps with the liquid crystal element 4013 corresponds to the liquid crystal element 4013 .

[0290] The first substrate 4001 and the second substrate 4006 are made of glass, metal (typically Stainless steel, ceramics, and plastics can be used. is a FRP (Fiberglass-Reinforced Plastics) plate, P VF (polyvinyl fluoride) film, polyester film, or acrylic resin Also, aluminum foil can be used as a PVF film or polyester film. A sheet sandwiched between two polyester films can also be used.

[0291] Also, 4035 is a spherical spacer, which is located between the pixel electrode 4030 and the counter electrode 4031. The insulating film is selectively etched to control the distance (cell gap). Alternatively, a spacer obtained by bonding may be used.

[0292] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section Various signals and potentials given to 4002 are transmitted through wirings 4014 and 4015. Powered by FPC4018.

[0293] In this embodiment, the connection terminal 4016 is connected to the pixel electrode 4030 of the liquid crystal element 4013. The lead wirings 4014 and 4015 are made of the same conductive film as the thin film transistors. The source electrode or drain electrode of the transistor 4010 is formed of the same conductive film.

[0294] The connection terminal 4016 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0295] Although not shown, the liquid crystal display device shown in this embodiment has an alignment film and a polarizing plate. Furthermore, a color filter and a shielding film may be provided.

[0296] In addition, in FIG. 36, a signal line driver circuit 4003 is separately formed and mounted on the first substrate 4001. However, this embodiment is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed and mounted. It may be formed separately and mounted.

[0297] This embodiment can be implemented in combination with the configurations described in other embodiments. be.

[0298] (Embodiment 10) Next, the appearance and cross section of a light-emitting display panel, which is one embodiment of a display device of the present invention, will be described. This will be explained using Figure 37(A). Figure 37 shows a structure in which an LPSAS film formed on a first substrate is used. The thin film transistor and the light emitting element are sealed between the second substrate and the substrate by a sealing material. 37(B) is a top view of the panel, and corresponds to a cross-sectional view taken along line A-A' in FIG. 37(A). do.

[0299] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. A sealing material 4005 is provided so as to cover the pixel portion 4002. A second substrate 4006 is provided on the circuit 4004. The scanning line driving circuit 4004 is a circuit board including a first substrate 4001, a sealing material 4005, and a second substrate 400. 6, together with the filler 4007. The area surrounded by the insulating material 4005 is different from the area surrounded by the insulating material 4005. A signal line driver circuit 4003 formed of a crystalline semiconductor film is mounted on the substrate. The signal line driver circuit having a thin film transistor using a polycrystalline semiconductor film is mounted on the first substrate 4. The example of bonding to 001 will be explained. In FIG. 37, a signal line driving circuit 40 is formed on the substrate. 40. A thin film transistor 4009 formed of a polycrystalline semiconductor film included in 03 is shown as an example.

[0300] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 37B, the thin film transistor included in the pixel portion 4002 is In this embodiment, the thin film transistor 4010 is shown as an example. It is assumed that 010 is a driving TFT, while thin film transistor 4010 is a current control TFT. The thin film transistor 4010 may be an LPS TFT or an erasing TFT. This corresponds to a thin-film transistor using an AS film.

[0301] The pixel electrode of the light emitting element 4011 is a thin film transistor. The source electrode or drain electrode of the transistor 4010 is electrically connected to the wiring 4017. In this embodiment, the light-transmitting conductive material 4011 is The light-emitting element 4011 has the same structure as that shown in this embodiment. The direction of light extracted from the light emitting element 4011 and the thin film transistor 4 The structure of the light emitting element 4011 can be changed as appropriate in accordance with the polarity of O10.

[0302] In addition, a signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel driver circuit 4006 are separately formed. Various signals and potentials are applied to the circuit 4002 via wirings 4014 and 4015. and is supplied by FPC4018.

[0303] In this embodiment mode, the connection terminal 4016 is made of the same conductive film as the pixel electrode of the wiring 4017. The lead wirings 4014 and 4015 are formed of the thin film transistor 40 The source electrode or drain electrode 10 is formed from the same conductive film.

[0304] The connection terminal 4016 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0305] The substrate located in the direction of light extraction from the light emitting element 4011 must be transparent. In this case, a glass plate, a plastic plate, a polyester film or an acrylic film A light-transmitting material such as aluminum is used.

[0306] In addition to inert gases such as nitrogen and argon, filler 4007 can also be used with ultraviolet curing gas. Resin or thermosetting resin can be used, such as PVC (polyvinyl chloride), acrylic , polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV In this embodiment, the filler can be ethylene vinyl acetate (A). Nitrogen was used.

[0307] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be provided as needed. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. It is possible to apply an anti-glare treatment that can diffuse reflected light and reduce glare.

[0308] In FIG. 37, the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001. However, this embodiment is not limited to this configuration. It may be formed separately and mounted, or only a part of the signal line driver circuit or a part of the scanning line driver circuit may be mounted. may be formed separately and mounted.

[0309] This embodiment can be implemented in combination with the configurations described in other embodiments. be.

[0310] (Embodiment 11) The display device obtained by the present invention can be used to manufacture an active matrix display module. That is, the present invention can be applied to all electronic devices that incorporate such a display unit. It can be implemented.

[0311] Such electronic devices include video cameras, digital cameras, and head-mounted displays. Ray (goggle-type display), car navigation, projector, car stereo, Personal computers, personal digital assistants (mobile computers, mobile phones or electronic books) An example of this is shown in Figure 30.

[0312] FIG. 30(A) is a television device. The display module is as shown in FIG. The TV set can be completed by installing it in a housing. The display panel is also called a display module. 03 is formed, and other accessories include a speaker unit 2009 and an operation switch. In this way, the television device can be completed.

[0313] As shown in FIG. 30(A), a display panel 2002 using a display element is mounted on a housing 2001. The receiver 2005 can receive general television broadcasts, and the modem 2004 By connecting to a wired or wireless communication network via It can also be used for two-way (between sender and receiver, or between receivers) information communication. The television set can be operated using a switch built into the housing or a separate remote control. This can be done by the remote control device 2006, and the information to be output is also displayed on this remote control device. A display unit 2007 may also be provided.

[0314] In addition to the main screen 2003, the television device also has a sub-screen 2008 for second display. It may be formed of a panel and may have a configuration for displaying the channel, volume, etc. The main screen 2003 is formed of a liquid crystal display panel with an excellent viewing angle, and the sub-screen is formed of a low-power It may be formed of a light-emitting display panel that can display with electricity. To achieve this, the main screen 2003 is formed of a light-emitting display panel, and the sub-screen is formed of a light-emitting display panel. The sub-screen may be configured to be able to blink.

[0315] FIG. 31 is a block diagram showing the main components of a television device. A pixel portion 921 is formed on the display panel 920. A signal line driver circuit 922 and a scanning line driver circuit 923 are connected to the display panel 920. The display panel 900 may be mounted using the COG method.

[0316] As for the configuration of other external circuits, on the video signal input side, a signal received by a tuner 924 A video signal amplifier circuit 925 amplifies the video signal, and the signal output from the video signal amplifier circuit 925 is converted into red. a video signal processing circuit 926 that converts the video signals into color signals corresponding to the colors 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 2 It has a control circuit 927 for converting the input specifications of the driver IC. The control circuit 927 outputs signals to the scanning line side and the signal line side. In this case, a signal dividing circuit 928 is provided on the signal line side to divide the input digital signal into m parts. It may also be configured to supply the power.

[0317] Of the signals received by the tuner 924, the audio signal is sent to an audio signal amplifier circuit 929. The output is supplied to a speaker 933 via an audio signal processing circuit 930. 1 receives control information for the receiving station (receiving frequency) and volume from an input unit 932, and A signal is sent to the audio signal processing circuit 930.

[0318] Of course, the present invention is not limited to television devices, and may be applied to monitors of personal computers. In addition, it is used for large-area displays such as information display boards at train stations and airports, and advertising display boards on the street. It can also be used for a variety of purposes as a display medium.

[0319] FIG. 30(B) shows an example of a mobile phone 2301. This mobile phone 2301 has a display The display unit 2302 includes an operation unit 2303. By applying the display device described in the above embodiment, mass productivity can be improved.

[0320] The portable computer shown in FIG. 30(C) includes a main body 2401, a display unit 2402, etc. By applying the display device described in the above embodiment to the display portion 2402, , and mass productivity can be improved.

[0321] FIG. 30(D) shows a table lamp, which includes a lighting unit 2501, a shade 2502, and an adjustable arm 2503. 2501, a support 2504, a base 2505, and a power supply 2506. The lighting fixtures are either ceiling-mounted or wall-mounted. By applying the display device described in the above embodiment, This can improve productivity and provide an inexpensive desk lighting fixture. [Explanation of symbols]

[0322] 23a: Microcrystalline semiconductor film 23b: Microcrystalline semiconductor film containing boron 33a:LPSAS membrane 33b: Microcrystalline semiconductor film containing boron 43: Microcrystalline semiconductor film 50: Circuit board 51: Gate electrode 52a, 52b, 52c: gate insulating film 53:LPSAS membrane 54: Buffer layer 55: Semiconductor film doped with impurities that give one conductivity type 56: Resist mask 59: Multi-tone mask 61:LPSAS membrane 62: Buffer layer 63: Semiconductor film doped with impurities that give one conductivity type 65a, 65b, 65c: Conductive film 66: Resist mask 71a, 71b, 71c: source electrode and drain electrode 72: Source and drain regions 73: Buffer layer 74: Thin-film transistor 76: Insulating film 77: Pixel electrode 80: Resist 81: Resist mask 83: Thin-film transistor 85a~85c: Conductive film 87: Buffer layer 86: Resist mask 88: Source and drain regions 90:LPSAS membrane 92a, 92b, 92c: source and drain electrodes 111: Flattening film

Claims

1. The semiconductor device includes first to eighth transistors and first to fifth wirings, one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the first wiring; one of the source electrode and the drain electrode of the third transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the gate electrode of the third transistor; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the fourth transistor is always electrically connected to a gate electrode of the first transistor; one of a source electrode and a drain electrode of the fifth transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the fourth wiring; one of a source electrode and a drain electrode of the sixth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the sixth transistor is always electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the seventh transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the seventh transistor is always electrically connected to the fifth wiring; one of a source electrode and a drain electrode of the eighth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the eighth transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the eighth transistor is always electrically connected to a gate electrode of the fifth transistor; a first conductive film functioning as one of a source electrode and a drain electrode of the third transistor is always electrically connected to a third conductive film functioning as the other of a source electrode and a drain electrode of the eighth transistor via a second conductive film functioning as a gate electrode of the second transistor and a gate electrode of the sixth transistor; the fourth conductive film functioning as one of the source electrode and the drain electrode of the fifth transistor functions as the other of the source electrode and the drain electrode of the seventh transistor; Semiconductor device.

2. The semiconductor device includes first to eighth transistors and first to fifth wirings, one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the first wiring; one of the source electrode and the drain electrode of the third transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the gate electrode of the third transistor; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the fourth transistor is always electrically connected to a gate electrode of the first transistor; one of a source electrode and a drain electrode of the fifth transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the fourth wiring; one of a source electrode and a drain electrode of the sixth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the sixth transistor is always electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the seventh transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the seventh transistor is always electrically connected to the fifth wiring; one of a source electrode and a drain electrode of the eighth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the eighth transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the eighth transistor is always electrically connected to a gate electrode of the fifth transistor; a first conductive film functioning as one of a source electrode and a drain electrode of the third transistor is always electrically connected to a third conductive film functioning as the other of a source electrode and a drain electrode of the eighth transistor via a second conductive film functioning as a gate electrode of the second transistor and a gate electrode of the sixth transistor; a fourth conductive film serving as one of a source electrode and a drain electrode of the fifth transistor serves as the other of a source electrode and a drain electrode of the seventh transistor; the fifth conductive film having a function as the third wiring has a function as one of a source electrode or a drain electrode of the second transistor, a function as one of a source electrode or a drain electrode of the fourth transistor, a function as one of a source electrode or a drain electrode of the sixth transistor, a function as one of a source electrode or a drain electrode of the seventh transistor, and a function as one of a source electrode or a drain electrode of the eighth transistor; Semiconductor device.

3. In claim 1 or claim 2, the first to eighth transistors have the same polarity; Semiconductor device.

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