Semiconductor device

Abstract

To suppress malfunction of a logic circuit by reducing a leakage current of a transistor.SOLUTION: A transistor including an oxide semiconductor layer functioning as a channel formation layer and having an off-state current per micrometer of channel width of less than or equal to 1*10-13A, a first signal, a second signal, and a third signal which is a clock signal are input as input signals, and a fourth signal and a fifth signal whose voltage states are set in accordance with the input first signal to third signal are output as output signals.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a logic circuit. Regarding the device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of semiconductor devices, including electro-optical devices such as display devices, semiconductor circuits, and electronic devices. be. [Background technology]

[0003] Thin film transistors formed on flat plates such as glass substrates, as typified by liquid crystal display devices. (hereinafter referred to as TFT: Thin Film Transistor) is mainly made of amorphous It is made using semiconductor materials such as amorphous silicon or polycrystalline silicon. Silicon TFTs have low field effect mobility but are compatible with larger glass substrates. On the other hand, TFTs using polycrystalline silicon have high field effect mobility, but Crystallization processes such as laser annealing are required, and it is not necessarily suitable for large-area glass substrates. It has the characteristic of not

[0004] In response to this, TFTs that use oxide semiconductors as the semiconductor material are attracting attention. TFTs are fabricated using zinc oxide or In-Ga-Zn-O oxide semiconductors as semiconductor materials. The technology for manufacturing such a semiconductor device and using it as a switching element in an image display device is disclosed in Patent Documents 1 and 2. It has been disclosed.

[0005] A TFT in which a channel formation region (also called a channel region) is formed in an oxide semiconductor is It has a higher field effect mobility than TFTs using oxide semiconductors. Conductive films can be formed by sputtering or other methods, and polycrystalline silicon is used. It is easier to fabricate than TFT.

[0006] TFTs made using such oxide semiconductors are widely used in liquid crystal displays, electroluminescence displays, and other applications. Luminescence display (hereinafter also referred to as EL display) or electronic paper It is expected that this technology will be applied to the switching elements that make up the pixel section and drive circuit of display devices. For example, a pixel portion and a pixel region of a display device can be formed by using a TFT manufactured using the above-mentioned oxide semiconductor. Patent Document 3 discloses a technique for configuring the driving circuit. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165527 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-165529 [Patent Document 3] Japanese Patent Application Laid-Open No. 2006-165528 Summary of the Invention [Problem to be solved by the invention]

[0008] The driving circuit is composed of a shift register and a buffer. Alternatively, the buffer is configured using a logic circuit. The logic circuit is configured using a transistor. However, conventional transistors can generate leakage current even when they are off. When leakage current occurs, for example, the voltage of the output signal in a logic circuit may be held constant. Even if you want to maintain the range, the value of the output signal may change, possibly causing a malfunction.

[0009] An object of one embodiment of the present invention is to reduce leakage current of a transistor. The object of the present invention is to suppress malfunction of logic circuits by reducing the leakage current of transistors. do. [Means for solving the problem]

[0010] One embodiment of the present invention is an oxide semiconductor having a low off-state current and functioning as a channel formation layer. The transistor having the layer is used as a transistor constituting a logic circuit. This helps to prevent malfunctions in the logic circuit.

[0011] The oxide semiconductor layer used as a channel formation layer of a transistor is an oxide semiconductor. True or substantial, purified by removing donor impurities. It is a completely intrinsic semiconductor with a larger energy gap than silicon semiconductors. A transistor using a conductor layer has a small leakage current in an off state (off current). In addition, a transistor using an oxide semiconductor layer as a channel formation layer has a tendency to have a low threshold voltage. The impact is small.

[0012] One embodiment of the present invention includes an oxide semiconductor layer having a function as a channel formation layer, The off-state current per 1 μm of width is 1×10 -13 A or less (preferably 1×10 -17 Below A ) and a first signal, a second signal, and a clock as input signals. A third signal is input, and the voltage state is changed according to the first to third signals input. The logic circuit outputs the fourth signal and the fifth signal, the states of which are set, as output signals.

[0013] In one embodiment of the present invention, a logic circuit generates an electric signal in response to first to third signals input thereto. a first unit logic circuit that outputs a fourth signal in which a pressure state is set; a second unit logic circuit that outputs a fifth signal whose voltage state is set in response to the third to fifth signals; It is also possible to have a configuration having the above.

[0014] One aspect of the present invention is a method for generating a clock signal using a first signal, a second signal, and a clock signal as input signals. A third signal is input, and a voltage state is set according to the input first to third signals. a first unit logic circuit that outputs a fourth signal obtained by the first unit logic circuit and a second unit logic circuit that receives as input signals the first signal, the second signal, and the A signal and a third signal, which is a clock signal, are input, and the input first to third signals are a second unit logic circuit that outputs a fifth signal whose voltage state is set in response to the signal; Each of the first unit logic circuit and the second unit logic circuit has a gate, a source, and a drain. a third signal is input to the gate, and a first signal and a second signal are input to one of the source and the drain. a first transistor to which either a first signal or a second signal is input, and a gate, a source, and a The first transistor has a drain, and the gate is electrically connected to the other of the source and drain of the first transistor. Either a high power supply voltage or a low power supply voltage is applied to one of the source and drain. The voltage of the other of the source and drain is the voltage of the fourth signal or the fifth signal. a first electrode and a second electrode, the first electrode being a gate electrode of the second transistor; the second electrode is electrically connected to the other of the source and drain of the second transistor. a first capacitance element electrically connected to the gate, a source, and a drain; a third signal is input to the source and a drain, and the other of the first signal and the second signal is input to one of the source and the drain. a third transistor to which the input signal is input, the third transistor having a gate, a source, and a drain, the gate of which is connected to the first The source and drain of the third transistor are electrically connected to the other of the source and drain of the third transistor. one of which is electrically connected to either the source or the drain of the second transistor, A fourth transistor to which the other of the high power supply voltage and the low power supply voltage is input. a first electrode and a second electrode, the first electrode being a source of a third transistor; and the drain, and the second electrode is electrically connected to the other of the high power supply voltage and the low power supply voltage. and a second capacitor to which the first to fourth transistors are input. Each of the gate electrodes includes an oxide semiconductor layer that functions as a channel forming layer, and has a channel width of 1 Off-state current per μm is 1×10 -13 A or less (preferably 1×10 -17 A or below) It is a logic circuit.

[0015] One aspect of the present invention is a driving circuit including a shift register including the logic circuit described above, and a driving and a pixel portion including pixels whose display state is controlled by a circuit. [Effects of the Invention]

[0016] According to one embodiment of the present invention, leakage current in a transistor can be reduced. Maintains the output signal voltage within the desired range by reducing the transistor leakage current Therefore, malfunctions can be suppressed. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 2 illustrates an example of the configuration of a logic circuit according to Embodiment 1. [Figure 2] FIG. 2 is a circuit diagram showing an example of a configuration of a shift register according to the first embodiment. [Figure 3] 3 is a timing chart for explaining an example of the operation of the shift register shown in FIG. 2; [Figure 4] FIG. 1 is a block diagram illustrating a semiconductor device according to Embodiment 1. [Figure 5] 1A and 1B are diagrams illustrating a configuration of a signal line driver circuit according to Embodiment 1 and a timing chart of the signal line driver circuit. [Figure 6] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 7] 1A and 1B are diagrams illustrating a transistor. [Figure 8] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 9] 1A and 1B are diagrams illustrating a transistor. [Figure 10] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 11] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 12] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 13] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 14] 1A and 1B are diagrams illustrating a transistor. [Figure 15] 1A to 1C illustrate a semiconductor device. [Figure 16] 1A and 1B are diagrams illustrating pixel equivalent circuits of a semiconductor device. [Figure 17] 1A to 1C illustrate a semiconductor device. [Figure 18] 1A to 1C illustrate a semiconductor device. [Figure 19] 1A to 1C illustrate a semiconductor device. [Figure 20] 1A and 1B are diagrams illustrating electronic devices. [Figure 21] 1A and 1B are diagrams illustrating electronic devices. [Figure 22] 1A and 1B are diagrams illustrating electronic devices. [Figure 23] 1A and 1B are diagrams illustrating electronic devices. [Figure 24] FIG. 1 is a diagram showing a band structure between the source and drain of a MOS transistor using an oxide semiconductor. [Figure 25] 25 is a diagram showing a state in which a positive voltage is applied to the drain side in FIG. 24. [Figure 26] 1A and 1B are energy band diagrams of the MOS structure of a MOS transistor using an oxide semiconductor, showing (A) the case where the gate voltage is positive, and (B) the case where the gate voltage is negative. [Figure 27] A diagram showing the band structure between the source and drain of a silicon MOS transistor. [Figure 28] FIG. 10 is a graph showing initial characteristics of a thin film transistor. [Figure 29] FIG. 1 is a top view showing a structure of a thin film transistor. [Figure 30] FIG. 10 is a graph showing the Vg-Id characteristics of a thin film transistor. [Figure 31] 1A to 1C illustrate a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0018] An example of an embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to the above description, and the embodiments and details thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications can be made to the above. The present invention should not be construed as being limited to the description of the embodiments.

[0019] (Embodiment 1) In this embodiment, a logic circuit according to one embodiment of the present invention will be described. In this document, unless otherwise specified, a logic circuit is a circuit that is is a combinational logic circuit, which is a logic circuit that is determined only by the state of the input signal at that time. , the state of the output signal at a certain time depends not only on the state of the input signal at that time but also on the A sequential logic circuit is a logic circuit whose state is determined by the state of the logic circuit before it is executed. The term "path" shall include the following:

[0020] An example of the configuration of a logic circuit according to this embodiment will be described with reference to FIG. 1 is a diagram illustrating an example of a configuration of a logic circuit in the embodiment.

[0021] The logic circuit 100 shown in FIG. 1A receives signals IN1, IN2, and The logic circuit 100 shown in FIG. 1A receives a signal CK1 as an input. It outputs the signal OUT1a and the signal OUT1b.

[0022] Generally, voltage refers to the difference in electric potential (also called potential difference) between two points. However, voltage and potential values ​​are often expressed in volts (V) in circuit diagrams, etc. Therefore, in this specification, unless otherwise specified, The potential difference between the potential at a point and the reference potential (also called the reference potential) is called the voltage at that point. It may be used.

[0023] In this specification, the signals may be, for example, voltage, current, resistance, or frequency. For example, a voltage signal (voltage signal) can be used. The voltage signal (also referred to as a voltage signal) is a signal having at least a first voltage state and a second voltage state. For example, a high level voltage state is used as the first voltage state and a low level voltage state is used as the second voltage state. A binary digital signal having a low-level voltage state can be used as the voltage state. In a binary digital signal, the high level voltage is expressed as voltage VH Also known as Law The voltage of the level is V L Also, the voltage in the first voltage state and the voltage in the second voltage state However, in electronic circuits, for example, noise may occur. Because of the influence of the voltages, the voltages in the first voltage state and the second voltage state are not constant values. , each of which may be a value within a certain range.

[0024] In this specification, a high power supply voltage refers to a voltage on the relatively high voltage side (also called VDD). The low power supply voltage is a voltage on the relatively low side (also called VSS). It is preferable that the voltage and the low power supply voltage are constants. Therefore, in this specification, the voltages are defined as being within a certain range. The values ​​can be considered as high and low power supply voltages. The high and low power supply voltages can be set appropriately. Since the locations given by the characteristics are interchangeable, either a high power supply voltage or a low power supply voltage can be used. One of the high power supply voltage and the low power supply voltage is taken as one, and the other is taken as the other of the high power supply voltage and the low power supply voltage.

[0025] In addition, in this specification, terms using ordinal numbers such as first and second may be confused with each other. The numbers are added to avoid confusion and are not intended to limit the number.

[0026] The signal IN2 may be, for example, an inverted signal of the signal IN1.

[0027] The signal CK1 functions as a clock signal for the logic circuit 100.

[0028] The signal OUT1a is a signal whose voltage state is set by the input signals IN1 and IN2. The number is.

[0029] The signal OUT1b is a signal whose voltage state is set by the input signals IN1 and IN2. The number is.

[0030] Furthermore, an example of a circuit configuration of the logic circuit shown in FIG. 1A is shown in FIG. The logic circuit shown in FIG. 1B includes a unit logic circuit 131 and a unit logic circuit 132.

[0031] The unit logic circuit 131 receives the signals IN1, IN2, and CK1. The unit logic circuit 131 outputs the following signals in response to the input signals IN1, IN2, and CK1: It has the function of outputting a signal OUT1a in which the voltage state is set.

[0032] The unit logic circuit 132 receives the signals IN1, IN2, and CK1. The signal IN1, the signal IN2, and the signal OUT1 whose voltage state is set according to the signal CK1. It has the function of outputting b.

[0033] Furthermore, the unit logic circuit 131 includes a transistor 101, a transistor 102, and a capacitance element a transistor 103, a transistor 104, a transistor 105, and a capacitance element 106. The unit logic circuit 132 includes a transistor 107, a transistor 108, and a capacitance element 10 9, a transistor 110, a transistor 111, and a capacitor 112.

[0034] In this specification, a field effect transistor is used as the transistor. It is possible.

[0035] In this specification, a field effect transistor is defined as a transistor having at least a gate, a source, and a drain. As the field effect transistor, for example, a thin film transistor (also known as a TFT) As a field effect transistor, for example, a top gate A field-effect transistor can be used. The transistors can be of N-type or P-type conductivity. As an example of a transistor, we will explain the case where all field effect transistors are of the same conductivity type. By making all transistors the same conductivity type, it is possible to use multiple transistors of different conductivity types. The number of manufacturing steps can be reduced compared to the conventional method.

[0036] The term "gate" refers to a gate electrode and a part or the whole of a gate wiring. This means that the gate electrode of at least one transistor is electrically connected to another electrode or another wiring. For example, the scanning lines in a display device are also included in the gate wiring. can be.

[0037] The source refers to the source region, the source electrode, and part or all of the source wiring. The source region is a region of the semiconductor layer that has a lower resistance than the channel formation layer. The source electrode is the conductive layer connected to the source region. The source electrode of at least one transistor is electrically connected to another electrode or another wiring. For example, a signal line in a display device is electrically connected to a source electrode. In this case, the source wiring also includes the signal line.

[0038] The drain refers to the drain region, drain electrode, and part or all of the drain wiring. The drain region is a region in the semiconductor layer that has a lower resistance than the channel formation region. The drain electrode is the conductive layer connected to the drain region. Drain wiring is a wiring that connects the drain electrode of at least one transistor to another electrode or another wiring. For example, a signal line in a display device is a When electrically connected to the IN electrode, the drain wiring also includes the signal line.

[0039] In addition, in this document (specification, claims, drawings, etc.), The and drain are interchangeable depending on the transistor structure and operating conditions. Therefore, it is difficult to determine whether the source or drain is the In the patent application, claims, drawings, etc., the source and drain may be arbitrarily selected. The selected one is referred to as one of the source and drain, and the other is referred to as the other of the source and drain. Write.

[0040] In addition, in this document (specification, claims, drawings, etc.), the capacitive element is defined as a first a first electrode, a second electrode, and a dielectric to which a voltage is applied between the first electrode and the second electrode. This is the configuration.

[0041] The transistor 101 receives a signal CK1 at its gate and a signal CK2 at one of its source and drain. The number IN1 is input.

[0042] The transistor 102 has a gate electrically connected to the other of the source and drain of the transistor 101. and one of the source and drain is supplied with one of a high power supply voltage and a low power supply voltage. In FIG. 1, for example, a high power supply voltage is applied to one of the source and drain of the transistor 102. The gate of transistor 102 and the source of transistor 101 are given as follows. The connection point between the source and the drain and the other is called a node 121. The other voltage of the source and drain of the transistor 102 is output as a signal OUT1a. do.

[0043] The capacitor 103 has a first electrode electrically connected to the gate of the transistor 102 and a second electrode electrically connected to the gate of the transistor 102. The electrode of the transistor 102 is electrically connected to the other of the source and drain of the transistor 102. When there is a parasitic capacitance between the gate of the transistor 102 and the other of the source and drain The parasitic capacitance can also be used as the capacitance element 103 .

[0044] The transistor 104 receives a signal CK1 at its gate and a signal CK2 at one of its source and drain. The number IN2 is input.

[0045] The transistor 105 has a gate electrically connected to the other of the source and drain of the transistor 104. and one of the source and drain of the transistor 102 is connected to the source and drain of the transistor 102. The other of the source and drain is electrically connected to the other of the high power supply voltage and the low power supply voltage. In the logic circuit shown in FIG. 1, for example, the source and drain of the transistor 105 are The other drain is supplied with a low power supply voltage. The connection point between the other of the source and drain of the transistor 104 is called a node 122. .

[0046] The capacitor 106 has a first electrode electrically connected to the other of the source and drain of the transistor 104. The other of the high power supply voltage and the low power supply voltage is applied to the second electrode. In the logic circuit, for example, a low power supply voltage is applied to the second electrode of the capacitor 106. do.

[0047] The transistor 107 receives a signal CK1 at its gate and a signal CK2 at one of its source and drain. The number IN2 is input.

[0048] The transistor 108 has a gate electrically connected to the other of the source and drain of the transistor 107. and one of the source and drain is supplied with one of a high power supply voltage and a low power supply voltage. Note that in the logic circuit shown in FIG. 1, the other of the source and drain of the transistor 108 is The voltage is output as a signal OUT1b. The connection point between the source and the drain of the capacitor 107 and the other is called a node 123 .

[0049] The capacitor 109 has a first electrode electrically connected to the gate of the transistor 108 and a second electrode electrically connected to the gate of the transistor 108. The electrode of the transistor 108 is electrically connected to the other of the source and drain of the transistor 108. When there is a parasitic capacitance between the gate of the transistor 108 and the other of the source and drain, In this case, the parasitic capacitance can be used as the capacitance element 109.

[0050] The transistor 110 receives a signal CK1 at its gate and a signal CK2 at one of its source and drain. The number IN1 is input.

[0051] The transistor 111 has a gate electrically connected to the other of the source and drain of the transistor 110. and one of the source and drain of the transistor 108 is connected to the source and drain of the transistor 108. The other of the source and drain is electrically connected to the other of the high power supply voltage and the low power supply voltage. In the logic circuit shown in FIG. 1, as an example, the source and The other drain is supplied with a low power supply voltage. The connection point between the other of the source and drain of the transistor 110 is called a node 124. cormorant.

[0052] The capacitor 112 has a first electrode electrically connected to the other of the source and drain of the transistor 110. The other of the high power supply voltage and the low power supply voltage is applied to the second electrode. In the logic circuit shown in FIG. 1, it is assumed that a low power supply voltage is applied to the second electrode of the capacitor 112. explain.

[0053] Note that transistor 101, transistor 102, transistor 104, and transistor 1 05, transistor 107, transistor 108, transistor 110, and transistor The transistor 111 is a transistor having an oxide semiconductor layer that functions as a channel formation layer. The hydrogen concentration in the channel formation layer is 5×10 19 / c m 3 Less than or equal to 5 x 10 18 / cm 3 Less than 5 × 10, more preferably 17 / cm 3 The hydrogen concentration is measured by, for example, secondary ion mass spectrometry (SIMS). The measurements were taken using Trans Ion Mass Spectrometry. The carrier concentration of the transistor is 1×10 14 / cm 3 Less than 1 × 10 12 / cm 3 The following applies.

[0054] As shown in FIG. 1, an example of the logic circuit of this embodiment receives a first input signal. a signal (e.g., signal IN1), a second signal (e.g., signal IN2), and a third signal (e.g., A signal CK1 is input, and the voltage state is set according to the first to third signals input. The fourth signal (for example, signal OUT1a) and the fifth signal (for example, signal OUT1b) are The signal is output as an output signal.

[0055] Furthermore, an example of the logic circuit of this embodiment is constructed using transistors of the same conductivity type. This reduces the number of manufacturing steps compared to when transistors of multiple conductivity types are used. The transistors of the same conductivity type can be, for example, N-type transistors. Alternatively, a P-type transistor can be used.

[0056] Furthermore, an example of the configuration of a shift register using the logic circuit shown in FIG. 1 is shown in FIG. FIG. 2 is a circuit diagram showing an example of the configuration of a shift register. Note that the number of logic circuits is not necessarily There are no limitations on the number of stages, and it is sufficient if the configuration has at least two or more stages of logic circuits. In Figure 2, as an example, all the transistors that make up the shift register are N-type transistors. However, the present invention is not limited to this and may be configured using a P-type transistor. It is also possible.

[0057] The shift register shown in FIG. 2 includes a logic circuit 151, a logic circuit 152, and a logic circuit 153. In each logic circuit, the same parts as those in the logic circuit shown in Figure 1 are The description of the logic circuits shown in FIG. 1 will be used as appropriate. are all sequential logic circuits.

[0058] The logic circuit 151 receives an input signal from the transistor 101 as an input signal, similar to the logic circuit shown in FIG. the gate of transistor 104, the gate of transistor 107, and the gate of transistor A signal CK1 is input to the gate of the transistor 110, and the signal CK2 is input to the source of the transistor 101. and drain of the transistor 110, and a signal IN 1 is input to one of the source and drain of the transistor 104 as an input signal, A signal IN2 is input to one of the source and drain of the transistor 107. The circuit 151 outputs signals OUT1a and OUT1b whose voltage states are set according to the states of the input signals. and output signal OUT1b as an output signal.

[0059] The logic circuit 152 receives the signals OUT1a, OUT1b, and CK2 as input signals. The signal OUT2a and the signal OUT 2b as an output signal. The circuit configuration is the same as 151.

[0060] The signal CK2 is input to the logic circuit 152 instead of the signal CK1 in the logic circuit 151. The signal CK2 is a signal that goes high at a different timing from the signal CK1. In the shift register of this embodiment, a clock signal that satisfies the following formula can be used. The logic circuit to which the signal CK1 is input and the logic circuit to which the signal CK2 is input are electrically connected alternately. For example, an odd number of logic circuits in a shift register can be connected in this manner. One of the signals CK1 and CK2 is input to the logic circuits in the even stages. It is also possible to configure the other signal CK2 to be input.

[0061] The logic circuit 153 receives the signals OUT2a, OUT2b, and CK1. The voltage state of the signal OUT3a and the signal OUT3b is set in accordance with the received signal. The circuit configuration of the logic circuit 153 is the same as that of the logic circuit 151. It is the same as sushi.

[0062] Next, an example of the operation of the shift register shown in FIG. 2 will be described with reference to FIG. 3. 3 is a timing chart for explaining an example of the operation of the shift register shown in FIG. 2; No. CK1, signal CK2, signal IN1, signal IN2, node 121, node 122, node 123, node 124, signal OUT1a, signal OUT1b, signal OUT2a, signal OUT 2b, signal OUT3a, and signal OUT3b are shown in waveform. In an example of the operation of the shift register shown in FIG. 2, which will be explained with reference to FIG. 3, each signal is converted into a binary value. The following description will be given assuming that the signals are digital signals and that the signals CK1 and CK2 are clock signals. The value of the power supply voltage is set equal to the high-level voltage VH, and the value of the low power supply voltage is set equal to the low-level voltage VH. V L In addition, in the operation of the logic circuit in this embodiment, the The voltage state of each signal can also be inverted.

[0063] The operation of the shift register shown in Figure 2 can be explained by dividing it into several periods. The operation in the following will be described.

[0064] First, the operation of each period will be described with reference to the logic circuit 151. In the period 141, the signal CK1 is at a low level, the signal CK2 is at a low level, the signal IN1 is at a low level, The signal IN2 is at a high level.

[0065] At this time, the signals OUT1a, OUT1b, and OUT2a in the logic circuit 151 are It is low level.

[0066] Next, in period 142, signal CK1 goes high at time A2, and signal CK2 goes low. The signals IN1 and IN2 remain at high and low levels, respectively. Note that the signal IN1 may be at a high level during the period 141, and the signal IN2 may be at a high level during the period It may go low during 141.

[0067] At this time, in the logic circuit 151, the transistor 101 and the transistor 110 are in an on state. The transistor 104 and the transistor 107 are in an off state. In response to N1, the potential of the node 121 and the potential of the node 124 increase, and the voltage V H Same as Furthermore, the transistor 102 is turned on in response to the potential of the node 121. The voltage of the signal OUT1a rises. At this time, the voltage of the signal OUT1a is rises in accordance with the potential of node 121, and the voltage V H It is the same as the so-called bootstrap. The potential of the node 124 increases in accordance with the voltage of the signal IN1. Pressure V H Furthermore, the transistor 111 is turned on in response to the potential of the node 124. The voltage of the signal OUT1b becomes V L At this time, the capacitance element 106 A voltage corresponding to the potential of the node 122 and the low power supply voltage is applied, and the capacitance element 106 The potential of the node 22 is held for a certain period. A voltage corresponding to the low power supply voltage is applied, and the potential of the node 124 is kept constant by the capacitance element 112. When there is no off-state current of the transistor 104 and the transistor 110, The voltages held in the capacitance element 106 and the capacitance element 112 are held within a certain range of values. A transistor with low off-state current, such as a transistor that can be applied to the logic circuit of this embodiment, By using a transistor, the potential of the node 122 and the node The potential of the electrode 124 can be maintained within a certain range.

[0068] Next, in period 143, the signal CK1 goes low at time A3, and the signal CK2 goes low. The signal IN1 remains at the low level, and the signal IN2 goes to the high level.

[0069] At this time, the logic circuit 151 includes the transistors 101, 104, and 107 and transistor 110 are turned off, and the potential of node 121 is set to voltage V H Same as The potential of node 122 is held at the same value as the voltage V L The potential of node 123 is held at voltage V L and the potential of node 124 is held at voltage V H and the signal OUT1a is held at a high level. The signal OUT1b remains at a low level.

[0070] Next, during a period 144, the signal CK1 remains at a low level, and the signal CK2 is turned on at a time A4. signal IN1 remains low and signal IN2 remains high. The signal IN1 may go low at time A3, and the signal IN2 may go high at time A3.

[0071] At this time, the logic circuit 151 maintains the state in the period 143, and the signal OUT1a is high. The signal OUT1b remains at a low level.

[0072] Next, in a period 145, the signal CK1 remains at a low level, and the signal CK2 is At 5, the signal IN1 remains at low level and the signal IN2 goes high. It remains the same.

[0073] At this time, the logic circuit 151 maintains the state in the period 144, and the signal OUT1a is high. The signal OUT1b remains at a low level.

[0074] Next, in period 146, signal CK1 goes high at time A6, and signal CK2 goes high. signal IN1 remains at a low level, and signal IN2 remains at a high level. It remains the same.

[0075] At this time, the logic circuit 151 includes the transistors 101, 104, and The transistor 107 and the transistor 110 are turned on, and the potential of the node 121 and the node 12 The potential at 4 is voltage V L Furthermore, the potential of the node 121 and the potential of the node 124 are the same as In response to this, the transistor 102 and the transistor 111 are turned off. The potential of node 22 and the potential of node 123 increase, and the voltage V H Furthermore, The transistors 105 and 106 are connected in response to the potential of the node 122 and the potential of the node 123. 11 is turned on, and the voltage of the signal OUT1a becomes voltage V L The voltage of the signal OUT1b is the voltage V H At this time, the capacitor 106 is connected to the potential of the node 122 and the low power supply voltage. A voltage corresponding to the voltage is applied, and the potential of the node 122 is maintained for a certain period by the capacitance element 106. In addition, a voltage corresponding to the potential of the node 124 and the low power supply voltage is applied to the capacitor 112. The potential of the node 124 is maintained for a certain period by the capacitor 112. When there is no off-state current of the transistor 4 and the transistor 110, the capacitors 106 and 112 The voltage held is held within a certain range of values, so it is applicable to the logic circuit of this embodiment. By using a transistor with low off-state current, such as a transistor that can When the starter is in the off state, the potential of the node 122 and the potential of the node 124 are set to values ​​within a certain range. It can be kept while maintaining.

[0076] During the subsequent period, the logic circuit 151 maintains the same state for a certain period, and the signal OUT1a The voltage of signal OUT1b is maintained at a low level for a certain period of time, and the voltage of signal OUT1b is maintained at a high level for a certain period of time. The data is maintained in a constant manner.

[0077] Furthermore, the logic circuits in the stages after the logic circuit 151 (here, as an example, the logic circuit 152 and the logic circuit The operation of each logic circuit is explained below. Since this is the same as the logic circuit 151 except for the state of (a), the explanation will be omitted here.

[0078] First, in the period 144, the logic circuit 152 detects that the signal OUT2a, which is the output signal, is at time A At 4, the signal OUT2b goes high, and the signal OUT2b remains low.

[0079] Furthermore, during the period 145 to the period 147, the logic circuit 152 is in the same state as during the period 144. The signal OUT2a remains at a high level, and the signal OUT2b remains at a low level. There are even some.

[0080] Furthermore, during period 148, logic circuit 152 detects that signal OUT2a is low at time A8. The signal OUT2b goes high at time A8.

[0081] Furthermore, during the period 146, the logic circuit 153 detects that the signal OUT2a, which is the output signal, is at time A6 goes high, and signal OUT2b remains low.

[0082] Furthermore, during the period 147 to the period 149, the logic circuit 153 is in the same state as during the period 146. The signal OUT3a remains at a high level, and the signal OUT3b remains at a low level. There are even some.

[0083] Furthermore, during period 150, logic circuit 152 detects that signal OUT3a is low at time A10. The signal OUT3b goes to high level.

[0084] Although not shown, a shift register may be configured using logic circuits of three or more stages. Similarly, the voltage state of the output signal in the logic circuit changes sequentially for each stage.

[0085] As described above, the shift register of this embodiment has two different logic circuits in each stage. In addition, the shift register of this embodiment can output an output signal having a voltage state. The gate potential of the transistor for setting the output signal to a high level or a low level is periodically The transistor has a structure including a storage capacitor for storing data for a certain period of time, and has a low off-state current. In this case, a transistor having an oxide semiconductor layer as a channel formation layer is used. This configuration reduces the leakage current through the transistor, resulting in a storage capacitance The voltage can be maintained within a certain range for a certain period of time, preventing malfunctions. In addition, the leakage current from the transistors is reduced, which reduces power consumption. In addition, a transistor having an oxide semiconductor layer as a channel formation layer can be In the case of the oxide semiconductor layer, the impurity concentration is low, and therefore the variation in threshold voltage is small. In a shift register having a large number of transistors, the variation in the threshold voltage of the transistors If the temperature is high, the voltage required to turn on all the transistors is high, so the Therefore, by using a transistor including an oxide semiconductor layer in the shift register of this embodiment, This makes it possible to reduce power consumption.

[0086] Furthermore, in this embodiment, a semiconductor device using a shift register according to one embodiment of the present invention as a driver circuit is described. In this embodiment, as an example, a semiconductor device is provided on the same substrate. The display device also has a part of a driver circuit and a pixel section including pixels whose display state is controlled by the driver circuit. The display device will now be described.

[0087] An example of a block diagram of an active matrix display device is shown in FIG. On the plate 5300, a pixel portion 5301, a first scanning line driving circuit 5302, a second scanning line driving circuit 5303, a The pixel portion 5301 has a plurality of signal lines. A plurality of scanning lines are arranged extending from the signal line driving circuit 5304, and the first scanning line driving circuit 5 302 and the second scanning line driver circuit 5303. At the intersections with the signal lines, pixels each having a display element are arranged in a matrix. In addition, the substrate 5300 of the display device is made of FPC (Flexible Printed Circuit). A timing control circuit 5305 (controller, control I) is connected to the timing control circuit 5305 via a connection part such as a C).

[0088] In FIG. 4A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. The number of externally provided components such as drive circuits is reduced, which contributes to cost reduction. When a driving circuit is provided outside the substrate 5300, it becomes necessary to extend the wiring, and the connection between the wiring becomes difficult. If a driver circuit is mounted on the same board 5300, the number of connections between the wiring will be reduced. This makes it possible to improve reliability or yield.

[0089] The timing control circuit 5305 controls the first scanning line driver circuit 5302 as follows: The first scanning line driving circuit start signal (GSP1), the first scanning line driving circuit clock The timing control circuit 5305 also supplies the second scanning line driver (GCK1). For example, a start signal (GSP2) for the second scanning line driver circuit is sent to the driving circuit 5303. (also called a start pulse) and a clock signal (GCK2) for the scanning line driving circuit. In addition, the timing control circuit 5305 controls the signal line driver circuit 5304 to Start signal for signal line driver circuit (SSP), clock signal for signal line driver circuit (SCK), It provides data for video signals (DATA) (also simply called video signals) and latch signals (LAT). Each clock signal may be a plurality of clock signals with different periods, or may be a single clock signal. The first clock signal may be supplied together with an inverted signal (CKB). a start signal for the first scanning line driving circuit, a start signal for the second scanning line driving circuit, A clock signal for the signal line driver circuit, a start signal for the signal line driver circuit, and a clock signal for the signal line driver circuit In the semiconductor device of this embodiment, the first scanning line driver circuit It is possible to omit either the second scanning line driver circuit 5302 or the second scanning line driver circuit 5303.

[0090] In FIG. 4B, circuits with low driving frequencies (for example, the first scanning line driving circuit 5302, the second scanning line driving circuit 5303, The scanning line driver circuit 5303 is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver This shows a structure in which the circuit 5304 is formed on a substrate different from that of the pixel portion 5301. The thin film transistor has a lower field-effect mobility than a transistor using a single-crystal semiconductor due to its structure. A driver circuit formed on the substrate 5300 can be configured using transistors. Therefore, it is possible to increase the size of the display device, reduce the number of processes, reduce costs, or improve yields. It is possible.

[0091] 5(A) and 5(B) show the configuration of a signal line driver circuit configured with N-channel TFTs. An example of the operation will be described below.

[0092] The signal line driver circuit shown in FIG. 5A includes a shift register 5601 and a switching circuit 5602. The switching circuit 5602 has a plurality of switching circuits. The switching circuits 5602_1 to 5602_N (N is a natural number of 2 or more) are each a thin film transistor. Multiple transistors named 5603_1 to 5603_k (k is a natural number greater than or equal to 2) are used. Here, the thin film transistors 5603_1 to 5603_k are N-channel thin film transistors. We will explain an example where T is

[0093] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. One of the source and the drain of each of the thin film transistors 5603_1 to 5603_k is The thin film transistor 5603_1 is electrically connected to the wirings 5604_1 to 5604_k. The other of the source and drain of each of the electrodes 5603_k is electrically connected to the corresponding one of the signal lines S1 to Sk. The gates of the thin film transistors 5603_1 to 5603_k are connected to a wiring 5605_1. are electrically connected.

[0094] The shift register 5601 sequentially transmits high-level signals to the wirings 5605_1 to 5605_N. and has the function of sequentially selecting the switching circuits 5602_1 to 5602_N. .

[0095] The switching circuit 5602_1 is connected to the wirings 5604_1 to 5604_k and the signal lines S1 to Sk. The function of controlling the conduction state between the signal line S1 and the wiring 5604_1 to 5604_k is to 〜Sk. In this way, the switching circuit 560 2_1 has a function as a selector. 03_k indicate the conduction state between the wirings 5604_1 to 5604_k and the signal lines S1 to Sk, respectively. The function of controlling the potential of the wirings 5604_1 to 5604_k is to supply the potential of the signal lines S1 to Sk. In this way, each of the thin film transistors 5603_1 to 5603_k has the following function: It functions as a switch.

[0096] The wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal.

[0097] Next, the operation of the signal line driver circuit of FIG. 5(A) will be explained with reference to the timing chart of FIG. 5(B). 5B, the signals Sout_1 to Sout_N and the signal Vda ta_1 to Vdata_k. 5601, and signals Vdata_1 to Vdata_k are , are examples of signals input to the wirings 5604_1 to 5604_k. One operation period of the drive circuit corresponds to one gate selection period in the display device. For example, the period is divided into periods T1 to TN. This is a period for writing video signal data (DATA) to pixels belonging to the selected row.

[0098] During the period T1 to the period TN, the shift register 5601 outputs a high-level signal to the wiring 56 For example, in the period T1, the shift register 5601 outputs a high level signal to the wiring 5605_1. Since the switches 5603_1 to 5603_k are turned on, the wiring 5604_1 to 5604_k and The signal lines S1 to Sk are electrically connected to the wirings 5604_1 to 5604_k. , Data(S1) to Data(Sk) are input. Data(S1) to Data(S k) are connected to the selected row via thin film transistors 5603_1 to 5603_k, respectively. In this way, during the periods T1 to TN, the pixels in the first to k-th columns are written. In the pixel of the selected row, the video signal data (DATA) is sequentially input to each k column. is written.

[0099] As described above, video signal data (DATA) is written to pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written This can prevent under-crowding.

[0100] Note that the shift register of one embodiment of the present invention is used as the shift register 5601. It is possible.

[0101] Next, the configuration of the scanning line driving circuit will be described. The scanning line driving circuit has a shift register. In some cases, a level shifter, a buffer, etc. may also be included. In the operation circuit, the selection signal is generated by a shift register. The signal is buffered and amplified in the amplifier and supplied to the corresponding scanning line. The gates of the pixel transistors are electrically connected. Since all the transistors must be turned on at the same time, the buffer must be able to pass a large current. What is possible is used.

[0102] As described above, the shift register which is one embodiment of the present invention can be applied to a driver circuit of a semiconductor device. By using the shift register according to one embodiment of the present invention, it is possible to The display period of the image can be extended, so power consumption is reduced when displaying a still image, for example. can be reduced.

[0103] (Embodiment 2) This embodiment relates to a transistor constituting a logic circuit and a semiconductor device disclosed in this specification. Examples of applicable thin film transistors are shown below.

[0104] One mode of the semiconductor device and the manufacturing method of the semiconductor device of this embodiment will be described with reference to FIGS. I will explain.

[0105] 31(A) and 31(B) show an example of a planar and cross-sectional structure of a semiconductor device. The thin film transistor 410 shown in FIG. 4 is one of the thin film transistors with a top gate structure.

[0106] FIG. 31(A) is a plan view of a thin film transistor 410 having a top gate structure, and FIG. 31(B) is a plan view of a thin film transistor 410 having a top gate structure. ) is a cross-sectional view taken along line C1-C2 in FIG. 31(A).

[0107] The thin film transistor 410 includes an insulating layer 407, an oxide semiconductor layer 412, a silicon dioxide film 413, and a silicon dioxide film 414 on a substrate 400. a source or drain electrode layer 415a and a source or drain electrode layer 415b , a gate insulating layer 402, a gate electrode layer 411, and a source or drain electrode layer 4 15a, and the source or drain electrode layer 415b are connected to the wiring layer 414a and the wiring layer 414b, respectively. 14b is provided adjacent to and electrically connected to the first electrode 14a.

[0108] The thin film transistor 410 is described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor with a multi-gate structure having multiple channel forming regions may be used. A data can also be formed.

[0109] 6A to 6E, a thin film transistor 410 is fabricated on a substrate 400. The process will be explained.

[0110] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least In either case, it is necessary for the barium phosphate to have sufficient heat resistance to withstand subsequent heat treatment. A glass substrate such as borosilicate glass or aluminoborosilicate glass can be used.

[0111] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point will be 730°C or higher. The glass substrate may be made of, for example, aluminosilicate glass, aluminum Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. Generally, it contains more barium oxide (BaO) than boron oxide (B2O3). Therefore, the glass containing more BaO than B2O3 is more practical. It is preferable to use a glass substrate containing

[0112] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, a substrate made of an insulating material may be used. Alternatively, a crystallized glass substrate or the like may be used. Furthermore, a plastic substrate or the like can also be used as appropriate.

[0113] First, an insulating layer 407 is formed as a base film over a substrate 400 having an insulating surface. The insulating layer 407 in contact with the conductor layer is a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or the like. It is preferable to use an oxide insulating layer such as an aluminum layer or an aluminum oxynitride layer. The method for forming 7 can be a plasma CVD method, a sputtering method, or the like. However, in order to prevent a large amount of hydrogen from being contained in the insulating layer 407, the sputtering method is used. An insulating layer 407 is preferably formed.

[0114] In this embodiment, a silicon oxide layer is formed as the insulating layer 407 by a sputtering method. The substrate 400 is transferred to a processing chamber and subjected to a spatula containing high-purity oxygen from which hydrogen and moisture have been removed. A targeting gas is introduced and a silicon target is used to form an insulating layer 407 on the substrate 400. The silicon oxide layer is deposited on the substrate 400. The substrate 400 may be at room temperature or may be heated.

[0115] For example, quartz (preferably synthetic quartz) is used as a target, the substrate temperature is 108° C., and the substrate The distance between the target and the source (TS distance) was set to 60 mm, the pressure was set to 0.4 Pa, and the high frequency power supply was set to 1 0.5kW, oxygen and argon (oxygen flow rate 25sccm: argon flow rate 25sccm = 1: 1) A silicon oxide film is formed by RF sputtering in an atmosphere. The film thickness is 100 nm. In place of quartz (preferably synthetic quartz), the silicon target is replaced by silicon oxide. It can be used as a target for forming a silicon film. Oxygen or a mixed gas of oxygen and argon is used as the gas.

[0116] In this case, it is preferable to form the insulating layer 407 while removing the remaining moisture in the processing chamber. This is to prevent the insulating layer 407 from containing hydrogen, a hydroxyl group, or moisture.

[0117] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O) and other compounds containing hydrogen atoms are discharged. The concentration of impurities contained can be reduced.

[0118] The sputtering gas used in forming the insulating layer 407 is hydrogen, water, a hydroxyl group, or a hydride. By using high-purity gas in which impurities such as It is preferable that:

[0119] The sputtering method uses a high frequency power supply as the sputtering power source. , DC sputtering method using a DC power supply, and pulse D RF sputtering is mainly used to form insulating films. The DC sputtering method is mainly used to form metal films.

[0120] There are also multi-target sputtering systems that can accommodate multiple targets of different materials. The sputtering equipment can deposit layers of different materials in the same chamber, or It is also possible to form films by discharging multiple types of materials simultaneously using the bar.

[0121] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. E using a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the CR sputtering method.

[0122] In addition, as a film formation method using the sputtering method, the target material and the sputtering Reactive sputtering is a method of forming a compound thin film by chemically reacting the gas components with the There are also methods such as a sputtering method in which a voltage is applied to the substrate during film formation, and a bias sputtering method in which a voltage is also applied to the substrate during film formation.

[0123] The insulating layer 407 may have a laminated structure, for example, a silicon nitride layer, a nitride layer, and so on from the substrate 400 side. nitride insulation such as silicon oxide, aluminum nitride, or aluminum oxide nitride layers; The insulating layer may have a stacked structure of the insulating layer and the oxide insulating layer.

[0124] For example, hydrogen and moisture are removed, and a high-purity sputtering gas containing nitrogen is introduced to form a silicon wafer. A silicon nitride layer is deposited between the silicon oxide layer and the substrate using a cone target. In this case, as with the silicon oxide layer, the remaining moisture in the processing chamber is removed while the silicon nitride layer is formed. It is preferable to form a coating layer.

[0125] When forming a silicon nitride layer, the substrate may also be heated during film formation.

[0126] When a silicon nitride layer and a silicon oxide layer are stacked as the insulating layer 407, the silicon nitride layer The silicon oxide layer and the silicon nitride layer are formed in the same processing chamber using a common silicon target. First, an etching gas containing nitrogen is introduced to etch the silicon wafers mounted in the processing chamber. A silicon nitride layer is formed using a target, and then the etching gas is changed to an etchant containing oxygen. The silicon oxide layer is then deposited using the same silicon target with the same nitriding gas. The silicon layer and the silicon oxide layer can be formed successively without exposure to the atmosphere. This can prevent impurities such as hydrogen and moisture from being adsorbed onto the surface of the silicon nitride layer.

[0127] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the insulating layer 407. .

[0128] In order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the oxide semiconductor film as much as possible, As a pretreatment for film formation, a substrate on which an insulating layer 407 is formed in a preheating chamber of a sputtering device The substrate 400 is preheated to desorb and discharge impurities such as hydrogen and moisture adsorbed on the substrate 400. It is preferable that the exhaust means provided in the preheating chamber is a cryopump. This preheating process can be omitted. This may be performed on the substrate 400 before the insulating layer 402 is formed, or after the source electrode layer or the drain electrode layer is formed later. The substrate 4 is formed with the drain electrode layer 415a and the source or drain electrode layer 415b. You can do the same for 00.

[0129] Before the oxide semiconductor film was formed by a sputtering method, argon gas was introduced. Plasma is generated to perform reverse sputtering, and dust adhering to the surface of the insulating layer 407 is removed. Reverse sputtering is a method in which a target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using a high frequency power supply under atmospheric pressure to generate plasma and modify the substrate surface. It should be noted that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere. .

[0130] The oxide semiconductor film is formed by sputtering. nO-based film, In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn -O-based, Al-Zn-O-based, In-O-based, Sn-O-based, and Zn-O-based oxide semiconductor films In this embodiment, the oxide semiconductor film is formed using a method for forming an In—Ga—Zn—O-based oxide semiconductor film. The oxide semiconductor film is formed by a sputtering method using a target. (typically argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) and The film can be formed by sputtering in a mixed atmosphere of oxygen and silicon. When using the targeting method, a target containing SiO2 of 2% by weight or more and 10% by weight or less is used. The film may be formed using the above method.

[0131] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, or hydrogen. High-purity gas is used, in which impurities such as chlorine have been removed to concentrations of ppm or ppb. It is preferable that

[0132] A target for forming an oxide semiconductor film by a sputtering method is a substrate containing zinc oxide as the main component. A metal oxide target can be used. Another example is a target for forming an oxide semiconductor film containing In, Ga, and Zn (composition ratio: As the composition, In2O3:Ga2O3:ZnO=1:1:1 [mol%], In:Ga:Zn =1:1:0.5 [atom%]). In, Ga, and Zn As a target for oxide semiconductor film formation containing In:Ga:Zn=1:1:1 [atom %], or a target having a composition ratio of In:Ga:Zn=1:1:2 [atom%] In addition, it is possible to use a target for forming an oxide semiconductor film having a volume of 10 ... The ratio of the volume of the part excluding the space occupied by voids, etc. to the total volume (also called the filling rate) The filling rate is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a target for oxide semiconductor film formation with a low thickness, the formed oxide semiconductor film is dense. It becomes a membrane.

[0133] The substrate is held in a processing chamber maintained in a reduced pressure state, and hydrogen and A sputtering gas from which the moisture and the like have been removed is introduced, and a metal oxide is used as a target to sputter the substrate 4. In order to remove residual moisture in the treatment chamber, an adsorption-type It is preferable to use a vacuum pump. For example, a cryopump, an ion pump, a titanium sa It is preferable to use a displacement pump. Also, a turbo pump is used as the exhaust means. A cold trap may be added to the chamber. The chamber may contain, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (HO), etc. (more preferably, carbon Since the exhaust gas contains the oxide semiconductor film formed in the deposition chamber, The concentration of impurities introduced into the oxide semiconductor film can be reduced.

[0134] As an example of the film formation conditions, the substrate temperature is room temperature, the distance between the substrate and the target is 60 mm, Pressure 0.4 Pa, DC power 0.5 kW, oxygen and argon (oxygen flow rate 15 scc The conditions are as follows: argon flow rate 30 sccm; pulsed direct current (DC ) power supply, powdery substances (also called particles or dust) generated during film formation can be reduced. The oxide semiconductor film is preferably 5 nm or more and 30 nm or more in thickness. The appropriate thickness varies depending on the oxide semiconductor material used. The thickness can be selected appropriately depending on the application.

[0135] Next, the oxide semiconductor film is subjected to a first photolithography process to form an island-shaped oxide semiconductor layer 4 In order to form the island-shaped oxide semiconductor layer 412, The resist mask for this purpose may be formed by an ink-jet method. When the film is formed by the PET method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0136] The etching of the oxide semiconductor film here can be performed by either dry etching or wet etching. Either one or both may be used.

[0137] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0138] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and rare gases such as helium (He) and argon (Ar) Additive gases, etc. can be used.

[0139] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0140] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0141] In addition, after wet etching, the etching solution is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium and the like contained in the oxide semiconductor layer may be recycled from the waste liquid after etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0142] The etching conditions (etching) are adjusted to suit the material so that the desired processing shape can be etched. The etching conditions (liquid, etching time, temperature, etc.) are adjusted appropriately.

[0143] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 412 by etching.

[0144] In this embodiment, the oxide semiconductor layer 412 is subjected to first heat treatment. The temperature is set to 400° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the strain point of the substrate. Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated to a nitrogen atmosphere. After heat treatment at 450°C for 1 hour in a nitrogen atmosphere, the material was oxidized without exposure to air. This first heat treatment prevents water and hydrogen from re-entering the oxide semiconductor layer, resulting in an oxide semiconductor layer. Therefore, the oxide semiconductor layer 412 can be dehydrated or dehydrogenated.

[0145] The heat treatment device is not limited to an electric furnace, and may be a device that uses heat conduction from a heating element such as a resistance heating element. Alternatively, a device that heats the object to be treated by thermal radiation may be used. For example, a GRTA (Ga s Rapid Thermal Anneal) equipment, LRTA (Lamp Rapi) d Thermal Anneal (RTA) equipment The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Iridium lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, A device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a pressure mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. The gas used is a rare gas such as argon or nitrogen, which reacts little with the object to be treated by heat treatment. An inert gas that does not react is used.

[0146] For example, as the first heat treatment, a base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate is moved and placed in the oven, heated for several minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. GRTA can be used to heat the food at high temperatures in a short time. become.

[0147] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, or the like. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. or 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably It is preferable to keep the concentration below 0.1 ppm.

[0148] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may It may crystallize to become a microcrystalline film or polycrystalline film. For example, the crystallization rate is 90% or more, or In some cases, the oxide semiconductor film is microcrystalline by 80% or more. Alternatively, depending on the material of the oxide semiconductor layer, the oxide semiconductor layer may be an amorphous oxide semiconductor film containing no crystalline components. In addition, there are cases where microcrystalline parts (grain size 1 nm to 20 nm) are present in the amorphous oxide semiconductor. In some cases, the oxide semiconductor film may contain a mixture of .

[0149] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography process.

[0150] The heat treatment that has the effect of dehydrating and dehydrogenating the oxide semiconductor layer is performed after the oxide semiconductor layer formation. After the formation of the oxide semiconductor layer, a source electrode layer and a drain electrode layer are stacked on the oxide semiconductor layer. The step may be performed either after forming the gate insulating layer on the drain electrode or after forming the gate insulating layer on the drain electrode.

[0151] Next, a conductive film is formed over the insulating layer 407 and the oxide semiconductor layer 412. The conductive film can be formed by deposition or vacuum deposition. Materials for the conductive film include Al, Cr, and , Cu, Ta, Ti, Mo, W, or a composite containing the above elements. Examples of the metal include gold and alloy films made of a combination of the above elements. The material is selected from one or more of aluminum, zirconium, beryllium, and thorium. The conductive film may have a single layer structure or a laminated structure of two or more layers. 2. A single layer structure of aluminum film containing silicon, 3. A titanium film laminated on an aluminum film. Layer structure: Ti film, aluminum film is layered on top of the Ti film, and Ti In addition, titanium (Ti) and tantalum (T a), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neodymium), Films made of a single or multiple combinations of elements selected from Sc (scandium), and their alloys A film or a nitride film may be used.

[0152] A resist mask is formed on the conductive film by a second photolithography process, and selective etching is performed. The source or drain electrode layer 415a is then After the electrode layer 415b is formed, the resist mask is removed (see FIG. 6(B)). When the ends of the formed source electrode layer and drain electrode layer are tapered, the gate electrode layer stacked thereon can be easily formed. This is preferable because it improves the coverage of the insulating layer.

[0153] In this embodiment, the source or drain electrode layer 415a As the electrode layer 415b, a titanium film having a thickness of 150 nm is formed by sputtering.

[0154] Note that the oxide semiconductor layer 412 is removed during etching of the conductive film. The respective materials and etching conditions are selected so that the insulating layer 407 underneath is not exposed. Adjust as appropriate.

[0155] Note that in the second photolithography step, only a part of the oxide semiconductor layer 412 is etched. In some cases, the oxide semiconductor layer has a groove (a recess). The drain electrode layer 415a and the source or drain electrode layer 415b are formed by The resist mask may be formed by an ink-jet method. When the film is formed by this method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0156] The exposure to light when forming the resist mask in the second photolithography process is done using ultraviolet light or KrF laser. The source electrode layers adjacent to each other on the oxide semiconductor layer 412 are exposed to the laser beam or ArF laser beam. The width of the gap between the end of the drain electrode layer and the lower end of the drain electrode layer determines the channel width of the thin film transistor to be formed later. The channel length L is determined. When performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from 10 nm to several tens of nm. t) is used to perform exposure when forming a resist mask in the second photolithography process. UV exposure has high resolution and a large depth of focus. The channel length L of the transistor can be set to 10 nm or more and 1000 nm or less. The operating speed can be increased and the off-state current can be made extremely small, resulting in low power consumption. It is also possible to reduce power consumption.

[0157] Next, the insulating layer 407, the oxide semiconductor layer 412, the source or drain electrode layer 415 a) A gate insulating layer 402 is formed over the source or drain electrode layer 415b (FIG. 6 See (C). ).

[0158] The gate insulating layer 402 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer The gate insulating layer 402 can be formed as a single layer or a stacked layer. In order to prevent a large amount of the oxide from being contained, the gate insulating layer 402 is formed by sputtering. When forming a silicon oxide film by sputtering, it is preferable to A silicon target or a quartz target is used as the sputtering target, and oxygen is used as the sputtering gas. A mixed gas of oxygen and argon or oxygen and argon is used.

[0159] The gate insulating layer 402 is a source or drain electrode layer 415a. A silicon oxide layer and a silicon nitride layer are stacked from the rain electrode layer 415b side. For example, a silicon oxide film having a thickness of 5 nm to 300 nm can be used as the first gate insulating layer. A silicon layer (SiOx (x>0)) is formed, and a second gate insulating layer is formed on the first gate insulating layer. Then, a silicon nitride layer (SiN) with a thickness of 50 nm to 200 nm is formed by sputtering. y (y>0) may be stacked to form a gate insulating layer with a film thickness of 100 nm. The pressure was 0.4 Pa, the high frequency power was 1.5 kW, and oxygen and argon (oxygen flow rate 25 scc The film was deposited by RF sputtering under an atmosphere of argon (flow rate 25 sccm = 1:1) to a thickness of 1 Form a 00 nm silicon oxide layer.

[0160] Next, a resist mask is formed by a third photolithography process and selectively etched. The source electrode layer or the drain electrode layer 402 is removed by etching. 15a, an opening 421a reaching the source or drain electrode layer 415b, and an opening 421b (See FIG. 6(D)).

[0161] Next, a conductive film is formed over the gate insulating layer 402 and the openings 421a and 421b. A gate electrode layer 411 and wiring layers 414a and 414b are formed by the photolithography process. The resist mask may be formed by an ink-jet method. When formed by the ink jet method, no photomask is used, which reduces manufacturing costs.

[0162] The gate electrode layer 411 and the wiring layers 414a and 414b are made of molybdenum, titanium, chromium, or the like. Metallic materials such as tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. The layer can be formed as a single layer or a multilayer using an alloy material containing these as the main component.

[0163] For example, a two-layer laminate structure of a gate electrode layer 411 and wiring layers 414a and 414b may be Two-layer laminate structure with a molybdenum layer laminated on an aluminum layer, or a molybdenum layer laminated on a copper layer or a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on a copper layer. Preferably, the structure is a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated. The laminated structure is a tungsten layer or a tungsten nitride layer, aluminum, and silicon. a titanium nitride layer or a titanium layer, and a titanium alloy layer or an aluminum-titanium alloy layer. It is preferable that the gate electrode layer be formed using a light-transmitting conductive film. Examples of the light-transmitting conductive film include a light-transmitting conductive oxide. It is possible.

[0164] In this embodiment, the gate electrode layer 411 and the wiring layers 414a and 414b are formed by sputtering. A titanium film having a thickness of 150 nm is formed by the method.

[0165] Next, a second heat treatment (preferably 20 The heating temperature is 0°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. A second heat treatment is carried out at 250°C for 1 hour in a nitrogen atmosphere. This may be performed after a protective insulating layer or a planarizing insulating layer is formed over the film transistor 410 .

[0166] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature, or by heating from room temperature to 1 The temperature is raised to a temperature between 00°C and 200°C and then lowered from the heating temperature to room temperature multiple times. Alternatively, this heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. If the heat treatment is carried out under reduced pressure, the heating time can be shortened.

[0167] Through the above steps, the oxide semiconductor layer 41 in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced is obtained. 2, a thin film transistor 410 having the same structure as in FIG. 6(E) can be formed.

[0168] In addition, a protective insulating layer and a planarizing insulating layer for planarization are provided over the thin film transistor 410. For example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like may be used as the protective insulating layer. A silicon nitride oxide layer, a silicon nitride oxide layer, or an aluminum oxide layer may be formed as a single layer or a stacked layer. can.

[0169] The planarization insulating layer may be made of polyimide, acrylic resin, benzocyclobutene resin, Heat-resistant organic materials such as polyamide and epoxy resin can be used. In addition to the above organic materials, low-k materials, siloxane resins, and PSG (phosphor silicon dioxide) are also available. Glass), BPSG (borophosphorus glass), etc. can be used. A planarization insulating layer may be formed by stacking a plurality of insulating films formed by the above method.

[0170] The siloxane resin is a Si—O— compound formed using a siloxane material as a starting material. It corresponds to a resin containing Si bonds. Siloxane resins contain organic groups (e.g., alkane) as substituents. Alternatively, an alkyl group or an aryl group, or a fluoro group may be used. It's fine.

[0171] The method for forming the planarizing insulating layer is not particularly limited, and may be a sputtering method, a SO G method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen Printing machines, such as offset printing, doctor knives, roll coaters, curtain coaters, A knife coater or the like can be used.

[0172] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0173] When forming the oxide semiconductor film as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. The oxide semiconductor film can be stabilized.

[0174] As described above, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, A highly reliable semiconductor device having stable electrical characteristics can be provided.

[0175] (Embodiment 3) This embodiment relates to a transistor constituting a logic circuit and a semiconductor device disclosed in this specification. Other examples of applicable thin film transistors are shown below. The functional parts and steps may be the same as those in the second embodiment, and the repeated explanations thereof will be omitted. Further, detailed explanations of the same parts will also be omitted.

[0176] One mode of the semiconductor device and the manufacturing method of the semiconductor device of this embodiment will be described with reference to FIGS. explain.

[0177] 7(A) and 7(B) show an example of a planar and cross-sectional structure of a semiconductor device. The thin film transistor 460 is one of the thin film transistors with a top gate structure.

[0178] FIG. 7A is a plan view of a thin film transistor 460 having a top gate structure, and FIG. FIG. 8 is a cross-sectional view taken along line D1-D2 in FIG. 7(A).

[0179] The thin film transistor 460 is formed by forming an insulating layer 457, a source electrode 458, a gate electrode 459, a gate electrode 459a, a gate electrode 459b, a gate electrode 459c, a gate electrode 459d, a gate electrode 459e, a gate electrode 459f, a gate electrode 459g ... a drain or electrode layer 465a (465a1, 465a2), an oxide semiconductor layer 462, the source or drain electrode layer 465b, the wiring layer 468, the gate insulating layer 452, and the gate The electrode layer 461 (461a, 461b) includes a source electrode layer or a drain electrode layer 465a. (465a1, 465a2) are electrically connected to the wiring layer 464 via the wiring layer 468. Although not shown, the source or drain electrode layer 465b is also formed as a gate insulating layer. An opening provided in 452 electrically connects to the wiring layer.

[0180] 8A to 8E, a thin film transistor 460 is fabricated on a substrate 450. The process will be explained.

[0181] First, an insulating layer 457 serving as a base film is formed over a substrate 450 .

[0182] In this embodiment, a silicon oxide layer is formed as the insulating layer 457 by a sputtering method. The substrate 450 is transferred to a processing chamber, where hydrogen and moisture are removed and a high-purity spa containing oxygen is used. A targeting gas is introduced and a silicon target or quartz (preferably synthetic quartz) is used. A silicon oxide layer is formed as an insulating layer 457 on the substrate 450. The gas used is oxygen or a mixture of oxygen and argon.

[0183] For example, the purity of the sputtering gas is 6N, and quartz (preferably synthetic quartz) is used. The substrate temperature was 108°C, the distance between the substrate and the target (TS distance) was 60 mm, and the pressure was 0 0.4 Pa, high frequency power supply 1.5 kW, oxygen and argon (oxygen flow rate 25 sccm: argon A silicon oxide film was formed by RF sputtering under a gas atmosphere (flow rate 25 sccm = 1:1). The film thickness is 100 nm. Note that silicon is used instead of quartz (preferably synthetic quartz). The target can be used as a target for forming a silicon oxide film.

[0184] In this case, it is preferable to form the insulating layer 457 while removing the remaining moisture in the processing chamber. This is to prevent the insulating layer 457 from containing hydrogen, hydroxyl groups, or moisture. The deposition chamber evacuated using an opto-pump contains, for example, hydrogen atoms and water (H2O) Since compounds containing impurities are exhausted, the concentration of impurities contained in the insulating layer 457 formed in the film formation chamber is The degree can be reduced.

[0185] The sputtering gas used in forming the insulating layer 457 is hydrogen, water, a hydroxyl group, or a hydride. By using high-purity gas in which impurities such as It is preferable that:

[0186] The insulating layer 457 may have a laminated structure, for example, a silicon nitride layer, a nitride layer, and so on from the substrate 450 side. and nitride insulating layers such as silicon oxide layers, aluminum nitride layers, and aluminum oxide nitride layers. The insulating film may have a stacked structure with the oxide insulating layer.

[0187] For example, hydrogen and moisture are removed, and a high-purity sputtering gas containing nitrogen is introduced to form a silicon wafer. A silicon nitride layer is deposited between the silicon oxide layer and the substrate using a cone target. In this case, as with the silicon oxide layer, the remaining moisture in the processing chamber is removed while the silicon nitride layer is formed. It is preferable to form a coating layer.

[0188] Next, a conductive film is formed on the insulating layer 457, and a conductive film is formed by a first photolithography process. A resist mask is formed on the film, and selective etching is performed to form a source electrode layer or a drain electrode layer. After the electrode layers 465a1 and 465a2 are formed, the resist mask is removed (see FIG. 8(A)). The source and drain electrode layers 465a1 and 465a2 are separated in the cross-sectional view. Although the source electrode layer and the drain electrode layer are shown as a continuous film, they are not included in the film. The end of the gate insulating layer is preferably tapered to improve coverage with the gate insulating layer to be laminated thereon. stomach.

[0189] The source electrode layer or drain electrode layer 465a1, 465a2 may be made of Al, Cr, An element selected from Cu, Ta, Ti, Mo, and W, or an alloy containing the above elements or an alloy film made of a combination of the above elements. , zirconium, beryllium, and thorium. The conductive film may have a single layer structure or a stacked structure of two or more layers. For example, Single layer structure of aluminum film containing silicon, two-layer structure of titanium film laminated on aluminum film Structure: Ti film, aluminum film layered on top of the Ti film, and Ti film on top of that In addition, titanium (Ti) and tantalum (Ta) are also used in the ), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neodymium), S c (Scandium) Alternatively, a nitride film may be used.

[0190] In this embodiment, the source and drain electrode layers 465a1 and 465a2 are formed by sputtering. A titanium film having a thickness of 150 nm is formed by a deposition method.

[0191] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the gate insulating layer 452. Complete.

[0192] Next, an oxide semiconductor film is formed, and an island-shaped oxide semiconductor is formed by a second photolithography process. The oxide semiconductor film is processed into a layer 462 (see FIG. 8B). The film is formed by sputtering using a Ga-Zn-O oxide semiconductor film formation target. do.

[0193] The oxide semiconductor film is formed by holding the substrate in a treatment chamber maintained in a reduced pressure state and removing residual moisture in the treatment chamber. While removing the hydrogen and moisture, a sputtering gas from which hydrogen and moisture have been removed is introduced to form a metal oxide. An oxide semiconductor film is formed on the substrate 450 as a target. For this purpose, it is preferable to use an adsorption type vacuum pump. It is preferable to use a pump or a titanium sublimation pump. Alternatively, a turbo pump with a cold trap may be used. The film formation chamber evacuated using the gas contains, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) ( More preferably, compounds containing carbon atoms are also exhausted, so that the acid film formed in the film formation chamber is The concentration of impurities contained in the oxide semiconductor film can be reduced. may be heated.

[0194] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, or hydrogen. High-purity gas is used, in which impurities such as chlorine have been removed to concentrations of ppm or ppb. It is preferable that

[0195] As an example of the film formation conditions, the substrate temperature is room temperature, the distance between the substrate and the target is 60 mm, Pressure 0.4 Pa, DC power 0.5 kW, oxygen and argon (oxygen flow rate 15 scc The conditions are as follows: argon flow rate 30 sccm; pulsed direct current (DC ) power supply, powdery substances (also called particles or dust) generated during film formation can be reduced. The oxide semiconductor film is preferably 5 nm or more and 30 nm or more in thickness. The appropriate thickness varies depending on the oxide semiconductor material used. The thickness can be selected appropriately depending on the application.

[0196] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 462 by etching.

[0197] In this embodiment, first heat treatment is performed on the oxide semiconductor layer 462. The temperature is set to 400° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the strain point of the substrate. Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated to a nitrogen atmosphere. After heat treatment at 450°C for 1 hour in a nitrogen atmosphere, the material was oxidized without exposure to air. This first heat treatment prevents water and hydrogen from re-entering the oxide semiconductor layer, resulting in an oxide semiconductor layer. Therefore, the oxide semiconductor layer 462 can be dehydrated or dehydrogenated.

[0198] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat radiation from a heat source such as a resistance heating element. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. For example, the first heat treatment may be performed at a temperature of 650°C to 700°C. The substrate was transferred into an inert gas atmosphere heated to a high temperature of 100°C, and after heating for several minutes, the substrate was transferred Alternatively, GRTA can be performed by moving the device and releasing it from an inert gas heated to a high temperature. This allows high-temperature heat treatment in a short time.

[0199] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, or the like. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. or 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably It is preferable to keep the concentration below 0.1 ppm.

[0200] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may It may also crystallize to form a microcrystalline or polycrystalline film.

[0201] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography process.

[0202] The heat treatment that has the effect of dehydrating and dehydrogenating the oxide semiconductor layer is performed after the oxide semiconductor layer formation. After the formation of the oxide semiconductor layer, a source electrode layer and a drain electrode layer are further stacked on the oxide semiconductor layer. This may be performed either after forming a gate insulating layer on the source electrode and the drain electrode.

[0203] Next, a conductive film is formed over the insulating layer 457 and the oxide semiconductor layer 462. A resist mask is formed on the conductive film by a lithography process, and selective etching is performed. After forming the source or drain electrode layer 465b and the wiring layer 468, a resist mask The source or drain electrode layer 465b and the wiring layer 465c are removed (see FIG. 8C). The source electrode layer 68 is formed by the same material and process as the source electrode layer 465a1 and the drain electrode layer 465a2. It is sufficient to form it.

[0204] In this embodiment, the source or drain electrode layer 465b and the wiring layer 468 are formed by sputtering. A titanium film having a thickness of 150 nm is formed by a deposition method. and the source or drain electrode layers 465a1 and 465a2. In this example, the same titanium film is used for the source electrode layer 465a1 and the drain electrode layer 46b. The source or drain electrode layer 465b and the source or drain electrode layer 465a2 have a selectivity in etching. Therefore, the source electrode layer 465a1 and the drain electrode layer 465a2 are not connected to the source electrode The oxide semiconductor layer 465b is not etched during etching of the drain electrode layer 465a. The wiring layer 468 is formed on the source electrode layer or the drain electrode layer 465a2 that is not covered with the dielectric layer 462. The source and drain electrode layers 465a1 and 465a2 are provided. The drain electrode layer 465b is made of a different material having a high selectivity in an etching process. When used, the source or drain electrode layer 465a2 is protected during etching. The wiring layer 468 does not necessarily have to be provided.

[0205] Note that the conductive film is etched so that the oxide semiconductor layer 462 is not removed. The material and etching conditions are adjusted appropriately.

[0206] Note that in the third photolithography step, only a part of the oxide semiconductor layer 462 is etched. In some cases, the oxide semiconductor layer has a groove (a recess). A resist mask for forming the drain electrode layer 465b and the wiring layer 468 is formed by inkjet printing. If the resist mask is formed by the ink-jet method, the photomask Since no additional materials are used, the manufacturing cost can be reduced.

[0207] Next, the insulating layer 457, the oxide semiconductor layer 462, the source or drain electrode layer 465 a1, 465a2, the source or drain electrode layer 465b, and the wiring layer 468. A gate insulating layer 452 is formed.

[0208] The gate insulating layer 452 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer The gate insulating layer 452 can be formed as a single layer or a stacked layer. In order to prevent a large amount of ZnO from being contained, the gate insulating layer 452 is formed by sputtering. When forming a silicon oxide film by sputtering, it is preferable to A silicon target or a quartz target is used as the sputtering target, and oxygen is used as the sputtering gas. The process is carried out using oxygen or a mixed gas of oxygen and argon.

[0209] The gate insulating layer 452 is provided between the source and drain electrode layers 465a1 and 465a2, A silicon oxide layer and a silicon nitride layer were stacked on the source electrode layer or drain electrode layer 465b side. In this embodiment, the pressure is 0.4 Pa, the high frequency power supply is 1.5 kW, Oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1) atmosphere A silicon oxide layer with a thickness of 100 nm is formed on the substrate by RF sputtering.

[0210] Next, a resist mask is formed by a fourth photolithography process and selectively etched. A part of the gate insulating layer 452 is removed by etching to form an opening 423 reaching the wiring layer 438. Although not shown, when the opening 423 is formed, the source electrode layer or the drain electrode layer is formed. An opening may be formed that reaches the drain electrode layer 465b. Alternatively, the opening to the drain electrode layer 465b is formed after an interlayer insulating layer is further laminated. In this example, a wiring layer connected to the wiring layer is formed in the opening.

[0211] Next, a conductive film is formed over the gate insulating layer 452 and the opening 423, and then a fifth photolithography is performed. A gate electrode layer 461 (461a, 461b) and a wiring layer 464 are formed by a photolithography process. The resist mask may be formed by an ink-jet method. When formed by the jet method, no photomask is used, which reduces manufacturing costs.

[0212] The gate electrode layer 461 (461a, 461b) and the wiring layer 464 are made of molybdenum. , titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium It is formed by using a metal material such as aluminum or an alloy material containing these as the main component, in a single layer or in a laminated form. It is possible.

[0213] In this embodiment, gate electrode layer 461 (461a, 461b) and wiring layer 464 are formed of silicon dioxide. A titanium film having a thickness of 150 nm is formed by a tartering method.

[0214] Next, a second heat treatment (preferably 20 The heating temperature is 0°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. A second heat treatment is carried out at 250°C for 1 hour in a nitrogen atmosphere. This may be performed after a protective insulating layer or a planarizing insulating layer is formed over the film transistor 410 .

[0215] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature, or by heating from room temperature to 10 Repeat the heating process from 0°C to 200°C and then cooling it down to room temperature several times. Alternatively, this heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. If the heat treatment is carried out under reduced pressure, the heating time can be shortened.

[0216] Through the above steps, the oxide semiconductor layer 46 in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced is obtained. 2, a thin film transistor 460 can be formed (see FIG. 8(E)).

[0217] In addition, a protective insulating layer and a planarization insulating layer for planarization are provided over the thin film transistor 460. Although not shown, the source insulating layer 452, the protective insulating layer, and the planarizing insulating layer may be formed. An opening reaching the source or drain electrode layer 465b is formed in the opening. A wiring layer electrically connected to the drain electrode layer 465b is formed.

[0218] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0219] When forming the oxide semiconductor film as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. The oxide semiconductor film can be stabilized.

[0220] As described above, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, A highly reliable semiconductor device having stable electrical characteristics can be provided.

[0221] (Fourth embodiment) This embodiment relates to a transistor constituting a logic circuit and a semiconductor device disclosed in this specification. Other examples of applicable thin film transistors are shown below. The functional parts and steps may be the same as those in the second embodiment, and the repeated explanations thereof will be omitted. The detailed description of the same parts will also be omitted. The transistors 425 and 426 are thin-film transistors that constitute the logic circuit and semiconductor device of the first embodiment. It can be used as a data.

[0222] The thin film transistor of this embodiment will be described with reference to FIG.

[0223] 9(A) and 9(B) show an example of a cross-sectional structure of a thin film transistor. The thin film transistors 425 and 426 each have an oxide semiconductor layer sandwiched between a conductive layer and a gate electrode layer. It is one of the thin film transistors with this structure.

[0224] 9(A) and 9(B), a silicon substrate is used as the substrate, and the silicon substrate 42 Thin film transistors 425 and 426 are provided on an insulating layer 422 provided on the substrate. are.

[0225] In FIG. 9A, an insulating layer 422 and an insulating layer 407 are provided on a silicon substrate 420. A conductive layer 427 is provided between the oxide semiconductor layer 412 so as to overlap with at least the entire oxide semiconductor layer 412. .

[0226] 9B, the conductive layer between the insulating layer 422 and the insulating layer 407 is a conductive layer such as the conductive layer 424. The oxide semiconductor layer 412 is processed by etching as shown in FIG. This is an example of partial overlap.

[0227] The conductive layers 427 and 424 may be made of any metal material that can withstand the heat treatment temperature in the subsequent process. Titanium (Ti), Tantalum (Ta), Tungsten (W), Molybdenum (Mo), An element selected from chromium (Cr), neodymium (Nd), and scandium (Sc), or an alloy film containing the above elements, an alloy film combining the above elements, or an alloy film containing the above elements The nitride may be a single layer or a laminated layer. For example, a single tungsten layer or a laminated structure of a tungsten nitride layer and a tungsten layer may be used. You can be there.

[0228] The conductive layers 427 and 424 are connected to the gate electrode layers of the thin film transistors 425 and 426. It may be the same as or different from 411 and may function as a second gate electrode layer. Alternatively, the potentials of the conductive layers 427 and 424 may be fixed potentials such as GND and 0V. Good too.

[0229] The conductive layers 427 and 424 control the electrical characteristics of the thin film transistors 425 and 426. It is possible.

[0230] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0231] (Embodiment 5) This embodiment relates to a transistor constituting a logic circuit and a semiconductor device disclosed in this specification. Examples of applicable thin film transistors are shown below.

[0232] One mode of the thin film transistor and the manufacturing method of the thin film transistor of this embodiment will be described with reference to FIGS. This will be used to explain.

[0233] 10A to 10E show examples of cross-sectional structures of thin film transistors. The thin film transistor 390 shown in (E) is one of the bottom gate structures and is an inverted staggered thin film transistor. Also called a transistor.

[0234] The thin film transistor 390 will be described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor with a multi-gate structure having multiple channel formation regions may be used. A data can also be formed.

[0235] 10(A) to 10(E), a thin film transistor 390 is fabricated on a substrate 394. The process will be explained.

[0236] First, a conductive film is formed on a substrate 394 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 391 is formed by this process. The end of the gate electrode layer is tapered. This is preferable because it improves the coverage of the gate insulating layer to be laminated thereon. The mask may be formed by an ink-jet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0237] There is no significant limitation on the substrate that can be used for the substrate 394 having an insulating surface, but at least In either case, it is necessary for the barium phosphate to have sufficient heat resistance to withstand subsequent heat treatment. A glass substrate such as borosilicate glass or aluminoborosilicate glass can be used.

[0238] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point will be 730°C or higher. The glass substrate may be made of, for example, aluminosilicate glass, aluminum Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. In general, by including more barium oxide (BaO) than boron oxide, A more practical heat-resistant glass can be obtained. For this reason, a glass base containing more BaO than B2O3 is used. It is preferable to use a plate

[0239] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, a substrate made of an insulating material may be used. Alternatively, a crystallized glass substrate or the like may be used. Furthermore, a plastic substrate or the like can also be used as appropriate.

[0240] An insulating film serving as a base film may be provided between the substrate 394 and the gate electrode layer 391. , which has the function of preventing the diffusion of impurity elements from the substrate 394, and the silicon nitride film, silicon oxide film, The insulating film is made of one or more films selected from a silicon film, a silicon nitride oxide film, and a silicon oxynitride film. The insulating film can be formed by a laminated structure.

[0241] The material of the gate electrode layer 391 is molybdenum, titanium, chromium, tantalum, or tungsten. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials containing these as their main components The insulating film 10 can be formed as a single layer or a stacked layer using an alloy material.

[0242] For example, the gate electrode layer 391 may have a two-layer laminate structure, such as a molybdenum layer on an aluminum layer. Two-layer structure with a molybdenum layer on a copper layer, two-layer structure with a nitride layer on a copper layer Two-layer structure consisting of a titanium nitride layer or a tantalum nitride layer, a titanium nitride layer and a molybdenum layer or a two-layer structure in which a tungsten nitride layer and a tungsten layer are laminated. The three-layer laminate structure is preferably a tungsten layer or a tungsten nitride layer. an aluminum-silicon alloy layer or an aluminum-titanium alloy layer, and titanium nitride It is preferable to use a conductive film having light-transmitting properties as a gate electrode. A light-transmitting conductive oxide film can also be formed. Examples of such things include:

[0243] Next, a gate insulating layer 397 is formed over the gate electrode layer 391 .

[0244] The gate insulating layer 397 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer The gate insulating layer 397 can be formed as a single layer or a stacked layer. In order to prevent a large amount of the oxide from being contained, the gate insulating layer 397 is formed by sputtering. When forming a silicon oxide film by sputtering, it is preferable to A silicon target or a quartz target is used as the sputtering target, and oxygen is used as the sputtering gas. A mixed gas of oxygen and argon or oxygen and argon is used.

[0245] The gate insulating layer 397 is formed by stacking a silicon nitride layer and a silicon oxide layer from the gate electrode layer 391 side. For example, a layered structure can be formed by sputtering as the first gate insulating layer. A silicon nitride layer (SiNy (y>0)) with a thickness of 50 nm to 200 nm is formed. On the first gate insulating layer, an oxide film having a thickness of 5 nm to 300 nm is formed as a second gate insulating layer. A silicon dioxide layer (SiOx (x>0)) is deposited to form a gate insulating layer with a thickness of 100 nm. .

[0246] In addition, the gate insulating layer 397 and the oxide semiconductor film 393 contain hydrogen, a hydroxyl group, and moisture as much as possible. In order to prevent this, a gate electrode is placed in the preheating chamber of the sputtering equipment as a pretreatment for film formation. A substrate 394 on which a gate electrode layer 391 is formed, or a substrate on which up to a gate insulating layer 397 is formed The plate 394 is preheated, and impurities such as hydrogen and moisture adsorbed on the substrate 394 are desorbed and exhausted. The preheating temperature is preferably 100°C or higher and 400°C or lower. The temperature is between 150 and 300°C. The exhaust means installed in the preheating chamber is a cryopump. It is preferable that the preheating step is omitted. Before the oxide insulating layer 396 is formed, the source electrode layer 395a and the drain electrode layer 395b are The same may be done to the formed substrate 394.

[0247] Next, an oxide semiconductor film 39 with a thickness of 2 nm to 200 nm is formed over the gate insulating layer 397. 3 is formed (see FIG. 10(A)).

[0248] Note that before the oxide semiconductor film 393 is formed by a sputtering method, argon gas is introduced. The silicon dioxide is introduced to generate plasma and reverse sputtering is performed, and the silicon dioxide adheres to the surface of the gate insulating layer 397. It is preferable to remove any dust that may be present.

[0249] The oxide semiconductor film 393 is formed by a sputtering method. n-Ga-Zn-O based film, In-Sn-Zn-O based, In-Al-Zn-O based, Sn-G a-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system , Sn-Zn-O, Al-Zn-O, In-O, Sn-O, and Zn-O oxides In this embodiment, the oxide semiconductor film 393 is an In—Ga—Zn—O based semiconductor film. The film is formed by a sputtering method using a target for forming an oxide semiconductor film. The semiconductor film 393 is heated under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. It is formed by sputtering in a mixed atmosphere of silicon (typically argon) and oxygen. In addition, when the sputtering method is used, SiO2 is preferably contained in an amount of 2% by weight or more and 10% by weight or less. % or less may be used for film formation.

[0250] Zinc oxide was used as a target for forming the oxide semiconductor film 393 by a sputtering method. A metal oxide target containing the metal oxide as the main component can be used. Another example of the target is a target for forming an oxide semiconductor film containing In, Ga, and Zn ( The composition ratio was In2O3:Ga2O3:ZnO=1:1:1 [mol%], In:Ga Zn=1:1:0.5 [atom %]) can be used. In, Ga, and As a target for forming oxide semiconductor films containing In and Zn, In:Ga:Zn=1:1:1 [a or a target having a composition ratio of In:Ga:Zn=1:1:2 [atom%] The filling rate of the oxide semiconductor film formation target is 90% or more, and % or less, preferably 95% to 99.9%. By using the get, the deposited oxide semiconductor film becomes a dense film.

[0251] The substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate is heated to room temperature or a temperature below 400°C. Then, the remaining moisture in the processing chamber is removed, and the sputtering gas from which hydrogen and moisture have been removed is heated. A metal oxide is used as a target to deposit an oxide semiconductor film 393 on a substrate 394. To remove residual moisture in the processing chamber, an adsorption type vacuum pump is used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferable. As an exhaust means, a turbo pump with a cold trap is preferably used. The deposition chamber evacuated using a cryopump may be evacuated by, for example, hydrogen atoms. , compounds containing hydrogen atoms such as water (H2O) (and more preferably compounds containing carbon atoms), etc. Since the gas is exhausted, the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber is reduced. can.

[0252] As an example of the film formation conditions, the distance between the substrate and the target is 60 mm, the pressure is 0.6 Pa, DC power supply 0.5kW, oxygen (oxygen flow rate 100%) atmosphere conditions are applied. Furthermore, if a pulsed direct current (DC) power supply is used, the amount of powdery material generated during film formation can be reduced. The oxide semiconductor film is preferably 5 nm to 30 nm thick. The appropriate thickness varies depending on the oxide semiconductor material used. The thickness can be selected appropriately.

[0253] Next, the oxide semiconductor film is subjected to a second photolithography process to form an island-shaped oxide semiconductor layer 3 10B). In addition, an island-shaped oxide semiconductor layer 399 is formed. A resist mask for this purpose may be formed by an ink-jet method. When the film is formed by the jet method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0254] In addition, when the oxide semiconductor layer 399 is formed, a contact hole is formed in the gate insulating layer 397. It is possible.

[0255] Note that the etching of the oxide semiconductor film 393 here can be performed by dry etching or wet etching. Alternatively, either etching or both may be used.

[0256] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0257] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and rare gases such as helium (He) and argon (Ar) Additive gases, etc. can be used.

[0258] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0259] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0260] In addition, after wet etching, the etching solution is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium and the like contained in the oxide semiconductor layer may be recycled from the waste liquid after etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0261] The etching conditions (etching) are adjusted to suit the material so that the desired processing shape can be etched. The etching conditions (liquid, etching time, temperature, etc.) are adjusted appropriately.

[0262] Note that reverse sputtering is performed before forming a conductive film in the next step, and the oxide semiconductor layer 399 and the gate electrode 396 are formed. It is preferable to remove resist residues and the like adhering to the surface of the insulating layer 397.

[0263] Next, a conductive film is formed over the gate insulating layer 397 and the oxide semiconductor layer 399. The conductive film can be formed by a tarpaulin method or a vacuum deposition method. Elements selected from r, Cu, Ta, Ti, Mo, and W, or elements containing the above elements The alloys and the alloy films of the above elements are also examples. a material selected from one or more of tungsten, zirconium, beryllium, and thorium; The conductive film may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, or a titanium film laminated on an aluminum film, Two-layer structure: Ti film, aluminum film on top of the Ti film, and T film on top of that. In addition, titanium (Ti), tantalum ( Ta), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neodymium) , Sc (Scandium), or a film made by combining a single or multiple elements, an alloy film, or a film made by combining a single or multiple elements. Alternatively, a nitride film may be used.

[0264] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. After forming the source electrode layer 395a and the drain electrode layer 395b by etching, a resist The mask is removed (see FIG. 10(C)).

[0265] The third photolithography process involves exposure to ultraviolet light or KrF laser light when forming a resist mask. The source electrode layer is formed on the oxide semiconductor layer 399. The width of the gap between the end of the drain electrode layer and the lower end of the drain electrode layer determines the channel width of the thin film transistor to be formed later. The channel length L is determined. When performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from 10 nm to several tens of nm. t) is used to perform exposure when forming a resist mask in the third photolithography process. UV exposure has high resolution and a large depth of focus. The channel length L of the transistor can be set to 10 nm or more and 1000 nm or less. The operating speed can be increased, and the off-current value is extremely small, so power consumption can also be reduced. This can be done.

[0266] Note that the conductive film was etched so that the oxide semiconductor layer 399 was not removed. The material and etching conditions are adjusted appropriately.

[0267] Note that in the third photolithography step, only a part of the oxide semiconductor layer 399 is etched. In some cases, the source electrode layer 3 is formed as an oxide semiconductor layer having a groove (a recess). 95a, a resist mask for forming the drain electrode layer 395b is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0268] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The resist mask is formed by a multi-tone mask, which is an exposure mask that allows the incident light to have multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0269] Plasma treatment with gases such as N2O, N2, or Ar removes exposed oxide semiconductor. It is also possible to remove adsorbed water and the like attached to the surface of the conductor layer. Also, a mixed gas of oxygen and argon is used. The plasma treatment may be carried out using

[0270] When plasma treatment is performed, a protective film that is in contact with a part of the oxide semiconductor layer is formed without being exposed to the air. An oxide insulating layer 396 is formed as an oxide insulating layer to serve as an insulating film (see FIG. 10D). In this embodiment, the oxide semiconductor layer 399 is formed between the source electrode layer 395a and the drain electrode layer 395b. In a region where the oxide semiconductor layer 399 does not overlap with the oxide insulating layer 396, It is formed so that

[0271] In this embodiment, the oxide insulating layer 396 includes an island-shaped oxide semiconductor layer 399, a source electrode The substrate 394 on which the electrode layer 395a and the drain electrode layer 395b have been formed is heated at room temperature or below 100°C. The sputtering gas is heated to a temperature of 1000 K and contains high-purity oxygen from which hydrogen and moisture have been removed. A silicon oxide layer containing defects is formed using a silicon semiconductor target.

[0272] For example, the purity of the sputtering gas is 6N, and a boron-doped silicon target is The distance between the substrate and the target (TS distance) was 89 mm, pressure 0.4 Pa, direct current (DC) power supply 6 kW, oxygen (oxygen flow rate 100%) A silicon oxide layer is formed by pulse DC sputtering in a 300 MPa atmosphere. nm. Instead of a silicon target, quartz (preferably synthetic quartz) is used to form a silicon oxide film. It can be used as a target for forming a silicon film. The gas used is oxygen or a mixture of oxygen and argon.

[0273] In this case, the oxide insulating layer 396 is formed while removing residual moisture in the treatment chamber. It is preferable that the oxide semiconductor layer 399 and the oxide insulating layer 396 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed.

[0274] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., which contain hydrogen atoms, The concentration of impurities contained in 396 can be reduced.

[0275] Note that as the oxide insulating layer 396, a silicon oxynitride layer or an oxide An aluminum layer, an aluminum oxynitride layer, or the like can also be used.

[0276] Further, the oxide insulating layer 396 and the oxide semiconductor layer 399 are heated at 100° C. to 40° C. in a state where the oxide insulating layer 396 and the oxide semiconductor layer 399 are in contact with each other. Heat treatment may be performed at 0° C. The oxide insulating layer 396 in this embodiment has many defects. Therefore, the heat treatment reduces hydrogen, moisture, and hydroxyl groups contained in the oxide semiconductor layer 399. Alternatively, impurities such as hydride are diffused into the oxide insulating layer 396 to form a layer in the oxide semiconductor layer 399. The impurities contained therein can be further reduced.

[0277] Through the above steps, the oxide semiconductor layer 39 in which the concentration of hydrogen, moisture, hydroxyl groups, or hydrides is reduced is formed. 2, a thin film transistor 390 having the same structure as in FIG. 10(E) can be formed.

[0278] When forming the oxide semiconductor film as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. The oxide semiconductor film can be stabilized.

[0279] A protective insulating layer may be provided over the oxide insulating layer. In this embodiment, the protective insulating layer 398 is formed by an oxide insulating film. The protective insulating layer 398 is formed on the oxide insulating layer 396. The protective insulating layer 398 may be a silicon nitride film, a nitride oxide film, or the like. A silicon film, an aluminum nitride film, an aluminum nitride oxide film, or the like is used.

[0280] The substrate 394 on which the oxide insulating layer 396 has been formed is heated at 100°C to 4 Sputtering gas containing high-purity nitrogen heated to a temperature of 00°C and from which hydrogen and moisture have been removed. A silicon nitride film is formed by introducing a silicon semiconductor target. Even if the oxide insulating layer 396 is removed, the protective insulating layer 39 It is preferable to deposit 8.

[0281] When forming the protective insulating layer 398, the temperature is set to 100° C. to 400° C. during the formation of the protective insulating layer 398. By heating the plate 394, hydrogen or moisture contained in the oxide semiconductor layer is oxidized to form an oxide insulating film. In this case, a heat treatment is performed after the oxide insulating layer 396 is formed. It doesn't have to be.

[0282] A silicon oxide layer is formed as the oxide insulating layer 396, and a silicon nitride layer is formed as the protective insulating layer 398. When stacking silicon layers, the silicon oxide layer and silicon nitride layer are processed in the same processing chamber using a common silicon nitride layer. The film can be formed using a silicon target. First, an etching gas containing oxygen is introduced. Then, a silicon oxide layer is formed using a silicon target installed in the processing chamber, and then The etching gas was changed to a nitrogen-containing etching gas and the same silicon target was used. The silicon oxide layer and the silicon nitride layer are formed in succession without being exposed to the atmosphere. Since the silicon oxide layer can be formed continuously, impurities such as hydrogen and moisture are not adsorbed on the surface of the silicon oxide layer. In this case, a silicon oxide layer is used as the oxide insulating layer 396. After that, a silicon nitride layer was stacked as a protective insulating layer 398. Heat treatment (temperature 100°C or higher) to diffuse the hydrogen or moisture contained in the oxide insulating layer into the oxide insulating layer. It is recommended to perform heating at 400℃.

[0283] After the protective insulation layer is formed, it is further heated in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature. Alternatively, the temperature may be increased from room temperature to a heating temperature of 100°C or more and 200°C or less, and then reduced from the heating temperature to room temperature. This heat treatment may be repeated several times to form an oxide insulating layer. Heat treatment under reduced pressure can shorten the heating time. By this heat treatment, a normally-off thin film transistor can be obtained. This improves the reliability of the thin film transistor.

[0284] In addition, when an oxide semiconductor layer serving as a channel formation region is formed over a gate insulating layer, a reaction By removing residual moisture in the atmosphere, the concentrations of hydrogen and hydride in the oxide semiconductor layer are reduced. can be reduced.

[0285] The above process can be applied to LCD panels, electroluminescent display panels, and electronic ink displays. Used in the manufacture of backplanes (substrates on which thin film transistors are formed) for display devices The above process is carried out at a temperature of 400°C or less, so the thickness is 1 mm or less. It can also be applied to manufacturing processes using glass substrates with sides exceeding 1 m. All processes can be carried out at temperatures below 00°C, making it ideal for manufacturing display panels. This means that you don't have to consume a lot of energy.

[0286] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0287] As described above, a thin film transistor using an oxide semiconductor layer has stable electrical characteristics. Therefore, a highly reliable thin film transistor can be provided.

[0288] (Sixth embodiment) This embodiment relates to a transistor constituting a logic circuit and a semiconductor device disclosed in this specification. Other examples of applicable thin film transistors are shown below.

[0289] One embodiment of the thin film transistor and the manufacturing method of the thin film transistor of this embodiment will be described with reference to FIG. and explain.

[0290] 11A to 11E show examples of cross-sectional structures of thin film transistors. The thin film transistor 310 shown in (E) is a type of bottom gate structure, and is an inverted staggered thin film transistor. Also called a transistor.

[0291] The thin film transistor 310 is described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor with a multi-gate structure having multiple channel forming regions may be used. A data can also be formed.

[0292] 11(A) to 11(E), a thin film transistor 410 is fabricated on the substrate 300. The process will be explained.

[0293] First, a conductive film is formed on a substrate 300 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 311 is formed by a process. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0294] There is no significant limitation on the substrate that can be used for the substrate 300 having an insulating surface, but at least In either case, it is necessary for the barium phosphate to have sufficient heat resistance to withstand subsequent heat treatment. A glass substrate such as borosilicate glass or aluminoborosilicate glass can be used.

[0295] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point will be 730°C or higher. The glass substrate may be made of, for example, aluminosilicate glass, aluminum Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. In addition, by containing more barium oxide (BaO) than boron oxide (B2O3), Therefore, glass containing more BaO than B2O3 is preferred. It is preferable to use a glass substrate.

[0296] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, a substrate made of an insulating material may be used. Alternatively, a crystallized glass substrate or the like may be used.

[0297] An insulating film serving as a base film may be provided between the substrate 300 and the gate electrode layer 311. , which has the function of preventing the diffusion of impurity elements from the substrate 300, and is a silicon nitride film, a silicon oxide film, A laminated structure of one or more films selected from a silicon nitride oxide film or a silicon oxynitride film It can be formed.

[0298] The material of the gate electrode layer 311 is selected from the group consisting of molybdenum, titanium, chromium, tantalum, and tungsten. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials containing these as their main components The insulating film 10 can be formed as a single layer or a stacked layer using an alloy material.

[0299] For example, the gate electrode layer 311 may have a two-layer laminate structure, such as a molybdenum layer on an aluminum layer. Two-layer laminated structure with a molybdenum layer on a copper layer, two-layer laminated structure with a molybdenum layer on a copper layer, copper layer A two-layer laminate structure with a titanium nitride layer or tantalum nitride layer laminated on top, a titanium nitride layer and a metal layer Two-layer laminated structure with a tungsten nitride layer and a tungsten layer, or a tungsten nitride layer and a tungsten layer A two-layer laminate structure is preferable. A three-layer laminate structure is preferably a tungsten layer or a nitride layer. a tungsten nitride layer, an aluminum-silicon alloy layer or an aluminum-titanium alloy layer; It is preferable to use a laminated layer in which a titanium nitride layer or a titanium layer is laminated.

[0300] Next, the gate insulating layer 302 is formed on the gate electrode layer 311 .

[0301] The gate insulating layer 302 is a silicon oxide layer formed by using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer in a single layer or For example, SiH4, oxygen, and nitrogen are used as the deposition gas. A silicon oxynitride layer may be formed by plasma CVD. The thickness is 100 nm to 500 nm. In the case of a laminate, for example, the thickness is 50 nm to 2 a first gate insulating layer having a thickness of 500 nm or less and a second gate insulating layer having a thickness of 5 nm or more and 300 nm or less on the first gate insulating layer; The second gate insulating layer is laminated to a thickness of 1 m or less.

[0302] In this embodiment, the gate insulating layer 302 is formed by plasma CVD to a thickness of 100 nm or more. A bottom silicon oxynitride layer is formed.

[0303] Next, an oxide semiconductor film 33 having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 302. Form 0.

[0304] Before the oxide semiconductor film 330 was formed by a sputtering method, argon gas was introduced. The reverse sputtering is performed by introducing the silicon dioxide into the gate insulating layer 302 to generate plasma. It is preferable to remove any dust particles that may be present in the atmosphere. etc. may also be used.

[0305] The oxide semiconductor film 330 may be an In-Ga-Zn-O based, In-Sn-Zn-O based, or In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn- An O-based or Zn—O-based oxide semiconductor film is used. In this embodiment, the oxide semiconductor film 330 The film was deposited by sputtering using an In-Ga-Zn-O oxide semiconductor target. The cross-sectional view at this stage corresponds to FIG. 11A. The method is carried out under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) atmosphere. The film can be formed by sputtering in an atmosphere of argon and oxygen. When a sputtering method is used, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used. The film may be formed using a catalyst.

[0306] The oxide semiconductor film 330 is formed by sputtering using zinc oxide as a target. A metal oxide target containing the metal oxide as the main component can be used. Another example of the target is a target for forming an oxide semiconductor film containing In, Ga, and Zn ( The composition ratio was In2O3:Ga2O3:ZnO=1:1:1 [mol%], In:Ga Zn=1:1:0.5 [atom %]) can be used. In, Ga, and As a target for forming oxide semiconductor films containing In and Zn, In:Ga:Zn=1:1:1 [a or a target having a composition ratio of In:Ga:Zn=1:1:2 [atom%] The filling rate of the oxide semiconductor film formation target is 90% or more, and % or less, preferably 95% to 99.9%. By using the get, the deposited oxide semiconductor film becomes a dense film.

[0307] The oxide semiconductor film 330 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or is a high-purity gas in which impurities such as hydrides have been removed to concentrations of ppm or ppb. It is preferable to use

[0308] The substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate temperature is preferably maintained at 100°C or more and 600°C or less. The temperature is preferably 200°C or higher and 400°C or lower. The concentration of impurities contained in the sputtered oxide semiconductor film can be reduced. Damage caused by heating is reduced. The removed sputtering gas is introduced, and metal oxide is used as a target to deposit on the substrate 300. The oxide semiconductor film 330 is formed. In order to remove residual moisture in the processing chamber, an adsorption type evaporator is used. It is preferable to use an air pump. For example, a cryopump, an ion pump, or a titanium sub-pump. It is preferable to use a displacement pump. A cold trap may be added. is, for example, a hydrogen atom, a compound containing a hydrogen atom such as water (H2O) (more preferably a carbon atom) Since the exhaust gas contains oxygen, the oxide semiconductor film formed in the deposition chamber is This can reduce the concentration of impurities.

[0309] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, if a pulsed direct current (DC) power supply is used, the amount of powdery material generated during film formation can be reduced. The oxide semiconductor film is preferably 5 nm to 30 nm thick. The appropriate thickness varies depending on the oxide semiconductor material used. The thickness can be selected appropriately.

[0310] Next, the oxide semiconductor film 330 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. In addition, a resist mask for forming an island-shaped oxide semiconductor layer is applied to the substrate. If the resist mask is formed by the ink jet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0311] Next, the oxide semiconductor layer is subjected to first heat treatment. The conductor layer can be dehydrated or dehydrogenated. The temperature of the first heat treatment is 400° C. or higher. The temperature is set to 750° C. or lower, preferably 400° C. or higher but lower than the distortion point of the substrate. The substrate was placed in an electric furnace, which is one of the devices, and the oxide semiconductor layer was heated to 450°C in a nitrogen atmosphere. After the heat treatment at 1000 K for 1 hour, the oxide semiconductor layer was cooled without being exposed to the air. Re-entry of hydrogen is prevented, and an oxide semiconductor layer 331 is obtained (see FIG. 11B).

[0312] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat radiation from a heat source such as a resistance heating element. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure water A device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. Inert gases such as rare gases like argon or nitrogen that do not react with the material to be treated by heat treatment. The body is used.

[0313] For example, as the first heat treatment, a base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate is moved and placed in the oven, heated for several minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. GRTA can be used to heat the food at high temperatures in a short time. become.

[0314] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, or the like. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. or 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably It is preferable to keep the concentration below 0.1 ppm.

[0315] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized and become microcrystalline. For example, a microcrystalline film with a crystallinity of 90% or more, or 80% or more, may be formed. In some cases, the oxide semiconductor film becomes crystalline. Depending on the material of the oxide layer, the oxide semiconductor film may be an amorphous oxide semiconductor film that does not contain crystalline components. In addition, the amorphous oxide semiconductor contains microcrystalline portions (grain size of 1 nm or more and 20 nm or less (typically In some cases, the oxide semiconductor film may contain a mixture of oxide semiconductor layers having thicknesses of 2 nm to 4 nm.

[0316] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. The semiconductor film 330 can also be subjected to the first heat treatment. In that case, after the first heat treatment, The substrate is removed and subjected to a photolithography process.

[0317] The heat treatment that has the effect of dehydrating and dehydrogenating the oxide semiconductor layer is performed after the oxide semiconductor layer formation. After the formation of the oxide semiconductor layer, a source electrode layer and a drain electrode layer are stacked on the oxide semiconductor layer. The step may be performed either after forming a protective insulating film on the drain electrode or after forming a protective insulating film on the drain electrode.

[0318] In addition, when a contact hole is formed in the gate insulating layer 302, the process is performed using an oxide semiconductor. This may be done before or after the membrane 330 has been subjected to a dehydration or dehydrogenation treatment.

[0319] Note that the etching of the oxide semiconductor film here is not limited to wet etching, but may be dry etching. Etching may also be used.

[0320] The etching conditions (etching) are adjusted to suit the material so that the desired processing shape can be etched. The etching conditions (liquid, etching time, temperature, etc.) are adjusted appropriately.

[0321] Next, a conductive film is formed over the gate insulating layer 302 and the oxide semiconductor layer 331. The conductive film can be formed by sputtering or vacuum deposition. Elements selected from r, Cu, Ta, Ti, Mo, and W, or elements containing the above elements The alloys and the alloy films of the above elements are also examples. a material selected from one or more of tungsten, zirconium, beryllium, and thorium; The conductive film may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, or a titanium film laminated on an aluminum film, Two-layer structure: Ti film, aluminum film on top of the Ti film, and T film on top of that. In addition, titanium (Ti), tantalum ( Ta), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neodymium) , Sc (Scandium), or a film made by combining a single or multiple elements, an alloy film, or a film made by combining a single or multiple elements. Alternatively, a nitride film may be used.

[0322] When a heat treatment is performed after the conductive film is formed, the conductive film must have heat resistance to withstand this heat treatment. It is preferable that

[0323] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. After forming the source electrode layer 315a and the drain electrode layer 315b by etching, a resist The mask is removed (see FIG. 11(C)).

[0324] The third photolithography process involves exposure to ultraviolet light or KrF laser light when forming a resist mask. The source electrode layer adjacent to each other on the oxide semiconductor layer 331 is formed by laser light or ArF laser light. The width of the gap between the end of the drain electrode layer and the lower end of the drain electrode layer determines the channel width of the thin film transistor to be formed later. The channel length L is determined. When performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from 10 nm to several tens of nm. t) is used to perform exposure when forming a resist mask in the third photolithography process. UV exposure has high resolution and a large depth of focus. The channel length L of the transistor can be set to 10 nm or more and 1000 nm or less. The operating speed can be increased, and the off-current value is extremely small, so power consumption can also be reduced. This can be done.

[0325] Note that the conductive film was etched so that the oxide semiconductor layer 331 was not removed. The material and etching conditions are adjusted appropriately.

[0326] Note that in the third photolithography step, only a part of the oxide semiconductor layer 331 is etched. In some cases, the source electrode layer 3 is formed as an oxide semiconductor layer having a groove (a recess). 15a, a resist mask for forming the drain electrode layer 315b is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0327] Further, an oxide conductive layer is formed between the oxide semiconductor layer and the source electrode layer and the drain electrode layer. The oxide conductive layer and the metal layer for forming the source and drain electrode layers may be The oxide conductive layer can function as a source region and a drain region.

[0328] The oxide conductive layer is formed as a source region and a drain region by forming an oxide semiconductor layer and a source electrode layer. By providing the source and drain electrode layers between the source and drain regions, the resistance of the source and drain regions can be reduced. This allows the transistor to operate at high speed.

[0329] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The resist mask is formed by a multi-tone mask, which is an exposure mask that allows the incident light to have multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0330] Next, a plasma treatment is performed using a gas such as N2O, N2, or Ar. The treatment removes adsorbed water and the like that adheres to the exposed surface of the oxide semiconductor layer. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0331] After the plasma treatment, the protective insulating film in contact with a part of the oxide semiconductor layer was removed without being exposed to the air. An oxide insulating layer 316 is formed as an insulating film.

[0332] The oxide insulating layer 316 has a thickness of at least 1 nm and is formed by an oxide method such as a sputtering method. The insulating layer 316 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed in. When hydrogen is contained in the oxide insulating layer 316, the hydrogen can penetrate into the oxide semiconductor layer or The oxygen in the oxide semiconductor layer is extracted by hydrogen, and the back channel of the oxide semiconductor layer is This may cause the transistor to become N-type (low resistance), resulting in the formation of a parasitic channel. The oxide insulating layer 316 is formed using a method that does not use hydrogen so as to contain as little hydrogen as possible. It is important that there is no

[0333] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering as the oxide insulating layer 316. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering using a rare gas ( Typically, under an atmosphere of argon, under an oxygen atmosphere, or under a rare gas atmosphere (typically, argon) and The process can be carried out in an oxygen-mixed atmosphere. For example, a silicon target can be used to oxidize oxygen, A silicon oxide film can be formed by sputtering in a nitrogen atmosphere. The oxide insulating layer formed in contact with the oxide semiconductor layer becomes depleted and becomes N-type, i.e., has low resistance. The edge layer 316 contains water, hydrogen ions, OH - It does not contain impurities such as An inorganic insulating film is used to block the An aluminum nitride film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0334] In this case, the oxide insulating layer 316 is formed while removing residual moisture in the treatment chamber. It is preferable that the oxide semiconductor layer 331 and the oxide insulating layer 316 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed.

[0335] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., which contain hydrogen atoms, The concentration of impurities contained in 316 can be reduced.

[0336] The sputtering gas used in forming the oxide insulating layer 316 is hydrogen, water, a hydroxyl group, or a water High-purity gas is used, in which impurities such as chlorine compounds have been removed to concentrations of ppm or ppb. It is preferable that

[0337] Next, a second heat treatment (preferably 20 0°C to 400°C (for example, 250°C to 350°C). The second heat treatment is performed at 250° C. for 1 hour under a temperature of 100° C. The oxide semiconductor A part of the layer (channel formation region) is heated in a state where the part is in contact with the oxide insulating layer 316 .

[0338] Through the above steps, the oxide semiconductor layer after deposition is dehydrated or dehydrogenated. At the same time as the heat treatment for the oxide semiconductor layer is performed, the oxide semiconductor layer becomes oxygen-deficient and the resistance is reduced, that is, After converting the oxide semiconductor layer to N-type, an oxide insulating layer is formed in contact with the oxide semiconductor layer. As a result, a portion of the compound semiconductor layer is selectively made to have an excess of oxygen. The resulting channel forming region 313 is an I-type. 3, and the high-resistance source region 314 overlapping the source electrode layer 315a. a, and the carrier concentration is higher than at least the channel formation region 363, and the drain electrode layer The high-resistance drain region 314b overlapping the drain region 315b is formed in a self-aligned manner. Thus, the thin film transistor 310 is formed (see FIG. 11(D)).

[0339] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained at 100°C or higher and 200°C or lower. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. By performing this heat treatment, the heating time can be shortened. Hydrogen is taken into the oxide insulating layer to obtain a normally-off thin film transistor. Therefore, the reliability of the thin film transistor can be improved. When a silicon oxide layer containing a large amount of silicon is used, the silicon dioxide contained in the oxide semiconductor layer is reduced by this heat treatment. Impurities such as hydrogen, moisture, a hydroxyl group, or hydride are diffused into the oxide insulating layer, and an oxide semiconductor This has the effect of further reducing the impurities contained in the layer.

[0340] Note that the oxide semiconductor layer overlapping with the drain electrode layer 315b (and the source electrode layer 315a) forming a high-resistance drain region 314b (and a high-resistance source region 314a) in This improves the reliability of the thin film transistor. By forming the drain electrode layer 315b, the high-resistance drain region 314b is 14b, a structure in which the conductivity can be changed stepwise from the first region to the channel forming region 313. Therefore, the drain electrode layer 315b can be connected to a high power supply potential VDD. When the transistor is connected to a wiring for operation, a gate electrode layer 311 and a drain electrode layer 315b are Even when voltage is applied, the high-resistance drain region acts as a buffer, making it difficult for localized electric field concentration to occur. In this case, the withstand voltage of the transistor can be improved.

[0341] The high-resistance source region or the high-resistance drain region in the oxide semiconductor layer is preferably formed of an oxide semiconductor. When the oxide layer is thin, 15 nm or less, it is formed throughout the entire thickness direction. When the thickness of the conductor layer is thicker, between 30 nm and 50 nm, a part of the oxide semiconductor layer, The resistance of the region in contact with the source electrode layer or the drain electrode layer and its vicinity is reduced, forming a high-resistance source region. Alternatively, a high-resistance drain region is formed, and the region of the oxide semiconductor layer close to the gate insulating film is It can also be type I.

[0342] A protective insulating layer may be further formed on the oxide insulating layer 316. For example, RF sputtering The RF sputtering method is suitable for mass production, so it is suitable for protection. This is a preferred method for forming an insulating layer. The protective insulating layer is formed by absorbing moisture, hydrogen ions, and OH - Impurities such as It does not contain silicon nitride and uses an inorganic insulating film that blocks these substances from entering from the outside. Silicon film, aluminum nitride film, silicon nitride oxide film, aluminum nitride oxide film, etc. In this embodiment, the protective insulating layer 303 is formed using a silicon nitride film. (See FIG. 11(E)).

[0343] In this embodiment, the protective insulating layer 303 is formed up to the oxide insulating layer 316. The formed substrate 300 is heated to a temperature of 100°C to 400°C to remove hydrogen and moisture. A protective insulating layer is formed by introducing a sputtering gas containing high-purity nitrogen and using a silicon target. In this case, a silicon nitride film is formed as the oxide insulating layer 316. Similarly, it is preferable to form the protective insulating layer 303 while removing residual moisture in the treatment chamber.

[0344] Note that a planarization insulating layer for planarization may be provided over the protective insulating layer 303.

[0345] In addition, an oxide film is formed on the protective insulating layer 303 (on the planarizing insulating layer if a planarizing insulating layer is provided). A conductive layer may be provided to overlap the compound semiconductor layer. The second gate electrode layer may be the same as or different from the gate electrode layer 311. In addition, even if the potential of the conductive layer is a fixed potential such as GND or 0V, good.

[0346] The conductive layer can control the electrical properties of the thin film transistor 310 .

[0347] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0348] As described above, a thin film transistor using an oxide semiconductor layer has stable electrical characteristics. Therefore, a highly reliable thin film transistor can be provided.

[0349] (Embodiment 7) This embodiment relates to a transistor constituting a logic circuit and a semiconductor device disclosed in this specification. Other examples of applicable thin film transistors are shown below.

[0350] One mode of the thin film transistor and the manufacturing method of the thin film transistor of this embodiment will be described with reference to FIGS. This will be used to explain.

[0351] 12A to 12D show examples of cross-sectional structures of thin film transistors. The thin film transistor 360 shown in (D) is a channel protection type (also called a channel stop type). ) and is also called an inverted staggered thin film transistor.

[0352] The thin film transistor 360 is described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor with a multi-gate structure having multiple channel forming regions may be used. A data can also be formed.

[0353] 12(A) to 12(D), a thin film transistor 360 is fabricated on a substrate 320. The process will be explained.

[0354] First, a conductive film is formed on a substrate 320 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 361 is formed by a process. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0355] The material of the gate electrode layer 361 is molybdenum, titanium, chromium, tantalum, or tungsten. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials containing these as their main components The insulating film 10 can be formed as a single layer or a stacked layer using an alloy material.

[0356] Next, the gate insulating layer 322 is formed on the gate electrode layer 361 .

[0357] In this embodiment, the gate insulating layer 322 is formed by plasma CVD to a thickness of 100 nm or more. A bottom silicon oxynitride layer is formed.

[0358] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the gate insulating layer 322. The oxide semiconductor layer is then processed into an island-shaped oxide semiconductor layer by a second photolithography process. In this case, sputtering is performed using an In-Ga-Zn-O oxide semiconductor film formation target. An oxide semiconductor film is formed by a deposition method.

[0359] In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the treatment chamber. This is preferable in order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film.

[0360] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., which contain hydrogen atoms, are exhausted. The concentration of impurities contained in the film can be reduced.

[0361] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, or hydrogen. High-purity gas is used, in which impurities such as chlorine have been removed to concentrations of ppm or ppb. It is preferable that

[0362] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the strain point of the substrate. Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and an oxide semiconductor layer is formed. After heat treatment at 450°C for 1 hour in a nitrogen atmosphere, Therefore, the oxide semiconductor layer 332 is obtained without any problem, and water or hydrogen is prevented from being recontaminated into the oxide semiconductor layer (FIG. 1). See 2(A). ).

[0363] Next, a plasma treatment is performed using a gas such as N2O, N2, or Ar. The treatment removes adsorbed water and the like that adheres to the exposed surface of the oxide semiconductor layer. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0364] Next, an oxide insulating layer was formed over the gate insulating layer 322 and the oxide semiconductor layer 332. After that, a resist mask is formed by a third photolithography process, and selective etching is performed. After forming the oxide insulating layer 366, the resist mask is removed.

[0365] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering as the oxide insulating layer 366. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering using a rare gas ( Typically, under an atmosphere of argon, under an oxygen atmosphere, or under a rare gas atmosphere (typically, argon) and The process can be carried out in an oxygen-mixed atmosphere. For example, a silicon target can be used to oxidize oxygen, A silicon oxide film can be formed by sputtering in a nitrogen atmosphere. The oxide insulating layer 366 formed in contact with the oxide semiconductor layer which has been depleted and has low resistance is , hydrogen ions, OH - It does not contain impurities such as these, and blocks them from entering from the outside. The inorganic insulating film is typically a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. An aluminum film, an aluminum oxynitride film, or the like is used.

[0366] In this case, the oxide insulating layer 366 is formed while removing residual moisture in the processing chamber. It is preferable that the oxide semiconductor layer 332 and the oxide insulating layer 366 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed.

[0367] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., which contain hydrogen atoms, The concentration of impurities contained in 366 can be reduced.

[0368] The sputtering gas used in forming the oxide insulating layer 366 is hydrogen, water, a hydroxyl group, or a water High-purity gas is used, in which impurities such as chlorine compounds have been removed to concentrations of ppm or ppb. It is preferable that

[0369] Next, a second heat treatment (preferably 20 For example, the nitrogen The second heat treatment is carried out at 250°C for 1 hour in a nitrogen atmosphere. A part of the compound semiconductor layer (channel formation region) is heated in contact with the oxide insulating layer 366. .

[0370] In this embodiment, an oxide insulating layer 366 is further provided and a part of the oxide semiconductor is exposed. The layer 332 is heat treated in an inert gas atmosphere such as nitrogen or under reduced pressure. The exposed areas of the oxide semiconductor layer 332 that are not covered by the edge layer 366 are filled with nitrogen-like When the heat treatment is performed in such an inert gas atmosphere or under reduced pressure, the resistance can be increased. For example, heat treatment is carried out in a nitrogen atmosphere at 250° C. for 1 hour.

[0371] Heat treatment in a nitrogen atmosphere on the oxide semiconductor layer 332 provided with the oxide insulating layer 366 As a result, the exposed region of the oxide semiconductor layer 332 becomes highly resistive, and the region with a different resistance (FIG. 12( In Fig. 1B, the oxide semiconductor layer 362 has a region indicated by hatched areas and white areas.

[0372] Next, a conductive film is formed on the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366. After forming the conductive film, a resist mask is formed by a fourth photolithography process. After selectively etching the silicon dioxide film to form the source electrode layer 365a and the drain electrode layer 365b, The resist mask is removed (see FIG. 12(C)).

[0373] The source electrode layer 365a and the drain electrode layer 365b may be made of Al, Cr, Cu, or T. An element selected from a, Ti, Mo, W, or an alloy containing the above elements, or In addition, metal conductive films can be used in single-layer structures or as a two-layer structure. A laminated structure of more than one layer may also be used.

[0374] Through the above steps, the oxide semiconductor layer after deposition is dehydrated or dehydrogenated. At the same time, the oxide semiconductor layer is deficient in oxygen, i.e., it is converted to N-type. By forming an oxide insulating layer in contact with the oxide semiconductor layer, a part of the oxide semiconductor layer is selectively filled with oxygen. As a result, the channel formation region 363 overlapping with the gate electrode layer 361 has an I-type At this time, the carrier concentration is higher than at least the channel forming region 363, and The high-resistance source region 364a overlapping the source electrode layer 365a and the channel forming region 363 are The high-resistance drain region 364b has a high carrier concentration and overlaps the drain electrode layer 365b. The above steps form the thin film transistor 360.

[0375] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained at 100°C or higher and 200°C or lower. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. By performing this heat treatment, the heating time can be shortened. Hydrogen is taken into the oxide insulating layer to obtain a normally-off thin film transistor. This makes it possible to improve the reliability of the thin film transistor.

[0376] Note that the oxide semiconductor layer overlapping with the drain electrode layer 365b (and the source electrode layer 365a) forming a high-resistance drain region 364b (and a high-resistance source region 364a) in This improves the reliability of the thin film transistor. By forming the drain electrode layer, the high-resistance drain region 364b, The conductivity of the channel forming region 363 can be changed stepwise. Therefore, the drain electrode layer 365b is connected to a wiring that supplies a high power supply potential VDD. When the transistor is operated continuously, a voltage is applied between the gate electrode layer 361 and the drain electrode layer 365b. Even if a large electric field is applied, the high-resistance drain region acts as a buffer to prevent localized electric field concentration. This allows for a configuration that improves the breakdown voltage of the transistor.

[0377] A protective insulating layer 3 is formed on the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride film. (See Figure 12(D)).

[0378] Note that an insulating film is further formed over the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. An oxide insulating layer may be formed and a protective insulating layer 323 may be stacked over the oxide insulating layer.

[0379] As described above, a thin film transistor using an oxide semiconductor layer has stable electrical characteristics. Therefore, a highly reliable thin film transistor can be provided.

[0380] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0381] (Embodiment 8) This embodiment relates to a transistor constituting a logic circuit and a semiconductor device disclosed in this specification. Other examples of applicable thin film transistors are shown below.

[0382] One mode of the thin film transistor and the manufacturing method of the thin film transistor of this embodiment will be described with reference to FIGS. This will be used to explain.

[0383] The thin film transistor 350 is described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor with a multi-gate structure having multiple channel forming regions may be used. A data can also be formed.

[0384] 13(A) to 13(D), a thin film transistor 350 is fabricated on a substrate 340. The process will be explained.

[0385] First, a conductive film is formed on a substrate 340 having an insulating surface, and then a first photolithography is performed. In this embodiment, the gate electrode layer 351 is formed by a process. Then, a tungsten film having a thickness of 150 nm is formed by sputtering.

[0386] Next, a gate insulating layer 342 is formed over the gate electrode layer 351. A silicon oxynitride layer having a thickness of 100 nm or less is formed as the insulating layer 342 by the plasma CVD method. Form.

[0387] Next, a conductive film is formed over the gate insulating layer 342 and is then subjected to a second photolithography process. A resist mask is formed on the conductive film, and selective etching is performed to form a source electrode layer 355. After the drain electrode layer 355b is formed, the resist mask is removed (see FIG. 13(A)). Light. ).

[0388] Next, an oxide semiconductor film 345 is formed (see FIG. 13B). -Ga-Zn-O oxide semiconductor film deposition target is used for sputtering. The oxide semiconductor film 345 is then formed by a third photolithography process. The oxide semiconductor layer is processed into a more island-shaped oxide semiconductor layer.

[0389] In this case, the oxide semiconductor film 345 is formed while removing residual moisture in the treatment chamber. In order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film 345, This is the case.

[0390] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., which contain hydrogen atoms, are exhausted. The concentration of impurities contained in the film 345 can be reduced.

[0391] The sputtering gas used in the deposition of the oxide semiconductor film 345 is hydrogen, water, a hydroxyl group, or High-purity gas in which impurities such as hydrides have been removed to concentrations of ppm or ppb. It is preferable to use

[0392] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the strain point of the substrate. Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and an oxide semiconductor layer is formed. After heat treatment at 450°C for 1 hour in a nitrogen atmosphere, Therefore, the oxide semiconductor layer 346 is obtained without any problem, and water or hydrogen is prevented from being recontaminated into the oxide semiconductor layer (FIG. 1). See 3(C). ).

[0393] In the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650°C to 700°C. After heating for several minutes, the substrate is removed from the inert gas atmosphere heated to a high temperature. GRTA can be used to heat the food at high temperatures in a short time. do.

[0394] An oxide insulating layer 356 serving as a protective insulating film in contact with the oxide semiconductor layer 346 is formed.

[0395] The oxide insulating layer 356 has a thickness of at least 1 nm and is formed by an oxide method such as a sputtering method. The insulating layer 356 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed in. When hydrogen is contained in the oxide insulating layer 356, the hydrogen can penetrate into the oxide semiconductor layer or The oxygen in the oxide semiconductor layer is extracted by hydrogen, and the back channel of the oxide semiconductor layer is This may result in the formation of a parasitic channel due to the low resistance of the transistor (N-type). The oxide insulating layer 356 is formed using a method that does not use hydrogen so as to contain as little hydrogen as possible. It is important that there is no

[0396] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering as the oxide insulating layer 356. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering using a rare gas ( Typically, under an atmosphere of argon, under an oxygen atmosphere, or under a rare gas atmosphere (typically, argon) and The process can be carried out in an oxygen-mixed atmosphere. For example, a silicon target can be used to oxidize oxygen, A silicon oxide film can be formed by sputtering in a nitrogen atmosphere. The oxide insulating layer 356 formed in contact with the oxide semiconductor layer which has been depleted and has low resistance is , hydrogen ions, OH - It does not contain impurities such as these, and blocks them from entering from the outside. The inorganic insulating film is typically a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. An aluminum film, an aluminum oxynitride film, or the like is used.

[0397] In this case, the oxide insulating layer 356 is formed while removing residual moisture in the treatment chamber. It is preferable that the oxide semiconductor layer 346 and the oxide insulating layer 356 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed.

[0398] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., which contain hydrogen atoms, The concentration of impurities contained in 356 can be reduced.

[0399] The sputtering gas used in forming the oxide insulating layer 356 is hydrogen, water, a hydroxyl group, or a water High-purity gas is used, in which impurities such as chlorine compounds have been removed to concentrations of ppm or ppb. It is preferable that

[0400] Next, a second heat treatment (preferably 20 0°C to 400°C (for example, 250°C to 350°C). The second heat treatment is performed at 250° C. for 1 hour under a temperature of 100° C. The oxide semiconductor A part of the layer (channel formation region) is heated in contact with the oxide insulating layer 356.

[0401] By going through the above process, dehydration or dehydrogenation occurs and oxygen deficiency occurs at the same time, resulting in low resistance. As a result, the oxide semiconductor film is converted into a high-resistance I-type oxide semiconductor film. This forms a conductor layer 352. Through the above steps, a thin film transistor 350 is formed.

[0402] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or more and 200°C or less. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. By performing the heat treatment, the heating time can be shortened. Hydrogen is absorbed from the conductor layer into the oxide insulating layer, resulting in a normally-off thin-film transistor. Therefore, the reliability of the thin film transistor can be improved.

[0403] A protective insulating layer may be further formed on the oxide insulating layer 356. For example, RF sputtering In this embodiment, a silicon nitride film is formed as a protective insulating layer 3. The film 43 is formed using a silicon nitride film (see FIG. 13(D)).

[0404] A planarization insulating layer for planarization may be provided over the protective insulating layer 343.

[0405] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0406] As described above, a thin film transistor using an oxide semiconductor layer has stable electrical characteristics. Therefore, a highly reliable thin film transistor can be provided.

[0407] (Embodiment 9) This embodiment relates to a transistor constituting a logic circuit and a semiconductor device disclosed in this specification. Other examples of applicable thin film transistors are shown below.

[0408] In this embodiment mode, an example in which a part of the manufacturing process of a thin film transistor is different from that in Embodiment Mode 6 is shown in FIG. 4. Figure 14 is the same as Figure 11 except for some differences in the process, so the same parts are The same reference numerals are used and detailed explanations of the same parts are omitted.

[0409] First, a gate electrode layer 381 is formed on a substrate 370, a first gate insulating layer 372a, a second In this embodiment, the gate insulating layer has a two-layer structure. The first gate insulating layer 372a is a nitride insulating layer, and the second gate insulating layer 372b is an oxide insulating layer. Use layers.

[0410] The oxide insulating layer may be a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer. As the nitride insulating layer, an aluminum oxynitride layer, or the like can be used. a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer A layer or the like can be used.

[0411] In this embodiment, a silicon nitride layer and a silicon oxide layer are stacked from the gate electrode layer 381 side. The first gate insulating layer 372a is formed by sputtering to a thickness of 50 nm. A silicon nitride layer (SiNy(y>) having a thickness of m or more and 200 nm or less (50 nm in this embodiment) 0)) is formed on the first gate insulating layer 372a, and a film is formed as a second gate insulating layer 372b on the first gate insulating layer 372a. A silicon oxide layer (SiO ) having a thickness of 5 nm to 300 nm (100 nm in this embodiment) x (x>0)) is laminated to form a gate insulating layer with a thickness of 150 nm.

[0412] Next, an oxide semiconductor film is formed, and the oxide semiconductor film is formed into island-like layers by a photolithography process. In this embodiment, the In—Ga—Zn—O-based oxide semiconductor layer is An oxide semiconductor film is formed by a sputtering method using a target.

[0413] In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the treatment chamber. This is preferable in order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film.

[0414] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., which contain hydrogen atoms, are exhausted. The concentration of impurities contained in the film can be reduced.

[0415] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, or a hydrogenated High-purity gas is used, in which impurities such as ions have been removed to concentrations of ppm or ppb. It is preferable.

[0416] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment is 400°C or higher and 750°C or lower, preferably 425°C or higher. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. The processing time is set to be longer than one hour. The substrate was placed in a furnace, and the oxide semiconductor layer was subjected to heat treatment in a nitrogen atmosphere. The oxide semiconductor layer is then heated to a temperature of 1000°C / 2500°F, and the oxide semiconductor layer is then heated to a temperature of 1000°C / 2500°F. After that, high-purity oxygen gas, high-purity N2O gas, or ultra-dry air (dew) is added to the same furnace. Cooling is performed by introducing oxygen gas or N2 It is preferable that the O gas does not contain water, hydrogen, etc. The purity of the nitrogen gas or NO gas is 6N (99.9999%) or more, preferably 7N (99 0.99999%) or more (i.e., impurity concentration in oxygen gas or N2O gas is 1 ppm or less, Preferably, it is 0.1 ppm or less.

[0417] The heat treatment device is not limited to an electric furnace, and may be, for example, a GRTA (Gas Rapid Atomic Furnace). d Thermal Anneal) equipment, LRTA (Lamp Rapid Thermal RTA (Rapid Thermal Anneal) equipment such as The LRTA device can be used with halogen lamps, metal halide lamps, Xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from lamps such as In addition, heat conduction or heat radiation from heating elements such as LRTA devices, lamps, and resistance heating elements GRTA is a device that uses high-temperature gas to heat the object to be treated. This is a method of performing heat treatment. The gas used is a rare gas such as argon or nitrogen, which is suitable for heat treatment. The RTA method uses an inert gas that does not react with the material being treated. Heat treatment may be performed at up to 750°C for several minutes.

[0418] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Heat treatment is usually performed at a temperature between 200°C and 300°C in an oxygen gas or N2O gas atmosphere. You may go.

[0419] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography process.

[0420] By going through the above steps, the entire oxide semiconductor layer is made into an oxygen-excess state, and thus a high resistance Thus, the oxide semiconductor layer 382 is entirely i-type.

[0421] Next, a conductive film is formed over the oxide semiconductor layer 382, ​​and a resist pattern is formed by a photolithography process. A mask is formed, and selective etching is performed to form the source electrode layer 385a and the drain electrode layer 385b. A layer 385b is formed, and an oxide insulating layer 386 is formed by a sputtering method.

[0422] In this case, the oxide insulating layer 386 is formed while removing residual moisture in the processing chamber. It is preferable that the oxide semiconductor layer 382 and the oxide insulating layer 386 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed.

[0423] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., which contain hydrogen atoms, The concentration of impurities contained in 386 can be reduced.

[0424] The sputtering gas used in forming the oxide insulating layer 386 is hydrogen, water, a hydroxyl group, or a water High-purity gas is used, in which impurities such as chlorine compounds have been removed to concentrations of ppm or ppb. It is preferable that

[0425] Through the above steps, the thin film transistor 380 can be formed.

[0426] Next, in order to reduce the variation in the electrical characteristics of the thin film transistors, For example, heat treatment (preferably at 150° C. or higher and lower than 350° C.) is carried out in a nitrogen gas atmosphere. For example, heat treatment may be performed at 250° C. for 1 hour in a nitrogen atmosphere.

[0427] In addition, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or more and 200°C or less. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. By performing the heat treatment, the heating time can be shortened. Hydrogen is absorbed from the conductor layer into the oxide insulating layer, resulting in a normally-off thin-film transistor. Therefore, the reliability of the thin film transistor can be improved.

[0428] The protective insulating layer 373 is formed over the oxide insulating layer 386. In this embodiment, the protective insulating layer 3 As the film 73, a silicon nitride film having a thickness of 100 nm is formed by sputtering.

[0429] The protective insulating layer 373 and the first gate insulating layer 372a made of a nitride insulating layer are resistant to moisture and water. It does not contain impurities such as hydrogen, hydrides, or hydroxides, and blocks these from entering from the outside. It has the effect of checking.

[0430] Therefore, in the manufacturing process after the protective insulating layer 373 is formed, impurities such as moisture from the outside Furthermore, the device can be completely used as a semiconductor device, for example, a liquid crystal display device. Even after the device is assembled, it can prevent the intrusion of impurities such as moisture from the outside for a long period of time. Long-term reliability can be improved.

[0431] In addition, a protective insulating layer 373 made of a nitride insulating layer and a first gate insulating layer 372a are provided between the protective insulating layer 373 and the first gate insulating layer 372a. A part of the insulating layer to be provided is removed to leave the protective insulating layer 373, the first gate insulating layer 372a, and may be in contact with each other.

[0432] Therefore, impurities such as moisture, hydrogen, hydrides, and hydroxides in the oxide semiconductor layer can be removed as much as possible. and the re-mixing of the impurities is prevented, thereby maintaining the impurity concentration in the oxide semiconductor layer at a low level. It is possible.

[0433] Further, a planarization insulating layer for planarization may be provided over the protective insulating layer 373.

[0434] Further, a conductive layer overlapping with the oxide semiconductor layer may be provided over the protective insulating layer 373. The potential may be the same as or different from the gate electrode layer 381 of the thin film transistor 380. The conductive layer may be a gate electrode layer, and may function as a second gate electrode layer. D, it may be a fixed potential of 0V.

[0435] The conductive layer can control the electrical properties of the thin film transistor 380 .

[0436] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0437] As described above, a thin film transistor using an oxide semiconductor layer has stable electrical characteristics. Therefore, a highly reliable thin film transistor can be provided.

[0438] (Embodiment 10) The appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described with reference to FIG. FIG. 15 shows thin film transistors 4010 and 4011 and a liquid crystal element 4013. 4005. This is a plan view of a panel sealed between a second substrate 4006 and the panel. 15(B) corresponds to a cross-sectional view taken along line MN in FIG. 15(A) or FIG. 15(C).

[0439] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0440] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, a wire The ear bonding method, TAB method, etc. can be used. FIG. 15(C) shows an example of mounting a signal line driver circuit 4003 by the G method, and FIG. 15(D) shows an example of mounting a signal line driver circuit 4003 by the TAB method. This is an example in which a signal line driver circuit 4003 is mounted.

[0441] In addition, the pixel portion 4002 and the scanning line driver circuit 4004 provided on the first substrate 4001 are 15B, the thin film transistor included in the pixel portion 4002 is a thin film transistor 4010 and a thin film transistor 401 included in a scanning line driver circuit 4004 The insulating layers 4041 and 4042 are formed on the thin film transistors 4010 and 4011. 42 and 4021 are provided.

[0442] The thin film transistors 4010 and 4011 may be the thin film transistors according to any one of Embodiments 2 to 9. The oxides of the thin film transistors 4010 and 4011 can be used as appropriate. The semiconductor layer has reduced hydrogen and water. This is a highly reliable thin film transistor. 0, 4011 are N-channel thin film transistors.

[0443] A channel of the oxide semiconductor layer of the thin film transistor 4011 is formed on the insulating layer 4021. The conductive layer 4040 is provided so as to overlap with the oxide semiconductor layer 401. By placing the thin film transistor at a position overlapping the channel formation region of the thin film transistor, The amount of change in the threshold voltage of the transistor 4011 can be reduced. 0 may have the same potential as the gate electrode layer of the thin film transistor 4011 or may have a different potential. The conductive layer 4040 may also function as a second gate electrode layer. The potential may be GND, 0V, or floating.

[0444] The pixel electrode layer 4030 of the liquid crystal element 4013 is The liquid crystal element 4013 is electrically connected to the source electrode layer or the drain electrode layer. The counter electrode layer 4031 is formed on the second substrate 4006. The portion where the electrode layer 4031 and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. The pixel electrode layer 4030 and the counter electrode layer 4031 are insulating layers that function as alignment films. The liquid crystal layer 4008 is connected to the insulating layer 4032 and the insulating layer 4033. It is being held.

[0445] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, or acrylic resin film A room can be used.

[0446] The spacers 4035 are columnar partition walls obtained by selectively etching an insulating film. and the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. A spherical spacer may be used. 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrodes via conductive particles disposed between the pair of substrates. The electrode layer 4031 can be electrically connected to a common potential line. It is contained in material 4005.

[0447] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 1 msec. It is optically isotropic, so alignment treatment is not required, and viewing angle dependency is small. Since there is no need to provide an alignment film, rubbing treatment is also unnecessary. This prevents electrostatic breakdown caused by the liquid crystal display device during the manufacturing process. Therefore, it is possible to improve the productivity of the liquid crystal display device. In particular, thin film transistors using oxide semiconductor layers are susceptible to static electricity. Therefore, the electrical characteristics of the capacitor may fluctuate significantly and deviate from the design range. It is possible to use a blue phase liquid crystal material in a liquid crystal display device having a thin film transistor using a layer. It is more effective.

[0448] In addition to the transmissive liquid crystal display device, the present invention can also be applied to a semi-transmissive liquid crystal display device.

[0449] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a colored layer and a display element are provided on the inner side. In this example, the polarizing plate is provided on the inner side of the substrate. In addition, the laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment, and the materials of the polarizing plate and the colored layer and The conditions may be appropriately set depending on the manufacturing process conditions. A light-shielding film that functions as a light-shielding film may be provided.

[0450] An insulating layer 4041 is provided over the thin film transistors 4011 and 4010 in contact with the oxide semiconductor layer. The insulating layer 4041 is formed using a material similar to that of the oxide insulating layer described in the above embodiment. Here, the insulating layer 4041 is formed by sputtering an oxide film. A protective insulating layer 4042 is formed on and in contact with the insulating layer 4041. The protective insulating layer 4042 is formed in a manner similar to that of the protective insulating layer 303 described in Embodiment 6. For example, a silicon nitride film can be used. An insulating layer 40 that functions as a planarizing insulating film to reduce surface irregularities caused by thin film transistors. It is configured to be covered with 21.

[0451] An insulating layer 4021 is formed as a planarization insulating film. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can also be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking multiple insulating films made of these materials, it is possible to obtain an insulating layer. 4021 may be formed.

[0452] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, a S OG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, lean printing, offset printing, etc.), doctor knife, roll coater, curtain coater A knife coater or the like can be used. By using the semiconductor device as a gate, a semiconductor device can be manufactured efficiently.

[0453] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium tin oxide (ITO), IZO (indium zinc oxide) is a mixture of indium oxide and zinc oxide (ZnO). de), conductive material made by mixing indium oxide with silicon oxide (SiO2), organic indium, Organotin, indium oxide containing tungsten oxide, indium oxide containing tungsten oxide Indium zinc oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide Alternatively, a reflective liquid crystal display device may be used. In the case where it is not necessary to have translucency or where it is necessary to have reflectivity, tungsten W, Molybdenum (Mo), Zirconium (Zr), Hafnium (Hf), Vanadium V, Niobium (Nb), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu) One or more of metals such as silver (Ag), their alloys, or their metal nitrides It can be formed using

[0454] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (also known as a conductive polymer). The conductive composition may be used to form the conductive layer. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 7.0 at a wavelength of 550 nm. It is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0% or more. It is preferable that the resistivity is 0.1 Ω·cm or less.

[0455] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or a copolymer of two or more of these.

[0456] In addition, a signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel portion 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0457] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layers of the thin film transistors 4010 and 4011. The drain electrode layer is formed of the same conductive film as the drain electrode layer.

[0458] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0459] In FIG. 15, a signal line driver circuit 4003 is formed separately and is mounted on the first substrate 4001. Although an example of mounting is shown, the present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. May be implemented.

[0460] In addition, optical components such as black matrices (light-shielding layers), polarizing components, phase difference components, and anti-reflection components For example, a circular polarization substrate and a retardation substrate may be used. Alternatively, a backlight, a sidelight, or the like may be used as the light source.

[0461] In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0462] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, resulting in image retention, or In order to improve the moving image characteristics of LCD devices, There is a driving technique called black insertion, which displays every other frame.

[0463] In addition, the response speed can be improved by increasing the normal vertical sync frequency by 1.5 times, preferably by more than 2 times. There is also a driving technology called double speed driving, which improves the image quality.

[0464] In addition, in order to improve the video characteristics of the LCD display, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode light source or multiple EL light sources. There is also a driving technology that drives each light source to light intermittently within one frame period. Three or more types of LEDs may be used, or white light emitting LEDs may be used. Since it is possible to control a large number of LEDs, the LEDs can be switched in accordance with the timing of the optical modulation of the liquid crystal layer. This driving technology can also synchronize the timing of LEDs to be turned off partially. This is especially useful when the image display has a large proportion of black areas occupying the entire screen. This can reduce power consumption.

[0465] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the past.

[0466] Furthermore, since thin film transistors are easily damaged by static electricity, etc., It is preferable that a protection circuit be provided over the same substrate as the circuit. For example, the protection circuit is preferably configured using a nonlinear element. The protection circuits are arranged between the input terminal and the signal line input terminal. By disposing the capacitors, a surge voltage is applied to the scanning lines, signal lines and capacitance bus lines due to static electricity or the like, and the image The protection circuit is designed to prevent damage to the element transistors. When a voltage is applied to the transistor, the charge is released to the common wiring. , and is configured using nonlinear elements arranged in parallel with the scanning lines. It is composed of a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, it can be formed in the same process as the thin film transistor of the pixel portion. By connecting the diode and drain terminals, it can have the same characteristics as a diode. .

[0467] The LCD module is available in TN (Twisted Nematic) mode, IP S (In-Plane-Switching) mode, FFS (Fringe Field d Switching) mode, ASM (Axially Symmetric al Ignition Micro-cell mode, OCB (Optically Comp Insulated Birefringence mode, FLC (Ferrerolector ic Liquid Crystal) mode, AFLC (AntiFerroelec tric Liquid Crystal) can be used.

[0468] As described above, the semiconductor device disclosed in the present specification is not particularly limited, and may be any of TN liquid crystal, O CB liquid crystal, STN liquid crystal, VA liquid crystal, ECB type liquid crystal, GH liquid crystal, polymer dispersed liquid crystal, Cotic liquid crystal panels can be used, among which normally black liquid crystal panels For example, it is preferable to use a transmissive liquid crystal display device that employs a vertical alignment (VA) mode. There are several types of vertical alignment modes, such as MVA (Multi-Door Alignment). main Vertical Alignment) mode, PVA(Patterne) d Vertical Alignment) mode, ASV mode, etc. can.

[0469] The present invention can also be applied to VA type liquid crystal display devices. VA type LCDs are a type of LCD panel that controls the alignment of liquid crystal molecules. This is a method in which the liquid crystal molecules are oriented perpendicular to the panel surface when no voltage is applied. In addition, a pixel is divided into several regions (subpixels), each of which is oriented in a different direction. It is called multi-domain or multi-domain design, which is designed to defeat molecules. The method can be used.

[0470] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0471] (Embodiment 11) In this embodiment mode, in the semiconductor device described in Embodiment 1, An active matrix type light emitting display is made by using a light emitting element that uses electroluminescence. An example of how to fabricate a display device is shown below.

[0472] Light-emitting elements that utilize electroluminescence are either organic or inorganic. Generally, the former is an organic EL element, and the latter is an inorganic EL element. It is called.

[0473] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. These carriers are then injected into a layer containing a light-emitting organic compound, causing a current to flow. Light is emitted by the recombination of electrons and holes. Such a light-emitting element is called a current-excited light-emitting element.

[0474] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0475] FIG. 16 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0476] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. The figure shows that an N-channel transistor using an oxide semiconductor layer as a channel formation region is used for one pixel. Here is an example of using two of them.

[0477] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, It has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode. The common potential line 6408 is electrically connected to the common potential line 6408 .

[0478] A low power supply potential is set to the second electrode (common electrode) of the light emitting element 6404. The low power supply potential is determined based on the high power supply potential set on the power supply line 6407. This is a potential that satisfies the power supply potential, and examples of low power supply potential include GND and 0V. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404 to emit light. In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and a low power supply potential are The potentials are set so that the potential difference between the potentials is equal to or greater than the threshold voltage of the light emitting element 6404. Determine.

[0479] The capacitor element 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. The gate capacitance of the driving transistor 6402 is determined by the channel formation A capacitance may be formed between the region and the gate electrode.

[0480] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is connected to The driving transistor 6402 is either fully on or off. A video signal is input, that is, the driving transistor 6402 is operated in a linear region. The driving transistor 6402 is operated in a linear region, so that the voltage of the driving transistor 6402 is higher than the voltage of the power supply line 6407. A high voltage is applied to the gate of the driving transistor 6402. The signal line 6405 is connected to A voltage equal to or greater than (power supply line voltage+Vth of the driving transistor 6402) is applied.

[0481] Furthermore, when analog grayscale driving is performed instead of digital time grayscale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 16 can be used.

[0482] When analog gradation driving is performed, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or greater than the forward voltage of the light emitting element 64 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and It should be noted that the driving transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The potential of the light emitting element is made higher than the gate potential of the capacitor 6402. A current corresponding to a video signal is passed through 6404, enabling analog gradation driving.

[0483] Note that the pixel configuration shown in Fig. 16 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0484] Next, the configuration of the light emitting element will be described with reference to FIG. 17. Here, the driving TFT is N The cross-sectional structure of a pixel will be described using the case of a liquid crystal display (LCD) as an example.

[0485] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. A top-side emission structure that emits light from the surface on the substrate side, a bottom-side emission structure that emits light from the surface on the substrate side, and a structure that emits light from the substrate side and the substrate There are also light-emitting elements with a double-sided emission structure that emit light from the opposite side of the pixel. The present invention can also be applied to light emitting devices having the following structure.

[0486] A light emitting element with a bottom emission structure will be described with reference to FIG.

[0487] The driving TFT 7011 is an N-type, and light emitted from the light emitting element 7012 is incident on the first electrode 701. 17A shows a cross-sectional view of a pixel when light is emitted to the driving TFT 7011. The light-emitting element 7 is formed on a light-transmitting conductive film 7017 electrically connected to the drain electrode layer of the light-emitting element 7. A first electrode 7013 of the OLED 012 is formed on the OLED 012. An EL layer 7014 is formed on the first electrode 7013. , and a second electrode 7015 are laminated in this order.

[0488] The light-transmitting conductive film 7017 may be formed of indium oxide containing tungsten oxide, oxide Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium-containing indium tin oxide, indium tin oxide, indium zinc oxide, oxide ketone A light-transmitting conductive film such as indium tin oxide to which indium is added can be used.

[0489] In addition, various materials can be used for the first electrode 7013 of the light-emitting element. When the electrode 7013 is used as a cathode, a material having a small work function, specifically, For example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, In addition to alloys containing these metals (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred. In FIG. 17A, the film thickness of the first electrode 7013 is set to a thickness that allows light to pass through (preferably For example, an aluminum film having a thickness of 20 nm is It is used as the first electrode 7013 .

[0490] After a light-transmitting conductive film and an aluminum film are stacked, the film is selectively etched. The light-transmitting conductive film 7017 and the first electrode 7013 may be formed by the same method. This is preferable because etching can be performed using the same mask.

[0491] The periphery of the first electrode 7013 is covered with a partition wall 7019. The partition wall 7019 is made of polyimide. organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxanes The partition wall 7019 is formed by using a photosensitive resin material in particular, and the first electrode 701 An opening is formed on the surface 3, and the side wall of the opening is an inclined surface formed with a continuous curvature. When a photosensitive resin material is used for the partition wall 7019, The step of forming a resist mask can be omitted.

[0492] The EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 is made of at least It is sufficient to include a light-emitting layer, and it may be composed of a single layer or a plurality of layers stacked. When the EL layer 7014 is made up of multiple layers, On the first electrode 7013 functioning as a It is not necessary to provide all of these layers except for the light-emitting layer. There is no.

[0493] The stacking order is not limited to the above, and the first electrode 7013 may function as an anode. Layers of hole injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are stacked on top of 7013 in this order. However, when comparing power consumption, the first electrode 7013 may function as a cathode. On the first electrode 7013, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole injection layer, and a By stacking the layers in the order of the incoming layers, it is possible to suppress the voltage rise in the drive circuit section and reduce power consumption. Therefore, it is preferable.

[0494] In addition, various materials can be used for the second electrode 7015 formed on the EL layer 7014. For example, when the second electrode 7015 is used as an anode, a material with a large work function can be used. Materials such as ZrN, Ti, W, Ni, Pt, Cr, ITO, IZO, ZnO, etc. A transparent conductive material is preferable. In addition, a shielding film 7016, for example, a film for blocking light, is provided on the second electrode 7015. A light-shielding metal, a light-reflecting metal, or the like is used. In this embodiment mode, the second electrode 7015 and An ITO film is used as the shielding film 7016, and a Ti film is used as the shielding film 7017.

[0495] An EL layer 7014 including a light-emitting layer is sandwiched between a first electrode 7013 and a second electrode 7015. In the case of the element structure shown in FIG. 17(A), the light-emitting element Light emitted from 7012 is emitted to the first electrode 7013 side as shown by the arrow.

[0496] In FIG. 17A, a light-transmitting conductive film is used as a gate electrode layer and a source electrode is used as a conductive film. 1 shows an example in which a light-transmitting thin film is used for the electrode layer and the drain electrode layer. The light emitted from 7012 passes through the color filter layer 7033 and exits through the substrate. It can be done.

[0497] The color filter layer 7033 can be formed by a droplet discharge method such as an ink jet method, a printing method, or a photolithography method. Each is formed by an etching method using graphic technology.

[0498] The color filter layer 7033 is covered with an overcoat layer 7034, which is further provided with a protective insulating layer. In FIG. 17(A), the overcoat layer 7034 is thin. As shown in the figure, the overcoat layer 7034 has irregularities caused by the color filter layer 7033. It has the function of flattening the surface.

[0499] Also, a protective insulating layer 7035, an overcoat layer 7034, a planarizing insulating layer 7036, an insulating layer 7032, and a contact hole formed in the insulating layer 7031 and reaching the drain electrode layer. The bolts are arranged at positions overlapping the partition walls 7019 .

[0500] Next, a light emitting element with a dual emission structure will be described with reference to FIG.

[0501] In FIG. 17(B), a transparent TFT 7021 electrically connected to the drain electrode layer of the driving TFT 7021 is A first electrode 7023 of the light-emitting element 7022 is formed over a conductive film 7027 having the An EL layer 7024 and a second electrode 7025 are stacked in this order on the first electrode 7023 .

[0502] The light-transmitting conductive film 7027 may be formed of indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium-containing indium tin oxide, indium tin oxide, indium zinc oxide, oxide ketone A light-transmitting conductive film such as indium tin oxide to which indium is added can be used.

[0503] In addition, various materials can be used for the first electrode 7023. For example, When 23 is used as a cathode, a material with a small work function, specifically, for example, Li or Cs Alkali metals such as Mg, Ca, Sr, and alkaline earth metals, and alloys containing these metals In addition to rare earth metals (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred. In this embodiment, the first electrode 7023 is used as a cathode, and the thickness thereof is set to a thickness that allows light to pass through (preferably Preferably, it is about 5 nm to 30 nm. For example, an aluminum film having a thickness of 20 nm is used. The membrane is used as the cathode.

[0504] After a light-transmitting conductive film and an aluminum film are stacked, the film is selectively etched. The light-transmitting conductive film 7027 and the first electrode 7023 may be formed by the same method. This is preferable because etching can be performed using the same mask.

[0505] The periphery of the first electrode 7023 is covered with a partition wall 7029. The partition wall 7029 is made of polyimide. organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxanes The partition wall 7029 is formed by using a photosensitive resin material in particular. An opening is formed on the surface 3, and the side wall of the opening is an inclined surface formed with a continuous curvature. When a photosensitive resin material is used for the partition wall 7029, The step of forming a resist mask can be omitted.

[0506] The EL layer 7024 formed over the first electrode 7023 and the partition wall 7029 includes a light-emitting layer. It can be made up of a single layer or multiple layers stacked together. When the EL layer 7024 is composed of multiple layers, it functions as a cathode. On the first electrode 7023, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are formed. It should be noted that it is not necessary to provide all of these layers except for the light-emitting layer.

[0507] The stacking order is not limited to the above, and the first electrode 7023 may be used as an anode, and a hole may be formed on the anode. The injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer may be laminated in this order. When comparing power consumption, the first electrode 7023 is used as a cathode, and an electron injection layer 7024 is provided on the cathode. The power consumption is reduced by stacking the electron transport layer, light emitting layer, hole transport layer, and hole injection layer in this order. This is preferable because

[0508] In addition, various materials can be used for the second electrode 7025 formed on the EL layer 7024. For example, when the second electrode 7025 is used as an anode, a material with a large work function can be used. A transparent conductive material such as ITO, IZO, or ZnO can be preferably used. In this embodiment, the second electrode 7026 is used as an anode, and the IT containing silicon oxide is used as an anode. O film is formed.

[0509] An EL layer 7024 including a light-emitting layer is sandwiched between a first electrode 7023 and a second electrode 7025. In the case of the element structure shown in FIG. 17(B), the light-emitting element The light emitted from 7022 travels between the second electrode 7025 and the first electrode 70 as shown by the arrows. 23It is fired on both sides.

[0510] In FIG. 17B, a light-transmitting conductive film is used as a gate electrode layer and a source electrode is used as a gate electrode layer. 1 shows an example in which a light-transmitting thin film is used for the electrode layer and the drain electrode layer. The light emitted from 7022 to the first electrode 7023 passes through the color filter layer 7043. and can be projected through the substrate.

[0511] The color filter layer 7043 can be formed by a droplet discharge method such as an ink jet method, a printing method, or a photolithography method. Each is formed by an etching method using graphic technology.

[0512] The color filter layer 7043 is covered with an overcoat layer 7044, which is further provided with a protective insulating layer. Covered by layer 7045.

[0513] Also, a protective insulating layer 7045, an overcoat layer 7044, a planarizing insulating layer 7046, an insulating layer 7042 and a contact hole formed in the insulating layer 7041 and reaching the drain electrode layer. The bolt is placed at a position where it overlaps with the partition wall 7029 .

[0514] However, if a light-emitting element with a dual-side emission structure is used and both display surfaces are full color, Since light from the second electrode 7025 side does not pass through the color filter layer 7043, a separate color filter is required. It is preferable to provide a sealing substrate with a filter layer above the second electrode 7025.

[0515] Next, a light emitting element with a top emission structure will be described with reference to FIG.

[0516] In FIG. 17(C), the driving TFT 7001 is an N-type, and the light emitted from the light emitting element 7002 is FIG. 17C shows a cross-sectional view of a pixel when the second electrode 7005 is exposed. The drain electrode layer of the TFT 7001 is in contact with the first electrode 7003, and the driving TFT 70 The first electrode 7001 is electrically connected to the first electrode 7003 of the light emitting element 7002. An EL layer 7004 and a second electrode 7005 are laminated in this order on the organic layer 003.

[0517] In addition, various materials can be used for the first electrode 7013. For example, When 13 is used as a cathode, a material with a small work function, specifically, for example, Li or Cs Alkali metals such as Mg, Ca, Sr, and alkaline earth metals, and alloys containing these metals In addition to (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred.

[0518] The periphery of the first electrode 7003 is covered with a partition wall 7009. The partition wall 7009 is made of polyimide. organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxanes The partition wall 7009 is formed by using a photosensitive resin material in particular, and the first electrode 701 An opening is formed on the surface 3, and the side wall of the opening is an inclined surface formed with a continuous curvature. When a photosensitive resin material is used for the partition wall 7009, The step of forming a resist mask can be omitted.

[0519] The EL layer 7004 formed on the first electrode 7003 and the partition wall 7009 is It is sufficient to include a light-emitting layer, and it may be composed of a single layer or a plurality of layers stacked. When the EL layer 7004 is composed of a plurality of layers, On the first electrode 7003 used as a light-emitting layer, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport ... It is not necessary to provide all of these layers except for the light-emitting layer. do not have.

[0520] The stacking order is not limited to the above, and the hole injection layer may be formed on the first electrode 7003 used as an anode. Alternatively, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer may be laminated in this order.

[0521] In Figure 17(C), hole injection is performed on a laminated film in which a Ti film, an aluminum film, and a Ti film are laminated in this order. The electron injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are stacked in this order, and Mg:A A laminate of a g-alloy thin film and ITO is formed.

[0522] However, when the driving TFT 7001 is an N-type, an electron injection layer and an electron The order of stacking the transport layer, light-emitting layer, hole transport layer, and hole injection layer is advantageous in terms of the drive circuit. This is preferable because it can suppress a voltage rise and reduce power consumption.

[0523] The second electrode 7005 is formed using a light-transmitting conductive material, for example, an acid. Indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide , indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Transparent films such as indium tin oxide, indium zinc oxide, and indium tin oxide doped with silicon oxide A conductive film having optical properties may also be used.

[0524] An EL layer 7004 including a light-emitting layer is sandwiched between a first electrode 7003 and a second electrode 7005. In the case of the pixel shown in FIG. 17(C), the light emitting element 700 Light emitted from 2 is emitted to the second electrode 7005 side as shown by the arrow.

[0525] In FIG. 17(C), the drain electrode layer of the driving TFT 7001 is made of silicon oxide. a layer 7051, a protective insulating layer 7052, a planarizing insulating layer 7056, a planarizing insulating layer 7053, and The insulating layer 7055 is electrically connected to the first electrode 7003 through a contact hole formed in the insulating layer 7055. The planarization insulating layers 7036, 7046, 7053, and 7056 are made of polyimide, acrylic, Resin materials such as polyethylene terephthalate, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above resin materials, low-k materials, siloxane resins, PSG ( Phosphorus glass, BPSG (borophosphorus glass), etc. can be used. By stacking multiple insulating films made of the material, planarization insulating layers 7036, 7046, and 7 Planarization insulating layers 7036, 7046, 7053, 7056 may be formed. The method for forming 56 is not particularly limited, and may be a sputtering method, an SOG method, or a sintering method depending on the material. Pin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing , offset printing, etc.), doctor knife, roll coater, curtain coater, knife A rotor or the like can be used.

[0526] In addition, a partition wall 700 is provided to insulate the first electrode 7003 from the first electrode of an adjacent pixel. The partition wall 7009 is made of an organic resin such as polyimide, acrylic, polyamide, or epoxy. The partition wall 7009 is formed by using an oil film, an inorganic insulating film, or an organic polysiloxane. An opening is formed on the first electrode 7003 using a resin material having a continuous side wall. It is preferable to form the partition wall 7009 so that it has an inclined surface with a certain curvature. When a photosensitive resin material is used as the resist mask, the step of forming a resist mask can be omitted. can.

[0527] In the structure of FIG. 17C, when full color display is performed, for example, the light emitting element 70 02 is a green light emitting element, one of the adjacent light emitting elements is a red light emitting element, and the other The light-emitting element is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element is also included, making a total of four A light-emitting display device capable of full-color display may be manufactured using a variety of light-emitting elements.

[0528] In the structure of FIG. 17(C), all the light emitting elements are white light emitting elements. A sealing substrate having a color filter or the like is disposed above the light emitting element 7002. A light-emitting display device capable of full color display may be manufactured. By combining a color filter and a color conversion layer, a full color display is achieved. It is possible.

[0529] Of course, a single-color display may be performed. For example, a lighting device may be formed using white light. Alternatively, a monochromatic light emitting device may be used to form an area color type light emitting device.

[0530] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0531] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0532] The thin film transistor (driving TFT) that controls the driving of the light emitting element and the light emitting element are electrically However, the current control TFT is connected between the driving TFT and the light emitting element. The configuration may be such that the power supply is connected to the power supply.

[0533] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0534] Next, the appearance and cross section of the light-emitting display panel (also called a light-emitting panel) in this embodiment will be described. This will be explained with reference to FIG. 18. FIG. 18 shows a thin film transistor formed on a first substrate. FIG. 10 is a plan view of a panel in which a light-emitting element and a second substrate are sealed with a sealant. 18(B) corresponds to a cross-sectional view taken along line HI in FIG. 18(A).

[0535] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0536] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 18B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45 shows an example of a thin film transistor 4509 included in a line driver circuit 4503a.

[0537] The thin film transistors 4509 and 4510 are the thin film transistors according to any one of Embodiments 2 to 9. A thin film transistor can be used as appropriate and can be formed using similar processes and materials. The oxide semiconductor layers of the transistors 4509 and 4510 have reduced hydrogen and water. The thin film transistors 4509 and 4510 are highly reliable thin film transistors.

[0538] The thin film transistor 4509 for the driver circuit is an oxide semiconductor thin film transistor. A conductive layer is provided at a position overlapping with the channel forming region of the semiconductor layer. The thin film transistors 4509 and 4510 are N-channel thin film transistors.

[0539] On the silicon oxide layer 4542, an oxide semiconductor of a thin film transistor 4509 for a driver circuit is formed. A conductive layer 4540 is provided at a position overlapping the channel forming region of the body layer. By providing the oxide semiconductor layer with a region overlapping the channel formation region, This can reduce the amount of change in the threshold voltage of the thin film transistor 4509 later. The conductive layer 4540 may have the same potential as the gate electrode layer of the thin film transistor 4509. Alternatively, it may be different and may function as the second gate electrode layer. The potential of the conductive layer 4540 may be GND, 0 V, or may be in a floating state.

[0540] In addition, a silicon oxide layer 4542 covering the oxide semiconductor layer of the thin film transistor 4510 is formed. The source electrode layer or the drain electrode layer of the thin film transistor 4510 is In the opening formed in the silicon oxide layer 4542 and the insulating layer 4551 provided on the transistor, The wiring layer 4550 is electrically connected to the first electrode 4517. The thin film transistor 4510 and the first electrode 4517 are formed in contact with each other. 50.

[0541] The silicon oxide layer 4542 is formed using a material and a method similar to those of the oxide insulating layer described in the above embodiment mode. It is sufficient to form it.

[0542] A color filter layer 4545 is formed on the insulating layer 455 so as to overlap the light-emitting region of the light-emitting element 4511. Formed on 1.

[0543] It also functions as a planarizing insulating film to reduce the surface irregularities of the color filter layer 4545. It is covered with an overcoat layer 4543 .

[0544] In addition, an insulating layer 4544 is formed on the overcoat layer 4543. The insulating layer 303 may be formed in the same manner as the protective insulating layer 303 shown in the sixth embodiment. For example, the insulating layer 303 may be formed of silicon nitride. The silicon film may be formed by sputtering.

[0545] The light emitting element 4511 has a first electrode 4 which is a pixel electrode. 517 is a source or drain electrode layer of the thin film transistor 4510 and a wiring layer 455 The light emitting element 4511 is electrically connected to the first electrode 4517 via the first electrode 4517. 4512 and the second electrode 4513, but is not limited to the structure shown. The structure of the light emitting element 4511 is determined according to the direction of the light extracted from the light emitting element 4511. It can be changed as appropriate.

[0546] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. An opening is formed on the first electrode 4517 using a photosensitive material, and the sidewall of the opening is continuous. It is preferable to form the inclined surface with a certain curvature.

[0547] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0548] The second electrode 45 is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 4511. A protective film may be formed on the insulating film 13 and the partition wall 4520. Examples of the protective film include a silicon nitride film, Silicon nitride oxide film, DLC film, etc. can be formed.

[0549] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a and the FPC 45 It is supplied by 18b.

[0550] The connection terminal electrode 4515 is made of the same conductive film as the first electrode 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed on the source electrode layer and the drain electrode layer of the thin film transistor 4509. It is formed from the same conductive film as the electrode layer.

[0551] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0552] The second substrate is not transparent to light, and is positioned in the direction of light extraction from the light emitting element 4511. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0553] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of PVC (polyvinyl chloride), acrylic, or thermosetting resin. Polyimide, epoxy resin, silicone resin, PVB (Polyvinyl Butyral) or EVA ( For example, if nitrogen is used as a filler, good.

[0554] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. An optical film such as a retardation plate (λ / 4 plate, λ / 2 plate) may be provided as appropriate. Alternatively, an anti-reflection film may be provided on the circular polarizer. For example, the surface roughness can be used to diffuse reflected light, Anti-glare treatment can be applied to reduce reflections.

[0555] The sealant is formed using a screen printing method, an inkjet device, or a dispensing device. The sealing material is typically a visible light curing material, an ultraviolet curing material, or a heat curing material. A material containing a resin can be used, and a filler may also be included.

[0556] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted, and the configuration is not limited to that of FIG.

[0557] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0558] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0559] (Embodiment 12) In this embodiment, an example of electronic paper is shown as a semiconductor device according to an embodiment of the present invention. vinegar.

[0560] FIG. 19 shows an active matrix semiconductor device as an example of a semiconductor device to which an embodiment of the present invention is applied. In this embodiment, the thin film transistor 581 is 5 is an example of applying the thin film transistor shown in FIG. 5. The layer has reduced hydrogen and water. Therefore, the thin film transistor 581 is a highly reliable thin film transistor. It is a transistor.

[0561] The electronic paper in Figure 19 is an example of a display device that uses the twisting ball display method. The spherical display method uses black and white spherical particles as the display element, and the electrode layer is The spherical particles are disposed between a first electrode layer and a second electrode layer, and the first electrode layer and the second electrode layer are This is a method of displaying information by creating a potential difference between the polar layers and controlling the orientation of the spherical particles. .

[0562] The thin film transistor 581 provided on the substrate 580 is a thin film transistor of a bottom gate structure. The source electrode layer or the drain electrode layer is a silicon oxide layer 583 and a protective insulating layer 58 4. The insulating layer 585 is electrically connected to the first electrode layer 587 through an opening formed in the insulating layer 585. It is being done.

[0563] Between the first electrode layer 587 and the second electrode layer 588, there are a black region 590a and a white region 590b. 0b and a spherical particle having a cavity 594 filled with liquid therearound. The spherical particles are filled with a filler 595 such as a resin (see FIG. 19). In this embodiment, the first electrode layer 587 corresponds to a pixel electrode and is provided on the opposing substrate 596. The second electrode layer 588 corresponds to a common electrode.

[0564] Also, instead of the spherical element, an electrophoretic element can be used. Diameter 10μm~200μm containing positively charged white particles and negatively charged black particles The microcapsules provided between the first electrode layer and the second electrode layer are used. When an electric field is applied to the black capsules by the first and second electrode layers, they turn into fine white particles. When the electrons move in the opposite direction, the black particles move in the opposite direction, and white or black can be displayed. The display element used is an electrophoretic display element, which is generally called electronic paper. Since electrophoretic display elements have a higher reflectivity than liquid crystal display elements, auxiliary lights are not required. It consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the , a semiconductor device with a display function (simply a display device, or a semiconductor device equipped with a display device) from a radio wave source Even if the device (also called the body device) is moved away, the displayed image can be saved. become.

[0565] Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured. .

[0566] The logic circuit shown in the first embodiment is used, for example, in a driver circuit of the electronic paper in this embodiment. In addition, the transistor in the display portion can also be a transistor using an oxide semiconductor layer. For example, a drive circuit and a display unit can be provided on the same substrate.

[0567] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0568] (Embodiment 13) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receiver) (also called signal processors), computer monitors, digital cameras, digital video cameras , digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable games Examples include gaming machines, mobile information terminals, sound reproduction devices, and large game machines such as pachinko machines. .

[0569] 20A shows an example of a mobile phone. The mobile phone 1600 has a housing 1601. In addition to the display unit 1602 incorporated in the It is equipped with an external connection port 1604, a speaker 1605, a microphone 1606, etc.

[0570] The mobile phone 1600 shown in FIG. 20A displays information by touching the display portion 1602 with a finger or the like. In addition, operations such as making a phone call or sending an email can be performed by using the This can be done by touching the display unit 1602 with a finger or the like.

[0571] The screen of the display unit 1602 has three main modes. The first is a display mode that mainly displays images. The first mode is a display mode, and the second mode is an input mode that mainly inputs information such as characters. This is a display + input mode that combines two modes: display mode and input mode.

[0572] For example, when making a call or creating an email, the display unit 1602 is used to input characters. This is the main character input mode, and you can input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1602. It's nice.

[0573] In addition, the mobile phone 1600 may include a sensor for detecting tilt, such as a gyro or acceleration sensor. By providing a detection device having the above, the orientation of the mobile phone 1600 (portrait or landscape) can be determined and the display The screen display of the display unit 1602 can be automatically switched.

[0574] The screen mode can be switched by touching the display unit 1602 or by operating the housing 1601. This is done by operating the buttons 1603a and 1603b. For example, the image to be displayed on the display unit can be switched depending on the type of image. If the image signal is video data, it switches to display mode, and if it is text data, it switches to input mode. can.

[0575] In the input mode, the optical sensor of the display unit 1602 detects a signal and displays it. If there is no input by touch operation on the part 1602 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0576] The display unit 1602 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to capture images of finger veins, palm veins, etc.

[0577] The semiconductor device described in the above embodiment modes can be applied to the display portion 1602. For example, As the element switching element, a plurality of thin film transistors shown in the other embodiments are arranged. It is possible.

[0578] FIG. 20(B) is also an example of a mobile phone. The portable information terminal shown in FIG. 20(B) is It can have multiple functions. For example, in addition to the telephone function, it can also have a built-in computer and perform various functions. It can also have various data processing functions.

[0579] The portable information terminal shown in FIG. 20B is configured with two housings, a housing 1800 and a housing 1801. The housing 1801 contains a display panel 1802, a speaker 1803, a microphone Phone 1804, pointing device 1806, camera lens 1807, external connection The housing 1800 includes a keyboard 1810 and an external memory slot. 1811, etc. The antenna is built into the housing 1801.

[0580] The display panel 1802 is equipped with a touch panel, and the image displayed on the display panel 1802 is shown in FIG. A plurality of operation keys 1805 are indicated by dotted lines.

[0581] In addition to the above configuration, a contactless IC chip, a small recording device, etc. may be built in.

[0582] The semiconductor device shown in the above embodiment mode can be used for the display panel 1802. The display direction changes accordingly. It is equipped with a microphone 1807, so it is possible to make video calls. The Crophone 1804 is not limited to voice calls, but also allows video calls, recording, playback, etc. Furthermore, the housing 1800 and the housing 1801 slide and are unfolded as shown in FIG. 20(B). The device can be folded from a folded state to a stacked state, making it possible to make the device compact and portable.

[0583] The external connection terminal 1808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. By inserting a recording medium into the memory slot 1811, it is possible to store and transfer a larger amount of data. do.

[0584] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0585] FIG. 21(A) shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this case, the housing 9601 is supported by a stand 9605. The figure shows the configuration.

[0586] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0587] The television device 9600 is configured to include a receiver, a modem, and the like. It is possible to receive more general television broadcasts, and also to receive them by wire or wirelessly via a modem. By connecting to a communication network, it can be transmitted in one direction (sender to receiver) or two directions (transmit to receiver). It is also possible to communicate information between followers and recipients, or between recipients themselves.

[0588] The semiconductor device described in the above embodiment modes can be applied to the display portion 9603. For example, As the element switching element, a plurality of thin film transistors shown in the other embodiments are arranged. It is possible.

[0589] FIG. 21(B) shows an example of a digital photo frame. The frame 9700 has a display unit 9703 built into a housing 9701. 3 is capable of displaying various images, for example, images taken with a digital camera. By displaying data, it can function like a regular photo frame.

[0590] The semiconductor device described in the above embodiment modes can be applied to the display portion 9703. For example, As the element switching element, a plurality of thin film transistors shown in the other embodiments are arranged. It is possible.

[0591] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US It is equipped with a terminal that can be connected to various cables such as B cable, a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but if they are provided on the side or back, For example, it is preferable to insert a recording medium into a digital photo frame. Insert a memory that stores image data taken with a digital camera and import the image data. The captured image data can be displayed on the display portion 9703 .

[0592] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0593] FIG. 22 shows a portable gaming machine consisting of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to the display unit 98 by a connecting portion 9893 so as to be openable and closable. 82 is incorporated, and a display portion 9883 is incorporated in the housing 9891.

[0594] The semiconductor device described in the above embodiment modes can be applied to the display portion 9883. For example, As the element switching element, a plurality of thin film transistors shown in the other embodiments are arranged. It is possible.

[0595] 22 also includes a speaker unit 9884, a recording medium insertion unit 9885, and a 886, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor Sa9888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature Degree, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient , vibration, odor or infrared measuring functions), microphone 9889) etc. Of course, the configuration of the portable gaming machine is not limited to the above, and It is sufficient if the device is configured with the thin film transistors disclosed in the specification, and other auxiliary equipment is provided as appropriate. The portable gaming machine shown in FIG. It has the function of reading out the programs or data stored in the device and displaying them on the display, and wirelessly connecting to other portable gaming machines. It has a function to communicate and share information. The function is not limited to this and can have various functions.

[0596] (Embodiment 14) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, trains, etc. It can be used for in-car advertising, displaying on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 23.

[0597] 23 shows an example of an electronic book. For example, an electronic book 2700 includes a housing 2701 and The housing 2701 and the housing 2703 are made up of two housings. The shaft 2711 serves as an axis for opening and closing. This configuration allows the device to operate like a paper book.

[0598] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are also configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, if a sentence is displayed on the right display (display 2705 in FIG. 23) and In FIG. 23, an image can be displayed on the display unit 2707).

[0599] 23 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The keyboard and pointing device may be provided on the rear surface of the housing. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB cable). The configuration is provided with a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. good.

[0600] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0601] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0602] (Embodiment 15) One embodiment of the present invention is to provide a semiconductor device that functions as a carrier donor (donor or acceptor) in an oxide semiconductor. By removing impurities to an extremely low level, an intrinsic or substantially intrinsic semiconductor can be obtained. The oxide semiconductor is applied to a thin film transistor.

[0603] FIG. 24 is a diagram showing the band structure between the source and drain of such a transistor. The Fermi level of a highly purified oxide semiconductor is ideally located in the center of the forbidden band. It is placed.

[0604] In this case, the work function is φm, and the electron affinity of the oxide semiconductor is χ.

[0605] Here, if φm=χ, the Fermi level of the electrode metal and the oxide semiconductor at the junction surface The conduction band levels of the ohmic contacts are the same. The band gap is 3.05 eV, the electron affinity is 4.3 eV, and the intrinsic state (carrier density) is Degrees: approx. 1 x 10 -7 / cm 3 ) and the work function is assumed as the source and drain electrodes. When titanium (Ti) with a potential of 4.3 eV is used, the electrons are shorted as shown in Figure 24. No Kitkey barrier is formed

[0606] Figure 25 shows the results of applying a positive voltage to the drain side of a transistor using an oxide semiconductor. This shows the state where a positive voltage (V D >0), the dashed line indicates the gate When no voltage is applied to (V G =0), the solid line indicates a positive voltage on the gate (V G >0) was applied Since oxide semiconductors have a wide band gap, they can be highly purified and used as intrinsic or substantially The intrinsic carrier density of an essentially intrinsic oxide semiconductor is zero or extremely close to zero. When no voltage is applied to the gate, the high ohmic contact resistance prevents the electrode from contacting the oxide semiconductor. This indicates the off state, where no carriers (electrons) are injected into the positive gate and no current flows. When a voltage of 0 V is applied, the ohmic contact resistance decreases, indicating an ON state in which current flows.

[0607] Figure 26(A) shows the energy band diagram of the MOS structure when the gate voltage is positive. This shows a transistor using a highly purified oxide semiconductor. Since there are almost no thermally excited carriers in oxide semiconductors, However, as shown in Figure 25, carriers injected from the source side A can be propagated.

[0608] FIG. 26(B) is an energy band diagram of the MOS structure when the gate voltage is made negative. The figure shows a transistor using an oxide semiconductor. Since there are almost no carriers (holes), carriers are not accumulated near the gate insulating film. This means that the off-state current is small.

[0609] FIG. 27 shows a band diagram of a transistor using silicon semiconductor. The semiconductor band gap is 1.12 eV. The intrinsic carrier density is 1.45 x 10 10 / cm 3 (300K), and carriers exist even at room temperature. Thermally excited carriers cannot be ignored even in this case, and the off-current varies greatly depending on the temperature. become.

[0610] Thus, simply applying oxide semiconductors with wide band gaps to transistors is not enough. The carrier concentration is 1×10 14 / c m 3 Less than 1 × 10 12 / cm 3 By making it as follows, practical operation can be achieved. The carriers thermally excited by the temperature are excluded, and only the carriers injected from the source side are used. This allows the transistor to operate with an off-state current of 1×10 -13 A The OFF current is reduced to below 100kJ / s, and the OFF current is extremely stable with almost no change due to temperature changes. A working transistor can be obtained.

[0611] (Embodiment 16) In this embodiment, the measured values ​​of the off-state current of the evaluation element (also referred to as TEG) are as follows: explain.

[0612] Figure 28 shows the effective performance of 200 thin film transistors with L / W = 3 μm / 50 μm connected in parallel. The initial characteristics of a thin film transistor with L / W=3 μm / 10,000 μm are shown in Fig. 1. The diagram is shown in FIG. 29(A), and a partially enlarged top view of the diagram is shown in FIG. 29(B). The area enclosed by the dotted line in the figure is the thin film for one stage with L / W=3μm / 50μm and Lov=1.5μm. To measure the initial characteristics of the thin-film transistor, the substrate temperature was set to room temperature. The source-drain voltage (hereinafter referred to as drain voltage or Vd) is set to 10 V. - The gate voltage (hereinafter referred to as gate voltage or Vg) was changed from -20V to +20V. The change in the source-drain current (hereinafter referred to as drain current or Id) when In other words, the Vg-Id characteristics were measured. In FIG. 28, Vg was measured in the range of -20V to +5V. is shown.

[0613] As shown in FIG. 28, a thin film transistor with a channel width W of 10000 μm has a Vd of 1 V and At 10V and 10V, the off-state current is 1×10 -13 [A] or less, and the measuring instrument (semiconductor The resolution of the parameter analyzer (Agilent 4156C; Agilent) The transistor output current per channel width W of 10,000 μm is less than 100 fA. The current is 1×10 -13 A or less, so the transistor per channel width W1μm The off-state current is also 1×10 -13 Furthermore, the channel width is 10,000 μm The off-state current of each transistor is 1×10 -13 If A or less, the channel width W is 1 μm The off-state current of a transistor is 1×10 -17 This can be converted to A or below.

[0614] A method for manufacturing the thin film transistors used for the measurements will be described.

[0615] First, a silicon nitride layer is formed on a glass substrate as a base layer by a CVD method. A silicon oxynitride layer was formed on the silicon oxynitride layer as a gate electrode layer by sputtering. The tungsten layer was then selectively etched to form a gate electrode. A gate electrode layer was formed.

[0616] Next, a 100 nm thick silicon oxynitride film was formed on the gate electrode layer by CVD as a gate insulating layer. A base layer was formed.

[0617] Next, an In-Ga-Zn-O oxide semiconductor is deposited on the gate insulating layer by sputtering. A film formation target (molar ratio: In2O3:Ga2O3:ZnO=1:1:2) was used. An oxide semiconductor layer having a thickness of 50 nm was formed by selectively etching the oxide semiconductor layer. Then, island-shaped oxide semiconductor layers were formed.

[0618] Next, the oxide semiconductor layer was subjected to a first etching treatment in a clean oven under a nitrogen atmosphere at 450° C. for 1 hour. Heat treatment was carried out.

[0619] Next, a titanium layer (thickness 150 The source and drain electrode layers were formed by sputtering. Selective etching was performed to obtain a thin-film transistor with a channel length L of 3 μm and a channel width W By setting the width to 50μm and connecting 200 pieces in parallel, the effective L / W is 3μm / 10000μ It was set to m.

[0620] Next, a protective insulating layer was deposited by reactive sputtering so as to contact the oxide semiconductor layer. A silicon oxide layer was formed to a thickness of 300 nm by selectively removing the silicon oxide layer, which was a protective layer. The gate electrode layer, the source electrode layer, and the drain electrode layer were etched to form openings. Then, a second heat treatment was carried out at 250°C for 1 hour in a nitrogen atmosphere.

[0621] Then, before measuring the Vg-Id characteristics, the device was heated at 150° C. for 10 hours.

[0622] Through the above steps, a bottom gate thin film transistor was fabricated.

[0623] As shown in Figure 28, the thin film transistor is 1×10 -13 [A] is the level of the above work This is because the hydrogen concentration in the oxide semiconductor layer can be sufficiently reduced during the manufacturing process. The hydrogen concentration in the semiconductor layer is 5×10 19 / cm 3 Less than or equal to 5 x 10 18 / cm 3 Less than 5 × 10, more preferably 17 / cm 3 In addition, in the oxide semiconductor layer The hydrogen concentration was measured using secondary ion mass spectrometry (SIMS). This is done using ss Spectrometry.

[0624] Although an example using an In-Ga-Zn-O-based oxide semiconductor has been shown, the present invention is not particularly limited and other oxide semiconductor materials, for example, In-Sn-Zn-O, Sn-Ga-Zn-O, Al -Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, In-Sn-O system, Sn-Zn-O, Al-Zn-O, In-O, Sn-O, Zn-O, etc. In addition, AlOx is mixed in an amount of 2.5 to 10 wt% as an oxide semiconductor material. In-Al-Zn-O system and In-Zn-O system containing 2.5 to 10 wt% SiOx can also be used.

[0625] In addition, the carrier concentration of the oxide semiconductor layer measured by the carrier measurement device is A concentration 1.45 x 10 10 / cm 3 Equal to or less than 5×10 14 / cm 3 Less than 5 × 10, more preferably 12 / cm 3 The following is an example of an oxide semiconductor. The carrier concentration of the layer can be made as close to zero as possible.

[0626] It is also possible to set the channel length L of the thin film transistor to 10 nm or more and 1000 nm or less. This allows for faster circuit operation and an extremely small off-state current, further reducing power consumption. It can also be electrified.

[0627] In addition, when the thin film transistor is in an off state, the oxide semiconductor layer is regarded as an insulator and the circuit is designed. It is possible to carry out calculations.

[0628] Next, the temperature characteristics of the off-current of the thin film transistor manufactured in this embodiment were evaluated. The temperature characteristics are important for the environmental resistance of the final product that uses the thin-film transistor and for maintaining its performance. It is important to consider that the smaller the amount of change, the better. increases.

[0629] The temperature characteristics are measured using a thermostatic chamber at -30, 0, 25, 40, 60, 80, 100, and 120 The substrate on which the thin film transistor was formed was kept at a constant temperature of 100°C, and the drain voltage was The gate voltage was changed from -20V to +20V at 6V to obtain the Vg-Id characteristics.

[0630] Figure 30(A) shows the Vg-Id characteristics measured at each of the above temperatures, overlaid. The area of ​​the off-state current surrounded by the dotted line is shown enlarged in FIG. 30(B). The curve on the right side indicated by the mark is obtained at -30℃, and the curve on the left side is obtained at 120℃. The curves shown are located between these two. The on-current has almost no temperature dependence. As is clear from the enlarged view of Figure 30(B), the gate current is At all temperatures, the resolution is close to 1×10 -12 [A] or less, Even at a high temperature of 120°C, the off-state current is 1×10 - 12 Considering that the channel width W is 10,000 μm, , it can be seen that the off-state current is very small.

[0631] Thin film transistors using highly purified oxide semiconductors have almost no temperature dependence of off-state current. This is because the energy gap of oxide semiconductors is 3 eV or more, and the intrinsic capacitance This is due to the extremely small number of carriers. Also, the source and drain regions are in a degenerate state. This is the reason why temperature dependency does not appear. Most of the electrons are generated by carriers injected into the oxide semiconductor from the degenerate source region. Therefore, the carrier density does not depend on temperature, and the above characteristics (no temperature dependence of off-current) are It can be explained.

[0632] Using thin film transistors with extremely low off-state current, memory circuits (memory elements) When fabricating a device such as this, the off-current value is small and there is almost no leakage, so the stored data is retained. The memory circuit here includes a logic circuit. [Explanation of symbols]

[0633] 100 Logic Circuits 101 Transistor 102 transistor 103 Capacitor element 104 transistors 105 transistors 106 Capacitor element 107 Transistor 108 transistors 109 Capacitive element 110 Transistor 111 Transistor 112 Capacitor element 121 nodes 122 nodes 123 nodes 124 nodes 131 Unit Logic Circuit 132 Unit Logic Circuit 141 period 142 period 143 period 144 period 145 period 146 period 147 period 148 period 149 period 150 period 151 Logic Circuits 152 Logic Circuits 153 Logic Circuits 300 boards 302 Gate insulating layer 303 Protective insulation layer 310 Thin-film transistor 311 Gate electrode layer 313 Channel formation region 314a High-resistivity source region 314b High-resistivity drain region 315a Source electrode layer 315b drain electrode layer 316 Oxide insulating layer 320 board 322 Gate insulating layer 323 Protective Insulation Layer 330 Oxide semiconductor film 331 Oxide semiconductor layer 332 Oxide semiconductor layer 340 PCB 342 Gate insulating layer 343 Protective Insulation Layer 345 Oxide semiconductor film 346 Oxide semiconductor layer 350 Thin-Film Transistors 351 Gate electrode layer 352 Oxide semiconductor layer 355a Source electrode layer 355b drain electrode layer 356 Oxide insulating layer 360 Thin Film Transistor 361 Gate electrode layer 362 Oxide semiconductor layer 363 Channel formation region 364a High-resistance source region 364b High-resistivity drain region 365a Source electrode layer 365b drain electrode layer 366 Oxide insulating layer 370 PCB 372a first gate insulating layer 372b second gate insulating layer 373 Protective Insulation Layer 380 Thin Film Transistors 381 Gate electrode layer 382 Oxide semiconductor layer 385a Source electrode layer 385b Drain electrode layer 386 Oxide insulating layer 390 Thin-Film Transistors 391 gate electrode layer 392 Oxide semiconductor layer 393 Oxide Semiconductor Film 394 PCB 395a Source electrode layer 395b Drain electrode layer 396 Oxide insulating layer 397 Gate insulating layer 398 Protective Insulation Layer 399 Oxide semiconductor layer 400 boards 402 Gate insulating layer 407 Insulating Layer 410 Thin Film Transistor 411 Gate electrode layer 412 Oxide semiconductor layer 414a wiring layer 414b wiring layer 415a Source electrode layer or drain electrode layer 415b Source electrode layer or drain electrode layer 420 silicon substrate 421a aperture 421b aperture 422 Insulating layer 423 Aperture 424 Conductive Layer 425 Thin-film transistor 426 Thin Film Transistor 427 Conductive Layer 438 Wiring layer 450 board 452 Gate insulating layer 457 Insulating Layer 460 Thin Film Transistor 461 Gate electrode layer 461a Gate electrode layer 461b Gate electrode layer 462 Oxide semiconductor layer 464 Wiring layer 465a Source electrode layer or drain electrode layer 465a1 Source electrode layer or drain electrode layer 465a2 Source electrode layer or drain electrode layer 465b Source electrode layer or drain electrode layer 468 Wiring layer 580 board 581 Thin-film transistor 583 Silicon oxide layer 584 Protective Insulation Layer 585 Insulation Layer 587 Electrode layer 588 Electrode layer 590a black area 590b White area 594 Cavity 595 Filling material 596 Opposing substrate 1600 mobile phones 1601 Case 1602 Display section 1603a Operation button 1603b Operation button 1604 External connection port 1605 Speaker 1606 Mike 1800 cabinet 1801 Case 1802 Display panel 1803 Speaker 1804 Microphone 1805 Operation Key 1806 Pointing Device 1807 Camera Lenses 1808 External connection terminal 1810 keyboard 1811 external memory slot 2700 e-books 2701 Housing 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 Thin Film Transistor 4011 Thin-film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4040 Conductive layer 4041 Insulation layer 4042 Protective insulation layer 4501 Circuit Board 4502 Pixel section 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scanning line driver circuit 4504b Scanning line driver circuit 4505 Sealing material 4506 board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode 4518a FPC 4518b FPC 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4542 silicon oxide layer 4543 Overcoat layer 4544 Insulation layer 4545 Color filter layer 4550 wiring layer 4551 Insulation layer 5300 board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing control circuit 5601 Shift Register 5602 Switching Circuit 5603 Thin-film transistor 5604 Wiring 5605 Wiring 6400 pixels 6401 Switching transistor 6402 Drive transistor 6403 Capacitor element 6404 Light-emitting element 6405 signal line 6406 scan lines 6407 Power line 6408 Common potential line 7001 Driving TFT 7002 Light-emitting element 7003 Electrode 7004 EL layer 7005 Electrode 7009 Bulkhead 7011 Driving TFT 7012 Light-emitting element 7013 Electrode 7014 EL layer 7015 Electrode 7016 Shielding membrane 7017 Conductive film 7019 Bulkhead 7021 Driving TFT 7022 Light-emitting element 7023 Electrode 7024 EL layer 7025 Electrode 7026 Electrode 7027 Conductive film 7029 Bulkhead 7031 Insulation layer 7032 Insulation layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulation layer 7036 Planarizing insulating layer 7041 Insulation layer 7042 Insulation layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulation layer 7046 Planarization insulating layer 7051 Silicon oxide layer 7052 Protective insulation layer 7053 Planarization insulating layer 7055 Insulation layer 7056 Planarization insulating layer 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Control Machine 9700 Digital Photo Frame 9701 Housing 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker unit 9885 Operation Key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section

Claims

[Claim 1] an oxide semiconductor layer having a function as a channel formation layer, and an off-state current per 1 μm of channel width of 1×10 －１３ A transistor having a capacitance of 1.0 A or less, a first signal, a second signal, and a third signal that is a clock signal are input as input signals; a logic circuit that outputs, as output signals, fourth and fifth signals whose voltage states are set in accordance with the first to third signals that are input;

Images