Display substrate and display device

Abstract

A display substrate and a display device are provided.SOLUTION: A display substrate and a display device, wherein the display substrate comprises a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer and a second metal layer stacked on a base, the metal oxide layer comprises a first pattern, a second pattern and a capacitor pattern, the first metal layer comprises a first polar plate, the first polar plate and the capacitor pattern at least have a first overlapping region to form a first storage capacitor, and the second metal layer comprises a second polar plate, the second polar plate and the capacitor pattern at least have a second overlapping region; A second storage capacitor is formed, and potentials of the first electrode plate and the second electrode plate are the same.SELECTED DRAWING: Figure 2a

Description

[Technical Field]

[0001] This application claims priority from a Chinese patent application filed with the China Patent Office on December 13, 2019, bearing application number 201922237251.2 and entitled "Display substrate and display device," the contents of which are hereby incorporated by reference.

[0002] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and more particularly to display substrates and display devices. [Background technology]

[0003] Organic Light Emitting Diode (OLED) displays have advantages such as ultra-thinness, wide viewing angle, automatic light emission, high brightness, continuously adjustable emission color, low cost, fast response time, low power consumption, wide operating temperature range, and flexible display, and are gradually becoming a promising next-generation display technology. Depending on the driving method, OLEDs are divided into two types: passive matrix (PM) type and active matrix (AM) type. AMOLED is a current-driven device that uses independent thin film transistors (TFT) to control each sub-pixel, and each sub-pixel can be continuously and independently driven to emit light.

[0004] In AMOLED, the voltage of the gate electrode of the drive transistor is maintained by a storage capacitor between data writes of one frame and the next. Because the transistor has leakage current, the voltage stored in the storage capacitor gradually decreases, changing the potential of the gate electrode of the transistor, which further affects the current flowing through the organic electroluminescent diode and the luminance of the subpixel. For this reason, the capacitance of the storage capacitor is usually designed to be large enough to prolong the duration of the voltage.

[0005] However, with the development of high-resolution (PPI) display technology, pixel size is becoming smaller and smaller, and the layout space is shrinking, which reduces the space for arranging the storage capacitor, significantly limiting the increase in the capacitance of the storage capacitor. Although several solutions have been proposed in related technologies, these solutions have defects that degrade display quality. Summary of the Invention [Means for solving the problem]

[0006] The following is a summary of the subject matter described in detail in this disclosure. This summary does not limit the scope of protection of the claims.

[0007] On the one hand, the present disclosure provides a display substrate, comprising: a base; and a plurality of sub-pixels disposed on the base and corresponding to different colors, each of the sub-pixels comprising a pixel driving circuit and an organic electroluminescent diode electrically connected to the pixel driving circuit; the pixel driving circuit comprises a first transistor, a second transistor, and a storage capacitor, wherein the first transistor has a gate electrode coupled to a first scan line, a first electrode coupled to a data line, and a second electrode coupled to a gate electrode of the second transistor; the second transistor has a first electrode coupled to a first power supply voltage line, a second electrode coupled to a first electrode of the organic electroluminescent diode, and a second electrode of the organic electroluminescent diode coupled to a second power supply voltage line; the storage capacitor has a first electrode coupled to the gate electrode of the second transistor, and a second electrode coupled to a second electrode of the second transistor, the storage capacitor being used to store a potential of the gate electrode of the second transistor; The display substrate includes a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer, and a second metal layer, which are stacked in a direction perpendicular to the base; the metal oxide layer includes a first pattern serving as an active layer of the first transistor, a second pattern serving as an active layer of the second transistor, and a capacitor pattern serving as a first electrode of the storage capacitor; the first metal layer includes a first plate, and an orthogonal projection of the first plate at a base and an orthogonal projection of the capacitor pattern at a base have at least a first overlapping area to form a first storage capacitor; the second metal layer comprises a second plate, and the orthogonal projection of the second plate at a base and the orthogonal projection of the capacitor pattern at a base have at least a second overlapping area to form a second storage capacitor; The first and second plates are at the same potential.

[0008] In one exemplary embodiment, there is an overlap region between the orthogonal projection of the second pattern on the base and the orthogonal projection of the first plate on the base.

[0009] In one exemplary embodiment, the semiconductor device further comprises a gate insulating layer between the first insulating layer and the second insulating layer, the thickness of the gate insulating layer being smaller than the thickness of the second insulating layer.

[0010] In one exemplary embodiment, the thickness of the first insulating layer is less than the sum of the thicknesses of the gate insulating layer and the second insulating layer.

[0011] In one exemplary embodiment, the semiconductor device further comprises a gate metal layer between the first metal layer and the second metal layer, the thickness of the gate metal layer being smaller than the thickness of the second metal layer.

[0012] In one exemplary embodiment, the aspect ratio of the channel of the first transistor is smaller than the aspect ratio of the channel of the second transistor.

[0013] In one exemplary embodiment, the voltage of the first power supply voltage line is higher than the voltage of the second power supply voltage line, the maximum voltage of the data line is lower than the maximum voltage of the first scan line, and the maximum voltage of the data line is lower than the voltage of the first power supply voltage line.

[0014] In one exemplary embodiment, the orthogonal projection of the first pattern on the base is spaced apart from the orthogonal projection of the capacitor pattern on the base, and the orthogonal projection of the first pattern on the base is spaced apart from the orthogonal projection of the first electrode plate on the base.

[0015] In one exemplary embodiment, the first pattern and the capacitor pattern are of a monolithic structure.

[0016] In one exemplary embodiment, the pixel driving circuit further includes a third transistor, the third transistor having a gate electrode coupled to a second scan line, a first electrode connected to a compensation line, and a second electrode coupled to the second electrode of the second transistor.

[0017] In one exemplary embodiment, the metal oxide layer further comprises a third pattern that serves as an active layer of the third transistor.

[0018] In one exemplary embodiment, the second insulating layer covers the first scanning line, the second scanning line, the gate electrode of the first transistor, the gate electrode of the second transistor, and the gate electrode of the third transistor, and a plurality of via holes are respectively opened in the second insulating layer.

[0019] In one exemplary embodiment, the second metal layer further comprises the data line, the first power supply voltage line, a source electrode of the first transistor, a drain electrode of the first transistor, a source electrode of the second transistor, a drain electrode of the second transistor, a source electrode of the third transistor, and a drain electrode of the third transistor.

[0020] In one exemplary embodiment, the source electrode of the first transistor and the data line are integrally formed, the source electrode of the second transistor and the first power supply voltage line are integrally formed, and the drain electrode of the second transistor and the drain electrode of the third transistor and the second plate are integrally formed.

[0021] In one exemplary embodiment, the capacitor plate is disposed in the same layer as the active layer of the first transistor, the active layer of the second transistor, and the active layer of the third transistor, and is made of the same material and formed by the same patterning process.

[0022] In one exemplary embodiment, the second plate is disposed in the same layer as the data line, the first power supply voltage line, the first source electrode, the drain electrode of the first transistor, the source electrode of the second transistor, the drain electrode of the second transistor, the source electrode of the third transistor, and the drain electrode of the third transistor, and is made of the same material and formed by the same patterning process.

[0023] In one exemplary embodiment, the metal oxide layer is a monolayer, bilayer, or multilayer.

[0024] In one exemplary embodiment, the metal oxide layer comprises a first oxide layer and a second oxide layer stacked together, the second oxide layer having a lower conductivity than the first oxide layer and a larger bandgap than the first oxide layer.

[0025] In one exemplary embodiment, the first oxide layer is configured to be adjacent to the gate electrodes of the first, second and third transistors.

[0026] On the other hand, the present disclosure further provides a display device including any of the above display substrates.

[0027] Other features and advantages of the present disclosure will be set forth in the following specification, examples, and in part will be obvious from the specification, or may be learned by the practice of the present disclosure. The objectives and other advantages of the embodiments of the present disclosure may be realized and obtained by the structure particularly pointed out in the description, claims, and drawings.

[0028] Other aspects can be understood after reading and understanding the drawings and detailed description.

[0029] The drawings are used to provide a further understanding of the technical solution of the present disclosure, constitute a part of the specification, and are used to interpret the technical solution of the present disclosure together with the embodiments of the present disclosure, but are not intended to limit the technical solution of the present disclosure. [Brief explanation of the drawings]

[0030] [Figure 1] FIG. 1 is a schematic diagram of an equivalent circuit of an OLED pixel driving circuit. [Figure 2a] FIG. 2a is an exemplary schematic diagram of a local structure of a display substrate according to an embodiment of the present disclosure. [Figure 2b] FIG. 2b is a cross-sectional view taken along the line AA in FIG. 2a. [Figure 3a] FIG. 3a is a schematic diagram of the first metal layer of the present disclosure after it has been patterned. [Figure 3b] FIG. 3b is a cross-sectional view taken along the line AA in FIG. 3a. [Figure 4a] FIG. 4a is a schematic diagram of the active layer and capacitor plates of the present disclosure after they have been patterned. [Figure 4b] FIG. 4b is a cross-sectional view taken along the line AA in FIG. 4a. [Figure 5a] FIG. 5a is a schematic diagram of the gate electrode of the present disclosure after it has been patterned. [Figure 5b] FIG. 5b is a cross-sectional view taken along the line AA in FIG. 5a. [Figure 6a] FIG. 6a is a schematic diagram of the second insulating layer of the present disclosure after it has been patterned. [Figure 6b] FIG. 6b is a cross-sectional view taken along the line AA in FIG. 6a. [Figure 7a] FIG. 7a is an exemplary schematic diagram of another local structure of a display substrate according to an embodiment of the present disclosure. [Figure 7b] FIG. 7b is a cross-sectional view taken along the line AA in FIG. 7a. [Figure 8a] FIG. 8a is an exemplary schematic diagram of yet another local structure of a display substrate according to an embodiment of the present disclosure. [Figure 8b] FIG. 8b is a cross-sectional view taken along the line AA in FIG. 8a. [Figure 9a] FIG. 9a is an exemplary schematic diagram of yet another local structure of a display substrate according to an embodiment of the present disclosure. [Figure 9b] FIG. 9b is a cross-sectional view taken along the line AA in FIG. 9a. [Figure 10a] FIG. 10a is an exemplary schematic diagram of yet another local structure of a display substrate according to an embodiment of the present disclosure. [Figure 10b] FIG. 10b is a cross-sectional view taken along the line AA in FIG. 10a. [Figure 11] FIG. 11 is a diagram showing the overall layout of a display substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0031] Hereinafter, embodiments will be described with reference to the drawings. The embodiments can be implemented in a number of different forms. Those skilled in the art will readily understand that the form and details of the present disclosure can be modified in various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the following description of the embodiments. The examples described below do not limit the present disclosure, but are merely intended to explain and interpret the present disclosure. The examples and features of the examples in the present disclosure can be combined with each other unless they are inconsistent.

[0032] In the drawings, for clarity, the size of each component, the thickness of a layer, or the area may be exaggerated. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of each member in the drawings do not represent actual proportions. Note that the drawings illustrate ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, etc. shown in the drawings.

[0033] In this disclosure, ordinal numbers such as "first," "second," and "third" are not used to limit the quantity but are used to avoid confusion of elements.

[0034] In this disclosure, for convenience, terms indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," are used to describe the positional relationships of components with reference to the drawings. These terms are merely intended to facilitate and simplify the description of the present specification, and are not intended to indicate or imply that a specified device or element necessarily has a specific orientation or is constructed and operated in a specific orientation, and are not intended to limit the present disclosure. The positional relationships of components may be changed as appropriate depending on the direction in which each component is described. Therefore, the terms are not limited to those described in the specification and may be changed as appropriate depending on the situation.

[0035] In this disclosure, a transistor is an element having at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and is capable of passing a current through the drain electrode, channel region, and source electrode. In this disclosure, a channel region refers to a region through which a current mainly flows.

[0036] The functions of "source electrode" and "drain electrode" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes in circuit operation, etc. Therefore, in this disclosure, "source electrode" and "drain electrode" are interchangeable.

[0037] In the present disclosure, "electrically connected" includes cases where components are connected by an element having some kind of electrical function. The "element having some kind of electrical function" is not particularly limited as long as it allows transmission and reception of electrical signals between the connected components. Examples of the "element having some kind of electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0038] In this disclosure, "parallel" refers to the angle between two lines being between -10° and 10°, and therefore includes the angle between -5° and 5°. "Perpendicular" refers to the angle between two lines being between 80° and 100°, and therefore includes the angle between 85° and 95°.

[0039] In the present disclosure, the terms "film" and "layer" are interchangeable. For example, a "conductive layer" may be referred to as a "conductive film." Similarly, an "insulating film" may be referred to as an "insulating layer."

[0040] In the present disclosure, for example, if the conductivity is sufficiently low, a "semiconductor" may have the properties of an "insulator." Note that, since the boundary between "semiconductor" and "insulator" is not clear, it may not be possible to accurately distinguish between "semiconductor" and "insulator." Therefore, a "semiconductor" in the present disclosure may be referred to as an "insulator." Similarly, an "insulator" in the present disclosure may be referred to as a "semiconductor." Furthermore, an "insulator" in the present disclosure may be referred to as a "semi-insulator."

[0041] In the present disclosure, for example, if the conductivity is sufficiently high, a "semiconductor" may have the properties of a "conductor." Also, since the boundary between a "semiconductor" and a "conductor" is not clear, it may not be possible to accurately distinguish between a "semiconductor" and a "conductor." Therefore, a "semiconductor" in the present disclosure may be referred to as a "conductor." Similarly, a "conductor" in the present disclosure may be referred to as a "semiconductor."

[0042] In this disclosure, impurities in semiconductors refer to elements other than the main components of the semiconductor. For example, elements with a concentration of less than 0.1 atomic % are considered impurities. When a semiconductor contains impurities, density of states (DOS) may be formed in the semiconductor, potentially reducing carrier mobility and crystallinity. When a semiconductor contains an oxide semiconductor, examples of impurities that change the semiconductor's properties include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components. Representative examples include hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In oxide semiconductors, the inclusion of impurities such as hydrogen can cause oxygen defects. When a semiconductor contains silicon, examples of impurities that change the semiconductor's properties include oxygen and Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements other than hydrogen.

[0043] Currently, in the structure of a display substrate, the overlapping portion of the gate electrode and source electrode is usually used as the two plates of the storage capacitor, and the gate insulating layer is used as the dielectric. STTo increase the capacitance of a display device, measures such as increasing the overlap area of ​​the electrodes, selecting a high-k material for the gate insulating layer, or reducing the thickness of the gate insulating layer are typically used. However, increasing the overlap area of ​​the electrodes not only contradicts the requirement for high resolution, but also reduces design margins, increases process difficulty, reduces yields, and degrades display quality. While selecting a high-k material for the gate insulating layer increases the capacitance of the storage capacitor, the high-k material significantly impacts the performance of transistors in other areas of the display substrate, thereby degrading display quality. Reducing the thickness of the gate insulating layer also increases the process flow and is incompatible with the self-aligned doping process, thereby degrading display quality.

[0044] In order to effectively increase the capacitance of a storage capacitor while ensuring display quality, an embodiment of the present disclosure provides a display substrate, which includes a base, and a plurality of sub-pixels arranged on the base in a direction parallel to the base, each sub-pixel corresponding to a different color, and each sub-pixel includes a pixel driving circuit and an organic electroluminescent diode (OLED) electrically connected to the pixel driving circuit.

[0045] 1 is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure. As shown in FIG. 1, the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor C STThe first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor. The first transistor T1 has a gate electrode coupled to a first scan line Gn, a first electrode coupled to a data line Dn, and a second electrode coupled to a gate electrode of the second transistor T2, and the first transistor T1 receives a data signal transmitted through the data line Dn under the control of the first scan line Gn, and the gate electrode of the second transistor T2 receives the data signal. The second transistor T2 has a gate electrode coupled to the second electrode of the first transistor T1, a first electrode coupled to a first power supply voltage line VDD, and a second electrode coupled to a first electrode of the OLED, and the second transistor T2 generates a corresponding current at its second electrode under the control of the data signal received at its gate electrode. The third transistor T3 has a gate electrode coupled to the second scan line Sn, a first electrode connected to the compensation line Se, and a second electrode coupled to the second electrode of the second transistor T2. The third transistor T3 extracts the threshold voltage Vth and mobility of the second transistor T2 according to the compensation timing and compensates the threshold voltage Vth. The OLED has a first electrode coupled to the second electrode of the second transistor T2 and a second electrode coupled to the second power supply voltage line VSS. The OLED emits light of a corresponding brightness in response to the current of the second electrode of the second transistor T2. The storage capacitor C ST has a first electrode coupled to the gate electrode of the second transistor T2, a second electrode coupled to the second electrode of the second transistor T2, and a storage capacitor C ST is used to store the potential of the gate electrode of the second transistor T2.

[0046] Here, the voltage of the first power supply voltage line VDD is higher than the voltage of the second power supply voltage line VSS, the maximum voltage of the data signal on the data line Dn is lower than the maximum voltage of the first scanning line Gn, and the maximum voltage of the data signal on the data line Dn is lower than the voltage of the first power supply voltage line VDD.

[0047] In a direction perpendicular to the base, a display substrate according to an embodiment of the present disclosure comprises a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer, and a second metal layer stacked together. The metal oxide layer comprises a first pattern serving as an active layer of the first transistor, a second pattern serving as an active layer of the second transistor, and a capacitor pattern serving as a first electrode of the storage capacitor. The first metal layer comprises a first plate serving as one second electrode of the storage capacitor, and the orthogonal projection of the first plate at the base and the orthogonal projection of the capacitor pattern at the base have at least a first overlapping area, forming a first storage capacitor. The second metal layer comprises a second plate serving as the other second electrode of the storage capacitor, and the orthogonal projection of the second plate at the base and the orthogonal projection of the capacitor pattern at the base have at least a second overlapping area, forming a second storage capacitor. The first plate and the second plate have the same potential, thereby forming the first storage capacitor and the second storage capacitor connected in parallel.

[0048] In the display substrate according to the embodiment of the present disclosure, the metal oxide layer forms the first electrode plate of the first metal layer and the second electrode plate of the second metal layer, respectively, to form the first storage capacitor and the second storage capacitor, and since the first electrode plate and the second electrode plate have the same potential, the first storage capacitor and the second storage capacitor are formed to be connected in parallel, thereby effectively increasing the capacitance of the storage capacitor, and helping to realize high-resolution display without affecting the display quality.

[0049] The display substrate according to the embodiments of the present disclosure may be realized in a number of ways, which will be described in more detail in the following embodiments.

[0050] 2a is an exemplary schematic diagram of a local structure of a display substrate according to an embodiment of the present disclosure. 2b is a cross-sectional view taken along the AA direction of FIG. 2a. As shown in FIGS. 2a and 2b, the display substrate according to this embodiment includes a base 10, a first metal layer, a first insulating layer 12, a metal oxide layer, a gate insulating layer 15, a first scan line Gn, a second scan line Sn, a first gate electrode 16, a second gate electrode 26, a third gate electrode 36, a second insulating layer 17, and a second metal layer. The first metal layer is disposed on the base 10 and includes a first electrode plate 11 and a connecting line 40, the first electrode plate 11 being a second electrode of a storage capacitor, forming a first storage capacitor; a first insulating layer 12 covering the first electrode plate 11 and the first metal layer comprising the connecting wires 40; The metal oxide layer is disposed on the first insulating layer 12, and includes a first pattern corresponding to the first active layer 13, a second pattern corresponding to the second active layer 23, a third pattern corresponding to the third active layer 33, and a capacitor pattern corresponding to the capacitor plate 14, wherein the orthogonal projection of the capacitor plate 14 on the base 10 and the orthogonal projection of the first plate 11 on the base 10 have a first overlapping area, and the capacitor plate 14 is a first electrode of a storage capacitor and is used to form a first storage capacitor together with the first plate 11; the first scanning line Gn, the second scanning line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36 are disposed on a gate insulating layer 15, the pattern of the gate insulating layer 15 is the same as the patterns of the first scanning line Gn, the second scanning line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36, the first gate electrode 16 and the first scanning line Gn have an integral structure, and the third gate electrode 36 and the second scanning line Sn have an integral structure; The second insulating layer 17 covers the first scan line Gn, the second scan line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36, and a plurality of via holes are opened in each of them. The plurality of via holes include a first via hole V1 and a second via hole V2 exposing both ends of the first active layer 13, a third via hole V3 exposing the second gate electrode 26, a fourth via hole V4 exposing the capacitor plate 14, a fifth via hole V5 and a sixth via hole V6 exposing both ends of the second active layer 23, a seventh via hole V7 exposing the first plate 11, an eighth via hole V8 and a ninth via hole V9 exposing both ends of the third active layer 33, and a tenth via hole V10 exposing the connecting line 40. In one exemplary embodiment, the first active layer may be the active layer of the first transistor T1, the second active layer may be the active layer of the second transistor T2, and the third active layer may be the active layer of the third transistor T3.

[0051] The second metal layer is disposed on the second insulating layer 17 and includes a data line Dn, a first power supply voltage line VDD, a first source electrode 18, a first drain electrode 19, a second source electrode 28, a second drain electrode 29, a third source electrode 38, a third drain electrode 39, and a second plate 30. The orthogonal projection of the second plate 30 on the base 10 and the orthogonal projection of the capacitor plate 14 on the base 10 have a second overlapping region. The second plate 30 serves as the other second electrode of the storage capacitor and forms a second storage capacitor together with the capacitor plate 14. The first source electrode 18 and the data line Dn are integrally formed, the second source electrode 28 and the first power supply voltage line VDD are integrally formed, and the second drain electrode 29, the third drain electrode 39, and the second plate 30 are integrally formed. The first source electrode 18 is connected to one end of the first active layer 13 through the first via hole V1, the first drain electrode 19 is connected to the other end of the first active layer 13 through the second via hole V2, the first drain electrode 19 is connected to the second gate electrode 26 through the third via hole V3, and the first drain electrode 19 is further connected to the capacitor plate 14 through the fourth via hole V4. The second source electrode 28 is connected to one end of the second active layer 23 through the fifth via hole V5, and the second drain electrode 29 is connected to the other end of the second active layer 23 through the sixth via hole V6. The third source electrode 38 is connected to one end of the third active layer 33 through the eighth via hole V8 and to the connecting line 40 through the tenth via hole V10, and the third drain electrode 39 is connected to the other end of the third active layer 33 through the ninth via hole V9. The second electrode plate 30 is connected to the first electrode plate 11 through the seventh via hole V7, and the first electrode plate 11 and the second electrode plate 30 have the same potential.

[0052] In one exemplary embodiment, the first source electrode 18 may be the source electrode of the first transistor T1, the first drain electrode 19 may be the drain electrode of the first transistor T1, the second source electrode 28 may be the source electrode of the second transistor T2, the second drain electrode 29 may be the drain electrode of the second transistor T2, the third source electrode 38 may be the source electrode of the third transistor T3, and the third drain electrode 39 may be the drain electrode of the third transistor T3.

[0053] In one exemplary embodiment, the source electrode of the first transistor T1 may be the first electrode or the second electrode of the first transistor T1, the drain electrode of the first transistor T1 may be the second electrode or the first electrode of the first transistor T1, the source electrode of the second transistor T2 may be the first electrode or the second electrode of the second transistor T2, the drain electrode of the second transistor T2 may be the second electrode or the first electrode of the second transistor T2, the source electrode of the third transistor T3 may be the first electrode or the second electrode of the third transistor T3, and the drain electrode of the third transistor T3 may be the second electrode or the first electrode of the third transistor T3.

[0054] Here, the capacitor plate 14 is disposed in the same layer as the first active layer 13, the second active layer 23, and the third active layer 33, and is made of the same material and formed by the same patterning process; the second plate 30 is disposed in the same layer as the data line Dn, the first power supply voltage line VDD, the first source electrode 18, the first drain electrode 19, the second source electrode 28, the second drain electrode 29, the third source electrode 38, and the third drain electrode 39, and is made of the same material and formed by the same patterning process.

[0055] In this embodiment, the capacitor plate 14 is the first electrode of the storage capacitor, the first plate 11 is the second electrode of one of the storage capacitors and is also the shielding layer, and the second plate 30 is the second electrode of the other of the storage capacitors, forming two parallel-connected storage capacitors, which are respectively a first storage capacitor between the first plate 11 and the capacitor plate 14, and a second storage capacitor between the second plate 30 and the capacitor plate 14.

[0056] The technical solution of this embodiment will be further described below with reference to the manufacturing process of the display substrate according to this embodiment. The "patterning process" described in this embodiment includes processes such as film layer deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature manufacturing process. The deposition can be performed using known processes such as sputtering, evaporation, and chemical vapor deposition, the coating can be performed using known coating processes, and the etching can be performed using known methods, without limitation. In this description, it should be understood that a "thin film" refers to a single thin film formed by depositing a material on a base or by other processes. If the "thin film" does not require a patterning process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern."

[0057] (1) Forming a pattern of a first metal layer. Forming a pattern of the first metal layer includes depositing a first metal thin film on a base, patterning the first metal thin film through a patterning process, and forming a first metal layer on the base 10 having a pattern of a first electrode plate 11 and a connecting line 40, as shown in Figures 3a and 3b, where Figure 3b is a cross-sectional view taken along the AA direction of Figure 3a. In this embodiment, the first electrode plate 11 is not only a shield layer but also a second electrode of a storage capacitor, and is used to form a first storage capacitor.

[0058] (2) Forming a pattern of a metal oxide layer. Forming a pattern of a metal oxide layer includes sequentially depositing a first insulating thin film and a metal oxide thin film on the patterned base, patterning the metal oxide thin film to form a first insulating layer 12 covering the first electrode plate 11 and the connecting line 40, and forming a pattern of a metal oxide layer on the first insulating layer 12. The metal oxide layer has a pattern of a second active layer 23, a first active layer 13, a third active layer 33, and a capacitor electrode plate 14, as shown in Figures 4a and 4b, where Figure 4b is a cross-sectional view taken along the AA direction in Figure 4a. Here, the first active layer 13 corresponds to the first pattern and is the active layer of the first transistor, the second active layer 23 corresponds to the second pattern and is the active layer of the second transistor, the third active layer 33 corresponds to the third pattern and is the active layer of the third transistor, and the capacitor electrode plate 14 corresponds to the capacitor pattern, and the capacitor pattern is conductively treated to form the first electrode of the storage capacitor. The orthogonal projection of the capacitor plate 14 (capacitor pattern) on the base 10 and the orthogonal projection of the first plate 11 on the base 10 have a first overlapping area, and the first plate 11 forms a first storage capacitor together with the capacitor plate 14 as the second electrode of the storage capacitor. The orthogonal projection of the second active layer 23 (second pattern) serving as the active layer of the second transistor on the base 10 and the orthogonal projection of the first plate 11 on the base 10 have an overlapping area, and the first plate 11 serving as the shielding layer can shield the channel region of the second transistor, preventing light from affecting the channel and preventing light-induced current leakage from affecting the display effect. In this embodiment, the orthogonal projection of the first active layer 13 (first pattern) serving as the active layer of the first transistor on the base 10 is spaced apart from the orthogonal projection of the capacitor plate 14 (capacitor pattern) on the base 10, i.e., there is no overlapping area between them. The orthogonal projection of the first active layer 13 (first pattern) on the base 10 is spaced apart from the orthogonal projection of the first electrode plate 11 on the base 10, i.e., there is no overlapping region between them. In this embodiment, the widths of the first active layer 13 and the second active layer 23 are designed so that the aspect ratio of the channel of the first transistor is smaller than the aspect ratio of the channel of the second transistor.

[0059] (3) Forming a gate electrode pattern. Forming the gate electrode pattern includes sequentially depositing a gate insulating thin film and a gate metal thin film on the patterned base, and then patterning the gate insulating thin film and the gate metal thin film through a patterning process to form a pattern of the gate insulating layer 15 and a pattern of the first scan line Gn, the second scan line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36 arranged on the gate insulating layer 15, where the pattern of the gate insulating layer 15 is the same as the patterns of the first scan line Gn, the second scan line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36, where the second gate electrode 26 is located at a corresponding position on the first electrode plate 11, the first gate electrode 16 is an integral structure connected to the first scan line Gn, and the third gate electrode 36 is an integral structure connected to the second scan line Sn, as shown in Figures 5a and 5b, where Figure 5b is a cross-sectional view taken along the AA direction in Figure 5a.

[0060] (4) Forming a pattern of the second insulating layer. Forming the pattern of the second insulating layer includes depositing a second insulating thin film on the patterned base, patterning the second insulating thin film by a patterning process, and forming a pattern of the second insulating layer 17 covering the structure. The second insulating layer 17 has a plurality of via holes, including a first via hole V1 and a second via hole V2 exposing both ends of the first active layer 13, a third via hole V3 exposing the second gate electrode 26, a fourth via hole V4 exposing the capacitor plate 14, a fifth via hole V5 and a sixth via hole V6 exposing both ends of the second active layer 23, a seventh via hole V7 exposing the first plate 11, an eighth via hole V8 and a ninth via hole V9 exposing both ends of the third active layer 33, and a tenth via hole V10 exposing the connecting line 40, as shown in Figures 6a and 6b, where Figure 6b is a cross-sectional view taken along the AA direction in Figure 6a. In this embodiment, the thickness of the gate insulating layer 15 is smaller than the thickness of the second insulating layer 17, and the thickness of the first insulating layer 12 is smaller than the sum of the thicknesses of the gate insulating layer 15 and the second insulating layer 17, thereby increasing the capacitance of the storage capacitor while ensuring the insulating effect.

[0061] (5) Forming a pattern of the second metal layer. Forming the pattern of the second metal layer includes depositing a second metal thin film on the patterned base, patterning the second metal thin film by a patterning process, and forming a pattern of the second metal layer on the second insulating layer 17. As shown in Figures 2a and 2b, the second metal layer has a pattern of a data line Dn, a first power supply voltage line VDD, a first source electrode 18, a first drain electrode 19, a second source electrode 28, a second drain electrode 29, a third source electrode 38, a third drain electrode 39, and a second electrode plate 30. Here, the first source electrode 18 is an integral structure connected to the data line Dn, the second source electrode 28 is an integral structure connected to the first power supply voltage line VDD, and the second drain electrode 29 and the third drain electrode 39 are an integral structure connected to the second electrode plate 30. The first source electrode 18 is connected to one end of the first active layer 13 through the first via hole V1, the first drain electrode 19 is connected to the other end of the first active layer 13 through the second via hole V2, the first drain electrode 19 is connected to the second gate electrode 26 through the third via hole V3, and the first drain electrode 19 is further connected to the capacitor plate 14 through the fourth via hole V4. The second source electrode 28 is connected to one end of the second active layer 23 through the fifth via hole V5, and the second drain electrode 29 is connected to the other end of the second active layer 23 through the sixth via hole V6. The third source electrode 38 is connected to one end of the third active layer 33 through the eighth via hole V8 and to the connecting line 40 through the tenth via hole V10, and the third drain electrode 39 is connected to the other end of the third active layer 33 through the ninth via hole V9. The second plate 30 is connected to the first plate 11 through the seventh via hole V7, and the orthogonal projection of the second plate 30 on the base 10 and the orthogonal projection of the capacitor plate 14 on the base 10 form a second overlapping region, which serves as the other second electrode of the storage capacitor and is used to form a second storage capacitor together with the capacitor plate 14. In this embodiment, the thickness of the second metal layer is greater than the thickness of the gate metal layer.

[0062] In this embodiment, the first metal layer, the gate metal layer, and the second metal layer may be made of any of chromium (Cr), gold (Au), zinc (Zn), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt (Co), etc., or an alloy containing any of the above metal elements, or an alloy containing a combination of the above metal elements, such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb), or a multilayer metal such as Mo / Cu / Mo may be used. In one exemplary embodiment, a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used. Using a Cu-X alloy film allows for thin film processing by a wet etching process, thereby reducing manufacturing costs. In one exemplary embodiment, a Cu-Mn alloy film is used. The first metal layer has a thickness of 800 to 1200 angstroms, the gate metal layer has a thickness of 3000 to 5000 angstroms, and the second metal layer has a thickness of 3000 to 9000 angstroms.

[0063] The first insulating layer, gate insulating layer, and second insulating layer may be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or the like, or may be made of aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), yttrium oxide, zirconium oxide, gallium oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, or the like. Here, the thickness of the first insulating layer is 3000 to 5000 angstroms, the thickness of the gate insulating layer is 1000 to 2000 angstroms, and the thickness of the second insulating layer is 4500 to 7000 angstroms.

[0064] In this embodiment, the metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium, gallium, and zinc.

[0065] The metal oxide layer may be an oxide semiconductor containing indium (In), which can improve carrier mobility (electron mobility). The oxide semiconductor may also contain element M. The element M may be aluminum, gallium, yttrium, tin, or the like. Other elements that can be used as element M include boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. The element M may be a combination of two or more of the above elements. The element M is, for example, an element having a high bond energy with oxygen. The element M is an element having a higher bond energy with oxygen than indium. Alternatively, the element M is, for example, an element having a function of increasing the energy gap of the oxide semiconductor. The metal oxide layer may also contain zinc (Zn), which makes the oxide semiconductor more likely to crystallize. In one exemplary embodiment, the oxide semiconductor is not limited to an oxide semiconductor containing indium, but may be an oxide semiconductor containing zinc, gallium, or tin without containing indium, such as zinc tin oxide or gallium tin oxide.

[0066] When the metal oxide layer is an In-M-Zn oxide, if the sum of In and M is 100 atomic %, In may be less than 50 atomic % and M may be 50 atomic % or more. The metal oxide layer uses an oxide with a large energy gap, for example, 2.5 eV to 4.2 eV, or 2.8 eV to 3.8 eV, or 3 eV to 3.5 eV. In one exemplary embodiment, the metal oxide layer is an oxide containing indium (In), M, and zinc (Zn), where M is aluminum (Al), gallium (Ga), or tin (Sn).

[0067] In this embodiment, the active layers of the first, second, and third transistors may have the same or substantially the same composition to reduce manufacturing costs. This embodiment is not limited thereto, and the active layers of the three transistors may have different compositions. If the active layers of the three transistors have a region in which the atomic percentage of In is greater than the atomic percentage of M, the field-effect mobility of the first and second transistors can be improved. For example, one or both of the field-effect mobilities of the first and second transistors may exceed 10 cm2 / Vs, e.g., 30 cm2 / Vs. For example, when the high field-effect mobility transistor is used in a gate driver that generates gate signals for a display device, the display device can have a narrower frame. When the high field-effect mobility transistor is used in a source driver that supplies signals from signal lines included in a display device, the number of wirings connected to the display device can be reduced. When the high field-effect mobility transistor is used as a transistor in a pixel circuit included in a display device, the display quality of the display device can be improved.

[0068] In one exemplary embodiment, the metal oxide layer of this embodiment may be a single layer, a double layer, or a multilayer. When the metal oxide layer is a double layer, it comprises a first oxide layer and a second oxide layer stacked together. The second oxide layer has a lower conductivity than the first oxide layer and a larger bandgap than the first oxide layer. The first oxide layer may be a main channel layer through which electrons move and may therefore be configured to be adjacent to the first, second, and third gate electrodes. When the metal oxide layer is a single layer, an indium gallium zinc oxide (IGZO) material may be used.

[0069] In this embodiment, part of the metal oxide layer is used as the active layer of the transistor, and the other part is used as the first electrode of the storage capacitor. Therefore, when conducting the conductive process, on the one hand, the channel direction and shape of different subpixels can be differentiated to accommodate designs with different aspect ratios, for example, by designing the widths of the first and second active layers so that the aspect ratio of the channel of the first transistor is smaller than that of the channel of the second transistor. On the other hand, in different regions of a subpixel, the metal oxide layer has different component contents to meet different electrical property requirements.

[0070] The above-described conductive treatment involves forming a pattern, such as the first, second, and third gate electrodes, and then performing a plasma treatment using the first, second, and third gate electrodes as a mask to treat the metal oxide layer in the corresponding regions as a conductive layer. As shown in Figures 4a and 5a, the metal oxide layer can be divided into three regions: the first region includes the region overlapping with the first, second, and third gate electrodes and serves as the channel region of the transistor; the second region includes the region adjacent to the first region, i.e., the region adjacent to the first, second, and third gate electrodes but not covered by the first, second, and third gate electrodes and serves as the source / drain region of the transistor; and the third region includes the region overlapping with the first and second plates and serves as the plate region of the storage capacitor. In this example, the indium gallium zinc oxide (IGZO) compositions in the three regions are different.

[0071] In this example, the oxygen content of the first region is in the range of 30 to 50 atomic %, the oxygen content of the second region is in the range of 50 to 60 atomic %, and the oxygen content of the second region is in the range of 60 to 70 atomic %. In one exemplary embodiment, the oxygen content of the IGZO in the first region is less than the oxygen content of the IGZO in the second region, and the oxygen content of the IGZO in the second region is less than the oxygen content of the IGZO in the third region. The zinc content of the IGZO in the first region is greater than the zinc content of the IGZO in the second region, and the zinc content of the IGZO in the second region is greater than the zinc content of the IGZO in the third region. In one exemplary embodiment, the atomic ratio of oxygen to zinc elements (O / Zn) in the first region is smaller than the O / Zn in the second region, and the O / Zn in the second region is smaller than the O / Zn in the third region. In addition, the oxide in the first region is mainly a semiconductor, and by increasing the In element content, the carrier concentration is significantly increased, and in order to increase the carrier concentration in the first region and improve the driving capability of the transistor, the In atomic content in the first region is greater than the In atomic content in the second region, which in turn is greater than the In atomic content in the third region.

[0072] The following table shows examples of indium gallium zinc oxide (IGZO) compositions in three regions, where Weight% represents the proportion of an element in the oxide and Atomic% represents the atomic percentage of the element in the oxide.

[0073] [Table 1]

[0074] Here, the first region is the channel region of at least one of the three transistors, the second region is the source / drain region of at least one of the three transistors, and the third region is the plate region of the storage capacitor. As shown in the table above, IGZO contains elements such as oxygen (O), zinc (Zn), gallium (Ga), and indium (In). Because the first region was not plasma-treated due to shielding by the gate electrode, the relative weight contents of the elements O:Zn:Ga:In are 11.82:25.68:28.38:34.12, and the relative atomic contents are 40.24:21.40:22.18:16.18. Because the third region was plasma-treated without shielding, the relative weight contents of the elements O:Zn:Ga:In are 23.35:18.72:25.66:32.24, and the relative atomic contents are 60.94:11.95:15.37:11.72. After plasma treatment, the oxygen content and atomic weight of the IGZO in the third region increases significantly, while the zinc (Zn) content and atomic weight of the IGZO decreases, improving the conductivity of the IGZO. Although the second region is not shielded by the gate electrode, it is adjacent to the gate electrode and is affected by it. Therefore, the oxygen content and atomic weight of the IGZO in the second region is lower than that in the third region, and the zinc (Zn) content and atomic weight of the IGZO in the second region is higher than that in the third region. Therefore, the conductivity of the IGZO in the second region is lower than that of the IGZO in the third region.

[0075] The metal oxide layer in the third region serves as the first electrode of the storage capacitor, and therefore requires excellent conductivity, i.e., a good degree of conductivity. When performing plasma treatment using the gate electrode as a mask, theoretically, regions farther from the gate electrode have a better degree of conductivity and thus superior conductivity. Therefore, in this embodiment, the minimum distance between the metal oxide layer in the third region (capacitor plate 14) and the first gate electrode 16 may be set to be greater than the width L1 of the first gate electrode 16, the minimum distance between the capacitor plate 14 and the second gate electrode 26 may be set to be greater than the width L2 of the second gate electrode 26, and the minimum distance between the capacitor plate 14 and the third gate electrode 36 may be set to be greater than the width L3 of the third gate electrode 36. In this way, plasma treatment of the metal oxide layer in the third region is not affected by the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36, thereby maximizing the degree of conductivity of the metal oxide layer in the third region. Note that these distances are in both directions perpendicular to the substrate. In a modified embodiment, depending on the design needs of a high-resolution backplane, the minimum distance between the metal oxide layer (capacitor plate 14) in the third region and the first gate electrode 16 may be greater than L1, the minimum distance between the capacitor plate 14 and the second gate electrode 26 may be greater than L2, and the minimum distance between the capacitor plate 14 and the third gate electrode 36 may be greater than L3. These three designs may satisfy any two or one of these situations. In another exemplary embodiment, the overlapping pattern of the capacitor plate 14 with the first and second electrodes may be designed to satisfy the above relationship. L1 is the width of the first gate electrode 16, L2 is the width of the second gate electrode 26, and L3 is the width of the third gate electrode 36. In this way, the plasma treatment of the metal oxide layer in the third region is less affected by the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36, and maximizes the degree of conductivity of the metal oxide layer in the third region.

[0076] As can be seen from the structure and manufacturing process of the display substrate of this embodiment, in this embodiment, the capacitor plate 14 using metal oxide material is the first electrode of the storage capacitor, the first plate 11 of the first metal layer is the second electrode of one of the storage capacitors, and the second plate 30 of the second metal layer is the second electrode of the other of the storage capacitors. The second plate 30 is connected to the first plate 11 through the seventh via hole V7, so that the first plate 11 and the second plate 30 have the same potential, and are the first electrodes of the storage capacitors. 14 is connected to the second gate electrode 26 through the third via hole V3, the first drain electrode 19, and the fourth via hole V4 and has a voltage different from that of the first plate 11 and the second plate 30. Therefore, two parallel-connected storage capacitors are formed between the first plate 11, the capacitor plate 14, and the second plate 30. The two parallel-connected capacitors are a first storage capacitor between the first plate 11 and the capacitor plate 14, and a second storage capacitor between the second plate 30 and the capacitor plate 14. A transparent electrode layer (not shown) is also formed on the second plate 30, and a third capacitor is also formed between the transparent electrode layer and the capacitor plate 14. Therefore, in this embodiment, three parallel-connected storage capacitors are actually formed. As can be seen, compared to the original structure, the storage capacitor according to the embodiment of the present disclosure is formed by connecting three capacitors in parallel, thereby maximizing the capacitance of the storage capacitor. In this embodiment, the capacitor plate 14 serving as the first electrode of the storage capacitor is disposed in the same layer as the active layer and is located between the first metal layer and the second metal layer, so that the distance between the capacitor plate 14 and the first plate 11 is short, separating them only by the first insulating layer 12, and the distance between the capacitor plate 14 and the second plate 30 is also short, separating them only by the second insulating layer 17. Because the insulating layer is thin and the area of ​​the first plate 11 serving as the shield layer is large, the capacitance of each storage capacitor in the present disclosure is greater than that of storage capacitors with existing structures, and even when applied to small pixel sizes, the required storage capacitor capacitance can be ensured, which helps to achieve high-resolution display.Since neither the first insulating layer 12 nor the second insulating layer 17 needs to use a high dielectric constant material or have a thin thickness, the structural design of the embodiments of the present disclosure does not increase the process flow, is compatible with the self-aligned doping process, does not affect the performance of the thin film transistor, and can ensure the display quality.

[0077] In one exemplary embodiment, the patterning number of the display substrate manufactured in this embodiment is the same as the patterning number of the original manufacturing method, and existing process equipment can be used to implement this embodiment, resulting in high process compatibility, high practicality, and excellent future applicability.

[0078] As described above, this embodiment effectively increases the capacitance of the storage capacitor while ensuring the display quality, which is helpful in realizing a high-resolution display.

[0079] Figure 7a is an exemplary schematic diagram of another local structure of a display substrate according to an embodiment of the present disclosure. Figure 7b is a cross-sectional view taken along the AA direction of Figure 7a. This embodiment includes a capacitor plate serving as a first electrode of a storage capacitor, a shield layer and a first plate serving as a second electrode of one of the storage capacitors, and a second plate serving as a second electrode of the other of the storage capacitors. A first storage capacitor is formed between the first plate and the capacitor plate, and a second storage capacitor is formed between the second plate and the capacitor plate. The first storage capacitor and the second storage capacitor are connected in parallel to form a storage capacitor. As shown in Figures 7a and 7b, in this embodiment, the capacitor plate 14 and the first active layer 13 (first pattern) may be an integral structure, i.e., the capacitor plate 14 and the first active layer 13 are formed of a continuous metal oxide, and a fourth via hole is omitted. For example, the display substrate of this embodiment includes a base 10, a first electrode plate 11, a connecting line 40, a first insulating layer 12, a metal oxide layer, a gate insulating layer 15, a first scanning line Gn, a second scanning line Sn, a first gate electrode 16, a second gate electrode 26, a third gate electrode 36, a second insulating layer 17, and a second metal layer; The structures of the base 10, the first electrode plate 11, the connecting wire 40, and the first insulating layer 12 can be referred to the explanations in the above embodiments. The metal oxide layer is disposed on the first insulating layer 12, and includes a first active layer 13, a second active layer 23, a third active layer 33, and a capacitor plate 14, the first active layer 13 and the capacitor plate 14 being an integral structure, and the orthogonal projection of the capacitor plate 14 on the base 10 and the orthogonal projection of the first plate 11 on the base 10 have a first overlapping area, the capacitor plate 14 is a first electrode of a storage capacitor and is used to form a first storage capacitor together with the first plate 11; Regarding the gate insulating layer 15, the first scanning line Gn, the second scanning line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36 arranged on the gate insulating layer 15, the structures thereof may be referred to the explanations in the above embodiments. The second insulating layer 17 covers the first scanning line Gn, the second scanning line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36, and a plurality of via holes are opened in each of them. In this embodiment, the fourth via hole of the above embodiment is omitted, or the second via hole and the fourth via hole of the above embodiment can be understood as the via hole of the integrated structure of this embodiment. The second metal layer is disposed on the second insulating layer 17 and includes a data line Dn, a first power supply voltage line VDD, a first source electrode 18, a first drain electrode 19, a second source electrode 28, a second drain electrode 29, a third source electrode 38, a third drain electrode 39, and a second plate 30. The orthogonal projection of the second plate 30 on the base 10 and the orthogonal projection of the capacitor plate 14 on the base 10 have a second overlapping region. The second plate 30 serves as the other second electrode of the storage capacitor and forms a second storage capacitor together with the capacitor plate 14. The first source electrode 18 and the data line Dn are integrally formed, the second source electrode 28 and the first power supply voltage line VDD are integrally formed, and the second drain electrode 29, the third drain electrode 39, and the second plate 30 are integrally formed. The first source electrode 18 is connected to one end of the first active layer 13 through the first via hole V1, and the first drain electrode 19 is connected to the other end of the first active layer 13 (also the capacitor plate 14) through an integral via hole, and the first drain electrode 19 is connected to the second gate electrode 26 through the third via hole V3. The second source electrode 28 is connected to one end of the second active layer 23 through the fifth via hole V5, and the second drain electrode 29 is connected to the other end of the second active layer 23 through the sixth via hole V6. The third source electrode 38 is connected to one end of the third active layer 33 through the eighth via hole V8 and to the connecting line 40 through the tenth via hole V10, and the third drain electrode 39 is connected to the other end of the third active layer 33 through the ninth via hole V9. The second plate 30 is connected to the first plate 11 through the seventh via hole V7.

[0080] This embodiment can also increase the capacitance of the storage capacitor, which is useful for realizing high-resolution display and ensuring display quality. In addition, this embodiment not only eliminates the need for a fourth via hole and simplifies the via hole etching process, which is useful for realizing high-resolution design, but also increases the area of ​​the capacitor plate by forming the capacitor plate and the second active layer, which are originally spaced apart, into an integral structure, thereby further increasing the overall capacitance of the storage capacitor.

[0081] The manufacturing process of the display substrate of this embodiment can be referred to the description in the above embodiment. In this embodiment, in the process of forming the pattern of the active layer and the capacitor plate, the second active layer and the capacitor plate are an integrated structure, in the process of forming the pattern of the second insulating layer, there is no need to form a fourth via hole, and in the process of forming the pattern of the second metal layer, the second drain electrode is connected to the second active layer only through the second via hole and to the first gate electrode through the third via hole, and the description here is omitted.

[0082] FIG. 8a is a schematic diagram illustrating another local structure of a display substrate according to an embodiment of the present disclosure. FIG. 8b is a cross-sectional view taken along the AA direction of FIG. 8a. This embodiment includes a capacitor plate serving as a first electrode of a storage capacitor, a shield layer and a first plate serving as a second electrode of one of the storage capacitors, and a second plate serving as a second electrode of the other of the storage capacitors. A first storage capacitor is formed between the first plate and the capacitor plate, and a second storage capacitor is formed between the second plate and the capacitor plate. The first storage capacitor and the second storage capacitor are connected in parallel to form a storage capacitor. As shown in FIGS. 8a and 8b, in this embodiment, the capacitor plate 14 and the first active layer 13 may be disposed in an integral structure. The third and fourth via holes may be omitted, or the second, third, and fourth via holes may be understood to be integrally formed. For example, the display substrate of this embodiment includes a base 10, a first electrode plate 11, a connecting line 40, a first insulating layer 12, a metal oxide layer, a gate insulating layer 15, a first scanning line Gn, a second scanning line Sn, a first gate electrode 16, a second gate electrode 26, a third gate electrode 36, a second insulating layer 17, and a second metal layer; The structures of the base 10, the first electrode plate 11, the connecting wire 40, and the first insulating layer 12 can be referred to the explanations in the above embodiments. The metal oxide layer is disposed on the first insulating layer 12, and includes a first active layer 13, a second active layer 23, a third active layer 33, and a capacitor plate 14, the first active layer 13 and the capacitor plate 14 being an integral structure, and the orthogonal projection of the capacitor plate 14 on the base 10 and the orthogonal projection of the first plate 11 on the base 10 have a first overlapping area, the capacitor plate 14 is a first electrode of a storage capacitor and is used to form a first storage capacitor together with the first plate 11; The first scanning line Gn, the second scanning line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36 are disposed on a gate insulating layer 15, the pattern of the gate insulating layer 15 is the same as the patterns of the first scanning line Gn, the second scanning line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36, the first gate electrode 16 has an integral structure connected to the first scanning line Gn, the third gate electrode 36 has an integral structure connected to the second scanning line Sn, and the second gate electrode 26 has a bent line shape, The second insulating layer 17 covers the first scan line Gn, the second scan line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36, and a plurality of via holes are opened in each of them. The plurality of via holes include a first via hole V1 exposing one end of the first active layer 13, a second via hole V2 exposing the other end of the first active layer 13 and the second gate electrode 26 at the same time, a fifth via hole V5 and a sixth via hole V6 exposing both ends of the second active layer 23, a seventh via hole V7 exposing the first electrode plate 11, an eighth via hole V8 and a ninth via hole V9 exposing both ends of the third active layer 33, and a tenth via hole V10 exposing the connecting line 40. Alternatively, the second via hole, the third via hole, and the fourth via hole in the above embodiment can be understood to be the via holes of the integral structure in this embodiment. The second metal layer is disposed on the second insulating layer 17 and includes a data line Dn, a first power supply voltage line VDD, a first source electrode 18, a first drain electrode 19, a second source electrode 28, a second drain electrode 29, a third source electrode 38, a third drain electrode 39, and a second plate 30. The orthogonal projection of the second plate 30 on the base 10 and the orthogonal projection of the capacitor plate 14 on the base 10 have a second overlapping region. The second plate 30 serves as the other second electrode of the storage capacitor and forms a second storage capacitor together with the capacitor plate 14. The first source electrode 18 and the data line Dn are integrally formed, the second source electrode 28 and the first power supply voltage line VDD are integrally formed, and the second drain electrode 29, the third drain electrode 39, and the second plate 30 are integrally formed. The first source electrode 18 is connected to one end of the first active layer 13 through the first via hole V1, and the first drain electrode 19 is simultaneously connected to the other end of the first active layer 13 and the second gate electrode 26 through an integral via hole. The second source electrode 28 is connected to one end of the second active layer 23 through the fifth via hole V5, and the second drain electrode 29 is connected to the other end of the second active layer 23 through the sixth via hole V6. The third source electrode 38 is connected to one end of the third active layer 33 through the eighth via hole V8 and to the connecting line 40 through the tenth via hole V10, and the third drain electrode 39 is connected to the other end of the third active layer 33 through the ninth via hole V9. The second electrode 30 is connected to the first electrode plate 11 through the seventh via hole V7.

[0083] This embodiment can also increase the capacitance of the storage capacitor, which is useful for realizing high-resolution display and ensuring display quality. In addition, this embodiment integrates the capacitor plate and the second active layer to have the same potential, omitting the third and fourth via holes and retaining only the second via hole, and the second drain electrode is simultaneously connected to the second active layer and the first gate electrode through the second via hole, which not only simplifies the process and helps realize high-resolution design, but also increases the area of ​​the capacitor plate and the second active layer, which are originally spaced apart, by forming them into an integrated structure, which increases the area of ​​the capacitor plate and the second metal layer, thereby further increasing the capacitance of the entire storage capacitor.

[0084] The manufacturing process of the display substrate of this embodiment can be referred to the description in the above embodiment. In this embodiment, in the process of forming the pattern of the active layer and the capacitor plate, the second active layer and the capacitor plate are an integral structure; in the process of forming the pattern of the second insulating layer, an integral via hole is formed that simultaneously exposes the second active layer and the first gate electrode; in the process of forming the pattern of the source / drain electrode and the second metal layer, the second drain electrode is simultaneously connected to the second active layer and the first gate electrode through the integral via hole, and the description here is omitted.

[0085] FIG. 9a is an exemplary schematic diagram of yet another local structure of a display substrate according to an embodiment of the present disclosure. FIG. 9b is a cross-sectional view taken along the AA direction in FIG. 9a. As shown in FIGS. 9a and 9b, in this embodiment, two second gate electrodes 26 are formed at the position of the first drain electrode 19. For example, in this embodiment, the second gate electrodes 26 are bent-line shaped, and two second gate electrodes 26 are formed at the position of the second transistor. An integrated via hole opened in the second insulating layer 17 simultaneously exposes the two second gate electrodes 26 and the first active layer 13, and the first drain electrode 19 is simultaneously connected to the first active layer 13 and the two second gate electrodes 26 through the integrated via hole. The integrated via hole exposes the first active layer 13 in the region between the two second gate electrodes 26 and simultaneously exposes the second gate electrodes 26 in the portions adjacent to the two second gate electrodes 26.

[0086] This embodiment can also increase the capacitance of the storage capacitor, which helps to realize high-resolution display and ensure display quality. In addition, in this embodiment, the two first gate electrodes are arranged to reduce the size of the second via hole, improve connection reliability, and help to realize a higher-resolution design.

[0087] For the manufacturing process of the display substrate of this embodiment, it is sufficient to refer to the explanation in the above embodiment. In this embodiment, in the process of forming patterns such as scanning lines, two first gate electrodes are formed at the position of the second drain electrode, and the explanation is omitted here.

[0088] FIG. 10a is an exemplary schematic diagram of yet another local structure of a display substrate according to an embodiment of the present disclosure. FIG. 10b is a cross-sectional view taken along the AA direction of FIG. 10a. As shown in FIGS. 10a and 10b, the two second gate electrodes 26 in this embodiment are arranged at different positions, respectively, on both sides of a step formed by the first electrode plate 11. For example, the second gate electrode 26 in this embodiment is bent-line shaped, and two second gate electrodes 26 are formed at the position of the second transistor, one above the step formed by the first electrode plate 11 and the other below the step. An integral via hole opened in the second insulating layer 17 simultaneously exposes the two second gate electrodes 26 and the first active layer 13 between the two second gate electrodes 26, and the first drain electrode 19 is simultaneously connected to the first active layer 13 and the two second gate electrodes 26 through the integral via hole.

[0089] This embodiment can also increase the capacitance of the storage capacitor, which helps achieve high-resolution display and ensure display quality. Furthermore, in this embodiment, two first gate electrodes are disposed on both sides of a step formed by the first metal layer, thereby effectively preventing failure due to breakage of the second active layer at the step and improving connection reliability. For example, the first gate electrodes connected to the second drain electrode are disposed both above and below the step, ensuring that the second active layer and the capacitor plate have the same potential even if the second active layer breaks at the step.

[0090] For the manufacturing process of the display substrate according to this embodiment, it is sufficient to refer to the explanation in the above embodiment. In this embodiment, in the process of forming patterns such as scanning lines, the positions of the two first gate electrodes formed at the positions of the second drain electrodes are different, and therefore the explanation is omitted here.

[0091] 11 is a diagram illustrating the overall layout of a display substrate according to an embodiment of the present disclosure. As shown in FIG. 11, a first power supply voltage line VDD, two data lines Dn, and a compensation line Se on the display substrate are parallel to each other and arranged in sequence. A pixel column is formed between the first power supply voltage line VDD and an adjacent data line Dn, and another pixel column is formed between the compensation line Se and an adjacent data line Dn. Thus, one compensation line Se and four data lines Dn are arranged between adjacent first power supply voltage lines VDD, thereby forming four pixel columns. Two of the four data lines Dn are located on one side of the compensation line Se, and the other two are located on the other side of the compensation line Se. Similarly, one first power supply voltage line VDD and four data lines Dn are arranged between adjacent compensation lines Se, thereby forming four pixel columns. Two of the four data lines Dn are located on one side of the first power supply voltage line VDD, and the other two are located on the other side of the first power supply voltage line VDD.

[0092] In an embodiment of the present disclosure, the first power supply voltage line VDD and the compensation line Se both use a 1:4 structure. In one exemplary embodiment, the display substrate further includes a plurality of connecting lines 40, which are disposed in the same layer as the shielding layer of the display substrate (the first plate, which also serves as the second electrode of the storage capacitor) and formed by the same patterning process, and which are perpendicular to the first power supply voltage line VDD (compensation line Se). The plurality of connecting lines 40 connected to the first power supply voltage line VDD through via holes are respectively electrically connected to pixels in pixel columns between the compensation line Se and the data line Dn on both sides of the first power supply voltage line VDD. Since the first power supply voltage line VDD is directly electrically connected to the pixels in pixel columns on both sides of the first power supply voltage line VDD, one first power supply voltage line VDD can supply signals to pixels in four pixel columns. Similarly, the multiple connection lines 40 connected to the compensation line Se through via holes are each electrically connected to pixels in pixel columns between the first power supply voltage line VDD and the data line Dn on both sides of the compensation line Se, and since the compensation line Se is directly and electrically connected to pixels in pixel columns on both sides of the compensation line Se, one compensation line Se can supply signals to pixels in four pixel columns.

[0093] In the display substrate according to the embodiment of the present disclosure, both the first power supply voltage line and the compensation line are designed as a 1:4 structure, which has the advantages of effectively increasing the size of each pixel while maintaining the same resolution, making full use of the layout space, and streamlining the overall layout.

[0094] An embodiment of the present disclosure further provides a display device including the display substrate, which may be a product or component with a display function, such as a mobile phone, a tablet PC, a television, a display, a laptop computer, a digital photo frame, or a navigation system.

[0095] In describing the embodiments of the present disclosure, unless otherwise expressly specified and limited, the terms "mounted," "coupled," and "connected" should be understood in a broad sense. For example, they may be fixedly connected, detachably connected, integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected via an intermediate member, or internally communicated between two elements. Those skilled in the art can understand the meaning of the above terms in the present disclosure depending on the context.

[0096] Although the embodiments disclosed in the present disclosure are as above, the above contents do not limit the present disclosure, but are merely embodiments used to facilitate understanding of the present disclosure. Those skilled in the art can make any modifications and changes to the embodiments and details without departing from the spirit and scope disclosed in the present disclosure, but the patent protection scope of the present disclosure should still comply with the scope defined by the appended claims.

Claims

1. A display substrate, a base; and a plurality of sub-pixels disposed on the base and corresponding to different colors, each sub-pixel comprising a pixel driving circuit and an organic electroluminescent diode electrically connected to the pixel driving circuit; the pixel driving circuit comprises a first transistor, a second transistor, and a storage capacitor, wherein the first transistor has a gate electrode coupled to a first scan line, a first electrode coupled to a data line, and a second electrode coupled to a gate electrode of the second transistor; the second transistor has a first electrode coupled to a first power supply voltage line, a second electrode coupled to a first electrode of the organic electroluminescent diode, and a second electrode of the organic electroluminescent diode coupled to a second power supply voltage line; the storage capacitor has a first electrode coupled to the gate electrode of the second transistor, and a second electrode coupled to a second electrode of the second transistor, the storage capacitor being used to store a potential of the gate electrode of the second transistor; The display substrate includes a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer, and a second metal layer, which are stacked in a direction perpendicular to the base; the metal oxide layer includes a first pattern serving as an active layer of the first transistor, a second pattern serving as an active layer of the second transistor, and a capacitor pattern serving as a first electrode of the storage capacitor, and the metal oxide layer contains gallium; the first metal layer includes a first plate, and an orthogonal projection of the first plate at a base and an orthogonal projection of the capacitor pattern at a base have at least a first overlapping area to form a first storage capacitor; the second metal layer includes a second plate, and the orthogonal projection of the second plate at a base and the orthogonal projection of the capacitor pattern at a base have at least a second overlapping area to form a second storage capacitor; The first and second plates have the same potential.

2. The display substrate of claim 1 , wherein an overlapping area exists between the orthogonal projection of the second pattern on the base and the orthogonal projection of the first electrode plate on the base.

3. The display substrate of claim 1 , further comprising a gate insulating layer between the first insulating layer and the second insulating layer, the gate insulating layer having a thickness smaller than that of the second insulating layer.

4. The display substrate of claim 3 , wherein the thickness of the first insulating layer is smaller than the sum of the thicknesses of the gate insulating layer and the second insulating layer.

5. The display substrate of claim 1 , further comprising a gate metal layer between the first metal layer and the second metal layer, the gate metal layer having a thickness smaller than that of the second metal layer.

6. The display substrate of claim 1 , wherein the aspect ratio of the channel of the first transistor is smaller than the aspect ratio of the channel of the second transistor.

7. 2. The display substrate of claim 1, wherein the voltage of the first power supply voltage line is higher than the voltage of the second power supply voltage line, the maximum voltage of the data line is lower than the maximum voltage of the first scan line, and the maximum voltage of the data line is lower than the voltage of the first power supply voltage line.

8. 8. The display substrate of claim 1, wherein the orthogonal projection of the first pattern on the base is spaced apart from the orthogonal projection of the capacitor pattern on the base, and the orthogonal projection of the first pattern on the base is spaced apart from the orthogonal projection of the first electrode plate on the base.

9. 8. The display substrate of claim 1, wherein the first pattern and the capacitor pattern are integrally formed.

10. 2. The display substrate of claim 1, wherein the pixel driving circuit further comprises a third transistor, the third transistor having a gate electrode coupled to a second scan line, a first electrode connected to a compensation line, and a second electrode coupled to the second electrode of the second transistor.

11. The display substrate of claim 10 , wherein the metal oxide layer further comprises a third pattern serving as an active layer of the third transistor.

12. 12. The display substrate of claim 11, wherein the second insulating layer covers the first scan line, the second scan line, the gate electrode of the first transistor, the gate electrode of the second transistor, and the gate electrode of the third transistor, and a plurality of via holes are respectively opened in the second insulating layer.

13. 13. The display substrate of claim 12, wherein the second metal layer further comprises: the data line; the first power supply voltage line; a source electrode of the first transistor; a drain electrode of the first transistor; a source electrode of the second transistor; a drain electrode of the second transistor; a source electrode of the third transistor; and a drain electrode of the third transistor.

14. 14. The display substrate of claim 13, wherein the source electrode of the first transistor and the data line are integrally formed, the source electrode of the second transistor and the first power supply voltage line are integrally formed, and the drain electrode of the second transistor and the drain electrode of the third transistor are integrally formed with the second plate.

15. 15. The display substrate of claim 14, wherein the capacitor pattern is disposed in the same layer as the active layer of the first transistor, the active layer of the second transistor, and the active layer of the third transistor, and is made of the same material and formed by the same patterning process.

16. 16. The display substrate of claim 15, wherein the second plate is disposed in the same layer as the data line, the first power supply voltage line, the source electrode of the first transistor, the drain electrode of the first transistor, the source electrode of the second transistor, the drain electrode of the second transistor, the source electrode of the third transistor, and the drain electrode of the third transistor, and is made of the same material and formed by the same patterning process.

17. 17. The display substrate according to claim 1, wherein the metal oxide layer is a single layer, a double layer, or a multilayer.

18. 18. The display substrate of claim 17, wherein the metal oxide layer comprises a first oxide layer and a second oxide layer stacked together, the second oxide layer having a lower conductivity than the first oxide layer, and the second oxide layer having a larger band gap than the first oxide layer.

19. 20. The display substrate of claim 18, wherein the first oxide layer is configured to be adjacent to the gate electrodes of the first transistor, the second transistor, and the third transistor.

20. A display device comprising the display substrate according to any one of claims 1 to 19.

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