Apparatus and method for failure diagnosis of image processing apparatus

Abstract

To perform a test for confirming that image data of a display image can be normally processed.SOLUTION: The image processor is provided with a plurality of image data paths of the same configuration and a test circuit. The test circuit may test the plurality of image data paths in a state in which the first setting is set for each of the plurality of image data paths. The test circuit may further test the plurality of image data paths in a state where the second setting is set to each of the plurality of image data paths. The testing of the image data path may be based on a comparison of the output of the image data path. One of the image data paths processes the first image data stream at a first setting to provide a first processed image data stream to a first display device, and another one of the image data paths processes the second image data stream at a second setting to provide a second processed image data stream to a second display device.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates generally to image processing devices, and more particularly to fault diagnosis of image processing devices configured to provide processed image data streams to multiple display devices. [Background technology]

[0002] To improve the quality of a displayed image, a display system including a display device (e.g., a liquid crystal display (LCD) device, an organic light-emitting diode (OLED) display device, a micro light-emitting diode (μLED) display device, etc.) may include an image processing device configured to process image data and provide the processed image data to the display device. The image processing applied to the image data may include, but is not limited to, one or more of color adjustment (e.g., color gamut adjustment), contrast enhancement, edge enhancement, demurration correction, image scaling, gamma conversion, and other image processing. In one implementation, the image processing device may be implemented as or integrated into a bridge integrated circuit (IC) that interfaces a host or image source to the display device. Alternatively, the image processing device may be implemented as or integrated into a display driver IC that drives a display panel. Processing the image data according to the system environment and the characteristics of the display device can effectively improve the image quality on the display device and provide a better user experience.

[0003] To ensure that display images are correctly displayed on the display device as intended, image processing devices may be tested for fault detection and diagnostics. For example, in an automotive implementation, an instrument panel display system is required to reliably display safety-related information such as vehicle speed, turn signals, vehicle equipment warnings, and monitor images on a display screen, so an image processing device provided in the instrument panel display system may be tested to ensure that it can properly process image data for display images.

[0004] This Summary is provided to introduce a selection of concepts in a concise form that are further described below. It is not intended to necessarily identify key features or essential features of the present disclosure. The present disclosure may include various aspects and embodiments described below.

[0005] In one aspect, the present disclosure provides an image processing device including a plurality of identically configured image data paths and a test circuit. The plurality of image data paths include a first image data path and a second image data path. The test circuit is configured to test the plurality of image data paths in a first state in which a first setting is set for each of the plurality of image data paths. The test of the plurality of image data paths in the first state is based on a comparison of outputs from the plurality of image data paths. The test circuit is further configured to test the plurality of image data paths in a second state in which a second setting is set for each of the plurality of image data paths. The test of the plurality of image data paths in the second state is based on a comparison of outputs from the plurality of image data paths. The first image data path is configured to process a first image data stream at the first setting and provide a first processed image data stream to a first display device during a display operation. The second image data path is configured to process a second image data stream at the second setting and provide a second processed image data stream to a second display device during a display operation.

[0006] In another aspect, the present disclosure provides a display system including a plurality of display devices and an image processing device. The plurality of display devices include a first display device and a second display device. The image processing device includes a plurality of identically configured image data paths, wherein the plurality of image data paths include a first image data path and a second image data path. The image processing device is configured to test the plurality of image data paths in a first state in which a first setting is set for each of the plurality of image data paths. The testing of the plurality of image data paths in the first state is based on a comparison of outputs of each of the plurality of image data paths. The image processing device is further configured to test the plurality of image data paths in a second state in which a second setting is set for each of the plurality of image data paths. The testing of the plurality of image data paths in the second state is based on a comparison of outputs of each of the plurality of image data paths. The first image data path is configured to process a first image data stream at the first setting and provide a first processed image data stream to the first display device during a display operation. The second image data path is configured to process a second image data stream at the second setting and provide a second processed image data stream to the second display device during a display operation.

[0007] In yet another aspect, the present disclosure provides a method for testing and operating an image processing device having multiple identically configured image data paths. The method includes performing a first test on the multiple image data paths in a first state with a first setting set for each of the multiple image data paths. The first test is based on a comparison of outputs from the multiple image data paths. The method further includes performing a second test on the multiple image data paths in a second state with a second setting set for each of the multiple image data paths. The second test is based on a comparison of outputs from the multiple image data paths. The method further includes, during a display operation, processing a first image data stream by a first image processing circuit of the multiple image data paths with the first setting set for the first image data path and providing a first processed image data stream to a first display device. The method further includes, during a display operation, processing a second image data stream by a second image data path of the multiple image data paths with the second setting set for the second image data path and providing a second processed image data stream to a second display device.

[0008] Other features and aspects are described in more detail below with reference to the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 illustrates an example configuration of a display system according to one or more embodiments.

[0010] [Figure 2] FIG. 2 illustrates an example configuration of an image processing device according to one or more embodiments.

[0011] [Figure 3] FIG. 3 is a flowchart illustrating an example testing process according to one or more embodiments.

[0012] [Figure 4] FIG. 4 is a flowchart illustrating an example process for display operation of a display system according to one or more embodiments.

[0013] [Figure 5] FIG. 5 illustrates an example configuration of a display system according to one or more embodiments.

[0014] To facilitate understanding, the same reference numbers have been used, where possible, to designate identical elements common to the figures. It is anticipated that elements disclosed in one embodiment may be beneficially used in other embodiments without specific mention. Reference numbers may include subscripts to distinguish identical elements from one another. The drawings referred to herein should not be understood as being drawn to scale unless specifically noted. The drawings and discussion are intended to illustrate the principles discussed below. Additionally, the drawings are often simplified, with details or components omitted for clarity of presentation and explanation. The drawings and discussion are intended to illustrate the principles discussed below.

[0015] The following detailed description is exemplary in nature and is not intended to be limiting as to the disclosure and its application and uses.Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding background, summary, brief description of the drawings or the following detailed description.

[0016] In the following detailed description, numerous specific details are presented to provide a deeper understanding of the disclosed technology. However, it will be apparent to those skilled in the art that the disclosed technology may be practiced without the use of these specific details. In other instances, well-known configurations have not been described in detail to avoid unnecessarily complicating the description.

[0017] As used herein, the term "coupled" means directly connected or connected via one or more intervening components or circuits. Additionally, throughout the application, ordinal numbers (e.g., first, second, third, etc.) may be used as adjectives for elements (i.e., any nouns in the application). The use of ordinal numbers is not intended to imply or create a particular ordering of any elements, nor is it intended to limit any element to only a single element, unless expressly disclosed, for example, by the use of "before," "after," "single," and other similar terms. Rather, the use of ordinal numbers is intended to distinguish between elements. For example, a first element is distinct from a second element, and a first element may encompass more than one element and may follow (or precede) a second element in the ordering of elements.

[0018] Display systems, such as LCD systems, OLED display systems, and μLED display systems, may include an image processing device configured to process image data to improve image quality. Image processing applied to image data may include, but is not limited to, one or more of color adjustment (e.g., white balance adjustment), contrast enhancement, edge enhancement, mura correction, image scaling, gamma conversion, and other image processing. The image processing device may be implemented as a component located between a host (e.g., an external controller such as an electronic control unit (ECU) or a processor such as an application processor, central processing unit (CPU), or microprocessing unit (MPU)) and a display device, or may be integrated into such a component. For example, in some embodiments, a bridge integrated circuit (IC) providing an interface between the ECU and one or more display devices may be configured to process image data and provide the processed image data to one or more display devices. In other embodiments, the image processing device may be implemented as, or integrated into, a display driver configured to drive a display panel (e.g., an LCD panel, an OLED panel, a μLED panel, etc.) in the display device.

[0019] In some implementations, an image processing device may include multiple image data paths (or pixel data paths) configured to provide processed image data to multiple display devices, respectively. Such a configuration may be referred to as a "multi-stream transport (MST)" configuration. The term "image data path" refers to image processing circuitry configured to process an image data stream. An image data path may include one or more image processing cores, each configured to apply image processing to the image data stream. The multiple image data paths may have the same configuration, but may operate with different settings in actual display operation depending on the display device (e.g., application, characteristics, etc.). This approach may effectively streamline the design, manufacturing, and testing processes of image processing devices.

[0020] To ensure that display images are properly displayed on the display device as intended, image processing devices may be tested to detect failures in the image data path. For example, in an automotive implementation, an instrument panel display system is required to reliably display safety-related information on the display screen, such as vehicle speed, turn signals, vehicle equipment warnings, and monitor images, so an image processing device integrated into the instrument panel display system may be tested to detect failures in the image data path.

[0021] Fault detection of an image data path of an image processing device may be achieved by supplying one or more test patterns (e.g., test image data) to the image data path and comparing the output of the image data path for the test patterns with predetermined expected values ​​before fault detection. If one or more of the outputs of the image data path differ from the corresponding expected values, it indicates that the image data path contains one or more faults. In one implementation, the expected values ​​for each test pattern may be stored in a predetermined register within the image processing device.

[0022] One issue in testing image data paths is preparing expected values. Depending on the application and characteristics of the corresponding display device, a user of an image processing device (e.g., a display system manufacturer) may want to adjust image data path settings (hereinafter simply referred to as "image data path settings") to improve display image quality. Image data path settings may include, but are not limited to, parameters used for image processing in the image data path and enabling or disabling each image processing core included in the image data path. The fact that a user can adjust image data path settings means that there may be many image data path settings that can be set for the image data path. Meanwhile, because the output of the image data path may change depending on the image data path setting, the expected values ​​used for testing may also change depending on the image data path setting. This disclosure recognizes that it may be unrealistic to prepare expected values ​​for all image data path settings that may be used in actual operation (e.g., during actual display operation). A vendor of an image processing device may be able to test the image data path with a limited number of image data path settings. However, this may not be sufficient to guarantee reliable display operation for all image data path settings that may be used in actual operation.

[0023] The present disclosure provides various techniques for testing image data paths of an image processing device having an MST configuration for image data path settings used in actual operation. In one or more embodiments, the image processing device includes multiple image data paths with identical configurations and a test circuit. The multiple image data paths include a first image data path and a second image data path. The test circuit is configured to test the multiple image data paths in a first state in which a first setting is set for each of the multiple image data paths. The test of the multiple image data paths in the first state is based on a comparison of outputs from each of the multiple image data paths. The test circuit is further configured to test the multiple image data paths in a second state in which a second setting is set for each of the multiple image data paths. The test of the multiple image data paths in the second state is based on a comparison of outputs from each of the multiple image data paths. The first image data path is configured to process a first image data stream at the first setting and provide a first processed image data stream to a first display device during a display operation. The second image data path is configured to process a second image data stream at the second setting and provide a second processed image data stream to a second display device during a display operation. The image processing device configured in this manner can test the first image data path with the first setting and the second image data path with the second setting, and even if the first setting and the second setting are adjusted in various ways, it is not necessary to prepare expected values ​​for the first setting and the second setting during testing. This function of the image processing device can facilitate testing of the image data path with the image data path settings used in actual operation.

[0024] FIG. 1 illustrates an exemplary configuration of a display system 1000 according to one or more embodiments. The display system 1000 includes an image processing device 100, a pair of display devices 200-1 and 200-2, and a host 500. The host 500 is configured to provide image data streams #1 and #2 to the image processing device 100. The image data stream #1 corresponds to an image displayed on the display device 200-1, and the image data stream #2 corresponds to an image displayed on the display device 200-2. The image data stream #1 may include pixel data for pixels of the display device 200-1, and the image data stream #2 may include pixel data for pixels of the display device 200-2. The pixel data for each pixel may include a gradation of each primary color (e.g., red, green, blue) for that pixel. Examples of the host 500 include, but are not limited to, an external controller such as an ECU, an application processor, a CPU, an MPU, or other processor.

[0025] The image processing device 100 is configured as a component (e.g., a bridge IC) that interfaces between the host 500 and the display devices 200-1 and 200-2. In the illustrated embodiment, the image processing device 100 is configured to receive image data streams #1 and #2 from the host 500, process the image data streams #1 and #2, and generate processed image data streams #1 and #2, respectively. The processed image data stream #1 is supplied to the display device 200-1, and the processed image data stream #2 is supplied to the display device 200-2.

[0026] Display device 200-1 is configured to display images based on processed image data stream #1, and display device 200-2 is configured to display images based on processed image data stream #2. In the illustrated embodiment, display device 200-1 includes a display panel 210-1 and a display driver 220-1, and display device 200-2 includes a display panel 210-2 and a display driver 220-2. Display panels 210-1 and 210-2 may be LCD panels, OLED display panels, μLED display panels, or display panels based on other suitable display technologies. Display driver 220-1 is configured to drive display panel 210-1 based on processed image data stream #1, and display driver 220-2 is configured to drive display panel 210-2 based on processed image data stream #2.

[0027] In some embodiments, display devices 200-1 and 200-2 may be used to display different types of information. For example, in embodiments in which display system 1000 is used as an automotive display system, display device 200-1 may be used as an instrument panel display that provides important vehicle information, including safety-related information such as vehicle speed, turn signals, vehicle equipment warnings, and monitor images, while display device 200-2 may be used as a general-purpose display device that may display maps and / or other entertainment content.

[0028] 2 illustrates an exemplary configuration of an image processing device 100 according to one or more embodiments. The image processing device 100 has a "multi-stream transport (MST)" configuration, which includes multiple identical image data paths. In the illustrated embodiment, the image processing device 100 includes a pair of identical image data paths 1401 and 1402 for processing image data streams #1 and #2. Image data path 1401 is primarily used to process image data stream #1, and is therefore also referred to as the "ST1 path." Similarly, image data path 1402 is primarily used to process image data stream #2, and is therefore also referred to as the "ST2 path."

[0029] Because the processed image data streams #1 and #2 are provided to different display devices 200-1 and 200-2, image data paths 1401 and 1402 may be set to different image data path settings depending on the destinations of the processed image data streams #1 and #2. When the processed image data streams #1 and #2 are generated using image data paths 1401 and 1402 and provided to the display devices 200-1 and 200-2, respectively, image data path 1401 is set to an image data path setting suitable for image display on display device 200-1, and image data path 1402 is set to an image data path setting suitable for image display on display device 200-2.

[0030] The image processing device 100 further includes an input interface (I / F) circuit 110, an input selector circuit 120, and a pair of line memories 1301 and 1302, which are collectively configured to transfer one of image data streams #1 and #2 to one of image data paths 1401 and 1402, and to transfer the other of image data streams #1 and #2 to the other of image data paths 1401 and 1402. The input selector circuit 120 includes a pair of selectors 1251 and 1252 coupled to the line memories 1301 and 1302, respectively. The input interface circuit 110 is configured to receive image data streams #1 and #2 from the host 500 (shown in FIG. 1) and transfer the image data streams #1 and #2 to the input selector circuit 120. The input selector circuit 120 includes a pair of selectors 1251 and 1252 configured to receive image data streams #1 and #2, respectively. The selector 1251 is configured to transfer image data stream #1 to one of the line memories 1301 and 1302, and the selector 1252 is configured to transfer image data stream #2 to the other of the line memories 1301 and 1302. The line memory 1301 is configured to store the input data stream (input data stream #1 or #2) received from the selector 1251 and transfer the stored input data stream to the image data path 1401. Similarly, the line memory 1302 is configured to store the input data stream (input data stream #2 or #1) received from the selector 1252 and transfer the stored input data stream to the image data path 1402.

[0031] As will be described in more detail below, input selector circuit 120 is used to provide increased flexibility in the operation of image data paths 1401 and 1402 in the event of a failure in image data paths 1401 or 1402. In one or more embodiments, during normal operation when no failures occur in image data paths 1401 and 1402, input data streams #1 and #2 are provided to image data paths 1401 and 1402, respectively, which generate processed image data streams #1 and #2. Furthermore, if a critical failure is detected in image data path 1401, input selector circuit 120 may route either input data streams #1 or #2 to image data path 1402, depending on the importance of input data streams #1 and #2. In one implementation, if a critical fault is detected in image data path 1401 while input data stream #1 is carrying critical information (e.g., safety-related information in an automotive application), input selector circuit 120 may route input data stream #1 to image data path 1402 for processing in image data path 1402 to generate processed input data stream #1. Further details of the operation of input selector circuit 120 are provided below.

[0032] Image data paths 1401 and 1402 are configured to process image data streams received from line memories 1301 and 1302, respectively. Note that image data paths 1401 and 1402 process image data streams #1 and #2, respectively, during normal operation when no faults have occurred in image data paths 1401 and 1402. Image data path 1401 includes a chain of N image processing cores 142-1 to 142-N (two shown) and N selectors 144-1 to 144-N (two shown), while image data path 1402 includes a chain of N image processing cores 146-1 to 146-N (two shown) and N selectors 148-1 to 148-N (two shown), where N is a natural number greater than or equal to 2. The image processing cores 142-1 to 142-N of the image data path 1401 are alternately connected in series to the selectors 144-1 to 144-N, and the image processing cores 146-1 to 146-N of the image data path 1402 are alternately connected in series to the selectors 148-1 to 148-N.

[0033] Each of image processing cores 142-1 through 142-N and image processing cores 146-1 through 146-N is configured to perform image processing on the image data stream provided thereto. Image processing performed by image processing cores 142 and 146 may include, but is not limited to, color adjustment (e.g., color gamut adjustment), contrast enhancement, edge enhancement, demurration correction, image scaling, gamma conversion, and other image processing. For any natural number i between 1 and N, inclusive, image processing core 142-i in image data path 1401 has the same configuration and provides the same image processing as corresponding image processing core 146-i in image data path 1402.

[0034] Each of selectors 144-1 to 144-N is used to bypass a corresponding image processing core 142 in image data path 1401. More specifically, for each natural number i between 1 and N, selector 144-i has a pair of inputs coupled to the input and output of image processing core 142-i, respectively. Selector 144-i is configured to select the input coupled to the output of image processing core 142-i when enabling (or activating) image processing core 142-i, and to select the input coupled to the input of image processing core 142-i when bypassing (or deactivating) image processing core 142-i.

[0035] Similarly, selectors 148-1 through 148-N of image data path 1402 are each used to bypass a corresponding image processing core 146 in image data path 1402. Selector 148-i has a pair of inputs coupled to the input and output of image processing core 146-i, respectively. Selector 148-i is configured to select the input coupled to the output of image processing core 146-i when enabling (or activating) image processing core 146-i, and to select the input coupled to the input of image processing core 146-i when bypassing (or deactivating) image processing core 146-i.

[0036] The image processing device 100 further includes a setting register circuit 190 that stores image data path settings to be set for the image data paths 1401 and 1402. The image data path settings may include, but are not limited to, parameters used for image processing in the image processing cores 142-1 to 142-N and 146-1 to 146-N, enable / disable information for each of the image processing cores 142-1 to 142-N and 146-1 to 146-N, and the like. The selector 144-i of the image data path 1401 may be configured to bypass the image processing core 142-i when the activation / deactivation information for the image processing core 142-i indicates that the image processing core 142-i should be deactivated. Similarly, the selector 148-i of the image data path 1402 may be configured to bypass the image processing core 146-i when the activation / deactivation information for the image processing core 146-i indicates that the image processing core 146-i should be deactivated.

[0037] When the processed image data stream generated by image data path 1401 is supplied to display device 200-1, the image data path settings to be set for image data path 1401 may be determined based on the use and / or characteristics of display device 200-1 in order to improve the display image quality of display device 200-1. When the processed image data stream generated by image data path 1401 is supplied to display device 200-2, the image data path settings to be set for image data path 1401 may be determined based on the use and / or characteristics of display device 200-2 in order to improve the display image quality of display device 200-2. Similarly, when the processed image data stream generated by image data path 1402 is provided to display device 200-1, the image data path settings to be set for image data path 1402 may be determined based on the use and / or characteristics of display device 200-1 in order to improve the display image quality of display device 200-1. When the processed image data stream generated by image data path 1402 is supplied to display device 200-2, the image data path settings to be set in image data path 1402 may be determined based on the use and / or characteristics of display device 200-2 in order to improve the display image quality of display device 200-2.

[0038] The image processing device 100 further comprises a pair of pixel mapping circuits 1501, 1502, an output selector circuit 160, and an output interface circuit 170, which are collectively configured to route each of the processed image data streams generated by the image data paths 1401 and 1402 to a desired one of the display devices 200-1 and 200-2. The output selector circuit 160 includes n selectors 1651 to 1655. n The output interface circuit 170 includes selectors 1651 to 165 n n transmitters 1751 to 175 connected to each n Transmitters 1751-175 m is used for data communication with the display device 200-1, and the remaining transmitter 175 m+1 ~175 nis used for data communication with the display device 200-2.

[0039] The pixel mapping circuit 1501 selects the data bits of the processed image data stream output from the image data path 1401 and outputs them to the selectors 1651 to 1655. n More specifically, when the processed image data stream output from image data path 1401 is to be transmitted to display device 200-1, pixel mapping circuit 1501 distributes the data bits of the processed image data stream to the necessary selectors among transmitters 1751 to 1755. m Selectors 1651 to 165 are connected to m When the processed image data stream output from image data path 1401 is to be transmitted to display device 200-2, pixel mapping circuit 1501 distributes the data bits of the processed image data stream to transmitter 175, respectively. m+1 ~175 n Selector 165 bound to m+1 ~165 n Distribute to.

[0040] Similarly, pixel mapping circuit 1502 selects data bits of the processed image data stream output from image data path 1402 and outputs them to selectors 1651-1655. n When the processed image data stream output from image data path 1402 is to be transmitted to display device 200-2, pixel mapping circuit 1502 distributes the data bits of the processed image data stream to the necessary selectors of transmitter 175. m+1 ~175 n Selector 165 bound to m+1 ~165 n When the processed image data stream output from image data path 1402 is to be transmitted to display device 200-1, pixel mapping circuit 1502 distributes the data bits of the processed image data stream to transmitters 1751 to 1755, respectively. m Selectors 1651 to 165 bound to m Distribute to.

[0041] The output selector circuit 160 selects the signals from the transmitters 1751 to 1755. n More specifically, the selectors 1651 to 1655 of the output selector circuit 160 are configured to select the pixel mapping circuits 1501 and 1502 connected to the respective selectors. m When the processed image data stream output from the image data path 1401 is to be transmitted to the display device 200-1, the pixel mapping circuit 1501 is connected to the transmitters 1751 to 1755. m When the processed image data stream output from the image data path 1402 is to be transmitted to the display device 200-1, the pixel mapping circuit 1502 is connected to the transmitters 1751 to 1755. m Selector 165 m+1 ~165 n When the processed image data stream output from the image data path 1401 is to be transmitted to the display device 200-2, the pixel mapping circuit 1501 is connected to the transmitter 175. m+1 ~175 n 1402 to transmit the processed image data stream output from image data path 1402 to display device 200-2. m+1 ~175 n Combine with.

[0042] Output interface circuit 170 is configured to provide data communication to display devices 200-1 and 200-2. More specifically, transmitters 1751-1755 of output interface circuit 170 m Selector 1651~165 m The transmitter 175 of the output interface circuit 170 is configured to transmit data bits received from the image data path 1401 or the image data path 1402 to the display device 200-1. m+1 ~175 n is Selector 165 m+1 ~165 n14. The image data path 1402 is configured to transmit data bits received from the image data path 1402 (which may be data bits of the processed image data stream received from the image data path 1401) to the display device 200-2.

[0043] The image processing apparatus 100 further includes test circuitry 180 configured to test the image data paths 1401 and 1402. The test circuitry 180 is capable of testing the image data paths 1401 and 1402 without using externally supplied expected values ​​(e.g., from a tester). In one or more embodiments, the test circuitry 180 may be configured to test the image data paths 1401 and 1402 based on a comparison of the outputs of the image data paths 1401 and 1402 to the same test pattern input with the image data paths 1401 and 1402 configured with the same image data path settings. The comparison of the outputs of the image data paths 1401 and 1402 may be performed by comparing an error detection code (EDC) calculated from the outputs of the image data paths 1401 and 1402. The EDC may be a cyclic redundancy check (CRC) code or other error detection code.

[0044] In the illustrated embodiment, test circuit 180 includes test pattern generators (TPGs) 181-1 to 181-N and 182-1 to 182-N, EDC calculators 183-1 to 183-N and 184-1 to 184-N, and comparators 185-1 to 185-N. TPGs 181-1 to 181-N may be collectively referred to as TPG 181, and TPGs 182-1 to 182-N may be collectively referred to as TPG 182. Similarly, EDC calculators 183-1 to 183-N may be collectively referred to as EDC calculator 183, and EDC calculators 184-1 to 184-N may be collectively referred to as EDC calculator 184.

[0045] TPGs 181-1 to 181-N are configured to supply test patterns (e.g., test image data) to image processing cores 142-1 to 142-N, respectively, and TPGs 182-1 to 182-N are configured to supply test patterns (e.g., test image data) to image processing cores 146-1 to 146-N, respectively. EDC calculators 183-1 to 183-N are configured to calculate error detection codes (EDCs) for the outputs of image processing cores 142-1 to 142-N when the test patterns are supplied to image processing cores 142-1 to 142-N, and EDC calculators 184-1 to 184-N are configured to calculate EDCs for the outputs of image processing cores 146-1 to 146-N when the test patterns are supplied to image processing cores 146-1 to 146-N. Comparators 185-1 to 185-N are configured to compare the EDCs received from EDC calculators 183-1 to 183-N with the EDCs received from EDC calculators 184-1 to 184-N to detect faults in image data paths 1401 and 1402. The outputs of comparators 185-1 to 185-N indicate whether there is a fault in image data paths 1401 and 1402. If the EDCs received from EDC calculators 183-i and 184-i are different, this may indicate a fault in at least one of image processing cores 142-i, 146-i in image data paths 1401 and 1402.

[0046] In some embodiments, EDC calculators 183-1 to 183-N may include EDC registers 187-1 to 187-N configured to store the EDC calculated by EDC calculators 183-1 to 183-N, respectively. If no fault is detected in image data path 1401 during a test process (e.g., a test process performed during the power-on sequence of display system 1000) based on the EDC calculated by EDC calculators 183-1 to 183-N, the calculated EDC may be stored in EDC registers 187-1 to 187-N and used as an expected value when later executing another test process. Similarly, EDC calculators 184-1 to 184-N may include EDC registers 188-1 to 188-N configured to store the EDC calculated by EDC calculators 184-1 to 184-N, respectively. The stored EDC may be used as an expected value when later executing another test process.

[0047] Test circuit 180 further includes test management circuit 186 configured to manage testing of image data paths 1401 and 1402. Test management circuit 186 may be configured to control TPGs 181-1 through 181-N and 182-1 through 182-N to provide test patterns to image data paths 1401 and 1402 when testing image data paths 1401 and 1402. Test management circuit 186 may be configured to detect faults and / or identify the type of fault (e.g., non-critical or critical) in image data paths 1401 and 1402 based on the outputs of comparators 185-1 through 185-N, particularly based on the number of comparators 185 whose outputs indicate that the input EDCs differ from each other. Test management circuit 186 may further be configured to reroute the image data stream based on the detection of a critical fault by controlling input selector circuit 120 and output selector circuit 160. For example, if a critical fault is detected in image data path 1401, test management circuit 186 may be configured to cause input selector circuit 120 to transfer image data stream #1 to image data path 1402 and cause output selector circuit 160 to transfer processed image data stream #1 generated by image data path 1402 to display device 200-1.

[0048] Image processing device 100 further includes a microcontroller unit (MCU) 195 configured to control the overall operation of image processing device 100, including the operation of image data paths 1401 and 1402. More specifically, MCU 195 may be configured to control configuration register circuit 190 to set desired image data path settings for image data paths 1401 and 1402. MCU 195 may be configured to update the image data path settings set for image data paths 1401 and 1402, as appropriate or necessary. MCU 195 may also be configured to report the fault detection to host 500 (shown in FIG. 1 ) when test manager circuit 186 detects a fault in image data paths 1401 and 1402.

[0049] 3 is a flowchart illustrating an exemplary testing process 300 for detecting faults in image data paths 1401 and 1402, according to one or more embodiments. Testing process 300 may be performed during a power-on sequence of display system 1000. While the various steps in the flowchart are shown and described in sequence, those skilled in the art will understand that some or all of the steps may be performed in a different order, combined, omitted, or performed in part or in whole. Additional steps may also be performed. Accordingly, the scope of the present disclosure should not be considered limited to the particular arrangement of steps shown in FIG. 3.

[0050] In step 302, an ST1 path setting (or first setting), which is an image data path setting to be set in image data path 1401 during actual display operation, is loaded into both image data paths 1401 and 1402. In FIG. 3, image data paths 1401 and 1402 are referred to as an ST1 path and an ST2 path. In one implementation, the ST1 path setting may be determined in advance based on the use and / or characteristics of display device 200-1 to improve the image quality of display device 200-1. The ST1 path setting may be obtained from setting register circuit 190 and set into both image data paths 1401 and 1402.

[0051] In step 304, TPGs 181 and 182 generate the same test pattern and supply it to image data paths 1401 and 1402, and EDC calculators 183 and 184 calculate an EDC for the test pattern from the output of image data paths 1401 and 1402, respectively. More specifically, for each natural number i between 1 and N, TPGs 181-i and 182-i supply the same test pattern to image processing core 142-i of image data path 1401 and image processing core 146-i of image data path 1402. EDC calculator 183-i performs an EDC calculation process on the output of image processing core 142-i to calculate an EDC for the test pattern, and EDC calculator 184-i performs an EDC calculation process on the output of image processing core 146-i to calculate an EDC for the test pattern.

[0052] In step 306, the EDCs calculated in step 304 are compared between the image data paths 1401 and 1402 (between the ST1 path and the ST2 path), and a fault in the image data paths 1401 and 1402 is detected. Specifically, each comparator 185-i compares the EDCs calculated by the EDC calculators 183-i and 184-i to detect a fault in the image processing cores 142-i and 146-i. In one implementation, the test management circuit 186 determines that a fault has occurred in at least one of the image processing cores 142-i and 146-i if the EDCs calculated by the EDC calculators 183-i and 184-i are different. If the test management circuit 186 does not detect a fault in the image data paths 1401 and 1402 (e.g., if the EDCs calculated by the EDC calculators 183-i and 184-i are equal for any natural number between 1 and N), the process proceeds to step 308. If the test management circuit 186 detects a fault in either of the image processing cores 142 and 146 in the image data paths 1401 and 1402, the process proceeds to step 320, in which the MCU 195 sends a fault detection notification to the host 500 in response to the test management circuit 186 detecting a fault in the image data paths 1401 and 1402.

[0053] In step 308, in response to the detection of no failure, the EDC calculators 183-1 to 183-N store the EDCs calculated in step 304 in the EDC registers 187-1 to 187-N, respectively. The EDCs stored in the EDC registers 187-1 to 187-N are associated with the ST1 path setting and are therefore sometimes referred to as ST1 path EDCs. As will be described in detail later, the ST1 path EDCs stored in the EDC registers 187-1 to 187-N may be used as expected values ​​in an in-operation test process of the image data path 1401.

[0054] In step 310, the ST2 path setting (or second setting), which is the image data path setting to be set in the image data path 1402 during actual display operation, is loaded into both the image data paths 1401 and 1402. In one implementation, the ST2 path setting may be determined in advance based on the use and / or characteristics of the display device 200-2 to improve the image quality of the display device 200-2. The ST2 path setting may be obtained from the setting register circuit 190 and set in both the image data paths 1401 and 1402.

[0055] In step 312, similar to step 304, TPGs 181 and 182 generate the same test pattern and supply it to image data paths 1401 and 1402, and EDC calculators 183 and 184 calculate an EDC for the test pattern from the outputs of image data paths 1401 and 1402. More specifically, TPGs 181-i and 182-i supply the same test pattern to image processing core 142-i of image data path 1401 and image processing core 146-i of image data path 1402. EDC calculator 183-i performs an EDC calculation process on the output of image processing core 142-i to calculate an EDC for the test pattern, and EDC calculator 184-i performs an EDC calculation process on the output of image processing core 146-i to calculate an EDC for the test pattern.

[0056] In step 314, the EDCs calculated in step 312 are compared between image data path 1401 and image data path 1402 (between the ST1 path and the ST2 path), and a failure in image data path 1401, 1402 is detected, as in step 306. In one implementation, each comparator 185-i compares the EDCs calculated by EDC calculators 183-i and 184-i, and if the EDCs calculated by EDC calculators 183-i and 184-i are different, test management circuit 186 determines that a failure has occurred in at least one of image processing cores 142-i and 146-i. If test management circuit 186 does not detect a failure in image data paths 1401 and 1402, the process proceeds to step 316. If the test management circuit 186 detects a fault in either of the image processing cores 142 and 146 in the image data paths 1401 and 1402, the process proceeds to step 320, in which the MCU 195 sends a fault detection notification to the host 500 in response to the test management circuit 186 detecting a fault in the image data paths 1401, 1402.

[0057] In step 316, in response to no failure being detected, the EDC calculators 184-1 to 184-N store the EDCs calculated in step 312 in the EDC registers 188-1 to 188-N, respectively. The EDCs stored in the EDC registers 188-1 to 188-N are sometimes referred to as ST2 pass EDCs because they are related to the ST2 pass setting. As will be described in more detail later, the ST2 pass EDCs stored in the EDC registers 188-1 to 188-N may be used as expected values ​​in an operational test process for the image data path 1402.

[0058] In step 318, the ST1 path setting is loaded and set in the image data path 1401. In one implementation, the ST1 path setting is obtained from the setting register circuit 190 and set in the image data path 1401. In addition, if necessary, the ST2 path setting may be loaded and set in the image data path 1402. By setting the ST1 path setting in the image data path 1401 and the ST2 path setting in the image data path 1402, the image data paths 1401 and 1402 are ready to process the image data streams #1 and #2, respectively, and the display system 1000 is ready to begin display operations.

[0059] 4 is a flowchart illustrating an exemplary process 400 for display operation of display system 1000, in accordance with one or more embodiments. While the various steps in the flowchart are shown and described in sequence, one skilled in the art will understand that some or all of the steps may be performed in a different order, combined, or omitted, or that some or all of the steps may be performed in parallel. Additional steps may also be performed. Accordingly, the scope of the present disclosure should not be considered limited to the particular arrangement of steps shown in FIG. 4.

[0060] In step 402, with the ST1 path setting set for image data path 1401 and the ST2 path setting set for image data path 1402, image data paths 1401 and 1402 process image data streams #1 and #2, respectively. The processed image data streams #1 and #2 are provided to display devices 200-1 and 200-2, respectively, and display drivers 220-1 and 220-2 of display devices 200-1 and 200-2 drive or update display panels 210-1 and 220-2 based on the processed image data streams #1 and #2, respectively. Processing of image data streams #1 and #2 may be performed during a display update period in which display drivers 220-1 and 220-2 update display panels 210-1 and 220-2.

[0061] In step 404, test circuitry 180 waits for the start of a vertical front porch (VFP) period. The VFP period may be part of the blanking period following the display update period. In one or more embodiments, an in-flight test process is performed in response to the start of the VFP period. Steps 406, 408, 410, 412, 420, 422, 424, 426, and 428 are steps performed during the in-flight test process.

[0062] In step 406, TPGs 181 and 182 generate test patterns and supply them to image data paths 1401 and 1402, and EDC calculators 183 and 184 calculate EDCs for the test patterns from the outputs of image data paths 1401 and 1402. More specifically, for each natural number i between 1 and N, TPG 181-i provides the same test pattern as the test pattern generated by TPG 181-i in step 304 (shown in FIG. 3) to image processing core 142-i on image data path 1401. EDC calculator 183-i performs an EDC calculation process on the output of image processing core 142-i to calculate the EDC for the test pattern. Meanwhile, TPG 182-i supplies the same test pattern as the test pattern generated by TPG 182-i in step 312 (shown in FIG. 3) to image processing core 146-i on image data path 1402. The EDC calculator 184-i performs EDC calculation processing on the output of the image processing core 146-i to calculate the EDC for the test pattern.

[0063] In step 408, the EDC calculated in step 406 is compared with the ST1 path EDC and ST2 path EDC stored in the EDC registers 187-1 to 187-N and 188-1 to 188-N to detect a failure in the image data paths 1401 and 1402. More specifically, each comparator 185-i compares the EDC calculated by the EDC calculator 183-i in step 406 with the ST1 path EDC stored in the EDC register 187-i to detect a failure in the image processing core 142-i of the image data path 1401. If the EDC calculated by the EDC calculator 183-i in step 406 does not match the ST1 path EDC stored in the EDC register 187-i, this indicates a failure in the image processing core 142-i. Each comparator 185-i further compares the EDC calculated by the EDC calculator 184-i with the ST2 path EDC stored in the EDC register 188-N in step 406 to detect a fault in the image processing core 146-i of the image data path 1402. If the EDC calculated by the EDC calculator 184-i in step 406 does not match the ST2 path EDC stored in the EDC register 188-i, this indicates a fault in the image processing core 146-i. The test management circuit 186 determines whether there is a fault in the image data paths 1401 and 1402 based on the outputs of the comparators 185-1 through 185-N. If no fault is detected in the image data paths 1401 and 1402 in step 408, the process returns to step 402.

[0064] When a fault is detected in image data paths 1401 and / or 1402, test management circuitry 186 may perform an action to address the detected fault depending on whether the detected fault is severe. Test management circuitry 186 may determine whether the detected fault is severe based on the number of failed image processing cores (which may be image processing core 142 or image processing core 146) in each of image data paths 1401 and 1402.

[0065] If the number of failed image processing cores in each of the image data paths 1401, 1402 is less than or equal to a predetermined number Th (e.g., 1), the test management circuit 186 may determine that the detected failure is a non-critical failure, notify the MCU 195 of the occurrence of the non-critical failure, and the process may proceed to step 410.

[0066] In step 410, MCU 195 may send a non-critical fault detection notification to host 500 in response to the notification from test management circuit 186. Further, in step 412, the image processing core in which the failure occurred may be deactivated. In one implementation, the failed image processing core may be deactivated by causing selectors 144 and 148 coupled to the outputs of the failed image processing core to bypass the failed image processing core. In one implementation, MCU 195 may update the image data path settings of image data paths 1401 and / or 1402 to bypass the failed image processing core.

[0067] If the number of failed image processing cores in one or both of the image data paths 1401 and 1402 exceeds a predetermined number Th, the test management circuit 186 may determine that the detected failure is a critical failure and notify the MCU 195 of the occurrence of the critical failure, and the process may proceed to step 420.

[0068] In step 420, in response to the notification from test management circuit 186, MCU 195 may send a critical fault detection notification to host 500. Further, in step 422, test management circuit 186 may determine whether the detected fault occurred in a "critical path," which is one of image data paths 1401 and 1402 assigned to process the more critical of input data streams #1 and #2. If input data stream #1 carries more critical information than input data stream #2, image data path 1401 assigned to process input data stream #1 may be the "critical path." More specifically, in embodiments in which display device 200-1 is used as an instrument panel display providing important vehicle information, including safety-related information such as vehicle speed, turn signals, vehicle equipment warnings, monitor images, etc., image data path 1401 is the "critical path."

[0069] If the detected failure does not occur on a critical path (e.g., image data path 1401), the process may proceed to step 428. In step 428, the failed image processing core may be deactivated by causing selector 144 or 148 coupled to the output of the failed image processing core to bypass the failed image processing core. In one implementation, MCU 195 may update the image data path settings of image data paths 1401 and / or 1402 to bypass the failed image processing core.

[0070] If the detected fault occurs in a critical path (e.g., image data path 1401), the process may proceed to step 424. In step 424, the ST1 path setting associated with display device 200-1 may be loaded into image data path 1402, causing image data path 1402 to process image data stream #1 using the ST1 path setting. Next, the process may proceed to step 426. In step 426, the image data path used to process image data stream #1 is switched from image data path 1401 (or ST1 path) to image data path 1402 (or ST2 path). More specifically, test management circuit 186 may cause input selector circuit 120 to transfer image data stream #1 to image data path 1402 and output selector circuit 160 to transfer processed image data stream #1 from image data path 1402 to display device 200-1. After the switch, image data path 1402 may process image data stream #1 and provide processed image data stream #1 to display device 200-1.

[0071] While the above-described embodiment is based on an image processing device having two image data paths (1401 and 1402), the techniques disclosed in this disclosure are applicable to image processing devices having three or more image data paths configured to provide processed image data streams to three or more display devices. Figure 5 shows an example configuration of a display system 2000 according to another embodiment, including an image processing device 1100, three display devices 200-1, 200-2, 200-3, and a host 1500.

[0072] Host 1500 is configured to provide image data streams #1, #2, and #3 to image processing device 1100, where image data streams #1, #2, and #3 correspond to images to be displayed on display devices 200-1, 200-2, and 200-3, respectively. Image data streams #1, #2, and #3 may include pixel data for pixels of display devices 200-1, 200-2, and 200-3, respectively. Examples of host 1500 include, but are not limited to, an external controller such as an ECU, an application processor, a CPU, an MPU, or other processor.

[0073] The image processing device 1100 is configured as a component (e.g., a bridge IC) that acts as an interface between the host 1500 and the display devices 200-1 to 200-3. In the illustrated embodiment, the image processing device 1100 is configured to receive image data streams #1, #2, and #3 from the host 1500, process the image data streams #1, #2, and #3, and generate processed image data streams #1, #2, and #3, respectively. The processed image data streams #1, #2, and #3 are supplied to the display devices 200-1, 200-2, and 200-3, respectively.

[0074] Display devices 200-1, 200-2, and 200-3 are configured to display images based on processed image data streams #1, #2, and #3, respectively. In the illustrated embodiment, display device 200-1 includes a display panel 210-1 and a display driver 220-1, display device 200-2 includes a display panel 210-2 and a display driver 220-2, and display device 200-3 includes a display panel 210-3 and a display driver 220-3. Display panels 210-1, 210-2, and 210-3 may be LCD panels, OLED display panels, μLED display panels, or display panels based on any other suitable display technology. Display driver 220-1 is configured to drive display panel 210-1 based on processed image data stream #1, display driver 220-2 is configured to drive display panel 210-2 based on processed image data stream #2, and display driver 220-3 is configured to drive display panel 210-3 based on processed image data stream #3.

[0075] The image processing device 1100 includes an input interface (I / F) circuit 1110, an input selector circuit 1120, three line memories 11301, 11302, and 11303, and three image data paths 11401, 11402, and 11403. The image data paths 11401, 11402, and 11403 have the same configuration. The input interface circuit 1110 is configured to receive image data streams #1, #2, and #3 from the host 1500. The input interface circuit 1110 is further configured to transfer one of the image data streams #1, #2, and #3 to the line memory 11301, transfer another to the line memory 11302, and transfer the remaining one to the line memory 11303. The line memories 11301, 11302, and 11303 are configured to store the image data streams received from the input selector circuit 1120 and provide the stored image data streams to the image data paths 11401, 11402, and 11403, respectively. The image data paths 11401, 11402, and 11403 are configured to process the image data streams received from the line memories 11301, 11302, and 11303. In one implementation, the image data paths 11401, 11402, and 11403 may each include an image processing core and a selector coupled in alternating series, similar to the image data paths 1401 and 1402 shown in FIG. 2.

[0076] The image processing device 1100 further includes pixel mapping circuits 11501, 11502, and 11503, an output selector circuit 1160, and an output interface circuit 1170, which are configured similarly to the pixel mapping circuits 1501 and 1502, the output selector circuit 160, and the output interface circuit 170, respectively, of the image processing device 100 shown in Figure 2. The pixel mapping circuits 11501, 11502, and 11503, the output selector circuit 1160, and the output interface circuit 1170 are configured as a whole to transfer each of the processed image data streams generated by the image data paths 11401, 11402, and 11403 to any one of the display devices 200-1, 200-2, and 200-3.

[0077] The image processing device 1100 further includes a test circuit 1180, a setting register circuit 1190, and an MCU 1195. Similar to the test circuit 180 shown in FIG. 2, the test circuit 1180 is configured to test the image data paths 11401, 11402, and 11403. The setting register circuit 1190 is configured to store image data path settings to be set for the image data paths 11401, 11402, and 11403. The setting register circuit 1190 is configured to store image data path settings to be set for the image data paths 11401, 11402, and 11403. The MCU 1195 is configured to control the overall operation of the image processing device 100, including the operation of the image data paths 11401, 11402, and 11403. For example, the MCU 1195 may be configured to control the setting register circuit 1190 to set desired image data path settings for the image data paths 11401, 11402, and 11403. MCU 1195 may further be configured to update the image data path settings set on image data paths 11401, 11402 and 11403 as appropriate or necessary.

[0078] In one or more embodiments, during a power-on sequence of display system 2000, a test process for image data paths 11401, 11402, and 11403 may be performed as follows: Test circuit 1180 may test the image data paths in a first state in which a first image data path setting (or ST1 path setting) is set for each of image data paths 11401, 11402, and 11403. In one implementation, the first image data path setting may be the data path setting set for image data path 11401 during actual operation (e.g., during actual display operation). Testing image data paths 11401, 11402, and 11403 in the first state may be based on a comparison of the outputs of image data paths 11401, 11402, and 11403. In one or more embodiments, test circuitry 1180 may provide identical test patterns (e.g., identical test image data) to image data paths 11401, 11402, and 11403 and calculate EDCs from the outputs of image data paths 11401, 11402, and 11403. Test circuitry 1180 may further compare the EDCs calculated from the outputs of image data paths 11401, 11402, and 11403 to detect faults in image data paths 11401, 11402, and 11403. A discrepancy between the EDCs calculated from the outputs of image data paths 11401, 11402, and 11403 indicates that a fault has occurred in the output of image data paths 11401, 11402, and 11403.

[0079] Test circuit 1180 may further test the image data paths in a second state in which a second image data path setting (or ST2 path setting) is set for each of image data paths 11401, 11402, and 11403. In one implementation, the second image data path setting may be the image data path setting set for image data path 11402 during actual display operation. Testing image data paths 11401, 11402, and 11403 in the second state may be based on a comparison of the outputs of image data paths 11401, 11402, and 11403, similar to testing image data paths 11401, 11402, and 11403 in the first state.

[0080] Test circuit 1180 may further test the image data paths in a third state in which a third image data path setting (or ST3 path setting) is set for each of image data paths 11401, 11402, and 11403. In one implementation, the third image data path setting may be the image data path setting that is set for image data path 11403 in actual display operation. Testing image data paths 11401, 11402, and 11403 in the third state may be based on a comparison of the outputs of image data paths 11401, 11402, and 11403, similar to testing image data paths 11401, 11402, and 11403 in the first and second states.

[0081] During actual display operation, image data paths 11401, 11402, and 11403 may operate at first, second, and third image data path settings, respectively. Image data path 11401 may process image data stream #1 using the first image data path setting and provide processed image data stream #1 to display device 200-1, image data path 11402 may process image data stream #2 using the second image data path setting and provide processed image data stream #2 to display device 200-2, and image data path 11403 may process image data stream #3 using the third image data path setting and provide processed image data stream #3 to display device 200-3.

[0082] All references cited herein, including publications, patent applications, and patents, are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0083] The use of "a," "an," "the," "at least one," and similar reference words in the context of describing the present invention (particularly in the context of the claims below) should be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The use of a list of one or more items following the term "at least one" (e.g., "at least one of A and B") should be construed to mean one item selected from the listed items (A or B) or any combination of two or more of the listed items (A and B), unless otherwise stated herein or clearly contradicted by context. The terms "comprising," "having," "including," and "including" should be construed as open-ended terms (i.e., meaning "including, but not limited to"), unless otherwise indicated. The recitation of ranges of values ​​herein, unless otherwise stated herein, is intended to serve merely as a shorthand method of referring individually to each separate value falling within the range, and each separate value is incorporated herein as if set forth individually herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context. Any examples provided herein, or the use of exemplary language (e.g., "such as"), are intended merely to better illustrate the invention and do not limit the scope of the invention unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention.

[0084] While exemplary embodiments are described herein, variations of those exemplary embodiments will become apparent to those skilled in the art upon reading the foregoing description. The inventors expect that those skilled in the art will adopt such variations as appropriate, and the inventors intend the invention to be practiced otherwise than as specifically described herein. Accordingly, this invention includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed by the invention unless otherwise indicated herein or otherwise clearly contradicted by context.

Claims

1. a plurality of image data paths having the same configuration, including a first image data path and a second image data path; testing the plurality of image data paths in a first state with a first setting set for each of the plurality of image data paths, the testing of the plurality of image data paths in the first state being based on a comparison of outputs of the plurality of image data paths; a test circuit configured to test the plurality of image data paths in a second state in which a second setting is set for each of the plurality of image data paths, the test of the plurality of image data paths in the second state being performed based on a comparison of outputs of the plurality of image data paths; Equipped with the first image data path is configured to process a first image data stream at the first setting and provide a first processed image data stream to a first display device during a display operation; the second image data path is configured to process the second image data stream at the second setting and provide a second processed image data stream to a second display device during the display operation; Image processing device.

2. testing the plurality of image data paths in the first state, calculating a plurality of error detection codes (EDCs) based on the respective outputs of the plurality of image data paths in the first state; testing the plurality of image data paths based on a comparison of the plurality of EDCs; Including, The image processing device according to claim 1 .

3. the testing of the plurality of image data paths in the first state and the testing of the plurality of image data paths in the second state are performed during a power-on sequence. The image processing device according to claim 2 .

4. The test circuit further comprises: storing a first EDC calculated based on a first output of the first image data path in the first state among the plurality of EDCs; calculating a second EDC based on a second output of the first image data path during the display operation; configured to test the first image data path during the display operation based on a comparison between the first EDC and the second EDC; The image processing device according to claim 2 .

5. The test circuit further comprises: configured, in response to detecting a first fault in the first image data path during testing of the first image data path during the display operation, to cause the second image data path to process a subsequent image data stream with the first setting to generate a subsequent processed image data stream, and to provide the subsequent processed image data stream to the first display device; The image processing device according to claim 4 .

6. the first failure in the first image data path is detected based on a number of failed image processing cores in the first image path exceeding a predetermined number; The image processing device according to claim 5 .

7. the test circuitry is further configured to disable one or more failed image processing cores of the first image data path in response to detecting a second failure in the first image data path during testing of the first image data path during the display operation. The image processing device according to claim 4 .

8. the second failure in the first image data path is detected based on a number of failed image processing cores in the first image path being less than or equal to a predetermined number. The image processing device according to claim 7 .

9. the image processing device is configured as a bridge integrated circuit (IC) configured to provide the first processed image data stream to the first display device and the second processed image data stream to the second display device; The image processing device according to claim 1 .

10. a plurality of display devices including a first display device and a second display device; an image processing device having a plurality of image data paths having the same configuration, including a first image data path and a second image data path; Equipped with The image processing device testing the plurality of image data paths in a first state with a first setting set for each of the plurality of image data paths, the testing of the plurality of image data paths in the first state being based on a comparison of outputs of the plurality of image data paths; testing the plurality of image data paths in a second state in which a second setting is set for each of the plurality of image data paths, and testing the plurality of image data paths in the second state is performed based on a comparison of outputs of the plurality of image data paths; the first image data path is configured to process a first image data stream at the first setting and provide the first processed image data stream to the first display device during a display operation; the second image data path is configured to process a second image data stream at the second setting and provide a second processed image data stream to the second display device during the display operation; Display system.

11. testing the plurality of image data paths in the first state, calculating a plurality of error detection codes (EDCs) based on the respective outputs of the plurality of image data paths in the first state; testing the plurality of image data paths based on a comparison of the plurality of EDCs; Including, The display system of claim 10.

12. the testing of the plurality of image data paths in the first state and the testing of the plurality of image data paths in the second state are performed during a power-on sequence. The display system of claim 11.

13. The image processing device further comprises: storing a first EDC calculated based on a first output of the first image data path in the first state among the plurality of EDCs; calculating a second EDC based on a second output of the first image data path during the display operation; configured to test the first image data path during the display operation based on a comparison between the first EDC and the second EDC; The display system of claim 11.

14. a first test is performed on a plurality of image data paths having the same configuration in a first state in which a first setting is set for each of the plurality of image data paths, and the first test is based on a comparison of outputs of the plurality of image data paths; performing a second test on the plurality of image data paths in a second state in which a second setting is set for each of the plurality of image data paths, the second test being based on a comparison of outputs of the plurality of image data paths; during a display operation, processing a first image data stream by a first image processing circuit of the plurality of image data paths with the first setting set on the first image data path, and providing a first processed image data stream to a first display device; During the display operation, processing a second image data stream through a second image data path of the plurality of image data paths with the second setting set on the second image data path, and providing a second processed image data stream to a second display device; Including, method.

15. the first test includes calculating a plurality of error detection codes (EDCs) based on the respective outputs of the plurality of image data paths in the first state; the first test is based on a comparison of the plurality of EDCs; 15. The method of claim 14.

16. the first test and the second test are performed during a power-on sequence; 16. The method of claim 15.

17. storing a first EDC calculated based on a first output of the first image data path in the first state among the plurality of EDCs; calculating a second EDC based on a second output of the first image data path during the display operation; performing a third test on the first image data path during the display operation based on a comparison between the first EDC and the second EDC; Further comprising:

16. The method of claim 15.

18. In response to detecting a first fault in the first image data path during the third test, processing a subsequent image data stream by the second image data path with the first setting set on the second image data path to generate a subsequent processed image data stream; providing the subsequent processed image data stream to the first display device; Further comprising:

18. The method of claim 17.

19. the first failure in the first image data path is detected based on a number of failed image processing cores in the first image path exceeding a predetermined number; 20. The method of claim 18.

20. and further comprising disabling one or more failed cores of the first image data path in response to detecting a second failure in the first image data path during the third test.

18. The method of claim 17.

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