Mother substrate for display device

Abstract

To improve the yield of a display device.SOLUTION: A display device according to an embodiment includes a plurality of panel units including a display region, a margin region around the plurality of panel units, a plurality of display elements arranged in the display region, a first partition wall arranged in each of the plurality of panel units and having an overhang shape surrounding the plurality of display elements, and a second partition wall arranged in the margin region and having an overhang shape. Further, a first coverage ratio, which is a ratio of a total area of the first partition walls and the second partition walls to a total area of the plurality of panel units and the margin region, is 30% or more.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a mother substrate for a display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have come into practical use. Techniques for improving the yield of such display devices are needed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a mother substrate for a display device that can improve the yield of the display device. [Means for solving the problem]

[0005] A display device according to one embodiment includes a plurality of panel units each including a display area, a margin area around the plurality of panel units, a plurality of display elements arranged in the display area, a first overhanging partition wall arranged in each of the plurality of panel units and surrounding the plurality of display elements, and a second overhanging partition wall arranged in the margin area, wherein a first coverage, which is the ratio of the total area of ​​the first partition wall and the second partition wall to the total area of ​​the plurality of panel units and the margin area, is 30% or more. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view of a motherboard according to an embodiment. [Figure 5] FIG. 5 is an enlarged plan view of a portion of the motherboard. [Figure 6] FIG. 6 is a schematic cross-sectional view of the motherboard taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the motherboard taken along line VII-VII in FIG. [Figure 8A] FIG. 8A is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 8B] FIG. 8B is a schematic cross-sectional view showing a step subsequent to FIG. 8A. [Figure 8C] FIG. 8C is a schematic cross-sectional view showing a step subsequent to FIG. 8B. [Figure 8D] FIG. 8D is a schematic cross-sectional view showing a step subsequent to FIG. 8C. [Figure 8E] FIG. 8E is a schematic cross-sectional view showing a step subsequent to FIG. 8D. [Figure 8F]FIG. 8F is a schematic cross-sectional view showing a step subsequent to FIG. 8E. [Figure 8G] FIG. 8G is a schematic cross-sectional view showing a step subsequent to FIG. 8F. [Figure 8H] FIG. 8H is a schematic cross-sectional view showing a step subsequent to FIG. 8G. [Figure 8I] FIG. 8I is a schematic cross-sectional view showing a step subsequent to FIG. 8H. [Figure 8J] FIG. 8J is a schematic cross-sectional view showing a step subsequent to FIG. 8I. [Figure 9] FIG. 9 is a schematic cross-sectional view of a motherboard according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0007] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0008] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. The Z direction is the normal direction of a plane including the X and Y directions. Viewing various elements parallel to the Z direction is referred to as planar view.

[0009] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0010] 1 is a diagram showing an example of the configuration of a display device DSP according to one embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0011] In this embodiment, the shape of the substrate 10 and the display area DA in a plan view is circular. However, the shape of the substrate 10 and the display area DA in a plan view is not limited to circular, and may be other shapes such as rectangular, square, or elliptical.

[0012] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. The pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0013] The display device DSP further includes a terminal section T arranged in the peripheral area SA. To the terminal section T, for example, a flexible circuit board is connected that supplies voltages and signals for driving the display device DSP.

[0014] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0015] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL. In the example of Fig. 1, the scanning lines GL and the power supply lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0016] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0017] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0018] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3 that constitute one pixel PX. In the example of Fig. 2, the subpixels SP1 and SP3 are aligned in the Y direction. Furthermore, the subpixels SP1 and SP3 are aligned with the subpixel SP2 in the X direction.

[0019] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP1 and SP3 are alternately arranged in the Y direction, and columns in which multiple subpixels SP2 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0020] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of FIG. 2, the pixel openings AP1 and AP3 are quadrangles with the same area. On the other hand, the pixel opening AP2 is a rectangle that is longer in the Y direction than the pixel openings AP1 and AP3. However, the shapes of the pixel openings AP1, AP2, and AP3 are not limited to this example.

[0021] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap pixel aperture AP3.

[0022] The portions of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlap with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The portions of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlap with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The portions of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlap with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0023] Conductive partition walls 6A (first partition walls) are disposed above the rib layer 5. The partition walls 6A function as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition walls 6A entirely overlap the rib layer 5 and have the same planar shape as the rib layer 5.

[0024] The partition 6A surrounds each of the pixel openings AP1, AP2, and AP3. Specifically, the partition 6A has partition openings 71A, 72A, and 73A (first partition openings) that surround the pixel openings AP1, AP2, and AP3, respectively.

[0025] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0026] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 3 , the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0027] The partition wall 6A includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. That is, the partition wall 6A has an overhanging shape in which both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61.

[0028] In the example of FIG. 3, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the shaft layer 64 is formed to be thicker than the bottom layer 63. In the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0029] 3, the upper portion 62 includes a first top layer 65 and a second top layer 66 disposed on the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, the present invention is not limited to this, and the first top layer 65 and the second top layer 66 may have the same width.

[0030] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6A.

[0031] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0032] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0033] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the display element DE1 and the partition wall 6A around it. The sealing layer SE12 continuously covers the display element DE2 and the partition wall 6A around it. The sealing layer SE13 continuously covers the display element DE3 and the partition wall 6A around it.

[0034] 3, the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the partition wall 6A. Also, the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the partition wall 6A. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact with each other above the partition wall 6A.

[0035] For example, gaps are formed between the sealing layers SE11, SE12, and SE13 and the upper portion 62 of the partition wall 6A. The stacked films FL1, FL2, and FL3 may be disposed in at least a part of these gaps.

[0036] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0037] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0038] The electrodes constituting the touch panel may be disposed on the sealing layer SE2. Also, color filters corresponding to the colors of the subpixels SP1, SP2, SP3 may be disposed above the display elements DE1, DE2, DE3, respectively.

[0039] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0040] The lower electrodes LE1, LE2, and LE3 each include a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0041] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0042] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0043] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0044] The bottom layer 63 and the shaft layer 64 of the partition wall 6A are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0045] The first top layer 65 of the partition wall 6A is formed of, for example, a metal material. The second top layer 66 of the partition wall 6A is formed of, for example, a conductive oxide. Examples of the metal material that can be used to form the first top layer 65 include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the second top layer 66 include ITO or IZO. The upper portion 62 may include three or more layers or may be formed of a single layer. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0046] A common voltage is supplied to the partition wall 6A. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. A pixel voltage corresponding to the video signal on the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0047] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0048] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0049] When manufacturing the display device DSP, a large motherboard is fabricated on which a plurality of regions (panel sections) each corresponding to a display device DSP are formed. The following describes a configuration that can be applied to this motherboard.

[0050] 4 is a schematic plan view of a mother substrate MB (mother substrate for a display device) according to this embodiment. The mother substrate MB has a plurality of panel portions PP arranged in a matrix and blank areas BA surrounding the panel portions PP.

[0051] In the example of Fig. 4, blocks B1 and B2 are formed on a motherboard MB. Each of these blocks B1 and B2 includes a plurality of panel portions PP arranged in close proximity to each other. A blank area BA is also formed between the blocks B1 and B2.

[0052] A cut line CL0 for cutting out the blocks B1 and B2 is set on the mother substrate MB. For example, at least one of the layers such as the rib layer 5, the insulating layers included in the circuit layer 11, and the organic insulating layer 12 is removed along the cut line CL0.

[0053] The configuration of the mother substrate MB is not limited to the example in Fig. 4. For example, the mother substrate MB may have more blocks and cut lines CL0.

[0054] 5 is an enlarged plan view of a portion of the motherboard MB, showing two panel portions PP and a blank area BA surrounding the panel portions PP.

[0055] The outer shape of the panel portion PP corresponds to the cut line CL1 used to cut out each panel portion PP from the mother substrate MB. The panel portion PP has the display area DA and peripheral area SA described above. The peripheral area SA of the panel portion PP corresponds to the area between the display area DA and the cut line CL1.

[0056] The peripheral area SA further has a cut line CL2 that defines the outline of the substrate 10 of the display device DSP. The peripheral area SA includes an inspection area TA between the cut lines CL1 and CL2.

[0057] In the example of Figure 5, multiple test pads TD1 are arranged in the test area TA. Additionally, multiple test pads TD2 and multiple alignment marks M are arranged in the blank area BA. The test pads TD1 and TD2 are used to test the operation of the display device DSP. The alignment marks M are used to position the mother substrate MB in various manufacturing processes.

[0058] The above-mentioned partition wall 6A is arranged not only in the display area DA but also in the peripheral area SA and the inspection area TA. In addition, a partition wall 6B (second partition wall) is arranged in the blank area BA. The partition wall 6B has an overhanging shape like the partition wall 6A.

[0059] 3, the partition wall 6B has a lower portion 61 including a bottom layer 63 and an axis layer 64, and an upper portion 62 including a first top layer 65 and a second top layer 66. The materials of the bottom layer 63, axis layer 64, first top layer 65, and second top layer 66 of the partition wall 6B are the same as the materials of the bottom layer 63, axis layer 64, first top layer 65, and second top layer 66 of the partition wall 6A described above.

[0060] In Fig. 5, a grid pattern is applied to the area where the partitions 6A and 6B are arranged. This grid pattern does not represent the shape of the partitions 6A and 6B themselves. For example, the partitions 6A in the display area DA have the planar shape shown in Fig. 2. The partitions 6A in the peripheral area SA may have at least a portion of the same shape as the partitions 6A in the display area DA, or may have a different shape overall.

[0061] An example of a planar shape applicable to the partition wall 6B is shown in the lower part of Fig. 5. In this example, the partition wall 6B is divided into a plurality of segments SG by slits SL1. These segments SG are, for example, rectangular and are arranged in the X and Y directions at the same pitch as the pixels PX.

[0062] The segment SG has partition wall openings 71B, 72B, and 73B (second partition wall openings). For example, the shapes and positional relationship of these partition wall openings 71B, 72B, and 73B are equivalent to the shapes and positional relationship of the partition wall openings 71A, 72A, and 73A shown in FIG.

[0063] The shape of the partition wall 6B is not limited to the example shown in Fig. 5. For example, the partition wall 6B may have segments without partition wall openings or linear segments in addition to the segments SG shown in the figure. Furthermore, the partition wall 6B does not have to be divided into multiple segments SG. The shape of the partition wall openings provided in the partition wall 6B may be different from the shapes of the partition wall openings 71A, 72A, and 73A.

[0064] The partition walls 6A are provided in most of the panel portion PP. Similarly, the partition walls 6B are provided in most of the blank area BA. However, the partition walls 6A and 6B do not necessarily have to be arranged in positions overlapping with the terminal portions T, the test pads TD1 and TD2, the cut lines CL0, CL1, and CL2, and the alignment marks M.

[0065] 6 is a schematic cross-sectional view of the motherboard MB taken along line VI-VI in FIG. 4. In this cross-section, an inorganic insulating layer 31 is disposed on a substrate 10. Furthermore, an organic insulating layer 32 is disposed on the inorganic insulating layer 31. The inorganic insulating layer 31 and the organic insulating layer 32 are included in the circuit layer 11 shown in FIG. 3. The inorganic insulating layer 31 is formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. The organic insulating layer 32 is formed of an organic insulating material such as polyimide.

[0066] The organic insulating layer 32 is covered with the organic insulating layer 12. The organic insulating layer 12 is covered with the rib layer 5. The partition wall 6B is disposed on the rib layer 5.

[0067] The organic insulating layers 12 and 32 are not disposed on or around the cut line CL0. That is, the organic insulating layers 12 and 32 have a slit SL2 along the cut line CL0. The inorganic insulating layer 31 covers the substrate 10 even at the slit SL2.

[0068] The rib layer 5 and the partition walls 6B are also not disposed on the cut lines CL0. However, in the example of FIG. 6, the rib layer 5 (hereinafter referred to as the rib layer 5a) is disposed in the region between the two cut lines CL0. The rib layer 5a extends along the two cut lines CL0 in a plan view. The rib layer 5a is also in contact with the inorganic insulating layer 31. The partition walls 6B are disposed not only on the rib layer 5 outside the slits SL2 but also on the rib layer 5a inside the slits SL2.

[0069] Fig. 7 is a schematic cross-sectional view of the motherboard MB taken along line VII-VII in Fig. 4. In this cross-section, the organic insulating layers 12 and 32 are not disposed on or around the cut line CL0.

[0070] The cross section of Fig. 7 includes an alignment mark M. The alignment mark M is formed, for example, by a metal layer included in the circuit layer 11 shown in Fig. 3. In the example of Fig. 7, the alignment mark M is disposed on an inorganic insulating layer 31 and is covered with an organic insulating layer 32.

[0071] 7, the organic insulating layer 12 is not disposed above the alignment mark M. This causes the rib layer 5 to be in contact with the organic insulating layer 32. As another example, the organic insulating layer 12 may be disposed above the alignment mark M.

[0072] The partition walls 6B are also disposed in the regions where the organic insulating layer 32 contacts the rib layer 5. However, above the alignment marks M, the partition walls 6B are not disposed.

[0073] 6 and 7 omit elements disposed above the rib layer 5 and the partition wall 6B. The rib layer 5 and the partition wall 6B may be covered with a sealing layer formed of an inorganic insulating material. This sealing layer may be formed, for example, of any one of sealing layers SE11, SE12, and SE13. This sealing layer may further be covered with sealing layer SE2. Furthermore, any one of stacked films FL1, FL2, and FL3 may be disposed at least partially below the sealing layer.

[0074] 6 and 7 can also be applied to the vicinity of the cut lines CL1 and CL2. That is, the organic insulating layers 12 and 32 may have slits along the cut lines CL1 and CL2. Furthermore, the partition walls 6A and 6B may be disposed within these slits.

[0075] Next, an example of a manufacturing method of the display device DSP will be described. Figures 8A to 8J are schematic cross-sectional views showing the manufacturing process of the display device DSP. Figures 8A to 8J mainly focus on the display area DA, and omit elements below the organic insulating layer 12.

[0076] In forming the panel portion PP, first, the circuit layer 11 and the organic insulating layer 12 are formed above the substrate 10 of the mother substrate MB. Next, as shown in FIG. 8A, the lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12.

[0077] 8B, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed over the entire mother substrate MB. At this point, pixel openings AP1, AP2, and AP3 are not provided in the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0078] After the rib layer 5 is formed, a process for forming the partition walls 6A and 6B is carried out. In this process, as shown in FIG. 8C , a first layer L1 to be processed into the bottom layer 63, a second layer L2 to be processed into the shaft layer 64, a third layer L3 to be processed into the first top layer 65, and a fourth layer L4 to be processed into the second top layer 66 are formed in this order over the entire mother substrate MB. Furthermore, a resist R1 is disposed on the fourth layer L4. The resist R1 is patterned into the shape of the partition walls 6A and 6B. The first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 can be formed by, for example, sputtering.

[0079] Then, using the resist R1 as a mask, the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 are patterned. In one example, the first layer L1 is formed of titanium nitride, the second layer L2 is formed of aluminum, the third layer L3 is formed of titanium, and the fourth layer L4 is formed of ITO. In this case, the patterning may include wet etching to remove the portion of the fourth layer L4 exposed from the resist R1, dry etching to remove the portion of the third layer L3 exposed from the resist R1, wet etching to remove the portion of the second layer L2 exposed from the resist R1 and reduce the width of the second layer L2 remaining below the resist R1, and dry etching to remove the portion of the first layer L1 exposed from the resist R1.

[0080] By patterning including these etching steps, partition walls 6A are formed in the display area DA and the peripheral area SA, as shown in Fig. 8D. Also, partition walls 6B are formed in the marginal area BA. After the partition walls 6A and 6B are formed, the resist R1 is removed (peeled off).

[0081] Next, a process for providing pixel openings AP1, AP2, and AP3 is performed. In this process, a resist R2 is formed to cover the partition wall 6A, as shown in FIG. 8E. Furthermore, the rib layer 5 is dry-etched using the resist R2 as a mask. As a result, pixel openings AP1, AP2, and AP3 that expose the lower electrodes LE1, LE2, and LE3 are formed in the rib layer 5, as shown in FIG. 8F. After the dry etching, the resist R2 is removed (peeled). Note that the pixel openings AP1, AP2, and AP3 may be formed before the partition walls 6A and 6B.

[0082] Next, a process for forming the display element DE1 is performed. To form the display element DE1, first, as shown in FIG. 8G, a stacked film FL1 and a sealing layer SE11 are formed. As shown in FIG. 3, the stacked film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed by, for example, vapor deposition. The sealing layer SE11 can be formed by, for example, CVD.

[0083] The laminated film FL1 and sealing layer SE11 are formed over the entire mother substrate MB, including the display area DA of each panel unit PP, the peripheral area SA, and the margin area BA. The laminated film FL1 is divided into multiple parts by overhanging partition walls 6A and 6B. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6A and 6B.

[0084] Next, the stacked film FL1 and the sealing layer SE11 are patterned. In this patterning, a resist R3 is disposed on the sealing layer SE11, as shown in FIG. 8G. The resist R3 covers the subpixel SP1 and part of the partition wall 6A around it.

[0085] Then, an etching process is performed using the resist R3 as a mask. As a result, as shown in FIG. 8H, the stacked film FL1 and the sealing layer SE11 are removed from the exposed portions of the resist R3, thereby forming a display element DE1 in the subpixel SP1. For example, in the peripheral region SA and the marginal region BA, the stacked film FL1 and the sealing layer SE11 are removed by this etching process. This etching process may include wet etching or dry etching performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching processes, the resist R3 is removed (peeled off).

[0086] Next, a process for forming the display element DE2 is performed. The display element DE2 can be formed using the same procedure as the display element DE1. That is, when forming the display element DE2, a stacked film FL2 and a sealing layer SE12 are formed over the entire mother substrate MB. As shown in FIG. 3, the stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2.

[0087] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed by, for example, vapor deposition. The sealing layer SE12 can be formed by, for example, CVD. By patterning the stacked film FL2 and the sealing layer SE2, a display element DE2 is formed in the subpixel SP2, as shown in FIG. 8I. For example, in the peripheral region SA and the marginal region BA, the stacked film FL2 and the sealing layer SE12 are removed by etching during the patterning process.

[0088] Next, a process for forming the display element DE3 is performed. The display element DE3 can be formed using the same procedure as for the display elements DE1 and DE2. That is, when forming the display element DE3, a stacked film FL3 and a sealing layer SE13 are formed over the entire mother substrate MB. As shown in FIG. 3, the stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3.

[0089] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed by, for example, vapor deposition. The sealing layer SE13 can be formed by, for example, CVD. By patterning the stacked film FL3 and the sealing layer SE13, a display element DE3 is formed in the subpixel SP3, as shown in FIG. 8J. For example, the stacked film FL3 and the sealing layer SE13 may be left in at least a portion of the peripheral region SA and the marginal region BA.

[0090] Although it is assumed here that the display elements DE1, DE2, and DE3 are formed in this order, the display elements DE1, DE2, and DE3 may be formed in a different order.

[0091] After the display elements DE1, DE2, and DE3 are formed, a resin layer RS1, a sealing layer SE2, and a resin layer RS2 are formed in this order. The resin layers RS1 and RS2 are formed on each panel portion PP by, for example, an inkjet method. The sealing layer SE2 is formed over the entire mother substrate MB by, for example, CVD.

[0092] Next, the mother substrate MB is cut along cut lines CL0. As a result, blocks (for example, blocks BL1 and BL2 shown in FIG. 4) each including a plurality of panel portions PP are cut out from the mother substrate MB. Furthermore, each block is cut along cut lines CL1. As a result, each panel portion PP is cut out. Thereafter, the panel portions PP are cut along cut lines CL2, and the display device DSP is completed.

[0093] The cutting along the cut lines CL0, CL1, and CL2 can be performed by laser cutting using, for example, an infrared laser, although these cuts may also be performed by other methods such as scribe cutting.

[0094] The laminated films FL1, FL2, and FL3 formed by vapor deposition may have poor adhesion to the substrate, which may cause the laminated films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 covering them to peel off from the substrate during the manufacturing of the display device DSP.

[0095] The peeling is likely to occur when the stacked films FL1, FL2, and FL3 are formed continuously over a wide area. In the display area DA, the stacked films FL1, FL2, and FL3 are divided into small pieces by the partition walls 6A. This prevents the peeling.

[0096] In this embodiment, the partition wall 6A is also arranged in the peripheral area SA. Furthermore, the partition wall 6B is arranged in the marginal area BA. This separates the stacked films FL1, FL2, and FL3 over the entire mother substrate MB, thereby suppressing the peeling.

[0097] Furthermore, the configuration of the motherboard MB according to this embodiment can provide the following effects. 9 is a schematic cross-sectional view of a motherboard MBx according to a comparative example of this embodiment, which shows the configuration in the vicinity of the two cut lines CL0, as in FIG.

[0098] In this comparative example, the partition walls 6B are not arranged inside the slits SL2 of the organic insulating layers 12 and 32. Furthermore, the partition walls 6B are not arranged on the organic insulating layers 12 and 32 near the slits SL2.

[0099] In this configuration, residues 6x of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 used to process the partition walls 6B may remain in the slits SL2. That is, in regions where the partition walls 6A and 6B are not formed over a wide area, the amount of each layer to be removed during patterning of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 increases compared to regions where the partition walls 6A and 6B are formed. Therefore, even after etching each layer, some of the layers, particularly the thick second layer L2 and the first layer L1 underneath, may remain.

[0100] For example, such residues 6x are likely to occur in areas where there are steps in the base, such as slits SL2. The same is true near the slits in the organic insulating layers 12 and 32 along the cut lines CL1 and CL2. Residues 6x can also occur near steps, such as near the ends of the organic insulating layers 12 and 32 shown in FIG.

[0101] If the residue 6x overlaps the cut lines CL0, CL1, and CL2, it may cause cutting defects. Furthermore, if the residue 6x overlaps the alignment mark M or the test pads TD1 and TD2, it may adversely affect the positioning and testing of the motherboard MB. Furthermore, because the residue 6x is conductive, if the residue 6x is generated over a wide area, it may contribute to damage due to electrostatic discharge (ESD).

[0102] The residue 6x can be suppressed by increasing the intensity (etching time and etching rate) of the wet etching of the first layer L1, second layer L2, third layer L3, and fourth layer L4, especially the thick second layer L2. However, in this case, the width of the second layer L2 (axis layer 64) is also significantly reduced where the partition walls 6A and 6B are to be formed, and the protrusion length of the upper portion 62 from the side surface of the axis layer 64 increases. This protrusion length is an important parameter for forming the display elements DE1, DE2, and DE3, as shown in Figures 8G to 8J. Therefore, if the protrusion length changes, the design of the display device DSP, including other parameters of the partition walls 6A and 6B, must be reconsidered.

[0103] 6 and 7, in this embodiment, the partition walls 6B are also arranged near the steps of the organic insulating layers 12 and 32. The partition walls 6B are also arranged inside the slits SL2. With this configuration, it is unlikely that an area in the blank area BA will have no partition wall 6B, and as a result, the generation of residues 6x can be suppressed.

[0104] The effect of suppressing the residue 6x can be enhanced by setting a suitable first coverage of the partition walls 6A, 6B on the mother substrate MB. Specifically, the first coverage is preferably 30% or more. Here, the first coverage is the ratio of the total area of ​​the partition walls 6A, 6B to the total area of ​​the panel portions PP and blank areas BA included in the mother substrate MB (i.e., the area of ​​the entire mother substrate MB). The total area of ​​the partition walls 6A, 6B here refers to the sum of the area of ​​the upper portion 62 of the partition wall 6A in a plan view and the area of ​​the upper portion 62 of the partition wall 6B in a plan view.

[0105] If too many partition walls 6B are arranged in the marginal area BA, the first coverage becomes too high, increasing the risk of ESD. Therefore, it is preferable that the first coverage is lower than the second coverage in the panel portion PP. The second coverage is the ratio of the area of ​​the partition walls 6A to the area of ​​one panel portion PP. The area of ​​the partition walls 6A here refers to the area of ​​the upper portion 62 of the partition walls 6A in a plan view.

[0106] The inventors fabricated the following mother substrates MB1, MB2, and MB3 to verify the coverage of the partition walls 6A and 6B and the effect of suppressing the residue 6x. The configurations of the mother substrates MB1, MB2, and MB3, except for the arrangement of the partition walls 6A and 6B, are the same as the mother substrate MB according to this embodiment.

[0107] [Motherboard MB1] 1st coverage: 29%, 2nd coverage: 32% [Motherboard MB2] 1st coverage: 34%, 2nd coverage: 39% [Motherboard MB3] 1st coverage: 35%, 2nd coverage: 42% Among these mother substrates MB1, MB2, and MB3, the generation of residues 6x was observed in mother substrate MB1, which had a first coverage rate of less than 30%, while the generation of residues 6x was well suppressed in mother substrates MB2 and MB3, which had a first coverage rate of 30% or more.

[0108] In addition, the first coverage rate is equal to or less than the second coverage rate for all of the mother substrates MB1, MB2, and MB3. In all of these mother substrates MB1, MB2, and MB3, the occurrence of ESD was suppressed.

[0109] From the above, it can be seen that by setting the first coverage to 30% or more and the second coverage to 30% or less as described above, it is possible to suppress the occurrence of residues 6x and ESD, and improve the yield of the mother substrate MB or the display device DSP.

[0110] All motherboards that can be implemented by a person skilled in the art by appropriately modifying the design based on the motherboard for a display device disclosed in each of the above embodiments also fall within the scope of the present invention as long as they include the gist of the present invention.

[0111] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0112] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0113] DSP...display device, DA...display area, SA...peripheral area, BA...margin area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE2...sealing layer, RS1, RS2...resin layer, MB...motherboard, PP...panel portion, 5...rib layer, 6A, 6B...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer, 65...first top layer, 66...second top layer.

Claims

1. a plurality of panel sections including a display area; marginal areas around the plurality of panel portions; a plurality of display elements arranged in the display area; an overhanging first partition wall disposed on each of the plurality of panel sections and surrounding the plurality of display elements; an overhanging second partition wall disposed in the marginal region; Equipped with a first coverage ratio, which is a ratio of a total area of ​​the first partition walls and the second partition walls to a total area of ​​the plurality of panel portions and the margin region, is 30% or more; Motherboard for display devices.

2. the first covering ratio is lower than a second covering ratio which is a ratio of an area of ​​the first partition wall to an area of ​​each of the plurality of panel portions; The mother substrate for a display device according to claim 1 .

3. The first partition wall and the second partition wall are a conductive lower portion; an upper portion having an end portion protruding beyond a side surface of the lower portion; Equipped with the first partition wall and the second partition wall have the same material at the lower portion; the upper portions of the first partition wall and the second partition wall are made of the same material; The mother substrate for a display device according to claim 1 .

4. The lower part is A bottom layer; a shaft layer formed on the bottom layer and thicker than the bottom layer; Equipped with The mother substrate for a display device according to claim 3 .

5. an organic insulating layer formed on the plurality of panel portions and the marginal area using an organic insulating material; a rib layer made of an inorganic insulating material formed on the plurality of panel portions and the marginal area and covering the organic insulating layer; Furthermore, the rib layer has a plurality of pixel openings overlapping with the plurality of display elements in the display region, the first partition wall and the second partition wall are disposed above the rib layer. The mother substrate for a display device according to claim 1 .

6. the organic insulating layer, the rib layer, the first partition wall, and the second partition wall are not disposed on a cut line for cutting the mother substrate; The mother substrate for a display device according to claim 5 .

7. the organic insulating layer has a slit along the cut line, a portion of the second partition wall is disposed in the slit; The mother substrate for a display device according to claim 6 .

8. the marginal area includes an alignment mark formed of a metal material below the organic insulating layer, the second partition is disposed at a position that does not overlap the alignment mark; The mother substrate for a display device according to claim 6 .

9. the first partition has a plurality of first partition openings overlapping the plurality of pixel openings, respectively; the second partition wall has a plurality of second partition wall openings having the same shape as the first partition wall openings; The mother substrate for a display device according to claim 5 .

10. the second partition wall includes a plurality of segments separated by slits, Each of the plurality of segments has at least one second partition wall opening. The mother substrate for a display device according to claim 9 .

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