Full-array digital 3D ultrasound imaging system with integrated matrix array transducers

Abstract

To provide a method and system for ultrasound imaging and beamforming using a novel matrix array of transducer elements.SOLUTION: The received signal of each transducer array element is amplified. The amplified receive signal of each transducer array element is digitized. Delays and weights are applied to the amplified and digitized received signals. The amplified, digitized, delayed, and weighted receive signals are summed across all transducer elements of the matrix array to form a dynamically focused receive beam. An applicationspecificintegratedcircuit (ASIC) integrated with a matrix array of transducer elements performs such steps.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE

[0001] The present disclosure relates to systems, devices, and methods for ultrasound imaging, particularly for three-dimensional (3D) imaging. [Background technology]

[0002]

[0002] Wide-field 3D imaging with large steering angles generally requires two-dimensional (2D) (matrix) array transducers with high element densities in both azimuth and elevation. On the other hand, high resolution and high sensitivity generally require wide apertures. Therefore, good 3D transducers generally require very large transducer element counts, such as thousands to tens of thousands of elements. A large element count poses significant implementation challenges for imaging systems, particularly for receive beamforming, forcing them to keep the element count small and / or limiting receive beamforming to multi-step beamforming, where only the first step, i.e., the microbeamformer, is located near or integrated into the array, and the second step, i.e., the macrobeamformer, is located in a remote processor. Microbeamformers generally perform intra-subarray beamforming and are typically single-beam analog beamformers, often lacking dynamic focusing capabilities. The macro beamformer performs inter-subarray beamforming and is typically a digital beamformer with dynamic focusing and multi-beam (parallel beam) capabilities. Split processing can create connectivity issues over flex / cables, limiting signal and control data bandwidth.

[0003]

[0003] U.S. Patent Application Publication No. 2021 / 183832, U.S. Patent Application Publication No. 2021 / 028792, U.S. Patent Application Publication No. 2020 / 405271, U.S. Patent Application Publication No. 2020 / 405267, U.S. Patent Application Publication No. 2020 / 405266, U.S. Patent Application Publication No. 2020 / 315586, U.S. Patent Application Publication No. 2019 / 361102, U.S. Patent Application Publication No. 2019 / 299251, U.S. Patent Application Publication No. 2019 / 261954, U.S. Patent Application Publication No. 2019 / No. 261955, U.S. Patent No. 10755692, U.S. Patent Application Publication No. 2018 / 366102, U.S. Patent No. 10857567, U.S. Patent Application Publication No. 2018 / 361431, U.S. Patent Application Publication No. 2019 / 196012, U.S. Patent Application Publication No. 2019 / 212424, U.S. Patent No. 11154276, U.S. Patent Application Publication No. 2019 / 133556, U.S. Patent No. 10641879, U.S. Patent No. 10405829, U.S. Patent Application Publication No. 2016 / 151045 No. 2019 / 388059, U.S. Patent Application Publication No. 2015 / 297193, U.S. Patent Application Publication No. 2017 / 135676, U.S. Patent No. 9592032, U.S. Patent Application Publication No. 2016 / 202349, U.S. Patent Application Publication No. 2016 / 242739, U.S. Patent Application Publication No. 2017 / 296144, U.S. Patent Application Publication No. 2017 / 296145, U.S. Patent No. 9521991, U.S. Patent Application Publication No. 2014 / 243676, U.S. Patent No. 9 No. 439625, U.S. Patent Application Publication No. 2012 / 143059, U.S. Patent No. 8545406, U.S. Patent Application Publication No. 2010 / 249596, U.S. Patent No. 8416643, U.S. Patent No. 8926514, U.S. Patent Application Publication No. 2009 / 326375, U.S. Patent No. 8834369, U.S. Patent Application Publication No. 2009 / 240152, U.S. Patent No. 8137280, U.S. Patent Application Publication No. 2007 / 016023, U.S. Patent Application Publication No. 2009 / 007414,The following patent documents may be relevant: U.S. Patent Application Publication No. 20050068221, U.S. Patent No. 6,937,176, U.S. Patent No. 5,928,152, U.S. Patent No. 5,675,554, U.S. Patent No. 5,685,308, U.S. Patent No. 5,555,534, U.S. Patent Application Publication No. 2001 / 020130, and U.S. Patent No. 5,970,025. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 183832 [Patent Document 2] U.S. Patent Application Publication No. 2021 / 028792 [Patent Document 3] US Patent Application Publication No. 2020 / 405271 [Patent Document 4] US Patent Application Publication No. 2020 / 405267 [Patent Document 5] US Patent Application Publication No. 2020 / 405266 [Patent Document 6] U.S. Patent Application Publication No. 2020 / 315586 [Patent Document 7] US Patent Application Publication No. 2019 / 361102 [Patent Document 8] US Patent Application Publication No. 2019 / 299251 [Patent Document 9] US Patent Application Publication No. 2019 / 261954 [Patent Document 10] US Patent Application Publication No. 2019 / 261955 [Patent Document 11] U.S. Patent No. 10,755,692 [Patent Document 12] US Patent Application Publication No. 2018 / 366102 [Patent Document 13] U.S. Patent No. 10,857,567 [Patent Document 14] US Patent Application Publication No. 2018 / 361431 [Patent Document 15] US Patent Application Publication No. 2019 / 196012 [Patent Document 16] US Patent Application Publication No. 2019 / 212424 [Patent Document 17] U.S. Patent No. 1,154,276 [Patent Document 18] US Patent Application Publication No. 2019 / 133556 [Patent Document 19] U.S. Patent No. 1,0641,879 [Patent Document 20] U.S. Patent No. 10,405,829 [Patent Document 21] US Patent Application Publication No. 2016 / 151045 [Patent Document 22] US Patent Application Publication No. 2019 / 388059 [Patent Document 23] US Patent Application Publication No. 2015 / 297193 [Patent Document 24] US Patent Application Publication No. 2017 / 135676 [Patent Document 25] U.S. Patent No. 9,592,032 [Patent Document 26] US Patent Application Publication No. 2016 / 202349 [Patent Document 27] US Patent Application Publication No. 2016 / 242739 [Patent Document 28] US Patent Application Publication No. 2017 / 296144 [Patent Document 29] US Patent Application Publication No. 2017 / 296145 [Patent Document 30] U.S. Patent No. 9,521,991 [Patent Document 31] US Patent Application Publication No. 2014 / 243676 [Patent Document 32] U.S. Patent No. 9,439,625 [Patent Document 33] US Patent Application Publication No. 2012 / 143059 [Patent Document 34] U.S. Patent No. 8,545,406 [Patent Document 35] US Patent Application Publication No. 2010 / 249596 [Patent Document 36] U.S. Patent No. 8,416,643 [Patent Document 37] U.S. Patent No. 8,926,514 [Patent Document 38] US Patent Application Publication No. 2009 / 326375 [Patent Document 39] U.S. Patent No. 8,834,369 [Patent Document 40] US Patent Application Publication No. 2009 / 240152 [Patent Document 41] U.S. Patent No. 8,137,280 [Patent Document 42] US Patent Application Publication No. 2007 / 016023 [Patent Document 43] US Patent Application Publication No. 2009 / 007414 [Patent Document 44] US Patent Application Publication No. 20050068221 [Patent Document 45] U.S. Patent No. 6,937,176 [Patent Document 46] U.S. Patent No. 5,928,152 [Patent Document 47] U.S. Patent No. 5,675,554 [Patent Document 48] U.S. Patent No. 5,685,308 [Patent Document 49] U.S. Patent No. 5,555,534 [Patent Document 50] US Patent Application Publication No. 2001 / 020130 [Patent Document 51] U.S. Patent No. 5,970,025 Summary of the Invention [Problem to be solved by the invention]

[0005] This disclosure relates to systems, devices, and methods for ultrasound imaging, and in particular to 3D imaging using multiple transducer elements. [Means for solving the problem]

[0006] This disclosure provides a method for full-array digital 3D transmit and receive beamformers that can be integrated onto an application specific integrated circuit (ASIC) that can be integrated onto a high-element-count 2D array transducer, thereby reducing the cost, size, weight, and power of ultrasound imaging systems.

[0007]

[0006] One aspect of the present disclosure provides that the analog signals of all elements of the 2D array are digitized by an N-bit ADC after pre-amplification at a sampling rate of Fs. In some embodiments, the sampling rate (Fs) is 16 times the imaging center frequency. s A single-bit ADC with a T = 16F (e.g., a simple comparator) is used. Using a single-bit ADC can significantly simplify the beamforming architecture and reduce cost and power. Sampling at 16F can enable high-quality dynamic receive beamforming with a T / 16 delay quantization step without the need for upsampling. As an example, a 4,096-element array with a dithered 1-bit ADC per element operating at 16 times the imaging frequency will have a 56 dB digital dynamic range for an imaging BW equal to the imaging frequency.

[0008] Another aspect of the present disclosure is that an on-ASIC dynamic receive beamformer can generate multiple beams in response to each transmit event, which may be essential for high volume rate imaging.

[0009] Another aspect of the present disclosure provides an on-ASIC delay and weight engine that can generate delays and weights for each element and each depth for dynamic receive beamforming. This allows the ASIC to generate any beam with only a few input parameters, namely, beam origin, beam angle, and f-number, thereby significantly reducing the amount of control data required by the ASIC. This significantly simplifies the off-ASIC circuitry and reduces interconnect bus width and bandwidth. In a preferred embodiment, the same delay and weight engine is also used to create delay and weight profiles for transmit beamforming.

[0010] Another aspect of the present disclosure provides a method for ultrasound imaging and beamforming using a matrix array of transducer elements. In step (a), a receive signal for each transducer array element may be amplified. In step (b), the amplified receive signal for each transducer array element may be digitized. In step (c), a delay and weight may be applied to the amplified and digitized receive signals. In step (d), the amplified, digitized, delayed, and weighted receive signals may be summed across all transducer elements of the matrix array to form a dynamically focused receive beam.

[0011] In some embodiments, an application specific integrated circuit (ASIC) is integrated with the matrix array of transducer elements. The ASIC can perform one or more of steps (a)-(d). The ASIC can perform all of steps (a)-(d). The ASIC can perform some of steps (a)-(d), and other circuitry can perform the rest of steps (a)-(d). The ASIC can also form transmit beams.

[0012] In some embodiments, a single receive beam is formed for each transmit event. In some embodiments, two or more receive beams are formed for each transmit event.

[0013] In some embodiments, the matrix array is composed of one or more cMUT transducer elements.

[0014] In some embodiments, the matrix array is composed of one or more pMUT transducer elements.

[0014]

[0015] In some embodiments, the transducer elements of the matrix array are arranged in a square, rotated square, rectangular, parallelogram, hexagonal, circular, or spiral lattice.

[0015]

[0016] In some embodiments, amplifying the received signal applies a depth-varying amplification gain to the received signal.

[0017] In some embodiments, an N-bit ADC digitizes the amplified received signal at a sampling rate Fs. The N-bit ADC may be a successive-approximation (SAR) ADC. The N-bit ADC may be a sigma-delta ADC. The N-bit ADC may be a pipeline ADC. The N-bit ADC may be a flash ADC. The number of bits N of the ADC may be 1. The input of the ADC may be. The sampling rate of the ADC may be programmable. The sampling rate may be a function of the imaging center frequency.

[0016]

[0018] In some embodiments, the delays and weights applied to the amplified and digitized receive signals are one or more of element-dependent or depth-dependent. The delays and weights for each element and each depth may be calculated by at least one on-ASIC delay and weight calculator. The at least one on-ASIC delay calculator may calculate delays for each element for a portion of the depth using a CORDIC algorithm and may interpolate between CORDIC-based delays for intermediate depth grid points. The delay interpolation for the intermediate depth grid points may be linear. The at least one on-ASIC delay calculator may calculate delays for a portion of the elements using a CORDIC algorithm and may interpolate between CORDIC-based delays for intermediate elements. The delay interpolation for the intermediate elements may be linear. The at least one on-ASIC delay calculator may calculate delays for a portion of the beams using a CORDIC algorithm and may interpolate between CORDIC-based delays for intermediate beams. The delay interpolation for the intermediate beams may be linear.

[0017]

[0019] In some embodiments, at least one on-ASIC weight calculator may assist in performing step (c).

[0020] In some embodiments, the at least one on-ASIC weight calculator calculates a weight for each element and each range sample based on the depth, the f-number, and the distance between the element and the beam origin. The element weights can be binary. The at least one on-ASIC weight calculator can expand the effective aperture with depth to a substantially circular or elliptical shape to reduce side lobes.

[0018]

[0021] Another aspect of the present disclosure provides a system for ultrasound imaging. An exemplary system can include a matrix array of transducer elements and circuitry having the matrix array. The circuitry can be configured to (a) amplify a receive signal for each transducer array element, (b) digitize the amplified receive signal for each transducer array element, (c) delay and weight the amplified and digitized receive signals, and (d) sum the amplified, digitized, delayed, and weighted receive signals across all transducer elements of the matrix array to form a dynamically focused receive beam.

[0019]

[0022] In some embodiments, the circuitry comprises an application specific integrated circuit (ASIC) integrated with the matrix array of transducer elements. The ASIC can perform one or more of steps (a)-(d). The ASIC can perform all of steps (a)-(d). The circuitry can further comprise other circuitry, where the ASIC can perform some of steps (a)-(d) and the other circuitry can perform the rest of steps (a)-(d).

[0020]

[0023] In some embodiments, the circuitry is also configured to form transmit beams. A single receive beam may be formed per transmit event. Two or more receive beams may be formed per transmit event.

[0021]

[0024] In some embodiments, the matrix array is composed of one or more cMUT transducer elements.

[0025] In some embodiments, the matrix array is composed of one or more pMUT transducer elements.

[0022]

[0026] In some embodiments, the transducer elements of the matrix array are arranged in a square, rotated square, rectangular, parallelogram, hexagonal, circular, or spiral lattice.

[0023]

[0027] In some embodiments, the circuitry is configured to amplify the received signal by applying a depth-varying amplification gain to the received signal.

[0028] In some embodiments, the circuitry includes an N-bit ADC for digitizing the amplified received signal at a sampling rate. The N-bit ADC may be a successive approximation register (SAR) ADC. The N-bit ADC may be a sigma-delta ADC. The N-bit ADC may be a pipeline ADC. The N-bit ADC may be a flash ADC. The number of bits N of the ADC may be 1. The input of the ADC may be dithered. The sampling rate of the ADC may be programmable. The sampling rate may be a function of the imaging center frequency.

[0024]

[0029] In some embodiments, the delays and weights applied to the amplified and digitized receive signals are one or more of element-dependent or depth-dependent. The circuitry can include at least one on-ASIC delay and weight calculator to calculate the delays and weights for each element and depth. The at least one on-ASIC delay calculator can calculate the delay for each element for a portion of the depth using a CORDIC algorithm and can interpolate between CORDIC-based delays for intermediate depth grid points. The delay interpolation for the intermediate depth grid points can be linear. The at least one on-ASIC delay calculator can calculate the delay for a portion of the elements using a CORDIC algorithm and can interpolate between CORDIC-based delays for intermediate elements. The delay interpolation for the intermediate elements can be linear. The at least one on-ASIC delay calculator can calculate the delay for a portion of the beam using a CORDIC algorithm and can interpolate between CORDIC-based delays for intermediate beams. The delay interpolation for the intermediate beams can be linear.

[0025]

[0030] In some embodiments, the circuitry includes at least one on-ASIC weight calculator to calculate a weight for each element and each range sample based on the distance between the element and the beam origin and the f-number. The element weights can be binary. The at least one on-ASIC weight calculator can expand the effective aperture with depth to a substantially circular or elliptical shape to reduce side lobes.

[0026]

[0031] Another aspect of the present disclosure provides a method and system for ultrasound beamforming using a matrix array of transducer elements.

[0032] In an exemplary method, delays can be added to received signals from a matrix array by performing at least one CORDIC (COordinate Rotation Digital Computer) operation. The at least one CORDIC operation can include two cascaded CORDIC operations. The two cascaded CORDIC operations can include a first CORDIC operation and a second CORDIC operation, and an output of the first CORDIC operation can be an input to the second CORDIC operation. The at least one CORDIC operation can be performed by an application specific integrated circuit (ASIC) operably coupled to the matrix array. A delay for each transducer element of the matrix array can be determined for a portion of the depth by the at least one CORDIC operation. Delays for intermediate depth grid points can be interpolated. Delays for intermediate elements can be interpolated. Delays for intermediate beams can be interpolated.

[0027]

[0033] In an exemplary system, the system may comprise a matrix array of transducer elements and circuitry coupled to the matrix array and configured to perform the exemplary methods described above. Incorporation by Reference

[0034] All patent publications, patents, and patent applications mentioned in this specification are herein incorporated by reference to the same extent as if each individual patent publication, patent, or patent application was specifically and individually indicated to be incorporated by reference.

[0028]

[0035] A further understanding of the features and advantages of the present disclosure will be obtained by reference to the following detailed description that sets forth illustrative embodiments and the accompanying drawings. [Brief explanation of the drawings]

[0029] [Figure 1]

[0036] FIG. 1 is an exemplary schematic diagram of an ultrasound system that uses a transducer assembly composed of a 2D array of transducers and an ASIC mounted on a PCB with additional circuitry, and a remote processor with a user interface and display. [Figure 2a]

[0037] Schematic diagram of a digital 3D single-stage full-array beamformer with ASIC. [Figure 2b] Same as above. [Figure 3a]

[0038] Schematic diagram of a digital 3D two-stage full-array beamformer with ASIC. [Figure 3b] Same as above. [Figure 4]

[0039] 1 is a graph of the geometry of an ultrasound beam produced by an ultrasound transducer array. [Figure 5]

[0040] 10 is a flow diagram of a 3D dynamic delay and weight calculator. DETAILED DESCRIPTION OF THE INVENTION

[0030]

[0041] Unless otherwise defined, all technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter belongs. Ultrasound Imaging System

[0042] FIG. 1 illustrates an exemplary embodiment of an ultrasound imaging system disclosed herein. The imaging system can include an ASIC (100), which is preferably integrated with a transducer 200. The transducer can be a one- or two-dimensional array of pMUTs (piezoelectric micromachined ultrasonic transducers), cMUTs (capacitive micromachined ultrasonic transducers), or bulk PZT elements. The ASIC and transducer array are typically mounted on a PCB (or multiple PCBs) (300). The PCB can contain additional circuitry such as a microprocessor, power supply (battery, regulator), clock, memory, and input / output devices.

[0031]

[0043] The ASIC, transducer array, and PCB form the transducer assembly (400). To keep the footprint small, the area of ​​the transducer assembly can match the area of ​​the transducer array. The transducer assembly can be packaged in a patch or in a wearable or retainable housing.

[0032]

[0044] The transducer assembly can communicate with a remote processor (500) via input / output devices, which can include a user interface, a display, and memory. The processor can be a mobile device such as a smartphone, smartwatch, pad, or laptop, or can be a desktop computer. The processor can perform image processing, planar and volumetric rendering, and can connect to networks and databases such as electronic health records. Communication between the transducer assembly and the remote processor can be wired or wireless and can use standard communication protocols.

[0033]

[0045] The microprocessor on the transducer assembly can initialize the ASIC with a small set of parameters, such as the imaging frequency and transmit and receive f-numbers, and then provide the transmit and receive beam parameters (beam origin, angle, focal depth) for each pulse-echo (transmit-receive) event in the scan sequence. The delay and weight calculator on the ASIC can calculate the transmit and receive beamforming parameters (delays and weights) for each beam defined by the transmit and receive beam parameters. The ASIC can send steered and focused transmit pulses, receive echoes from tissue at each transducer element, and form receive beams using the delays and weights calculated by the ASIC. The output of the ASIC is typically a fully formed beam using an open aperture.

[0034]

[0046] The following sections describe the transducer assembly, transmitter and receiver, the geometries used in the derivation of the 3D delay equations, and methods and devices for delay and weight calculations using the 3D delay equations. Transducer Assembly

[0047] Figure 2 shows details of the transducer assembly (400) and the ASIC (100) within the transducer assembly. The ASIC receives inputs (101) from a microprocessor on the PCB (300). These inputs can include initialization parameters such as transmit center frequency and bandwidth, transmit and receive f-numbers, and receive center frequency and bandwidth. The ASIC can also receive transmit and receive beam parameters and triggers for each pulse-echo event. The transmitter can generate transmit pulses (110), apply element-coordinate-dependent delays (111a) and weights (111b) to the pulses, and drive the pulsers (112) of each acoustic element with the delayed and weighted pulses based on the transmit pulse and transmit beam parameters.

[0035]

[0048] The receive path for each acoustic element can contain a transmit / receive switch (121), an analog front end (122) for low-noise preamplification, time gain compensation, and anti-aliasing, an ADC (123), element memory (124), and a beamformer (125) that can apply time-varying (dynamic) delays and weights to the stored element data. The transmit beamformer (delay and weight), pulser, receive switch, analog front end, ADC, memory, and receive beamformer (delay and weight) circuitry can form an electronic element (120). There can be one electronic element per acoustic element.

[0036]

[0049] The outputs of the electronic elements across the entire array (140) can be summed to complete full-array beamforming. The beams thus formed can then be filtered by a receive filter (150) for data compression, which may include demodulation to baseband with a complex time-varying multiplier followed by a low-pass baseband filter (BBF). Using the same element data stored in memory, the delay, weight, array summation, and receive filter circuitry can be replicated to form multiple beams (160) with distinct delay and / or weight parameters in parallel. An on-ASIC 3D dynamic delay and weight calculator (170) can generate delays and weights for transmit and receive beamforming (for all parallel beams). The output of the ASIC (102) can be complex (in-phase and quadrature) samples of the parallel beams. The transducer assembly stores the output beams and sends them to a remote processor (500) for further processing, rendering, and display.

[0037]

[0050] The receive beamforming of Figure 2 can also be implemented in multiple stages. Figure 3 shows a two-stage version. The multi-stage implementation allows flexibility for reducing the size of both the element memory and the parallel beam circuitry. Rather than summing the outputs of all electronic elements, the outputs of a subset of electronic elements (subarrays) (130) can be summed (131) and stored in a second set of subarray memories (132). Note that the first stage of beamforming within each subarray can also be referred to as micro-beamforming. The second stage adds delays and weights (133) to the subarray beamformer outputs, allowing full-array beamforming to be completed by array summation (140). Only the second stage circuitry (macro-beamformer) can be replicated for parallel beam operation. The subarray size can be reduced by 131. x ×S y element, where S x and S y can be 2, 3, 4, 5, etc. electronic elements. Transmitter

[0051] A single K-bit deep, L-bit long shift register with a programmable clock can serve as the arbitrarily programmable pulse generator (110).

[0038]

[0052] The depth K of the shift register can be determined by the number of pulser states. Generally, a K-bit deep shift register can have a maximum of 2 K states. Thus, K is 1 for two-state (unipolar) pulsers, 2 for three-state (bipolar) and four-state pulsers, and so on.

[0039]

[0053] The length of the shift register, L, can be determined by the maximum pulse length specification and the transmitter clock frequency. In a preferred embodiment, the shift register length, L, is set to 256 bits. This will accommodate pulses up to 16 cycles long, with a transmit clock cycle 16 times the transmit center frequency. Pulses longer than 16 cycles can also be accommodated by lowering the transmitter clock frequency (a trade-off in delay quantization steps).

[0040]

[0054] The simplest type of pulse may be a unipolar pulse, in which the active node of the transducer element is switched between ground and a positive (or negative) voltage rail by two complementary switches. These switches may be controlled by a single bit stream: a set of ones for the +V segment followed by a set of zeros for GND; this pattern of ones and zeros is repeated for the required number of cycles. Each bit may represent the duration of a transmitter clock cycle. Thus, if the transmitter clock cycle is 16F0, the bit stream for a two-cycle pulse at F0 would be 11111111000000001111111100000000. The durations of the individual +V and GND segments may be fixed or independently programmable, for example, for linear (or nonlinear) frequency modulation or some other coded excitation. Such a bit pattern may be pre-generated, loaded into a pulse generator shift register within the ASIC during initialization, and triggered upon receiving an impulse indicating the start of transmission. In some embodiments, the start and / or end of the pulse can be indicated by a very short code such as 010 to trigger other transmit and / or receive circuitry on or off, e.g.

[0041]

number

[0042] Utilizing such an embedded code may require a decoder (matched filter) of the same length. In some embodiments, each element's transmit / receive switch can be turned on to turn on receive mode as soon as the element has completed its own pulse transmission, rather than waiting for all elements to finish transmitting their pulses. This can help clean up some of the near-field artifacts by distributing the stray transmit and receive enable / disable signals in time, and eliminate dead bands due to missed receive samples.

[0043]

[0055] The next most complex is the three-state bipolar pulse, where the active node of the transducer element is changed between positive, ground, and negative voltage rails by three complementary switches. This type of pulse can be implemented using a two-bit deep pulse stream, where, for example, 00 indicates ground, 10 indicates +V, and 01 indicates -V. The 11 states can be used to indicate the start and / or end of the pulse.

[0044]

[0056] A special case of a three-state bipolar pulse grounds the transducer before the pulse begins and only after the pulse ends, switching between +V and -V states during the pulse. This type of pulse can provide the best second-harmonic suppression compared to all two-state pulses and three-state pulses with a ground segment within the pulse. This type of pulse can also result in the simplest (lowest-cost) architecture in terms of power supply. This special case of a bipolar pulse can be implemented using the single bit stream described above, with 1s mapped to +V and 0s mapped to -V. The embedded code fragment described above can be used to indicate the beginning of the ground state at the end of the pulse. Receiving this code grounds the transducer element until the beginning of the next pulse, indicated by a stream of 1s. Pulse reversal capability can be added with an additional programmable bit common to all elements that reverses the mapping of 1 and 0 values ​​to -V and +V in the pulser.

[0045]

[0057] When the impulse indicates the beginning of a pulse-echo event, which typically repeats at a regular pulse repetition interval (PRI), a pulse common to all elements can be generated. The pulse can then be delayed by element-specific delays for all elements of the array (111a). For apodization, the delayed pulse can then be weighted by element-specific weights; here, simple binary on / off weights are shown. In a preferred embodiment, both the delays and weights for the transmit beamformer are generated by an on-ASIC delay and weight calculator (170) before the transmit event begins.

[0046]

[0058] The output of the apodization, after digital-to-analog conversion, can drive a transmit pulser (112).

[0059] In some embodiments, the pulse generator and delay operation share the same transmitter clock for architectural simplicity. Furthermore, for efficiency purposes, the transmitter clock frequency F s may be varied as a function of the transmit center frequency F0 and may be set equal to 16F0 to achieve the desired delay quantization step T0 / 16, where T0=1 / F0.

[0047]

[0060] In some embodiments, the order of the pulse generator, delay, and binary weights can be changed, for example, the binary weights can be moved before the delay operation, or the delay operation can be moved before the pulse generator, etc., for various architectural tradeoffs. Receiver

[0061] A typical receiver consists of individual elements ij The echoes from (t) are dynamically adjusted with gain, delay, and weight (apodization), where (i,j) are the column and row numbers of the elements in the matrix array. The beamformer then sums the amplified, delayed, and weighted element signals to form a beam.

[0048]

number

[0049] where

[0050]

number

[0051] is the coordinate of the beam origin (x O ,y O ,z O ) (for planar arrays, z O is zero), r is the depth,

[0052]

number

[0053] are the beam angles in the zx and zy planes. In the case of a digital beamformer, the analog signal can be converted to digital by an ADC after the LPF and before the delay stage.

[0054]

number

[0055]

[0062] The gain G(t) is the static low noise amplifier gain G LNA , and a dynamic time-varying gain G to compensate for tissue attenuation TGC It may have multiple programmable components, including (t) (also called time gain compensation). The final gain stage may be an optional programmable gain amplifier.

[0056]

[0063] A low pass filter (LPF), preferably with a programmable cutoff frequency, provides anti-aliasing and improves SNR. Multiple poles of the LPF can be distributed among the various gain stages.

[0057]

[0064] Dynamic delays are used to track the depth at which echoes occur as the transmit beam propagates deeper into tissue.

[0058]

number

[0059] can vary with time. The input of a delay stage is a function of time, and its output is a function of depth (range). Because of the time-varying delay, the depth is a distorted time.

[0065] Dynamic Apodization or Weighting

[0060]

number

[0061] The effective aperture size can be expanded with depth to maintain resolution, and the edge element contributions are gradually reduced, i.e., apodized, to reduce beam sidelobes. In the case of a matrix array, the effective aperture shape can also have an apodization effect. In some embodiments, the apodization weight is depth-dependent but binary: 0 for off and 1 for on, thereby eliminating the need for per-element and per-depth multiplications. Semicircular apodization is achieved by turning on elements around the beam origin in a constantly expanding circle or ellipse. The expansion ratio of the circle and ellipse can be controlled by a programmable f-number. G is used before the delay operation. TGC is added so that the gain can be distributed over time as a function of the element-dependent delay, which can provide an additional apodization effect for depths where the gain changes rapidly.

[0062]

[0066] Dynamic delay and weight calculations are performed based on the beam parameters

[0063]

number

[0064] and

[0065]

number

[0066] Element coordinates

[0067]

number

[0068] ADC sampling rate F s , the speed of sound c0, as well as the f-value, can be performed by a calculator. In many prior art systems, these calculations are performed entirely or partly on a remote processor.

[0069] The element summation stage can sum the time-aligned (and therefore coherent) weighted element signals.

[0068] Multiple beams with independent origins and angles can be generated in parallel using replicated sets of delays, weights, and element summation stages. Alternatively, if element data is stored for the entire depth of interest, multiple beams can be formed sequentially using a single beamformer circuitry using the time between transmit events, trading off frame rate. Array and beam geometry FIG. 4 shows a graph of N on an xy plane (or a non-planar curved xyz surface not shown in FIG. 4) centered at (0,0,0) in Cartesian coordinates. x ×N y A 2D array of elements (201) is shown.

[0070]

number

[0071] are the x, y, and z coordinates of the (i,j)th element (x i ,y j,z ij ) The elements of the 2D array can be a square or rectangular grid, a rotated square, a rhombus (parallelogram), a hexagon, a torus, or any grid. The physical apertures can be square, rectangular, circular or oval, or any shape.

[0072] The beam has a focal depth r in the case of a static transmit focus, or a set of focal depths in the case of a dynamic receive focus, a (nominal) beam origin which is a vector of x, y, and z coordinates.

[0073]

number

[0074] and an angle which is also an angle vector in the zx and zy planes

[0075]

number

[0076] It can be defined in 3D by the following three parameters:

[0077]

number

[0078] and

[0079]

number

[0080] We use bold to represent vectors such as . The receive beam at depth (or range) r

[0081]

number

[0082] The coordinates of the sample along are

[0083]

number

[0084] is.

[0085]

number

[0086] The rule is θ zx and θ zy are positive from the +z axis to the +x and +y axes, respectively.

[0087]

number

[0088] is also at zero depth (r=0).

[0089]

number

[0090] is the beam diameter, excluding truncation due to physical apertures.

[0091]

number

[0092] All samples of the receive beam are projected onto the zx and zy planes at angles θ zx and θ zy It is located on the line at

[0071] 2D imaging in the azimuthal (i.e., xz) plane is performed by θ zyand y O is a special case where θ is zero. 2D imaging in the orthogonal elevation (yz) plane is zx and x O A special case of 2D imaging corresponds to the case where the array is a 1D array, e.g., N y =1.

[0093] The geometries defined herein can correspond to independent combinations of scanning geometries for azimuth and elevation. For example, to define a sector geometry in both azimuth and elevation, x O and y O Both are set to 0 for all beams. For linear scanning, e.g., elevation, θ zy is set to zero for all beams, and y O will vary from the first row to the last row. In the case of vector form such as elevation angle, θ zy varies from negative to positive angles, and y O will vary from the first line to the last line.

[0094]

[0073] The geometry here can be similarly applied to multi-stage beamforming, where the first stage subarray beamformer (microbeamformer) is S x ×S y Perform beamforming on groups of elements and then use the second stage M x ×M y The beamformer (macro beamformer) completes the beamforming on the output of the subarray beamformer, where N x =S x M x and N y =S y M y is.

[0095]

[0074] Note that there are alternative coordinate systems for defining a beam in 3D, such as spherical coordinates.

[0096]

number

[0097] The angle (θ, φ) of the spherical coordinates centered on and the beam angle (θ zx ,θ zy ) is as follows:

[0098]

number

[0099] The analysis and derivations herein can be applied with minor modifications to any alternative beam definition. 3D Delay Equation Next, for a particular element (i, j), the beam

[0100]

number

[0101] Distance along the

[0102]

number

[0103] can be derived.

[0077] beam sample,

[0104]

number

[0105] Cartesian coordinates of (b x ,b y ,b z )teeth, (b x ,b y ,b z )=r(v x ,v y ,v z)+(x O ,y O ,z O ) where the unit vector along the beam

[0106]

number

[0107] teeth,

[0108]

number

[0109] and The x, y, z coordinates of the beam are:

[0110]

number

[0111] is.

[0112]

[0080] Next,

[0113]

number

[0114] and

[0115]

number

[0116] The distance between

[0117]

number

[0118] is given by The square root of the sum of the squares of three terms can be written as the square root of the sum of the squares of two terms as follows:

[0119]

number

[0120]

[0082] Delay in μsec

[0121]

number

[0122] is the distance in mm

[0123]

number

[0124] divided by the two-way sound velocity c0 in mm / μsec,

[0125]

number

[0126] is the sampling rate of the ADC in MHz, F s In units of sample size

[0127]

number

[0128] is. 3D Dynamic Delay and Weight Calculator The above delay formula lends itself to an efficient implementation using CORDIC (Coordinate Rotation Digital Computing), an efficient method for calculating the square root of the square of two numbers. Figure 5 shows the block diagram and steps of a Dynamic 3D Delay and Weight Calculator (170) using two cascaded CORDIC operations (176).

[0129]

[0084] Inputs to the delay and weight calculator may include the beam origin, unit vector and focal depth, element coordinates, ADC sampling rate, sound speed, and f-number.

[0085] The beam unit vector Cartesian coordinate (171) can be multiplied (172) by the depth and added (173) to the beam origin coordinate to produce the beam sample Cartesian coordinate for a particular depth r (174). The x, y, and z coordinates of the element can be subtracted (175) from the respective x, y, and z coordinates of the beam sample to produce the input to the CORDIC operation. The output of the first CORDIC and the x component of the beam sample can form the input to the second CORDIC. The output of the second CORDIC is the combination of element (i,j) and the beam sample,

[0130]

number

[0131] and the distance between the delay calculator and the delay time can be provided, where the distance is scaled by the gain of the two CORDIC stages (CORDIC is not a unity gain operation). In a preferred implementation, the CORDIC gain compensation can be performed by a distance delay conversion multiplier (178) located at the output of the delay calculator.

[0132] In some embodiments, the cascaded CORDICs each perform eight angle rotations. This number of rotations is sufficient to obtain a maximum range error within T / 16, where T is the period at the imaging center frequency F. Each angle rotation can perform two bit shifts and two additions. With eight angle rotations, each CORDIC stage has a gain equal to approximately 1.65, and the two CORDIC stages together have a total gain of approximately 2.71.

[0133] Note that high-precision range (delay) calculations based on CORDIC may only be required for a sparse set of depths, elements, and beams. Linear interpolation (177) between CORDIC-calculated range values ​​may be sufficient to keep delay errors within specifications. In some embodiments, a coarse range grid is

[0134]

number

[0135] The coarse element grid is spaced four elements apart in both azimuth and elevation. Again, a linear distance interpolator can interpolate distance values ​​for the intermediate elements. Linear interpolation for power-of-two upsampling can be very efficient because it requires only additions and bit shifts.

[0136] The final stage of the delay engine (178) can compensate for the non-unit gain of the CORDIC stage and uses the ADC sampling rate and sound speed as inputs to calculate distance in mm.

[0137]

number

[0138] delay in units of the ADC sample rate

[0139]

number

[0140] Having a range-delay conversion at the final output allows for an easy way to optimize the bulk sound speed depending on the clinical application and optimize the ADC sample rate as a function of the imaging center frequency.

[0141]

[0089] The order of linear operations is interchangeable: for example, the range-delay conversion can be performed at any point in the delay calculator signal path, or the interpolations can be reordered depending on implementation-specific considerations.

[0142] In some embodiments, the weights are binary, i.e., the element is either on or off at any particular time / depth. The delay calculator can provide input to the weight calculator. Note that the distance between any element and the beam origin can be calculated by the delay calculator by setting r to zero:

[0143]

number

[0144] During a receive event, this distance can be scaled by a scalar that is a function of the f-number (aperture expansion factor) and compared to the distance output of the delay calculator to turn on each element at the correct time (depth) (179). This method allows the aperture to be expanded as a circle around the beam origin. Alternatively, both the expansion factor and the aperture limit can be programmed independently in x and y, for example for rectangular or elliptical aperture expansion.

[0145] While preferred embodiments have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Numerous variations, changes, and substitutions will occur to those skilled in the art without departing from the scope of the present disclosure. It is understood that various alternatives to the embodiments described herein can be employed in practice. Many different combinations of the embodiments described herein are possible, and such combinations are considered to be part of this disclosure. In addition, all features discussed in connection with any one embodiment herein can be readily adapted for use with other embodiments herein. The following claims define the scope of the present disclosure, and it is intended that methods and structures within the scope of these claims and their equivalents be covered thereby.

Claims

1. 1. A method for ultrasound imaging and beamforming using a matrix array of transducer elements, comprising: a) amplifying the received signal of each transducer array element; b) digitizing the amplified receive signal for each transducer array element; c) delaying and weighting the amplified and digitized receive signals; and d) summing the amplified, digitized, delayed and weighted receive signals across all transducer elements of the matrix array to form a dynamically focused receive beam. A method comprising:

2. The method of claim 1 , wherein an application specific integrated circuit (ASIC) is integrated with the matrix array of transducer elements.

3. The method of claim 2 , wherein the ASIC performs one or more of steps (a) through (d).

4. The method of claim 3 , wherein the ASIC performs all of steps (a) through (d).

5. 4. The method of claim 3, wherein the ASIC performs some of steps (a) through (d) and other circuitry performs the remainder of steps (a) through (d).

6. The method of any one of claims 2 to 5, wherein the ASIC also forms transmit beams.

7. The method of any one of claims 1 to 6, wherein a single receive beam is formed for each transmit event.

8. The method of any one of claims 1 to 6, wherein for each transmit event, two or more receive beams are formed.

9. The method according to any one of claims 1 to 8, wherein the matrix array is composed of one or more cMUT transducer elements.

10. The method of any one of claims 1 to 9, wherein the matrix array is composed of one or more pMUT transducer elements.

11. 11. The method of any one of claims 1 to 10, wherein the transducer elements of the matrix array are arranged in a square, rotated square, rectangular, parallelogram, hexagonal, circular, or spiral lattice.

12. The method of any one of claims 1 to 11, wherein amplifying the received signal comprises applying a depth-varying amplification gain to the received signal.

13. The method of any one of claims 1 to 12, wherein an N-bit ADC digitizes the amplified received signal at a sampling rate Fs.

14. 14. The method of claim 13, wherein the N-bit ADC is a successive-approximation (SAR) ADC.

15. The method of claim 13 , wherein the N-bit ADC is a sigma-delta ADC.

16. The method of claim 13 , wherein the N-bit ADC is a pipelined ADC.

17. The method of claim 13 , wherein the N-bit ADC is a flash ADC.

18. The method of claim 13 , wherein the number of bits N of the ADC is 1.

19. The method of claim 13 , wherein the input of the ADC is dithered.

20. The method of claim 13 , wherein the sampling rate of the ADC is programmable.

21. The method of claim 20, wherein the sampling rate is a function of an imaging center frequency.

22. A method according to any preceding claim, wherein the delays and weights applied to the amplified and digitised received signals are one or more of element dependent or depth dependent.

23. 23. The method of claim 22, wherein the delays and weights for each element and each depth are calculated by at least one on-ASIC delay and weight calculator.

24. 24. The method of claim 23, wherein the at least one on-ASIC delay calculator calculates delays for each element for a portion of the depth by a cordic algorithm and interpolates between cordic-based delays for intermediate depth grid points.

25. The method of claim 24 , wherein the delay interpolation for the intermediate depth grid points is linear.

26. 26. A method according to any one of claims 23 to 25, wherein the at least one on-ASIC delay calculator uses a CORDIC algorithm to calculate delays for some of the elements and interpolates between CORDIC-based delays for intermediate elements.

27. 27. The method of claim 26, wherein the delay interpolation for the intermediate elements is linear.

28. 28. A method according to any one of claims 23 to 27, wherein the at least one on-ASIC delay calculator uses a cordic algorithm to calculate delays for some of the beams and interpolates between cordic-based delays for intermediate beams.

29. 30. The method of claim 28, wherein the delay interpolation for the intermediate beams is linear.

30. A method according to any one of claims 23 to 29, wherein at least one on-ASIC weight calculator assists in performing step (c).

31. A method according to any preceding claim, wherein at least one on-ASIC weight calculator calculates the weight for each element and each range sample based on depth, f-number and distance between the element and the beam origin.

32. 32. The method of claim 31 , wherein the element weights are binary.

33. 32. The method of claim 31, wherein the at least one on-ASIC weight calculator expands an effective aperture with depth as a substantially circular or elliptical shape to reduce side lobes.

34. 1. A system for ultrasound imaging, comprising: i. a matrix array of transducer elements; ii. A circuit configuration having the matrix array, a) amplifying the received signal of each transducer array element; b) digitizing the amplified receive signal for each transducer array element; c) delaying and weighting the amplified and digitized received signal; d) summing the amplified, digitized, delayed, and weighted receive signals across all transducer elements of the matrix array to form a dynamically focused receive beam; A circuit configuration configured as follows: A system comprising:

35. 35. The system of claim 34, wherein the circuitry comprises an application specific integrated circuit (ASIC) integrated with the matrix array of transducer elements.

36. 36. The system of claim 35, wherein the ASIC performs one or more of steps (a) through (d).

37. 37. The system of claim 36, wherein the ASIC performs all of steps (a) through (d).

38. the circuit configuration further comprises other circuit configurations; The ASIC performs a part of steps (a) to (d), and the other circuit configuration performs the rest of steps (a) to (d).

37. The system of claim 36.

39. A system according to any one of claims 34 to 38, wherein the circuitry is also configured to form transmit beams.

40. A system according to any one of claims 34 to 39, wherein a single receive beam is formed for each transmit event.

41. A system according to any one of claims 34 to 39, wherein two or more receive beams are formed for each transmit event.

42. The system of any one of claims 34 to 41, wherein the matrix array is comprised of one or more cMUT transducer elements.

43. The system of any one of claims 34 to 42, wherein the matrix array is comprised of one or more pMUT transducer elements.

44. 44. The system of any one of claims 34 to 43, wherein the transducer elements of the matrix array are arranged in a square, rotated square, rectangular, parallelogram, hexagonal, circular, or spiral lattice.

45. A system according to any one of claims 34 to 44, wherein the circuitry is configured to amplify the received signal by applying a depth-varying amplification gain to the received signal.

46. A system according to any one of claims 34 to 45, wherein the circuitry comprises an N-bit ADC for digitising the amplified received signal at a sampling rate.

47. 47. The system of claim 46, wherein the N-bit ADC is a successive-approximation (SAR) ADC.

48. 47. The system of claim 46, wherein the N-bit ADC is a sigma-delta ADC.

49. 47. The system of claim 46, wherein the N-bit ADC is a pipelined ADC.

50. 47. The system of claim 46, wherein the N-bit ADC is a flash ADC.

51. 47. The system of claim 46, wherein the number of bits N of the ADC is 1.

52. 47. The system of claim 46, wherein the input of the ADC is dithered.

53. 47. The system of claim 46, wherein the sampling rate of the ADC is programmable.

54. 54. The system of claim 53, wherein the sampling rate is a function of an imaging center frequency.

55. A system according to any one of claims 34 to 54, wherein the delays and weights applied to the amplified and digitised received signals are one or more of element dependent or depth dependent.

56. 56. The system of claim 55, wherein the circuitry comprises at least one on-ASIC delay and weight calculator for calculating the delays and weights for each element and each depth.

57. 57. The system of claim 56, wherein the on-ASIC delay calculator calculates the delay for each element for a portion of the depth by a cordic algorithm and interpolates between cordic-based delays for intermediate depth grid points.

58. 58. The system of claim 57, wherein the delay interpolation for the intermediate depth grid points is linear.

59. 59. The system of any one of claims 56 to 58, wherein the at least one on-ASIC delay calculator calculates delays for some of the elements using a CORDIC algorithm and interpolates between CORDIC-based delays for intermediate elements.

60. 60. The system of claim 59, wherein delay interpolation for the intermediate elements is linear.

61. 61. The system of any one of claims 56 to 60, wherein the at least one on-ASIC delay calculator uses a CORDIC algorithm to calculate delays for some of the beams and interpolates between CORDIC-based delays for intermediate beams.

62. 62. The system of claim 61, wherein delay interpolation for the intermediate beams is linear.

63. 63. The system of any one of claims 34 to 62, wherein the circuitry comprises at least one on-ASIC weight calculator for calculating the weight for each element and each range sample based on the distance between the element and the beam origin and the f-number.

64. 64. The system of claim 63, wherein the element weights are binary.

65. 64. The system of claim 63, wherein the at least one on-ASIC weight calculator expands an effective aperture with depth as a substantially circular or elliptical shape to reduce side lobes.

66. 1. A method for ultrasound beamforming using a matrix array of transducer elements, comprising: adding a delay to the received signal from the matrix array by performing at least one CORDIC (COordinate Rotation Digital Computer) operation; A method comprising:

67. 67. The method of claim 66, wherein the at least one cordic operation comprises two cascaded cordic operations.

68. the two cascaded cordic operations include a first cordic operation and a second cordic operation; 68. The method of claim 67, wherein an output of the first cordic operation becomes an input to the second cordic operation.

69. 69. A method according to any one of claims 66 to 68, wherein the at least one cordic operation is performed by an application specific integrated circuit (ASIC) operatively coupled to the matrix array.

70. 70. A method according to any one of claims 66 to 69, wherein the delay for each transducer element of the matrix array is determined over a portion of the depth by the at least one cordic operation.

71. 71. The method of claim 70, further comprising the step of interpolating between delays for intermediate depth grid points.

72. 71. The method of claim 70, further comprising the step of interpolating between delays for intermediate elements.

73. 71. The method of claim 70, further comprising the step of interpolating between delays for intermediate beams.

74. 1. A system for ultrasound imaging, comprising: a matrix array of transducer elements; a circuit arrangement coupled to the matrix array and configured to perform the method of any one of claims 66 to 73; A system comprising:

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