Semiconductor device

Abstract

To provide a semiconductor device with improved reliability. A semiconductor device having stable characteristics is provided. A transistor having a low off-state current is provided. A transistor having a high on-state current is provided. A novel semiconductor device, a novel electronic device, or the like is provided.SOLUTION: In the semiconductor device, a first semiconductor is formed over a substrate, a second semiconductor is formed over and in contact with the first semiconductor, a first layer is formed over the second semiconductor, oxygen plasma treatment is performed, the first layer is removed to expose at least part of a surface of the second semiconductor, a third semiconductor is formed over and in contact with the second semiconductor, a first insulator is formed over and in contact with the third semiconductor, and a first conductor is formed over the first insulator.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. Therefore, one aspect of the present invention disclosed in this specification more specifically relates to The technical fields of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, imaging devices, and storage devices. , their driving methods, or their manufacturing methods can be cited as examples.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. It refers to a semiconductor element, circuit, or device, etc. Examples include a transistor, a diode, and other semiconductor elements. In another example, a circuit having a semiconductor element is a semiconductor device. As another example, a device including a circuit having a semiconductor element is a semiconductor device. do. [Background technology]

[0004] In recent years, metal oxides that exhibit semiconductor properties have been used in transistors instead of silicon semiconductors. This technology is attracting attention.

[0005] Patent Document 1 describes a transistor using an oxide semiconductor. Oxygen is added to the film in contact with the semiconductor or oxide semiconductor using oxygen plasma or the like, and the film is oxidized. The idea is to improve the characteristics of transistors by supplying oxygen to semiconductors. do.

[0006] In addition, Non-Patent Document 1 states that the absorption observed in the vicinity of g value = 1.93 in the ESR spectrum is The main cause is carriers generated when hydrogen is captured by oxygen vacancies in oxide semiconductors. It has been suggested that this is the case. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-080947 [Non-patent literature]

[0008] [Non-Patent Document 1] Yusuke Nonaka et. al, “Investigation of defects in In-Ga-Zn oxide thin film using electron spin resonance signals”, JOURNAL OF APPLIED PHYSICS, 2014, 115, pp. 163707-1-163707-5 Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to provide a highly reliable semiconductor device. An object of one embodiment of the present invention is to provide a semiconductor device having stable characteristics. .

[0010] Another object of one embodiment of the present invention is to reduce oxygen vacancies in an oxide semiconductor. Another object of one embodiment of the present invention is to reduce the hydrogen concentration in an oxide semiconductor. Another embodiment of the present invention is a transistor including an oxide semiconductor with few oxygen vacancies. Another object of one embodiment of the present invention is to provide an oxide semiconductor having a low hydrogen concentration. Another object of the present invention is to provide a transistor including a conductor. The object of the present invention is to control the fluctuation, variation, or decrease in the threshold voltage of a transistor. Another embodiment of the present invention provides a transistor with a low current when off. Another object of one embodiment of the present invention is to provide a transistor that has a large current when it is turned on. Another object of one embodiment of the present invention is to provide a transistor. One of the objects is to provide a method.

[0011] Another embodiment of the present invention is to provide a method for reducing oxygen vacancies in an oxide semiconductor. Another object of one embodiment of the present invention is to provide a method for reducing the hydrogen concentration in an oxide semiconductor. One of our goals is to provide a method for

[0012] Another object of one embodiment of the present invention is to provide a novel semiconductor device, a novel electronic device, or the like. Another embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device. This is one of the challenges.

[0013] Note that the problems of one embodiment of the present invention are not limited to the above-listed problems. This does not preclude the existence of other problems. The issues not mentioned in this section are issues that are not mentioned in the description of the specification or drawings, etc. These can be derived from the above and can be extracted appropriately from these descriptions. One aspect of the present invention is to solve at least one of the above-listed problems and / or other problems. This is what is decided. [Means for solving the problem]

[0014] In one aspect of the present invention, a first semiconductor is formed on a substrate, and a second semiconductor is formed on the first semiconductor so as to be in contact with the first semiconductor. After forming a second semiconductor, forming a first layer on the second semiconductor, and performing oxygen plasma treatment, removing the first layer to expose at least a portion of the surface of the second semiconductor; A third semiconductor is formed so as to be in contact with the first insulator, and a first insulator is formed on the third semiconductor so as to be in contact with the first insulator. This is a method for manufacturing a semiconductor device in which a first conductor is formed on a first insulator.

[0015] Alternatively, one embodiment of the present invention is a method for forming a first semiconductor over a substrate, and forming a first semiconductor layer on the first semiconductor layer. A second semiconductor is formed so as to contact the upper surface of the second semiconductor. a first layer is formed so as to be in contact with the upper surfaces of the pair of conductors and the upper surface of the second semiconductor; After oxygen plasma treatment, the first layer is removed to expose the surface of the second semiconductor. a third semiconductor is formed in contact with the upper surface of the conductor and the upper surface of the second semiconductor; forming a first insulator on the semiconductor so as to be in contact with the semiconductor; and forming a first conductor on the first insulator. The present invention relates to a method for manufacturing a semiconductor device.

[0016] Alternatively, one embodiment of the present invention is a method for forming a first semiconductor over a substrate, and forming a first semiconductor layer on the first semiconductor layer. A second semiconductor is formed so as to contact the upper surface of the second semiconductor, and a first layer is formed so as to contact the upper surface of the second semiconductor. After the nitrogen plasma treatment, the first layer is removed to expose the surface of the second semiconductor. A pair of conductors is formed so as to contact the upper surface of the semiconductor, and the upper surfaces of the pair of conductors and the second semiconductor A third semiconductor is formed so as to be in contact with the upper surface of the conductor, and a second semiconductor is formed so as to be in contact with the third semiconductor. A method for manufacturing a semiconductor device, comprising forming a first insulator and forming a first conductor on the first insulator. be.

[0017] In the above structure, the first layer has a higher water content than the first semiconductor or the third semiconductor. It is preferable that the material has permeability to oxygen.

[0018] In the above structure, the first layer is made of boron, carbon, fluorine, magnesium, aluminum, or the like. Aluminum, silicon, phosphorus, chlorine, argon, titanium, vanadium, chromium, manganese, Baltic, nickel, copper, zinc, gallium, germanium, yttrium, zirconium, Niobium, molybdenum, ruthenium, indium, tin, lanthanum, neodymium, hafnium It is preferable to have an oxide containing tantalum or tungsten.

[0019] In the above structure, the second semiconductor contains indium, the element M, and zinc, M is aluminum, gallium, yttrium, tin, boron, silicon, titanium, iron, Nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium Preferably, the metal is aluminum, neodymium, hafnium, tantalum, or tungsten.

[0020] Other aspects of the present invention will be described in the following embodiments and is shown in the drawings. [Effects of the Invention]

[0021] According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment, a semiconductor device with stable characteristics can be provided.

[0022] According to one embodiment of the present invention, oxygen vacancies in an oxide semiconductor can be reduced. According to one embodiment of the present invention, the hydrogen concentration in the oxide semiconductor can be reduced. According to one embodiment of the present invention, a transistor including an oxide semiconductor with few oxygen vacancies is provided. According to one embodiment of the present invention, a transistor including an oxide semiconductor with a low hydrogen concentration can be manufactured. According to one embodiment of the present invention, a threshold voltage of a transistor can be set. The present invention also provides a method for controlling fluctuations, variations, or decreases in the voltage. This makes it possible to provide a transistor with a small current when it is off. According to one embodiment, a transistor that conducts a large amount of current can be provided. According to one embodiment of the present invention, a method for manufacturing the transistor can be provided.

[0023] According to another embodiment of the present invention, a method for reducing oxygen vacancies in an oxide semiconductor is provided. According to one embodiment of the present invention, a method for reducing the hydrogen concentration in an oxide semiconductor can be provided. can be provided.

[0024] According to one embodiment of the present invention, a novel semiconductor device, a novel electronic device, or the like can be provided. According to one embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided. Cut.

[0025] The effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are effects that are not mentioned in the description of the specification or drawings, etc. These can be derived from the above and can be extracted appropriately from these descriptions. One aspect of the present invention has at least one of the effects listed above and / or other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. There are also cases where this is not possible. [Brief explanation of the drawings]

[0026] [Figure 1] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 2] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 3] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 4] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 5] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 6] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 7] FIG. 1 is a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 8] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 9] FIG. 1 is a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 10] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 11] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 12] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 13] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 14] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 15] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 16]1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 17] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 18] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 19] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 20] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 21] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 22] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 23] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 24] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 25] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 26] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 27] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 28] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 29] Electron diffraction pattern of CAAC-OS. [Figure 30] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 31] Schematic diagram illustrating the film formation model of CAAC-OS and nc-OS. [Figure 32] A diagram explaining InGaZnO4 crystals and pellets. [Figure 33] Schematic diagram illustrating a film formation model of CAAC-OS. [Figure 34] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 35]FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 36] FIG. 1 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. [Figure 37] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 38] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 39] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 40] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 41] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 42] 1A and 1B are a perspective view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 43] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 44] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 45] 1A to 1C are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 46] 1A and 1B are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 47] FIG. 10 is a perspective view illustrating an electronic device according to one embodiment of the present invention. [Figure 48] FIG. 1 shows spin density evaluated by electron spin resonance. [Figure 49] FIG. 10 is a diagram illustrating the depth profile of hydrogen concentration in a sample in an example. [Figure 50] FIG. 1 shows spin density evaluated by electron spin resonance. [Figure 51] FIG. 10 is a diagram illustrating the depth profile of hydrogen concentration in a sample in an example. [Figure 52] FIG. 10 is a diagram illustrating the depth profile of hydrogen concentration in a sample in an example. [Figure 53] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 54] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 55] 1A and 1B are cross-sectional views showing stacked layers of semiconductors and diagrams showing band structures. DETAILED DESCRIPTION OF THE INVENTION

[0027] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description, and various modifications in form and details can be easily made by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same symbols are used It is used in common among different drawings. When referring to the same thing, the hatch pattern is used in the same way. In some cases, no particular symbol is given.

[0028] In the drawings, the size, thickness of the film (layer), or area is exaggerated for clarity. This may be the case.

[0029] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Almost parallel" means that two straight lines are arranged at an angle of between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0030] Also, a voltage is a voltage between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, voltage can be replaced with potential. do.

[0031] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. It does not indicate the layer order. For example, "first" should not be replaced with "second" or "third" In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers. , the ordinal numbers used to identify an aspect of the present invention may not match.

[0032] Even when written as "semiconductor," if the conductivity is sufficiently low, it may be called an "insulator." In addition, the boundary between "semiconductors" and "insulators" is unclear and cannot be clearly defined. Therefore, the term "semiconductor" as used herein is not necessarily an "insulator" Similarly, the term "insulator" used in this specification can be interpreted as "semiconductor." It can sometimes be rephrased as "body."

[0033] Also, even if a material is written as a "semiconductor," if the material has a sufficiently high conductivity, it may be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is unclear and cannot be clearly defined. Therefore, the term "semiconductor" as used herein is not necessarily a "conductor" Similarly, the term "conductor" used in this specification can be interpreted as "semiconductor." It can sometimes be rephrased as "body."

[0034] The impurities in a semiconductor refer to, for example, anything other than the main component that constitutes the semiconductor. Elements present at concentrations of less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of State) in the conductor and carrier movement The semiconductor may be an oxide semiconductor, and the crystallinity may decrease. In the case of a conductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1, Group elements, Group 14 elements, Group 15 elements, transition metals other than the main component, etc., in particular, , hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen In the case of oxide semiconductors, oxygen vacancies can be created by the inclusion of impurities such as hydrogen. In addition, when the semiconductor is silicon, there are cases where an impurity that changes the properties of the semiconductor is formed. The pure substances include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 1 elements. Group 5 elements, etc.

[0035] In the following embodiments, unless otherwise specified, the insulator is, for example, boron. element, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neodymium Insulators containing one or more of hafnium and tantalum may be used in a single layer or a multilayer. Alternatively, resin may be used as the insulator. For example, polyimide, polyamide, Resin containing acrylic or silicone may be used. By using resin, the upper surface of the insulator In some cases, it may not be necessary to perform a flattening process. Also, resin can form a thick film in a short time. As the insulator, aluminum oxide is preferably used. um, silicon nitride oxide, silicon nitride, gallium oxide, yttrium oxide, zirconium oxide insulators containing tungsten oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used in a single layer or in a laminated layer.

[0036] In the following embodiments, unless otherwise specified, the conductor is, for example, boron. element, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, Cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, Conductors containing one or more of ruthenium, silver, indium, tin, tantalum, or tungsten For example, an alloy film or a compound film may be used. Conductors containing aluminum, conductors containing copper and titanium, conductors containing copper and manganese Conductors containing indium, tin and oxygen, or titanium and nitrogen are used. That's fine.

[0037] In this specification, when it is stated that A has a region of concentration B, for example, If the entire depth direction in a certain region is concentration B, the average depth direction in a certain region of A is If the average value is concentration B, then if the median value in the depth direction in a region of A is concentration B, If the maximum value of concentration B in the depth direction in a region of A is If the minimum value in the direction is concentration B, the convergence value in the depth direction in a region of A is concentration B. This includes cases where the area where a reliable value of A itself can be obtained in measurement is concentration B. .

[0038] In this specification, A represents an area of ​​size B, length B, thickness B, width B or distance B. When describing something as having a certain area of ​​A, for example, the whole of A has size B, length B, thickness B, etc. If B, width B or distance B, the average value in a certain area of ​​A is size B, length B, thickness B If the length B, width B, or distance B is the median value of a region of A, then the median value of A has size B, length B, or If thickness B, width B, or distance B, the maximum value in a certain area of ​​A is size B, length B , thickness B, width B, or distance B, the minimum value of A in a certain area is the size B, length If B, thickness B, width B or distance B, the convergence value in a region of A is magnitude B, length B When the length B, thickness B, width B or distance B is measured, the value of A itself is not certain. This includes cases where the area has size B, length B, thickness B, width B or distance B.

[0039] The words "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be used interchangeably with "conductive It may be possible to change the term to "film." Alternatively, for example, It may be possible to change the term to "insulating layer."

[0040] (Embodiment 1) In this embodiment, a transistor according to one embodiment of the present invention and a semiconductor device including the transistor will be described. The manufacturing method thereof will be described.

[0041] <Transistor structure> FIG. 1A is an example of a top view of a transistor 490. An example of a cross-sectional view corresponding to the line A2 and the dashed line A3-A4 is shown in FIG. In order to facilitate understanding, some insulators and other components are omitted in Figure 1(A).

[0042] The transistor 490 shown in FIG. 1 includes a conductor 413, an insulator 402 on the conductor 413, and , a semiconductor 406a on the insulator 402, a semiconductor 406b on the semiconductor 406a, and a semiconductor 406b on the semiconductor 406a. The conductors 416a and 416b contact the side of the semiconductor 406a and the top and side of the semiconductor 406b. and the conductor 416b, the side surface of the semiconductor 406a, the top surface and side surface of the semiconductor 406b, and the conductor The semiconductor 416a and the conductor 416b are in contact with each other. 406c, an insulator 412 on the semiconductor 406c, and a conductor 404 on the insulator 412. Note that the conductor 413 is a part of the transistor 490. For example, the conductor 413 may be a separate component from the transistor 490. It may also be possible to use the following.

[0043] Here, the transistor 490 is provided on, for example, the substrate 442 as shown in FIG. The substrate 442 may be a semiconductor substrate, an SOI substrate, a glass substrate, a quartz substrate, or a plastic substrate. , metal substrate, stainless steel substrate, substrate with stainless steel foil, Tungsten substrate, substrate with tungsten foil, flexible substrate, lamination film, Paper containing fibrous materials or base film can be used as the semiconductor substrate. For example, elemental semiconductors such as silicon and germanium, or silicon carbide and silicon gel aluminum, gallium arsenide, gallium nitride, indium phosphide, zinc oxide, gallium oxide, etc. The substrate 442 may be made of an amorphous semiconductor or a crystalline semiconductor. The crystalline semiconductor may be a single crystal semiconductor, a polycrystalline semiconductor, or a microcrystalline semiconductor. Crystalline semiconductors, etc.

[0044] Here, an insulator may be provided between the substrate 442 and the conductor 413 .

[0045] Alternatively, the transistor 490 may be provided on a substrate, as will be described later in the description of FIG. 23. The transistor 491, the transistor 492, etc. may be stacked on the stomach.

[0046] The conductor 413 functions as a gate electrode of the transistor. 2 serves as a gate insulator of the transistor 490. and conductor 416b serves as the source and drain electrodes of transistor 490. The insulator 412 also functions as a gate insulator for the transistor 490. The conductor 404 also functions as a gate electrode of the transistor 490. do.

[0047] Note that the conductor 413 and the conductor 404 are both used as gate electrodes of transistors. Although the conductors have the same function, the potentials applied to them may be different. The threshold voltage of the transistor 490 is adjusted by applying a negative or positive gate voltage to the transistor 490. Alternatively, the conductor 413 and the conductor 404 may be arranged in a conductive manner as shown in FIG. The same potential may be applied by electrically connecting them with the body 421 or the like. Since the effective channel width can be increased, the current when the transistor 490 is turned on In addition, the electric field can be guided to a region where it is difficult for the conductor 404 alone to reach. Since the dielectric 413 can cover the subthreshold voltage of the transistor 490, The switching value (also referred to as the S value) of the transistor 490 can be reduced. The conductor 421 can be made smaller by, for example, the conductor 476 described later. Please refer to the descriptions in a etc.

[0048] Alternatively, transistor 490 may not have conductor 413 as shown in FIG. stomach.

[0049] Note that the insulator 402 is preferably an insulator containing excess oxygen.

[0050] For example, an insulator containing excess oxygen can be used as an insulator that releases oxygen upon heat treatment. For example, silicon oxide containing excess oxygen releases oxygen when heated. Therefore, the insulator 402 is silicon oxide, which allows oxygen to move through the film. That is, the insulator 402 may be an insulator having oxygen permeability. For example, The insulator 402 may have higher oxygen permeability than the semiconductor 406a.

[0051] The insulator containing excess oxygen has a function of reducing oxygen vacancies in the semiconductor 406b. Oxygen vacancies in the semiconductor 406b form DOS, which become hole traps, etc. In addition, hydrogen atoms enter the oxygen vacancy sites, generating electrons as carriers. Therefore, by reducing oxygen vacancies in the semiconductor 406b, the transistor 490 This can impart stable electrical properties to the

[0052] Here, the insulator that releases oxygen by heat treatment is analyzed by thermal desorption spectroscopy (TDS). Thermal Desorption Spectroscopy (TDS) analysis at 100°C 1×10 in the range of surface temperature between 700℃ and 100℃ or between 500℃ and 100℃ 18 at oms / cm 3 That's it, 1 x 10 19 atoms / cm 3 or more than 1×10 20 atom s / cm3 It may release more than this amount of oxygen (calculated as the number of oxygen atoms).

[0053] Here, a method for measuring the amount of released oxygen using TDS analysis will be described below.

[0054] The total amount of gas released when the measurement sample is subjected to TDS analysis is calculated by the integral value of the ion intensity of the released gas. By comparison with a standard sample, the total amount of gas released can be calculated.

[0055] For example, the TDS analysis results of a silicon substrate containing a specified density of hydrogen as a standard sample, and From the TDS analysis results of the measurement sample, the amount of oxygen molecules released from the measurement sample (N O2 ) is shown below Here, the gas detected at a mass-to-charge ratio of 32 obtained by TDS analysis can be calculated using the formula: We assume that all of the carbon atoms are derived from oxygen molecules. The mass-to-charge ratio of CH3OH is 32, but It is not considered here as it is unlikely. Also, the mass number of the isotope of the oxygen atom is 17. The existence of oxygen atoms with mass number 18 and oxygen molecules with mass number 18 in nature is also Not considered as the ratio is extremely small.

[0056] N O2 =N H2 / S H2 ×S O2 ×α

[0057] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is the standard This is the integrated value of the ion intensity when the sample is subjected to TDS analysis. Here, the reference value of the standard sample is N H2 / S H2 Let's say S O2 is the integral value of the ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ion intensity in TDS analysis. Details of the above formula For details, see Japanese Patent Application Laid-Open No. 6-275697. A thermal desorption analyzer EMD-WA1000S / W manufactured by Kagaku Co., Ltd. was used as a standard sample. 1×10 16 atoms / cm 2 The measurements were carried out using a silicon substrate containing hydrogen atoms.

[0058] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The atomic ratio can be calculated from the ionization rate of oxygen molecules. Since it includes the ionization rate of the molecules, evaluating the amount of released oxygen molecules can be used to estimate the amount of released oxygen atoms. It is also possible to estimate.

[0059] In addition, N O2 is the amount of released oxygen molecules. The amount of released oxygen atoms is This is twice the amount of offspring released.

[0060] Alternatively, insulators that release oxygen upon heat treatment may contain peroxide radicals. Specifically, the spin density due to peroxide radicals is 5×10 17 spins / cm 3 Insulators containing peroxide radicals have an ESR g value of 2 or more. It may also have an asymmetric signal around .01.

[0061] Alternatively, an insulator containing excess oxygen can be formed by using silicon oxide (SiO X (X>2) Silicon oxide (SiO X (X>2) is the number of silicon atoms It contains more than twice as many oxygen atoms per unit volume as silicon per unit volume. The number of atoms and oxygen atoms was measured by Rutherford backscattering (RBS). The values ​​were measured by backscattering spectrometry.

[0062] The insulator 412 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or oxide. aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide, silicon nitride Silicon or the like may be used, and the layer may be laminated or formed as a single layer.

[0063] The insulator 412 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate (HfAl x O y N z ), high-k materials such as yttrium oxide may also be used. .

[0064] The insulator 412 may be aluminum oxide, magnesium oxide, silicon oxide, or oxide. Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Oxide insulation such as aluminum oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide films, silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, etc. The insulating film can be formed using a nitride insulating film or a film made of a mixture of the above materials.

[0065] In addition, as the insulator 412, similar to the insulator 402, a material having a stoichiometric composition of oxygen is used. It is preferable to use an oxide insulating film containing as much oxygen as possible.

[0066] In addition, when a specific material is used for the gate insulating film, electrons are captured in the gate insulating film under specific conditions. For example, silicon oxide and hafnium oxide can be used to increase the threshold voltage. Like the stacked film of hafnium, a part of the gate insulating film is made of hafnium oxide, aluminum oxide, and oxide. By using a material with many electron capture levels, such as tantalum, and by using it at a higher temperature (the operating temperature of the semiconductor device), Or higher than the storage temperature, or 125°C or higher and 450°C or lower, typically 1 Under the temperature range of 50°C to 300°C, the potential of the gate electrode is set to the potential of the source electrode and drain electrode. By maintaining a higher state for at least one second, typically at least one minute, the gate voltage is released from the semiconductor layer. Electrons move towards the poles, and some of them are captured by the electron capture levels.

[0067] In this way, a transistor that has captured the necessary number of electrons in the electron capture level has a threshold voltage The amount of electrons captured is controlled by controlling the voltage of the gate electrode. This allows the threshold voltage to be controlled. The process for adding the conductive layer may be performed during the manufacturing process of the transistor.

[0068] For example, forming wiring metal that connects to the source electrode or drain electrode of a transistor After the wafer processing, or after the wafer dicing process. It is advisable to carry out this at any stage before shipping from the factory, such as after packaging. It is preferred that the subsequent exposure to temperatures above 125°C is not carried out for more than one hour.

[0069] In addition, nitrogen oxides (NO x , x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), Generally speaking, NO2 or NO forms a level in the insulator 412. The nitroxide is located within the energy gap of the insulator 412 and When the electrons diffuse to the interface between the insulator 412 and the semiconductor 406, the level traps electrons on the insulator 412 side. As a result, the trapped electrons may move to the interface between the insulator 412 and the semiconductor 406. Since it remains in the vicinity, it shifts the threshold voltage of the transistor in the positive direction.

[0070] As the insulator 412, an oxide insulating film having a small amount of nitrogen oxide and a low density of defect states is used. By doing so, it is possible to reduce the shift in the threshold voltage of the transistor, This can reduce fluctuations in the electrical characteristics of the capacitor.

[0071] The heat treatment in the manufacturing process of a transistor is typically performed at a temperature of 300°C or higher but below the substrate distortion point. By heat treatment, the insulator 412 is measured by ESR (electron spin resonance) below 100K. In the obtained spectrum, the first signal, g, having a g value of 2.037 or more and 2.039 or less A second signal with a g value between 2.001 and 2.003, and a g value between 1.964 and 1.9 The third signal below 66 is not observed. The split width of the second signal and the split width of the third signal are The ESR measurement shows that the g value is approximately 5 mT. a signal with a g value between 2.001 and 2.003, and a second signal with a g value between 1.9 The sum of the spin densities of the third signal, which is greater than or equal to 64 and less than or equal to 1.966, is below the detection limit. Typically, it is 1×10 17 spins / cm 3 The ESR measurement temperature is as follows: It should be 100K or less.

[0072] In the ESR spectrum, the first signal with a g value of 2.037 or more and 2.039 or less , the second signal with a g value of 2.001 to 2.003, and the second signal with a g value of 1.964 to 1. The third signal, below 0.966, corresponds to the signal due to nitrogen dioxide. First signal between 2.037 and 2.039, g between 2.001 and 2.003 and the third signal with a g value of 1.964 or more and 1.966 or less. The lower the total density of pins, the lower the nitrogen oxide content in the oxide insulating film. Hereafter, these three signals will be referred to as "NOx-induced signals."

[0073] In addition, oxide insulating films with low nitrogen oxide content and low defect level density are The nitrogen concentration measured by ion mass spectrometry (Ion Mass Spectrometry) 2×10 20 atoms / cm 3 Less than 7 x 10 19 atoms / cm 3 Less than 2 x 10 19 atoms / cm 3 The higher the deposition temperature of the insulator 412, the The nitrogen oxide content of the insulator 412 can be reduced. , 450°C or higher but lower than the substrate strain point, 500°C or higher but lower than the substrate strain point, or 500°C or higher but lower than 55°C A temperature of 0°C or below is preferred.

[0074] As shown in FIG. 1, the side surfaces of the conductor 416a and the conductor 416b are The electric field of the conductor 404 electrically surrounds the semiconductor 406b. (The electric field of the conductor can be used to electrically surround the semiconductor.) This is called the surrounded channel (s-channel) structure. Therefore, a channel may be formed in the entire (bulk) of the semiconductor 406b. In the n-channel structure, a large current can flow between the source and drain of the transistor, and conduction The current (on-state current) can be increased.

[0075] Because of the high on-current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, the semiconductor device having the transistor The device can be a highly integrated, high density semiconductor device. The transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less. Preferably, the transistor has a channel width of 20 nm or less. or 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. It has a region.

[0076] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor through which current flows when the transistor is on). The source (source region or source electrode) in the region where the channel is formed. The distance between the transistor and the drain (drain region or drain electrode) is In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is any one of the values, maximum and minimum, in the region where the channel is formed. The value is the average value.

[0077] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The area where the gate electrode overlaps with the gate electrode (the area where current flows) or the area where the channel is formed. The length of the part where the source and drain face each other is called the length of one transistor. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is any one of the values, maximum and minimum, in the region where the channel is formed. The value is the average value.

[0078] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width shown in the figure becomes larger, and the effect becomes non-negligible. For example, in transistors with a fine, three-dimensional structure, the side surface of the semiconductor In this case, the ratio of the channel region formed in the top view may be increased. The effective channel width of the channel is actually formed rather than the apparent channel width shown. will be larger.

[0079] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width if the channel conditions are not precisely known. .

[0080] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent thickness is the length of the part where the source and drain face each other in the region where the The channel width is referred to as "Surrounded Channel Width (SCW)". In this specification, when simply referred to as the channel width, This may refer to the enclosed channel width or apparent channel width. In the detailed description, when simply referred to as a channel width, it may refer to an effective channel width. In addition, channel length, channel width, effective channel width, apparent channel width, and enclosure The channel width can be determined by acquiring a cross-sectional TEM image and analyzing the image. , values ​​can be determined.

[0081] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0082] Next, the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c will be described.

[0083] The semiconductor 406b is, for example, an oxide semiconductor containing indium. For example, when indium is contained, the carrier mobility (electron mobility) increases. The body 406b preferably contains the element M. The element M is preferably aluminum, gallium, or the like. Other elements that can be used for element M include: Boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, These include lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. However, as the element M, a combination of the above elements may be used. For example, it is an element with a high bond energy with oxygen. The element M is an element having a higher energy than indium. Alternatively, the element M may be, for example, an element having an energy The semiconductor 406b contains zinc, which has the function of widening the gap. It is preferable that the oxide semiconductor contains zinc, and therefore the oxide semiconductor may be easily crystallized.

[0084] However, the semiconductor 406b is not limited to an oxide semiconductor containing indium. 06b does not contain indium, such as zinc tin oxide, gallium tin oxide, etc. Oxide semiconductors containing zinc, oxide semiconductors containing gallium, oxide semiconductors containing tin, etc. It's okay if there is.

[0085] The semiconductor 406b is made of, for example, an oxide with a large energy gap. The energy gap of 6b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2. The voltage is set to 8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0086] For example, the semiconductor 406a and the semiconductor 406c contain oxygen other than the oxygen that constitutes the semiconductor 406b. The semiconductor 406b is an oxide semiconductor composed of one or more of the following elements: The semiconductor 406a and the semiconductor 406b are formed from one or more elements other than oxygen. 6c is formed, the interface between the semiconductor 406a and the semiconductor 406b, and the semiconductor 406 At the interface between the semiconductor 406b and the semiconductor 406c, an interface state is unlikely to be formed.

[0087] The semiconductor 406a, the semiconductor 406b, and the semiconductor 406c contain at least indium. When the semiconductor 406a is an In-M-Zn oxide, the sum of In and M is When the atomic percentage of In is 100, it is preferable that In is less than 50 atomic percent and M is 5. 0 atomic % or more, more preferably In is less than 25 atomic % and M is 7 5 atomic % or more. Also, the semiconductor 406b is an In-M-Zn oxide. When the sum of In and M is 100 atomic %, it is preferable that In is 25 atomic %. mic%, M is less than 75 atomic %, and more preferably In is 34 atomic % % and M is less than 66 atomic %. In the case of M-Zn oxide, when the sum of In and M is 100 atomic %, it is preferable Preferably, In is less than 50 atomic % and M is greater than 50 atomic %. In is less than 25 atomic % and M is greater than 75 atomic %. The semiconductor 406c may be made of the same oxide as the semiconductor 406a.

[0088] The semiconductor 406b has an acid with a larger electron affinity than the semiconductor 406a and the semiconductor 406c. For example, the semiconductor 406b is made of a compound having a higher conductivity than the semiconductor 406a and the semiconductor 406c. The electron affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less. 5 or less, more preferably, an oxide having a larger energy level than the above by 0.15 eV or more and 0.4 eV or less. , electron affinity is the difference in energy between the vacuum level and the bottom of the conduction band.

[0089] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the semiconductor 406c contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and More preferably, it is 90% or more.

[0090] At this time, when an electric field is applied to the gate electrode, the semiconductor 406a, the semiconductor 406b, and the semiconductor A channel is formed in the semiconductor 406b having a large electron affinity among the semiconductors 406c.

[0091] Here, between the semiconductor 406a and the semiconductor 406b, In addition, a mixed region of semiconductor 406b and semiconductor 406c may be formed between semiconductor 406b and semiconductor 406c. , a mixed region of semiconductor 406b and semiconductor 406c may be present. Therefore, the level density of the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c is reduced. In this laminate, the energy changes continuously near each interface (continuous junction). 55A shows a band structure of the semiconductor 406a and the semiconductor 406b. and semiconductor 406c are stacked in this order. The energy (Ec) of the conduction band minimum corresponds to the dashed line P1-P2 in A, and is the energy of the semiconductor 4 55(C) shows the case where the electron affinity of the semiconductor 406c is larger than that of the semiconductor 406a. This shows the case where the electron affinity of the semiconductor 406c is smaller than that of the conductor 406a.

[0092] At this time, the electrons are not in the semiconductor 406a and the semiconductor 406c, but in the semiconductor 406 As described above, the electrons move mainly through the interface between the semiconductor 406a and the semiconductor 406b. , and the interface state density at the interface between the semiconductor 406b and the semiconductor 406c. By lowering the temperature, the movement of electrons in the semiconductor 406b is less hindered, and the The on-current of the transistor 490 can be increased.

[0093] The on-current of the transistor 490 is increased to the extent that the factors that hinder the movement of electrons are reduced. For example, if there is no factor that inhibits the movement of electrons, electrons can move efficiently. It is estimated that the electron movement is hindered when, for example, the physical unevenness of the channel formation region is large. This can also occur in

[0094] Therefore, in order to increase the on-current of the transistor 490, for example, the semiconductor 40 6b (the surface to be formed, in this case, the semiconductor 406a) in a range of 1 μm×1 μm Root Mean Square (RMS) roughness is less than 1 nm. less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably 0. The average surface roughness (Ra) in the area of ​​1 μm x 1 μm should be less than 4 nm. ) is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, More preferably, it is less than 0.4 nm. The difference in surface area (also called PV) is less than 10 nm, preferably less than 9 nm, and more preferably less than 8 nm. The RMS roughness, Ra and PV are SPA-50 scanning probe microscope system manufactured by SII NanoTechnology Inc. 0 etc. can be used for measurement.

[0095] Alternatively, for example, when the defect level density in the region where the channel is formed is high, the electron Movement is hindered.

[0096] Here, the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c may be made of an insulator or a conductor. The transistor 490 may be formed of either the semiconductor 406a or the semiconductor 406c. It may be possible to have neither or both.

[0097] The impurity concentration in the semiconductor 406 can be measured by SIMS.

[0098] For example, consider a case where the semiconductor 406b has oxygen vacancies. Hydrogen enters the oxygen vacancies. In this case, electrons, which are carriers, are generated. Here, oxygen vacancies are represented as Vo. The hydrogen atoms that enter the oxygen vacancies are sometimes expressed as VoH. Also, when some of the hydrogen atoms are replaced by metal atoms, By bonding with oxygen, electrons, which are carriers, may be generated. A transistor using an oxide semiconductor containing hydrogen tends to be normally on. In addition, hydrogen contained in the semiconductor 406b reacts with oxygen that bonds with metal atoms to form water. At the same time, oxygen vacancies are formed in the lattice from which oxygen is desorbed (or in the part from which oxygen is desorbed). There is.

[0099] Therefore, the semiconductor 406b must have as little hydrogen as possible, along with oxygen vacancies. Specifically, in the semiconductor 406b, the hydrogen concentration obtained by SIMS analysis is degrees, 5 x 10 19 atoms / cm 3 or less, or 1×10 19 atoms / cm 3 Below Below, or 5x10 18atoms / cm 3 or less, or 1×10 18 atoms / cm 3 or less, or 5 x 10 17 atoms / cm 3 or less, or 1×10 16 atoms / cm 3 As a result, the transistor 490 is electrically connected to the positive threshold voltage. It has a characteristic (also called a normally-off characteristic).

[0100] The semiconductor 406b contains silicon and carbon, which are elements of Group 14. As a result, oxygen vacancies increase in the semiconductor 406b, and an n-type region is formed. , the concentration of silicon and carbon in the semiconductor 406b (obtained by secondary ion mass spectrometry) concentration) to 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 As a result, the transistor 490 is electrically connected to the positive threshold voltage. It has a characteristic (also called a normally-off characteristic).

[0101] In addition, in the semiconductor 406b, alkali metals or or alkaline earth metal concentration is 1×10 18 atoms / cm 3 Below, preferably 2x 10 16 atoms / cm 3 The alkali metals and alkaline earth metals are oxidized When they bond with semiconductors, they can generate carriers, which increases the off-state current of the transistor. For this reason, the alkali metal or alkaline earth metal of the semiconductor 406b As a result, transistor 490 has a threshold voltage of 100 volts. It has a low electrical characteristic (also called a normally-off characteristic).

[0102] Furthermore, if the semiconductor 406b contains nitrogen, electrons that act as carriers are generated, and the carriers The density increases and an n-type region is formed. As a result, the oxide semiconductor containing nitrogen Therefore, the transistor using the oxide semiconductor film tends to be normally on. In the solid film, it is preferable that nitrogen is reduced as much as possible. For example, The nitrogen concentration obtained by quantitative analysis is 5 × 10 18 atoms / cm 3 The following can be done preferable.

[0103] By reducing impurities in the semiconductor 406b, the carrier density of the oxide semiconductor film is reduced. Therefore, the semiconductor 406b has a carrier density of 1×10 17 pieces / cm 3 Below Below, preferably 1 x 10 15 pieces / cm 3 or less, more preferably 1 × 10 13 pieces / cm 3 Less than 1×10, more preferably 11 pieces / cm 3 It is preferable that:

[0104] The semiconductor 406b is an oxide semiconductor film with a low impurity concentration and a low density of defect states. By doing so, a transistor with even better electrical characteristics can be manufactured. The term "high purity intrinsic or intrinsic" refers to a material with a low impurity concentration and a low defect level density (low oxygen vacancy). The term "high-purity intrinsic" refers to a substantially high-purity intrinsic oxide semiconductor. In this case, since there are fewer carrier generation sources, it may be possible to lower the carrier density. Therefore, the threshold voltage of a transistor whose channel region is formed in the oxide semiconductor film is It is easy for the electrical characteristics to become positive (also called normally-off characteristics). Since a pure or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, The level density may also be lower. The off-state current of the nitride semiconductor film is extremely small, and the voltage between the source and drain electrodes (drain When the on-state voltage is in the range of 1V to 10V, the off-state current is Below the detection limit, i.e., 1×10 -13 A characteristic of less than A can be obtained. A transistor in which a channel region is formed in the oxide semiconductor film has small fluctuations in electrical characteristics. This may result in a highly reliable transistor.

[0105] When the transistor 490 has an s-channel structure, the semiconductor 406b Therefore, the thicker the semiconductor 406b, the larger the channel region. That is, the thicker the semiconductor 406b, the higher the on-current of the transistor 490. For example, it can be 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more. A region having a thickness of 100 nm or more, more preferably 60 nm or more, and even more preferably 100 nm or more However, productivity of the semiconductor device may be reduced. Therefore, for example, it is 300 nm or less, preferably 200 nm or less, and more preferably 150 The semiconductor 406b may have a region with a thickness of 1 nm or less.

[0106] In order to increase the on-current of the transistor 490, the thickness of the semiconductor 406c is small. For example, it is less than 10 nm, preferably 5 nm or less, and more preferably 3 On the other hand, the semiconductor 406c may be a channel semiconductor 406c having a region of 100 nm or less. The semiconductor 406b on which the insulator is formed is charged with elements other than oxygen (hydrogen, silicon) that constitute the adjacent insulator. Therefore, the semiconductor 406c It is preferable that the thickness of the film is 0.3 nm or more, preferably 1 nm or more. The semiconductor 406c may have a thickness of 1 nm or more, more preferably 2 nm or more. In addition, the semiconductor 406c suppresses outward diffusion of oxygen released from the insulator 402, etc. Therefore, it is preferable that the material has oxygen blocking properties.

[0107] In order to increase reliability, the semiconductor 406a is thick and the semiconductor 406c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 40 nm or more. The semiconductor 406a may have a thickness of 60 nm or more, more preferably 60 nm or more. By increasing the thickness of the semiconductor 406a, the interface between the adjacent insulator and the semiconductor 406a The distance from the semiconductor 406b where the channel is formed can be increased. Therefore, for example, the thickness is set to 200 nm or less, preferably 120 If the semiconductor 406a has a region with a thickness of 80 nm or less, more preferably 80 nm or less, good.

[0108] For example, secondary ion mass spectroscopy (SIMS) is performed between the semiconductor 406b and the semiconductor 406a. : Secondary Ion Mass Spectrometry) 10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, More preferably 2×10 18 atoms / cm 3 having a region with a silicon concentration of less than In addition, SIMS showed that the thickness of the semiconductor 406b and the semiconductor 406c was 1×10 19 a toms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, even more preferred Kuha 2 x 10 18 atoms / cm 3 The silicon concentration is less than 1000 .mu.m.

[0109] In addition, in order to reduce the hydrogen concentration in the semiconductor 406b, the semiconductor 406a and the semiconductor 406b are It is preferable to reduce the hydrogen concentration of the semiconductor 406a and the semiconductor 406c. In S, 2 x 10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Less than 1×10, more preferably 19 atoms / cm 3 More preferably, 5×10 18 atoms / cm 3 The semiconductor 40 has a region where the hydrogen concentration is as follows: In order to reduce the nitrogen concentration in the semiconductor 406b, the nitrogen concentration in the semiconductor 406a and the semiconductor 406c is reduced. The semiconductor 406a and the semiconductor 406c are preferably 5×1 0 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 More information below: Preferably 1 x 10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 ato ms / cm 3 The nitrogen concentration ranges as follows:

[0110] The three-layer structure described above is an example. For example, a two-layer structure without semiconductor 406a or semiconductor 406c Alternatively, the semiconductor 406 may be formed on or under the semiconductor 406a, or on or under the semiconductor 406. c) are illustrated as semiconductor 406a, semiconductor 406b, and semiconductor 406c. Alternatively, a four-layer structure may be formed by using one of the semiconductors 406a and 406b. , two or more locations below the semiconductor 406a, above the semiconductor 406c, and below the semiconductor 406c In addition, any of the semiconductors exemplified as semiconductor 406a, semiconductor 406b, and semiconductor 406c Alternatively, an n-layer structure (n is an integer of 5 or more) having one of these layers may be used.

[0111] At least a portion (or all) of the conductor 416a (or / and the conductor 416b) The semiconductor 406b may have a surface, a side surface, a top surface, or / and a bottom surface. are also provided in some (or all) areas.

[0112] Alternatively, at least a portion (or both) of the conductor 416a (or / and the conductor 416b) (all of these) refer to the surface, side, top, and / or bottom surfaces of a semiconductor, such as semiconductor 406b. Or, the conductor 416a (or / and and conductor 416b) is at least partially (or entirely) a semiconductor such as semiconductor 406b. It is in contact with at least part (or all) of the body.

[0113] Alternatively, at least a portion (or both) of the conductor 416a (or / and the conductor 416b) (all of these) refer to the surface, side, top, and / or bottom surfaces of a semiconductor, such as semiconductor 406b. or the conductor 416a is electrically connected to at least a part (or all) of the conductor 416a. At least a portion (or all) of the semiconductor 406 (or / and the conductor 416b) b) is electrically connected to at least a part (or all) of the semiconductor.

[0114] Alternatively, at least a portion (or both) of the conductor 416a (or / and the conductor 416b) (all of these) refer to the surface, side, top, and / or bottom surfaces of a semiconductor, such as semiconductor 406b. At least a part (or all) of the conductors 416a ( and / or conductor 416b), at least a portion (or all) of which is semiconductor 406b. The semiconductor device is disposed adjacent to at least a portion (or all) of the semiconductor.

[0115] Alternatively, at least a portion (or both) of the conductor 416a (or / and the conductor 416b) (all of these) refer to the surface, side, top, and / or bottom surfaces of a semiconductor, such as semiconductor 406b. At least a part (or all) of the conductor 416a (or conductor 416b) is disposed on the side of the conductor 416a. At least a portion (or all) of the conductive material 416b is a semiconductor 406b, etc. The semiconductor is disposed on at least a portion (or all) of the lateral side of the semiconductor.

[0116] Alternatively, at least a portion (or both) of the conductor 416a (or / and the conductor 416b) (all of these) refer to the surface, side, top, and / or bottom surfaces of a semiconductor, such as semiconductor 406b. Alternatively, the conductor 416a ( and / or conductor 416b), at least a portion (or all) of which is semiconductor 406b. The semiconductor device is disposed diagonally above at least a part (or all) of the semiconductor.

[0117] Alternatively, at least a portion (or both) of the conductor 416a (or / and the conductor 416b) (all of these) refer to the surface, side, top, and / or bottom surfaces of a semiconductor, such as semiconductor 406b. Alternatively, the conductive material 416a (or the conductive material 416b) is disposed on at least a part (or all) of the conductive material 416a. At least a portion (or all) of the conductive material 416b is a semiconductor 406b, etc. The semiconductor layer is disposed on at least a portion (or all) of the semiconductor.

[0118] Here, transistor 490 may have insulator 408 and insulator 418 thereon. The details of the insulators 408 and 418 will be described later in the structure of the semiconductor device. I will explain.

[0119] In addition, an oxide semiconductor that can be used for the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c The structure will be explained in the embodiment described later.

[0120] <Modifications of Transistor Structure> Next, as a modification of the transistor 490 in FIG. 1, a transistor 490 shown in FIG. 2 will be described. and explain.

[0121] 2A is an example of a top view of the transistor 490. An example of a cross-sectional view corresponding to the dashed line E3-E4 is shown in FIG. In 2(A), some insulators and other parts are omitted to facilitate understanding.

[0122] In FIG. 1, the conductor 416a and the conductor 416b function as a source electrode and a drain electrode. 16b contacts the upper and side surfaces of the semiconductor 406b and the upper surface of the insulator 402. However, the structure of a transistor according to one embodiment of the present invention is not limited to this. As shown in FIG. 1, the conductor 416a and the conductor 416b are in contact only with the upper surface of the semiconductor 406b. It is acceptable for the structure to be

[0123] In the transistor shown in FIG. 2, the conductor 416a and the conductor 416b are Therefore, the conductor 404 having the function of a gate electrode does not contact the side of the semiconductor. An electric field applied to the side of the conductor 406b is generated by the conductor 416a and the conductor 416b. The conductor 416a and the conductor 416b are made of insulating material. Therefore, the excess oxygen (oxygen) released from the insulator 402 is not introduced. The insulating material 416a and the insulating material 416b are not consumed to oxidize the conductive material 416a and the conductive material 416b. Excess oxygen (oxygen) released from the body 402 is used to reduce oxygen vacancies in the semiconductor 406b. That is, the transistor having the structure shown in FIG. High on-state current, high field-effect mobility, low subthreshold swing, high reliability It is a transistor with excellent electrical characteristics.

[0124] In addition, in FIG. 1, the semiconductor 406c and the insulator 412 are provided over the entire surface in the transistor. 3, the semiconductor 406c and the insulator 412, and the conductor 404 However, either end may have a shape that does not protrude (stick out). 3A is an example of a top view of a transistor 490. An example of a cross-sectional view corresponding to the chain line A3-A4 is shown in FIG. 3(B). To simplify the solution, some parts such as insulators are omitted.

[0125] 4A is an example of a top view of a transistor 490. An example of a cross-sectional view corresponding to the line B1-B2 and the dashed line B3-B4 is shown in FIG. In FIG. 4A, some insulators and the like are omitted for ease of understanding.

[0126] 5A is an example of a top view of the transistor 490. An example of a cross-sectional view corresponding to the line C1-C2 and the dashed line C3-C4 is shown in FIG. In FIG. 5(A), some insulators and the like are omitted for ease of understanding.

[0127] The semiconductor 406c, the insulator 412, and the conductor 404 are shown in the top view of FIG. In this way, the semiconductor 406c covers the channel formation region of the transistor and the surrounding region. The insulator 412 is provided so as to cover the semiconductor 406c. In the cross-sectional view of FIG. 4B, the semiconductor 406c is a conductor. The shape has an area where the end protrudes (pushes out) from 404. Alternatively, as shown in FIG. As shown in the top view of FIG. 1, the semiconductor 406c and the insulator 412 form the channel shape of the transistor. It is also acceptable to provide the insulating film so as to cover the surrounding area from the forming area. In the plan view, the semiconductor 406c and the insulator 412 have their ends protruding (approaching) beyond the conductor 404. The shape becomes (pull out).

[0128] When the transistor has the structure shown in FIG. 1, FIG. 4, or FIG. 5, the semiconductor 406c This may reduce leakage current through the surface, the surface of the insulator 412, etc. That is, the off-state current of the transistor can be further reduced. In addition, when etching the semiconductor 406c, the conductor 404 does not need to be used as a mask. Therefore, the electric conductor 404 is not exposed to the plasma. Electrostatic breakdown of the capacitor is unlikely to occur, and semiconductor devices can be produced with a high yield. As the degree of freedom in designing semiconductor devices increases, LSIs (Large Scale Integrated Circuits) with complex structures are becoming increasingly common. cale Integration) and VLSI (Very Large Scale) It is suitable for integrated circuits such as MOS transistors.

[0129] 6A is an example of a top view of the transistor 490. An example of a cross-sectional view corresponding to the line D1-D2 and the dashed line D3-D4 is shown in FIG. In FIG. 6(A), some insulators and the like are omitted for ease of understanding.

[0130] 1, 2, and the like, the conductors 416a and 416b functioning as the source and drain electrodes. A structure having a region where the conductor 416b overlaps with the conductor 404 that functions as a gate electrode. However, the structure of a transistor according to one embodiment of the present invention is not limited to this. As shown in FIG. 6, the area where the conductor 416a and the conductor 416b overlap with the conductor 404 is Such a structure can reduce the parasitic capacitance. Therefore, it has good switching characteristics and low noise. This results in a high-speed transistor.

[0131] In addition, since the conductors 416a and 416b do not overlap with the conductor 404, This may increase the resistance between the conductor 416a and the conductor 416b. Since the on-current of the transistor may become small, it is preferable to make the resistance as low as possible. For example, the distance between the conductor 416a (conductor 416b) and the conductor 404 is preferably small. For example, the distance between the conductor 416a (conductor 416b) and the conductor 404 is set to 0. μm or more and 1 μm or less, preferably 0 μm or more and 0.5 μm or less, and more preferably 0 μm or more and 1 μm or less. The thickness may be set to at most 0.2 μm, more preferably at least 0 μm and at most 0.1 μm.

[0132] Alternatively, the semiconductor 406 between the conductor 416a (conductor 416b) and the conductor 404 b and / or a low resistance region 423a (low resistance region 423b) is provided in the semiconductor 406a. The low resistance region 423a and the low resistance region 423b may be formed by, for example, the semiconductor 406 b and / or has regions with a higher carrier density than other regions of the semiconductor 406a. Alternatively, the low resistance region 423a and the low resistance region 423b may be formed by the semiconductor 406b and / or and a region having a higher impurity concentration than the other regions of the semiconductor 406a. The region 423a and the low resistance region 423b are formed by the semiconductor 406b and / or the semiconductor 406a. The low resistance region 423a and the low resistance region 423b have a higher carrier mobility than the other regions. The resistive region 423b is formed by masking, for example, the conductor 404, the conductor 416a, the conductor 416b, etc. The semiconductor 406b and / or the semiconductor 406a are doped with impurities to form the semiconductor 406b. That's fine.

[0133] The distance between the conductor 416a (conductor 416b) and the conductor 404 is reduced, and The semiconductor 406b or / and the semiconductor 406b between the conductor 416a (conductor 416b) and the conductor 404 In addition, a low resistance region 423a (low resistance region 423b) may be provided in the semiconductor 406a. .

[0134] Alternatively, for example, the transistor 490 may have a low resistance region 423 as shown in FIG. The low resistance region 423a and the low resistance region 423b may not be provided. The absence of 423b may reduce the on-state current of transistor 490. 6B, the transistor 490 is less affected by the short channel effect. The regions corresponding to the low resistance regions 423a and 423b (conductors 416a (conductive The region between the conductive body 416b and the conductive body 404 is defined as the Loff1 region and the Loff2 region, respectively. For example, the length of the Loff1 and Loff2 regions is 50 nm. When the distance is shortened to 20 nm or less or 10 nm or less, the low resistance region 423a and the low resistance region 423b are Even without the resistor region 423b, the on-current of the transistor 490 is hardly reduced. It is preferable that the Loff1 region and the Loff2 region have different sizes. It's okay.

[0135] Alternatively, for example, the transistor 490 may be formed in the Loff1 region as shown in FIG. It is possible to have only the Loff2 region and not have the Loff2 region. The transistor 490 is less susceptible to the short channel effect while minimizing the decrease in the on-current. The area where the conductor 416b and the conductor 404 overlap is called the Lov area. For example, the length of the Lov region can be set to 50 nm or less, 20 nm or less, or 10 nm or less. When the parasitic capacitance is reduced to 0.5 V, the switching characteristics of transistor 490 are hardly affected. This is preferable because it does not cause any problems.

[0136] Alternatively, for example, the transistor 490 may be configured such that the conductor 404 is a transistor In this case, for example, the low resistance region 423a and the low The resistance region 423b may have a shape with a gradient in the depth direction. In addition, in other drawings, the conductor 404 may have a tapered shape. stomach.

[0137] 8A is an example of a top view of the transistor 490. An example of a cross-sectional view corresponding to the line F1-F2 and the dashed line F3-F4 is shown in FIG. In FIG. 8(A), some insulators and the like are omitted for ease of understanding.

[0138] Transistor 490 has conductor 416a and conductor 416b as shown in FIG. The conductor 426a and the conductor 426b are in contact with the semiconductor 406b. In this case, at least the conductive layer of the semiconductor 406b and / or the semiconductor 406a may be The low resistance region 423a (low resistance region 423b) is formed in the region in contact with the conductor 426a and the conductor 426b. It is preferable to provide the low resistance region 423a and the low resistance region 423b, for example. The conductor 404 or the like is used as a mask, and impurities are introduced into the semiconductor 406b and / or the semiconductor 406a. The conductors 426a and 426b may be formed by adding a semiconductor. The hole (through hole) or the recess (non-through hole) of the body 406b is provided. The conductor 426a and the conductor 426b may be formed in the holes or depressions of the semiconductor 406b. By providing the conductor 426a and the conductor 426b in the semiconductor 406b, the conductor 426a and the conductor 426b are in contact with each other. Since the area is large, the influence of contact resistance can be reduced. The on-state current can be increased.

[0139] Alternatively, for example, the transistor 490 may have a low resistance region 423 as shown in FIG. The low resistance region 423a and the low resistance region 423b may not be provided. The absence of 423b may reduce the on-state current of transistor 490. This results in a transistor 490 that is less affected by the short channel effect. The region between the conductor 426b and the conductor 404 is called the Loff region. When the length of the region is shortened to 50 nm or less, 20 nm or less, or 10 nm or less, the low resistance region Even if the transistor 490 does not have the low-resistance region 423a and the low-resistance region 423b, the on-current of the transistor 490 There may be little or no decrease in

[0140] Alternatively, for example, the transistor 490 may be configured such that the conductor 404 is a transistor In this case, for example, the low resistance region 423a and the low The resistance region 423b may have a shape that has a gradient in the depth direction.

[0141] 10A and 10B are a top view and a cross-sectional view of a transistor 490. 10(A) is a top view, and FIG. 10(B) is a diagram showing the structure of the dashed line G1-G1 shown in FIG. 10(A). 2 and a cross-sectional view corresponding to the dashed line G3-G4. In the drawings, some elements are omitted for clarity of illustration.

[0142] The transistor 490 shown in FIGS. 10A and 10B is a conductor on a substrate 442. 413, an insulator 402 having a protrusion on the substrate 442 and on the conductor 413, and an insulator 4 The semiconductor 406a on the protruding portion of the semiconductor 406a, the semiconductor 406b on the semiconductor 406a, and the semiconductor 406 The semiconductor 406c on the semiconductor 406b is in contact with the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c. , spaced apart conductors 416a and 416b and on semiconductor 406c, The insulator 412 on the conductor 416a and the conductor 416b, and the conductor 416 on the insulator 412 04, on the conductor 416a, on the conductor 416b, on the insulator 412, and on the conductor 404 It has an insulator 408 and an insulator 418 on the insulator 408 .

[0143] In addition, the insulator 412 is in contact with at least the side surface of the semiconductor 406b in the G3-G4 cross section. In addition, the conductor 404 is in contact with the insulator 412 at least in the G3-G4 cross section. The conductor 413 faces at least the top and side surfaces of the semiconductor 406b. The insulator 402 faces the bottom surface of the semiconductor 406b via the protrusion. The semiconductor 406c may not be included. The insulator 408 may not be included. The insulator 418 may be omitted.

[0144] Therefore, the transistor 490 shown in FIG. 10 is similar to the transistor 490 shown in FIG. Only a part of the structure is different. Specifically, the semiconductor of the transistor 490 shown in FIG. 406a, the semiconductor 406b, and the semiconductor 406c, and the transistor 4 shown in FIG. 90, the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c are different only in structure. Therefore, the transistor shown in FIG. 10 is the same as the transistor shown in FIG. can be referred to as appropriate.

[0145] FIG. 11A is an example of a top view of the transistor 490. An example of a cross-sectional view corresponding to the dashed dotted line H1-H2 and the dashed dotted line H3-H4 is shown in FIG. 11(B). In order to make it easier to understand, some parts such as insulators are omitted in Figure 11(A). .

[0146] Note that in the top view shown in FIG. 10A, the insulator 412 has the same shape as the conductor 404. However, the structure of a transistor according to one embodiment of the present invention is not limited to this example. For example, as shown in FIGS. 11(A) and 11(B), the insulator 412 is disposed on the insulator 402 and the semiconductor It may be disposed on conductor 406c, on conductor 416a, and on conductor 416b.

[0147] <Transistor manufacturing method 1> Next, an example of a manufacturing method of the transistor 490 shown in FIG. 1 will be described with reference to FIGS. 12 to 15. and explain.

[0148] First, a substrate 442 is prepared. An insulator may be formed on the substrate 442.

[0149] Next, a conductor that will become the conductor 413 is formed. The conductor that will become the conductor 413 is formed by sputtering. The film may be formed by a method such as a ring method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0150] Next, a part of the conductor that will become the conductor 413 is etched to form the conductor 413.

[0151] Next, the insulator 402 is formed. The insulator 402 is formed by a method such as sputtering, CVD, or MB. The insulator 4 may be formed by the PLD method, the ALD method, or the like. 02 will be described when the insulator 40 is planarized from the top surface by a CMP method or the like. By planarizing the upper surface of the transistor 490, subsequent processes become easier and the yield of the transistor 490 is increased. For example, the RMS roughness of the insulator 402 can be increased to 1 nm by the CMP method. The thickness is set to 0.5 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. Ra in the range of 1 μm×1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably or less than 0.5 nm, more preferably less than 0.4 nm. PV in the range of less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm However, the thickness of the transistor 4 according to one embodiment of the present invention is preferably less than 7 nm. 90 is not limited to the case where the top surface of the insulator 402 is flattened.

[0152] The insulator 402 may be formed to contain excess oxygen. Oxygen may be added after the film formation. The addition of oxygen may be performed by, for example, ion implantation using an accelerated voltage. The voltage is set to 2 kV or more and 100 kV or less, and the dose is set to 5 × 10 14 ions / cm 2 5x or more 10 16 ions / cm 2 This can be done as follows.

[0153] When the insulator 402 is made of a laminated film, each film is formed as described above. For example, the first layer may be formed by a CVD method, and the second layer may be formed by a different deposition method. The second layer may be formed by the ALD method. Alternatively, the first layer may be formed by the sputtering method, and the second layer may be formed by the ALD method. The film may be formed by ALD. This allows each layer of film to have different functions and properties. By doing so, it is possible to form a more suitable film as a whole laminated film.

[0154] That is, the nth layer (n is a natural number) is formed by sputtering, CVD, MBE or The film is formed by at least one of the PLD method, ALD method, etc., and the n+1th layer film is formed by At least one of the following methods: sputtering, CVD, MBE, PLD, ALD, etc. The film is formed by one method. Note that the film formation method for the nth layer and the n+1th layer may be the same. The film forming method may be the same for the nth layer and the n+2th layer. Alternatively, the deposition method may be the same for all the films.

[0155] Next, the semiconductor 436a that will become the semiconductor 406a and the semiconductor 436b that will become the semiconductor 406b are 6b are deposited in this order (see FIG. 12(A)). The semiconductor that becomes the conductor 406b is formed by a sputtering method, a CVD method, an MBE method, or a PLD method. The film may be formed using an ALD method or the like.

[0156] The semiconductor 436a and the semiconductor 436b are made of an In-Ga-Zn oxide layer. When forming a film by the CVD method, trimethylindium and trimethylgallium are used as raw material gases. The combination of source gases is not limited to the above. In place of trimethylindium, triethylindium or the like may be used. Triethylgallium may be used instead of trimethylgallium. Diethyl zinc or the like may be used in place of lead.

[0157] Next, first heat treatment is preferably performed. The excess oxygen contained in the semiconductor 406 moves to the semiconductor 406b through the semiconductor 406a. In this case, the semiconductor 406a is preferably a semiconductor having a low oxygen content. It is preferable that the layer is permeable (a layer that allows oxygen to pass through or permeate).

[0158] Oxygen is released from the insulator 402 by heat treatment or the like and is taken into the semiconductor 406a. The oxygen may be present in a free state between atoms in the semiconductor 406a or in a state where oxygen is present in a free state. The lower the density of the semiconductor 406a, the more gaps there are between the atoms. For example, the semiconductor 406a has a layered crystal structure. However, if oxygen migration across the layer is difficult, the semiconductor 406a will have a moderate crystallinity. A lower layer is preferred.

[0159] The first heat treatment is carried out at a temperature of 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower. The first heat treatment may be performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at a concentration of 10 ppm or more. The first heat treatment is carried out in an atmosphere containing 1% or more or 10% or more of the above. Alternatively, the first heat treatment may be performed in an inert gas atmosphere, followed by desorbing the oxygen. To compensate for the oxygen, the gas is heated in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. Heat treatment may be performed. The first heat treatment It is possible to increase the crystallinity of b and remove impurities such as hydrogen and water.

[0160] Next, a mask is formed, and the semiconductor 436a and the semiconductor 436b are etched using the mask. The semiconductor 406a and the semiconductor 406b are formed by etching (see FIG. 12B). A photoresist can be used as the mask. A specific example of using a hard mask will be described later in the description of FIG.

[0161] Next, a conductor 416 is formed. The conductor 416 can be formed by a sputtering method, a CVD method, or an MB method. The film may be formed by the E method, PLD method, ALD method or the like.

[0162] The conductor 416a and the conductor 416b are formed by depositing the conductor 416. Therefore, when the conductor 416 is formed, the semiconductor It is preferable to use a deposition method that does not damage the conductive material 406b. It is preferable to use the MCVD method or the like for the film.

[0163] When the conductor 416 is made of a laminated film, each film is formed by a sputtering method. , CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc.), MBE The film may be formed by a different film formation method such as a PLD method, an ALD method, etc. For example, the first layer may be formed by MOCVD and the second layer may be formed by sputtering. Alternatively, the first layer may be formed by the ALD method and the second layer may be formed by the MOCVD method. Alternatively, the first layer may be formed by the ALD method and the second layer may be formed by the sputtering method. The first layer is deposited by the ALD method, the second layer by the sputtering method, and the third layer by the ALD method. In this way, by using different film forming methods, the films of each layer can be formed. By stacking these films, different functions and properties can be given to the As a result, a more suitable film can be formed as a whole laminated film.

[0164] That is, when the conductor 416 is made of a laminated film, for example, the n-th layer is formed by sputtering. Ring method, CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc.) , MBE method, PLD method, ALD method, etc., and the n+1 layer The eye membrane is made by sputtering, CVD (plasma CVD, thermal CVD, MCVD, At least one method selected from the group consisting of MOCVD, MBE, PLD, and ALD. The film formation method may be different between the nth layer and the n+1th layer (n is a number that is determined automatically). The film forming method may be the same for the nth layer and the n+2th layer. The film formation method may be the same for all the films.

[0165] In addition, the conductor 416 or at least one film of the laminated film of the conductor 416 and the semiconductor The semiconductor that becomes the body 406a and the semiconductor that becomes the semiconductor 406b are formed using the same film formation method. For example, the ALD method may be used for both. As a result, it is possible to prevent the inclusion of impurities.

[0166] In addition, the conductor 416 or at least one film of the laminated film of the conductor 416 and the semiconductor The semiconductor 406a or the semiconductor 406b is an insulator 402, or At least one of the stacked films of the insulator 402 may be formed using the same film formation method. For example, a sputtering method may be used for all of these. This allows the film to be formed without being exposed to the atmosphere. As a result, it is possible to prevent the inclusion of impurities. The manufacturing method of the semiconductor device is not limited to these.

[0167] Next, a mask is formed, and the mask is used to form the conductors 416a and 416b. The conductor is etched to form the conductor 416a and the conductor 416b (FIG. 13(A)). reference.).

[0168] Next, a semiconductor film that will become the semiconductor 406c is formed (see FIG. 13(B)). The semiconductors that are used for c are produced by methods such as sputtering, CVD, MBE, PLD, and ALD. The film may be formed using a material such as a metal.

[0169] The semiconductor 406c is an In-Ga-Zn oxide layer grown by MOCVD. When forming a film by this method, trimethylindium, trimethylgallium and The combination of raw material gases is not limited to the above, and may be any combination. Triethylindium or the like may be used in place of trimethylindium. Triethylgallium may be used instead of zinc. Alternatively, diethyl zinc or the like may be used.

[0170] Next, a second heat treatment may be performed. A semiconductor having higher oxygen permeability than the semiconductor 406c is selected. As the semiconductor, a semiconductor having lower oxygen permeability than the semiconductor 406a is selected. Then, a semiconductor having a function of transmitting oxygen is selected as the semiconductor 406a. A semiconductor having the function of blocking oxygen is selected as the semiconductor that will become the body 406c. In this case, by performing second heat treatment, the semiconductor 406a contained in the insulator 402 is The excess oxygen migrates to semiconductor 406b, which becomes semiconductor 406c. Because the body is covered, the outward diffusion of excess oxygen is difficult. By performing the second heat treatment, defects (oxygen vacancies) in the semiconductor 406b are efficiently reduced. The second heat treatment is performed to convert excess oxygen (oxygen) in the insulator 402 into the semiconductor 4. For example, see the description of the first heat treatment. Alternatively, the second heat treatment is preferably performed at a temperature lower than that of the first heat treatment. The temperature difference between the first heat treatment and the second heat treatment is 20°C or more and 150°C or less, preferably 40°C or less. The temperature is set to 100° C. or higher. This allows excess oxygen (oxygen) to be released from the insulator 402. It can reduce the amount of waste released.

[0171] Here, it is preferable that the semiconductor 406b has oxygen vacancies and hydrogen as little as possible. For example, it is preferable to reduce hydrogen contained in the semiconductor 406b by performing heat treatment. A higher heat treatment temperature is preferable because the hydrogen concentration can be reduced as the heat treatment temperature increases.

[0172] On the other hand, for example, when heat treatment is performed after the formation of the conductors 416a and 416b, The heat treatment may oxidize the wiring material, resulting in high resistance. In addition, it may be preferable to keep the heat treatment temperature after forming the conductor 416b low. Also in terms of manufacturing costs, it is preferable that the heat treatment temperature is as low as possible.

[0173] Here, consider the case where hydrogen trapped in oxygen vacancies in the semiconductor 406b is removed. The hydrogen trapped in the oxygen vacancies of 406b is desorbed from the trapping sites and transported to the outside of the semiconductor 406b. It is preferable to diffuse the

[0174] Here, for example, by adding excess oxygen to the semiconductor 406b or the semiconductor 406c, Oxygen may enter the oxygen vacancy where the element is trapped, making it easier to desorb hydrogen. In addition, excess oxygen is added to the semiconductor 406c, and the oxygen in the semiconductor 406c is transferred to the semiconductor 406b. By adding oxygen, oxygen vacancies can be reduced and the In some cases, hydrogen can be reduced at low temperatures. Conductor 406b may have a lower hydrogen concentration.

[0175] In addition, the added oxygen and hydrogen combine to form water, which facilitates the removal of hydrogen from the semiconductor 406b. It may become less noticeable.

[0176] Here, by adding oxygen, a high concentration When forming a region containing oxygen in the silicon substrate, damage may occur in the region. A high acceleration voltage is applied using an ion implantation method or the like to form a semiconductor 406b and a semiconductor on the semiconductor 406b. When oxygen is implanted into 406c, defects may occur during the implantation process.

[0177] Here, for example, a layer 420 is provided above the semiconductor 406b, and the oxygen-rich region is formed in the layer 420. By forming the semiconductor 406b in this manner, damage to the semiconductor 406b may be reduced. For example, a high concentration of oxygen is added to the layer 420 provided above the semiconductor 406b, and then , oxygen in layer 420 is transferred to semiconductor 406b by diffusion, whereby semiconductor 406 This can reduce damage to b.

[0178] Furthermore, by adding oxygen after providing the layer 420 on the semiconductor 406b, for example, Contamination can be prevented during the process of adding the element. This prevents the adhesion and contamination of elements other than oxygen from the treatment chamber or transport system.

[0179] In the example shown in FIG. 13C, a semiconductor 406c is provided over a semiconductor 406b. Layer 420 is deposited on conductor 406c. As will be described later, layer 420 is a semiconductor 406c. The film may be formed before providing c.

[0180] Layer 420 is preferably highly hydrogen permeable.

[0181] The layer 420 can be made of an insulator, a semiconductor, or the like. For example, the layer 420 can be made of gold. Examples of metal oxides include oxides of boron, carbon, fluorine, ma, and the like. Magnesium, aluminum, silicon, phosphorus, chlorine, argon, titanium, vanadium, Chromium, manganese, cobalt, nickel, copper, zinc, gallium, germanium, yttrium Aluminum, zirconium, niobium, molybdenum, ruthenium, indium, tin, lanthanum, Oxides containing odymium, hafnium, tantalum or tungsten, either in a single layer or multilayer For example, the layer 420 may be made of titanium oxide, manganese oxide, zinc oxide, or oxide. Gallium oxide, molybdenum oxide, indium oxide, tin oxide, tungsten oxide, etc. The layer 420 may be made of, for example, silicon oxide, silicon nitride, or silicon oxynitride. Silicon, silicon nitride oxide, etc. can be used.

[0182] The layer 420 may also contain at least one of indium, element M, and zinc, or Layer 420 may be made of an oxide having a plurality of layers, such as In-Ga oxide, In-Zn oxide, Zn-Ga oxide, Zn-Sn oxide, In-Ga-Zn oxide, I n-Sn-Zn oxide, In-Hf-Zn oxide, etc. may be used. In-Ga-Zn oxides containing more Ga than In, and In-Ga-Zn oxides containing more than twice as much Ga as In. In-Ga-Zn oxide, which has more than three times as much Ga as In, It is preferable to use n-oxides.

[0183] The layer 420 can also be made of the material described as the insulator 412 .

[0184] Next, oxygen is added (see FIG. 14(A)). Oxygen can be added by ion implantation, plasma In addition, in the ion implantation method, a mass separation method is used. Here, the ions are mainly, for example, O + and O2 + can be used.

[0185] After the oxygen addition, a heat treatment may be performed. By performing the heat treatment, oxygen is converted into the semiconductor 4 It may be easier to spread up to 06b.

[0186] Next, the layer 420 is removed (see FIG. 14(B)). The layer 420 is removed using a wet etching method. For example, wet etching can be used to remove the plating. This method is preferable because it does not cause damage such as Zuma and is a simple method.

[0187] In addition, in the wet etching, the film under the layer 420, for example, the semiconductor 406c and the semiconductor When the selectivity with respect to the conductor 406b is low, it is preferable to use dry etching. By performing dry etching of the layer 420 under conditions of high selectivity, the layer 4 It may be possible to perform 20 eliminations.

[0188] Next, an insulator that will become the insulator 412 is formed (see FIG. 14C). The insulating material can be deposited by sputtering, CVD, MBE, PLD, ALD, etc. The film may be formed using the same.

[0189] When the insulator 412 is made of a laminated film, each film is CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc.) (e.g., MBE, PLD, ALD, etc.) For example, the first layer may be formed by MOCVD and the second layer by sputtering. Alternatively, the first layer may be formed by the ALD method and the second layer by the MOCVD method. Alternatively, the first layer may be formed by the ALD method, and the second layer may be formed by the sputtering method. Alternatively, the first layer can be deposited by ALD, the second layer by sputtering, and the third layer by The film may be formed by the ALD method. By stacking these films, it is possible to give each layer a different function or property. By doing so, it is possible to form a more appropriate film as a whole laminated film.

[0190] That is, when the insulator 412 is made of a laminated film, for example, the n-th layer The sputtering method, CVD method (plasma CVD method, thermal CVD method, MCVD method, MOC The film is formed by at least one of the following methods: VD method, MBE method, PLD method, ALD method, etc. The n+1th layer is then deposited by sputtering, CVD (plasma CVD, thermal CVD, MCVD method, MOCVD method, etc.), MBE method, PLD method, ALD method, etc. Even if the film formation methods are different between the nth layer and the n+1th layer, (n is a natural number). The film formation method may be the same for the nth layer and the n+2th layer. Alternatively, the deposition method may be the same for all the films.

[0191] Next, oxygen may be added from above the insulator 412. The oxygen addition method is as follows: Reference can be made to the above-mentioned oxygen addition method.

[0192] Next, a third heat treatment may be performed. A semiconductor having higher oxygen permeability than the semiconductor 406c is selected. As the semiconductor, a semiconductor having lower oxygen permeability than the semiconductor 406a is selected. A semiconductor having the function of blocking oxygen is selected as the semiconductor that will become the conductor 406c. Alternatively, for example, the semiconductor 406a may be made of an insulator having higher oxygen permeability than the insulator that becomes the insulator 412. That is, the insulator 412 is selected to have a higher conductivity than the semiconductor 406a. A semiconductor with low oxygen permeability is selected. In other words, a semiconductor 406a that is permeable to oxygen is selected. In addition, a semiconductor that can block oxygen is selected as an insulator to be the insulator 412. At this time, a third heat treatment is performed to form an insulating material that can be used as a semiconductor. Excess oxygen contained in the insulator 402 moves to the semiconductor 406b via the body 406a. The semiconductor 406b is covered with a semiconductor that will become the semiconductor 406c and an insulator that will become the insulator 412. Therefore, the outward diffusion of excess oxygen is unlikely to occur. By performing the heat treatment, defects (oxygen vacancies) in the semiconductor 406b can be efficiently reduced. Note that the third heat treatment is performed to remove excess oxygen (oxygen) from the insulator 402 to the semiconductor 406b. The heating may be performed at a temperature at which the diffusion occurs. For example, the description of the first heating treatment may be referred to. Alternatively, the third heating treatment is preferably performed at a temperature lower than that of the first heating treatment. The temperature difference between the first and second heat treatments is 20°C to 150°C, preferably 40°C to 100°C. This allows excess oxygen (oxygen) to be released from the insulator 402. The insulator 412 has a function of blocking oxygen. In this case, the semiconductor 406c does not need to have the function of blocking oxygen. stomach.

[0193] Next, a conductor that will become the conductor 404 is formed. The conductor that will become the conductor 404 is formed by sputtering. The film may be formed by a method such as a ring method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0194] The insulator that becomes insulator 412 functions as a gate insulator for transistor 490. Therefore, when the conductor that becomes the conductor 404 is formed, the insulator that becomes the insulator 412 is not damaged. It is preferable to use a film formation method that does not give rise to a problem. That is, the film formation of the conductor is performed using the MCVD method or the like. It is preferable to have one.

[0195] When the conductor 404 is made of a laminated film, each film is CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc.) (e.g., MBE, PLD, ALD, etc.) For example, the first layer may be formed by MOCVD and the second layer by sputtering. Alternatively, the first layer may be formed by the ALD method and the second layer by the MOCVD method. Alternatively, the first layer may be formed by the ALD method, and the second layer may be formed by the sputtering method. Alternatively, the first layer can be deposited by ALD, the second layer by sputtering, and the third layer by The film may be formed by the ALD method. By stacking these films, it is possible to give each layer a different function or property. By doing so, it is possible to form a more appropriate film as a whole laminated film.

[0196] That is, when the conductor 404 is made of a laminated film, for example, the n-th layer The sputtering method, CVD method (plasma CVD method, thermal CVD method, MCVD method, MOC The film is formed by at least one of the following methods: VD method, MBE method, PLD method, ALD method, etc. The n+1th layer is then deposited by sputtering, CVD (plasma CVD, thermal CVD, MCVD method, MOCVD method, etc.), MBE method, PLD method, ALD method, etc. Even if the film formation methods are different between the nth layer and the n+1th layer, (n is a natural number). The film formation method may be the same for the nth layer and the n+2th layer. Alternatively, the deposition method may be the same for all the films.

[0197] In addition, the conductor that becomes the conductor 404 or a small amount of the laminated film of the conductor that becomes the conductor 404 At least one film and an insulator that becomes the insulator 412, or a product of an insulator that becomes the insulator 412 At least one of the layers may be formed by the same film formation method. ALD may also be used, which allows film formation without exposure to the atmosphere. As a result, it is possible to prevent impurities from being mixed in. Alternatively, for example, the insulator that becomes the insulator 412 can be A conductor that becomes the conductor 404 in contact with the insulator 412 that becomes the conductor 404 The insulating material may be formed by the same film forming method. As a result, it is possible to prevent the inclusion of impurities.

[0198] In addition, the conductor that becomes the conductor 404 or a small amount of the laminated film of the conductor that becomes the conductor 404 At least one film and an insulator that becomes the insulator 412, or a product of an insulator that becomes the insulator 412 At least one of the layers may be formed by the same deposition method. A tartering method may also be used, which allows the film to be formed without being exposed to the atmosphere. As a result, the inclusion of impurities can be prevented.

[0199] Next, a part of the conductor that will become the conductor 404 is etched to form the conductor 404 (FIG. 15(A). Note that the conductor 404 overlaps at least a part of the semiconductor 406b. Form it as follows.

[0200] Next, the insulator 408 is formed. The insulator 408 is formed by a method such as sputtering, CVD, or MB. The film may be formed by the E method, PLD method, ALD method or the like.

[0201] Next, a fourth heat treatment may be performed. A semiconductor having higher oxygen permeability than semiconductor 406c is selected. A semiconductor having lower oxygen permeability than 406a is selected. Alternatively, for example, a semiconductor 406a may be selected that has the function of blocking the In this case, a semiconductor having a higher oxygen permeability than the insulator 412 is selected. A semiconductor having lower oxygen permeability than the semiconductor 406a is selected. 6a is selected from a semiconductor having higher oxygen permeability than the insulator 408. 8, a semiconductor having lower oxygen permeability than the semiconductor 406a is selected. The insulator 406a is selected from a semiconductor that is permeable to oxygen. As the insulating layer, an insulating material having a function of blocking oxygen is selected. By performing this, excess oxygen contained in the insulator 402 is oxidized through the semiconductor 406a to the semiconductor 406b. The semiconductor 406b moves to the semiconductor 406c, the insulator 412, or the insulator 408. Since the film is covered with either of these, the outward diffusion of excess oxygen is unlikely to occur. By performing the fourth heat treatment with heating, defects (oxygen vacancies) in the semiconductor 406b are efficiently reduced. Note that the fourth heat treatment is performed to convert excess oxygen (oxygen) in the insulator 402 into a semiconductor. The temperature may be set to a temperature at which the diffusion of the metal into the body 406b occurs. For example, see the description of the first heat treatment. Alternatively, the fourth heat treatment is preferably performed at a temperature lower than that of the first heat treatment. The temperature difference between the first heat treatment and the fourth heat treatment is 20°C or more and 150°C or less, preferably The temperature is set to 40° C. or higher and 100° C. or lower. This allows excess oxygen (oxygen) to be released from the insulator 402. The insulator 408 has a function of blocking oxygen. In this case, the semiconductor 406c and / or the insulator 412 have a function of blocking oxygen. It's okay if you don't.

[0202] All of the first, second, third and fourth heat treatments Or you may not need to do some of it.

[0203] Next, an insulator 418 is formed (see FIG. 15B). The film may be formed by a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0204] In the above manner, the transistor 490 shown in FIG. 20 can be manufactured.

[0205] After the step shown in FIG. 14(C), the insulator 4 In this case, a part of the transistor 12 and a part of the semiconductor 406c may be etched. The shape of the sinter 490 is, for example, as shown in FIG. 15(C), The end face of the semiconductor 406c is connected to the end face of the semiconductor 412 in a generally smooth manner. The conductor that becomes the conductor 404, the insulator that becomes the insulator 412, and the semiconductor 40 When etching a part of the semiconductor that will become 6c, the same photolithography process is used. Alternatively, the conductor 404 may be used as a mask to mask the insulator and the The semiconductor 406c may be etched. The body 412 and the semiconductor 406c have the same shape in the top view. ) shows the enlarged cross section of the insulator 412 and / or semiconductor 404 rather than the conductor 404. 6c may have a protruding (protruding) shape, or as shown in the enlarged cross section of Figure 17(D), The conductor 404 protrudes (overhangs) beyond the insulator 412 and / or the semiconductor 406c. By making the shape as shown above, the possibility of defective shape can be reduced. This may reduce the gate leakage current.

[0206] <Transistor manufacturing method 2> Next, as a modification of the above-described manufacturing method 1, a manufacturing method of a transistor 490 shown in FIG. The method will be explained with reference to FIGS.

[0207] In the manufacturing method 1, an example in which the layer 420 is formed after the semiconductor 406c is provided is shown. 4 shows an example in which the layer 420 is formed before the semiconductor 406c is provided.

[0208] First, a substrate 442 and a conductor 444 are formed by the steps described with reference to FIGS. 12(A) to 12(C). 13, the insulator 402, the semiconductor 406a, the semiconductor 406b, the conductor 416a and the conductor 41 Form 6b.

[0209] Next, a layer 420 is formed, followed by adding oxygen (see FIG. 16(B)).

[0210] After the oxygen addition, a heat treatment may be performed. By performing the heat treatment, oxygen is converted into the semiconductor 4 It may be easier to spread up to 06b.

[0211] Next, the layer 420 is removed (see FIG. 16(C)). The material, deposition of layer 420, subsequent oxygen addition, and subsequent removal of layer 420 are described above. The method for producing the same can be referred to.

[0212] Next, the semiconductor 406c is formed.

[0213] In the transistor 490, in order to improve the characteristics of the transistor, the semiconductor 40 It may be preferable to use a film that is denser than the semiconductor 406b as the semiconductor 606c. It is preferable to use a film having lower hydrogen permeability than the semiconductor 406b as the semiconductor 406c. Alternatively, the semiconductor 406c may have lower oxygen permeability than the semiconductor 406b. On the other hand, when such a film is used for the semiconductor 406c, The hydrogen desorbed from the semiconductor 406a and the semiconductor 406b is blocked by the semiconductor 406c. Therefore, it may be difficult to reduce the hydrogen concentration in the semiconductor 406a and the semiconductor 406b. It may be difficult to diffuse oxygen from the layers above the body 406c.

[0214] Therefore, as shown in FIGS. 16(A) to 16(C), the semiconductor 406a and the semiconductor 40 After forming the semiconductor 406b, the layer 420 is provided, oxygen is added, and the semiconductor 406a and the semiconductor 406b are formed. After reducing the oxygen vacancies and hydrogen in b, the layer 420 is removed and a semiconductor 406c is provided. This may allow the hydrogen concentrations in the semiconductor 406a and the semiconductor 406b to be further reduced, which is preferable. I wish.

[0215] Here, a layer 420 is formed on the semiconductor 406b, and after oxygen is added, as shown in FIG. As shown, when etching is used to remove layer 420, the etching removes the semiconductor It is preferable that the etching rate of the layer 420 is higher than that of the semiconductor 406b. It is preferable that the etching rate of the semiconductor 40 by this etching is faster than that of the semiconductor 40 by this etching. It is preferable that the damage to the surface of 6b is small.

[0216] Alternatively, in the etching step of the layer 420, the very surface of the semiconductor 406b is etched. For example, when the layer 420 is formed, damage may occur or the elements contained in the layer 420 may be decomposed into the semiconductor 4 If they get close to the surface of 06b, they will be removed by etching the extreme surface. It is possible.

[0217] Here, as an example, the layer 420 and the semiconductor 406b may contain indium, the element M, and zinc. Consider the case where a membrane having at least one, or more than one, is used.

[0218] The difference between the indium content of layer 420 and the indium content of semiconductor 406b is For example, the ratio of indium in the layer 420 is preferably 0.6 times or less. It is preferable that the ratio is 0.3 times or less, and for example, 1.5 times or more is preferable, and 3 times or more is preferable. is more preferred.

[0219] Here, the ratio of indium is the ratio of indium to the sum of the number of atoms of indium, element M, and zinc. The ratio of the number of atoms of element M to that of zinc is the same.

[0220] Alternatively, the difference between the ratio of element M in layer 420 and the ratio of element M in semiconductor 406b is For example, the ratio of element M in layer 420 is preferably 0.6 times or less. More preferably, it is 0.3 times or less. Alternatively, it is preferably 1.5 times or more, and more preferably 3 times or more. It's nice.

[0221] Alternatively, the difference between the zinc content of layer 420 and the zinc content of semiconductor 406b may be large. For example, the ratio of zinc in layer 420 is preferably 0.6 times or less, and 0. It is more preferably 3 times or less, or preferably 1.5 times or more, and more preferably 3 times or more.

[0222] The difference between the ratio of indium, element M, or zinc in layer 420 and that in semiconductor 406b is large. This increases the selectivity when removing the layer 420 by, for example, dry etching. In addition, the difference in the ratio of these elements can be increased. For example, dry etching can improve the processing accuracy. When monitoring etching by spectroscopic analysis of plasma emission from reactive species, At this point, etching of layer 420 is largely complete and etching of the underlying semiconductor 406b begins. The timing of the change becomes easier to detect, and the amount of etching of the semiconductor 406b can be reduced. There is a match.

[0223] By having a higher ratio of zinc in layer 420 than in semiconductor 406b, e.g. When an acid or alkali is used as the etching chemical, the layer 420 is wet-etched. The acid solution may be, for example, For example, a solution containing phosphoric acid or a solution containing oxalic acid can be used. For example, an acid mixture of phosphoric acid, acetic acid, nitric acid, and pure water can be used. The mixture of acid, acetic acid, nitric acid, and pure water may be, for example, 85:5:5:5 by volume. In addition, the alkaline chemical solution is ammonia hydrogen peroxide (a mixture of ammonia water and hydrogen peroxide water). (things) can be used.

[0224] The conductors 416a and 416b may be made of metal nitrides such as tantalum nitride or white metal. By using platinum-based materials such as gold, ruthenium, and iridium, the wet etching of layer 420 can be achieved. This is more preferable because it can increase the resistance to etching.

[0225] Also, it is preferable that the layer 420 be made of a film having a higher hydrogen permeability than the semiconductor 406c. I wish.

[0226] For example, layer 420 may contain indium and semiconductor 406c may contain no indium. It is also preferable to use gallium oxide as the semiconductor 406c. For example, By using gallium oxide as the semiconductor 406c, a transistor with a lower off-current can be obtained. This can be realized.

[0227] Next, an insulator 412 is deposited.

[0228] Next, oxygen may be added from above the insulator 412. The oxygen addition method is as follows: Reference can be made to the above-mentioned oxygen addition method.

[0229] Next, a heat treatment may be carried out.

[0230] Next, a conductor 404 is formed (see FIG. 17A). Note that the conductor 404 is a semiconductor. It is formed to overlap at least a portion of the body 406b.

[0231] Next, the insulator 408 is formed. After the insulator 408 is formed, heat treatment may be performed. Next, an insulator 418 is formed (see FIG. 17B). A transistor 490 can be fabricated.

[0232] <Transistor manufacturing method 3> Next, as a variation of the above two manufacturing methods, a transistor 490 shown in FIG. The manufacturing method will be explained with reference to Figures 18 and 19. In the manufacturing method shown below, the layer 420 is removed. After that, the conductor 416a and the conductor 416b are formed.

[0233] The substrate 442, the conductor 413, the insulator 402, the semiconductor 406a, and the semiconductor 406b are shown in FIG. 12(A) and 12(B) are used to form the semiconductor layer (see FIG. 18(A)). .

[0234] Next, a layer 420 is formed (see FIG. 18(B)). Next, oxygen is added (see FIG. 18(C)). See C). ).

[0235] After the oxygen addition, a heat treatment may be performed. By performing the heat treatment, oxygen is converted into the semiconductor 4 It may be easier to spread up to 06b.

[0236] Next, layer 420 is removed. For the subsequent oxygen addition and subsequent removal of layer 420, please refer to the fabrication method described above. can.

[0237] Next, the conductor 416a and the conductor 416b are formed (see FIG. 19A). By forming the conductor 416a and the conductor 416b in a step after the oxygen addition, for example, The conductive material 416a and the conductive material 416b react with oxygen, and the reacted region is prevented from being insulated. In addition, for example, under the etching conditions of the layer 420, the conductor 416a and the conductor 4 Since it is no longer necessary to consider etching conditions with a high selectivity to 16b, wet etching This allows for more options for conditions such as chemicals used in etching and gases used in dry etching. This may make etching easier.

[0238] Next, the steps from FIG. 19(B) onward will be described. You can refer to the method.

[0239] First, the semiconductor 406c is formed. After the semiconductor 406c is formed, heat treatment may be performed. stomach.

[0240] Next, an insulator 412 is deposited.

[0241] Next, oxygen may be added from above the insulator 412. The oxygen addition method is as follows: Reference can be made to the above-mentioned oxygen addition method.

[0242] Next, a heat treatment may be carried out.

[0243] Next, the conductor 404 is formed. Note that the conductor 404 is formed by forming at least one of the semiconductor 406b. Next, the insulator 408 is formed. After the insulator 408 is formed, Heat treatment may be performed. Next, the insulator 418 is formed (see FIG. 19B). In this manner, the transistor 490 shown in FIG. 1 can be fabricated.

[0244] <Transistor manufacturing method 4> Next, an example of a manufacturing method of the transistor 490 shown in FIG. 2 will be described with reference to FIGS. 20 and 21. explain.

[0245] First, the insulator 552, the conductor 413, the insulator 402, and the semiconductor 43 which will become the semiconductor 406a are 6a and the semiconductor 436b that will become the semiconductor 406b are formed by the process described with reference to FIG. and form.

[0246] Next, a conductor 416 is formed. The conductor 416 is formed by the above-described method. Next, a mask 427 is formed (see FIG. 20(A)). 7 may be made of photoresist. Bottom Anti Reflective Coa (BARC) By providing an anti-reflection film, defects caused by halation can be suppressed. This allows for the production of fine shapes.

[0247] Next, the conductor 416 is etched using the mask 427, and the conductor 417 is Here, the conductor 417 is sometimes called a hard mask. In order to form the conductor 417 having a fine shape, a micro-machined metal film having a fine shape is used. If the mask 427 having a fine shape is too thick, it may collapse. Therefore, it is preferable that the mask 42 has a region thick enough to be able to stand on its own. The conductor 416 is etched using the mask 427 under conditions that the mask 427 can withstand. However, the conductor 416 is preferably thin enough to be easily cut away from the transistor 49. Conductor 416a and conductor 416b functioning as the source and drain electrodes of 40 16b, a certain thickness is required to increase the on-current of the transistor 490. Therefore, for example, it is preferable that the thickness is 5 nm or more and 30 nm or less, and preferably 5 nm or less. A conductive region having a thickness of 100 nm or more and 20 nm or less, more preferably 5 nm or more and 15 nm or less. The electrode 416 may be used.

[0248] Next, the semiconductor 436b and the semiconductor 436a are etched using the conductor 417 as a mask. The semiconductor 406a and the semiconductor 406b are formed by etching. Etching facilitates the formation of an s-channel structure (see Figure 20(C)). ).

[0249] Next, a part of the conductor 417 is etched to form the conductor 416a and the conductor 416b. In this way, the semiconductor 436a and the semiconductor 436b are formed (see FIG. 21(A)). Conductor 416, formed as a mask for etching, is the source of transistor 490. Conductors 416a and 416b functioning as a source electrode and a drain electrode, respectively. The conductor 416 that becomes the conductor 416a and the conductor 416b is also used as a mask. Therefore, the number of steps required to manufacture the transistor 490 can be reduced. The conductor 490 can reduce the area occupied by the conductors 416a and 416b. Therefore, this structure is suitable for fine semiconductor devices.

[0250] Next, the steps from FIG. 21(B) onwards will be explained. The method for producing the same can be referred to.

[0251] First, the layer 420 is formed. The materials that can be used for the layer 420 are the same as those described above. Please refer to the details of the manufacturing method. Next, oxygen is added (see FIG. 21(B)).

[0252] After the oxygen addition, a heat treatment may be performed. By performing the heat treatment, oxygen is converted into the semiconductor 4 It may be easier to spread up to 06b.

[0253] Next, the layer 420 is removed. Next, a semiconductor film that will become the semiconductor 406c is formed. After the film is formed, a heat treatment may be performed.

[0254] Next, an insulating film that will become the insulator 412 is formed.

[0255] Next, oxygen may be added from above the insulator 412. The oxygen addition method is as follows: Reference can be made to the above-mentioned oxygen addition method.

[0256] Next, a heat treatment may be carried out.

[0257] Next, a conductive film that will become the conductor 404 is formed.

[0258] Next, a part of the conductive film that will become the conductor 404 is etched to form the conductor 404. The conductor 404 is formed so as to overlap at least a portion of the semiconductor 406b.

[0259] Next, like the conductive film that becomes the conductor 404, a part of the insulating film that becomes the insulator 412 is etched. 412 is formed by etching.

[0260] Next, the conductive film that becomes the conductor 404 and the insulating film that becomes the insulator 412 are formed on the semiconductor 4 A part of the semiconductor that will become 406c is etched to form the semiconductor 406c (see FIG. 21(C)). Light. ).

[0261] Next, the insulator 408 is formed. After the insulator 408 is formed, heat treatment may be performed. Next, an insulator 418 is formed (see FIG. 22). A resistor 490 can be created.

[0262] <Structure of semiconductor device> Next, an example of a semiconductor device including the transistor 490 will be described with reference to FIG.

[0263] 23 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. shows different cross sections.

[0264] The semiconductor device shown in FIG. 23 includes a transistor 491 and an insulator 5 on the transistor 491. 52 and a transistor 490 on an insulator 552. Note that the insulator 552 is an oxide. It is an insulator that has the function of blocking atoms and hydrogen.

[0265] The transistor 491 is formed by an insulator 462 on a semiconductor substrate 400 and a conductive layer on the insulator 462. The conductive body 454, the insulator 470 in contact with the side surface of the conductive body 454, and the conductive body in the semiconductor substrate 400 454 and the insulator 470 do not overlap the region 476, and the insulator 470 overlaps the region 476. and region 474, which is a region.

[0266] The semiconductor substrate 400 may be, for example, a semiconductor element such as silicon or germanium, or a carbide. Silicon, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, oxide The semiconductor substrate 400 may be a compound semiconductor such as zinc oxide or gallium oxide. An amorphous semiconductor or a crystalline semiconductor may be used. As a crystalline semiconductor, a single crystal semiconductor may be used. , polycrystalline semiconductors, and microcrystalline semiconductors.

[0267] The insulator 462 functions as a gate insulator of the transistor 491. The insulator 454 functions as a gate electrode of the transistor 491. 70 functions as a sidewall insulator (also called a sidewall) of the conductor 454. Region 476 also functions as a source or drain region of transistor 491. The region 474 also functions as an LDD (Lightly Doped) transistor 491. It functions as a drain area.

[0268] The region 474 can be formed by adding impurities using the conductor 454 as a mask. After that, the insulator 470 is formed, and the conductor 454 and the insulator 470 are mass-produced. Region 476 can be formed by a gated impurity implant. When the region 74 and the region 476 are formed with the same impurity, the region 474 is thicker than the region 476. This results in a region with a lower impurity concentration than the region above.

[0269] The transistor 491 suppresses the short channel effect by having the region 474. Therefore, it is clear that this structure is suitable for miniaturization.

[0270] The transistor 491 is connected to the other transistors provided on the semiconductor substrate 400 and the region 46 0, etc. The region 460 is an insulating region. The region 460 is called STI (Shallow Trench Isolation). For example, instead of the region 460, Formed by the LOCOS (Local Oxidation of Silicon) method The transistors may be separated by insulating material.

[0271] In FIG. 23, a transistor having the same polarity as the transistor 491 is adjacent to the transistor 491. 23 shows an example in which a transistor 492 is arranged. and a transistor 492 are electrically connected via a region 476. The transistor 491 and the transistor 492 have different polarities. In this case, the transistor 491 and the transistor 492 may be connected to the region 46 0, and transistors 491 and 492 are connected to region 474 and region The type of impurity contained in 476 is changed, and the transistors 491 and 492 A semiconductor substrate 400 overlying a conductor that functions as one or both gate electrodes. In this case, a well region of a different conductivity type may be formed in a part of the region.

[0272] The transistors 491 and 492 have different polarities, which allows for complementary metal Oxide semiconductor (CMOS: Complementary Metal Oxide Semiconductor By constructing CMOS, it is possible to construct a semiconductor The power consumption of the device can be reduced, or the operating speed can be increased.

[0273] The structure of the transistor 491 and the transistor 492 is the same as that shown in FIG. For example, transistors 491 and 492 shown in FIG. As shown in the figure, the semiconductor substrate 400 has a protruding portion (also called a projection or a fin). The transistors 491 and 492 shown in FIG. Compared with the structure of transistor 491 and transistor 492 shown in FIG. The effective channel width relative to the area can be increased. This allows the current of the transistor 491 and the transistor 492 to be increased when they are turned on.

[0274] Or, for example, like transistor 491 and transistor 492 shown in FIG. Alternatively, a structure in which an insulator region 452 is provided in the semiconductor substrate 400 may be used. By using the structure of the transistor 491 and the transistor 492, the transistors are driven independently. This allows for more reliable isolation between transistors, thereby suppressing leakage current. As a result, the current when the transistors 491 and 492 are not conducting can be reduced. In addition, the current when the transistor 491 and the transistor 492 are turned on can be increased. It can be made easier.

[0275] As shown in FIG. 23, the transistors 491 and 492 , and the transistor 490, etc., an insulator 552 is preferably provided between the insulator 552 and the transistor 490, etc. 552 preferably has a function of blocking oxygen and hydrogen. 552 is more effective at blocking oxygen and hydrogen than semiconductor 406a and / or semiconductor 406c. The insulating material 552 is preferably made of, for example, aluminum oxide, oxide, or the like. Aluminum oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide, yttrium oxide nitride tritium, hafnium oxide, hafnium oxynitride, tantalum oxide, zirconium oxide, Lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (B a,Sr)TiO3(BST) or the like can be used in a single layer or laminated layer. These insulating films may be nitrided to form oxynitride films. This is preferable because it has excellent barrier properties against oxygen.

[0276] The insulator 552 is formed by a sputtering method, a chemical vapor deposition (CVD) method, or the like. por Deposition method, molecular beam epitaxy (MBE) Beam Epitaxy or Pulsed Laser Deposition (PLD) ser Deposition) method, Atomic Layer Deposition (ALD) method The film may be formed by using a deposition method or the like.

[0277] The CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD) method, and thermal CVD (TCVD) method. Furthermore, depending on the source gas used, it can be classified into metal CVD (MCVD:Me tal CVD) method, Metal Organic CVD (MOCVD) method D) can be divided into laws.

[0278] The plasma CVD method produces high-quality films at relatively low temperatures. The thermal CVD method uses plasma. Since no plasma is used, no plasma damage occurs and a film with few defects can be obtained.

[0279] In the CVD method, the composition of the resulting film can be controlled by adjusting the flow rate ratio of the source gases. For example, in the MCVD and MOCVD methods, a film of any composition can be produced by adjusting the flow rate ratio of the source gases. In addition, for example, in the MCVD method and the MOCVD method, the film can be formed. By changing the flow rate ratio of the source gases while When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film by hand, the time required for film formation is shortened by the time required for transport and pressure adjustment. Therefore, the productivity of the transistor 490 can be improved.

[0280] For example, the transistor 491 and the transistor 492 are silicon transistors. In the case of a silicon wafer, hydrogen is supplied from an external source to reduce the dangling bonds of silicon. The supply of hydrogen can be achieved by, for example, For example, the heat treatment may be performed in an atmosphere containing hydrogen. an insulator including By performing the above, the hydrogen is diffused and supplied to the transistor 491 and the transistor 492. Specifically, the insulators on the transistors 491 and 492 may be It is preferable that the insulator 464 is an insulator containing hydrogen. For example, a layer structure of silicon oxynitride or silicon oxide and silicon nitride may be used. The insulating layer may have a layered structure including silicon dioxide or silicon nitride.

[0281] For example, insulators containing hydrogen are those that are heated to temperatures between 100°C and 700°C or 10 1×10 in the surface temperature range of 0℃ to 500℃ 18 atoms / cm 3 That's it, 1×1 0 19 atoms / cm 3 or more than 1×10 20 atoms / cm 3 More than hydrogen (hydrogen It may also emit atoms equivalent to the number of atoms.

[0282] Incidentally, hydrogen diffused from the insulator 464 is absorbed by the conductive material provided at the opening of the insulator 464. through the insulator 472, the wiring layer 467 on the insulator 464, the wiring layer 469 on the wiring layer 467, etc. , the hydrogen may reach the vicinity of the transistor 490, but the insulator 552 blocks the hydrogen. Because of this function, only a small amount of hydrogen reaches the transistor 490. Carrier traps and carrier sources in oxide semiconductors affect the electrical characteristics of transistors 490. Therefore, blocking hydrogen with the insulator 552 is not recommended. It is important to improve the performance and reliability of conductor devices. The conductors filling the openings electrically connect elements such as transistors and capacitors. In addition, in the wiring layer 467 and the wiring layer 469, etc., The hatched area indicates a conductor, and the unhatched area indicates an insulator. The wiring layers such as 67 and the wiring layer 469 are provided by filling the openings of the conductor 472. It has the function of electrically connecting conductors.

[0283] On the other hand, for example, when oxygen is supplied to the transistor 490 from the outside, Since oxygen vacancies can be reduced, the electrical characteristics of the transistor may be improved. Oxygen may be supplied by, for example, heat treatment in an atmosphere containing oxygen. Alternatively, for example, an insulator containing excess oxygen (oxygen) is placed near the transistor 490, and the The oxygen may be diffused by heat treatment and supplied to the transistor 490 . Here, the insulator 402 of the transistor 490 is an insulator containing excess oxygen.

[0284] The diffused oxygen reaches the transistor 491 and the transistor 492 through each layer. However, since the insulator 552 has a function of blocking oxygen, Only a small amount of oxygen reaches the transistor 491 and the transistor 492. If the transistor 492 is a silicon-based transistor, the silicon may contain oxide. The inclusion of elements reduces the crystallinity of silicon and inhibits the movement of carriers. Therefore, blocking oxygen with the insulator 552 is a This has important implications for improving the performance and reliability of the device.

[0285] In addition, in FIG. 23 and the like, the semiconductor device has an insulator 408 on the transistor 490. This is preferable. The insulator 408 has a function of blocking oxygen and hydrogen. , the insulator 408 is, for example, more oxygen-doped than the semiconductor 406a or / and the semiconductor 406c. The insulator 408 has a high blocking function for hydrogen and, for example, the insulator 552 Please refer to the description.

[0286] The semiconductor device includes an insulator 408, which prevents oxygen from diffusing out of the transistor 490. Therefore, the amount of excess oxygen (oxygen) contained in the insulator 402 or the like can be suppressed. In contrast, oxygen can be effectively supplied to the transistor 490. 8 includes hydrogen that is mixed in from layers provided above the insulator 408 or from the outside of the semiconductor device. Because it blocks impurities, the electrical characteristics of the transistor 490 are degraded by the inclusion of impurities. This can prevent the

[0287] For convenience, the insulator 552 and / or the insulator 408 are distinguished from the transistor 490. However, it may be a part of the transistor 490.

[0288] Note that the semiconductor device preferably includes an insulator 418 over the insulator 408. The semiconductor device also includes a conductive film formed in the opening in the insulator 418 and the insulator 408. conductor 424 electrically connected to transistor 490 via conductor 416b; It's okay to have it.

[0289] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0290] (Embodiment 2) In this embodiment, the semiconductor 406a, the semiconductor 406b, and the semiconductor The structure of an oxide semiconductor according to one embodiment of the present invention, which can be applied to the semiconductor layer 406c and the like, will be described. In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0291] <Oxide semiconductor structure> The structure of an oxide semiconductor will be described below.

[0292] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Examples of the oxide semiconductor include a semiconductor, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor.

[0293] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxides. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC- Examples of such oxide semiconductors include OS, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors.

[0294] <caac-os> First, let me explain about CAAC-OS. Axis-Aligned Nanocrystals It can also be done as follows.

[0295] CAAC-OS is an oxide having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0296] Transmission Electron Microscope (TEM) A combined analysis image (high resolution) of the bright-field image and diffraction pattern of CAAC-OS was obtained by using a microscope. When observing a high-resolution TEM image, multiple pellets can be confirmed. On the other hand, high-resolution TEM images reveal the boundaries between pellets, i.e., grain boundaries. Therefore, the CAAC-OS is not clearly characterized by the grain boundaries. It can be said that the resulting decrease in electron mobility is unlikely to occur.

[0297] Below, we will explain the CAAC-OS observed by TEM. 1 shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction is required. The spherical aberration correction function was used to obtain high-resolution TEM images. , specifically referred to as a Cs-corrected high-resolution TEM image. Cs-corrected high-resolution TEM images can be obtained, for example, This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0298] An enlarged Cs-corrected high-resolution TEM image of region (1) in Figure 26(A) is shown in Figure 26(B). From Figure 26(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). Or it reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0299] As shown in Figure 26(B), CAAC-OS has a characteristic atomic arrangement. ) shows the characteristic atomic arrangement with auxiliary lines. ) the size of each pellet is about 1 nm to 3 nm, and the size of each pellet is about 1 nm to 3 nm. It can be seen that the size of the gap caused by the tilt is about 0.8 nm. The pellets may also be referred to as nanocrystals (nc).

[0300] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on the substrate 5120 were The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 26(D)). Between the pellets observed in FIG. 26(C), The portion where the tilt occurs corresponds to the area 5161 shown in FIG.

[0301] FIG. 27(A) shows the C of the plane of the CAAC-OS observed from a direction approximately perpendicular to the sample surface. The s-corrected high-resolution TEM images are shown. Regions (1), (2), and (3) in Figure 27(A). ) are enlarged Cs-corrected high-resolution TEM images shown in Figure 27(B), Figure 27(C), and Figure 27(D), respectively. As shown in Figure 27(D), Figure 27(B), Figure 27(C) and Figure 27(D) show that the pellet It can be seen that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0302] Next, C analyzed by X-ray diffraction (XRD) For example, CAAC-O with InGaZnO4 crystals When S is subjected to structural analysis using the out-of-plane method, the results are as shown in Figure 28(A). As shown in the figure, a peak may appear at a diffraction angle (2θ) of around 31°. Since this is attributed to the (009) plane of the ZnO4 crystal, it is believed that the CAAC-OS crystal is c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0303] In addition, in the structural analysis of CAAC-OS using the out-of-plane method, 2θ is 31 In addition to the peak around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks in the vicinity indicate that some of the CAAC-OS crystals do not have a c-axis orientation. The more preferable CAAC-OS is a structure produced by the out-of-plane method. The analysis shows a peak at 2θ around 31°, but no peak at 2θ around 36°.

[0304] On the other hand, in-pla, X-rays are incident on the CAAC-OS from a direction almost perpendicular to the c-axis. When structural analysis is performed using the NE method, a peak appears at 2θ around 56°. This peak is due to I It is attributed to the (110) plane of the nGaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 5 The sample is fixed at approximately 6° and analyzed while rotating around the normal vector of the sample surface (φ axis). Even if a (φ scan) is performed, no clear peak appears as shown in Figure 28(B). On the other hand, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ When scanned, it is assigned to a crystal plane equivalent to the (110) plane as shown in Figure 28(C). Six peaks are observed. Therefore, from the structural analysis using XRD, CAAC-OS It can be seen that the orientation of the a-axis and b-axis is irregular.

[0305] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the probe diameter is 300 nm parallel to the sample surface. When an electron beam is incident on the sample, a diffraction pattern (selected area transmission electron diffraction) as shown in FIG. This diffraction pattern may appear due to the presence of InGaZnO4 This includes spots due to the (009) plane of the crystal. The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis faces the surface to be formed or the upper surface. On the other hand, when the probe was applied to the same sample perpendicular to the sample surface, The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in Figure 29(B). 9(B) shows a ring-shaped diffraction pattern. It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. The first ring in FIG. 29(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and the like. This is thought to be due to the (110) surface.

[0306] In addition, the CAAC-OS is an oxide semiconductor with a low density of defect states. Defects include, for example, defects caused by impurities and oxygen vacancies. AC-OS can also be considered an oxide semiconductor with a low impurity concentration. S can also be said to be an oxide semiconductor with few oxygen vacancies.

[0307] Impurities contained in oxide semiconductors can act as carrier traps or as carrier generation sources. In addition, oxygen vacancies in an oxide semiconductor may become carrier traps or By capturing hydrogen, it may become a carrier generation source.

[0308] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon are more oxidative than metal elements that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0309] In addition, oxide semiconductors with low defect state density (few oxygen vacancies) have low carrier density. Such an oxide semiconductor can be a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and a low density of defect states. Therefore, the oxide semiconductor is likely to be a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. A transistor using AC-OS has electrical characteristics in which the threshold voltage is negative (normal It is also called "on." It is rare for it to become a high-purity intrinsic or substantially high-purity intrinsic Oxide semiconductors have few carrier traps. The charge that is trapped takes a long time to be released and behaves like a fixed charge. Therefore, transistors using oxide semiconductors with high impurity concentrations and high defect state densities are being developed. On the other hand, transistors using CAAC-OS can have unstable electrical characteristics. The resulting transistor has little fluctuation in electrical characteristics and is highly reliable.

[0310] In addition, CAAC-OS has a low defect level density, so it is possible to generate Therefore, the carriers are less likely to be captured by the defect level. The electrical characteristics of a transistor are less susceptible to change when irradiated with visible light or ultraviolet light.

[0311] <Microcrystalline oxide semiconductor> Next, a microcrystalline oxide semiconductor will be described.

[0312] Microcrystalline oxide semiconductors have regions where crystals can be confirmed in high-resolution TEM images. The microcrystalline oxide semiconductor has a crystal structure including a region where a crystal part is clearly visible and a region where a crystal part is not clearly visible. The crystal part contained is between 1 nm and 100 nm, or between 1 nm and 10 nm in size. In particular, fine crystals of 1 nm to 10 nm or 1 nm to 3 nm are often The oxide semiconductor with nanocrystalline structure is called nc-OS (nanocrystalline silicon). nc-OS is called NC-Oxide Semiconductor. In some cases, the grain boundaries cannot be clearly identified in the TEM images. It is possible that the origin of the pellets in C-OS is the same as that of the pellets in C-OS. The crystalline part of the OS is sometimes called a pellet.

[0313] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, an XRD apparatus using an X-ray beam with a diameter larger than that of the pellet is used for nc-OS. When structural analysis is performed using the out-of-plane method, the crystal plane is shown. In addition, the probe diameter ( For example, electron diffraction (also called selected area electron diffraction) is performed using an electron beam of 50 nm or more. On the other hand, for nc-OS, a halo-like diffraction pattern is observed. Nanobeam electron circuits use electron beams with a probe diameter close to the pellet size or smaller than the pellet. When the nc-OS is subjected to nanobeam electron diffraction, spots are observed. When the light is too bright, a circular (ring-shaped) area of ​​high brightness may be observed. Multiple spots may be observed within a ring-like region.

[0314] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc -OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) The semiconductor may also be referred to as an oxide semiconductor having a structure (s).

[0315] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. However, the density of defect states in nc-OS is lower than that in amorphous oxide semiconductors. There is no regularity in the crystal orientation between different pellets in S. Therefore, nc-OS is The defect density is higher than that of AAC-OS.

[0316] <Amorphous oxide semiconductor> Next, the amorphous oxide semiconductor will be described.

[0317] Amorphous oxide semiconductors are oxides in which the atomic arrangement within the film is irregular and does not have crystalline parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0318] In amorphous oxide semiconductors, no crystalline parts can be observed in high-resolution TEM images.

[0319] When structural analysis is performed on amorphous oxide semiconductors using an XRD device, out-of-p In the analysis by the Lane method, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductor, a halo pattern is observed. When nanobeam electron diffraction is performed on the sample, no spots are observed, and only a halo pattern is observed. It is observed.

[0320] There are various views on amorphous structures. For example, A structure that does not have this property is called a completely amorphous structure. The distance between the nearest neighboring atoms or the second nearest neighboring atoms is also called the structure. A structure that has order at the interface but does not have long-range order is sometimes called an amorphous structure. Therefore, according to the strictest definition, an oxide semiconductor that has even a slight degree of order in its atomic arrangement is called a non-metallic oxide semiconductor. Furthermore, it cannot be called an crystalline oxide semiconductor. Therefore, since the semiconductor has crystalline parts, it cannot be called an amorphous oxide semiconductor. For example, CAAC-OS and nc-OS are used as amorphous oxide semiconductors or completely amorphous It cannot be called an oxide semiconductor.

[0321] <Amorphous-like oxide semiconductor> Note that an oxide semiconductor may have a structure between an nc-OS and an amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor (aluminum oxide). ike OS:amorphous-like Oxide Semiconductor It is called r).

[0322] In a-like OS, voids (also called voids) are observed in high-resolution TEM images. In addition, crystals can be clearly seen in high-resolution TEM images. and regions where no crystalline portions can be identified.

[0323] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0324] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS (hereinafter referred to as Sample B) and CAAC-OS (hereinafter referred to as Sample C) are prepared. Both samples are In-Ga-Zn oxides.

[0325] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all the materials have crystalline parts.

[0326] The determination of which part is to be regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, six of which are stacked in layers in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing is 0.28 nm or more and 0.30 nm or less are considered to be InGaZnO4 crystal parts. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0327] Figure 30 shows an example of investigating the average size of the crystal parts (22 to 45 locations) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystalline part of ke OS grows in size according to the cumulative amount of electron irradiation. Specifically, as shown in Figure 30 (1), the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2 × 10 8 e - / n m 2 On the other hand, in the nc-O For S and CAAC-OS, the cumulative electron irradiation dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystal part within the range of As shown in (2) and (3) in Figure 30, regardless of the cumulative electron dose, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. It can be seen that...

[0328] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in nc-OS and CAAC-OS, the growth of the crystals by electron irradiation is almost nonexistent. In other words, a-like OS is not as good as nc-OS and CAAC- It is clear that it has an unstable structure compared to the OS.

[0329] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal of the same composition. The density of the nc-OS is 78.6% or more and less than 92.3% of that of the normal crystal. The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0330] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It will be less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0331] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions may be used in any proportion. By combining single crystals with the desired composition, the density equivalent to that of a single crystal can be estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate by combining different types of single crystals.

[0332] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or a microcrystalline oxide semiconductor. The layer may be a laminated film containing two or more of a compound semiconductor and a CAAC-OS.

[0333] <Film formation model> An example of a film formation model for CAAC-OS and nc-OS will be described below.

[0334] FIG. 31(A) shows a process of forming a CAAC-OS film by sputtering. Schematic diagram of the inside of the membrane chamber.

[0335] The target 5130 is glued to a backing plate. A plurality of magnets are arranged at positions facing the target 5130 through the magnets. The magnetic field is generated by a number of magnets. The sputtering method used is called magnetron sputtering.

[0336] The substrate 5120 is disposed so as to face the target 5130, and the distance therebetween is d( The target-substrate distance (also called the TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the film deposition chamber is 0.02m or more and 0.5m or less. oxygen, argon, or a gas mixture containing 5% or more by volume of oxygen) and The pressure is controlled to 1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a voltage above a certain level to the target 5130, a discharge begins and plasma is generated. It is confirmed that a high density plasma region is generated near the target 5130 by the magnetic field. In the high density plasma region, the deposition gas is ionized, and ions 5101 The ions 5101 are, for example, positive ions of oxygen (O + ) and argon cations ( Ar + ) etc.

[0337] Here, the target 5130 has a polycrystalline structure having a plurality of crystal grains, and The crystal grains include cleavage planes. The crystal structure of InGaZnO4 is shown in Fig. 32(A). This is the structure of InGaZnO4 crystals observed from the outside. In the two Ga-Zn-O layers, the oxygen atoms in each layer are arranged in close proximity. The negative charge of the oxygen atom makes it possible to separate two adjacent atoms. Repulsion occurs between the Ga-Zn-O layers. As a result, the InGaZnO4 crystals are The cleavage plane is located between the two Ga-Zn-O layers.

[0338] Ions 5101 generated in the high-density plasma region are attracted to the target 5130 by the electric field. The particles are accelerated and eventually collide with the target 5130. At this time, flat or planar particles are formed from the cleavage plane. pellets 5100a and 5100b, which are pellet-shaped sputtered particles, are peeled off, The pellets 5100a and 5100b are ejected by the ions 5101. The impact of a collision can cause distortion of the structure.

[0339] The pellet 5100a is a flat plate or pellet having a triangular, for example, equilateral triangular, plane. The pellet 5100b is a sputtered particle having a hexagonal shape, for example, a regular hexagonal plane. The pellets 5100a and 5100b are sputtered particles in the form of plates or pellets. Sputter particles in the form of flat or pellets, such as pellets 5100b, are collectively called pellets. The planar shape of the pellet 5100 is not limited to a triangle or a hexagon, for example. For example, there are cases where the shape is made up of multiple triangles. In some cases, two squares (or polygons) may join together to form a quadrilateral (for example, a rhombus).

[0340] The thickness of the pellet 5100 is determined depending on the type of deposition gas, etc. The reason for this will be explained later. It is preferable that the thickness of the pellet 5100 is uniform. Thin pellets are preferable to thick cubes. The thickness of the PET 5100 is 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. For example, the pellet 5100 has a width of 1 nm or more and 3 nm or less, preferably The pellet 5100 is the one shown in FIG. ) corresponds to the initial nucleus described in (1). For example, the target 5 having In-Ga-Zn oxide When ions 5101 are bombarded onto the Ga-Zn-O layer 130, as shown in FIG. 32(B), A pellet 5100 having three layers, an In-O layer, a Ga-Zn-O layer, and a Ga-Zn-O layer, is exfoliated. Figure 2(C) shows the structure of the exfoliated pellet 5100 observed from a direction parallel to the c-axis. The ret 5100 has two Ga-Zn-O layers (pan) and an In-O layer (filler). It can also be called a nano-sized sandwich structure.

[0341] As the pellet 5100 passes through the plasma, it receives a charge, causing the sides to become negative and The pellet 5100 may have, for example, negatively charged oxygen atoms on the side. The sides have the same polarity of charge, so the charges repel each other. This allows the material to maintain its flat or pellet shape. When the OS is an In-Ga-Zn oxide, the oxygen atom bonded to the indium atom is negatively charged. It may become charged or bond with indium, gallium or zinc atoms. The oxygen atoms may become negatively charged. When the electrons are released, they bond with indium atoms, gallium atoms, zinc atoms, oxygen atoms, etc. in the plasma. The difference in size between (2) and (1) in Figure 30 above is This corresponds to the growth in the plasma. Here, when the substrate 5120 is at about room temperature, Since the growth of pellet 5100 on 120 is difficult, it becomes nc-OS (Figure 31 (See (B).) Since the film can be formed at room temperature, even if the substrate 5120 has a large area, It is possible to form nc-OS films. In addition, pellet 5100 is grown in plasma. To achieve this, it is effective to increase the film formation power in the sputtering method. By doing so, the structure of the pellet 5100 can be stabilized.

[0342] As shown in FIG. 31(A) and FIG. 31(B), for example, a pellet 5100 is It flies like a kite through the air and flutters up to the top of the board 5120. Since the pellet 100 is electrically charged, it will be attracted to an area where other pellets 5100 are already deposited. Here, on the upper surface of the substrate 5120, a repulsive force is generated in a direction parallel to the upper surface of the substrate 5120. A horizontal magnetic field (also called a horizontal magnetic field) is generated between the substrate 5120 and the target 5120. Since a potential difference is applied between the substrate 5120 and the target 5130, Therefore, the pellet 5100 is disposed on the upper surface of the substrate 5120 in the following direction: The magnetic field and the electric current act on the object, creating a force (Lorentz force). This can be understood by the left-hand rule.

[0343] The pellet 5100 has a larger mass than an atom. In order to move the surface, it is important to apply some kind of force from the outside. One of these forces is It is possible that the force is generated by the action of a magnetic field and an electric current. To provide sufficient force to move the top surface of 5120, the top surface of substrate 5120 must: The magnetic field parallel to the upper surface of the substrate 5120 is 10 G or more, preferably 20 G or more, and more preferably It is preferable to provide a region where the resistance is 30 G or more, and more preferably 50 G or more. On the upper surface of the plate 5120, a magnetic field parallel to the upper surface of the substrate 5120 The magnetic field is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more than the magnetic field perpendicular to the upper surface. It is preferable to provide an area where the thickness is 5 times or more, more preferably 5 times or more.

[0344] At this time, the magnet and the substrate 5120 move or rotate relative to each other. The direction of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change. On the upper surface of the plate 5120, the pellet 5100 is subjected to forces from various directions. You can move to.

[0345] Also, when the substrate 5120 is heated as shown in FIG. 31(A), the pellet 510 0 and the substrate 5120, the resistance due to friction etc. is small. The pellet 5100 glides over the top surface of the substrate 5120. The transfer occurs with the flat surface facing the substrate 5120. When the particles reach the side of the pellet 5100, the sides are joined together. The oxygen atom on the side of 00 is released. The released oxygen atom causes the Since oxygen vacancies may be filled, a CAAC-OS with a low density of defect states is obtained. The temperature of the upper surface of the plate 5120 is, for example, 100°C or higher and lower than 500°C, or 150°C or higher and 450°C. or 170° C. or higher and lower than 400° C. Even in such a case, it is possible to form a CAAC-OS film.

[0346] In addition, the pellet 5100 is heated on the substrate 5120, whereby the atoms are rearranged. The distortion of the structure caused by the collision of the ions 5101 is relaxed. 100 is almost a single crystal. Pellet 5100 is almost a single crystal. Even if the pellets 5100 are heated after being bonded together, the pellets 5100 themselves do not expand. Therefore, the gaps between the pellets 5100 widen, and the crystallization Defects such as grain boundaries do not form, and crevasses do not form.

[0347] In addition, the CAAC-OS is not made of a single-crystal oxide semiconductor. The aggregates of pellets 5100 (nanocrystals) resemble bricks or blocks stacked on top of each other. In addition, there are no grain boundaries between the pellets 5100. Heating during film formation, heating after film formation, or bending can cause deformation such as shrinkage in CAAC-OS. Even in such a case, it is possible to relieve local stress or release strain. This structure is suitable for use in flexible semiconductor devices. The resulting arrangement is like a disorderly stack of Red 5100 (nanocrystals).

[0348] When the target 5130 is sputtered by the ions 5101, not only the pellet 5100 but also Zinc oxide is lighter than pellet 5100. Therefore, it reaches the upper surface of the substrate 5120 first. A zinc oxide layer 5102 having a thickness of 2 nm or more and 5 nm or less, or 0.5 nm or more and 2 nm or less, is formed. Figure 33 shows a schematic cross-sectional view.

[0349] As shown in FIG. 33(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are deposited. The pellets 5105c are arranged so that their sides are in contact with each other. After being deposited on pellet 5105b, the pellet 510 slides on pellet 5105b. In another aspect of FIG. 5a, a plurality of particles 510 detached from the target along with zinc oxide. 3 is crystallized by heating from the substrate 5120 to form a region 5105a1. The number of particles 5103 may include oxygen, zinc, indium, and gallium, among others.

[0350] As shown in FIG. 33(B), the region 5105a1 is integral with the pellet 5105a. The pellet 5105c is formed by the side surface of the pellet 5105a. Place it so that it is in contact with another side of 5105b.

[0351] Next, as shown in FIG. 33(C), a pellet 5105d is further added to the pellet 5105a2. After being deposited on pellet 5105a2 and pellet 5105b, It slides on the other side of the pellet 5105c. The pellet 5105e slides on the zinc oxide layer 5102.

[0352] As shown in FIG. 33(D), the pellet 5105d has a side surface similar to that of the pellet 51. The pellet 5105e is placed so that its side faces the pellet 5105a2. Also, the other side of the pellet 5105d is placed in contact with the other side of the pellet 5105c. On the surface, a plurality of particles 5103 peeled off from the target 5130 together with zinc oxide are formed. Heat from plate 5120 causes crystallization, forming region 5105d1.

[0353] As described above, the piled pellets are arranged so that they come into contact with each other, and the side surfaces of the pellets are The growth occurs to form a CAAC-OS on the substrate 5120. The individual pellets of AC-OS are larger than those of nc-OS. The difference in size between (3) and (2) corresponds to the growth after deposition.

[0354] In addition, the gaps between the pellets become extremely small, forming one large pellet. One large pellet may have a single crystal structure. The size is 10 nm or more and 200 nm or less, 15 nm or more and 100 nm or less when viewed from the top surface, or In this case, the size of the transistors used can be between 20 nm and 50 nm. In an oxide semiconductor, a channel formation region may be contained in one large pellet. That is, a region having a single crystal structure can be used as a channel forming region. As the size of the lattice increases, the region with a single crystal structure becomes the channel formation region of the transistor. , may be used as source and drain regions.

[0355] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. By doing so, it may be possible to improve the frequency characteristics of the transistor.

[0356] Based on the above model, it is assumed that the pellet 5100 is deposited on the substrate 5120. CAAC-OS can be deposited even when the surface does not have a crystalline structure. This indicates that the growth mechanism is different from epitaxial growth. AC-OS does not require laser crystallization and can be grown uniformly even on large glass substrates. For example, if the structure of the upper surface (surface to be formed) of the substrate 5120 is an amorphous structure (e.g., It is possible to form a CAAC-OS film even on amorphous silicon oxide.

[0357] In addition, even if the upper surface of the substrate 5120 on which the formation is performed is uneven, the CAAC-OS It can be seen that the pellets 5100 are arranged along the shape of the substrate 5120. If the surface is atomically flat, the pellet 5100 will have a flat surface that is parallel to the ab plane. If the thickness of the pellet 5100 is uniform, it is flat and has a uniform thickness. A layer with high crystallinity is formed. Then, the layer is stacked in n layers (n is a natural number). By doing so, CAAC-OS can be obtained.

[0358] On the other hand, even if the upper surface of the substrate 5120 has irregularities, the CAAC-OS can be easily formed by the pellet 51 The structure is made up of n layers (n is a natural number) of layers in which 00 are arranged along the unevenness. Because the surface of the CAAC-OS is uneven, gaps tend to form between the pellets. However, even in this case, intermolecular forces act between the pellets 5100, and unevenness may occur. Even if the pellets are uneven, they are arranged so that the gaps between them are as small as possible. Furthermore, a CAAC-OS having high crystallinity can be obtained.

[0359] Since the CAAC-OS film is formed using this model, the sputtered particles are distributed evenly across the film thickness. It is preferable that the sputtered particles are in the form of thick dices. In this case, the surface facing the substrate 5120 is not uniform, and the thickness and crystal orientation cannot be made uniform. There is.

[0360] The film formation model shown above allows for highly crystalline films to be formed even on a surface with an amorphous structure. Therefore, a CAAC-OS having the desired properties can be obtained.

[0361] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0362] (Embodiment 3) In this embodiment, a circuit of a semiconductor device including a transistor or the like according to one embodiment of the present invention will be described. An example of the path will be described.

[0363] <CMOSインバータ> The circuit diagram shown in FIG. 34A includes a p-channel transistor 2200 and an n-channel transistor The transistors 2100 are connected in series and the gates of the transistors are connected together. The configuration of the OS inverter is shown.

[0364] <Semiconductor device structure 2> 35 is a cross-sectional view of the semiconductor device corresponding to FIG. 34(A). The device includes a transistor 2200 and a transistor 2100. The transistor 2100 is disposed above the transistor 2200. 1 of the first embodiment is used. The semiconductor device according to the embodiment is not limited to this. For example, the semiconductor device shown in FIGS. A transistor such as the above may be used as the transistor 2100. For the transistor 2100, the above description of the transistor may be referred to as appropriate.

[0365] The transistor 2200 shown in FIG. 35 is a transistor using a semiconductor substrate 450. The transistor 2200 includes a region 472a in the semiconductor substrate 450 and a region 472b in the semiconductor substrate 450. The transistor shown in FIG. For example, transistor 491 and transistor 492 shown in FIG. 23 are used as the transistor 2200. You may also use the

[0366] In transistor 2200, regions 472a and 472b are source and drain regions. The insulator 462 also functions as a gate insulator. The conductor 454 also functions as a gate electrode. The resistance of the channel forming region can be controlled by the potential applied to the electrode 454 . That is, the potential applied to the conductor 454 causes conduction between the region 472a and the region 472b. Non-conduction can be controlled.

[0367] For the semiconductor substrate 450, the description of the semiconductor substrate 400 can be referred to.

[0368] The semiconductor substrate 450 is a semiconductor substrate containing impurities that impart n-type conductivity. However, a semiconductor substrate having impurities that impart p-type conductivity is used as the semiconductor substrate 450. In that case, the region that will become the transistor 2200 is given n-type conductivity. Alternatively, if the semiconductor substrate 450 is an i-type, It's okay.

[0369] The upper surface of the semiconductor substrate 450 preferably has a (110) surface. The on-state characteristics of the transistor 2200 can be improved.

[0370] The regions 472a and 472b are regions containing impurities that impart p-type conductivity. In this way, the transistor 2200 constitutes a p-channel transistor.

[0371] Note that the transistor 2200 is separated from adjacent transistors by a region 460 or the like. The region 460 is an insulating region.

[0372] The semiconductor device shown in FIG. 35 includes an insulator 464, an insulator 466, an insulator 468, and a conductive Conductor 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478 b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, and conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, and conductor 49 6c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, It includes an insulator 493, an insulator 495, and an insulator 494.

[0373] The insulator 464 is disposed on the transistor 2200. The insulator 466 is disposed on the 464. Insulator 468 is disposed on insulator 466. Insulator 493 is disposed on the insulator 468. Also, the transistor 2100 is disposed on the insulator 493. Also, an insulator 495 is disposed on the transistor 2100. Also, an insulator 494 is disposed on an insulator 495 .

[0374] The insulator 464 has an opening that reaches the region 472a, an opening that reaches the region 472b, and a conductive The openings also include openings that reach the conductors 480a and 454. The conductor 480b or the conductor 480c is embedded.

[0375] Insulator 466 also has an opening that reaches conductor 480a and an opening that reaches conductor 480b. The openings each have a mouth and an opening that reaches the conductor 480c. The conductive body 478a, the conductive body 478b, or the conductive body 478c is embedded therein.

[0376] Insulator 468 also has an opening that reaches conductor 478b and an opening that reaches conductor 478c. The openings each have a conductor 476a or a conductor 476b. It is embedded.

[0377] The insulator 493 has an opening overlapping with a channel formation region of the transistor 2100 and It has an opening that reaches the conductor 476a and an opening that reaches the conductor 476b. The openings are filled with a conductor 474a, a conductor 474b, or a conductor 474c. It is being done.

[0378] The conductor 474a may function as the gate electrode of the transistor 2100. For the conductor 474a, the description of the conductor 413 can be referred to.

[0379] The insulator 495 is also connected to one of the source and drain electrodes of the transistor 2100. An opening through conductor 416b, which is the transistor 210, to conductor 474b. An opening reaching the conductor 416a, which is the other of the source electrode or drain electrode of 0, and An opening reaching the conductor 404, which is the gate electrode of the transistor 2100, and a The openings are provided with a conductor 496a and a conductor 496b. b, the conductor 496c or the conductor 496d is embedded. The portion may also be connected through an opening in any of the components, such as the transistor 2100. There is a match.

[0380] The insulator 494 also has an opening that reaches the conductor 496a and an opening that reaches the conductor 496b and the conductor The opening extends to the conductive body 496d and the opening extends to the conductive body 496c. The conductive body 498a, the conductive body 498b, and the conductive body 498c are embedded in the respective portions. There are.

[0381] Insulator 464, insulator 466, insulator 468, insulator 493, insulator 495 and insulator The body 494 can be described as insulator 552 .

[0382] Insulator 464, Insulator 466, Insulator 468, Insulator 493, Insulator 495 or Insulator At least one of the bodies 494 is made of an insulator that has the function of blocking impurities such as hydrogen and oxygen. It is preferable to provide impurities such as hydrogen and oxygen near the transistor 2100. By disposing an insulator with a blocking function, the electrical The characteristics can be stabilized.

[0383] Conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b , conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor 474b , conductor 474c, conductor 496a, conductor 496b, conductor 496c, conductor 496d The conductors 498a, 498b, and 498c may include, for example, boron, nitrogen, and the like. element, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt Nickel, Copper, Zinc, Gallium, Yttrium, Zirconium, Molybdenum, Ruthenium Conductors containing one or more of aluminum, silver, indium, tin, tantalum and tungsten are used. It may be used in layers or laminates. For example, it may be an alloy or compound, such as aluminum. Conductors containing copper and titanium, conductors containing copper and manganese, indium Conductors containing titanium, tin and oxygen, and conductors containing titanium and nitrogen may also be used.

[0384] In the semiconductor device shown in FIG. 35, the structure of the transistor 2200 is the same as that shown in FIG. The transistor 491 and the transistor 492 may have the same structure as the transistor shown in FIG. The stator 491 and the transistor 492 are shown as having a fin-type structure.

[0385] In the semiconductor device shown in FIG. 35, the structure of the transistor 2200 is The transistor 491 and the transistor 492 may have the same structure as the transistor shown in FIG. The stator 491 and the transistor 492 are provided on a semiconductor substrate 400, which is an SOI substrate. This shows the case.

[0386] The semiconductor device shown in FIG. 35 is a semiconductor substrate on which a p-channel transistor is fabricated. Since an n-channel transistor is fabricated above the silicon nitride film, the area occupied by the device can be reduced. In other words, the degree of integration of the semiconductor device can be increased. Compared with the case where a p-channel transistor and a p-channel transistor are fabricated using the same semiconductor substrate, In this way, the manufacturing process can be simplified, and the productivity of semiconductor devices can be increased. In addition, the yield of the semiconductor device can be increased. The data is made up of an LDD (Lightly Doped Drain) region and a shallow trench structure. In some cases, complicated processes such as distortion design can be omitted. The productivity and yield of the photoresist can be increased compared to when it is manufactured using a semiconductor substrate. It may be possible to do this.

[0387] <CMOSアナログスイッチ> The circuit diagram shown in FIG. 34B shows the transistors 2100 and 2200. The figure shows a configuration in which the source and drain of each are connected. It can function as a so-called CMOS analog switch.

[0388] <Storage device 1> A memory device using a transistor according to one embodiment of the present invention and capable of storing stored contents even when power is not supplied An example of a semiconductor device (memory device) that can retain data and has no limit on the number of times it can be written is shown in Figure 3. Shown in 6.

[0389] The semiconductor device shown in FIG. 36A includes a transistor 3200 using a first semiconductor and a second semiconductor. The semiconductor device includes a transistor 3300 and a capacitor 3400. The transistor 3300 can be any of the transistors described above.

[0390] The transistor 3300 is preferably a transistor with low off-state current. For example, a transistor using an oxide semiconductor can be used as the transistor 300. The low off-state current of the STAR 3300 allows for long-term storage of specific nodes in the semiconductor device. It is possible to retain the stored contents, i.e., no refresh operation is required, and This allows for extremely low frequency refresh operations, resulting in low power consumption. It becomes a conductor device.

[0391] In FIG. 36A, a first wiring 3001 is electrically connected to the source of a transistor 3200. The second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300. The fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the source of the transistor 3300 are connected to each other. The other of the drains is electrically connected to one of the electrodes of the capacitor 3400 and is connected to the fifth wiring 3 005 is electrically connected to the other electrode of the capacitor 3400 .

[0392] The semiconductor device shown in FIG. 36A can hold the potential of the gate of the transistor 3200. This property makes it possible to write, store, and read information, as shown below. be.

[0393] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to The transistor 3300 is set to a potential at which it becomes conductive, thereby making the transistor 3300 conductive. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 3200 and The voltage is applied to a node FG electrically connected to one electrode of the capacitor 3400. A predetermined charge is applied to the gate of the transistor 3200 (write). The charges that give two potential levels (hereinafter referred to as low-level charge and high-level charge) ) is given. Then, the potential of the fourth wiring 3004 is given to the transistor. The potential is set to a level at which the transistor 3300 is in a non-conducting state. As a result, charge is held (retained) at node FG.

[0394] Since the off-state current of the transistor 3300 is small, the charge of the node FG is maintained for a long period of time. Retained.

[0395] Next, reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the second wiring The line 3002 takes on a potential corresponding to the amount of charge held in the node FG. If the transistor 3200 is an n-channel type, a high level voltage is applied to the gate of the transistor 3200. The apparent threshold voltage V under load th_H is a transistor 3200 The apparent threshold voltage V when a low-level charge is applied to the gate of th_L Here, the apparent threshold voltage is the voltage at which the transistor 3200 The potential of the fifth wiring 3005 required to make the fifth wiring 3005 in a "conductive state" is referred to as the potential of the fifth wiring 3005. Then, the potential of the fifth wiring 3005 is V th_H and V th_L The potential between For example, in a write operation, the charge applied to node FG can be determined by When a high level charge is applied to G, the potential of the fifth wiring 3005 becomes V0 ( >V th_H ), transistor 3200 is in a "conducting state." Meanwhile, node F When a low level charge is applied to G, the potential of the fifth wiring 3005 becomes V0 (< V th_L ), transistor 3200 remains in a "non-conducting state." Therefore, by determining the potential of the second wiring 3002, the data stored in the node FG can be read. It can be seen.

[0396] When memory cells are arranged in an array, the information of a desired memory cell is read out. In order to avoid reading information from other memory cells, The voltage at which transistor 3200 is in a "non-conducting state" regardless of the charge applied to the FG. Place, that is, V th_H A lower potential may be applied to the fifth wiring 3005. The voltage at which transistor 3200 is in a "conducting state" regardless of the charge applied to node FG is Place, that is, V th_L A higher potential may be applied to the fifth wiring 3005 .

[0397] <Semiconductor device structure 3> 37 is a cross-sectional view of the semiconductor device corresponding to FIG. 36(A). The device includes a transistor 3200, a transistor 3300, and a capacitor 3400. The transistor 3300 and the capacitor 3400 are connected to the upper side of the transistor 3200. The transistor 3300 is arranged in the same manner as the transistor 2100. The transistor 3200 may be the transistor shown in FIG. Please refer to the description of the transistor 2200. Note that in FIG. Although the case where the transistor 3200 is a p-channel transistor has been described, A channel transistor may also be used.

[0398] The transistor 3200 shown in FIG. 37 is a transistor using a semiconductor substrate 450. The transistor 3200 includes a region 472a in the semiconductor substrate 450 and a region 472b in the semiconductor substrate 450. The region 472b includes an insulator 462 and a conductor 454.

[0399] The semiconductor device shown in FIG. 37 includes an insulator 464, an insulator 466, an insulator 468, and a conductive Conductor 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478 b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, and conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, and conductor 49 6c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, It includes a conductor 498d, an insulator 493, an insulator 495, and an insulator 494.

[0400] The insulator 464 is disposed on the transistor 3200. The insulator 466 is disposed on the insulator 464. Insulator 468 is disposed on insulator 466. Insulator 493 is disposed on the insulator 468. Also, the transistor 3300 is disposed on the insulator 493. Also, an insulator 495 is disposed on the transistor 3300. Also, an insulator 494 is disposed on an insulator 495 .

[0401] The insulator 464 has an opening that reaches the region 472a, an opening that reaches the region 472b, and a conductive The openings also include openings that reach the conductors 480a and 454. The conductor 480b or the conductor 480c is embedded.

[0402] Insulator 466 also has an opening that reaches conductor 480a and an opening that reaches conductor 480b. The openings each have a mouth and an opening that reaches the conductor 480c. The conductive body 478a, the conductive body 478b, or the conductive body 478c is embedded therein.

[0403] Insulator 468 also has an opening that reaches conductor 478b and an opening that reaches conductor 478c. The openings each have a conductor 476a or a conductor 476b. It is embedded.

[0404] The insulator 493 has an opening overlapping with a channel formation region of the transistor 3300 and It has an opening that reaches the conductor 476a and an opening that reaches the conductor 476b. The openings are filled with a conductor 474a, a conductor 474b, or a conductor 474c. It is being done.

[0405] The conductor 474a may function as a bottom gate electrode of the transistor 3300. Alternatively, for example, applying a constant potential to the conductor 474a can The electrical properties of the capacitor 3300, such as the threshold voltage, may be controlled. The conductive body 474a is electrically connected to the conductive body 404, which is the top gate electrode of the transistor 3300. This can increase the on-state current of the transistor 3300. In addition, since the punch-through phenomenon can be suppressed, the transistor 330 This makes it possible to stabilize the electrical characteristics in the saturated region of 0.

[0406] The insulator 495 is connected to one of the source and drain electrodes of the transistor 3300. An opening through conductor 416b, which is the transistor 330, to conductor 474b. 4 through the conductor 416a, which is the other of the source electrode or drain electrode of 0, and the insulator 412. An opening reaching the overlying conductor 414 and the conductor that is the gate electrode of transistor 3300 404 and the other of the source electrode or drain electrode of the transistor 3300. and an opening through the conductor 416a, which is the opening, to the conductor 474c. The openings are provided with conductors 496a, 496b, 496c, and 496d. However, each opening is filled with a transistor 3300 or the like. This may be through an opening in any of the components.

[0407] In addition, the insulator 494 has an opening that reaches the conductor 496a and an opening that reaches the conductor 496b. a mouth, an opening that reaches conductor 496c, and an opening that reaches conductor 496d. In addition, the openings are provided with a conductor 498a, a conductor 498b, a conductor 498c, or A conductor 498d is embedded therein.

[0408] Insulator 464, Insulator 466, Insulator 468, Insulator 493, Insulator 495 or Insulator At least one of the bodies 494 is made of an insulator that has the function of blocking impurities such as hydrogen and oxygen. It is preferable to have impurities such as hydrogen and oxygen near the transistor 3300. By disposing an insulator with a blocking function, the electrical The characteristics can be stabilized.

[0409] As for materials that can be used for the conductor 498d, see the description of the conductor 480a, etc. It can be illuminated.

[0410] The source or drain of transistor 3200 is connected to conductor 480a and conductor 478a. , the conductor 476a, the conductor 474b, and the conductor 496c. The conductive material 416b is electrically connected to the source electrode or the drain electrode of the semiconductor device 300. The conductor 454, which is the gate electrode of the transistor 3200, is connected to the conductor 480c. via the conductor 478c, the conductor 476b, the conductor 474c, and the conductor 496d The conductor 416a, which is the other of the source electrode and the drain electrode of the transistor 3300, and Connect emotionally.

[0411] The capacitor 3400 is connected to the other of the source electrode and the drain electrode of the transistor 3300. The electrode 412 is electrically connected to the conductor 414, and the insulator 412. 12 can be formed in the same process as the gate insulator of the transistor 3300, and therefore productivity is improved. In some cases, it is preferable to use a transistor 3 as the conductor 414. By using a layer formed through the same process as the gate electrode of 300, productivity can be improved. This may be preferable in some cases.

[0412] For other structures, please refer to the descriptions in Figure 35 etc. as appropriate. In FIG. 35, the transistor 2200 is a p-channel transistor. However, the transistor 3200 may be an n-channel transistor.

[0413] 37, the structure of the transistor 3200 is the same as that of the transistor 4 shown in FIG. The transistor 491 and the transistor 492 shown in FIG. The transistor 492 is shown to have a fin-type structure.

[0414] 37, the structure of the transistor 3200 is the same as that of the transistor 4 shown in FIG. The structure of the transistor 491 and the transistor 492 shown in FIG. The transistor 492 is shown to be provided on a semiconductor substrate 450, which is an SOI substrate. .

[0415] <Storage device 2> The semiconductor device shown in FIG. 36B is different from the semiconductor device shown in FIG. 36A in that it does not include the transistor 3200. This is different from the semiconductor device shown in FIG. This allows information to be written and retained.

[0416] How to read data from the semiconductor device shown in FIG. When the capacitor 3300 is brought into a conductive state, the third wiring 3003 and the capacitor element 340, which are in a floating state, 0 is electrically connected, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is The potential of one of the electrodes of the capacitor 3400 (or the charge stored in the capacitor 3400) and take different values.

[0417] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the The capacitance component of the third wiring 3003 is CB, and the capacitance of the third wiring 3003 before the charge is redistributed is If the potential of the third wiring 3003 after the charge is redistributed is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB ×VB0+C×V) / (CB+C). Therefore, the state of the memory cell is The potential of one of the electrodes of the element 3400 takes two states: V1 and V0 (V1>V0). and the potential of the third wiring 3003 when the potential V1 is maintained (=(CB×VB0+C× V1) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is maintained. =(CB×VB0+C×V0) / (CB+C)).

[0418] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. This can be done.

[0419] In this case, the first semiconductor is applied to a driving circuit for driving the memory cell. A transistor in which a second semiconductor is applied as the transistor 3300. may be stacked on the drive circuit.

[0420] The semiconductor device described above includes a transistor using an oxide semiconductor and having low off-state current. By using this function, it is possible to retain the memory contents for a long period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, a semiconductor device with low power consumption can be realized. Even if the potential is fixed, it is possible to store it for a long period of time. The content can be preserved.

[0421] Furthermore, since the semiconductor device does not require a high voltage to write information, deterioration of the elements does not occur. For example, unlike conventional non-volatile memory, the flow of electrons to the floating gate Since there is no injection or extraction of electrons from the floating gate, there is no degradation of the insulator. That is, the semiconductor device according to one embodiment of the present invention does not have the same problem as the conventional nonvolatile memory. There is no limit to the number of times that data can be rewritten, which is a problem in the past, and reliability has improved dramatically. Furthermore, information is written depending on whether the transistor is conductive or non-conductive. This allows for high-speed operation.

[0422] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0423] (Fourth embodiment) An imaging device according to one aspect of the present invention will be described below.

[0424] <Imaging device> 38A is a plan view showing an example of an imaging device 200 according to one aspect of the present invention. The device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and a peripheral The pixel section 210 has a pixel circuit 270, a peripheral circuit 280, and a peripheral circuit 290. It has a plurality of pixels 211 arranged in a matrix of columns (p and q are integers of 2 or more). The peripheral circuits 260, 270, 280, and 290 are respectively The pixel 211 is connected to the plurality of pixels 211 and has a function of supplying signals for driving the plurality of pixels 211. In this specification, the peripheral circuits 260, 270, 280, and The peripheral circuit 290 and the like may be referred to as the "peripheral circuit" or the "drive circuit." For example, peripheral circuit 260 can be considered a part of the peripheral circuit.

[0425] The imaging device 200 preferably includes a light source 291. The light source 291 emits detection light. It can emit P1.

[0426] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be fabricated on the same substrate on which the pixel section 210 is formed. Also, semiconductor devices such as IC chips may be used for part or all of the peripheral circuits. The peripheral circuits are peripheral circuits 260, 270, 280, and 29. One or more of the 0s may be omitted.

[0427] Also, as shown in FIG. 38(B), in the pixel section 210 of the imaging device 200, The pixels 211 may be arranged at an angle. By arranging the pixels 211 at an angle, the pixel This allows the pixel interval (pitch) in the column direction to be shortened. This can further improve the quality of imaging in the imaging device.

[0428] <Pixel configuration example 1> One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and each The sub-pixel 212 is combined with a filter (color filter) that transmits light of a specific wavelength band. By doing so, it is possible to obtain information for realizing a color image display.

[0429] FIG. 39(A) is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in FIG. 39(A) is provided with a color filter that transmits the red (R) wavelength band. The sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") transmits light in the green (G) wavelength band. A sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") provided with a color filter corresponding to the and blue (B) wavelength bands. The subpixel 212 functions as a photosensor. It is possible.

[0430] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 2 31, and are electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The subpixels 212R, 212G, and 212B are each connected to an independent wiring 2 53. In this specification, for example, the pixel connected to the n-th row pixel 211 is The wiring 248 and the wiring 249 are respectively referred to as wiring 248[n] and wiring 249[n]. For example, the wiring 253 connected to the pixel 211 in the m-th column is referred to as wiring 253[m In FIG. 39A, the sub-pixel 212 of the pixel 211 in the m-th column is written as The wiring 253 connected to R is the wiring 253[m]R, and the wiring 253 connected to the subpixel 212G is the wiring 253[m]R. The wiring 253[m]G and the wiring 253 connected to the subpixel 212B are referred to as wiring 253[m]B. The subpixel 212 is electrically connected to the peripheral circuit via the wiring.

[0431] In addition, the imaging device 200 has color filters 211 adjacent to each other that transmit the same wavelength band. The sub-pixels 212 provided with the filters are electrically connected to each other via the switches. In Figure 39(B), the matrix is ​​arranged in n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q). The sub-pixel 212 of the pixel 211 arranged in the n+1th row and the mth column adjacent to the pixel 211 is 39B shows an example of connection of sub-pixels 212 of a pixel 211 placed in the nth row. The sub-pixel 212R arranged in the mth column and the sub-pixel 212R arranged in the n+1th row and the mth column are switched. The sub-pixels 212G arranged in the nth row and the mth column are connected via the n+ The sub-pixels 212G arranged in the first row and the mth column are connected via the switches 202. The sub-pixels 212B arranged in the nth row and the mth column and the sub-pixels 212B arranged in the n+1th row and the mth column are switched. 203.

[0432] The color filters used for the subpixel 212 are limited to red (R), green (G), and blue (B). color filters that transmit cyan (C), yellow (Y) and magenta (M) light, respectively. A sub-pixel for detecting light of three different wavelength bands may be used in one pixel 211. By providing the element 212, a full color image can be obtained.

[0433] Alternatively, color filters that transmit red (R), green (G), and blue (B) light are used. In addition to the sub-pixel 212, a color filter that transmits yellow (Y) light is provided. Alternatively, a pixel 211 having sub-pixels 212 may be used. The sub-pixel 212 is provided with a color filter that transmits light of blue (Y) and magenta (M). In addition, a pixel 212 having a sub-pixel 212 provided with a color filter that transmits blue (B) light is 11 may be used. One pixel 211 may have four sub-pixels that detect light in different wavelength bands. By providing 212, the color reproducibility of the acquired image can be further improved.

[0434] Also, for example, in FIG. 39(A), the sub-pixel 212 for detecting the red wavelength band and the sub-pixel 213 for detecting the green wavelength band are The ratio of the number of sub-pixels 212 that detect the long wavelength band and the number of sub-pixels 212 that detect the blue wavelength band (or light receiving area ratio) does not have to be 1:1:1. For example, The ratio of red to green to blue may be set to 1:2:1. Alternatively, the ratio of the number of pixels ( The light receiving area ratio may be red:green:blue=1:6:1.

[0435] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that the number is two or more. For example, by providing two or more sub-pixels 212 that detect the same wavelength band, redundancy can be increased and imaging can be performed more efficiently. The reliability of the device 200 can be improved.

[0436] In addition, IR (Infrared) filters absorb or reflect visible light and transmit infrared light. ) filter, an imaging device 200 that detects infrared light can be realized.

[0437] In addition, ND (Neutral Density) filters (light-reducing filters) are used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, The dynamic range of the device can be increased.

[0438] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described using the cross-sectional view of the pixel 211. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 40(A), a lens 255 and a filter 256 are formed in the pixel 211. 54 (filter 254R, filter 254G and filter 254B), and pixel circuit A structure can be adopted in which light 256 is incident on the photoelectric conversion element 220 through 230 or the like.

[0439] However, as shown in the area surrounded by the dashed line, part of the light 256 indicated by the arrow is connected to the wiring 257. Therefore, as shown in Figure 40(B), the light is blocked by a part of the A lens 255 and a filter 254 are arranged on the photoelectric conversion element 220 side. A structure in which the light 256 is efficiently received by the photoelectric conversion element 220 is preferable. By making the light incident on the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity can be provided. This can be done.

[0440] As the photoelectric conversion element 220 shown in FIG. 40, a pn-type junction or a pin-type junction is formed. Alternatively, a photoelectric conversion element may be used.

[0441] The photoelectric conversion element 220 is made of a material having a function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating charges may be: Selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy There is money etc.

[0442] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element with optical absorption coefficient over a wide wavelength range, including X-rays and gamma rays 220 can be achieved.

[0443] Here, one pixel 211 included in the imaging device 200 is added to a sub-pixel 212 shown in FIG. In addition, there may be a subpixel 212 having a first filter.

[0444] <Pixel configuration example 2> Below, a transistor using silicon, a transistor using an oxide semiconductor, and An example of configuring a pixel using the above will be described.

[0445] 41(A) and 41(B) are cross-sectional views of elements constituting the imaging device. The imaging device shown in FIG. 1 includes a silicon transistor 300 formed on a silicon substrate 300. 51, a transistor 3 using an oxide semiconductor stacked on the transistor 351 52 and transistor 353, and a photodiode provided on the silicon substrate 300. Each transistor and photodiode 360 ​​is connected to a different plug 37. 0 and the wiring 371. Also, the anode of the photodiode 360 361 has an electrical connection with plug 370 via low resistance region 363 .

[0446] The imaging device also includes a transistor 351 and a photodiode 352 provided on a silicon substrate 300. A layer 310 having a diode 360 ​​and a layer 371 provided in contact with the layer 310. 320, and a transistor 352 and a transistor 353 are provided in contact with the layer 320. a layer 330 having a wiring 372 and a wiring 373 provided in contact with the layer 330; It is equipped with 340.

[0447] In the example of the cross-sectional view of FIG. 41(A), transistor 3 is formed on a silicon substrate 300. The light receiving surface of the photodiode 360 ​​is located on the opposite side to the surface on which the photodiode 51 is formed. This configuration ensures an optical path without being affected by various transistors and wiring. Therefore, it is possible to form pixels with a high aperture ratio. The light-receiving surface of the gate 360 ​​may be the same as the surface on which the transistor 351 is formed.

[0448] When a pixel is configured using a transistor, the layer 310 is formed by a layer having a transistor. Alternatively, the layer 310 may be omitted and the pixel may be formed only by a transistor. stomach.

[0449] If a pixel is configured using a transistor, the layer 330 may be omitted. An example of a cross-sectional view in which 30 is omitted is shown in FIG.

[0450] The silicon substrate 300 may be an SOI substrate. Instead of germanium, silicon germanium, silicon carbide, gallium arsenide, and arsenic carbide, a substrate having aluminum gallium, indium phosphide, gallium nitride or an organic semiconductor; It can also be used.

[0451] Here, a layer 310 having a transistor 351 and a photodiode 360, An insulator 380 is provided between the layer 330 having the transistor 352 and the layer 330 having the transistor 353. However, the location of the insulator 380 is not limited.

[0452] The hydrogen in the insulator provided near the channel formation region of the transistor 351 is This has the effect of terminating dangling bonds and improving the reliability of the transistor 351. On the other hand, the water in the insulator provided near the transistor 352 and the transistor 353 is The element is one of the factors that generate carriers in the oxide semiconductor. This may cause a decrease in reliability of the transistor 352 and the transistor 353. Therefore, a transistor using an oxide semiconductor is placed on top of a transistor using a silicon semiconductor. When stacking the sintered bodies, an insulator 380 having a function of blocking hydrogen is provided between the sintered bodies. By confining hydrogen below the insulator 380, the transistor The reliability of the capacitor 351 can be improved. Since hydrogen diffusion to the layer above the body 380 can be suppressed, the transistor 352 and the transistor The reliability of the transistor 353 and the like can be improved.

[0453] For the insulator 380, see, for example, the description of the insulator 408.

[0454] In the cross-sectional view of FIG. 41(A), a photodiode 360 ​​provided in the layer 310, The transistors provided in the layer 330 can be formed to overlap with each other. This allows for an increase in the degree of integration of elements, which in turn allows for an increase in the resolution of the imaging device.

[0455] Also, as shown in FIG. 42(A1) and FIG. 42(B1), a part or all of the imaging device 42(A1) shows the imaging device in the direction of the dashed line X1-X2 in the figure. FIG. 42(A2) shows the state where the lens is bent along the dashed line X1- in FIG. 42(A3) is a cross-sectional view of the portion indicated by X2. FIG. 10 is a cross-sectional view of the portion indicated by -Y2.

[0456] FIG. 42(B1) shows the case where the imaging device is bent in the direction of the dashed line X3-X4 in the same figure, and The figure shows a state where the lens is bent in the direction of the dashed line Y3-Y4 in the figure. FIG. 42(B3) is a cross-sectional view of the portion indicated by the dashed line X3-X4 in FIG. 42(B1) is a cross-sectional view of a portion indicated by a dashed line Y3-Y4 in FIG. 42(B1).

[0457] By curving the imaging device, it is possible to reduce field curvature and astigmatism. This makes it possible to facilitate the optical design of lenses and the like that are used in combination with the imaging device. Since the number of lenses required for aberration correction can be reduced, it is possible to miniaturize electronic devices using imaging devices. It is possible to realize a lighter and more compact camera. It is also possible to improve the quality of the captured image. do.

[0458] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0459] (Embodiment 5) In this embodiment, a semiconductor device including the above-described transistor and the above-described memory device is Explain about the CPU.

[0460] <cpu> FIG. 43 is a block diagram showing the configuration of an example of a CPU that uses the above-mentioned transistor in part. is.

[0461] The CPU shown in FIG. 43 includes an ALU 1191 (Arithmetic and logic unit) on a board 1190. tic logic unit, arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. 1199 and the ROM interface 1189 may be provided on separate chips. The CPU shown in FIG. 43 is merely an example of a simplified configuration, and an actual CPU may differ from the For example, the CPU or the arithmetic circuit shown in Figure 43 A configuration including a path is considered to be one core, and multiple such cores are included, and each core operates in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit and data bus is , for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0462] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, Interrupt controller 1194, register controller 1197, timing controller It is entered into La1195.

[0463] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to trigger the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it accordingly. Generates an address and reads or writes register 1196 depending on the CPU state. .

[0464] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and and generates signals that control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generator supplies an internal clock signal to the various circuits.

[0465] In the CPU shown in FIG. 43, a memory cell is provided in the register 1196. The above-mentioned transistors and memory devices can be used as memory cells of the memory cell 1196. Cut.

[0466] In the CPU shown in FIG. 43, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 6, data is held by a flip-flop or a capacitance element. If data is held by a flip-flop, the data is held by the flip-flop. If selected, the power supply voltage is supplied to the memory cells in the register 1196 . If data retention in the capacitor is selected, data rewriting to the capacitor is This allows the supply of power supply voltage to the memory cells in register 1196 to be stopped.

[0467] FIG. 44 shows a circuit diagram of a storage element 1200 that can be used as a register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is turned off, and a power supply A circuit 1202, a switch 1203, and a switch 1204 that prevent the stored data from volatilizing when cut off. 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1201. 210. The memory element 1200 may include a diode, a resistor, etc., as needed. , and may further include other elements such as an inductor.

[0468] Here, the above-described memory device can be used for the circuit 1202. When the supply of power supply voltage to GND is stopped, the gate of transistor 1209 in circuit 1202 is GND (0V) or a potential that turns off the transistor 1209 is continuously input. For example, if the gate of the transistor 1209 is grounded via a load such as a resistor, do.

[0469] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first transistor 1214 of the switch 1203 is used. The terminal corresponds to one of the source and drain of the transistor 1213, and the first terminal of the switch 1203. The terminal 2 corresponds to the other of the source and drain of the transistor 1213, and the terminal 3 corresponds to the other of the source and drain of the switch 1203. The first terminal and the second terminal are connected by a control signal RD input to the gate of the transistor 1213. Conduction or non-conduction between the terminals of (i.e., the conductive or non-conductive state of transistor 1213) The first terminal of the switch 1204 is connected to the source of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the transistor 1214. The switch 1204 connects the input to the gate of the transistor 1214. The control signal RD determines whether the first terminal and the second terminal are electrically connected or disconnected (i.e., , the conductive or non-conductive state of transistor 1214) is selected.

[0470] One of the source and drain of the transistor 1209 is connected to one of the pair of electrodes of the capacitor 1208. The gate of the transistor 1210 is electrically connected to one of the gates of the transistor 1210. The part is designated as node M2. One of the source and drain of the transistor 1210 is connected to the low power supply voltage. The other is electrically connected to a wiring (for example, a GND line) that can supply a voltage. The first terminal of the transistor 1203 (one of the source and drain of the transistor 1213) is electrically connected to the The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the other terminal of the switch 1204 (the source and drain of the transistor 1214) The second terminal of the switch 1204 (the first terminal of the transistor 1214) is electrically connected to the The other of the source and drain) is electrically connected to the wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (as well as the source and drain of the transistor 1213) the first terminal of the switch 1204 (one of the source and drain of the transistor 1214) the input terminal of the logic element 1206 and one of the pair of electrodes of the capacitor 1207. , are electrically connected. Here, the connection point is referred to as node M1. The other electrode of the pair may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a The pair of electrodes of the capacitor 1208 are electrically connected to a wiring (for example, a GND line). The other terminal may be configured to receive a constant potential. For example, a low power supply potential (GND The capacitor element 12 may be configured to receive a high power supply potential (VDD, etc.) or a high power supply potential (VDD, etc.). The other of the pair of electrodes 08 is connected to a wiring (e.g., GN D line).

[0471] The capacitors 1207 and 1208 are formed by using parasitic capacitances of transistors and wirings. It is also possible to omit this by actively using

[0472] A control signal WE is input to the gate of the transistor 1209. and the switch 1204 is connected between the first terminal and the second terminal by a control signal RD that is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal of one switch is selected. When the first and second terminals of the other switch are in a conductive state, the first and second terminals of the other switch are in a non-conductive state. It becomes a state.

[0473] The other of the source and drain of the transistor 1209 is connected to a data terminal of the circuit 1201. In FIG. 44, the signal output from the circuit 1201 is The example shown is input to the other of the source and drain of the transistor 1209. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and the inverted signal is output via the circuit 1220. and input to the circuit 1201.

[0474] In FIG. 44, the second terminal of the switch 1203 (the source of the transistor 1213) The signal output from the other drain is passed through the logic element 1206 and the circuit 1220. Although an example of inputting the signal to the circuit 1201 is shown, this is not limiting. The signal output from the other of the source and drain of the transistor 1213 is It may be input to the circuit 1201 without being inverted. For example, If there is a node that holds a signal whose logical value is the inverse of the signal input from the input terminal, In this case, the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) can be input to the node.

[0475] In addition, in FIG. 44, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are made of a film or a substrate 11 made of a semiconductor other than an oxide semiconductor. For example, a transistor having a channel formed in a silicon film or The memory element may be a transistor in which a channel is formed in a silicon substrate. All the transistors used in the element 1200 are transistors whose channels are formed of oxide semiconductors. Alternatively, the memory element 1200 may be implemented by any other element than the transistor 1209. The other transistors may include a transistor in which the channel is formed of an oxide semiconductor. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. The transistor may also be a transistor that is

[0476] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0477] In the semiconductor device according to one embodiment of the present invention, while power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0478] Further, a transistor whose channel is formed in an oxide semiconductor has an extremely small off-state current. For example, the off-state current of a transistor whose channel is formed in an oxide semiconductor is The off-state current is significantly lower than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, the memory element 12 Even when power supply voltage is not supplied to 00, the signal held in the capacitor 1208 is retained for a long period of time. In this way, the memory element 1200 can maintain its stored contents (data) even when the supply of power supply voltage is stopped. It is possible to hold the data.

[0479] In addition, by providing the switches 1203 and 1204, the precharge Since the memory element is characterized by performing the following operation, after the power supply voltage is supplied again, the circuit 1201 This can shorten the time it takes to restore the original data.

[0480] In the circuit 1202, the signal held by the capacitor 1208 is transferred to the transistor. Therefore, the supply of the power supply voltage to the memory element 1200 is restarted. After the capacitor 1208 is opened, the signal held by the capacitor 1208 is transferred to the transistor 1210 (conducting state or non-conducting state) and can be read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original The signal can be read out accurately.

[0481] Such a storage element 1200 may be a register or cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one of the components of the processor, In addition, power can be stopped for a short period of time in multiple logic circuits, reducing power consumption. can be suppressed.

[0482] Although the memory element 1200 has been described as being used in a CPU, the memory element 1200 may also be used in a DSP. (Digital Signal Processor), Custom LSI, PLD(P LSIs such as programmable logic devices, RF (Radio It can also be applied to (frequency) devices.

[0483] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0484] (Sixth embodiment) A display device according to one embodiment of the present invention will be described below with reference to FIGS. 45 and 46. do.

[0485] <Display device> Display elements used in display devices include liquid crystal elements (also called liquid crystal display elements), light-emitting elements, The light-emitting element can be a light-emitting element that emits current or voltage. This category includes elements whose brightness is controlled by the These include fluoroluminescence, organic electroluminescence (EL), etc. The display devices using EL elements (EL display devices) and the display devices using liquid crystal elements (LCD devices) are This section explains the display device.

[0486] The display device described below is a panel in which a display element is sealed, and a display device in which a display element is sealed. This includes modules that have ICs, including controllers, mounted on them.

[0487] Moreover, the display device described below refers to an image display device or a light source (including a lighting device). Also, connectors such as FPC, modules with TCP attached, and TCP with plugs A module or display element with a printed wiring board is fitted with an IC (integrated circuit) by the COG method. All directly mounted modules are also included in the display device.

[0488] 45A and 45B are diagrams illustrating an example of an EL display device according to one embodiment of the present invention. 45(B) is a top view showing the entire EL display device. FIG. 45(C) is a cross section of the MN corresponding to a part of the dashed line MN in FIG. 45(B). do.

[0489] FIG. 45(A) is an example of a circuit diagram of a pixel used in an EL display device.

[0490] In this specification, the terms "active elements (transistors, diodes, etc.)" and "passive elements" are used interchangeably. For all terminals of elements (capacitance elements, resistance elements, etc.), the connection destination must be specified. Even if the invention is not so simple, a person skilled in the art may be able to construct one aspect of the invention. Even if the connection destination is not specified, one aspect of the invention can be said to be clear. When the content of the above is described in this specification, etc., one aspect of the invention that does not specify a connection destination is the present invention. In some cases, it may be possible to determine that the information is written in the detailed instructions, etc. In particular, If multiple locations are expected, there is no need to limit the connection destination of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements) By specifying the connection destinations for only some of the terminals of a device (such as a semiconductor device), This may constitute an aspect of the invention.

[0491] In this specification, if at least the connection destination of a certain circuit is specified, the circuit is considered to be a A person skilled in the art may be able to identify the invention. A person skilled in the art may be able to identify an invention by simply specifying its functions. In other words, if the function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in this specification, etc. Therefore, even if the function of a circuit is not specified, if the connection destination is specified, it can be considered as an invention. The invention is disclosed as an embodiment and can be implemented as an embodiment of the invention. Regarding a certain circuit, even if the connection destination is not specified, specifying the function is considered as one aspect of the invention. and can constitute one aspect of the invention.

[0492] The EL display device shown in FIG. 45(A) includes a switch element 743, a transistor 741, and The pixel includes a capacitor 742 and a light-emitting element 719 .

[0493] Note that FIG. 45(A) is an example of a circuit configuration, so if a transistor is added, Conversely, at each node in FIG. 45(A), it is possible to It is also possible to avoid adding switches, passive elements, etc.

[0494] The gate of the transistor 741 is connected to one end of the switch element 743 and one end of the capacitance element 742. The source of the transistor 741 is electrically connected to the other electrode of the capacitor 742. The transistor is electrically connected to one electrode of the light emitting element 719. The drain of the switch element 741 is supplied with a power supply potential VDD. The other end of the switch element 743 is connected to a signal line The other electrode of the light emitting element 719 is electrically connected to the light emitting element 744. A constant potential is applied to the other electrode of the light emitting element 719. The constant potential is the ground potential GND or a potential lower than that.

[0495] It is preferable to use a transistor as the switch element 743. This allows the pixel area to be reduced, resulting in an EL display device with high resolution. In addition, the switching element 743 is a transistor manufactured through the same process as the transistor 741. The use of transistors can improve the productivity of EL display devices. 41 and / or the switch element 743, for example, the above-mentioned transistor is applied. It is possible.

[0496] 45(B) is a top view of the EL display device. The EL display device includes a substrate 700 and a substrate 750, a sealing material 734, a driving circuit 735, a driving circuit 736, a pixel 737, and F The sealing material 734 covers the pixels 737, the driving circuit 735, and the driving circuit 736. The driving circuit 73 is disposed between the substrate 700 and the substrate 750 so as to surround the path 736. 5 and / or the driving circuit 736 may be disposed outside the sealing material 734 .

[0497] FIG. 45(C) is a cross section of the EL display device corresponding to a part of the dashed line MN in FIG. 45(B). Figure.

[0498] In FIG. 45C, a conductor 704a and a conductor Insulator 712a on insulator 704a, insulator 712b on insulator 712a, and insulator 71 2b and overlapping with the conductor 704a, and a conductor 71 6a and conductor 716b, and on the semiconductor 706, on the conductor 716a and conductor 716b. Insulator 718a on top, insulator 718b on insulator 718a, and insulator 718b on insulator 718b. and a conductor 714a that is on the insulator 718c and overlaps the semiconductor 706. The structure of the transistor 741 is an example, and the structure shown in FIG. It may have a different structure.

[0499] Therefore, in the transistor 741 shown in FIG. 45C, the conductor 704a is The insulators 712a and 712b function as gate insulators. The conductor 716a functions as a source electrode, and the conductor 716b functions as a drain electrode. The insulators 718a, 718b, and 718c function as insulator electrodes. The conductor 714a functions as a gate insulator, and the conductor 714b functions as a gate electrode. Note that the electrical characteristics of the semiconductor 706 may change when exposed to light. At least one of the conductor 704a, the conductor 716a, the conductor 716b, and the conductor 714a It is preferable that the film has a light-blocking property.

[0500] The interface between the insulator 718a and the insulator 718b is shown by a broken line. For example, the insulators 718a and 718b may not be clearly defined. Therefore, when the same type of insulator is used, it may be difficult to distinguish between them depending on the observation method. .

[0501] In FIG. 45C, a conductor 704b and a conductor 704b are provided on a substrate as a capacitor 742. b, insulator 712a on insulator 712a, and insulator 712b on insulator 712b. A conductor 716a overlapping the conductor 704b, an insulator 718a on the conductor 716a, and an insulating Insulator 718b on insulator 718a, insulator 718c on insulator 718b, and insulator 71 conductor 714b on the substrate 8c and overlapping with the conductor 716a, In the overlapping region of the conductor 714b, a portion of the insulator 718a and the insulator 718b is removed. The structure shown is:

[0502] In the capacitor 742, the conductor 704b and the conductor 714b function as one electrode. The conductor 716a serves as the other electrode.

[0503] Therefore, the capacitor 742 can be formed using the same film as that of the transistor 741. It is also preferable that the conductors 704a and 704b are made of the same type of conductor. In this case, the conductor 704a and the conductor 704b can be formed through the same process. In addition, the conductor 714a and the conductor 714b are preferably made of the same type of conductor. In this case, the conductor 714a and the conductor 714b can be formed through the same process. do.

[0504] The capacitor 742 shown in FIG. 45C has a large capacitance per occupied area. Therefore, the EL display device shown in FIG. 45(C) has high display quality. The capacitor 742 shown in FIG. 1 is formed by thinning the overlapping area of ​​the conductor 716a and the conductor 714b. Therefore, the insulator 718a and the insulator 718b have a structure in which a part of the insulator 718a and the insulator 718b are removed. The capacitor according to one embodiment is not limited to this. A part of the insulator 718c is removed to thin the overlapping area of ​​the conductor 714b. It is acceptable to have

[0505] An insulator 720 is provided over the transistor 741 and the capacitor 742. The insulator 720 extends to the conductor 716a, which serves as the source electrode of the transistor 741. The insulator 720 may have an opening. A conductor 781 is disposed on the insulator 720. 81 may be electrically connected to the transistor 741 through an opening in the insulator 720 .

[0506] A partition 784 having an opening that reaches the conductor 781 is arranged over the conductor 781 . A light-emitting layer 782 is disposed over the partition wall 784 and is in contact with the conductor 781 through the opening of the partition wall 784. A conductor 783 is disposed over the light-emitting layer 782. The overlapping region of the light-emitting element 719 and the conductor 783 becomes the light-emitting element 719 .

[0507] Up to this point, an example of an EL display device has been explained. Next, an example of a liquid crystal display device will be explained. Reveal.

[0508] 46(A) is a circuit diagram showing an example of the configuration of a pixel of a liquid crystal display device. 751, a capacitor 752, and an element ( The liquid crystal element 753 is also included.

[0509] In the transistor 751, one of the source and the drain is electrically connected to a signal line 755. , the gate is electrically connected to the scan line 754 .

[0510] One electrode of the capacitor 752 is connected to the other of the source and drain of the transistor 751. The other electrode is electrically connected to a wiring that supplies a common potential.

[0511] In the liquid crystal element 753, one electrode is connected to the other of the source and drain of the transistor 751. The other electrode is electrically connected to a wiring that supplies a common potential. The common potential applied to the wiring to which the other electrode of the capacitor 752 is electrically connected is The potential applied to the other electrode of the liquid crystal element 753 may be different from the common potential applied to the other electrode of the liquid crystal element 753 .

[0512] The liquid crystal display device will be described assuming that the top view is the same as that of the EL display device. A cross-sectional view of the liquid crystal display device corresponding to the dashed line MN is shown in FIG. In this case, the FPC 732 is connected to the wiring 733a via the terminal 731. 33a is a conductor of the same type as the conductor or semiconductor that constitutes the transistor 751. Alternatively, a semiconductor may be used.

[0513] For the transistor 751, refer to the description of the transistor 741. For the capacitor 752, refer to the description of the capacitor 742. 5(C) shows the structure of the capacitor element 752 corresponding to the capacitor element 742, but is not limited to this. do not have.

[0514] Note that when an oxide semiconductor is used as the semiconductor of the transistor 751, the off-state current is extremely small. Therefore, the charge held in the capacitor 752 can be It is difficult to leak and can maintain the voltage applied to the liquid crystal element 753 for a long period of time. Therefore, when displaying a moving image or a still image with little movement, the transistor 751 is turned off. By doing so, power for operating the transistor 751 is not required, and power consumption is low. In addition, the area occupied by the capacitor 752 can be reduced. Therefore, it is possible to provide a liquid crystal display device with a high aperture ratio or a high-definition liquid crystal display device. .

[0515] An insulator 721 is provided over the transistor 751 and the capacitor 752. The insulator 721 has an opening that reaches the transistor 751. On the insulator 721, A conductor 791 is disposed. The conductor 791 is connected to the transistor through an opening in the insulator 721. 751.

[0516] An insulator 792 functioning as an alignment film is disposed over the conductor 791. A liquid crystal layer 793 is disposed thereon. An insulating layer functioning as an alignment film is disposed on the liquid crystal layer 793. 794 is disposed on the insulating material 794. A spacer 795 is disposed on the insulating material 794. A conductor 796 is disposed on the substrate 75 and the insulator 794. 97 will be placed.

[0517] By using the above-described structure, a display device having a capacitor element with a small occupation area can be provided. Alternatively, a display device with high display quality can be provided. It is possible to provide a thin display device.

[0518] For example, in this specification, a display element, a display device which is a device having a display element, a light-emitting device, The light-emitting device, which is a device having an element and a light-emitting element, can be used in various forms, or A display element, a display device, a light-emitting element, or a light-emitting device can have various elements. For example, light emitting diodes (LEDs) that are white, red, green, or blue tting diode), transistor (transistor that emits light according to the current), electron Emission element, liquid crystal element, electronic ink, electrophoretic element, grating light valve (GLV) ), plasma display panels (PDP), MEMS (microelectromechanical systems) Display elements using the Digital Micromirror Device (DMD), DM S (Digital Micro Shutter), IMOD (Interference Modulator) shutter-type MEMS display elements, optical interference-type MEMS display elements, Electrowetting elements, piezoelectric ceramic displays, and carbon nanotubes In addition to these, it has at least one electric or magnetic display element. The display medium has a contrast, brightness, reflectance, transmittance, etc. that change depending on the effect. Good too.

[0519] An example of a display device using an EL element is an EL display. An example of a display device using electrons is a field emission display (FED). or SED type flat panel display (SED: Surface-conduction LCDs are liquid crystal displays. An example of a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display). Spray, reflective LCD, direct-view LCD, projection LCD ) Display using electronic ink, electronic liquid powder, or electrophoretic elements An example of such a device is electronic paper. In order to realize a liquid crystal display, a part or all of the pixel electrodes are used as reflective electrodes. For example, a part or all of the pixel electrodes may be made of aluminum. In this case, the SRA may be provided under the reflective electrode. It is also possible to provide a memory circuit such as M. This further reduces power consumption. It is possible.

[0520] When using an LED, graphene or graphene is placed under the LED electrode or nitride semiconductor. Graphene and graphite can be arranged in layers to form a multilayer film. In this way, by providing graphene or graphite, it is possible to form nitride on it. This makes it easy to form films of semiconductors, such as crystalline n-type GaN semiconductors. Furthermore, a p-type GaN semiconductor with crystals is placed on top of it to form an LED. It is possible to form a crystalline n-type GaN semiconductor with graphene or graphite. An AlN layer may be provided. The GaN semiconductor in the LED is formed by MOCVD. However, by providing graphene, the GaN semiconductor of the LED may be It is also possible to form the film by sputtering.

[0521] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0522] (Embodiment 7) In this embodiment, an electronic device or the like equipped with a semiconductor device according to one embodiment of the present invention will be described. Reveal.

[0523] <Electronic equipment> The semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, a recording medium, and the like. Image playback device (typically DVD: Digital Versatile Disk) c) a device having a display that can play back a recording medium such as a In addition, electronic devices in which the semiconductor device according to one embodiment of the present invention can be used As such, mobile phones, portable game consoles, portable data terminals, e-book terminals, video cameras cameras such as digital still cameras, goggle-type displays (head-mounted displays), Play), navigation systems, sound reproduction equipment (car audio, digital audio copiers, facsimiles, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. show.

[0524] FIG. 47A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display 904, microphone 905, speaker 906, operation keys 907, stylus 90 8. The portable game machine shown in FIG. 47(A) has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. stomach.

[0525] FIG. 47(B) shows a portable data terminal, which includes a first housing 911, a second housing 912, a first display unit The first display unit 91 has a first display unit 913, a second display unit 914, a connection unit 915, an operation key 916, etc. 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. The display may be switched according to the angle between the first display unit 91 and the second display unit 912. At least one of the first display unit 913 and the second display unit 914 is provided with a function as a position input device. A display device may be used. The function as a position input device may be implemented by adding a Alternatively, the function as a position input device can be added by providing a touch panel. Alternatively, a photoelectric conversion element, also called a photosensor, may be provided in the pixel portion of the display device. It is possible.

[0526] FIG. 47C shows a notebook personal computer, which includes a housing 921, a display unit 922, It has a keyboard 923, a pointing device 924, and the like.

[0527] FIG. 47(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, a freezer compartment door 933, and a It has 33 etc.

[0528] FIG. 47(E) shows a video camera, which includes a first housing 941, a second housing 942, and a display unit 943. , operation keys 944, a lens 945, a connection part 946, etc. The lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection part 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 942 at the connection unit 946. 42.

[0529] FIG. 47(F) shows an automobile, which includes a body 951, wheels 952, a dashboard 953, a light fixture, and a steering wheel 954. It has To954 etc.

[0530] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. [Example]

[0531] In this example, the spin density in the oxide semiconductor film was evaluated using ESR.

[0532] The method for preparing the samples used in this example will be described below.

[0533] First, a quartz substrate with a thickness of 0.5 mm was prepared as a substrate. Then, a 50 nm thick In-Ga-Zn oxide film was formed. Heat treatment was carried out at 450°C for 1 hour. Next, heat treatment was carried out at 450°C for 1 hour in an oxygen atmosphere. Next, a silicon oxynitride film was formed to a thickness of 10 nm on the oxide semiconductor film. Next, plasma treatment was performed. The plasma treatment was oxygen (O2) plasma treatment or Nitrous oxide (N2O) plasma treatment was performed for 90, 180 or 300 seconds.

[0534] In-Ga-Zn oxide is an In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=1:1:1. The film was formed by sputtering using an n-Ga-Zn oxide target. The gas used was a mixture of argon and oxygen such that the volume of oxygen was 33%. The pressure during film formation was measured at 0.7 Pa using a Canon Anelva miniature gauge MG-2. The deposition power was adjusted to 0.5 kW using a DC power supply. The substrate temperature was 300 The temperature was set to °C.

[0535] The silicon oxynitride film was formed using the PECVD method. The gas mixture used was a volume ratio of 1 part silane to 800 parts nitrous oxide. The pressure was adjusted to 200 Pa. The film formation power was a 60 MHz high frequency power supply. The power was set to 150 W. The substrate temperature was set to 350°C.

[0536] In addition, oxygen (O2) plasma treatment was performed using the PECVD method with an oxygen flow rate of 800 sccm. The source material was supplied into the reaction chamber of the PECVD device. The pressure during supply was adjusted to 200 Pa. The deposition power was 150 W using a 60 MHz high frequency power supply. The substrate temperature was 350 The temperature was set to °C.

[0537] Nitrous oxide (N2O) plasma treatment was performed using the PECVD method at a flow rate of 800 sc cm of nitrous oxide was supplied into the reaction chamber of the PECVD device. The pressure during supply was 200 Pa. The film formation power was adjusted to 150 W using a 60 MHz high frequency power source. The plate temperature was set to 350°C.

[0538] Next, the samples were evaluated by ESR. The sample was also evaluated by the magnetic field. The signal in the oxide semiconductor film where the g value appears near 1.93 (hereinafter referred to as "Vo The spin density of the H-induced signal and the NOx-induced signal in the insulating film were The related spin density is shown in Figure 48. The ESR evaluation was performed by the JEOL Ltd. The electron spin resonance spectrometer JES-FA300 was used.

[0539] As shown in Figure 48, the spin density of VoH in the oxide semiconductor film can be detected by plasma treatment. Lower limit (here 2.6 × 10 17 spins / cm 3 ) It was confirmed that It was also confirmed that the longer the plasma treatment, the more the spin density caused by VoH decreased. In addition, oxygen (O2) plasma treatment and nitrous oxide (N2O) plasma treatment were compared. It was found that oxygen (O2) plasma treatment is more preferable because it reduces the spin density caused by NOx. It was confirmed that:

[0540] In addition, among the above samples, oxygen (O2) plasma treatment was performed for 0 seconds (none), 90 seconds, or 1 The hydrogen concentration was evaluated for the sample after 80 seconds. The hydrogen concentration depth profile of the sample was measured using an MS analyzer and is shown in Figure 49. The condition of 0 seconds of plasma treatment is indicated by a solid line, and the other conditions are indicated by dashed lines.

[0541] As shown in Figure 49, the hydrogen concentration in the oxide semiconductor film can be reduced by oxygen (O2) plasma treatment. It was also confirmed that the VoH It was suggested that the spin density caused by the ion beam could be reduced. [Example]

[0542] In this example, a stacked film was formed on an oxide semiconductor film and a plasma treatment was performed on the stacked film. The spin density in the nitride semiconductor film was evaluated.

[0543] The method for preparing the samples used in this example will be described below.

[0544] First, a quartz substrate with a thickness of 0.5 mm was prepared as a substrate. Then, a 50 nm thick In-Ga-Zn oxide film was formed. Heat treatment was carried out at 450°C for 1 hour. Next, heat treatment was carried out at 450°C for 1 hour in an oxygen atmosphere. Next, a metal oxide film having a thickness of 5 nm was formed. Next, a silicon oxynitride film with a thickness of 10 nm was formed on the metal oxide film. O2) plasma treatment was performed.

[0545] The In-Ga-Zn oxide used in the oxide semiconductor film has an atomic ratio of In:Ga:Zn=1. Deposited by sputtering using an In-Ga-Zn oxide target with a ratio of 1:1. The deposition gas was a mixture of argon and oxygen so that the volume of oxygen was 33%. The pressure during film formation was measured using a Canon Anelva miniature gauge MG-2F. The pressure was adjusted to 0.7 Pa. The film formation power was set to 0.5 kW using a DC power supply. The substrate-target distance was 60 mm, and the substrate temperature was 300°C.

[0546] For the metal oxide film, two conditions, Condition 1 and Condition 2, were used. The sample prepared under condition 2 is designated as sample A, and the sample prepared under condition 2 is designated as sample B.

[0547] Condition 1: In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=1:3:2 The film was formed by sputtering using an In-Ga-Zn oxide target. The membrane gas was a mixture of argon and oxygen with a volumetric oxygen content of 33%. The pressure during film formation was measured at 0.4°C using a Canon Anelva BA gauge BRG-1B. The film formation power was adjusted to 0.5 kW using a DC power supply. The target distance was 60 mm and the substrate temperature was 200°C.

[0548] Condition 2: Gallium oxide was sputtered using a gallium oxide target. The deposition gas was argon and SiO2, with the volume of oxygen being 33%. The pressure during film formation was measured using a Canon Anelva miniature gauge M. The pressure was adjusted to 0.4 Pa using G-2L. The film formation power was set to 0. The power was 4 kW, the substrate-target distance was 130 mm, and the substrate temperature was 200°C.

[0549] The silicon oxynitride film was formed using the PECVD method. The gas mixture used was a volume ratio of 1 part silane to 800 parts nitrous oxide. The pressure was adjusted to 200 Pa. The film formation power was a 60 MHz high frequency power supply. The power was set to 150 W. The substrate temperature was set to 350°C.

[0550] In addition, oxygen (O2) plasma treatment was performed using the PECVD method with an oxygen flow rate of 800 sccm. The source material was supplied into the reaction chamber of the PECVD device. The pressure during supply was adjusted to 200 Pa. The deposition power was 150 W using a 60 MHz high frequency power supply. The substrate temperature was 350 The plasma treatment time for sample A was set to 0 seconds (none), 90 seconds, and 180 seconds. For sample B, the conditions were 0 seconds (none), 90 seconds, or 180 seconds. This was a condition.

[0551] Next, ESR analysis was performed on Sample A. The sample was made of In-Ga-Zn The oxide film surface was placed perpendicular to the magnetic field. The g value in the oxide semiconductor film was around 1.93. The spin density of the defect level (caused by VoH) related to the signal appearing in The ESR evaluation was performed using an electron spin resonance apparatus JES-FA300 manufactured by JEOL Ltd. there was.

[0552] As can be seen from FIG. 50, the spin density due to VoH in the oxide semiconductor film is reduced by plasma treatment. By performing plasma treatment for 180 seconds or more, the V The spin density due to oH is at the detection limit (7.4 × 10 17 spins / cm 3 )below It was confirmed that this was the case.

[0553] In addition, oxygen (O2) plasma treatment was performed on sample A for 0 seconds (none), 90 seconds, or 180 seconds. The conditions for sample B were 0 seconds (none), 90 seconds, or 180 seconds. The hydrogen concentration was evaluated using a SIMS analyzer. The depth profile of hydrogen concentration in sample A is shown in Figure 51, and the depth profile of hydrogen concentration in sample B is shown in Figure 52. The profile is shown in Figure 52. The condition of 0 seconds of plasma treatment is shown by a solid line, and the other conditions are shown by dashed lines.

[0554] As can be seen from FIG. 51, the longer the oxygen (O2) plasma treatment time for sample A, the greater the increase in the first It was confirmed that the hydrogen concentration in the oxide semiconductor film of Sample B was reduced. In the figure, the first oxide semiconductor film was heated to 180 seconds for the longest plasma treatment time. This result suggests that oxygen (O2) plasma treatment after insulating film deposition reduces the hydrogen concentration. It was confirmed that the hydrogen concentration in the oxide semiconductor film can be reduced by performing In addition, by reducing the hydrogen concentration in the oxide semiconductor film, the spin density due to VoH can be reduced. It was suggested that it can be reduced.

[0555] In addition, compared to when gallium oxide was used as the metal oxide, the In:Ga:Zn=1 In-Ga-Zn oxide formed using an In-Ga-Zn oxide target with a ratio of 1:1 It was suggested that the oxides were more permeable to hydrogen.

[0556] Furthermore, in comparison with Example 1, it was found that the silicon oxynitride film 10n The second oxide semiconductor film is formed on the first oxide semiconductor film by a 5 nm single layer. The hydrogen concentration is lower than that in the case where a 10 nm silicon oxynitride film is stacked. Therefore, the silicon oxynitride film is more likely to be reduced than the second oxide semiconductor film. The membrane may be more permeable to hydrogen. [Explanation of symbols]

[0557] 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel section 211 pixels 212 subpixels 212B subpixel 212G subpixel 212R subpixel 220 Photoelectric conversion element 230 pixel circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 filters 254B filter 254G filter 254R filter 255 Lens 256 light 257 Wiring 260 Peripheral Circuits 270 Peripheral Circuits 280 Peripheral Circuits 290 Peripheral Circuits 291 Light source 300 silicon substrate 310 layers 320 layers 330 layers 340 layers 351 Transistor 352 transistors 353 Transistor 360 photodiode 361 Anode 363 Low resistance region 370 Plug 371 Wiring 372 Wiring 373 Wiring 380 Insulator 400 Semiconductor Substrates 402 Insulator 404 Conductors 406 Semiconductors 406a Semiconductors 406b Semiconductors 406c Semiconductors 408 Insulator 412 Insulator 413 Conductors 414 Conductors 416 Conductors 416a Conductor 416b Conductor 417 Conductors 418 Insulator 420 layers 421 Conductors 423a Low resistance area 423b Low resistance region 424 Conductors 426a Conductors 426b Conductor 427 Mask 436a Semiconductors 436b Semiconductors 442 PCB 450 Semiconductor Substrate 452 Insulator Region 454 Conductors 460 areas 462 Insulator 464 Insulator 466 Insulator 467 Wiring layer 468 Insulator 469 Wiring layer 470 Insulator 472 Conductors 472a area 472b area 474 area 474a Conductor 474b Conductor 474c Conductor 476 area 476a Conductors 476b Conductor 478a Conductor 478b Conductor 478c Conductor 480a Conductor 480b Conductor 480c conductor 490 transistors 491 Transistors 492 transistors 493 Insulators 495 Insulators 494 Insulators 496a Conductors 496b Conductor 496c Conductor 496d Conductor 498a Conductors 498b Conductor 498c Conductor 498d Conductor 552 Insulator 700 boards 704a Conductor 704b Conductor 706 Semiconductors 712a Insulator 712b Insulator 714a Conductor 714b Conductor 716a Conductor 716b Conductor 718a Insulator 718b Insulator 718c Insulator 719 Light-emitting element 720 Insulator 721 Insulator 731 terminal 732 FPC 733a wiring 734 Sealing material 735 Drive Circuit 736 Drive Circuit 737 pixels 741 Transistor 742 Capacitor 743 Switching Elements 744 signal line 750 board 751 Transistor 752 Capacitor 753 Liquid crystal elements 754 scan lines 755 signal line 781 Conductors 782 luminescent layer 783 Conductors 784 Bulkhead 791 Conductors 792 Insulators 793 Liquid Crystal Layer 794 Insulators 795 Spacer 796 Conductors 797 Circuit Board 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 chassis 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 lens 946 Connection 951 body 952 wheels 953 Dashboard 954 Light 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Elements 1207 Capacitor element 1208 Capacitor 1209 Transistor 1210 transistor 1213 Transistor 1214 transistor 1220 circuits 2100 transistors 2200 transistors 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitor 5100 pellets 5100a pellets 5100b pellets 5101 AEON 5102 Zinc oxide layer 5103 particles 5105a Pellets 5105a1 area 5105a2 pellets 5105b Pellets 5105c Pellets 5105d Pellets 5105d1 area 5105e Pellets 5120 board 5130 Target 5161 area< / cpu>

Claims

1. a first transistor having a first channel formation region including silicon; a second transistor including a second channel formation region including an oxide semiconductor; a capacitance element; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitance element are electrically connected to each other; a first conductive layer that functions as one electrode of the capacitor; a second conductive layer having a region located above the first conductive layer and functioning as the other electrode of the capacitor; an oxide semiconductor layer having the second channel formation region; a third conductive layer having a region overlapping with the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a first insulating layer having a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third conductive layer; a second insulating layer having a region located above the first insulating layer and having at least a first opening, a second opening, and a third opening; a fourth conductive layer having a region located in the first opening of the second insulating layer; a fifth conductive layer having a region located in the second opening of the second insulating layer; a sixth conductive layer having a region located in the third opening of the second insulating layer; a seventh conductive layer having a region located above the fourth conductive layer; the second conductive layer has a region overlapping with a channel formation region of the first transistor, the fourth conductive layer has a region in contact with an upper surface of the second conductive layer and a region in contact with a lower surface of the seventh conductive layer, the fifth conductive layer has a region in contact with the oxide semiconductor layer, the fifth conductive layer is electrically connected to one of a source region and a drain region of the first transistor; the sixth conductive layer has a region in contact with the oxide semiconductor layer, the sixth conductive layer is electrically connected to a gate electrode of the first transistor; the seventh conductive layer has a region overlapping with the oxide semiconductor layer.

2. a first transistor having a first channel formation region including silicon; a second transistor having a second channel formation region including an oxide semiconductor; a capacitance element; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitance element are electrically connected to each other; a first conductive layer that functions as one electrode of the capacitor; a second conductive layer having a region located above the first conductive layer and functioning as the other electrode of the capacitor; an oxide semiconductor layer having the second channel formation region; a third conductive layer having a region overlapping with the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a first insulating layer having a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third conductive layer; a second insulating layer having a region located above the first insulating layer and having at least a first opening, a second opening, and a third opening; a fourth conductive layer having a region located in the first opening of the second insulating layer; a fifth conductive layer having a region located in the second opening of the second insulating layer; a sixth conductive layer having a region located in the third opening of the second insulating layer; a seventh conductive layer having a region located above the fourth conductive layer; the second conductive layer has a region overlapping with a channel formation region of the first transistor, the fourth conductive layer has a region in contact with an upper surface of the second conductive layer and a region in contact with a lower surface of the seventh conductive layer, the fifth conductive layer has a region in contact with the oxide semiconductor layer, the fifth conductive layer is electrically connected to one of a source region and a drain region of the first transistor; the sixth conductive layer has a region in contact with the oxide semiconductor layer, the sixth conductive layer is electrically connected to a gate electrode of the first transistor; the seventh conductive layer has a region overlapping with the oxide semiconductor layer and a region overlapping with the first channel formation region.

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