Solar cell, method for manufacturing the same, and photovoltaic module

Abstract

SOLUTION: A solar cell includes a silicon substrate, a first semiconductor layer doped with an N-type conductive element and a second semiconductor layer doped with a P-type conductive element on the silicon substrate, a first electrode electrically connected to the first semiconductor layer through a plurality of first conductive structures, and a second electrode electrically connected to the second semiconductor layer through a plurality of second conductive structures, wherein a density of the first conductive structures is greater than a density of the second conductive structures.EFFECT: The solar cell can improve the transport efficiency of carriers, reduce recombination, and reduce scattering.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to the field of solar cells, and more particularly to a solar cell, a method for manufacturing the same, and a photovoltaic module. [Background technology]

[0002] In solar cells, the ability to transport carriers between the semiconductor layer and the electrode has a significant impact on the photoelectric conversion efficiency of the solar cell. If the resistance of carriers to the electrode is high, the probability of carriers coming into contact with defects or impurities in the semiconductor layer increases, which increases the probability of carrier scattering and causes more carriers to recombine, limiting further improvement in the photoelectric conversion efficiency of solar cells. Summary of the Invention [Problem to be solved by the invention]

[0003] The embodiments of the present invention disclose a solar cell, a manufacturing method thereof, and a photovoltaic module, which can further improve the photoelectric conversion efficiency of the solar cell by improving carrier transport efficiency, reducing recombination, and reducing scattering. [Means for solving the problem]

[0004] In a first aspect, embodiments of the present invention provide a solar cell, the solar cell comprising: A silicon substrate; a first semiconductor layer doped with an N-type conductive element and a second semiconductor layer doped with a P-type conductive element, the first semiconductor layer being provided on the silicon substrate; a first electrode electrically connected to the first semiconductor layer via a plurality of first conductive structures; a second electrode electrically connected to the second semiconductor layer via a plurality of second conductive structures; The density of the first conductive structures is greater than the density of the second conductive structures.

[0005] Furthermore, in any 1 mm×1 mm area where the first electrode and the first semiconductor layer are in contact, the number of the first conductive structures is 1×10 5 pieces~1×10 6 and the number of the second conductive structures in any 1 mm×1 mm area in contact with the second electrode and the second semiconductor layer is 5×10 4 pieces~5×10 5 There are individuals.

[0006] Furthermore, the projection size of the first conductive structure on the first semiconductor layer is equal to or larger than the projection size of the second conductive structure on the second semiconductor layer, the projection size of any of the first conductive structures on the first semiconductor layer is 100 nm to 2000 nm, and the projection size of any of the second conductive structures on the second semiconductor layer is 100 nm to 1000 nm.

[0007] Furthermore, the first conductive structure and the second conductive structure are both vein-shaped.

[0008] Further, any of the first conductive structures includes a plurality of strip-shaped first structures diverging in a direction of the first electrode; Each of the second conductive structures includes a plurality of strip-shaped second structures diverging in the direction of the second electrode.

[0009] Furthermore, each of the first structures includes a first crystalline main chain and a plurality of first crystalline side chains extending in a direction different from the growth direction of the first crystalline main chain, Each of the second structures includes a second crystalline main chain and a plurality of second crystalline side chains extending in a direction different from the growth direction of the second crystalline main chain.

[0010] Furthermore, the first structure and the second structure are both formed by crystallization polymerization of a plurality of conductive fine particles.

[0011] Furthermore, the elements in the conductive fine particles include one or a combination of a silver element, an aluminum element, a copper element, and a lead element.

[0012] Furthermore, the doping concentration of the N-type conductive element in the first semiconductor layer is 1×10 20 atoms / cm 3 ~1×10 21 atoms / cm 3 and The doping concentration of the P-type conductive element in the second semiconductor layer is 1×10 18 atoms / cm 3 ~1×10 20 atoms / cm 3 is.

[0013] Furthermore, the first semiconductor layer and the second semiconductor layer are provided on a non-light-receiving surface of the silicon substrate, the first semiconductor layer and the second semiconductor layer are isolated by an isolation region, and the first semiconductor layer and the second semiconductor layer are arranged in a fingerprint pattern.

[0014] Furthermore, the solar cell further includes a first dielectric layer provided between the first semiconductor layer and the silicon substrate, and a second dielectric layer provided between the second semiconductor layer and the silicon substrate.

[0015] Furthermore, the silicon substrate is N-type, the second semiconductor layer is provided on the light-receiving surface of the silicon substrate, the first semiconductor layer is provided on the non-light-receiving surface of the silicon substrate, and a first dielectric layer is further provided between the first semiconductor layer and the silicon substrate.

[0016] Further, a plurality of the first semiconductor layers are provided on the non-light-receiving surface, each of the first semiconductor layers is provided in a partial region of the non-light-receiving surface, and adjacent first semiconductor layers are isolated by a first isolation region, and / or a plurality of the second semiconductor layers are provided on the light receiving surface, each of the second semiconductor layers is provided in a partial region of the light receiving surface, and two adjacent second semiconductor layers are isolated by a second isolation region; A textured structure is provided in the second isolated region.

[0017] In a second aspect, the present application discloses a method for manufacturing the solar cell according to the first aspect, the method comprising: providing a silicon substrate having the first semiconductor layer and the second semiconductor layer disposed thereon; applying a paste for manufacturing the first electrode to the first semiconductor layer and a paste for manufacturing the second electrode to the second semiconductor layer; a heat treatment step of forming a first conductive precursor at a contact interface between the first electrode and the first semiconductor layer and forming a second conductive precursor at a contact interface between the second electrode and the second semiconductor layer; and a light injection step to convert the first conductive precursor into a first conductive structure and the second conductive precursor into a second conductive structure to produce the solar cell.

[0018] Furthermore, the light injection step a heating step of heating the first conductive precursor and the second conductive precursor, the peak temperature of the heating step being 400°C to 650°C; When the temperature in the heating step is reduced from the peak temperature to a predetermined temperature, the solar cell is heated to a temperature of 50°C to 400°C and an energy density of 10 kW / m 2 ~100kW / m 2 and applying light irradiation in which The predetermined temperature is 320°C to 360°C.

[0019] Furthermore, in the heating step, heating to the predetermined temperature; and a step of heating from the predetermined temperature to the peak temperature within a predetermined time of 10 seconds to 30 seconds, and then lowering the temperature back to the predetermined temperature.

[0020] Furthermore, the first conductive precursor includes a plurality of first crystalline main chains that all diverge toward the first electrode; The second conductive precursor includes a plurality of second crystalline main chains that all diverge toward the second electrode.

[0021] Furthermore, in the heat treatment step, the heat treatment temperature is 700°C to 900°C.

[0022] Further, the step of providing a silicon substrate comprises: depositing a second dielectric layer and the second semiconductor layer in sequence on the non-light-receiving surface of the silicon substrate; performing a patterning process on the second dielectric layer and the second semiconductor layer located on the non-light-receiving surface to expose a portion of the non-light-receiving surface; depositing a first dielectric layer and the first semiconductor layer in sequence on the exposed non-light-receiving surface and the second semiconductor layer; removing the first semiconductor layer and the first dielectric layer located on the second semiconductor layer to form an isolation region between the adjacent second semiconductor layer and the first semiconductor layer.

[0023] Further, the step of providing a silicon substrate comprises: depositing the second semiconductor layer on a light-receiving surface of the silicon substrate; and depositing a first dielectric layer and the first semiconductor layer in sequence on the non-light-receiving surface of the silicon substrate.

[0024] In a third aspect, an embodiment of the present application discloses a photovoltaic module including the solar cell according to the first aspect, or the solar cell manufactured by the manufacturing method according to the second aspect. [Effects of the Invention]

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] The present application provides a solar cell, a manufacturing method thereof, and a photovoltaic module, which can improve the stability and photoelectric conversion efficiency of the solar cell by improving the carrier transport ability, reducing recombination, and reducing scattering.

[0027] In the solar cell structure, the first semiconductor layer is doped with an N-type conductive element and the second semiconductor layer is doped with a P-type conductive element, so the carrier diffusion ability in the first semiconductor layer is higher than that in the second semiconductor layer. In this case, if the carriers in the first semiconductor layer are difficult to transport to the first electrode, the carriers in the first semiconductor layer are more likely to come into contact with impurities and defects, resulting in serious carrier scattering and recombination in the first semiconductor layer. Therefore, to improve the effectiveness of carrier transport in the first semiconductor layer, the present application sets the density of the first conductive structures higher than the density of the second conductive structures. This makes the distribution of the first conductive structures more dense, providing multiple paths for carrier transport, reducing contact resistance and reducing carrier transport blockage between the first semiconductor layer and the first electrode, improving carrier mobility, suppressing carrier scattering, and reducing carrier recombination, thereby contributing to improving the photoelectric conversion efficiency of the solar cell.

[0028] In other words, by adjusting the densities of the first conductive structure and the second conductive structure, the effectiveness of carrier transport between the first semiconductor layer and the first conductive structure is improved, recombination is reduced, scattering is reduced, and the photoelectric conversion efficiency of the solar cell is improved.

[0029] In order to more clearly explain the technical solutions of the embodiments of the present application or the prior art, the drawings necessary for describing the embodiments or the prior art will be briefly described. The drawings described below are only shown in the embodiments of the present application, and it is clear that those skilled in the art can obtain drawings of other embodiments based on these drawings without any creative efforts. [Brief explanation of the drawings]

[0030] [Figure 1] 1 is a schematic diagram of a first type of solar cell configuration according to an embodiment of the present application; [Figure 2] FIG. 2 is an enlarged view of part A in FIG. 1 according to an embodiment of the present application. [Figure 3] FIG. 2 is an enlarged view of part B in FIG. 1 according to an embodiment of the present application. [Figure 4]2 is a schematic diagram of a configuration of a first conductive structure according to an embodiment of the present application; [Figure 5] 1 is a schematic diagram of a first structure configuration according to an embodiment of the present application; [Figure 6] 2 is a schematic diagram of a second type of solar cell configuration according to an embodiment of the present application. [Figure 7] 1 is a schematic diagram of a third type of solar cell configuration according to an embodiment of the present application. [Figure 8] FIG. 2 is an electron microscope view of a first conductive precursor according to an embodiment of the present application. [Figure 9] FIG. 2 is an electron microscope view of a second conductive structure according to an embodiment of the present application. [Figure 10] FIG. 2 is an electron microscope view of a second conductive precursor according to an embodiment of the present application. [Figure 11] FIG. 2 is an electron microscope view of a second conductive structure according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0031] In order to more clearly explain the technical solutions according to the embodiments of the present invention, the drawings necessary for describing the embodiments will be briefly described. The drawings described below are merely illustrative of some embodiments of the present invention and do not limit the scope of the claims. Other embodiments that can be obtained by those skilled in the art based on the embodiments of the present application without requiring creative efforts also fall within the scope of protection of the present application.

[0032] In this application, the orientations or positional relationships indicated by terms such as "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," "longitudinal," etc. are orientations or positional relationships shown in the drawings. These terms are primarily intended to better explain the application and its embodiments, and are not intended to limit the illustrated devices, elements, or components that must have a specific orientation or be configured and operated in a specific orientation.

[0033] In addition, some of the above terms can be used to express other meanings in addition to expressing an orientation or positional relationship, for example, the term "on" can also be used to express a dependency or connection relationship in some cases. Those skilled in the art can understand the specific meanings of these terms in the present application according to specific circumstances.

[0034] It should be noted that the terms "first," "second," etc. are primarily intended to distinguish between different devices, elements, or components (which may be the same or different in specific type and structure), and are not intended to state or imply the relative importance or number of the devices, elements, or components shown. Unless otherwise specified, the term "plurality" means at least two.

[0035] The technical means disclosed in the present application will be further described below with reference to examples and drawings.

[0036] In solar cells, the carrier concentration and carrier transport ability have a very important effect on the performance such as the photoelectric conversion efficiency of the solar cell.

[0037] Since electron mobility is higher than hole mobility, electrons are transported faster under the same electric field and can participate more effectively in the conduction process. However, if electrons are difficult to transport to the electrode, the probability of electrons coming into contact with impurities or defects in the semiconductor layer increases, increasing the probability of scattering and recombination. As a result, it becomes difficult to effectively improve the conduction performance of solar cells.

[0038] Based on the above problems, the present application discloses a solar cell, which can improve the photoelectric conversion efficiency of the solar cell by improving the carrier mobility and reducing the recombination.

[0039] In a first aspect, as shown in FIGS. 1 to 3, an embodiment of the present application provides a solar cell, the solar cell comprising: a silicon substrate 1; a first semiconductor layer 21 doped with an N-type conductive element and a second semiconductor layer 22 doped with a P-type conductive element, both of which are provided on a silicon substrate 1; a first electrode 31 electrically connected to the first semiconductor layer 21 via a plurality of first conductive structures 41; a second electrode 32 electrically connected to the second semiconductor layer 22 via a plurality of second conductive structures 42; The density of the first conductive structures 41 is greater than the density of the second conductive structures 42 .

[0040] In this embodiment, by setting the density of the first conductive structure 41 higher than the density of the second conductive structure 42, the distribution density of the first conductive structure 41 is increased, providing multiple transport paths for carrier transport, contributing to lowering contact resistance, reducing carrier transport obstruction between the first semiconductor layer 21 and the first electrode 31, improving carrier mobility, reducing carrier scattering, contributing to reducing recombination, and improving the photoelectric conversion efficiency of the solar cell.

[0041] In addition, in solar cells, the doping concentration of the N-type conductive element in the first semiconductor layer is usually set to be higher than the doping concentration of the P-type conductive element in the second semiconductor layer. Because the doping concentration of the N-type conductive element is high, the carrier concentration increases. However, if the carriers are less likely to be efficiently transported to the electrode, the probability of carrier scattering and recombination increases. Therefore, in the present application, the density of the first conductive structure is set to be higher than the density of the second conductive structure, and carriers are efficiently transported to the first electrode via the first conductive structure. This reduces carrier recombination and scattering, improving the photoelectric conversion efficiency of the solar cell.

[0042] As described above, the present application further reduces the effect of the high carrier diffusion rate in the first semiconductor layer on carrier scattering and recombination by optimizing the densities of the first conductive structure 41 and the second conductive structure 42, thereby effectively transporting carriers to the electrode and improving the performance of the solar cell. That is, the semiconductor layer and the conductive structure work together to improve the stability of the contact between the semiconductor layer and the electrode, reduce contact resistance, improve carrier mobility, reduce recombination, and contribute to improving conductivity, thereby improving the photoelectric conversion efficiency of the solar cell.

[0043] The type of carrier that can be provided by the N-type conductive element is an electron, and the N-type conductive element includes at least one of phosphorus and arsenic. The type of carrier that can be provided by the P-type conductive element is a hole, and the N-type conductive element includes at least one of boron and gallium.

[0044] Furthermore, in any 1 mm×1 mm area where the first electrode 31 and the first semiconductor layer 21 are in contact, the number of first conductive structures 41 is 1×10 5 pieces~1×10 6 In any 1 mm×1 mm area where the second electrode 32 and the second semiconductor layer 22 are in contact, the number of second conductive structures 42 is 5×10 4 pieces~5×10 5 There are individuals.

[0045] When the number of first conductive structures 41 and second conductive structures 42 satisfies the above range, the contact area between the electrode and the semiconductor layer is appropriate, which effectively reduces contact resistance and improves carrier transport. This not only avoids the situation where it is difficult to effectively improve carrier transport efficiency when the number of conductive structures is small, but also avoids problems such as the contact area between the semiconductor layer and the electrode being too large, which can lead to large damage ranges in the contact area and serious contamination when the number of conductive structures is too large, reducing the occurrence of recombination and thereby better optimizing the performance of the solar cell.

[0046] Furthermore, as shown in Figures 2 and 3, the projection size of the first conductive structure 41 on the first semiconductor layer 21 is equal to or larger than the projection size of the second conductive structure 42 on the second semiconductor layer 22, and the projection size of any of the first conductive structures 41 on the first semiconductor layer 21 is 100 nm to 2000 nm, and the projection size of any of the second conductive structures 42 on the second semiconductor layer 22 is 100 nm to 1000 nm.

[0047] 4, taking the first conductive structure 41 as an example, the projected size of the first conductive structure 41 refers to the width d between the two most distant points of the first conductive structure 41 that diverge outward. Similarly, the projected size of the second conductive structure 42 refers to the width d between the two most distant points of the second conductive structure 42 that diverge outward.

[0048] When the projected sizes of the first conductive structure 41 and the second conductive structure 42 are within the above range, good carrier transport capability is ensured, damage to the contact interface between the semiconductor layer and the electrode is reduced, contact recombination is reduced, and the contact performance between the semiconductor layer and the electrode is better optimized. Furthermore, since the doping content of the second semiconductor layer 22 is low, it is preferable that the projected size of the second conductive structure 42 is smaller than that of the first conductive structure 41, which reduces defects at the contact interface and further reduces carrier recombination. Furthermore, since the projected size of the first conductive structure 41 is large, the carrier transport speed in the first semiconductor layer 21 is significantly improved, carrier scattering is reduced, and the photoelectric conversion efficiency of the solar cell is improved, and the paste consumption and usage cost are also reduced.

[0049] Furthermore, both the first conductive structure 41 and the second conductive structure 42 have a vein-like shape.

[0050] To further improve carrier mobility, the first conductive structure 41 and the second conductive structure 42 of the present invention are both vein-shaped. The use of such a structure not only contributes to increasing the contact area between any conductive structure and the semiconductor layer, but also provides carrier transport paths in multiple directions, ensuring uniformity of carrier transport and reducing resistance losses, thereby contributing to improving the photoelectric conversion efficiency of solar cells. It also improves the stability of the contact between the electrode and the semiconductor layer, helping to ensure excellent contact performance during welding processes and stability tests of related cells or assemblies.

[0051] 5, the first conductive structure 41 includes a plurality of strip-shaped first structures 411 that diverge toward the first electrode 31, and the second conductive structure 42 includes a plurality of strip-shaped second structures that diverge toward the second electrode 32. The large number of first structures 411 and second structures ensures that the first conductive structure 41 and the second conductive structure 42 can provide many carrier transport paths, which is advantageous for improving carrier mobility.

[0052] Each of the first structures 411 includes a first crystalline main chain 4111 and a plurality of first crystalline side chains 4112 extending in a direction different from the growth direction of the first crystalline main chain 4111, and each of the second structures includes a second crystalline main chain and a plurality of second crystalline side chains extending in a direction different from the growth direction of the second crystalline main chain. The large number of first crystalline side chains 4112 and second crystalline side chains ensures that the first conductive structure 41 and the second conductive structure 42 can provide many carrier transport paths, which is advantageous for improving carrier mobility and reducing recombination.

[0053] Specifically, taking the first conductive structure 41 as an example, the first conductive structure 41 includes multiple first structures 411, each of which is composed of one first crystalline main chain 4111 and multiple first crystalline side chains 4112. Therefore, carriers in the first semiconductor layer 21 can transport not only along the first crystalline main chain 4111 but also along the first crystalline side chains 4112. Furthermore, the large number of first crystalline main chains 4111 and first crystalline side chains 4112 in the first conductive structure 41 ensures a high contact area between the first electrode 31 and the first semiconductor layer 21, contributing to reduced contact resistance. Furthermore, the multiple transport paths provided by the first conductive structure 41 enhance the bonding stability between the first electrode 31 and the first semiconductor layer 21, contributing to the stability of welding of the subsequent solar cell module and significantly improving the performance of the solar cell.

[0054] Furthermore, both the first structure 411 and the second structure are formed by crystallization polymerization of multiple conductive particles, and the elements in the conductive particles include one or a combination of multiple elements selected from the group consisting of silver, aluminum, copper, and lead.

[0055] In addition, in order to ensure that the solar cell of the present invention has good conductivity, the doping concentration of the N-type conductive element in the first semiconductor layer 21 is set to 1×10 20 atoms / cm 3 ~1×10 21 atoms / cm 3 and the doping concentration of the P-type conductive element in the second semiconductor layer 22 is 1×10 18 atoms / cm 3 ~1×10 20 atoms / cm 3 When the doping concentration of the conductive element is controlled within the above range, the carrier content and the number of conductive structures are closely matched, which can effectively improve the conductivity of the solar cell, avoid the influence of high doping concentration on carrier transport, improve carrier mobility, reduce recombination, and improve the photoelectric conversion efficiency of the solar cell.

[0056] In a first embodiment, returning to FIG. 1, the solar cell is a back-contact cell, in which the first semiconductor layer 21 and the second semiconductor layer 22 are provided on the non-light-receiving surface of the silicon substrate 1, the first semiconductor layer 21 and the second semiconductor layer 22 are separated by an isolation region, and the first semiconductor layer 21 and the second semiconductor layer 22 are arranged in a fingerprint pattern.

[0057] For back-contact cells, the positive and negative electrodes of such solar cells are all located on the non-light-receiving side, so there is no shading by metal grid lines on the light-receiving side, which avoids light-shading losses caused by the electrodes and reduces recombination on the light-receiving side, thereby improving the photoelectric conversion efficiency of the solar cell.

[0058] In addition, to further improve the performance of the solar cell, a passivation contact structure can be provided on the non-light-receiving surface of the solar cell, i.e., the solar cell further includes a first dielectric layer 51 provided between the first semiconductor layer 21 and the silicon substrate 1, and a second dielectric layer 52 provided between the second semiconductor layer 22 and the silicon substrate 1.

[0059] Since a solar cell includes a dielectric layer and a semiconductor layer, the two together form a passivation contact structure, providing a good interface passivation effect on the non-light-receiving surface. The material of the dielectric layer may include at least one of a variety of dielectric materials, for example, silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Preferably, the dielectric layer is a silicon oxide layer made of silicon oxide, because the silicon oxide layer has excellent passivation performance, can minimize the recombination loss of minority carriers on the silicon substrate surface, and is a thin film with excellent durability against subsequent high-temperature processes.

[0060] The dielectric layer acts as an energy barrier against electrons and holes, and by bonding with the semiconductor layer, it forms a passivation contact structure that blocks the passage of minority carriers. The dielectric layer also has a pinhole channel effect, allowing carriers to move freely within the solar cell, while the heavily doped semiconductor layer selectively allows majority carriers to pass through, which is advantageous for reducing minority carrier recombination loss. The dielectric layer can also be used as a diffusion energy barrier to prevent conductive elements in the semiconductor layer from diffusing into the silicon substrate. Furthermore, controlling the thickness of the dielectric layer to 0.5 nm to 4 nm is advantageous for reducing carrier transport inhibition and improving its transport efficiency.

[0061] In addition, providing a first functional layer 61 on the first semiconductor layer 21 and a second functional layer 62 on the second semiconductor layer 22 also helps to improve the performance of the solar cell, where the first functional layer 61 is a first passivation layer and / or a first anti-reflection layer, and the second functional layer 62 is a second passivation layer and / or a second anti-reflection layer.

[0062] Furthermore, since the first semiconductor layer 21 and the second semiconductor layer 22 are both located on the non-light-receiving surface of the silicon substrate 1, i.e., the first functional layer 61 and the second functional layer 62 are both located on the non-light-receiving surface of the solar cell, in this case, the first functional layer 61 and the second functional layer 62 are manufactured in the same step and are the same type of film layer, and in order to further improve the photoelectric conversion efficiency of the solar cell, a third functional layer 63 is further provided on the light-receiving surface of the silicon substrate 1.

[0063] In a second embodiment, as shown in Figures 6 and 7, the solar cell is a passivation contact cell, the silicon substrate 1 is N-type, the second semiconductor layer 22 is provided on the light-receiving surface of the silicon substrate 1, the first semiconductor layer 21 is provided on the non-light-receiving surface of the silicon substrate 1, and a first dielectric layer 51 is further provided between the first semiconductor layer 21 and the silicon substrate 1.

[0064] Returning to FIG. 7 , in order to further improve the passivation effect of the solar cell and increase the photoelectric conversion efficiency of the solar cell, the present application provides a plurality of first semiconductor layers 21 on the non-light-receiving surface, each of which is provided in a partial region of the non-light-receiving surface, with adjacent first semiconductor layers 21 separated by a first isolation region 7; and / or a plurality of second semiconductor layers 22 on the light-receiving surface, each of which is provided in a partial region of the light-receiving surface, with adjacent two second semiconductor layers 22 separated by a second isolation region 8, with the second isolation region 8 provided with a textured structure. When a local passivation structure is provided on both the light-receiving surface and the non-light-receiving surface, the passivation effect of the light-receiving surface is high and the impact on the amount of sunlight absorption is small. Providing a local passivation structure on the non-light-receiving surface reduces production costs and reduces damage caused by contact between the semiconductor layer and the silicon substrate, contributing to improving the photoelectric conversion efficiency of the solar cell.

[0065] In addition, in order to improve the passivation effect of the light-receiving surface, a second dielectric layer 52 may be provided on the light-receiving surface, and the second dielectric layer 52 is located between the second semiconductor layer 22 and the silicon substrate 1.

[0066] Furthermore, a first functional layer 61 is manufactured on the side of the first semiconductor layer 21 away from the silicon substrate 1, and a second functional layer 62 is manufactured on the side of the second semiconductor layer 22 away from the silicon substrate 1, the first functional layer 61 being a first passivation layer and / or a first antireflection layer, and the second functional layer 62 being a second passivation layer and / or a second antireflection layer.

[0067] The passivation layer reduces surface recombination and contributes to improving the photoelectric conversion efficiency of the solar cell, and the anti-reflection layer reduces the reflection of incident light while also fulfilling a passivation function, thereby further improving the photoelectric efficiency of the solar cell. Illustratively, the first functional layer 61 is a first passivation layer, a first anti-reflection layer, or a first passivation layer and a first anti-reflection layer, and the second functional layer 62 is a second anti-reflection layer, a second passivation layer, or a second passivation layer and a second anti-reflection layer.

[0068] When functional layers are provided on the first semiconductor layer 21 and the second semiconductor layer 22, they contribute to improving the photoelectric conversion efficiency of the solar cell, and the first electrode 31 needs to penetrate the first functional layer 61 and be connected to the first semiconductor layer 21 via the first conductive structure 41, and the second electrode 32 needs to penetrate the second functional layer 62 and be connected to the second semiconductor layer 22 via the second conductive structure 42. In this case, since the second semiconductor layer 22 is located on the light-receiving surface of the solar cell, the second functional layer 62 is located on the second semiconductor layer 22 and the exposed texture structure, and the first functional layer 61 is located on the first semiconductor layer 21 and the exposed non-light-receiving surface.

[0069] The first functional layer 61 contains at least one of aluminum oxide, silicon oxide, silicon oxynitride, and silicon nitride, and the second functional layer 62 contains at least one of aluminum oxide, silicon oxide, silicon oxynitride, and silicon nitride.

[0070] In a second aspect, the present embodiment further discloses a method for manufacturing a solar cell, the method comprising: providing a silicon substrate having a first semiconductor layer and a second semiconductor layer disposed thereon; Applying a paste for manufacturing a first electrode to the first semiconductor layer and applying a paste for manufacturing a second electrode to the second semiconductor layer; a heat treatment step for forming a first conductive precursor at the contact interface between the first electrode and the first semiconductor layer and for forming a second conductive precursor at the contact interface between the second electrode and the second semiconductor layer; and a light injection step to convert the first conductive precursor into a first conductive structure and the second conductive precursor into a second conductive structure to produce a solar cell.

[0071] The paste can be printed onto the semiconductor layer by screen printing.

[0072] The paste contains conductive particles, glass, an organic solvent, and a binder. The conductive particles have good conductivity and can bring the crystals and the semiconductor layer into good contact during the heat treatment process, ensuring efficient current transport. The glass can melt and bond the conductive particles and the semiconductor layer during the heat treatment process, promoting contact of the conductive particles with the semiconductor layer through the functional layer. The organic solvent and binder modify the fluidity of the paste, reducing the difficulty of printing and improving printing quality.

[0073] Furthermore, the first conductive precursor includes a plurality of first crystalline main chains that all diverge toward the first electrode, and the second conductive precursor includes a plurality of second crystalline main chains that all diverge toward the second electrode.

[0074] As shown in Figure 8, during the heat treatment, the organic solvent and binder in the paste for manufacturing the first electrode volatilize and leave behind conductive particles, some of which further crystallize and aggregate. After these conductive particles crystallize, they form a first conductive precursor at the interface between the first electrode and the first semiconductor layer. The first conductive precursor structure appears as several first crystalline main chains diverging toward the first electrode. As shown in Figure 9, during the subsequent light injection process, some of the conductive particles aggregate and grow in a direction different from the growth direction of the first crystalline main chain due to the high temperature and strong photocatalytic reduction, forming a plurality of elongated first crystalline side chains, thereby producing a leaf-vein-like first conductive structure.

[0075] As shown in Figure 10, during the heat treatment process, the organic solvent and binder in the paste for manufacturing the second electrode volatilize and leave behind conductive particles, some of which further crystallize and aggregate. After these conductive particles crystallize, a second conductive precursor is formed at the contact interface between the second electrode and the second semiconductor layer. The structure of this second conductive precursor appears as several second crystalline main chains diverging toward the second electrode. As shown in Figure 11, during the subsequent light injection process, some of the conductive particles aggregate and grow in a direction different from the growth direction of the second crystalline main chain due to the high temperature and strong photocatalytic reduction, forming multiple elongated second crystalline side chains, thereby producing a vein-like second conductive structure.

[0076] That is, the light injection step causes some of the conductive particles to aggregate and grow into a crystalline main chain, forming crystalline side chains, i.e., converting the first conductive precursor into a first conductive structure, connecting the first electrode and the first semiconductor layer, and converting the second conductive precursor into a second conductive structure, connecting the second electrode and the second semiconductor layer. In addition, the manufacturing method of the present application ensures that the density of the manufactured second microstructure is lower than that of the first microstructure, which is advantageous for improving the carrier transport ability.

[0077] Furthermore, the light injection step a heating step in which the first conductive precursor and the second conductive precursor are heated, and the peak temperature of the heating step is 400°C to 650°C; When the temperature in the heating stage is lowered from the peak temperature to a predetermined temperature, the solar cell is heated to a temperature of 50°C to 400°C and the energy density is 10kW / m 2 ~100kW / m 2 and applying light irradiation at a predetermined temperature of 320°C to 360°C.

[0078] Controlling the light injection parameters within the above ranges is beneficial to the diffusion and crystalline aggregation of conductive particles, ensuring that the parameters of the formed first conductive structure and second conductive structure are within the ranges of the present application, contributing to reducing contact resistance and improving carrier transport efficiency.

[0079] Furthermore, the heating step includes a step of heating to a predetermined temperature, and a step of heating from the predetermined temperature to a peak temperature within a predetermined time and then lowering the temperature to a predetermined temperature, the predetermined time being 10 to 30 seconds. During the heating step, the glass solvent is in a softened state, so that the conductive particles are uniformly dispersed in the glass. By controlling the predetermined time within the above range, there is sufficient time for the conductive particles to migrate, agglomerate, and reduce to form a conductive structure, thereby ensuring that both the manufactured first conductive structure and second conductive structure meet the scope of the present application.

[0080] Furthermore, in the heat treatment step, the heat treatment temperature is 700°C to 900°C. Controlling the heat treatment temperature within the above range promotes the diffusion and bonding of the conductive particles, contributes to the formation of the conductive precursor, and ensures that the structure of the produced conductive precursor meets the requirements of the present application.

[0081] Furthermore, after the step of applying the first electrode paste to the first semiconductor layer and before the step of applying the second electrode paste to the second semiconductor layer, the manufacturing method may further include a step of drying the first electrode paste at a temperature of 100°C to 300°C; and / or After the step of applying the paste for the second electrode to the second semiconductor layer, the method includes a step of drying the paste for the second electrode at a temperature of 100°C to 300°C before the step of heat treatment.

[0082] By drying the paste before the heat treatment step, part of the organic solvent in the paste can be volatilized and the humidity of the paste can be reduced, thereby avoiding the problem that the rapid evaporation of the organic solvent during the heat treatment process reduces the stability of the electrode structure, reduces the stability of the contact area between the electrode and the semiconductor layer, and increases the number of defects in the contact area, making it difficult to effectively improve the photoelectric conversion performance of the solar cell.

[0083] In a first alternative embodiment, the step of providing a silicon substrate comprises: depositing a second dielectric layer and a second semiconductor layer in sequence on the non-light-receiving surface of the silicon substrate; performing a patterning process on the second dielectric layer and the second semiconductor layer located on the non-light-receiving surface to expose a portion of the non-light-receiving surface; depositing a first dielectric layer and a first semiconductor layer in sequence on the exposed non-light-receiving surface and the second semiconductor layer; removing the first semiconductor layer and the first dielectric layer located on the second semiconductor layer to form an isolation region between the adjacent second semiconductor layer and the first semiconductor layer.

[0084] The present application does not limit the manufacturing process of the dielectric layer and the semiconductor layer, as long as the object of the present application is achieved.

[0085] As an option, a second dielectric layer and a second semiconductor layer are fabricated on the non-light-receiving surface by chemical vapor deposition, in which high-purity oxygen gas is first introduced to grow the second dielectric layer at 400°C to 650°C, then high-purity SiH4 is introduced to fabricate the second amorphous silicon layer at 450°C to 700°C, and finally BCl3 is introduced at 750°C to 1050°C to perform boron diffusion and crystallize the second amorphous silicon layer, and then the second semiconductor layer is formed; The second semiconductor layer and the second dielectric layer are removed by laser and wet alkaline etching to expose a portion of the non-light-receiving surface; A first dielectric layer and a first semiconductor layer are fabricated on the non-light-receiving surface by chemical vapor deposition. High-purity oxygen gas is introduced to grow the first dielectric layer at 400°C to 650°C. High-purity SiH4 is then introduced to fabricate a first amorphous silicon layer at 450°C to 700°C. POCl3 is then introduced at 700°C to 950°C to diffuse phosphorus, and the first amorphous silicon layer is crystallized and doped, after which the first semiconductor layer is formed.

[0086] The above manufacturing process not only ensures that the doping concentrations of the conductive elements in the first and second semiconductor layers of the present application are within the range of the present application, but also contributes to the high flatness of the deposited film layer, the small interfacial defects, and the reduction of recombination.

[0087] After fabricating the first and second semiconductor layers, the light-receiving surface of the silicon substrate is textured, cleaned, and then textured, resulting in a textured structure across the entire light-receiving surface, which contributes to reducing solar light reflection and improving solar light absorption. Furthermore, both the first and second semiconductor layers are located on the non-light-receiving surface, i.e., the first functional layer on the first semiconductor layer and the second functional layer on the second semiconductor layer are fabricated simultaneously, so that the first and second functional layers located on the non-light-receiving surface of the solar cell have identical structures, and the second electrode is connected to the second semiconductor layer by a second conductive structure through the second functional layer, and the first electrode is connected to the first semiconductor layer by a first conductive structure through the first functional layer.

[0088] In a second alternative embodiment, the step of providing a silicon substrate comprises: depositing a second dielectric layer and a second semiconductor layer in sequence on the light-receiving surface of the silicon substrate; removing the second dielectric layer and the second semiconductor layer on the light receiving surface to expose a part of the light receiving surface; depositing a first dielectric layer and a first semiconductor layer in sequence on a non-light-receiving surface of a silicon substrate; and removing the first dielectric layer and the first semiconductor layer on the non-light-receiving surface to expose a portion of the non-light-receiving surface.

[0089] After fabricating the first and second semiconductor layers, the light-receiving surface of the silicon substrate is textured, cleaned, and textured to form a textured structure only on the exposed light-receiving surface, followed by depositing a passivation layer and depositing a second passivation layer on the textured structure on the light-receiving surface and on the second semiconductor layer, so that the first semiconductor layer and the exposed non-light-receiving surface are covered with the first passivation layer, a second electrode is connected to the second semiconductor layer by a second conductive structure through the second functional layer, and a first electrode is connected to the first semiconductor layer by a first conductive structure through the first functional layer.

[0090] The first functional layer may be fabricated by atomic layer deposition and / or plasma-enhanced vapor deposition, and the second functional layer may be fabricated by plasma-enhanced vapor deposition. Illustratively, the first functional layer may be fabricated by atomic layer deposition, or may be fabricated by plasma-enhanced vapor deposition. Alternatively, if the first functional layer has a two-layer structure, at least one layer may be fabricated by plasma-enhanced vapor deposition, and the other layer may be fabricated by atomic layer deposition.

[0091] Furthermore, to ensure the flatness of the first and second dielectric layers, the silicon substrate is polished and cleaned before depositing the first and second dielectric layers to remove metal ions and damage on the surface of the silicon substrate, which contributes to improving the photoelectric conversion efficiency of the solar cell.

[0092] In a third alternative embodiment, the step of providing a silicon substrate comprises: depositing a second semiconductor layer on the light-receiving surface of the silicon substrate; and depositing a first dielectric layer and a first semiconductor layer in sequence on the non-light-receiving surface of the silicon substrate.

[0093] Before the step of depositing the second semiconductor layer, the light-receiving surface of the silicon substrate is textured and cleaned, and a textured structure is formed on the textured light-receiving surface; after the step of depositing a first dielectric layer and a first semiconductor layer on the non-light-receiving surface, a second passivation layer is deposited on the second semiconductor layer on the light-receiving surface, and a first passivation layer is deposited on the first semiconductor layer; a second electrode penetrates the second functional layer and is connected to the second semiconductor layer by a second conductive structure; and a first electrode penetrates the first functional layer and is connected to the first semiconductor layer by a first conductive structure.

[0094] The technical solution of the present application will be further described below with reference to more specific examples and experimental test results.

[0095] Example 1 In the present embodiment, the doping concentration of the N-type conductive element in the first semiconductor layer is 5×10 20 atoms / cm 3and the doping concentration of the P-type conductive element in the second semiconductor layer is 5×10 19 atoms / cm 3 and the number of first conductive structures in any 1 mm × 1 mm area is 5 × 10 5 and the number of second conductive structures is 1×10 in any 1 mm×1 mm area where the second electrode and the second semiconductor layer are in contact. 5 The solar cell has a projection size of 1500 nm on the first semiconductor layer of any first conductive structure, and a projection size of 900 nm on the second semiconductor layer of any second conductive structure.

[0096] The present embodiment further provides a method for manufacturing the solar cell.

[0097] The step of providing a silicon substrate comprises: A polishing step is to select an N-type silicon wafer as a substrate, and polish, remove damage, remove lines, and clean oil stains on the surface of the N-type silicon wafer to form a flat and clean silicon substrate; a step of forming a second dielectric layer and a second semiconductor layer, in which the second dielectric layer and the second semiconductor layer are manufactured on the non-light-receiving surface by plasma vapor deposition, first introducing high-purity oxygen gas to grow the second dielectric layer at a temperature of 400°C to 650°C, then introducing high-purity SiH4 to manufacture a second amorphous silicon layer at a temperature of 450°C to 700°C, and finally introducing BCl3 at a temperature of 750°C to 1050°C to diffuse boron, thereby performing crystallization doping on the second amorphous silicon layer, and then forming the second semiconductor layer; removing the second semiconductor layer and the second dielectric layer by laser and wet alkaline etching to expose a portion of the non-light-receiving surface; The method includes the steps of forming a first dielectric layer and a first semiconductor layer on the non-light-receiving surface by chemical vapor deposition, introducing high-purity oxygen gas to grow the first dielectric layer at a temperature of 400°C to 650°C, then introducing high-purity SiH4 to form a first amorphous silicon layer at a temperature of 450°C to 700°C, and then introducing POCl3 at a temperature of 700°C to 950°C to diffuse phosphorus, and then crystallizing and doping the first amorphous silicon layer, and then forming the first semiconductor layer.

[0098] In the texturing and cleaning step, a chain-type HF device is used to remove the boron phosphorus silicon glass caused by boron / phosphorus diffusion on the light-receiving surface of the silicon substrate, and in a tank-type device, sodium hydroxide and TS40-type additives with a volume ratio of 7:1 are used, the temperature is maintained at 80°C, and the time is 7 minutes, thereby forming a texture structure on the light-receiving surface of the silicon substrate and controlling the thinning amount of the silicon substrate to 5 μm.

[0099] A first functional layer and a second functional layer are fabricated on the non-light-receiving surface of a silicon substrate by plasma-enhanced vapor deposition.

[0100] The paste for producing the first electrode is printed on the first functional layer and dried at 200°C. Then, the paste for producing the second electrode is printed on the second functional layer and dried at 200°C.

[0101] In the heat treatment step, a first conductive precursor is formed at the contact interface between the first electrode and the first semiconductor layer, and a second conductive precursor is formed at the contact interface between the second electrode and the second semiconductor layer, and the heat treatment temperature is 900°C.

[0102] In the light injection step, the first conductive precursor is transformed into a first conductive structure, the second conductive precursor is transformed into a second conductive structure, and the second electrode penetrates the second functional layer and is connected to the second semiconductor layer via the second conductive structure, and the first electrode penetrates the first functional layer and is connected to the first semiconductor layer via the first conductive structure; The light injection step includes: In the heating step, the first conductive precursor and the second conductive precursor are heated to 350°C, and then heated from 350°C to 500°C within 20 seconds, and then cooled to 350°C. When the temperature of the heating step is reduced from 500°C to 350°C, the solar cell is irradiated with light, the temperature of the light irradiation is 200°C, and the energy density of the light irradiation is 100 kW / m 2 and

[0103] Example 2 In this example, in the solar cell, the doping concentration of the N-type conductive element in the first semiconductor layer is 1×10 20 atoms / cm 3 and the doping concentration of the P-type conductive element in the second semiconductor layer is 9×10 19 atoms / cm 3 This is the only difference from the first embodiment.

[0104] Example 3 This example differs from Example 1 only in that the projected size of any of the first conductive structures on the first semiconductor layer is 500 nm, and the projected size of any of the second conductive structures on the second semiconductor layer is 1000 nm.

[0105] Example 4 This example differs from Example 1 only in that the solar cell structure of this example is a passivation contact solar cell, in which a second dielectric layer and a second semiconductor layer are provided on a portion of the light-receiving surface of the solar cell, and a first dielectric layer and a first semiconductor layer are provided on a portion of the non-light-receiving surface, and a structural schematic diagram of the manufactured solar cell is shown in Figure 7.

[0106] Example 5 This example differs from Example 1 only in that the solar cell structure of this example is a passivation contact solar cell, in which a second semiconductor layer is provided on the light-receiving surface of the manufactured solar cell, and a first dielectric layer and a first semiconductor layer are provided on the non-light-receiving surface, and a structural schematic diagram of the manufactured solar cell is shown in Figure 6.

[0107] Comparative Example 1 In this embodiment, the number of first conductive structures in any 1 mm×1 mm area is 5×10 4 In any 1 mm×1 mm area where the second electrode and the second semiconductor layer are in contact, the number of second conductive structures is 5×10 4 The only difference from Example 1 is that there are 1.

[0108] Comparative Example 2 This comparative example differs from Example 1 only in that the density of the first conductive structure is lower than the density of the second conductive structure.

[0109] Performance Test The solar cells manufactured in Examples 1 to 6 and Comparative Examples 1 and 2 were subjected to the following related tests.

[0110] In this application, the provided solar cells are subjected to performance tests such as open circuit voltage, short circuit current, and fill factor using a HALM test screening device. The HALM device is a device that simulates sunlight, and is further equipped with electronic loads, data collection and calculation devices, etc., to test the electrical performance of photovoltaic devices (including solar cells). The silicon wafer of the test solar cell is controlled to a 182mm size, and the calibrated light intensity is 1000±5W / m 2 The test temperature was controlled to 25°C ± 0.5°C, and the test results were as follows: Table 1. Solar cell performance test results [Table 1]

[0111] As can be seen from an analysis of the data of Examples 1 to 3 and Comparative Examples 1 and 2, the performance of the Examples is superior to that of the Comparative Examples. This is because the density of the first conductive structure in the Examples is greater than the density of the second conductive structure, and both are within the range of the present application, which contributes to improving the carrier diffusion ability in the first semiconductor layer and reduces the probability of carrier scattering and recombination, thereby improving the photoelectric conversion efficiency of the solar cell.

[0112] As can be seen from analyzing the data of Examples 1 and 2, the performance of Example 1 is superior to that of Example 2. This is because, in Example 1, the doping concentration of the N-type conductive element in the first semiconductor layer is high and the doping concentration of the P-type conductive element in the second semiconductor layer is low, resulting in a high carrier concentration in the first semiconductor layer and a high matching between the carrier concentration in the first semiconductor layer and the density of the first conductive structure, which promotes an improvement in the carrier transport speed, thereby improving the conductivity of the solar cell, reducing the probability of carrier recombination and scattering, and contributing to a significant improvement in the photoelectric conversion efficiency of the solar cell.

[0113] Analyzing the data of Examples 1 and 3, it can be seen that the performance of Example 1 is superior to that of Example 3. This is because in Example 1, the projection size of the first conductive structure on the first semiconductor layer is larger than that of Example 3, and the projection size of the second conductive structure on the second semiconductor layer is smaller than that of Example 3. Therefore, either of the first conductive structures in Example 1 has a higher content of transportable carriers, which effectively improves the carrier transport ability in the first semiconductor layer and effectively reduces the probability of carrier scattering and recombination in the first semiconductor layer, thereby improving the performance of the solar cell.

[0114] As can be seen from an analysis of the data in Examples 1, 4, and 5, whether the solar cell is a back-contact solar cell or a passivation-contact solar cell (including a solar cell in which a passivation contact structure is partially provided on both the light-receiving surface and the non-light-receiving surface, or a solar cell in which a passivation contact structure is provided only on the non-light-receiving surface), controlling the density of the first conductive structure to be greater than the density of the second conductive structure contributes to improving the carrier transport speed in either case, thereby improving the performance of the solar cell.

[0115] The solar cell, its manufacturing method, and photovoltaic module disclosed in the examples of the present application have been described in detail above, and the present specification uses specific examples to explain the principles and embodiments of the present application, but the explanation of the above examples is for understanding the technical solutions and core inventive points of the examples of the present application. At the same time, those skilled in the art can make any changes in the specific embodiments and application scope based on the concept of the present application, and the content of the present specification should not be construed as limiting the present application. [Explanation of symbols]

[0116] 1 silicon substrate, 21 first semiconductor layer, 22 second semiconductor layer, 31 first electrode, 32 second electrode, 41 first conductive structure, 411 first structure, 4111 first crystalline main chain, 4112 first crystalline side chain, 42 second conductive structure, 51 first dielectric layer, 52 second dielectric layer, 61 first functional layer, 62 second functional layer, 63 third functional layer, 7 first isolation region, 8 second isolation region.

Claims

1. A solar cell, A silicon substrate; a first semiconductor layer doped with an N-type conductive element and a second semiconductor layer doped with a P-type conductive element, the first semiconductor layer being provided on the silicon substrate; a first electrode electrically connected to the first semiconductor layer via a plurality of first conductive structures; a second electrode electrically connected to the second semiconductor layer via a plurality of second conductive structures; A solar cell, wherein the density of the first conductive structure is greater than the density of the second conductive structure.

2. In any 1 mm×1 mm area where the first electrode and the first semiconductor layer are in contact, the number of the first conductive structures is 1×10 ５ pieces ~ 1×10 ６ and the number of the second conductive structures in any 1 mm×1 mm area in contact with the second electrode and the second semiconductor layer is 5×10 ４ pieces ~ 5×10 ５ 2. The solar cell according to claim 1, wherein the number of solar cells is 1.

3. The solar cell of claim 1, characterized in that the projection size of the first conductive structure on the first semiconductor layer is equal to or larger than the projection size of the second conductive structure on the second semiconductor layer, the projection size of any of the first conductive structures on the first semiconductor layer is 100 nm to 2000 nm, and the projection size of any of the second conductive structures on the second semiconductor layer is 100 nm to 1000 nm.

4. The solar cell according to claim 1 , wherein the first conductive structure and the second conductive structure are both vein-shaped.

5. Any of the first conductive structures includes a plurality of strip-shaped first structures diverging in a direction of the first electrode; 5. The solar cell according to claim 4, wherein any one of the second conductive structures includes a plurality of strip-shaped second structures diverging in the direction of the second electrode.

6. Any of the first structures includes a first crystalline main chain and a plurality of first crystalline side chains extending in a direction different from the growth direction of the first crystalline main chain, The solar cell according to claim 5, characterized in that any of the second structures includes a second crystalline main chain and a plurality of second crystalline side chains extending in a direction different from the growth direction of the second crystalline main chain.

7. 7. The solar cell according to claim 6, wherein the first structure and the second structure are both formed by crystallization polymerization of a plurality of conductive fine particles.

8. 8. The solar cell according to claim 7, wherein the elements in the conductive fine particles include one or a combination of a silver element, an aluminum element, a copper element, and a lead element.

9. The doping concentration of the N-type conductive element in the first semiconductor layer is 1×10 ２０ atoms / cm ３ ~1 x 10 ２１ atoms / cm ３ and The doping concentration of the P-type conductive element in the second semiconductor layer is 1×10 １８ atoms / cm ３ ~1 x 10 ２０ atoms / cm ３ 2. The solar cell according to claim 1, wherein:

10. 2. The solar cell according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are provided on a non-light-receiving surface of the silicon substrate, the first semiconductor layer and the second semiconductor layer are isolated by an isolation region, and the first semiconductor layer and the second semiconductor layer are arranged in a fingerprint pattern.

11. 11. The solar cell according to claim 10, further comprising: a first dielectric layer provided between the first semiconductor layer and the silicon substrate; and a second dielectric layer provided between the second semiconductor layer and the silicon substrate.

12. 2. The solar cell according to claim 1, wherein the silicon substrate is N-type, the second semiconductor layer is provided on a light-receiving surface of the silicon substrate, the first semiconductor layer is provided on a non-light-receiving surface of the silicon substrate, and a first dielectric layer is further provided between the first semiconductor layer and the silicon substrate.

13. A plurality of the first semiconductor layers are provided on the non-light-receiving surface, each of the first semiconductor layers is provided in a partial region of the non-light-receiving surface, and adjacent first semiconductor layers are isolated by a first isolation region; and / or a plurality of the second semiconductor layers are provided on the light receiving surface, each of the second semiconductor layers is provided in a partial region of the light receiving surface, and two adjacent second semiconductor layers are isolated by a second isolation region; The solar cell of claim 12, wherein the second isolation region is provided with a textured structure.

14. A method for producing the solar cell according to any one of claims 1 to 13, comprising the steps of: providing a silicon substrate having the first semiconductor layer and the second semiconductor layer disposed thereon; applying a paste for manufacturing the first electrode to the first semiconductor layer and a paste for manufacturing the second electrode to the second semiconductor layer; a heat treatment step of forming a first conductive precursor at a contact interface between the first electrode and the first semiconductor layer and forming a second conductive precursor at a contact interface between the second electrode and the second semiconductor layer; and a light injection step of converting the first conductive precursor into a first conductive structure and converting the second conductive precursor into a second conductive structure to produce the solar cell.

15. The light injection step includes: a heating step of heating the first conductive precursor and the second conductive precursor, the peak temperature of the heating step being 400°C to 650°C; When the temperature of the heating step is reduced from the peak temperature to a predetermined temperature, the solar cell receives a voltage of 50°C to 400°C and an energy density of 10 kW / m ２ ~100kW / m ２ and applying light irradiation in which 15. The manufacturing method according to claim 14, wherein the predetermined temperature is 320°C to 360°C.

16. In the heating step, heating to the predetermined temperature; and heating the substrate from the predetermined temperature to the peak temperature within a predetermined time period of 10 seconds to 30 seconds, and then cooling the substrate to the predetermined temperature again.

17. the first conductive precursor includes a plurality of first crystalline main chains that all diverge toward the first electrode; The method according to claim 14 , wherein the second conductive precursor comprises a plurality of second crystalline main chains, each of which diverges toward the second electrode.

18. 15. The manufacturing method according to claim 14, wherein the temperature of the heat treatment is 700 to 900°C in the heat treatment step.

19. The step of providing a silicon substrate comprises: depositing a second dielectric layer and the second semiconductor layer in sequence on the non-light-receiving surface of the silicon substrate; performing a patterning process on the second dielectric layer and the second semiconductor layer located on the non-light-receiving surface to expose a portion of the non-light-receiving surface; depositing a first dielectric layer and the first semiconductor layer in sequence on the exposed non-light-receiving surface and the second semiconductor layer; 15. The method of claim 14, further comprising removing the first semiconductor layer and the first dielectric layer located on the second semiconductor layer to form an isolation region between the adjacent second semiconductor layer and the first semiconductor layer.

20. The step of providing a silicon substrate comprises: depositing the second semiconductor layer on a light-receiving surface of the silicon substrate; 15. The method of claim 14, further comprising the step of depositing a first dielectric layer and the first semiconductor layer in that order on the non-light-receiving surface of the silicon substrate.

21. A photovoltaic module, A photovoltaic module comprising the solar cell according to any one of claims 1 to 13, or a solar cell manufactured by the manufacturing method according to any one of claims 14 to 20.

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