Semiconductor equipment

Abstract

To provide a new shift register.SOLUTION: The semiconductor device includes a transistor 101, a transistor 102, a transistor 103, and a transistor 104. A first terminal of the transistor 101 is connected to the wiring 111, and a second terminal of the transistor 101 is connected to the wiring 112. A first terminal of the transistor 102 is connected to the wiring 113, and a second terminal of the transistor 102 is connected to the wiring 112. A first terminal of the transistor 103 is connected to the wiring 113, and a gate of the transistor 103 is connected to the wiring 111 or the wiring 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103, a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device, a display device, a display module, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. Therefore, one aspect of the present invention disclosed in this specification more specifically relates to The technical fields of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, and the like. One example is a driving method or a manufacturing method thereof. [Background technology]

[0003] In recent years, the development of shift registers consisting of transistors of the same polarity has been progressing. Patent Documents 1 and 2 disclose technologies relating to such shift registers. is shown. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-103226 [Patent Document 2] Japanese Patent Application Laid-Open No. 2005-050502 Summary of the Invention [Problem to be solved by the invention]

[0005] In the shift register shown in FIG. 7 of Patent Document 1, transistor M2 is turned on. However, when GOUT[N-1] is at a high level, the voltage VOFF is output. During this period, the transistor M2 is turned off, and the voltage VOFF is output. The gate of transistor M2 is connected to the gate of transistor M4. Therefore, when transistor M2 is turned on, transistor M4 is also turned on. When transistor M2 is turned on while GOUT[N-1] is at a high level, , the shift register does not work.

[0006] In the shift register shown in FIG. 7 of Patent Document 2, transistor Q53 or When the resistor Q56 turns on, the voltage VOFF is output. During a certain period, transistor Q53 is off, but transistor Q56 is is on, the voltage VOFF is output. However, to achieve this, Two transistors, Q53 and Q56, are required. , and has a large number of transistors.

[0007] An object of one embodiment of the present invention is to provide a novel circuit configuration. A novel circuit configuration applicable to a part of a shift register or a part of a sequential circuit included in the shift register One object of one embodiment of the present invention is to provide a voltage output period that is longer. Another object of the present invention is to provide a circuit configuration that can realize the above. , or to lengthen the period during which a transistor for outputting a voltage is turned on. One object of the present invention is to provide a circuit configuration in which the number of transistors can be reduced. An object of one embodiment of the present invention is to reduce power consumption. An object of one embodiment of the present invention is to reduce the layout area. An object of one embodiment of the present invention is to reduce the number of manufacturing steps. One of the challenges is to

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor device including first to fourth transistors. One of the source and drain of the first transistor is electrically connected to the first wiring. The other of the source and drain of the second transistor is electrically connected to the second wiring. One of the source and drain of the second transistor is electrically connected to the third wiring. The other of the source and drain of the third transistor is electrically connected to the second wiring. One of the source and drain of the fourth transistor is electrically connected to the third wiring. One of the source or drain of the first transistor is connected to the other of the source or drain of the third transistor. The other of the source and the drain of the fourth transistor is electrically connected to the first transistor. The gate of the fourth transistor is electrically connected to the gate of the second transistor. The gate of the transistor is electrically connected to the gate of the transistor.

[0010] In the semiconductor device, the gate of the third transistor is electrically connected to the first wiring. This may also be done.

[0011] In the semiconductor device, the gate of the third transistor is electrically connected to a fourth wiring. This may also be done.

[0012] In the semiconductor device, W (channel width) / L (channel length) of the fourth transistor is , may be larger than the W / L of the third transistor.

[0013] In the semiconductor device, the area where the semiconductor layer of the fourth transistor and the gate electrode overlap is , may be larger than the area where the semiconductor layer and the gate electrode of the third transistor overlap.

[0014] In the semiconductor device, at least one of the first to fourth transistors is made of an oxide semiconductor The semiconductor layer may have a channel forming region. [Effects of the Invention]

[0015] One aspect of the present invention can provide a novel circuit configuration. [Brief explanation of the drawings]

[0016] [Figure 1] Circuit diagram of a sequential circuit. [Figure 2] Timing chart of a sequential circuit. [Figure 3] Circuit diagram of a sequential circuit. [Figure 4] Circuit diagram of a sequential circuit. [Figure 5] Circuit diagram of a sequential circuit. [Figure 6] Circuit diagram of a sequential circuit. [Figure 7] Circuit diagram of a sequential circuit. [Figure 8] Circuit diagram of a sequential circuit. [Figure 9] Circuit diagram of a sequential circuit. [Figure 10] Circuit diagram of a sequential circuit. [Figure 11] Circuit diagram of a shift register. [Figure 12] 1 is a timing chart of a shift register. [Figure 13] FIG. 1 is a diagram showing a configuration of a semiconductor display device. [Figure 14] Top view of a pixel. [Figure 15] FIG. [Figure 16] 1A and 1B are diagrams illustrating a cross-sectional structure of a transistor. [Figure 17] FIG. [Figure 18] FIG. [Figure 19] Electronics illustration DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and the embodiments and aspects thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0018] One embodiment of the present invention is a semiconductor device using a transistor, such as an integrated circuit, an RF tag, or a semiconductor display device. The category includes all semiconductor devices. Processing circuit, DSP (Digital Signal Processor), microcomputer LSI (Large Scale Integrated Circuit) including controllers it), FPGA (Field Programmable Gate Array) and Programmable logic circuits (PLD: Programmable Logic Devices) such as CPLD (Complex PLD) The category includes semiconductors. Display devices include liquid crystal displays and organic light-emitting devices (OLEDs) that use light-emitting elements as pixels. Light-emitting devices, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Fi Circuit elements using semiconductor films, such as high-energy emission displays, are used as driving circuits. This category includes semiconductor display devices having a circuit.

[0019] In this specification, the semiconductor display device is a display device in which display elements such as liquid crystal elements and light emitting elements are formed in pixels. The panel is a module in which ICs including a controller are mounted on the panel. This category includes both.

[0020] For example, in this specification, when it is explicitly stated that X and Y are connected, When X and Y are electrically connected, when X and Y are functionally connected, This includes the case where X and Y are directly connected. For example, the present invention is not limited to the connection relationships shown in the drawings or text, but may be modified to include the connection relationships shown in the drawings or text. This also includes matters other than those in charge.

[0021] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). , etc.).

[0022] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. It is possible. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. The switch has the function of controlling whether or not the current flows. It has the function to switch between them.

[0023] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if X is transmitted to Y.

[0024] When it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. (i.e., there is another element or circuit between X and Y. X and Y are functionally connected (i.e., there is no other element or (X and Y are functionally connected via another circuit) and (X and Y are directly connected) (i.e., when X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that they are electrically connected, it is not enough to simply It is the same as if it were explicitly stated that the item is connected.

[0025] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or (not shown), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z 2 (or not), and is electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0026] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" The terminals of the transistor (or the first terminal) are electrically connected to each other. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of the transistor. and the drain (or second terminal, etc.) are electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this order of connection. By specifying the order of connections in the circuit configuration using a simple expression method, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above expressions. Here, X, Y, Z1, and Z2 are the coordinates of the object (for example, the , elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0027] The source of a transistor is the source region, or part of the semiconductor film that functions as the active layer. The term "source electrode" refers to a source electrode electrically connected to the semiconductor film. The drain is a drain region that is a part of the semiconductor film that functions as an active layer, or The term "gate" refers to the gate electrode electrically connected to the conductor film. do.

[0028] The source and drain of a transistor are determined by the channel type of the transistor and the characteristics given to each terminal. The name changes depending on the level of the potential applied. Generally, n-channel transistors are In a transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel transistor, the terminal to which a low potential is applied is called The terminal to which a high potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. Assuming that the source and drain are fixed, explain the connection relationship of the transistor. However, in reality, the names of source and drain are changed according to the above potential relationship. Replace.

[0029] (Embodiment 1) In this embodiment mode, a sequential circuit (also referred to as a semiconductor device) will be described.

[0030] An example of the configuration of a sequential circuit will be described with reference to Figure 1. Figure 1 is an example of a circuit diagram of a sequential circuit. The sequential circuit in FIG. 1 includes transistors 101 to 107 and a wiring 111. The wiring 115 is also included.

[0031] Note that the transistors 101 to 107 illustrated in FIG. 1 are N-channel transistors. However, the present invention is not limited to this, and the transistors 101 to 107 are P-channel transistors. The transistors 101 to 107 may be of the same conductivity type. This simplifies the manufacturing process and reduces costs compared to CMOS circuits. It is possible.

[0032] If the transistors 101 to 107 are N-channel transistors, The composition region can be made of an oxide semiconductor, amorphous silicon, or microcrystalline silicon. This simplifies the manufacturing process compared to when polycrystalline silicon is used for the channel formation region. In particular, the channel forming region can be formed without an oxide semiconductor. By using a conductor, the off-state current of the transistors 101 to 107 can be made extremely small. This allows for a reduction in power consumption.

[0033] The connection relationship of each transistor will be explained. The first terminal of the transistor 101 is connected to the wiring. The first terminal of the transistor 102 is connected to the wiring 111, and the second terminal is connected to the wiring 112. The first terminal of the transistor 1 is connected to a wiring 113, and the second terminal of the transistor 1 is connected to a wiring 112. 03 has a first terminal connected to a wiring 113 and a gate connected to a wiring 111. The first terminal of the transistor 104 is connected to the second terminal of the transistor 103. is connected to the gate of transistor 101, and its gate is connected to the gate of transistor 102. The first terminal of the transistor 105 is connected to the wiring 114, and the second terminal of the transistor 105 is connected to the wiring 114. The gate of the transistor 101 is connected to the wiring 115. 06 has a first terminal connected to the wiring 115 and a second terminal connected to the gate of the transistor 102. and a gate connected to a wiring 115. The transistor 107 has a first terminal connected to a wiring 115. The first terminal is connected to the line 113, the second terminal is connected to the gate of the transistor 102, and the gate is connected to the transistor 103. The gate of the transistor 101 is connected to the gate of the transistor 102. In this way, a novel circuit configuration can be provided. can.

[0034] The gate of the transistor 101 is indicated as a node N1, and the gate of the transistor 102 is indicated as a node N2. This is denoted as node N2.

[0035] An example of a signal or voltage input to each wiring will be described. A voltage VSS is input to the wiring 113, and a signal SP is input to the wiring 114. A signal CK2 is input to the wiring 115. The signals CK1, CK2, and SP Based on this, the signal OUT is output to the wiring 112. There is a lock signal. The signal CK1 and the signal CK2 are out of phase with each other. The signal SP is There is a start pulse (also called a set signal). The voltage VSS can be the power supply voltage or the ground voltage. The signal OUT is the output signal of the sequential circuit.

[0036] For convenience, the high-level potential of the signals CK1, CK2, and SP is VD D (VDD>VSS), and the low-level potential is VSS.

[0037] Note that one embodiment of the present invention also includes a case where no signal or voltage is input to each wiring. For example, each wiring may be any wiring that can receive the above signals or voltages.

[0038] The function of each transistor will be described below.

[0039] The transistor 101 controls conduction between the wiring 111 and the wiring 112 or between the wiring 112 and the transistor 101 based on the potential of the node N1. The transistor 101 controls the non-conduction of the signal CK By supplying 1 to the wiring 112, the signal OUT is set to a high level.

[0040] The transistor 102 turns on or off the wiring 113 and the wiring 112 based on the potential of the node N2. The transistor 102 controls the voltage VS based on the potential of the node N2. By supplying S to the wiring 112, the signal OUT is set to low level.

[0041] The transistor 103 connects the wiring 113 and the first terminal of the transistor 104 based on the signal CK1. The transistor 104 controls conduction or non-conduction between the node N1 and the transistor 104 based on the potential of the node N2. Based on this, conduction or non-conduction between the second terminal of the transistor 103 and the node N1 is controlled. That is, the circuit including the transistor 103 and the transistor 104 is connected to the signal CK1 and the The conduction or non-conduction between the wiring 113 and the node N1 is controlled based on the potential of the node N2. The circuit including the transistors 103 and 104 is connected to the signal CK1 and the node N 2, the voltage VSS is supplied to the node N1, thereby The value is set so that transistor 101 is turned off.

[0042] The transistor 105 turns on or off the connection between the wiring 114 and the node N1 based on the signal CK2. Then, the transistor 105 controls the signal SP based on the signal CK2 to the node N1. , the potential of the node N1 is set to a value at which the transistor 101 is turned on. Thereafter, transistor 105 turns off the node N1 by cutting off the supply of signal SP to node N1. Put node N1 in a floating state.

[0043] The transistor 106 turns on or off the connection between the wiring 115 and the node N2 based on the signal CK2. Then, the transistor 106 controls the signal CK2 to the node N 2, the potential of node N2 is supplied to transistors 102 and 103. Set the value to 4 to turn it on.

[0044] The transistor 107 controls conduction between the wiring 113 and the node N2 or between the wiring 113 and the node N3 based on the potential of the node N1. The transistor 107 controls the voltage VS based on the potential of the node N1. By supplying S to node N2, the potential of node N2 is increased by transistor 102 and transistor The value is set to a value at which the transistor 104 turns off.

[0045] An example of the operation of the sequential circuit of FIG. 1 will be described with reference to FIGS. 2 to 4. FIG. 2 shows the operation of the signal C K1, signal CK2, signal SP, and the potential of node N1 (V N1), the potential of node N2 (V N2 3A is a timing chart showing an example of the signal OUT from time t1 to time t 3(B) is a schematic diagram of the operation during the period t2 to t3 (also referred to as period T1). 4A is a schematic diagram of the operation during the period T2, and FIG. 4B is a schematic diagram of the operation during the period T3 to t4 (period T5). 4B is a schematic diagram of the operation from time t4 to t5 (period T4 This is a schematic diagram of the operation in the

[0046] The signals CK1 and CK2 shown in FIG. 2 are at a high level during one cycle. The periods when the signal CK1 is at a low level are equal to each other, and the phase difference is 180°. The signal SP shown in FIG. 2 has a pulse width of 1 / 2. The period is a half period of the signal CK1 or the signal CK2.

[0047] First, at time t1, the signal SP goes high and the signal CK1 goes low. , signal CK2 becomes high level.

[0048] The potential of the node N1 is as follows: Since the signal CK2 is at a high level, the transistor Also, since the signal CK1 is at a low level, the transistor 103 is turned on. As will be described later, the potential of node N2 becomes high, and the transistor Therefore, a high level signal SP is applied to the node N1, and the transistor 104 is turned on. Since the potential of the node N1 is supplied via the potential Vcc of the node N2, the potential of the node N1 rises. is the value obtained by subtracting the threshold voltage of the transistor 105 from the gate potential of the transistor 105, i.e., That is, the value obtained by subtracting the threshold voltage of the transistor 105 from the high level potential of the signal CK2 (VDD When the voltage rises to −Vth105, the transistor 105 turns off. The node N1 is in a floating state, and the potential of the node N1 is maintained at VDD-Vth105. do.

[0049] The potential of the node N2 is as follows: Since the signal CK2 is at a high level, the transistor In addition, the potential of the node N1 becomes high, so that the transistor 107 Therefore, a high level signal CK2 is applied to the node N1 to turn on the transistor 106. The voltage VSS is supplied through the transistor 107. Therefore, the potential of the node N2 is determined by the resistance ratio of the transistor 106 and the transistor 107. Here, the transistor 106 has a larger source and drain than the transistor 107. The resistance between the node N1 and the node N2 is sufficiently small. Specifically, the potential of the node N2 is set to a value slightly higher than that of the transistor 102. The potential of the first terminal is higher than the sum of the potential of the first terminal and the threshold voltage of the transistor 102, and the potential of the transistor a value higher than the sum of the potential of the first terminal of transistor 104 and the threshold voltage of transistor 104, i.e., is higher than the sum of the voltage VSS and the threshold voltage of the transistor 102 (VSS+Vth102), And the sum of the voltage VSS and the threshold voltage of the transistor 104 (VSS+Vth104) It will be a high value.

[0050] The potential of the wiring 112 is as follows: Since the potential of the node N1 is high, The potential of the node N2 becomes high, so that the transistor 101 is turned on. Therefore, a low-level signal CK1 is applied to the wiring 112, and the transistor 101 and the voltage VSS is supplied through transistor 102. The potential of the wiring 112 becomes VSS, that is, the signal OUT becomes low.

[0051] Next, at time t2, the signal SP goes low and the signal CK1 goes high. , the signal CK2 goes low.

[0052] The potential of the node N1 is as follows: Since the signal CK2 is at a low level, the transistor The signal CK1 goes high, so the transistor 103 As will be described later, the potential of the node N2 becomes VSS, and the transistor 10 4 is turned off. Therefore, the node N1 remains in a floating state, and the potential of the node N1 is VD However, as will be described later, as the potential of the wiring 112 rises, This causes the potential of the node N1 to further rise.

[0053] The potential of the node N2 is as follows: Since the signal CK2 is at a low level, the transistor In addition, the potential of the node N1 becomes high, so that the transistor 107 Therefore, the voltage VSS is applied to the node N2 through the transistor 107. As a result, the potential of the node N2 becomes VSS.

[0054] The potential of the wiring 112 is as follows: Since the potential of the node N1 remains high, The transistor 101 remains on. Also, the potential of the node N2 becomes VSS. Therefore, the wiring 112 is connected to the high-voltage terminal via the transistor 101. Since the signal CK1 of the high level is supplied, the potential of the wiring 112 rises. The parasitic capacitance between the gate and the second terminal of the transistor 101 causes a The potential difference between the node N1 and the wiring 1 is maintained. As the potential of node N1 rises, the potential of node N1 also rises. is the sum of the potential of the first terminal of the transistor 101 and the threshold voltage of the transistor 101, i.e., The sum of the high level potential of the signal CK1 and the threshold voltage of the transistor 101 (VDD+Vth 101) becomes higher than the potential of the wiring 112. That is, the signal OUT becomes high level.

[0055] Next, at time t3, the signal SP remains at a low level, and the signal CK1 goes low. and the signal CK2 becomes high level.

[0056] The potential of the node N1 is as follows: Since the signal CK2 is at a high level, the transistor The signal CK1 goes low, so the transistor 103 turns off. As will be described later, the potential of the node N2 becomes high, and therefore the transistor 10 Therefore, a low level signal SP is input to node N1, and node The potential of the node N1 becomes VSS.

[0057] The potential of the node N2 is as follows: Since the signal CK2 is at a high level, the transistor Also, the potential of the node N1 becomes VSS, so the transistor 107 Therefore, a high level signal CK2 is applied to the node N2 to turn the transistor 106 off. Since the voltage at the node N2 is supplied via the The potential at the gate of transistor 106 minus the threshold voltage of transistor 106, i.e., the signal The value obtained by subtracting the threshold voltage of the transistor 106 from the high level potential of CK2 (VDD-Vt When the voltage at node N2 rises to h106, transistor 106 turns off. is put into a floating state, and the potential of the node N2 is maintained at VDD-Vth106.

[0058] The potential of the wiring 112 is as follows: Since the potential of the node N1 becomes VSS, The potential of the node N2 becomes high, so that the transistor 101 is turned off. 2 is turned on. Therefore, the voltage VSS is supplied to the wiring 112 via the transistor 102. Therefore, the potential of the wiring 112 becomes VSS. That is, the signal OUT becomes low.

[0059] Next, at time t4, the signal SP remains at a low level, and the signal CK1 goes to a high level. and the signal CK2 becomes low level.

[0060] The potential of the node N1 is as follows: Since the signal CK2 is at a low level, the transistor Also, since the signal CK1 becomes high level, the transistor 103 As will be described later, the potential of node N2 remains high, so that the transistor Therefore, the voltage VSS is applied to the node N1 through the transistor 103. and is supplied via the transistor 104, the potential of the node N1 remains at VSS. do.

[0061] The potential of the node N2 is as follows: Since the signal CK2 is at a low level, the transistor In addition, the potential of the node N1 becomes VSS, so that the transistor 107 Therefore, the node N2 is in a floating state, and the potential of the node N2 is VDD- Maintained at Vth106.

[0062] The potential of the wiring 112 is as follows: Since the potential of the node N1 remains at VSS, The transistor 101 remains off. Also, the potential of the node N2 remains high. Therefore, the voltage VSS is applied to the wiring 112. Since the potential of the wiring 112 remains VSS, the potential of the wiring 112 remains VSS. That is, the signal OUT remains at a low level.

[0063] After time t5, the signals CK1 and CK2 are held constant until the signal SP goes high again. Each time the voltage is inverted, the operation from time t3 to t4 and the operation from time t4 to t5 are repeated. vinegar.

[0064] An example of the effect achieved by the sequential circuit of FIG. 1 will be described.

[0065] A novel circuit configuration can be provided.

[0066] During the period T1, the transistor 103 is turned off, and the gate of the transistor 102 is turned off. The gate of the transistor 104 can be connected to the gate of the transistor 104, and the period T1, the period T In periods T3 and T4, the transistor 102 can be turned on. The period during which the resistor 102 is on can be extended, and the voltage VSS can be supplied to the line 112. In addition, the period during which the transistor 102 is turned on alternately with the transistor 103 can be increased. Since there is no need to provide a transistor, the number of transistors can be reduced. The on / off of the transistor 102 and the transistor 104 is controlled by a common signal or a common circuit. Since the control is possible, it is possible to reduce the number of signals or the circuit scale.

[0067] By connecting the transistor 104 between the transistor 103 and the node N1, Fluctuations in the potential of the gate of the transistor 103 can be made less likely to be transmitted to the node N1. Therefore, the potential of the node N1 can be stabilized, and malfunctions can be suppressed.

[0068] It is possible to provide a circuit configuration that can achieve the above-mentioned effects.

[0069] W (channel width) and L (channel length) of the transistors 101 to 107 An example will be described.

[0070] The load of the wiring 112 is often larger than the load of the node N1 and the load of the node N2. Therefore, the W / L of the transistor 101 is larger than the W / L of the transistor 103. It is preferable that the W / L of the transistor 101 is larger than the W / L of the transistor 104. It is preferable that the W / L of the transistor 101 is larger than the W / L of the transistor 105. It is preferable that the W / L of the transistor 101 is larger than the W / L of the transistor 106. It is preferable that the W / L of the transistor 101 is larger than the W / L of the transistor 107. It is also preferable that the W / L of the transistor 102 is larger than that of the transistor 103. It is preferable that the W / L of transistor 102 is larger than the W / L of transistor 104. It is preferable that the W / L of transistor 102 is greater than the W / It is preferable that the W / L of transistor 102 is greater than the W / L of transistor 106. It is preferable that W / L of transistor 102 is larger than W / L of transistor 107. It is preferable that the W / L is larger than the W / L. Since the current supply capacity of 02 can be increased, the change in the signal OUT can be made steeper. In addition, the load on the wiring 112 can be increased. 3 to 107 can be reduced in size, the layout of the sequential circuit can be improved. The area required for installation can be reduced.

[0071] The load on node N1 is often larger than the load on node N2. The W / L of transistor 105 is preferably greater than the W / L of transistor 106. The W / L of 105 is preferably greater than the W / L of transistor 107. Since the current supply capability of the transistor 105 can be increased, the potential of the node N1 can be increased This allows for quick changes, which increases the operating speed of sequential circuits. Since the size of the transistor 106 and the transistor 107 can be reduced, the sequential circuit The layout area of ​​the road can be reduced.

[0072] Transistor 105 is turned on to change the potential of node N1, while transistor The transistor 103 and the transistor 104 are turned on to maintain the potential of the node N1. Therefore, the W / L of the transistor 105 is larger than the W / L of the transistor 103. It is preferable that the W / L of the transistor 105 is larger than the W / L of the transistor 104. In this way, the current supply capability of the transistor 105 can be increased. Therefore, the potential of the node N1 can be changed quickly, and the operating speed of the sequential circuit can be increased. On the other hand, by reducing the sizes of the transistors 103 and 104, This allows the layout area of ​​the sequential circuit to be reduced.

[0073] The transistor 103 and the transistor 104 are connected in series between the wiring 113 and the node N1. The transistor 107 is connected between the wiring 113 and the node N2. In addition, the load on node N1 is often larger than the load on node N2. Therefore, it is preferable that the W / L of the transistor 103 is larger than the W / L of the transistor 107. Also, the W / L of the transistor 104 is larger than the W / L of the transistor 107. In this way, it is preferable to increase the current supply capacity of the transistor 103 and the transistor 104. Since the potential of the node N1 can be reduced quickly, The operating speed of the circuit can be improved. In addition, the potential of the node N1 can be reliably maintained at VSS. Therefore, it is possible to maintain the voltage of the transistor 107 and prevent malfunction. Since the size can be reduced, the layout area of ​​the sequential circuit can be reduced. Cut.

[0074] The smaller the area where the semiconductor layer and the gate electrode of the transistor 103 overlap, the The potential of the gate of the transistor 103 is not easily transmitted to the node N1. When the area where the semiconductor layer and the gate electrode overlap is reduced, the current supply capability of the transistor 103 is reduced. Therefore, it is preferable to increase the current supply capacity of the transistor 104. Therefore, the area where the semiconductor layer of the transistor 104 overlaps with the gate electrode is preferably It is preferable that the area is larger than the area where the semiconductor layer of the transistor 103 and the gate electrode overlap. Preferably, the W / L of the transistor 104 is greater than the W / L of the transistor 103. Alternatively, the W×L of the transistor 104 is preferably larger than the W×L of the transistor 103. It is preferable that it is large.

[0075] The resistance between the source and drain of transistor 106 is higher than that of transistor 107. To be small enough, the W / L of transistor 106 is smaller than the W / L of transistor 107. It is preferable that the thickness is larger than the thickness of the slab.

[0076] A modified example of the sequential circuit of FIG. 1 will be described. However, parts common to FIG. 1 are designated by the same reference numerals. are not shown, and the description thereof will be omitted.

[0077] As shown in FIG. 5A, the gate of the transistor 105 may be connected to a wiring 114. The transistor 105 shown in FIG. 5A supplies the signal SP to the node N1 based on the signal SP. Therefore, it is possible to prevent malfunctions due to a timing difference between the signal SP and the signal CK2. can be done.

[0078] As shown in FIG. 5B, the first terminal of the transistor 105 is connected to the wiring 115. The gate of the transistor 105 may be connected to the wiring 114. 105 supplies a signal CK2 to the node N1 based on the signal SP. Since the potential change can be made steeper, the operating speed of the sequential circuit can be improved. do.

[0079] As shown in FIG. 5C, the first terminal of the transistor 105 is connected to the wiring 117. The gate of the transistor 105 may be connected to the wiring 114. The wiring 117 is supplied with a voltage VDD. The transistor 105 shown in FIG. 5C outputs the voltage VDD to the node 102 based on the signal SP. Therefore, the change in the potential of the node N1 can be made steep, The operating speed of the circuit can be improved.

[0080] Note that two of the transistors 105 shown in FIGS. 1, 5A, 5B, and 5C For example, as shown in FIG. 5(D), the sequential circuit may include one or more of the A transistor 105A corresponding to the transistor 105 and a transistor 105B shown in FIG. A transistor 105B corresponding to 05 may be provided.

[0081] As shown in FIG. 6A, the first terminal of the transistor 107 may be connected to a wiring 115. The transistor 107 shown in FIG. 6A outputs a signal CK2 based on the potential of the node N1. The signal CK2 is at a high level during the period T1. Therefore, a through current can be prevented from occurring in the transistors 106 and 107. Therefore, power consumption can be reduced. Since it is not necessary to increase the size of the sequential circuit, the layout area of ​​the sequential circuit can be reduced.

[0082] As shown in FIG. 6B, the first terminal of the transistor 107 may be connected to the wiring 114. The transistor 107 shown in FIG. 6B outputs the signal SP to the node N1 based on the potential of the node N1. Since the signal SP is at a high level during the period T1, Therefore, a through current can be prevented from occurring in the transistors 106 and 107. Therefore, power consumption can be reduced. Since there is no need to increase the size, the layout area of ​​the sequential circuit can be reduced.

[0083] As shown in FIG. 6C, the gate of the transistor 107 may be connected to a wiring 112. The transistor 107 shown in FIG. 6C supplies the voltage VSS to the node N2 based on the signal OUT. Since the signal OUT is at a low level during the period T1, Therefore, the transistor 107 can be turned off during the period T1. 6 and transistor 107, the through current can be prevented, and the power consumption can be reduced. In addition, since there is no need to increase the W / L of the transistor 106, The layout area of ​​the sequential circuit can be reduced.

[0084] As shown in FIG. 6D, the first terminal of the transistor 107 is connected to the wiring 115. The gate of the transistor 107 may be connected to the wiring 112. 107 supplies a signal CK2 to the node N2 based on the signal OUT. The signal OUT is supplied during the period T Since the signal goes low in period T1, the transistor 107 is turned off in period T2. Therefore, the voltage generated in the transistors 106 and 107 during the period T1 can be This prevents the through current from flowing through the transistor, thereby reducing power consumption. Since it is not necessary to increase the W / L of the transistor 106, the layout area of ​​the sequential circuit is reduced. It is possible to make small plans.

[0085] As shown in FIG. 6E, the first terminal of the transistor 107 is connected to the wiring 114. The gate of the transistor 107 may be connected to the wiring 112. 107 supplies a signal SP to the node N2 based on the signal OUT. The signal OUT is supplied during the period T1 Since the signal goes low during the period T1, the transistor 107 is turned off during the period T2. Therefore, the voltage generated in the transistors 106 and 107 during the period T1 can be This can prevent through current from flowing through the transistors, thereby reducing power consumption. Since there is no need to increase the W / L of the transistor 106, the layout area of ​​the sequential circuit is reduced. This can be achieved.

[0086] As shown in FIG. 7A, the first terminal of the transistor 106 may be connected to a wiring 117. The transistor 106 shown in FIG. 7A applies the voltage VDD to the node N This allows a low-level signal to be supplied to node N2 due to timing errors, etc. This can prevent the supply of the ion beam.

[0087] As shown in FIG. 7B, the first terminal of the transistor 106 is connected to the wiring 118. The gate of the transistor 106 may be connected to a wiring 118. The wiring 118 receives a signal CK3. The signal CK3 is a clock signal. However, the signal CK3 is the same as the signal CK1. The transistor 106 shown in FIG. 7B is driven based on the signal CK3. The signal CK3 is supplied to the node N2.

[0088] As shown in FIG. 7C, the first terminal of the transistor 106 is connected to the wiring 117. The gate of the transistor 107 may be connected to the wiring 118. 106 supplies the voltage VDD to the node N2 based on the signal CK3. This prevents a low-level signal from being supplied to node N2 due to timing misalignment or the like. This can be done.

[0089] As shown in FIG. 8A, the first terminal of the transistor 104 is connected to the wiring 113. A first terminal of the transistor 103 is connected to a second terminal of the transistor 104. The second terminal of 103 may be connected to node N1.

[0090] As shown in FIG. 8B, the gate of the transistor 103 may be connected to a wiring 119. A signal CK4 is input to the wiring 119, and the signal CK4 is transmitted to the transistor 1 The signal CK4 is a clock signal. 4 is out of phase with signals CK1 and CK2.

[0091] Although not shown, the gate of the transistor 103 may be connected to the wiring 118.

[0092] Although not shown, the first terminal is connected to the node N1, and the second terminal is connected to the wiring 112. A capacitive element may be provided.

[0093] Although not shown, the first terminal of the transistor 102 is connected to a wiring different from the wiring 113. For example, a voltage higher than the voltage VSS may be supplied to the wiring. Therefore, the current generated in the transistor 101 and the transistor 102 can be reduced.

[0094] Although not shown, the gate of the transistor 102 is connected to the wiring 115, the wiring 118, or the wiring 11. May be connected to 9.

[0095] The above-described sequential circuits shown in FIGS. 1, 5 to 8, etc. may be freely combined. For example, when the first terminal of the transistor 106 is connected to the wiring 117 as shown in FIG. In both cases, the first terminal of the transistor 107 is connected to the wiring 115 as shown in FIG. As another example, as shown in FIG. 7A, a transistor 10 The first terminal of the transistor 6 is connected to the wiring 117, and as shown in FIG. The gate of the transistor 103 may be connected to a wiring 119 (see FIG. 9B).

[0096] One embodiment of the present invention includes the following configuration within its category.

[0097] One embodiment of the present invention is a transistor 101, a transistor 102, a transistor 103, and The first terminal of the transistor 101 is connected to a wiring 111. The second terminal of the transistor 101 is connected to the wiring 112. The first terminal of the transistor 101 is connected to a wiring 113, and the second terminal of the transistor 102 is connected to a wiring 112. The first terminal of the transistor 103 is connected to the wiring 113. The gate of the transistor 104 is connected to the wiring 111. The second terminal of the transistor 104 is connected to the second terminal of the transistor 101. The gate of transistor 104 is connected to the gate of transistor 102. (See FIG. 10(A)).

[0098] One embodiment of the present invention is a transistor 101, a transistor 102, a transistor 103, and The first terminal of the transistor 101 is connected to a wiring 111. The second terminal of the transistor 101 is connected to the wiring 112. The first terminal of the transistor 101 is connected to a wiring 113, and the second terminal of the transistor 102 is connected to a wiring 112. The first terminal of the transistor 103 is connected to the wiring 113. The gate of the transistor 104 is connected to the wiring 119. The second terminal of the transistor 104 is connected to the second terminal of the transistor 101. The gate of transistor 104 is connected to the gate of transistor 102. (See FIG. 10(B)).

[0099] This embodiment may be appropriately combined with the configurations disclosed in the present specification and the like of other embodiments. This can be implemented.

[0100] (Embodiment 2) In this embodiment, a shift register (also called a semiconductor device) using the sequential circuit of the first embodiment is We will explain about (c).

[0101] An example of the configuration of the shift register will be described with reference to FIG. 1 is an example of a circuit diagram of a starter.

[0102] The shift register in FIG. 11 includes sequential circuits 100[1] to 100[N] (N is 2 or more). 11, sequential circuits 100[1] to 100[2] are shown. Only the sequential circuits 100[1] to 100[N] are shown. However, the sequential circuits 100[1] to 100[N] are The sequential circuit is not limited to the sequential circuit of FIG. 11, and may be any other sequential circuit disclosed in the present specification, such as the first embodiment. The road may be adopted.

[0103] The shift register in FIG. 11 includes wirings 121[1] to 121[N], wiring 122, and wiring 123, wiring 124, and wiring 125. In either one of the above, the wiring 111 is connected to one of the wiring 123 and the wiring 124, The line 112 is connected to the line 121[i], the line 113 is connected to the line 125, and the line 11 4 is connected to the wiring 121[i-1], and the wiring 115 is connected to the other of the wiring 123 and the wiring 124. The sequential circuit 100[1] is sequential at the point where the wiring 114 is connected to the wiring 122. The circuit 100[i] is different from the circuit 100[i]. For example, in the odd-numbered stages, the wiring 111 and the wiring 115 are connected to opposite locations. When 11 is connected to the wiring 123 and the wiring 115 is connected to the wiring 124, in the even-numbered stages, , the wiring 111 is connected to the wiring 124 , and the wiring 115 is connected to the wiring 123 .

[0104] Signals SOUT[1] to SOUT[N] are output from wirings 121[1] to 121[N]. Each of the wirings 121[1] to 121[N] is connected to the wiring 112. Each of the signals SOUT[1] to SOUT[N] corresponds to the signal OUT. A signal SSP is input to the line 122. The line 122 corresponds to the line 114, and the signal SSP is In particular, in the sequential circuit 100[i], the wiring 121[i-1] corresponds to the wiring 1 14, and the signal SOUT[i-1] corresponds to the signal SP. The signal K1 is input to the wiring 123, and the signal SCK2 is input to the wiring 124. corresponds to one of the wirings 115, and the signal SCK1 corresponds to one of the signals CK1 and CK2. The wiring 124 corresponds to the other of the wiring 111 and the wiring 115, and the signal SCK2 corresponds to the signal This corresponds to the other of the signal CK1 and the signal CK2. The voltage VSS is supplied to the wiring 125. 125 corresponds to the wiring 113 .

[0105] An example of the operation of the shift register of FIG. 11 will be described with reference to FIG. 12. Signal SCK1, signal SCK2, signal SSP, the potential of node N1 of the sequential circuit 100[1] (V N1 ), the potential of the node N2 of the sequential circuit 100[1] (V N2 ), signal SOUT[1], signal 10 is a timing chart showing an example of a signal SOUT[2] and a signal SOUT[3].

[0106] First, at time t1, the signal SCK1 goes low and the signal SCK2 goes high. The sequential circuit 100[1] in the first embodiment is In order to perform the operation during the period T1 described above, the signal SOUT[1] becomes low level. The circuit 100[2] performs the operation during the period T4 described in the first embodiment. The signal SOUT[2] becomes low level. To perform the operation during the period T3 described above, the signal SOUT[3] becomes low level.

[0107] Next, at time t2, the signal SCK1 goes high and the signal SCK2 goes low. The sequential circuit 100[1] in the first embodiment is In order to perform the operation during the period T2 described above, the signal SOUT[1] becomes high level. The circuit 100[2] performs the operation during the period T1 described in the first embodiment. The signal SOUT[2] becomes low level. To perform the operation during the period T4 described above, the signal SOUT[3] becomes low level.

[0108] Next, at time t3, the signal SCK1 goes low and the signal SCK2 goes high. The sequential circuit 100[1] in the first embodiment is In order to perform the operation during the period T3 described above, the signal SOUT[1] becomes low level. The circuit 100[2] performs the operation during the period T2 described in the first embodiment. The signal SOUT[2] becomes high level. To perform the operation during the period T1 described above, the signal SOUT[3] becomes low level.

[0109] Next, at time t4, the signal SCK1 goes high and the signal SCK2 goes low. The sequential circuit 100[1] in the first embodiment is In order to perform the operation during the period T4 described above, the signal SOUT[1] becomes low level. The circuit 100[2] performs the operation during the period T3 described in the first embodiment. The signal SOUT[2] becomes low level. To perform the operation during the period T2 described above, the signal SOUT[3] becomes high level.

[0110] This embodiment may be appropriately combined with the configurations disclosed in the present specification and the like of other embodiments. This can be implemented.

[0111] (Embodiment 3) <Configuration Example of Semiconductor Display Device> Next, a structural example of a semiconductor display device according to one embodiment of the present invention will be described.

[0112] In the semiconductor display device 70 shown in FIG. 13A, a pixel section 71 includes a plurality of pixels 55 and a pixel 5 5, the wiring GL1 to wiring GLy (y is natural) corresponding to the bus lines for selecting each row. and a wiring GL for supplying an image signal to a selected pixel 55. 1 to SLx (x is a natural number). The input of the signal is controlled by the driving circuit 72. The input of the image signal to the wiring SL is The pixels 55 are controlled by a driving circuit 73. The pixels 55 are connected to at least one of the wirings GL. Each of the wirings SL is connected to at least one of the wirings SL.

[0113] Specifically, the driver circuit 72 generates a signal for sequentially selecting the wirings GL1 to GLy. Specifically, the driver circuit 73 has a shift register 75 which sequentially outputs pulses. a shift register 76 that generates a signal corresponding to the shift signal; a switch circuit 77 for controlling the supply of image signals to the wirings SL1 to SLx; .

[0114] The sequential circuit or shift register according to one embodiment of the present invention is a shift register 75 or a shift In this case, for example, the wirings GL1 to GLy can be used as the resistor 76. Each of these corresponds to the wiring 112.

[0115] The type and number of wirings provided in the pixel section 71 depend on the configuration, number and arrangement of the pixels 55. Specifically, in the case of the pixel section 71 shown in FIG. 13A, the pixel area can be determined by the following formula: The pixels 55 in the row are arranged in a matrix, and the wirings SL1 to SLx and the wiring GL1 10 shows an example in which the wirings GLy are arranged inside the pixel portion 71.

[0116] In FIG. 13A, the driver circuit 72 and the driver circuit 73 are formed on a single substrate together with the pixel section 71. Although the example shows a case where the driving circuits 72 and 73 are formed on a substrate, the driving circuits 72 and 73 are formed on a substrate. It may be formed on a substrate different from that of 71.

[0117] 13B shows an example of the configuration of a pixel 55. Each pixel 55 includes a liquid crystal element 60 a transistor 56 for controlling the supply of an image signal to the liquid crystal element 60; The liquid crystal element 60 has a capacitance element 57 for holding the voltage between the pixel electrode and the common electrode. The liquid crystal display includes a pixel electrode, a common electrode, and a liquid crystal material to which a voltage is applied between the pixel electrode and the common electrode. and a liquid crystal layer.

[0118] The transistor 56 controls whether or not the potential of the wiring SL is applied to the pixel electrode of the liquid crystal element 60. A predetermined potential is applied to the common electrode of the liquid crystal element 60.

[0119] The specific connection configuration between the transistor 56 and the liquid crystal element 60 will be described below. In B), the gate of the transistor 56 is connected to one of the wirings GL1 to GLy. One of the source and drain of the transistor 56 is connected to the line SL1. Lx, and the other of the source and drain of the transistor 56 is connected to the liquid crystal It is connected to the pixel electrode of the element 60 .

[0120] In the liquid crystal element 60, the voltage applied between the pixel electrode and the common electrode changes depending on the voltage contained in the liquid crystal layer. The orientation of the liquid crystal molecules contained in the liquid crystal element 60 changes, and the transmittance changes. The transmittance is controlled by the potential of the image signal applied to the In each of the plurality of pixels 55 included in the pixel section 71, the liquid crystal element The gray scale of the pixel 60 is adjusted in accordance with an image signal having image information, and an image is displayed on the pixel section 71. is displayed.

[0121] In FIG. 13B, in the pixel 55, a switch that controls the input of an image signal to the pixel 55 is However, the case where one transistor 56 is used as a switch is shown. A plurality of transistors may be used in pixel 55, each of which functions in the same way.

[0122] In one embodiment of the present invention, the transistor 56 having an extremely low off-state current is used as a It is preferable to use the transistor 56 as a switch that controls the input to the A small value prevents charge from leaking through transistor 56. The potential of the image signal applied to the liquid crystal element 60 and the capacitance element 57 can be more reliably maintained. Therefore, the transmittance of the liquid crystal element 60 changes due to leakage of electric charges within one frame period. This prevents the image from being displayed incorrectly, thereby improving the quality of the displayed image. When the off-state current of the transistor 56 is small, the charge leakage through the transistor 56 is prevented. Therefore, during the period when a still image is displayed, the driving circuits 72 and 73 With the above configuration, the supply of the image signal to the pixel section 71 may be stopped. This reduces the number of times signals are written, thereby reducing the power consumption of the semiconductor display device.

[0123] For example, a transistor including an oxide semiconductor in a semiconductor film has an extremely small off-state current. This is suitable for use as transistor 56.

[0124] In FIG. 13B, the transistor 56 is a single layer that is overlapped with a semiconductor film sandwiched therebetween. The semiconductor device may have a pair of gate electrodes, the pair of gate electrodes being electrically connected to each other. In one embodiment of the present invention, the above structure increases the on-state current of the transistor 56. In addition, the reliability of the transistor 56 can be improved.

[0125] Next, Fig. 13(C) shows another example of the pixel 55. The pixel 55 has an image signal a transistor 95 for controlling the input of a signal, a light emitting element 98, and a light emitting element 99 in accordance with an image signal; A transistor 96 controls the current value supplied to the image signal 8, and a capacitor 97 holds the potential of the image signal. and a capacitance element 97.

[0126] The light emitting element 98 is an LED (Light Emitting Diode) or an OLED (Electron Electrical Light Emitting Diodes (ELDs) and other devices that are sensitive to current or voltage The category includes devices whose brightness can be controlled by the light emitting diode (EL) layer. For example, an OLED includes an EL layer and The device has at least an anode and a cathode. The EL layer is provided between the anode and the cathode. It is composed of a single layer or multiple layers, each containing a luminescent material. It includes at least a light-emitting layer.

[0127] The EL layer is turned on when the potential difference between the cathode and the anode is equal to or greater than the threshold voltage of the light emitting element 98. When the current is supplied, electroluminescence is obtained. There are two types of emission: fluorescence when returning from the singlet excited state to the ground state and fluorescence when returning from the triplet excited state. This includes light emission (phosphorescence) when the element returns to its ground state.

[0128] Either the anode or the cathode of the light emitting element 98 is connected to the image signal input to the pixel 55. Therefore, the potential of the anode and cathode is controlled according to the image signal. The electrode to be controlled is a pixel electrode, and the other electrode is a common electrode. A predetermined potential is applied to the electrode, and the brightness of the light emitting element 98 is determined by the voltage between the pixel electrode and the common electrode. Therefore, the luminance of the light emitting element 98 is determined by the potential difference between the image signals. By controlling the pixel area, it is possible to display gradation. In each of the above-mentioned embodiments, the gradation of the light-emitting element 98 is adjusted in accordance with an image signal having image information. As a result, an image is displayed on the pixel section 71.

[0129] Next, the transistor 95, the transistor 96, the capacitor element 97, the light emitting element 98, and the like included in the pixel 55 are shown. The connection configuration of the element 98 will be described.

[0130] The transistor 95 has one of a source and a drain connected to a wiring SL. The other input is connected to the gate of transistor 96. The gate of transistor 95 is , and is connected to the wiring GL. One of the source and the drain of the transistor 96 is connected to the power supply line The other of the source and drain is connected to the light emitting element 98. The other of the source and drain of the transistor 96 is connected to the anode and cathode of the light emitting element 98. The light emitting element 98 is connected to either the anode or the cathode. A predetermined potential is applied to the

[0131] In FIG. 13C, the transistor 96 is a pair of gate electrodes overlapping each other with a semiconductor film sandwiched therebetween. The pair of gate electrodes may be electrically connected to each other. In one embodiment, the above structure increases the on-state current of the transistor 96. This can improve the reliability of Transistor 96.

[0132] For example, in this specification, a display element, a display device which is a device having a display element, a light-emitting device, A light-emitting device, which is a device having an element and a light-emitting element, can be used in various forms or in various The display element, the display device, the light-emitting element or the light-emitting device can have, for example, EL (electroluminescence) elements (EL elements containing organic and inorganic materials, organic EL elements) LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.) , transistors (transistors that emit light according to current), electron-emitting devices, liquid crystal devices, electrons Ink, electrophoretic element, grating light valve (GLV), plasma display (PDP), display element using MEMS (microelectromechanical systems) Digital Micromirror Device (DMD), DMS (Digital MicroShutter) , IMOD (Interference Modulation) element, shutter type MEMS display element, optical interference type MEMS display element, electrowetting element, pressure At least one of electroceramic displays, display elements using carbon nanotubes, etc. In addition to these, the contrast, brightness, etc. can be improved by electrical or magnetic effects. The display device using an EL element may have a display medium whose reflectance, transmittance, etc. change. An example of a display device using electron-emitting devices is an EL display. As for the display, a field emission display (FED) or an SED type flat panel display is used. Play (SED: Surface-conduction Electron-emit An example of a display device using a liquid crystal element is a liquid crystal display. Displays (transmissive LCD displays, semi-transmissive LCD displays, reflective LCD displays) LCD, direct-view LCD, projection LCD, etc. An example of a display device using electronic liquid powder (registered trademark) or an electrophoretic element is an electronic page. There are also other LCDs that can be used to realize semi-transmissive and reflective LCD displays. In this case, part or all of the pixel electrode can function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. Furthermore, in this case, a memory circuit such as an SRAM should be provided under the reflective electrode. This makes it possible to further reduce power consumption.

[0133] For example, in this specification and the like, it is possible to form transistors using various substrates. The type of substrate is not limited to a specific one. Conductor substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrates, metal substrates, stainless steel substrates, stainless steel foils Substrate with tungsten foil, tungsten substrate, substrate with tungsten foil, flexible substrate, adhesive Examples include laminated films, paper containing fibrous materials, and base films. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of flexible substrates, laminated films, and base films include glass. Examples include polyethylene terephthalate (PET), polyethylene terephthalate (PE ... Plastics such as polyethylene naphthalate (PEN) and polyethersulfone (PES) For example, synthetic resin such as acrylic resin is used. Examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy, and inorganic vapor deposition. Films or papers, etc. In particular, semiconductor substrates, single crystal substrates, or SOI substrates, etc. By manufacturing transistors using this method, variations in characteristics, size, shape, etc. can be reduced. This allows the manufacture of transistors with low resistance, high current capability, and small size. When a circuit is constructed using such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated. This can be achieved.

[0134] In addition, a flexible substrate is used as the substrate, and a transistor is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate and the transistor. After a semiconductor device is partially or completely completed, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be formed of an inorganic film such as a tungsten film and a silicon oxide film. It uses a laminated film structure or a structure in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0135] That is, a transistor is formed using one substrate, and then the transistor is transferred to another substrate. The transistor may be placed on one of the substrates to which the transistor is transferred. Examples include substrates on which the above-mentioned transistors can be formed, as well as paper substrates, ceramic substrates, and the like. Fan substrate, aramid film substrate, polyimide film substrate, stone substrate, wood substrate, fabric substrate Board (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or Recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), leather Leather substrates or rubber substrates are available. By using these substrates, it is possible to obtain a transistor with good characteristics. the formation of low-power transistors, the manufacture of durable devices, and the manufacture of heat-resistant It is possible to provide a lighter or thinner structure.

[0136] This embodiment may be appropriately combined with the configurations disclosed in the present specification and the like of other embodiments. This can be implemented.

[0137] (Fourth embodiment) Pixel configuration Next, a liquid crystal display device, which is one of the semiconductor display devices 70 shown in FIG. 13(A), will be taken as an example. Next, a configuration example of the pixel 55 will be described. FIG. 14 shows a top view of the pixel 55 as an example. In FIG. 14, various insulating films are omitted to clarify the layout of the pixel 55. A liquid crystal display device formed using an element substrate having pixels 55 shown in FIG. A cross-sectional view of the liquid crystal display device shown in FIG. corresponds to a cross-sectional view taken along dashed line B1-B2 in FIG.

[0138] A pixel 55 shown in FIGS. 14 and 15 includes a transistor 56 and a capacitor 57. Furthermore, the pixel 55 shown in FIG.

[0139] The transistor 56 is provided on the substrate 31 having an insulating surface, and has a function as a gate electrode. A conductive film 40 and an insulating film 50 which functions as a gate insulating film and is located on the conductive film 40 an oxide semiconductor film 41 that overlaps the conductive film 40 on the insulating film 22; A conductive electrode electrically connected to the body film 41 and functioning as a source electrode or a drain electrode. The conductive film 40 includes a film 43 and a conductive film 44. The conductive film 40 serves as the wiring GL shown in FIG. The conductive film 43 also functions as the wiring SL shown in FIG. .

[0140] The pixel 55 also has a metal oxide film 42 on the insulating film 22. The metal oxide film 42 is The metal oxide film 42 is a conductive film that is transparent to visible light. A conductive film 61 is provided which is electrically connected to the metal oxide film 42. The conductive film 61 is The wiring functions as a wiring for supplying a predetermined potential to the

[0141] The insulating film 22 may be made of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, Silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, dioxide One or more of: zinc oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide The insulating film containing the acid may be used as a single layer or a stacked layer. Nitrides are materials whose composition contains more oxygen than nitrogen, while nitride oxides are It refers to a material whose composition contains more nitrogen than oxygen.

[0142] 15, the oxide semiconductor film 41, the conductive film 43, and the conductive film 44, and the metal oxide film An insulating film 26 and an insulating film 27 are provided on the insulating film 42 and the conductive film 61 in this order. The transistor 56 may include the insulating film 26 and the insulating film 27 as its components. In addition, although FIG. 15 illustrates the insulating film 26 and the insulating film 27 stacked in this order, Instead of the insulating film 26 and the insulating film 27, a single layer insulating film may be used, or a laminated insulating film may be used. Three or more insulating layers may be used.

[0143] The insulating film 26 and the insulating film 27 have openings 58 at positions where they overlap the metal oxide film 42. The opening 58 is formed in a region different from the oxide semiconductor film 41, the conductive film 43, and the conductive film 44. and is provided in a region overlapping with the metal oxide film 42.

[0144] 15, the metal oxide film 4 on the insulating film 26 and the insulating film 27 and in the opening 58 On the substrate 2, a nitride insulating film 28 and an insulating film 29 are provided in this order.

[0145] An oxide semiconductor film is formed on the insulating film 22, and a nitride film is formed in contact with the oxide semiconductor film. By forming the oxide insulating film 28, the conductivity of the oxide semiconductor film can be increased. As a result, the oxide semiconductor film with increased conductivity can be used as the metal oxide film 42. The conductivity of the oxide semiconductor film increases when the opening 58 is formed or when the nitride insulating film 2 When the nitride insulating film 28 is formed, oxygen vacancies are formed in the oxide semiconductor film, and the oxygen vacancies diffuse from the nitride insulating film 28. This is thought to be because the hydrogen atoms bond to the oxygen vacancies, generating donors. The resistivity of the metal oxide film 42 is typically 1×10 -3 Ωcm or more 1×10 4 Ωcm More preferably, the resistivity is less than 1×10 -3 Ωcm or more 1×10 -1 Less than Ωcm It would be good to do so.

[0146] The metal oxide film 42 preferably has a higher hydrogen concentration than the oxide semiconductor film 41. In the film 42, secondary ion mass spectrometry (SIMS) was performed. The hydrogen concentration obtained by ass spectrometry is 8×10 19 atom s / cm 3 or more, preferably 1 × 10 20 atoms / cm 3 More preferably, 5x 10 20 atoms / cm 3 In the oxide semiconductor film 41, the secondary ion mass The hydrogen concentration obtained by the analytical method is 5 x 10 19 atoms / cm 3 Less than 5, preferably x10 18 atoms / cm 3 Less than 1 x 10 18 atoms / cm 3 below, More preferably, 5 × 10 17 atoms / cm 3 or less, more preferably 1 × 10 16 a toms / cm 3 The following is the result.

[0147] The nitride insulating film 28 may be made of, for example, silicon nitride, silicon nitride oxide, or aluminum nitride. The nitride insulating film made of the above-mentioned material may be aluminum oxide nitride. 28 is more resistant to external impurities than oxide insulating films such as silicon oxide and aluminum oxide. Substances such as water, alkali metals, alkaline earth metals, etc., diffuse into the oxide semiconductor film 41. This can prevent this.

[0148] In addition, an opening 62 is provided in the nitride insulating film 28 and the insulating film 29 at a position overlapping the conductive film 44. On the nitride insulating film 28 and the insulating film 29, a transparent film that is transparent to visible light is formed. The conductive film 45 has an opening and functions as a pixel electrode. The conductive film 45 is electrically connected to the conductive film 44 at the opening 62. The conductive film 45 and the metal oxide film 42 overlap at 58. The overlapping portion sandwiching the oxide insulating film 28 and the insulating film 29 functions as a capacitance element 57. .

[0149] The capacitor element 57 includes a metal oxide film 42 and a conductive film 45 which function as a pair of electrodes, and a dielectric The nitride insulating film 28 and the insulating film 29 functioning as a film are transparent to visible light. Therefore, the capacitor 57 is transparent to visible light, and the capacitance of the capacitor The aperture ratio of the pixel 55 can be increased compared to pixels with low translucency to visible light. Therefore, it is possible to minimize the loss of light within the panel while ensuring the capacitance required to obtain high image quality. This reduces the power consumption of the semiconductor device.

[0150] As mentioned above, the insulating film 29 is not necessarily provided, but it is preferable to provide the insulating film 29 in place of the nitride insulating film 28. The insulating film 29 using an insulating material with a lower dielectric constant than the nitride insulating film 28 is used as a dielectric film together with the nitride insulating film 28. By using the nitride insulating film 28, the dielectric constant of the dielectric film of the capacitance element 57 can be increased. It can be adjusted to a desired value without any adjustment.

[0151] An alignment film 52 is provided on the conductive film 45 .

[0152] In addition, a substrate 46 is provided so as to face the substrate 31. On the substrate 46, a visible light and a colored layer 48 that transmits visible light in a specific wavelength range. A resin film 50 is provided on the shielding film 47 and the colored layer 48. A conductive film 59 having a function as a common electrode is provided on the film 50. An alignment film 51 is provided on the liquid crystal display panel 59 .

[0153] Between the substrate 31 and the substrate 46, a liquid crystal layer is sandwiched between the alignment film 52 and the alignment film 51. The liquid crystal element 60 includes a conductive film 45, a conductive film 59, and a liquid crystal layer 53 containing the ... and a liquid crystal layer 53 .

[0154] 14 and 15, a TN (Twisted Nemat) liquid crystal driving method is used. The example shows the case where the FFS (Fringe Free System) mode is used. e Field Switching) mode, STN (Super Twisted Nematic mode, VA (Vertical Alignment) mode, MV A (Multi-domain Vertical Alignment) mode, IP S (In-Plane Switching) mode, OCB (Optically C compensated birefringence mode, blue phase mode, TBA (Transverse Bend Alignment) mode, VA-IPS mode ,ECB(Electrically Controlled Birefringen) ce) mode, FLC (Ferroelectric Liquid Crystal) Mode, AFLC (AntiFerroelectric Liquid Crysta) l) mode, PDLC (Polymer Dispersed Liquid Crystal tal) mode, PNLC (Polymer Network Liquid Crystal tal) mode, guest host mode, ASV (Advanced Super Vie It is also possible to apply modes such as w).

[0155] In the liquid crystal display device according to one embodiment of the present invention, the liquid crystal layer may include, for example, a thermotropic Liquid crystal materials classified as lyotropic liquid crystals or lyotropic liquid crystals can be used. The liquid crystal layer may be, for example, a nematic liquid crystal, a smectic liquid crystal, a cholesteric liquid crystal, or For the liquid crystal layer, a liquid crystal material classified as a discotic liquid crystal can be used. For example, a liquid crystal material classified as a ferroelectric liquid crystal or an antiferroelectric liquid crystal can be used. Alternatively, the liquid crystal layer may be made of, for example, a main chain type polymer liquid crystal, a side chain type polymer liquid crystal, or By using a liquid crystal material classified as a polymer liquid crystal such as a composite polymer liquid crystal or a low molecular weight liquid crystal, Alternatively, the liquid crystal layer may be, for example, a liquid crystal layer classified as a polymer dispersed liquid crystal (PDLC). A liquid crystal material can be used.

[0156] Furthermore, a liquid crystal exhibiting a blue phase without using an alignment film may be used in the liquid crystal layer. When the temperature of cholesteric liquid crystal is increased, the phase changes from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so The temperature range is improved by adding chiral agents and UV-curable resins. The liquid crystal composition containing the compound has a short response time of 1 msec or less and is optically isotropic, so that alignment This is preferable because no processing is required and the viewing angle dependency is small.

[0157] FIG. 15 shows a liquid crystal display device that displays color images by using color filters. However, the liquid crystal display device according to one aspect of the present invention can be configured to emit multiple light beams of different hues. The light source may be sequentially turned on to display a color image.

[0158] Note that the oxide semiconductor film 41 of the transistor 56 is formed of a single oxide semiconductor film. The oxide semiconductor layer 16 may be formed by stacking a plurality of oxide semiconductor films. Now, let us consider a case where the oxide semiconductor film 41 is composed of three stacked oxide semiconductor films. Specifically, in the transistor 56 shown in FIG. 16A, an oxide semiconductor film 41, oxide semiconductor films 41a to 41c are arranged in this order from the insulating film 22 side. It is layered.

[0159] The oxide semiconductor film 41a and the oxide semiconductor film 41c constitute the oxide semiconductor film 41b. The constituent elements of the oxide semiconductor include at least one metal element that forms the oxide semiconductor. The difference is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.05 eV or more, more preferably 0.07 eV or more, more preferably 0.1 eV or more, more preferably ...7 eV or more, more preferably 0.07 eV or more, more preferably .15eV or more and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less, true The oxide semiconductor film 41b is an oxide film close to an unoccupied level. It is preferable that the compound contains the compound having the formula (I) because it increases carrier mobility.

[0160] As shown in FIG. 16B, the oxide semiconductor film 41c is formed by the conductive film 43 and the conductive film 44. It may be configured so as to overlap the insulating film 22 in the upper layer.

[0161] This embodiment may be appropriately combined with the configurations disclosed in the present specification and the like of other embodiments. This can be implemented.

[0162] (Embodiment 5) <Top view and cross-sectional view of semiconductor display device> Next, the appearance of a semiconductor display device according to one embodiment of the present invention will be described using a liquid crystal display device as an example. This will be explained with reference to FIG. 17. FIG. 17 shows a substrate 4001 and a substrate 4006 sealed with a sealing material 40. 17. Also, FIG. 18 is a top view of the liquid crystal display device bonded by the broken line C in FIG. This corresponds to the cross-sectional view at 1-C2.

[0163] A pixel portion 4002 and a pair of driver circuits 4004 are provided on a substrate 4001. A sealing material 4005 is provided on the pixel portion 4002 and the driver circuit 4004. Therefore, the pixel portion 4002 and the driver circuit 4004 are connected to the substrate 4006. It is sealed by 4001, a sealing material 4005 and a substrate 4006.

[0164] In addition, a region other than the region surrounded by the sealing material 4005 on the substrate 4001 is covered with a driving An operating circuit 4003 is implemented.

[0165] In addition, a pixel portion 4002 and a driver circuit 4004 provided on a substrate 4001 are made of transistors. In FIG. 18, a transistor 4010 included in the pixel portion 4002 is illustrated. On the transistor 4010, an insulating layer made of various insulating films including a nitride insulating film is formed. The transistor 4010 is formed on the insulating film 4020. At the opening, it is connected to a pixel electrode 4021 on the insulating film 4020 .

[0166] A resin film 4059 is provided on the substrate 4006, and a common An electrode 4060 is provided. A pixel electrode is provided between the substrate 4001 and the substrate 4006. A liquid crystal layer 4028 is provided so as to be sandwiched between the electrode 4021 and the common electrode 4060. The liquid crystal element 4023 includes a pixel electrode 4021, a common electrode 4060, and a liquid crystal layer 4028. do.

[0167] In the liquid crystal element 4023, the value of the voltage applied between the pixel electrode 4021 and the common electrode 4060 Accordingly, the orientation of the liquid crystal molecules contained in the liquid crystal layer 4028 changes, and the transmittance changes. The liquid crystal element 4023 changes its pixel voltage according to the potential of the image signal given to the pixel electrode 4021. By controlling the transmittance, it is possible to display gradations.

[0168] In addition, as shown in FIG. 18, in one embodiment of the present invention, the insulating film 4020 is In the region where the insulating film 4020 has been removed, the conductive film 4 The conductive film 4050 and the source or drain of the transistor 4010 are formed. The conductive film that functions as an insulating film can be formed by etching a conductive film. do.

[0169] Conductive particles 4061 having conductivity are dispersed between the substrate 4001 and the substrate 4006. The conductive film 4050 is provided with a resin film 4062 dispersed therein. The common electrode 4060 and the conductive particles 4061 are electrically connected to each other. The film 4050 is electrically connected to the panel edge via conductive particles 4061. The resin film 4062 may be made of a thermosetting resin or an ultraviolet curing resin. The conductive particles 4061 can be formed by, for example, dissolving spherical organic resin in Au, Ni, Co, or the like. Particles coated with a thin film of metal such as the above can be used.

[0170] Although the alignment film is not shown in FIG. 18, the alignment film is formed on the pixel electrode 4021 and the common electrode 4 When the conductive film 4050 is provided on the common electrode 4060, the conductive particles 4061 and the conductive film 4050 are In order to electrically connect the common electrode 4060 and the alignment film, a part of the alignment film is removed in the area where the alignment film overlaps the common electrode 4060. The alignment film may be partially removed in a portion overlapping with the conductive film 4050 .

[0171] Note that in the liquid crystal display device according to one embodiment of the present invention, color filters are used to display color images. An image may be displayed, or multiple light sources that emit light of different hues may be sequentially turned on. A color image may be displayed.

[0172] In addition, image signals from the driver circuit 4003 and various control signals and potentials from the FPC 4018 are input. are connected to the driver circuit 4004 or the pixel portion 400 via lead wirings 4030 and 4031. It is given to 2.

[0173] This embodiment may be appropriately combined with the configurations disclosed in the present specification and the like of other embodiments. This can be implemented.

[0174] (Sixth embodiment) In this embodiment mode, a semiconductor layer of the transistor described in the above embodiment mode can be formed by The oxide semiconductor layer will be described.

[0175] The oxide semiconductor used for the channel formation region in the semiconductor layer of the transistor is at least It is preferable that the material contains indium (In) or zinc (Zn). In addition to these, it is preferable to have a stabilizer that strongly binds oxygen. The stabilizer is preferably gallium (Ga), tin (Sn), or zirconia. containing at least one of tungsten (Zr), hafnium (Hf) and aluminum (Al). Just do that.

[0176] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0177] Examples of oxide semiconductors used as semiconductor layers of transistors include indium oxide. Aluminum, tin oxide, zinc oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, S n-Al-Zn oxide, In-Hf-Zn oxide, In-Zr-Zn oxide, In -Ti-Zn oxide, In-Sc-Zn oxide, In-Y-Zn oxide, In-L a-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd -Zn-based oxides, In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd- Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Z n-based oxides, In-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn In-based oxides, In-Lu-Zn-based oxides, In-Sn-Ga-Zn-based oxides, In-Hf- Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide oxides, In-Sn-Hf-Zn oxides, In-Hf-Al-Zn oxides, etc.

[0178] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=3:1:2, or I In-Ga-Zn oxides with an atomic ratio of n:Ga:Zn=2:1:3 and other oxides with similar compositions It is preferable to use an oxide.

[0179] When a large amount of hydrogen is contained in the oxide semiconductor film that constitutes the semiconductor layer, hydrogen bonds with the oxide semiconductor. By doing so, some of the hydrogen atoms become donors, generating electrons that act as carriers. This causes the threshold voltage of the transistor to shift in the negative direction. After the semiconductor film is formed, dehydration treatment (dehydrogenation treatment) is performed to remove water from the oxide semiconductor film. It is preferable to highly purify the material by removing hydrogen or moisture to minimize the amount of impurities contained therein.

[0180] Note that dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film Therefore, the oxygen content may decrease due to dehydration treatment (dehydrogenation treatment). In order to compensate for the oxygen vacancies, treatment for adding oxygen to the oxide semiconductor film is preferably performed. In the specification and the like, supplying oxygen to an oxide semiconductor film may be referred to as oxygen-adding treatment. Alternatively, the oxide semiconductor film may contain more oxygen than in the stoichiometric composition. This may be referred to as "sulfonation treatment."

[0181] In this manner, hydrogen or moisture is removed from the oxide semiconductor film by dehydration treatment (dehydrogenation treatment). By adding oxygen to the material, the oxygen deficiency is compensated for, resulting in an i-type (intrinsic) or i-type The oxide semiconductor film can be an oxide semiconductor film that is as close to an i-type as possible and is substantially i-type (intrinsic). The term "substantially intrinsic" means that there are very few carriers derived from donors in the oxide semiconductor film (zero). (near B), and the carrier density is 1×10 17 / cm 3 Below, 1×10 16 / cm 3 Below, 1 x10 15 / cm 3 Below, 1×10 14 / cm 3 Below, 1×10 13 / cm 3 is This means that.

[0182] In addition, a transistor including an i-type or substantially i-type oxide semiconductor film as described above For example, a transistor using an oxide semiconductor film can achieve excellent off-state current characteristics. The drain current when the transistor is off is 1×10 at room temperature (approximately 25°C). -18 Below A , preferably 1 x 10 -21 A or less, more preferably 1×10-24 A or below, or 85℃ 1 x 10 -15 A or less, preferably 1×10 -18 A or less, more preferably 1×10 -21 A or less. Note that the off state of a transistor is an n-channel In the case of a transistor, this refers to a state in which the gate voltage is sufficiently smaller than the threshold voltage. If the gate voltage is more than 1 V, more than 2 V, or more than 3 V less than the threshold voltage, the transistor is in the off state.

[0183] The structure of the oxide semiconductor film will be described below.

[0184] Oxide semiconductor films are classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. Alternatively, oxide semiconductors can be divided into, for example, crystalline oxide semiconductors and amorphous oxide semiconductors. do.

[0185] Note that as a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductors, microcrystalline oxide semiconductors, amorphous oxide semiconductors, etc. The materials include single-crystalline oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxides. Semiconductors, etc.

[0186] First, the CAAC-OS film will be described.

[0187] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0188] Transmission Electron Microscope (TEM) A bright-field image and a combined analysis image of the diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be identified. On the other hand, high-resolution TEM images also reveal clear boundaries between crystalline parts, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0189] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction approximately parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystalline part. Each layer of metal atoms is The CAAC-OS film is formed on a surface (also called a surface to be formed) or on a surface that reflects the unevenness of the surface. The CAAC-OS film has a shape and is aligned parallel to the surface on which the film is formed or the upper surface.

[0190] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction approximately perpendicular to the sample surface. It was confirmed that the metal atoms in the crystals were arranged in a triangular or hexagonal shape. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0191] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was found by structural analysis using the device. In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. You can see that it is oriented vertically.

[0192] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ around 31°, a peak also appeared at 2θ around 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferable that the peak is exhibited at 2θ of around 36° and that the peak is not exhibited at 2θ of around 36°.

[0193] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. These are elements other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that constitute the oxide semiconductor film, such as fluorine, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius (or molecular radius) is large, and when it is contained inside the oxide semiconductor film, The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement and cause a decrease in crystallinity. Objects can act as carrier traps or carrier sources.

[0194] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a source of carrier generation.

[0195] Low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or The term "substantially highly purified intrinsic" refers to a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics ( It is also called normally-on.) It is rare for it to become a high-purity intrinsic or substantially high-purity The intrinsic oxide semiconductor film has few carrier traps. Transistors using this film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes time for the charges trapped in the carrier traps in the oxide semiconductor film to be released. The impurity concentration is high and the charge is stable for a long time, so the charge may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high density of defect states has unstable electrical characteristics. This may occur.

[0196] In addition, transistors using CAAC-OS films show improved electrical characteristics when irradiated with visible light or ultraviolet light. The fluctuation is small.

[0197] Next, a microcrystalline oxide semiconductor film will be described.

[0198] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a crystal region and a crystal region where no clear crystal part can be identified. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fine particles are often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In addition, the nc-OS film has clearly defined grain boundaries in high-resolution TEM images. It may not be possible to recognize it.

[0199] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) using X-rays with a diameter larger than that of the crystals is used for nc-OS films. When structural analysis is performed using the D device, the crystal plane is In addition, the peaks indicating the probes larger than the crystalline part were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter (for example, 50 nm or more) When the diffraction pattern is changed to 0.05μm, a halo-like diffraction pattern is observed. Nanobeam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal part. When diffraction is performed, spots are observed. If you do this, you may observe a circular (ring-shaped) area of ​​high brightness. When nanobeam electron diffraction was performed on the nc-OS film, multiple spots were observed within the ring-shaped region. It may be observed.

[0200] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher defect state density than the CAAC-OS film.

[0201] Next, the amorphous oxide semiconductor film will be described.

[0202] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and is an oxide film that does not have a crystalline portion. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0203] In the amorphous oxide semiconductor film, no crystalline portion can be confirmed in a high-resolution TEM image.

[0204] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the analysis by the Lane method, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0205] The oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may be used, particularly, for amorphous-like oxidation. Amorphous-like Oxide Semiconductor (a-like OS) The membrane is called a conductor membrane.

[0206] In the a-like OS film, voids are observed in high-resolution TEM images. In addition, crystals can be clearly seen in high-resolution TEM images. The a-like OS film has a region where the crystal part is not observed and a region where the crystal part is not observed. Crystallization occurs due to the small amount of electron irradiation, which is the level observed with a TEM, and the growth of the crystals can be seen. On the other hand, if the nc-OS film is of good quality, the small amount of charge observed by TEM can be detected. Almost no crystallization due to electron irradiation is observed.

[0207] The size of the crystalline parts of the a-like OS film and the nc-OS film was measured using a high-resolution T This can be done using EM images. For example, InGaZnO4 crystals have a layered structure, There are two Ga-Zn-O layers between the In-O layers. The structure has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned in the c-axis direction. Therefore, the spacing between these adjacent layers is The lattice spacing (also called the d value) is approximately the same as the value of 0.29 nm from crystal structure analysis. Therefore, we focused on the lattice fringes in high-resolution TEM images and calculated the spacing between the lattice fringes. In the region where the distance is between 0.28 nm and 0.30 nm, each lattice fringe is InG aIt corresponds to the ab plane of the ZnO4 crystal.

[0208] In addition, the density of an oxide semiconductor film may differ depending on the structure. If the composition of the membrane is known, the density can be determined by comparing it with that of a single crystal with the same composition. The structure of the oxide semiconductor film can be estimated. The density of the OS-like film is 78.6% or more and less than 92.3%. The density of the nc-OS film and the CAAC-OS film was 92.3% or more. Note that an oxide semiconductor film having a density of less than 78% of the density of a single crystal is The film formation itself is difficult.

[0209] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atomic In the oxide semiconductor film that satisfies the numerical ratio, single crystal InGaZnO4 with a rhombohedral crystal structure The density of 3 Therefore, for example, In:Ga:Zn=1:1:1 In an oxide semiconductor film that satisfies the atomic ratio, the density of the a-like OS film is 5.0g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1: In the oxide semiconductor film satisfying the atomic ratio of 1, the density and CAAC- The density of the OS film is 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0210] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions at any ratio are used. By combining single crystals, it is possible to calculate the density corresponding to a single crystal of the desired composition. The density of a single crystal of a desired composition can be determined by the ratio of the single crystals of different compositions combined. However, the density should be calculated using as few types of single crystals as possible. It is preferable to calculate them in combination.

[0211] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, an a-like OS film, or a finely crystalline oxide semiconductor film. The film may be a stacked film including two or more of a crystalline oxide semiconductor film and a CAAC-OS film.

[0212] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case of -5° or more and 5° or less. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0213] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0214] This embodiment may be appropriately combined with the configurations disclosed in the present specification and the like of other embodiments. This can be implemented.

[0215] (Embodiment 7) <Configuration example of electronic device using semiconductor device> A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices (typically DVD: Digital Versatile Disc) (Devices having a display that can play back recording media such as DVDs and display the images) In addition, electronic devices in which the semiconductor device according to one embodiment of the present invention can be used are Mobile phones, portable game consoles, personal digital assistants, e-books, video cameras, digital cameras, Cameras such as digital still cameras, goggle-type displays (head-mounted displays) ), navigation systems, sound reproduction devices (car audio, digital audio players) Years, etc.), copiers, fax machines, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0216] FIG. 19A shows a portable game machine, which includes a housing 5001, a housing 5002, a display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, The display unit 5003 or the display unit 5004 and other integrated circuits A semiconductor device according to one embodiment of the present invention can be used for the semiconductor device shown in FIG. The portable game machine has two display units 5003 and 5004. The number of display units that the gaming machine has is not limited to this.

[0217] FIG. 19B shows a portable information terminal, which includes a first housing 5601, a second housing 5602, a first display unit, and a 5603, a second display unit 5604, a connection unit 5605, operation keys 5606, etc. Table 1 The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected by a connection portion 56 5605, and the angle between the first housing 5601 and the second housing 5602 is The image on the first display unit 5603 can be changed by the connection unit 5605. 605, the first housing 5601 and the second housing 5602 are switched according to the angle between them. The first display portion 5603, the second display portion 5604, or other integrated circuits may be used. In this case, the semiconductor device according to one embodiment of the present invention can be used.

[0218] FIG. 19C shows a notebook personal computer, which includes a housing 5401 and a display portion 5402. 5402, a keyboard 5403, a pointing device 5404, etc. The semiconductor device according to one embodiment of the present invention can be used for the above-mentioned integrated circuits and other integrated circuits.

[0219] FIG. 19D shows a wristwatch, which includes a housing 5201, a display unit 5202, operation buttons 5203, and a backlight. The display portion 5202 and other integrated circuits may include a display element 5204 and other integrated circuits. A semiconductor device having such a structure can be used.

[0220] FIG. 19(E) shows a video camera, which includes a first housing 5801, a second housing 5802, and a display unit 58 03, operation keys 5804, a lens 5805, a connection part 5806, etc. The lens 5805 is provided in the first housing 5801, and the display unit 5803 is provided in the second housing. The first housing 5801 and the second housing 5802 are connected by a connection part. The first housing 5801 and the second housing 5802 are connected by a The video on the display unit 5803 can be changed by the video input unit 5806. , according to the angle between the first housing 5801 and the second housing 5802 at the connection portion 5806. The semiconductor device according to one embodiment of the present invention may be provided in the display portion 5803 or other integrated circuits. A body device can be used.

[0221] FIG. 19(F) shows a mobile phone, which includes a housing 5901, a display portion 5902, a microphone 5907, a speaker 5908, and a microphone 5909. Speaker 5904, camera 5903, external connection part 5906, and operation button 5905 are installed. The semiconductor device according to one embodiment of the present invention is used in the display portion 5902 and other integrated circuits. Furthermore, the semiconductor device according to one embodiment of the present invention can be mounted on a flexible substrate. In this case, the semiconductor device is formed in a display portion 5902 having a curved surface as shown in FIG. It is possible to apply the position.

[0222] Note that the content (or even a part of the content) described in one embodiment may be used in conjunction with that embodiment. Other content (or even part of content) described in the above, and / or one or more other implementations The content (or part of the content) described in the form of You can do things like:

[0223] The contents described in the embodiments are explained in detail in each embodiment using various drawings. This refers to the content that is stated or the content that is stated using the text in the specification.

[0224] In addition, a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part thereof) described in another embodiment of the present invention, , and many more diagrams can be constructed.

[0225] In addition, regarding the contents not specified in the drawings or text in the specification, Alternatively, the upper limit of a certain value may be set. When a numerical range is listed, such as a lower limit, you can narrow the range arbitrarily. Or, by excluding one point within the scope, one aspect of the invention that excludes part of the scope is defined. As a result, for example, the prior art can be included within the technical scope of one aspect of the present invention. It can be stipulated that it will not be included.

[0226] As a specific example, a circuit diagram using first to fifth transistors in a circuit is shown below. In that case, the circuit does not have a sixth transistor. Alternatively, the circuit may be defined as an invention that does not have a capacitance element. Furthermore, it is possible to specify that the circuit has a specific connection structure. The invention can be configured by specifying that the semiconductor device does not have a sixth transistor. Alternatively, it is specified that the circuit does not have a capacitive element having a specific connection structure. For example, the gate of the first transistor is connected to the gate of the second transistor. It is possible to define the invention as not having a sixth transistor. Alternatively, for example, a capacitor element having a first electrode connected to the gate of the third transistor may be provided. It is possible to define the invention as not having

[0227] As another example, for a certain value, for example, "a certain voltage is 3V or more and 10V or less." In that case, for example, if a certain voltage is -2V, It is possible to specify one aspect of the invention as "excluding cases where the voltage is greater than or equal to 1 V and less than or equal to 1 V." For example, one aspect of the invention may be defined as excluding cases where a certain voltage is 13 V or higher. It is also possible to define the invention as requiring that the voltage be between 5V and 8V. It is possible to define the invention as having a voltage of approximately 9V. For example, the voltage is between 3V and 10V, but excluding the case where it is 9V. It is also possible to define an invention as follows: Even if it is stated that "it is preferable that these conditions are met" or "it is preferable that these conditions are met," , and certain values ​​are not limited to those descriptions. That is, "preferred," "preferred," etc. However, even if it is described as such, it is not necessarily limited to such description.

[0228] As another specific example, regarding a certain value, for example, "a certain voltage is preferably 10V" may be used. In that case, for example, if a certain voltage is between -2V and 1V, It is possible to define one aspect of the invention as "except when One aspect of the invention can be defined as excluding cases where the voltage is 13V or higher.

[0229] Another example is when describing the properties of a substance, for example, "a certain film is an insulating film." In that case, it is assumed that the insulating film is an organic insulating film. Alternatively, for example, the insulating film may be an inorganic insulating film. It is possible to define one aspect of the invention as excluding the case where the membrane is a velum. It is possible to define one aspect of the invention as excluding cases where the film is a conductive film. For example, it is possible to define one aspect of the invention as excluding cases where the film is a semiconductor film. It is Noh.

[0230] As another example, regarding a certain laminated structure, for example, "a certain film is present between film A and film B" In that case, for example, if the film is a stack of four or more layers, Or, for example, it is possible to define the invention as excluding the case of a film A and its It is possible to define the invention as excluding cases where a conductive film is provided between the film and the .

[0231] In this specification, the terms "active elements" and "passive elements" are used interchangeably. For all terminals of elements such as capacitors and resistors, the connection destination must be specified. However, a person skilled in the art may be able to compose an aspect of the invention. Even if the destination is not specified, one aspect of the invention can be said to be clear. When the content is described in this specification, etc., one aspect of the invention that does not specify the connection destination is In particular, if the terminals are connected to multiple If such a case is considered, there is no need to limit the connection destination of the terminal to a specific location. Therefore, there are active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements, etc.) By specifying the connection destinations of only some of the terminals possessed by a device, etc., It may be possible to configure one aspect.

[0232] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art. It may be possible for a person skilled in the art to identify an invention. A person skilled in the art may be able to identify an invention by at least specifying the function. In other words, if the function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, specifying the connection destination can be considered an aspect of an invention. and can constitute one aspect of the invention. Even if the connection destination of a certain circuit is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an aspect of the invention.

[0233] In this specification, etc., in a drawing or text that describes one embodiment, It is possible to extract a part of it and use it to constitute an aspect of the invention. If there is a figure or text describing a certain part, the extracted content of a part of the figure or text is also disclosed as an aspect of the invention and can constitute an aspect of the invention. And it can be said that an aspect of the invention is clear. Therefore, for example, in a drawing or text in which one or more active elements (such as transistors, diodes, etc.), wirings, passive elements (such as capacitor elements, resistor elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operation methods, manufacturing methods, etc. are described, it is assumed that an aspect of the invention can be constituted by extracting a part thereof. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitor elements, etc.), M (M is an integer and M < N) circuit elements (such as transistors, capacitor elements, etc.) are extracted, and it is possible to constitute an aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, M (M is an integer and M < N) layers are extracted, and it is possible to constitute an aspect of the invention. As yet another example, from a flowchart composed of N (N is an integer) elements, M (M is an integer and M < N) elements are extracted, and it is possible to constitute an aspect of the invention. As yet another example, from a text stating that "A has B, C, D, E, or F", some elements are arbitrarily extracted to form aspects of the invention such as "A has B and E", "A has E and F", "A has C, E, and F", or "A has B, C, D, and E". It is also possible to constitute an aspect of the invention. And it can be said that an aspect of the invention is clear. Therefore, for example, in a drawing or text in which one or more active elements (such as transistors, diodes, etc.), wirings, passive elements (such as capacitor elements, resistor elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operation methods, manufacturing methods, etc. are described, it is assumed that an aspect of the invention can be constituted by extracting a part thereof. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitor elements, etc.), M (M is an integer and M < N) circuit elements (such as transistors, capacitor elements, etc.) are extracted, and it is possible to constitute an aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, M (M is an integer and M < N) layers are extracted, and it is possible to constitute an aspect of the invention. <000​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​If at least one specific example is described, it is not possible to derive a generic concept of that specific example. This will be easily understood by those skilled in the art. When at least one specific example is described in a figure or text, the general outline of that specific example is The invention is also disclosed as an aspect of the invention and may constitute an aspect of the invention. Therefore, one aspect of the invention can be said to be clear.

[0235] In this specification, at least the contents shown in the drawings (or even a part of the drawings) This is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, if something is shown in a diagram, it is not necessarily stated in words. However, the content is disclosed as one aspect of the invention and constitutes one aspect of the invention. Similarly, even if a part of the drawings is taken out, it can be regarded as one embodiment of the invention. This is disclosed as an embodiment of the present invention. It can be said that one aspect of the invention is clear. [Explanation of symbols]

[0236] 22 insulating film 26 insulating film 27 Insulating film 28 Nitride insulating film 29 Insulating film 31 PCB 40 Conductive film 41 Oxide semiconductor film 41a Oxide semiconductor film 41b Oxide semiconductor film 41c Oxide semiconductor film 42 Metal oxide film 43 Conductive Film 44 Conductive film 45 Conductive film 46 PCB 47 Shielding membrane 48 Colored layer 50 Resin Film 51 Orientation film 52 Alignment film 53 Liquid crystal layer 55 pixels 56 transistors 57 Capacitor element 58 Opening 59 Conductive film 60 Liquid crystal element 61 Conductive film 62 Opening 70 Semiconductor display device 71 Pixel section 72 Drive circuit 73 Drive circuit 75 Shift Register 76 Shift Register 77 Switch Circuit 95 transistors 96 transistors 97 Capacitor 98 Light-emitting element 100 sequential circuits 101 Transistor 102 transistor 103 Transistor 104 transistors 105 transistors 105A transistor 105B transistor 106 transistors 107 Transistor 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 117 Wiring 118 Wiring 119 Wiring 121 Wiring 122 Wiring 123 Wiring 124 Wiring 125 Wiring 4001 board 4002 Pixel section 4003 Drive circuit 4004 drive circuit 4005 Encapsulating material 4006 board 4010 transistor 4018 FPC 4020 insulating film 4021 Pixel electrode 4023 Liquid crystal element 4028 Liquid crystal layer 4030 Wiring 4050 Conductive film 4059 Resin film 4060 Common electrode 4061 Conductive particles 4062 Resin film 5001 Case 5002 Case 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5201 Case 5202 Display section 5203 Operation button 5204 band 5401 Housing 5402 Display section 5403 Keyboard 5404 Pointing Device 5601 Housing 5602 Housing 5603 Display section 5604 Display section 5605 Connection 5606 Operation Key 5801 Housing 5802 Housing 5803 Display section 5804 Operation key 5805 Lens 5806 Connection 5901 Housing 5902 Display section 5903 Camera 5904 Speaker 5905 Button 5906 External connection part 5907 Mike

Claims

1. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fourth wiring is to which the first clock signal is input. Semiconductor equipment.

2. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The first wiring has the function of outputting a first signal, The second wiring is input to the second clock signal. The third wiring is supplied with the first power supply voltage. The fourth wiring is input to the first clock signal. The fifth wiring is input to the second signal. The sixth wiring is to receive the third clock signal. Semiconductor equipment.

3. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fourth transistor has a larger ratio of channel width to channel length than the seventh transistor. The fourth wiring is to which the first clock signal is input. Semiconductor equipment.

4. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fourth transistor has a larger ratio of channel width to channel length than the seventh transistor. The first wiring has the function of outputting a first signal, The second wiring is input to the second clock signal. The third wiring is supplied with the first power supply voltage. The fourth wiring is input to the first clock signal. The fifth wiring is input to the second signal. The sixth wiring is to receive the third clock signal. Semiconductor equipment.

5. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fifth transistor has a larger ratio of channel width to channel length than the third transistor. The fifth transistor has a larger ratio of channel width to channel length than the fourth transistor. The fourth wiring is to which the first clock signal is input. Semiconductor equipment.

6. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fifth transistor has a larger ratio of channel width to channel length than the third transistor. The fifth transistor has a larger ratio of channel width to channel length than the fourth transistor. The first wiring has the function of outputting a first signal, The second wiring is input to the second clock signal. The third wiring is supplied with the first power supply voltage. The fourth wiring is input to the first clock signal. The fifth wiring is input to the second signal. The sixth wiring is to receive the third clock signal. Semiconductor equipment.

7. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fifth transistor has a larger ratio of channel width to channel length than the sixth transistor. The fifth transistor has a larger ratio of channel width to channel length than the seventh transistor. The fourth wiring is to which the first clock signal is input. Semiconductor equipment.

8. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fifth transistor has a larger ratio of channel width to channel length than the sixth transistor. The fifth transistor has a larger ratio of channel width to channel length than the seventh transistor. The first wiring has the function of outputting a first signal, The second wiring is input to the second clock signal. The third wiring is supplied with the first power supply voltage. The fourth wiring is input to the first clock signal. The fifth wiring is input to the second signal. The sixth wiring is to receive the third clock signal. Semiconductor equipment.

9. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fourth transistor has a larger ratio of channel width to channel length than the seventh transistor. The fifth transistor has a larger ratio of channel width to channel length than the third transistor. The fifth transistor has a larger ratio of channel width to channel length than the fourth transistor. The fifth transistor has a larger ratio of channel width to channel length than the sixth transistor. The fifth transistor has a larger ratio of channel width to channel length than the seventh transistor. The fourth wiring is to which the first clock signal is input. Semiconductor equipment.

10. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fourth transistor has a larger ratio of channel width to channel length than the seventh transistor. The fifth transistor has a larger ratio of channel width to channel length than the third transistor. The fifth transistor has a larger ratio of channel width to channel length than the fourth transistor. The fifth transistor has a larger ratio of channel width to channel length than the sixth transistor. The fifth transistor has a larger ratio of channel width to channel length than the seventh transistor. The first wiring has the function of outputting a first signal, The second wiring is input to the second clock signal. The third wiring is supplied with the first power supply voltage. The fourth wiring is input to the first clock signal. The fifth wiring is input to the second signal. The sixth wiring is to receive the third clock signal. Semiconductor equipment.

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