Display device

Abstract

To provide a wiring in which an angle of a side face of the wiring is precisely made different in each desired part on one mother glass substrate without increasing processes.SOLUTION: By using a multi-tone mask, a photoresist layer having a tapered shape whose cross-sectional area is continuously decreased in a direction away from one mother glass substrate is formed. When one wiring is formed, a metal film is selectively etched using one photomask, so that one wiring whose side surface shape (specifically, an angle with respect to a main plane of a substrate) is different depending on the location is obtained.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device having a circuit configured with thin film transistors (hereinafter referred to as TFTs). The present invention relates to electro-optical devices such as liquid crystal display panels and photonic devices, and methods for manufacturing such devices. The present invention relates to an electronic device that incorporates a light-emitting display device having a light-emitting element as a component.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term "semiconductor device" refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all semiconductor devices. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used. The technology for constructing thin film transistors (TFTs) is attracting attention. It is widely used in electronic devices such as ICs and electro-optical devices, especially in switches for image display devices. Development of this device as a photonics element is being rushed.

[0004] In particular, a switching element made of a TFT is provided for each display pixel arranged in a matrix. Active matrix display devices (liquid crystal display devices and light-emitting display devices) have been actively developed. are.

[0005] The switching elements of this image display device are designed to be area-efficient in order to obtain high-definition image displays. This requires high-precision photolithography technology that can be used to place the electrodes.

[0006] In addition, up until now, multiple panels have been cut out from a single mother glass substrate, making mass production more efficient. The size of the mother glass substrate was The first generation was 300 x 400 mm, and in 2000 it was expanded to the fourth generation, 680 x 88 0mm or 730 x 920mm, and multiple display panels can be mounted on a single substrate. In the future, the size of the mother glass substrate will become larger. To accommodate this, it is necessary to support, for example, 10th generation boards that exceed 3m in size.

[0007] In order to obtain a display device that can display high-definition images, a metal film formed on a mother glass substrate is Etching of thin films using a resist mask obtained by photolithography This forms wiring.

[0008] There are various etching methods, but they can be broadly divided into dry etching and wet etching. Wet etching is an isotropic etching method. The side of the wiring layer protected by the resist mask is scraped away to some extent, which is inappropriate for miniaturization. It is considered to be the direction.

[0009] Also, the commonly known dry etching method is the RIE dry etching method. Since it is anisotropic etching, isotropic etching is required for miniaturization. This is considered to be advantageous compared to wet etching methods, which require high etching efficiency.

[0010] In addition, tungsten wiring with a tapered cross section was fabricated using an ICP etching device. is disclosed in Patent Document 1.

[0011] In addition, an auxiliary pattern having a light intensity reducing function, which is made of a diffraction grating pattern or a semi-transparent film, is provided. The photomask or reticle is applied to a photolithography process for forming a gate electrode. Such a TFT manufacturing process is disclosed in Patent Document 2.

[0012] In addition, the cross-sectional shape of the wiring can be partially adjusted by adjusting the resist mask width and etching conditions. Patent Document 3 discloses a technique for making the difference.

[0013] In addition, a photomask having an auxiliary pattern with a light intensity reducing function made of a semi-transparent film is used. Patent Document 4 discloses a technique for forming a source electrode or a drain electrode using a semiconductor device. [Prior art documents] [Patent documents]

[0014] [Patent Document 1] Patent Publication No. 2001-35808 [Patent Document 2] Patent Publication No. 2002-151523 [Patent Document 3] Patent Publication No. 2006-13461 [Patent Document 4] Patent Publication No. 2007-133371 Summary of the Invention [Problem to be solved by the invention]

[0015] When forming wiring on a single mother glass substrate, the conventional method requires wiring with the same cross-sectional shape. For example, when using the RIE dry etching method, the developed resist The resist shape is changed by heating and melting the material, and then etching is performed to change the resist shape. The side of the wiring is tapered to reflect this. In addition, the resist area is expanded by dissolving it, which increases the number of adjacent It is difficult to narrow the spacing between the lines. If there is wiring below the area to be removed, the wiring below will also be heated when the resist is melted. Therefore, the resist heating temperature becomes uneven, and the rate at which the resist melts and spreads varies depending on the location. This makes it difficult to obtain a desired wiring shape.

[0016] In addition, when using an ICP etching device, a coil antenna is used, so a rectangular However, it is difficult to obtain a uniform discharge over the entire surface of a single mother glass substrate.

[0017] For example, in the pixel portion of a transmissive liquid crystal display device, by making the gate wiring tapered, A thin semiconductor layer is formed on top of it, but the tapered shape widens the wiring width, so the opening In addition, the tapered shape increases the wiring width, which may result in a decrease in the wiring efficiency. If there is another wiring that overlaps with the above via an insulating film, an unnecessary parasitic capacitance is formed. To reduce capacitance, wiring on each layer is arranged so that wiring on different layers does not overlap. When the layout is performed, the aperture ratio is reduced.

[0018] In addition, an auxiliary pattern having a light intensity reducing function, which is made of a diffraction grating pattern or a semi-transparent film, is provided. When a photomask having a different cross section is used, the cross section of the wiring can be selectively changed. In this case, the side of the wiring has two types of cross-sectional shapes: a two-step staircase and a non-step staircase. It becomes wiring.

[0019] In a method for manufacturing a semiconductor device, a semiconductor device can be manufactured on a single mother glass substrate without increasing the number of processes. The object of the present invention is to provide wiring in which the angles of the side surfaces of the wiring are precisely different in each desired portion. do. [Means for solving the problem]

[0020] a light-transmitting substrate that can transmit exposure light; and a light-shielding portion formed on the light-transmitting substrate and made of chromium or the like; A light intensity reducer in which lines and spaces made of a light-shielding material are repeatedly formed with a predetermined line width. An exposure mask having a semi-transparent portion and a line and space portion is used. An exposure mask with a semi-transparent portion is also called a gray-tone exposure mask. Such exposure is also called gray-tone exposure.

[0021] A gray-tone exposure mask has at least one pattern such as a slit or dot, and a periphery. The aperture pattern is periodically or non-periodically arranged. Light intensity reduction consisting of spaces between mask openings consisting of lines and spaces below the boundary The light intensity of the functional auxiliary pattern can be adjusted within the range of 10 to 70%.

[0022] Also, an exposure mask having a semi-transparent portion made of a semi-transparent film having a function of reducing the light intensity of exposure light is provided. The mask is also called a half-tone exposure mask, and exposure using this exposure mask is called half-tone exposure. In addition to MoSiN, other semi-transparent films include MoSi, MoSiO, and MoS iON, CrSi, etc. can be used.

[0023] In this specification, gray-tone exposure masks and half-tone exposure masks are collectively referred to as "masks for exposure." For convenience, this is called a multi-tone mask.

[0024] By using a multi-tone mask, one photoresist layer is separated from one mother glass substrate. A photoresist layer having a tapered shape in which the cross-sectional area continuously decreases in that direction is formed. The present invention uses a gray-tone exposure mask or a half-tone exposure mask. By doing so, one photoresist layer is developed to two different film thicknesses, and the two ends of the photoresist layer are They do not form a single step each.

[0025] In the present invention, when forming one wiring, one photomask is used, and the first region is A gray-tone exposure (or half-tone exposure) is performed, and at the same time, a portion of the second region is exposed to light. Then, development is performed and the metal film is selectively etched to remove the A single wiring is obtained in which the side shape (specifically, the angle relative to the main surface of the substrate) varies depending on the location. This method allows the side shape of the wiring to be intentionally changed, and the implementer can You can get the desired wiring.

[0026] As a result, the width of the side of the wiring in the first region (also called the width of the tapered portion) is The width of the side of the wiring in the first region is wider than the width of the side of the wiring in the first region. The angle of the facet is smaller than that of the second region.

[0027] In one wiring, at least a portion of the first region and a portion of the second region are formed on the main surface of the substrate. It is preferable that the difference in angle of the side surface with respect to the surface be greater than 10°.

[0028] For example, in a transmissive liquid crystal display device, the region that will become the gate electrode and that overlaps with the semiconductor layer is called a first The thin film transistor with excellent electrical properties is formed as the region, and the gate electrode extending between the pixel electrodes is formed as the region. The area that will become the wiring is used as the second area, and the width of the tapered part is narrowed to improve the aperture ratio. In addition, the gate wiring is tapered to reduce wiring resistance and improve the aperture ratio. It is preferable to narrow the width of the gate electrode. By making the width of the electrode wider than that of the metal, the wiring resistance can be reduced.

[0029] The configuration of the invention disclosed in this specification is a semiconductor layer on a substrate, and wiring that partially overlaps the semiconductor layer. The wiring has a wide region on the side of the wiring and a narrow region on the side of the wiring, The wide region at least partially overlaps the semiconductor layer and has a narrow width on the side of the wiring. The side angle of the cross section in the wiring width direction is smaller by 10° or more than the side angle of the cross section in the wiring width direction. This is a semiconductor device characterized by the above.

[0030] Specifically, the side angle of the cross section in the wiring width direction in the wide region of the wiring side is 10° to 50°. The side angle of the cross section in the wiring width direction in the narrow region of the wiring side is in the range of 60° to 90°. If the side angle of the cross section in the wiring width direction is 90°, the cross section shape of the wiring is If the cross section of the wiring is rectangular or square and is less than 90°, the top side is shorter than the bottom side. It is a shape.

[0031] In the case of an inverted staggered thin film transistor, the semiconductor layer formed on the gate wiring is approximately 50 Because the gate wiring is so thin (only 10 nm), the side angle of the wide area on the side of the gate wiring in the cross section in the wiring width direction is 10°. The part of the semiconductor layer that overlaps the edge or side of the gate wiring is thinned within the range of 50°. It is preferable not to do so.

[0032] The present invention solves at least one of the above problems.

[0033] In addition, the wiring is not limited to gate wiring, and may include source wiring, drain wiring, connection wiring, etc. on the interlayer insulating film. The present invention can also be used to form any other wiring.

[0034] In addition to forming a wiring having side surfaces at the same angle at both ends of the wiring in cross section, In addition, the angle of one side surface and the other side surface relative to the main surface of the substrate can be made different. In this case, the cross-sectional shape of the wiring can be said to be a trapezoid with two different interior angles that touch the base.

[0035] Another aspect of the present invention is a semiconductor device including a first wiring on a substrate, an insulating film covering the first wiring, and a semiconductor device including a first insulating film. and a second wiring electrically connected to the first wiring via the second wiring. The angle between one side surface and the other side surface of the two ends of the semiconductor substrate is different from that of the other side surface. It is a body device.

[0036] In addition to the above configuration, the transparent conductive film is provided so as to partially overlap the second wiring, and the transparent conductive film is Of the two ends in the cross section of the wiring of 2, the one with the smaller angle with respect to the main surface of the substrate By adopting such a configuration, the transparent wiring overlapping one side surface of the second wiring To ensure reliable electrical connection with the conductive film and reduce disconnection of the transparent conductive film.

[0037] Another aspect of the present invention is a gray-tone exposure mask or a half-tone exposure mask. By using this method, one photoresist layer can be developed to three or more different film thicknesses, Two or more steps are formed on both ends of the layer. When the conductive layer is etched, the cross section of the resulting wiring has two or more steps on one side. Of course, wiring having this cross-sectional shape can be selectively formed. Therefore, a first wiring and a second wiring having a cross-sectional shape different from that of the first wiring are provided on the same insulating film surface. The cross-sectional shape of the first wiring is rectangular or trapezoidal, and the cross-sectional shape of the second wiring is The first wiring and the second wiring are made of the same material. When the cross section of the wiring is tapered, the tapered The position of the edge of the groove is affected by the etching time, and especially when the taper angle is less than 60°, There is a risk of variations in the wiring width of the casing, and the side surfaces may become curved and skirt-like, resulting in cutoff. Although there is a risk that the area will decrease and the wiring resistance will increase, the etching time can be reduced by making it step-shaped. Even if the cross section of the second wiring is slightly different, a constant wiring width can be obtained. By using this wiring layer, it is possible to secure a sufficient margin for the etching conditions. By making the end of the wiring have two steps in the cross section of the wiring of 2, the taper angle is less than 50°. It is possible to ensure the same level of step coverage as that of a wiring having a full tapered shape.

[0038] In one wiring, the cross-sectional shape of the first region is rectangular or trapezoidal, and the cross-sectional shape of the second region is The cross-sectional shape may be a stepped shape having two or more steps on one side surface.

[0039] The invention also relates to a manufacturing method for realizing the above structure, and is configured by forming a conductive layer on a substrate. A multi-tone mask is used to perform one exposure, and the side surface and the main surface of the substrate in the cross section are clearly visible. The first resist mask and the second resist mask, which have different angles, are developed. The conductive layer is etched using the first and second resist masks to form wiring. The angle of the side cross section of the first resist mask after development and the angle of the side cross section of the second resist mask are The difference between the angle is greater than 10°.

[0040] Another manufacturing method of the present invention is to form a conductive layer on a substrate and then use a multi-tone mask. The first resist pattern is formed by performing one exposure and forming a first resist pattern having a different angle between the side surface in the cross section and the main surface of the substrate. The first resist mask and the second resist mask are developed, and the first resist mask and the second resist mask are The conductive layer is etched using the mask as a mask to form a single wiring, and the first resist is The difference between the angle of the side cross section of the first resist mask and the angle of the side cross section of the second resist mask is less than 10°. This is a method for manufacturing a large semiconductor device.

[0041] In each of the above manufacturing methods, the cross-sectional shape of the first resist mask is rectangular or trapezoidal. The cross-sectional shape of the second resist mask is trapezoidal. The cross-sectional shape of the first resist mask is rectangular or trapezoidal, and the cross-sectional shape of the second resist mask is The surface shape is stepped, with two or more steps on one side.

[0042] These methods mentioned above are not just design matters, but are actually used to form wiring using a multi-tone mask. This invention was made after careful consideration by the inventors.

[0043] The technique disclosed in Patent Document 1 is to control the side of the wiring by changing the etching conditions of the ICP etching device. Since the angle on the surface is determined, wiring formed on the same substrate using the same etching process The side shape of the wiring is intended to be uniform for all wiring. This is significantly different from the present invention, in which the side shape of the line is made different depending on the location.

[0044] In addition, the techniques disclosed in Patent Documents 2 and 4 have a step-like side of the resist mask, The side of the wiring is also stepped to reflect the shape of the resist mask. The wiring disclosed in Patent Document 4 has one step, which is provided on each end.

[0045] Furthermore, the technology disclosed in Patent Document 3 is a technology for partially varying the cross-sectional shape of wiring, The side surfaces of the wiring formed in the same etching step form the same angle with the main surface of the substrate.

[0046] In this specification, terms indicating directions such as top, bottom, side, horizontal, and vertical refer to the top of the substrate surface. This refers to the direction based on the board surface when the device is placed on the board.

[0047] In this specification, the term "gate electrode" refers to a thin gate electrode that overlaps with a semiconductor layer via a gate insulating film. The gate wiring refers to the part that forms the channel of the film transistor. Note that part of one pattern made of the same conductive material is the gate electrode, and the other part is The remaining part becomes the gate wiring.

[0048] In the present invention, the semiconductor layer is a semiconductor film mainly composed of silicon or a metal oxide. As a semiconductor film containing silicon as a main component, Amorphous semiconductor films, semiconductor films containing crystalline structures, compound semiconductor films containing amorphous structures, etc. Specifically, amorphous silicon, microcrystalline silicon, polycrystalline silicon, monocrystalline silicon, Crystalline silicon or the like can be used. Also, a semiconductor film containing metal oxide as a main component can be used. For example, zinc oxide (ZnO) and zinc, gallium, and indium oxide (In-Ga-Zn- O) etc. can be used.

[0049] Furthermore, the present invention can be applied regardless of the TFT structure or transistor structure. For example, top gate TFT, bottom gate (reverse staggered) TFT, and forward staggered It is possible to use TFTs. Also, it is not limited to transistors with a single gate structure. First, a multi-gate transistor having a plurality of channel forming regions, such as a double gate A type transistor may also be used. [Effects of the Invention]

[0050] Using one mask, desired areas can be printed on one mother glass substrate without increasing the number of processes. This allows for the fabrication of wirings with precisely different side angles. [Brief explanation of the drawings]

[0051] [Figure 1] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 2] FIG. 10 is a photograph showing an example of a cross section of a wiring. [Figure 3] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 4] FIG. 10 is a photograph showing an example of a cross section of a wiring. [Figure 5] (A), (C), and (D) are partial top views of the mask, and (B) and (E) are schematic diagrams showing an example of the relationship between light intensity. [Figure 6] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 7] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 8] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views illustrating a manufacturing method of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating a manufacturing method of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a manufacturing method of the present invention. [Figure 12] 1A to 1C are top views illustrating a manufacturing method of the present invention. [Figure 13]FIG. 10 is a diagram showing an example of a time chart illustrating a process of forming a microcrystalline silicon film. [Figure 14] FIG. [Figure 15] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 16] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 17] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 18] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 19] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 20] FIG. 1 is a cross-sectional view illustrating an example of a liquid crystal display device. [Figure 21] FIG. 1 is a top view illustrating an example of a liquid crystal display device. [Figure 22] FIG. 1 is a top view illustrating an example of a liquid crystal display device. [Figure 23] FIG. 1 is an equivalent circuit diagram of a pixel of a liquid crystal display device. [Figure 24] FIG. 1 is a diagram illustrating an example of a liquid crystal display device. [Figure 25] FIG. 1 is a diagram illustrating an example of a liquid crystal display device. [Figure 26] FIG. 2 is a perspective view illustrating a display panel. [Figure 27] 1A and 1B are a top view and a cross-sectional view illustrating a display panel. [Figure 28] FIG. 1 is a perspective view illustrating an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0052] An embodiment of the present invention will be described below.

[0053] (Embodiment 1) In this embodiment, a pixel portion having a thin film transistor is connected to an external device using an FPC or the like. Figure 1 shows the manufacturing process for forming a terminal part with connection wiring for connecting the device to the semiconductor device on the same substrate.

[0054] First, a substrate 101 having an insulating surface is prepared. a light-transmitting substrate, such as a glass substrate, a crystallized glass substrate, or a plastic substrate; When the substrate 101 is a mother glass, the size of the substrate is (320mm x 400mm), 2nd generation (400mm x 500mm), 3rd generation (550 mm x 650 mm), 4th generation (680 mm x 880 mm, or 730 mm x 920 mm m), 5th generation (1000mm x 1200mm or 1100mm x 1250mm), 6th generation (1500mm x 1800mm), 7th generation (1900mm x 2200mm), 8th generation Generation (2160mm x 2460mm), 9th generation (2400mm x 2800mm, 245 10th generation (2950mm x 3400mm), etc. can.

[0055] In addition, the substrate 101 having an insulating surface is formed by forming an insulating layer or film on the outermost surface. For example, an underlying film made of an insulator, a semiconductor layer, or a conductive film may already be formed.

[0056] Next, a first conductive layer 103 is formed on the substrate 101 having an insulating surface. Layer 103 is made of a high melting point metal such as tungsten, titanium, chromium, tantalum, or molybdenum. alloys or compounds whose main component is a high-melting point metal such as tantalum or tantalum nitride The thickness is about 600 nm. In order to reduce the resistance of the wiring, aluminum and gold are used. Alternatively, a metal film such as copper and the above-mentioned high melting point metal may be laminated.

[0057] Next, a resist film 403 is applied to the entire surface of the first conductive layer 103, and then, as shown in FIG. The exposure is performed using a mask 400 shown in FIG. 1. Here, a resist film having a thickness of 1.5 μm is applied. The exposure is performed using an exposure machine with a resolution of 1.5 μm. The light used for exposure is i-line (wavelength 365 nm), and the exposure energy is 70 to 140 mJ / cm 2 Select from a range of , not limited to i-line, but a mixture of i-line, g-line (wavelength 436 nm) and h-line (wavelength 405 nm) Alternatively, light emitted from the source may be used for exposure.

[0058] In this embodiment, the first photomask is an exposure mask having a light intensity reducing function in part. Auxiliary patterns (gray tones) are used to form the thin film transistors in the pixel area. The taper angle of the gate electrode is set in the range of 10° to 50°.

[0059] In FIG. 1A, the exposure mask 400 has a light-shielding portion 401b made of a metal film such as Cr. and a semi-transmitting portion 401 having a slit as an auxiliary pattern having a light intensity reducing function. In the cross-sectional view of the exposure mask 400, the width of the light-shielding portion 401b is set to t2 The width of the semi-transparent portion 401a is denoted by t1 and t3. Although an example using a light tone has been shown, a half tone using a semi-permeable film may also be used.

[0060] When the resist film 403 is exposed using the exposure mask 400 shown in FIG. Non-exposed regions 403a and 403b and exposed region 403c are formed on the photoresist film 403. 1(A) is obtained by light passing around the light-shielding portion 401b or through the semi-transparent portion 401a. ) is formed.

[0061] Then, when development is performed, the exposed region 403c is removed, and the image is left as shown in FIG. 1(B). A first resist mask 404a is formed on the element portion, and a second resist mask 404b is formed on the terminal portion. Each of these is obtained on the first conductive layer 103. By adjusting the exposure conditions such as the exposure energy, Therefore, the first resist mask 404a has a tapered shape, rather than an edge having a single step. The terminal portion exposed by the photomask in the area where the gray tone is not provided can be In this case, a second resist mask having a larger side angle in cross section than the first resist mask 404a is used. A photomask 404b is formed.

[0062] Next, using the resist masks 404a and 404b as masks, the substrate is subjected to dry etching. The first conductive layer 103 is etched by etching. The substrate 101 having the same thickness is also etched, and the thickness of the substrate is partially thinned. The top surface layer of 101 or the substrate 101 has an insulating film that may be etched. Etching gases include carbon tetrafluoride (CF4), sulfur fluoride (SF6), and chlorine (C It also uses oxygen (O2) and a wide area compared to an ICP etching system. A dry etching device that can easily obtain uniform discharge is used. The upper electrode is grounded, and the lower electrode is connected to a 13.56 MHz high-frequency power source. Furthermore, a 3.2MHz low frequency power supply was connected to the lower electrode. Capacitively Coupled Plasma (CAP) etching equipment This etching equipment is suitable for the substrate 101, for example, a 10th generation 3m It is also possible to accommodate cases where a substrate having a size exceeding 100 mm is used.

[0063] After the etching step is completed, the remaining resist mask is removed by ashing. In this way, as shown in FIG. 1(C), a first wiring layer 107a and a second wiring layer 107b are formed on the substrate 101. The second wiring layer 107b is formed on the first wiring layer 107a. The taper angle θ1 of the layer 107a is set to about 50°, and the taper angle θ1 of the second wiring layer 107b formed in the terminal portion is set to about 50°. The taper angle θ2 is set to about 70°. In a later process, a semiconductor film or a wiring layer is formed on the first wiring layer 107a. Since a line is formed, it is effective to make the taper angle on both sides small to prevent breakage. In addition, a plurality of second wiring layers 107b are arranged adjacent to each other, and are connected to an FPC or the like. Therefore, the taper angles of both sides are made large to prevent short circuits from occurring between adjacent second wiring layers 107b. In addition, it is effective to arrange a plurality of second wiring layers 107b in a narrow area. In this case, the interval between adjacent second wiring layers 107b can be narrowed, so that the tape on both sides can be It is effective to process the angle of the beam to a large value.

[0064] The resist film used in the etching process of the first conductive layer 103 is a negative resist. Since it is difficult to apply, the pattern configuration of the photomask or reticle for forming the gate electrode is , and is based on the assumption that a positive resist is used.

[0065] Next, a gate electrode made of silicon nitride (dielectric constant 7.0, thickness 300 nm) is formed on the first wiring layer 107a. An insulating film 102 is laminated. The gate insulating film 102 is formed by using a CVD method, a sputtering method, or the like. The insulating film can be formed of a silicon nitride film or a silicon nitride oxide film. The silicon dioxide film has a composition in which the nitrogen content is higher than the oxygen content, and the concentration range is As the atomic percentage, oxygen is 15 to 30%, nitrogen is 20 to 35%, silicon is 25 to 35%, and water is It refers to a material containing 15 to 25 atomic percent of elements.

[0066] Next, after the gate insulating film 102 is formed, the substrate is transported without being exposed to the atmosphere. The amorphous semiconductor film 105 is formed in a vacuum chamber different from the vacuum chamber in which the insulating film is formed. To film.

[0067] Next, after the amorphous semiconductor film 105 is formed, the substrate is transported without being exposed to the air. The semiconductor film 105 is formed in a vacuum chamber different from the vacuum chamber in which the semiconductor film 105 is formed. A semiconductor film containing an impurity is formed.

[0068] A semiconductor film to which an impurity that gives one conductivity type is added is typically doped with phosphorus. It is possible to add an impurity gas such as phosphine gas to silicon hydride. The semiconductor film doped with impurities that impart a mold is formed to a thickness of 2 nm to 50 nm. The throughput can be improved by thinning the thickness of the semiconductor film to which impurities that give one conductivity type are added. can be improved.

[0069] Next, a resist mask is formed on the semiconductor film to which an impurity imparting one conductivity type is added. The resist mask is formed by photolithography or ink-jet printing. Here, a second photomask is used to form a semiconductor doped with an impurity that gives it one conductivity type. The resist applied on the film is exposed and developed to form a resist mask.

[0070] Next, a semiconductor film to which an impurity imparting one conductivity type is added and a non- The amorphous semiconductor film 105 is etched to form an island-shaped semiconductor layer. Remove the mask.

[0071] Next, a semiconductor film doped with an impurity that imparts one conductivity type and a gate insulating film 102 are formed. The second conductive layer is formed as follows. The second conductive layer is made of aluminum, copper, silicon, or Titanium, neodymium, scandium, molybdenum, and other heat-resistant elements or hillock prevention elements It is preferable to form the insulating layer from a single layer or a multilayer of an aluminum alloy to which a blocking element is added. Although not shown, the second conductive layer is a conductive film having a three-layer laminated structure. The first and third conductive layers are made of molybdenum film, and the second conductive layer is made of aluminum film. The second conductive layer is formed by sputtering or vacuum deposition.

[0072] Next, as shown in FIG. 1(D), a resist is formed on the second conductive layer using a third photomask. A mask is formed, and a portion of the second conductive layer is etched to form a pair of source and drain electrodes. The electrodes 109 and 110 are formed. When the second conductive layer is wet-etched, the second conductive layer As a result, the edge of the source, which has an area smaller than the resist mask, is selectively etched. The source and drain electrodes 109, 110 can be formed.

[0073] Next, a semiconductor film to which an impurity that gives one conductivity type is added is formed using a resist mask. The silicon dioxide is then etched to form a pair of source and drain regions 106 and 108. In addition, part of the amorphous semiconductor film 105 is also etched in this etching step. The process of forming the source region and the drain region and the recess (groove) in the amorphous semiconductor film 105 are performed in the same process. The depth of the recess (groove) in the amorphous semiconductor film 105 can be adjusted by By making the thickness 1 / 2 to 1 / 3 of the thickest region of 05, the source and drain regions Since the distance between the source and drain regions can be increased, the leakage current between the source and drain regions can be reduced. After that, the resist mask is removed.

[0074] Next, the source or drain electrodes 109, 110, the source or drain region 1 106, 108, the amorphous semiconductor film 105, and the insulating film 111 that covers the gate insulating film 102. The insulating film 111 can be formed using the same film formation method as the gate insulating film 102. The gate insulating film 102 is resistant to contamination such as organic matter, metal matter, and water vapor floating in the air. This is to prevent the intrusion of dye impurities, and a dense membrane is preferred.

[0075] Through the above steps, a thin film transistor can be formed in the pixel portion.

[0076] Next, the insulating film 111 is selected using a resist mask formed using a fourth photomask. The first contact is selectively etched to expose the source electrode or drain electrode 109 in the pixel area. The contact holes, the insulating film 111 and the gate insulating film 102 are selectively etched to form terminals. A second contact hole is formed in the contact portion to expose the second wiring layer 107b. After the holes are formed, the resist mask is removed.

[0077] Next, after forming a transparent conductive film, a resist mask was formed using a fifth photomask. A part of the transparent conductive film is etched using a 9, and a pixel electrode 112 electrically connected to the second wiring layer 107b at the terminal portion. After the pixel electrode 112 and the connection electrode 113 are formed, a resist is The mask is then removed. The cross-sectional view after completing the steps up to this point is shown in Figure 1(D).

[0078] The transparent conductive film is made of indium oxide containing tungsten oxide, indium oxide containing tungsten oxide, Indium zinc oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide oxide, indium tin oxide, indium zinc oxide, indium doped with silicon oxide A transparent conductive material such as tin oxide can be used. The conductive layer can be formed using a conductive composition containing a conductive macromolecule (also called a conductive polymer). The pixel electrode 112 formed using the conductive composition has a sheet resistance of 10000 Ω / □ The transmittance at a wavelength of 550 nm is preferably 70% or more. The resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less.

[0079] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0080] In this way, an element substrate that can be used in a transmission type liquid crystal display device can be formed. .

[0081] In addition, we conducted an experiment and measured the cross-section SE of the wiring obtained by etching using a gray-tone mask. A photograph is shown in Figure 2.

[0082] The sample was prepared by depositing a silicon oxynitride film with a thickness of 100 nm on a glass substrate, and then depositing a 400 nm A titanium film was formed on the titanium film. A resist film was then formed on the titanium film.

[0083] The resist film was exposed using an exposure device with a resolution of 1.5 μm and then developed. As the first etching condition, the flow rate of BCl3 gas was set to 40 sccm, and the flow rate of Cl2 gas was set to 0.5 sccm. After etching for 65 seconds with the flow rate set to 40 sccm, the second etching condition was changed to B Etching was performed with the Cl3 gas flow rate set to 70 sccm and the Cl2 gas flow rate set to 10 sccm. We conducted a survey.

[0084] The cross section of the wiring in the area without gray tones corresponds to Figure 2(A). The width of the light-shielding part is 3 μm. The taper angle of the wiring in FIG. 2(A) is approximately 50°.

[0085] In addition, exposure was performed using a gray-tone mask with a line width of 0.5 μm and a space width of 0.5 μm. The cross section of the wiring in the shaded area corresponds to Figure 2(B). The width of the light-shielding part is 3 μm. The taper angle of the wiring is approximately 40°.

[0086] In addition, a grate with a line width of 0.5 μm and a space width of 0.5 μm repeated twice was used. The cross section of the wiring in the exposed area using the light-shielding mask corresponds to Figure 2(C). The taper angle of the wiring in Figure 2(C) is approximately 30°.

[0087] Even if the width of the light-shielding part is the same, the width of the gray tone line and space can affect the image quality. The resulting wiring width and taper angle can be varied. When experiments were conducted by changing the wiring shape and space width, The wiring shape may have a broken portion.

[0088] Here, the experiment was conducted under the above etching conditions, but there are no particular limitations. The resists with different resist angles are obtained, and wiring that reflects the resist shape is obtained. It is desirable that the operator appropriately adjust the mask design and etching conditions.

[0089] (Embodiment 2) In this embodiment mode, when forming a wiring on an interlayer insulating film covering a thin film transistor, An example of making the cross-sectional shape different between the terminal portion and the substrate will be described with reference to FIG.

[0090] Since the steps up to this stage are the same as those in the first embodiment, detailed explanations will be omitted here. In addition, in FIG. 3, the same parts as those in FIG. 1 will be described using the same reference numerals.

[0091] In this embodiment, a flat film is formed on the insulating film 111 that covers the thin film transistor formed in the first embodiment. This is an example of forming a film.

[0092] First, the steps up to the formation of the insulating film 111 are carried out in accordance with the first embodiment.

[0093] Next, a planarization film 114 is formed. The planarization film 114 is formed of an organic resin film. Next, The insulating film 111 and the planarizing film 112 are formed using a resist mask formed using the fourth photomask. 114 is selectively etched to expose the source electrode or drain electrode 109 in the pixel area. A first contact hole is formed, and the gate insulating film 102, the insulating film 111, and the planarizing film are formed. The second contact 114 is selectively etched to expose the second wiring layer 107b at the terminal portion. This creates a hole.

[0094] Next, a third conductive layer 115 is formed on the planarizing film 114. corresponds to Figure 3(A).

[0095] Next, a resist film is applied to the entire surface of the third conductive layer 115, and then the mask shown in FIG. Exposure is performed using the 410.

[0096] In this embodiment, a fourth photomask is provided as an exposure mask having a light intensity reducing function in a part thereof. One side of the connection electrode of the terminal is provided with an auxiliary pattern (gray tone) The taper angle of the surface is in the range of 10° to 50°.

[0097] In FIG. 3B, the exposure mask 410 has a light-shielding portion 411a made of a metal film such as Cr. and a semi-transmitting portion 411 having a slit as an auxiliary pattern having a light intensity reducing function. Here we show an example where gray tones are used as part of the exposure mask. However, a halftone using a semi-permeable film may also be used.

[0098] When the resist film is exposed using the exposure mask 410 shown in FIG. 3(B), Non-exposed regions 413a and 413b and exposed region 413c are formed. 3B. Region 413c is formed.

[0099] Then, when development is performed, the exposed region 413c is removed, and the third resist mask is left in the pixel portion. A resist mask is formed on the third conductive layer 115, and a fourth resist mask is formed on the terminal portion. By adjusting the exposure conditions such as light energy, it is possible to create a single step on one side instead of an edge. A fourth resist mask having a tapered surface can be obtained.

[0100] Next, using the third resist mask and the fourth resist mask as masks, a dry etching process is performed. The third conductive layer 115 is etched by etching. A dry etching device is used, which makes it easier to obtain uniform discharge over a wide area. In such a dry etching device, the upper electrode is grounded and the lower electrode is connected to a 13.56MH An ECC with a high frequency power supply of 3.2 MHz connected to the lower electrode and a low frequency power supply of 3.2 MHz connected to the lower electrode. P(Enhanced Capacitively Coupled Plasma) In this etching system, for example, the substrate 101 and This also makes it possible to use 10th generation substrates that are larger than 3m.

[0101] The cross-sectional view of the process up to this stage corresponds to FIG. 3(C). The resist mask is also etched when the third conductive layer 115 is etched, and the first connecting electrode 116 is removed. A third resist mask 414a is formed on the electrode 116, and a fourth resist mask 414b is formed on the second connection electrode 117. The mask 414b remains. The second connection electrode 117 is formed by reflecting the shape of the fourth resist mask. Only one side is tapered. In the pixel portion exposed by the photomask in the region where no photoresist is present, the area of ​​the first connection electrode 116 is The etching is performed to make the area smaller, which can contribute to improving the aperture ratio.

[0102] After the etching step is completed, the remaining resist mask is removed by ashing. Remove.

[0103] Next, after forming a transparent conductive film, a resist mask was formed using a fifth photomask. A part of the transparent conductive film is etched using a a pixel electrode 118 electrically connected to the second connection electrode 117 at the terminal portion; After the pixel electrode 118 and the third connection electrode 119 are formed, a resist The cross-sectional view after the process up to this point corresponds to Figure 3(D). The connection electrode 119 is arranged so as to overlap the tapered portion of the second connection electrode 117. By providing this, it is possible to prevent the third connection electrode 119 from being broken.

[0104] In this way, an element substrate that can be used in a transmission type liquid crystal display device can be formed. .

[0105] In addition, we conducted an experiment and measured the cross-section SE of the wiring obtained by etching using a gray-tone mask. The photograph is shown in Figure 4.

[0106] The sample was prepared by depositing a silicon oxynitride film with a thickness of 100 nm on a glass substrate, and then depositing a 400 nm A titanium film was formed on the titanium film. A resist film was then formed on the titanium film.

[0107] The resist film was exposed using an exposure device with a resolution of 1.5 μm and then developed. As the first etching condition, the flow rate of BCl3 gas was set to 40 sccm, and the flow rate of Cl2 gas was set to 0.5 sccm. After etching for 65 seconds with the flow rate set to 40 sccm, the second etching condition was changed to B Etching was performed with the Cl3 gas flow rate set to 70 sccm and the Cl2 gas flow rate set to 10 sccm. We conducted a survey.

[0108] As shown in the photomask in Figure 3(B), the line width is 0.5 μm and the space is 0.5 μm on only one side. Wiring in the exposed area using a gray-tone mask with two 0.5 μm width repeats The cross section of the prism corresponds to Figure 4(A). One taper angle is about 70°, and the other taper angle is is about 35°.

[0109] In addition, a grate with a line width of 0.5 μm and a space width of 0.75 μm is arranged on only one side. The cross section of the wiring in the region exposed using the laser mask corresponds to Figure 4(B). The first side is about 70°, and the second side is more gentle than the first, resulting in different taper angles. The other side has a taper angle of about 30° on the side closer to the substrate. The taper angle on the far side is approximately 60°.

[0110] Note that a line width of 0.5 μm and a space width of 0.5 μm are arranged three times on only one side. When exposed using a gray-tone mask, a wiring shape with a step on the side was obtained. In this way, if the line width and space width are changed, the resulting wiring shape changes significantly. Therefore, the operator must select the optimum line width and space width and optimize the etching conditions. It is important to optimize it.

[0111] Also, semi-transparent areas formed with lines and spaces or rectangular patterns and spaces An example of an exposure mask having the above structure will be described with reference to FIG.

[0112] A specific example of a top view of an exposure mask is shown in FIG. 5(A). An example of the light intensity distribution 214 is shown in Fig. 5(B). The exposure mask shown in Fig. 5(A) has a light-shielding portion P , semi-transmitting portion Q, and transmitting portion R. The semi-transmitting portion Q of the exposure mask shown in FIG. Lines 203, 205, 207 and spaces 201 are arranged in a stripe or slit shape. , 204, 206 are repeatedly provided, and the lines and spaces are arranged at the end 202 of the light-shielding portion P. In this semi-transparent portion, the lines 205 made of light-shielding material are arranged in a parallel direction. The width of the line 203 is L, and the width of the space 204 between the light-shielding materials is W2. The line 203 is formed in a rectangular shape. However, it is not limited to this. It is sufficient if it has a certain width. For example, It may also have a curved shape.

[0113] In the exposure mask of FIG. 5(A), the width W of the space 204 is smaller than the width W1 of the space 201. 2 is wider, and the width W3 of space 206 is wider than the width W2 of space 204. In addition, in the exposure mask of FIG. 5(A), the line width is the same.

[0114] The exposure mask shown in FIG. 5(A) is an example, and the light intensity distribution shown in FIG. 5(B) can be obtained. For example, as shown in FIG. 5(C), Exposure is performed using an exposure mask having a light-shielding portion 215 with an acute angle at the end, and the resulting film is In addition, the light intensity distribution is set to be as shown in FIG. The light intensity distribution shown in FIG. 5(B) is obtained by using an exposure mask having the above structure.

[0115] This embodiment mode can be freely combined with Embodiment Mode 1.

[0116] (Embodiment 3) This embodiment is an example that is partly different from Embodiment 2, and will be described with reference to FIG. 6. Since the figure is the same as in FIG. 3(A), detailed explanations are omitted here, and the same parts are denoted by the same reference numerals. This will be used to explain.

[0117] According to the second embodiment, the steps up to the formation of the third conductive layer 115 are carried out, and the result is shown in FIG. The same stage.

[0118] Next, the third conductive layer 115 is selectively etched using a photomask different from that used in the second embodiment. In this embodiment, the pixel portion has a taper angle on only one side. A first connection electrode 120 is formed, and a second connection electrode 120 having the same taper angle at both ends is formed at the terminal portion. This is an example of forming an electrode 121.

[0119] After the etching step is completed, the remaining resist mask is removed by ashing. Remove.

[0120] Next, after forming a transparent conductive film, a resist mask was formed using a fifth photomask. A part of the transparent conductive film is etched using a The pixel electrode 122 is electrically connected to the terminal portion, and the second connection electrode 121 is electrically connected to the terminal portion. A third connection electrode 123 is formed.

[0121] In this embodiment, the pixel electrode 122 has a tapered shape of the first connection electrode 120. By arranging the pixel electrode 122 so as to overlap the portion where the pixel electrode 122 is being cut off, the pixel electrode 122 is prevented from being cut off.

[0122] In this way, an element substrate that can be used in a transmission type liquid crystal display device can be formed. .

[0123] This embodiment mode can be freely combined with Embodiment Mode 1 or 2.

[0124] (Fourth embodiment) In this embodiment, an auxiliary pattern ( This is an example of using a halftone film.

[0125] First, as in the first embodiment, a first conductive layer 103 is formed on a substrate 101, and a laser is formed on the first conductive layer 103. Forms a gyrst membrane.

[0126] In FIG. 7A, the exposure mask 420 has a light-shielding portion 421a made of a metal film such as Cr. , 421b, and a semi-transparent film (halftone film) as an auxiliary pattern having a light intensity reducing function. and a portion where the semi-transparent portion 422a and the semi-transparent portion 422b are provided. In the cross-sectional view of the exposure mask 420, the light-shielding portion 421b and the semi-transmitting portion 422b are shielded. The width of the overlapping area of ​​the light-transmitting portion 421b and the semi-transmitting portion 422b is denoted by t2. , the width of the region of one layer is shown as t1 and t3. The widths of the regions that do not overlap with the portion 421a are denoted as t1 and t3.

[0127] When the resist film is exposed using the exposure mask 420 shown in FIG. 7(A), Non-exposed regions 423a and 423b and exposed region 423c are formed. By passing through the semi-transparent portions 422a and 422b, An exposed region 423c shown in FIG. 7(A) is formed.

[0128] Then, when development is performed, the exposed region 423c is removed, and as shown in FIG. 7(B), The resist mask 424a has a rectangular cross section. A mask 424b is obtained on the first conductive layer 103.

[0129] Next, using the resist masks 424a and 424b as masks, the substrate is subjected to dry etching. The first conductive layer 103 is then etched.

[0130] After the etching step is completed, the remaining resist mask is removed by ashing. In this way, as shown in FIG. 7(C), the first wiring layer 124a and the The second wiring layer 124b is formed on the first wiring layer 124a. The taper angle of the layer 124a is set to about 60°, and the side surface of the second wiring layer 124b formed in the terminal portion The angle is approximately 90°.

[0131] The subsequent steps are carried out in accordance with the first embodiment to form a thin film transistor, and a transmissive liquid crystal display device. An element substrate that can be used for the above is formed.

[0132] This embodiment can be freely combined with embodiment 1, embodiment 2, or embodiment 3. It is possible.

[0133] (Embodiment 5) In this embodiment, the wiring has a cross-sectional shape with two steps, a trapezoidal cross-sectional shape, and a single This is an example in which three types of cross-sectional shapes having steps are formed using the same mask.

[0134] First, as in the first embodiment, a first conductive layer 103 is formed on a substrate 101, and a laser is formed on the first conductive layer 103. Forms a gyrst membrane.

[0135] Next, the resist film is exposed to light using an exposure mask 430 shown in FIG. When the film is exposed, the resist film has non-exposed regions 433a, 433b, and 433d and exposed regions 433a, 433b, and 433d. During exposure, light is guided around the light-shielding portion 431b and through the semi-transmitting portion 431a and 33c. By passing through 431c, an exposed area 433c shown in FIG. 8(A) is formed.

[0136] In this embodiment, the first photomask is an exposure mask having a light intensity reducing function in part. Auxiliary patterns (gray tones) are used to form the thin film transistors in the pixel area. Two steps are formed on both ends of the gate electrode. The first photomask is shown in FIG. The pattern shown in the figure is placed on both sides of the light-shielding part. By changing the conditions, a light intensity distribution different from that shown in FIG. 5(B), for example, the light intensity distribution shown in FIG. 5(E), can be obtained. The light intensity distribution 217 has two steps. For example, as shown in FIG. 5C, a light blocking pattern having a sharp edge is used instead of a line. Exposure is performed using an exposure mask having a portion 215, and the light intensity distribution shown in FIG. 5(E) is obtained. Also, an exposure mask having a light-shielding portion 216 with a plurality of branch portions as shown in FIG. A mask may be used to obtain the light intensity distribution shown in FIG. 5(E).

[0137] In addition, a step is formed on both ends of the connection electrode in the terminal section. It is formed by using a semi-transparent portion 431c that is different from the gate electrode.

[0138] Then, when development is performed, the exposed region 433c is removed, and as shown in FIG. 8(B), A first resist mask 434a is formed on the element portion, and a second resist mask is formed on the gate wiring portion of the pixel portion. A resist mask 434b is formed on the first conductive layer 103, and a third resist mask 434c is formed on the terminal portion. By adjusting the exposure conditions such as exposure energy, a first step with two steps at the edge can be obtained. The resist mask 434a of 1 can be obtained. In the gate wiring portion of the pixel portion exposed with the photomask, a trapezoidal second resist A mask 434b is formed. A third resist having a step at the end is formed on the terminal portion. A top mask 434c can be obtained.

[0139] Next, using the resist masks 434a, 434b, and 434c as masks, dry etching is performed. The first conductive layer 103 is etched by etching.

[0140] After the etching step is completed, the remaining resist mask is removed by ashing. In this way, as shown in FIG. 8(C), the first wiring layer 125a and the A second wiring layer 125b and a third wiring layer 125c are formed. The first wiring layer 125a formed in the above-mentioned manner has two steps at the end, and the gate wiring of the pixel portion is The side of the second wiring layer 125b formed in the terminal portion is trapezoidal, and the side of the third wiring layer 125b formed in the terminal portion is trapezoidal. The wire layer 125c has an end portion with one step. When the wire layer 125c has a tapered shape, the end of the tapered The position of the part is affected by the etching time, and especially when the taper angle is less than 60°, the total However, by using a stepped wiring layer, it is possible to reduce the etching time. Even if the time varies slightly, a constant wiring width can be obtained. This allows for a sufficient margin in the etching conditions. By making the end portion have two steps, it has a tapered shape with a taper angle of less than 50° It is possible to ensure the same level of step coverage as the wiring layer. The side angle of the formed second wiring layer 125b is in the range of 60° to 90°.

[0141] In this way, the operator can select the desired shape of the wiring layer by appropriately designing the exposure mask 430. It can be formed automatically.

[0142] The subsequent steps are carried out in accordance with the first embodiment to form a thin film transistor, and a transmissive liquid crystal display device. An element substrate that can be used for the above is formed.

[0143] This embodiment is the same as the first, second, third, or fourth embodiment. can be freely combined.

[0144] (Sixth embodiment) In this embodiment mode, a manufacturing process of a thin film transistor used in a liquid crystal display device will be described with reference to FIGS. 9 to 11 show the manufacturing process of a thin film transistor. 12 is a cross-sectional view of a thin film transistor and a pixel electrode in one pixel. FIG. 13 is a timing chart showing a method for forming a microcrystalline silicon film. FIG. 14 is a cross-sectional view of an etching device used to form electrodes or wiring. be.

[0145] Thin film transistors with microcrystalline semiconductor films have higher mobility when they are n-type than when they are p-type. It is more suitable for use in operating circuits. It is desirable to have the same polarity in order to reduce the number of processes. This will be explained using a thin film transistor of this type.

[0146] As shown in FIG. 9A, a gate electrode 51 is formed on a substrate 50. The substrate 50 is aluminoborosilicate glass, aluminoborosilicate glass, or aluminosilicate glass It is possible to use alkali-free glass substrates manufactured by the fusion method or the float method. If the substrate 50 is a mother glass, the size of the substrate is 0mm), 2nd generation (400mm x 500mm), 3rd generation (550mm x 650mm) , 4th generation (680mm x 880mm or 730mm x 920mm), 5th generation (1 000mm x 1200mm or 1100mm x 1250mm), 6th generation 1500mm x 1800mm), 7th generation (1900mm x 2200mm), 8th generation (2160mm) ×2460mm), 9th generation (2400mm×2800mm, 2450mm×3050mm m), 10th generation (2950mm x 3400mm), etc. can be used.

[0147] The gate electrode 51 is made of titanium, molybdenum, chromium, tantalum, tungsten, or aluminum. The gate electrode 51 is formed by sputtering. A conductive film is formed on the substrate 50 by coating or vacuum deposition, and the conductive film shown in Embodiment 1 is formed on the conductive film. A resist mask is formed using a multi-tone mask, and the conductive film is etched using the mask. In addition, a barrier layer is formed to improve the adhesion of the gate electrode 51 and to prevent diffusion to the underlying layer. As a metal, a nitride film of the above metal material may be provided between the substrate 50 and the gate electrode 51. Here, a resist mask formed using a multi-tone photomask is used. The conductive film formed on the substrate 50 is then etched to form a gate electrode 51. Wiring with different side angles (gate wiring, routing wiring, capacitance wiring, etc.) can also be formed at the same time. do.

[0148] In this case, etching is performed using the etching apparatus shown in FIG.

[0149] The etching apparatus shown in FIG. 14 has an upper electrode 137 grounded and a lower electrode 135 connected to a ground potential of 13.5 V. A 6 MHz high frequency power supply 132 is connected, and a 3.2 MHz low frequency power supply is further connected to the lower electrode 135. ECCP (Enhanced Capacitive Coupling) connected to source 131 This etching equipment operates in the LED Plasma mode. For example, the substrate 50 can be used in a case where a 10th generation substrate having a size exceeding 3 m is used. It is possible.

[0150] The chamber 130 has an opening on the outer wall thereof for introducing a substrate to be processed. The gate valve 133 is provided in the substrate loading chamber or the access point. The chamber 130 is connected to the unloading chamber or the transfer chamber. The pressure in the chamber 130 can be reduced by using a vacuum pump or other vacuum exhaust means. It has a pair of parallel plate electrodes consisting of an upper electrode 137 and a lower electrode 135 .

[0151] The upper electrode 137 is a shower head, and an etching gas is introduced into the chamber 130. A plurality of openings are provided for introducing the etching gas supplied to the hollow portion of the upper electrode 137. The cooling gas is supplied from a gas supply mechanism 139 connected via a gas supply pipe and a valve. Furthermore, the gas supply mechanism 139 is connected to the gas supply source 138 .

[0152] An insulating member 134 is provided on the outer periphery and the upper peripheral edge of the lower electrode 135. However, the lower electrode 135 is provided with a device such as an electrostatic chuck for holding the substrate 136 to be processed. The apparatus has a substrate holding means and a heating or cooling means for adjusting the temperature. The outer electrode 137 may be provided with a heating means or a cooling means for adjusting the temperature.

[0153] A power supply line is electrically connected to the lower electrode 135, and the first matching unit 1 40a is connected to a high frequency power supply 132. The high frequency power supply 132 is a 13.56 MHz The high frequency power for plasma generation is supplied to the lower electrode. The combiner 140b is connected to a low-frequency power supply 131. The low-frequency power supply 131 is, for example, A 0.2MHz high frequency power is supplied to the lower electrode and is superimposed on the high frequency power for plasma generation. It looks like this.

[0154] Each component of the etching apparatus shown in FIG. 14 is controlled by a process controller. By using this etching equipment, even 10th generation substrates exceeding 3m in size can be It is possible to ensure in-plane uniformity.

[0155] Next, gate insulating films 52a, 52b, and 52c are formed in this order on the gate electrode 51. The cross-sectional view after completing the steps up to this point corresponds to FIG. 9(A).

[0156] The gate insulating films 52a, 52b, and 52c are formed by using a CVD method, a sputtering method, or the like. The insulating film can be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. To prevent interlayer shorts caused by pinholes in the gate insulating film, It is preferable to form a multi-layer structure using insulating layers. 2c shows a configuration in which a silicon nitride film, a silicon oxynitride film, and a silicon nitride film are laminated in this order. vinegar.

[0157] Here, the silicon oxynitride film is a film whose composition contains more oxygen than nitrogen. The concentration ranges are 55 to 65 atomic % for oxygen, 1 to 20 atomic % for nitrogen, and 25 to 30 atomic % for silicon. 35 atomic % and hydrogen in the range of 0.1 to 10 atomic %.

[0158] The thickness of both the first and second layers of the gate insulating film is set to be greater than 50 nm. The first layer is silicon nitride to prevent the diffusion of impurities (such as alkali metals) from the substrate. The first layer of the gate insulating film is preferably a silicon nitride oxide film. In addition to preventing oxidation, it can also prevent hillocks when aluminum is used for the gate electrode. The third layer of the gate insulating film in contact with the crystalline semiconductor film is thicker than 0 nm and less than 5 nm, preferably The third layer of the gate insulating film is about 1 nm thick to improve adhesion with the microcrystalline semiconductor film. In addition, by using a silicon nitride film as the third layer of the gate insulating film, For example, when the oxygen content is When heat treatment is performed in a state where a thick insulating film and a microcrystalline semiconductor film are in contact with each other, the microcrystalline semiconductor film is oxidized. There is a risk.

[0159] Furthermore, a gate insulating film was formed using a microwave plasma CVD device with a frequency of 1 GHz. It is preferable to form a silicon oxynitride film or a silicon nitride film using a microwave plasma CVD apparatus. The silicon dioxide film has a high breakdown voltage and can improve the reliability of the thin film transistor.

[0160] Here, the gate insulating film has a three-layer structure, but it is also used as a switching element for a liquid crystal display device. In this case, only a single layer of silicon nitride film may be used for AC drive.

[0161] Next, after the gate insulating film is formed, the substrate is transported without being exposed to the atmosphere. The microcrystalline semiconductor film 53 is formed in a vacuum chamber different from the vacuum chamber in which the It is preferable that:

[0162] A procedure for forming the microcrystalline semiconductor film 53 will be described below with reference to FIG. The explanation in 13 starts from the stage of evacuating the vacuum chamber from atmospheric pressure to vacuum 200. Pre-coating 1201, substrate loading 1202, substrate pre-treatment 1203, and film formation process are performed after this. The processes of 1204, 1205, and 1206 are shown in chronological order. However, it is not limited to evacuation from atmospheric pressure, and it is also possible to maintain a certain degree of vacuum in the vacuum chamber at all times. It is preferable to maintain the same level of vacuum for mass production, or to reduce the ultimate vacuum in a short time. Above is preferred.

[0163] In this embodiment, the degree of vacuum in the vacuum chamber before the substrate is carried in is set to 10 -5 Lower than Pa This stage corresponds to the vacuum pumping 1200 in FIG. When performing high vacuum evacuation, a cryopump is used in combination with a turbomolecular pump. Furthermore, it is preferable to use a cryopump to evacuate the chamber. It is also effective to connect the cells in a row and evacuate them. It is preferable to provide a heater and perform a heat treatment to remove gases from the inner wall of the vacuum chamber. The heater for heating the substrate is also operated to stabilize the temperature. The heating is carried out at a temperature of from 120 to 220°C.

[0164] Next, a pre-coat 1201 is performed before the substrate is carried in, and a silicon film is formed as an inner wall coating film. As the precoat 1201, hydrogen or a rare gas is introduced to generate plasma and create a vacuum. Gases adhering to the inner wall of the chamber (atmospheric components such as oxygen and nitrogen, or vacuum chamber After removing the etching gas used to clean the plate, silane gas is introduced to Silane gas reacts with oxygen, moisture, etc., so if silane gas is passed through the By generating silane plasma in the vacuum chamber, oxygen and moisture can be removed. In addition, by performing the pre-coat 1201 treatment, the vacuum chamber is formed in the microcrystalline silicon film. This prevents the metal elements of the components that make up the member from being absorbed as impurities. In other words, by covering the inside of the vacuum chamber with silicon, the inside of the vacuum chamber This prevents the silicon from being etched by the plasma, and the silicon is contained in the microcrystalline silicon film that is formed later. The pre-coat 1201 can reduce the impurity concentration in the inner wall of the vacuum chamber. This involves coating the substrate with a film of the same type as the film to be deposited on it.

[0165] After pre-coating 1201, the substrate is loaded 1202. A microcrystalline silicon film is deposited. The substrates to be tested are stored in a vacuum-evacuated load chamber. The degree of vacuum in the empty chamber does not deteriorate significantly.

[0166] Next, a base pretreatment 1203 is performed. The base pretreatment 1203 is a process for forming a microcrystalline silicon film. In other words, it is a particularly effective treatment when the glass substrate surface A microcrystalline silicon film is formed on the surface of an insulating film or on the surface of amorphous silicon by plasma CVD. When forming a film by this method, the film becomes amorphous in the early stage of deposition due to factors such as impurities and lattice mismatch. The thickness of this amorphous layer should be reduced as much as possible, and if possible, eliminated. It is preferable to perform a base pretreatment 1203 for this purpose. It is preferable to carry out the treatment by rare gas plasma, hydrogen plasma treatment, or a combination of the two. For the Zuma treatment, rare gas elements with large mass numbers such as argon, krypton, and xenon are used. It is preferable to use a spatula to remove impurities such as oxygen, moisture, organic matter, and metal elements adhering to the surface. The hydrogen plasma treatment removes the surface by hydrogen radicals. Removal of the impurities adsorbed on the surface and etching of the insulating film or amorphous silicon film This is effective in forming a clean film-forming surface. The use of plasma treatment in combination helps to promote the formation of microcrystalline nuclei.

[0167] In terms of promoting the generation of microcrystalline nuclei, as shown by the dashed line 1207 in FIG. In addition, it is effective to continue supplying a rare gas such as argon in the initial stage of the formation of the microcrystalline silicon film. It is effective.

[0168] Next, a substrate pretreatment 1203 is followed by a film formation treatment 1204 for forming a microcrystalline silicon film. In this embodiment, the first film formation condition, which has a low film formation rate but good quality, is used to form a gate insulating film interface. A film is formed in the vicinity of the first film, and then the film is deposited under second film formation conditions with a higher film formation rate.

[0169] There is no particular limitation as long as the film formation rate under the second film formation condition is faster than the film formation rate under the first film formation condition. Therefore, high frequency plasma CVD methods with frequencies of several tens to several hundreds of MHz, or is formed by a microwave plasma CVD apparatus of 1 GHz or more, and typically, SiH4, Silicon hydride such as Si2H6 can be diluted with hydrogen and plasma generated to form a film. In addition to silicon hydride and hydrogen, it can also be produced from helium, argon, krypton, and neon. A microcrystalline semiconductor film can be formed by diluting the semiconductor with one or more selected rare gas elements. In these cases, the flow rate ratio of hydrogen to silicon hydride is preferably 12 times or more and 1000 times or less. Preferably, it is 50 times or more and 200 times or less, and more preferably 100 times. Instead, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. can be used. .

[0170] In addition, when helium is added to the material gas, helium has the highest energy of all gases at 24.5 eV. has a high ionization energy, and is slightly lower than that, about 20 eV Since there is a metastable state at this level, the difference in ionization is about 4 eV during the duration of the discharge. Therefore, the discharge initiation voltage is the lowest among all gases. Due to its properties, helium can maintain a stable plasma. Therefore, even if the area of ​​the substrate on which the microcrystalline silicon film is deposited becomes large, the process This has the effect of making the plasma density uniform.

[0171] In addition, carbon hydrides such as CH4 and C2H6, GeH4, GeF4 By mixing germanium hydride and germanium fluoride, the energy bandwidth can be increased to 1. It may be adjusted to 5 to 2.4 eV or 0.9 to 1.1 eV. Adding luminium can change the temperature characteristics of the TFT.

[0172] Here, the first film formation condition is that silane is mixed with hydrogen and / or a rare gas at a concentration of 100 times or more and 2000 times or more. The substrate is heated to a temperature of 100 to 300°C, preferably 120 to 220°C. The growth surface of the microcrystalline silicon film is inactivated with hydrogen to promote the growth of microcrystalline silicon. To achieve this, it is preferable to perform film formation at a temperature of 120°C to 220°C.

[0173] FIG. 9B shows a cross-sectional view of the gate insulating film 52c after the first film formation condition is completed. Although the deposition rate is low, a high-quality microcrystalline semiconductor film 23 is formed. The quality of the microcrystalline semiconductor film 23 obtained under these conditions will increase the on-current of the TFT to be formed later and To improve the field-effect mobility, the oxygen concentration in the film is 1×10 17 / cm or less It is important to reduce the oxygen concentration sufficiently so that the Therefore, the concentration of nitrogen and carbon mixed into the microcrystalline semiconductor film can be reduced. Therefore, the microcrystalline semiconductor film can be prevented from becoming n-type.

[0174] Next, the film formation conditions are changed to the second film formation conditions, and the film formation rate is increased to form a microcrystalline semiconductor film 53. The cross-sectional view at this stage corresponds to FIG. 9(C). The thickness of the insulating film 100 may be set to 0 nm (preferably 100 nm to 250 nm). The deposition time of the microcrystalline semiconductor film 53 is the first deposition period in which the film is deposited under the first deposition condition. and a second film formation period in which film formation is performed under second film formation conditions.

[0175] Here, the second film formation conditions are that silane is 12 times or more and 100 times or less with hydrogen and / or rare gas. The substrate is heated to a temperature of 100 to 300°C, preferably 120 to 220°C. In addition, a capacitively coupled (parallel plate) CVD device was used, and the gap (the distance between the electrode surface and the substrate surface) The spacing between the electrodes was set to 20 mm, the vacuum level in the vacuum chamber was set to 100 Pa, and the substrate temperature was set to 300°C. Then, 20 W of 60 MHz high frequency power was applied, and silane gas (flow rate 8 sccm) was mixed with hydrogen (flow rate 400 sccm) and diluted 50 times to form a microcrystalline silicon film. Then, the flow rate of silane gas was changed to 4 sccm and diluted 100 times to form a microcrystalline silicon film. The deposition rate slows down when the hydrogen flow rate is fixed and the silane flow rate is increased. By decreasing the deposition rate, the crystallinity improves.

[0176] In this embodiment, a capacitively coupled (parallel plate) CVD apparatus is used, and a gap (between the electrode surface and The first film formation condition was set to a vacuum of 100P in the vacuum chamber. a, the substrate temperature was set to 100°C, and 30 W of 60 MHz high frequency power was applied. Silane gas (flow The gas flow rate was 200 times diluted with hydrogen (flow rate 400 sccm). The second deposition condition was to increase the deposition rate by changing the flow rate of silane gas at 4 sccm and hydrogen gas (flow rate 4 The film is formed under the condition of diluting the solution 100 times at a flow rate of 0.00 sccm.

[0177] Next, after the formation of the microcrystalline silicon film under the second film formation conditions is completed, materials such as silane and hydrogen are added. The supply of the source gas and high frequency power is stopped and the substrate is unloaded 1205. When a film formation process is to be performed using the vacuum chamber, the process returns to the stage of substrate loading 1202 and the same process is performed. Cleaning 1206 is performed to remove any coating or powder adhering to the inside of the chamber.

[0178] Cleaning 1206 is a plasma etching process using NF3 and SF6. Etching is performed. Also, etching is possible without using plasma like ClF3. In cleaning 1206, the heater for heating the substrate is turned off. It is preferable to lower the temperature in order to suppress the generation of reaction by-products due to etching. After the cleaning 1206 is completed, the wafer returns to the pre-coat 1201 and is then placed on the next substrate. Since NF3 contains nitrogen in its composition, the nitrogen in the film formation chamber In order to reduce the concentration, it is desirable to carry out precoating to sufficiently reduce the nitrogen concentration.

[0179] Next, after the microcrystalline semiconductor film 53 is formed, the substrate is transported without being exposed to the air. The buffer layer 54 is formed in a vacuum chamber different from the vacuum chamber in which the semiconductor film 53 is formed. By separating the buffer layer 54 from the vacuum chamber, it is possible to The vacuum chamber in which the film 53 is formed is a dedicated chamber that is evacuated to an ultra-high vacuum before the substrate is introduced. This minimizes contamination by impurities and shortens the time required to reach an ultra-high vacuum. When baking is performed to achieve ultra-high vacuum, the temperature of the chamber inner wall drops and stabilizes. This is particularly effective because it takes time for the vacuum chamber to The frequency of the high frequency power can be varied to suit the desired film quality. .

[0180] The buffer layer 54 is formed using an amorphous semiconductor film containing hydrogen or halogen. The flow rate of hydrogen is 1 to 10 times, more preferably 1 to 5 times, the flow rate of silicon hydride. The amorphous semiconductor film containing hydrogen can be formed by using the above silicon hydride. Gases containing fluorine, chlorine, bromine, or iodine (F2, Cl2, Br2, I2, HF, H By using (e.g., Cl, HBr, HI), amorphous materials containing fluorine, chlorine, bromine, or iodine can be obtained. It is possible to form a high-quality semiconductor film. iHCl3, SiCl4, SiF4, etc. can be used.

[0181] The buffer layer 54 is formed by sputtering with hydrogen or a rare gas using an amorphous semiconductor as a target. An amorphous semiconductor film can be formed by quartz crystallization. , bromine, or iodine-containing gases (F2, Cl2, Br2, I2, HF, HCl, HBr , HI, etc.) to form amorphous semiconductors containing fluorine, chlorine, bromine, or iodine. A body membrane can be formed.

[0182] The buffer layer 54 is preferably formed of an amorphous semiconductor film that does not contain crystal grains. Therefore, high frequency plasma CVD method with a frequency of several tens to several hundreds of MHz or microwave plasma CVD method is used. When forming the film using the Zuma CVD method, the film formation conditions are adjusted so that the film becomes an amorphous semiconductor film that does not contain crystal grains. It is preferable to control the conditions.

[0183] The buffer layer 54 is partially etched in the subsequent process of forming the source and drain regions. At this time, a part of the buffer layer 54 is removed so that the microcrystalline semiconductor film 53 is not exposed. It is preferable to form the film with a thickness that allows the film to remain. It is preferable to form the thin film transistor with a thickness of 200 nm or more and 300 nm or less. In display devices where the applied voltage to the transistor is high (for example, about 15 V), typically liquid crystal display devices In this case, if the thickness of the buffer layer 54 is made thick as shown in the above range, the breakdown voltage becomes high, Even if a high voltage is applied to the thin film transistor, the thin film transistor is prevented from deteriorating. It is possible.

[0184] The buffer layer 54 is doped with impurities such as phosphorus or boron that impart one conductivity type. The impurity imparting one conductivity type is not added to the semiconductor film 55. The buffer layer 54 functions as a barrier layer to prevent substances from diffusing into the microcrystalline semiconductor film 53. When no buffer layer is provided, the microcrystalline semiconductor film 53 and the impurity imparting one conductivity type are added. If the semiconductor film 55 comes into contact with the impurities, the impurities will be removed by the subsequent etching process or heat treatment. may move, making it difficult to control the threshold.

[0185] Furthermore, a buffer layer 54 is formed on the surface of the microcrystalline semiconductor film 53. It is possible to prevent natural oxidation of the surface of the crystal grains contained in 53. In the area where the matrix and the microcrystalline grains come into contact, cracks are easily generated due to local stress. If the crystal grains are exposed to heat, they will be oxidized and silicon oxide will be formed.

[0186] The energy gap of the buffer layer 54, which is an amorphous semiconductor film, is smaller than that of the microcrystalline semiconductor film 53. The energy gap of the amorphous semiconductor film is 1.6 eV or more and 1.8 eV or less. The energy gap of the crystalline semiconductor film 53 is 1.1 eV or more and 1.5 eV or less, and the resistance is high. The mobility is low, being 1 / 5 to 1 / 10 of that of the microcrystalline semiconductor film 53. In the thin film transistor to be formed, the source region and the drain region and the microcrystalline semiconductor film 53 The buffer layer formed between the microcrystalline semiconductor film 53 and the channel functions as a high resistance region. This functions as a thin film transistor formation region, which can reduce the off-current of the thin film transistor. When the thin film transistor is used as a switching element of a display device, The contrast can be improved.

[0187] A buffer layer 54 is formed on the microcrystalline semiconductor film 53 by plasma CVD at 300° C. to 4 The film is preferably formed at a temperature of 00° C. The hydrogen is removed from the microcrystalline semiconductor film 5 by this film formation process. 3, and the same effect as hydrogenating the microcrystalline semiconductor film 53 can be obtained. By depositing the buffer layer 54 on the microcrystalline semiconductor film 53, the microcrystalline semiconductor film 53 is The element can be diffused to terminate dangling bonds.

[0188] Next, after the buffer layer 54 is formed, the substrate is transported without being exposed to the atmosphere. The impurity that gives one conductivity type is deposited in a vacuum chamber different from the vacuum chamber in which 54 is deposited. It is preferable to form a doped semiconductor film 55. The cross section at this stage is shown in FIG. The buffer layer 54 is formed in a vacuum chamber different from the vacuum chamber in which the buffer layer 54 is formed. By forming a semiconductor film 55 to which an impurity for imparting a type is added, a uniform structure is formed during the film formation of the buffer layer. This can prevent impurities that impart a conductivity type from being mixed in.

[0189] The semiconductor film 55 to which an impurity that gives one conductivity type is added is an n-channel thin film transistor. When forming a silicon hydride, phosphorus can be added as a typical impurity element. Adding impurity gas such as PH3 is sufficient. Also, forming a p-channel thin film transistor In this case, boron can be added as a typical impurity element, and B2H The semiconductor film 5 to which an impurity that gives one conductivity type is added may be formed by adding an impurity gas such as 6. The semiconductor layer 5 can be formed of a microcrystalline semiconductor or an amorphous semiconductor. The semiconductor film 55 to which the impurity is added is formed to a thickness of 2 nm to 50 nm. The throughput can be improved by thinning the semiconductor film to which impurities that give the impurity are added. It can be done.

[0190] Next, as shown in FIG. 10(A), a semiconductor film 5 to which an impurity that imparts one conductivity type is added is formed. A resist mask 56 is formed on the SiO 2 film 5 by photolithography. Alternatively, the second photomask is used to form the conductive film. The resist coated on the semiconductor film 55 to which the impurity for imparting the electrostatic type is added is exposed and developed. Then, a resist mask 56 is formed.

[0191] Next, the microcrystalline semiconductor film 53, the buffer layer 54, and the conductive type The semiconductor film 55 to which the impurity that provides the conductivity is added is etched and separated, and the semiconductor film 55 is separated as shown in FIG. As shown in FIG. 1, the microcrystalline semiconductor film 61, the buffer layer 62, and the semiconductor layer 63 are doped with an impurity imparting one conductivity type. This forms a semiconductor film 63. After that, the resist mask 56 is removed.

[0192] The side surfaces of the microcrystalline semiconductor film 61 and the buffer layer 62 are inclined, so that the buffer layer The leakage current between the source region and the drain region formed on the microcrystalline semiconductor film 62 and the microcrystalline semiconductor film 61 is In addition, the source electrode and the drain electrode are micro-connected. Therefore, it is possible to prevent the occurrence of leakage current between the microcrystalline semiconductor film 61 and the microcrystalline semiconductor film 62. The inclination angle of the end side surfaces of the film 61 and the buffer layer 62 is 30° to 90°, preferably 45°. By setting the angle at this angle, the source electrode or drain electrode due to the step shape can be prevented from being damaged. This can prevent breakage of the inner electrode.

[0193] Next, as shown in FIG. 10(C), a semiconductor film 63 doped with an impurity that imparts one conductivity type is formed. Conductive films 65a to 65c are formed so as to cover the gate insulating film 52c. 65c is aluminum, copper, silicon, titanium, neodymium, scandium, molybdenum Aluminum alloys containing elements such as ribdenum to improve heat resistance or to prevent hillocks It is preferable that the layer is formed of a single layer or a laminated layer. The film in contact with the semiconductor film is made of titanium, tantalum, molybdenum, tungsten, or It is formed by nitrides of these elements, and aluminum or aluminum alloy is formed on it. Furthermore, the upper and lower surfaces of the aluminum or aluminum alloy may be laminated. sandwiched between titanium, tantalum, molybdenum, tungsten, or nitrides of these elements. Here, the conductive film is a laminated structure of three conductive films 65a to 65c. The conductive film 65a and 65c are made of molybdenum, and the conductive film 65b is made of aluminum. The conductive films 65a and 65c are made of titanium films, and the conductive film 65b is made of aluminum films. The conductive films 65a to 65c are formed by sputtering or It is formed by vacuum evaporation.

[0194] Next, as shown in FIG. 10(D), a third photomask is used to apply a mask to the conductive films 65a to 65c. A resist mask 66 is formed, and a part of the conductive films 65a to 65c is etched to form a pair of so The source and drain electrodes 71a to 71c are formed. As a result, the conductive films 65a to 65c are isotropically etched. Therefore, the source and drain electrodes having a smaller area than the resist mask 66 are selectively etched. Electrodes 71a to 71c can be formed.

[0195] Next, as shown in FIG. 11(A), a resist mask 66 is used to remove impurities that impart one conductivity type. The doped semiconductor film 63 is etched to form a pair of source and drain regions 72. Furthermore, in this etching step, a part of the buffer layer 62 is also etched. The buffer layer in which a recess (groove) is formed by etching is designated as buffer layer 73. The source and drain regions are formed in the same process as the recesses (grooves) in the buffer layer. The depth of the recess (groove) in the buffer layer can be set to the thickness of the buffer layer 73 at its thickest point. By making the area 1 / 2 to 1 / 3 of the area where the source and drain regions are located, the distance between the source and drain regions can be increased. Therefore, the leakage current between the source region and the drain region can be reduced. After that, the resist mask 66 is removed.

[0196] In particular, when exposed to plasma used in dry etching, the resist mask changes in quality and The buffer layer 73 is formed by 50° C. to prevent the layer from being completely removed in the etching removal process and leaving residues. The resist mask 66 is etched by etching a part of the conductive films 65a to 65c. and etching for forming the source and drain regions 72. In both cases, dry etching tends to leave residue, so it is necessary to The buffer layer 73 may be formed thick enough to be etched away completely. Furthermore, the buffer layer 73 is hardly damaged by plasma during dry etching. It is also possible to prevent the radiation from being applied to the crystalline semiconductor film 61 .

[0197] Next, as shown in FIG. 11(B), the source and drain electrodes 71a to 71c, the source The gate insulating film 5 is formed of a gate electrode 72, a drain region 72, a buffer layer 73, a microcrystalline semiconductor film 61, and a gate insulating film 5. An insulating film 76 is formed to cover the gate insulating films 52a, 52b, and 52c. The insulating film 76 can be formed by the same film forming method as that of the insulating film 76. It is used to prevent the intrusion of polluting impurities such as organic matter, metals, and water vapor, and a dense membrane is preferred. Furthermore, by using a silicon nitride film for the insulating film 76, the oxygen concentration in the buffer layer 73 can be reduced. 5×10 19 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 below It can be said that:

[0198] As shown in FIG. 11(B), the ends of the source and drain electrodes 71a to 71c and the source The ends of the source and drain regions 72 are not aligned but are offset, so that the source electrode and Since the distance between the ends of the drain electrodes 71a to 71c is large, In addition, the source electrode and the drain electrode 7 can be prevented from leaking current or shorting. The ends of the regions 1a to 71c and the ends of the source and drain regions 72 are not aligned but are shifted. Therefore, the source and drain electrodes 71a to 71c and the source and drain regions The electric field is not concentrated at the end of the gate electrode 51 and the source and drain electrodes 71a to 72. Therefore, it is possible to prevent leakage current between the transistor 71c and the transistor 71a. High-voltage thin film transistors can be fabricated.

[0199] Through the above steps, the thin film transistor 74 can be formed.

[0200] The thin film transistor shown in this embodiment mode has a gate insulating film and a microcrystalline semiconductor film over a gate electrode. a buffer layer, a source region and a drain region, a source electrode and a drain electrode, The surface of the microcrystalline semiconductor film which functions as a channel formation region is covered with a buffer layer. A recess (groove) is formed in a part of the power layer, and the area other than the recess is the source region and the drain region. That is, the recess formed in the buffer layer allows the source and drain regions to be covered. The distance between the source and drain regions is large, which reduces leakage current between the source and drain regions. Also, by etching a part of the buffer layer, a recess can be formed. To prevent this, etching residues generated in the process of forming the source and drain regions are removed. Therefore, leakage current (parasitic current) flows through the residue to the source and drain regions. This can prevent the occurrence of a channel.

[0201] In addition, the microcrystalline semiconductor film serving as a channel formation region and the source and drain regions A buffer layer is formed between the microcrystalline semiconductor film and the insulating film. The high resistance buffer layer is formed between the microcrystalline semiconductor film and the source and drain regions. Since the insulating layer extends to the gap between the thin film transistor and the insulating layer, it is possible to reduce the occurrence of leakage current in the thin film transistor. This makes it possible to reduce the deterioration caused by the application of high voltage. The layer, the microcrystalline semiconductor film, the source region, and the drain region are all areas overlapping with the gate electrode. Therefore, it can be said that the structure is not affected by the edge shape of the gate electrode. When the electrode has a laminated structure, if aluminum is used as the lower layer, the aluminum on the side of the gate electrode However, the source and drain regions are also exposed, which may result in hillocks. By configuring the gate electrode so that it does not overlap with the gate electrode edge, In addition, the surface of the microcrystalline semiconductor film can be prevented from being terminated by hydrogen. Since the amorphous semiconductor film is formed as a buffer layer, the oxidation of the microcrystalline semiconductor film is prevented. It is possible to prevent the generation of the oxide film during the formation of the source and drain regions. It is possible to prevent etching residues from being mixed into the microcrystalline semiconductor film. The thin film transistor has excellent properties and excellent withstand voltage.

[0202] Furthermore, the channel length of the thin film transistor can be shortened, and the planar surface of the thin film transistor can be reduced. The product can be reduced.

[0203] Next, a resist mask is formed on the insulating film 76 using a fourth photomask. A contact hole is formed by etching a part of 76, and A pixel electrode 77 is formed in contact with the source electrode or drain electrode 71c. 12C) corresponds to a cross-sectional view taken along the chain line AB in FIG.

[0204] As shown in FIG. 12, the ends of the source and drain regions 72 are connected to the source and drain electrodes. It can be seen that the edge of the buffer layer 73 is located outside the edge of the source electrode 71c. The source and drain electrodes 71c and the source and drain regions 72 are positioned outside the edge of the source and drain electrodes 71c and the In addition, one of the source electrode and the drain electrode is connected to the other of the source region and the drain region. The shape is a surrounding shape (specifically, U-shaped or C-shaped). Since the area can be increased, the amount of current can be increased. In addition, the area of ​​the transistor can be reduced. Since the source electrode and the drain electrode are overlapped, the influence of the unevenness of the gate electrode is small. It is possible to reduce the coverage rate and suppress the occurrence of leakage current. One of the drain electrodes also functions as a source wiring or a drain wiring.

[0205] The width of the side of the gate wiring that does not overlap with the microcrystalline semiconductor film is This is narrower than the width of the gate electrode side, which is connected to the pixel. In addition, the angle (taper angle) of the side surface of the gate electrode overlapping with the microcrystalline semiconductor film is This is smaller than the side of the gate wiring that does not overlap with the crystalline semiconductor film. This ensures good coating properties of the film that is formed.

[0206] The pixel electrode 77 is made of indium oxide containing tungsten oxide. Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium tin oxide, indium zinc oxide, indium with silicon oxide A light-transmitting conductive material such as indium tin oxide can be used.

[0207] The pixel electrode 77 is made of a conductive composition containing a conductive macromolecule (also called a conductive polymer). The pixel electrode 77 formed using a conductive composition can be formed by Resistance is 10,000Ω / □ or less, and light transmittance at a wavelength of 550nm is 70% or more. It is also preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm or less. It is preferable that:

[0208] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0209] Here, the pixel electrode 77 is formed by depositing an indium tin oxide film by sputtering. After that, a resist is applied onto the indium tin oxide film. The resist is exposed and developed to form a resist mask. The indium tin oxide film is then etched to form the pixel electrode 77 .

[0210] In this manner, an element substrate that can be used in a display device can be formed.

[0211] This embodiment is the same as embodiment 1, embodiment 2, embodiment 3, embodiment 4 or embodiment 5. It can be freely combined with form 5.

[0212] (Embodiment 7) In this embodiment, before the substrate is carried into the vacuum chamber, hydrogen or a rare gas is introduced to generate plasma. The generated gas (oxygen, nitrogen, and other atmospheric components, or After removing the etching gas used to clean the vacuum chamber, hydrogen and silane were This example shows the introduction of carbon dioxide gas and a small amount of phosphine (PH3) gas. Since only the process steps are different, only the different process steps will be explained in detail below with reference to FIG. In 15, the same parts as in the second embodiment are designated by the same reference numerals.

[0213] First, a gate electrode is formed on a substrate 350 using a multi-tone mask in the same manner as in the sixth embodiment. Here, a non-alkali glass substrate measuring 600 mm x 720 mm is used. Here, since this is an example of manufacturing a display device with a large display screen using a large-area substrate, The first conductive layer 351a is made of aluminum having low air resistance, and the second conductive layer 351a is made of aluminum having low air resistance. The gate electrode is formed by laminating a second conductive layer 351b made of molybdenum, which has a high heat resistance. The etching device used is an ECCP mode etching device shown in FIG.

[0214] Next, a gate insulating film 352 is formed on the second conductive layer 351b, which is the upper layer of the gate electrode. When used as a switching element in a liquid crystal display device, the gate insulating layer is used to drive the device by AC. The film 352 is preferably a single layer of silicon nitride film. 2) A single layer silicon nitride film (dielectric constant 7.0, thickness 300 nm) was deposited by plasma CVD. The cross-sectional view after the steps up to this point is shown in FIG. 15(A).

[0215] Next, after the gate insulating film is formed, the substrate is transported without being exposed to the atmosphere. The microcrystalline semiconductor film is formed in a vacuum chamber different from the vacuum chamber in which the first film is formed.

[0216] Before the substrate is loaded into the vacuum chamber of the film deposition equipment, hydrogen or a rare gas is introduced to generate a plasma. The gas (oxygen, nitrogen, and other atmospheric components, if any) attached to the inner wall of the vacuum chamber is generated. After removing the etching gas (used for cleaning the vacuum chamber), hydrogen and silicon Silane gas and a small amount of phosphine (PH3) gas are introduced. The trace amount of phosphine gas reacts with the oxygen and moisture in the film. Phosphorus can be contained in the microcrystalline semiconductor film.

[0217] Next, the substrate is carried into a vacuum chamber, and silane gas and After exposure to a small amount of phosphine gas, a microcrystalline semiconductor film is formed. Generally speaking, plasma is generated by diluting silicon hydrides such as SiH4 and Si2H6 with hydrogen. The film can be formed with a flow rate of more than 100 times but not more than 2000 times the flow rate of silane gas. Using hydrogen, a microcrystalline semiconductor film 353 containing phosphorus and hydrogen can be formed. By exposing the semiconductor substrate to the phosphine gas, crystal nucleation is promoted to form a microcrystalline semiconductor film 353. The microcrystalline semiconductor film 353 has a phosphorus concentration that increases with distance from the gate insulating film interface. The concentration profile shows a decreasing concentration as the concentration increases.

[0218] Next, the film formation conditions were changed in the same chamber, and the flow rate of silicon hydride was increased from 1 to 10 times, More preferably, hydrogen is used at a flow rate of 1 to 5 times, and the amorphous silicon containing hydrogen is The cross section after completing the steps up to this point corresponds to FIG. 15(C). do.

[0219] Next, after the buffer layer 54 is formed, the substrate is transported without being exposed to the atmosphere, and the microcrystalline semiconductor The vacuum chamber for forming the dielectric film 353 and the buffer layer 54 is different from the vacuum chamber for forming the dielectric film 353 and the buffer layer 54. A semiconductor film 55 is formed by adding impurities that impart a conductivity type. Since this step is the same as that in the sixth embodiment, a detailed description thereof will be omitted here.

[0220] This embodiment includes the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the It can be freely combined with embodiment 5 or embodiment 6.

[0221] (Embodiment 8) A manufacturing method of a thin film transistor different from that in Embodiment 2 will be described with reference to FIGS. 16 to 18. Here, the number of photomasks can be reduced compared to the sixth embodiment. The process for manufacturing a thin film transistor will be described.

[0222] As in FIG. 9(A) shown in the sixth embodiment, a conductive film is formed on a substrate 50, and a laser is applied to the conductive film. A resist is applied and formed by a photolithography process using a multi-tone mask. A part of the conductive film is etched using a mask to form a gate electrode 51. Although not shown, gate electrodes or gate wirings having side surfaces with different taper angles are formed as appropriate. Next, gate insulating films 52a, 52b, and 52c are formed in this order on the gate electrode 51. .

[0223] Next, a microcrystalline semiconductor film 53 is formed under the first film formation condition. 9C shown in the sixth embodiment. Next, in the same manner as in FIG. 9(D) shown in the sixth embodiment, the microcrystalline semiconductor film 5 A buffer layer 54 and a semiconductor film 55 doped with impurities that give one conductivity type are formed in this order on the substrate 3. Complete.

[0224] Next, conductive films 65a to 65c are formed on the semiconductor film 55 to which an impurity imparting one conductivity type is added. Next, as shown in FIG. 16(A), a resist 80 is applied onto the conductive film 65a. .

[0225] The resist 80 can be a positive resist or a negative resist. , shown using a positive resist.

[0226] Next, the resist 80 is irradiated with light using the multi-tone mask 59 as a second photomask. The resist 80 is exposed to light.

[0227] After exposure using a multi-tone mask, development is performed to obtain a film thickness of 100 μm as shown in FIG. 16(B). A resist mask 81 having different areas can be formed.

[0228] Next, the resist mask 81 is used as a mask to form the microcrystalline semiconductor film 53, the buffer layer 54, and the conductive layer 55. The semiconductor film 55 to which the impurity for imparting the conductivity type is added and the conductive films 65a to 65c are etched. As a result, as shown in FIG. 17(A), a microcrystalline semiconductor film 61, a buffer layer 62, a semiconductor film 63 to which an impurity that imparts one conductivity type is added, and conductive films 85a to 85c can be formed.

[0229] Next, the resist mask 81 is ashed. As a result, the area of ​​the resist is reduced and the thickness is At this time, the resist in the thin film region (which overlaps with a part of the gate electrode 51) The resist mask 86 is then removed to form a separate resist mask 86, as shown in FIG. 17(A). It is possible.

[0230] Next, the conductive films 85a to 85c are etched and separated using the resist mask 86. As a result, pairs of source and drain electrodes 92a to 92c are formed as shown in FIG. 17(B). The conductive films 85a to 85c are formed by wet etching using the resist mask 86. When etching is performed, the ends of the conductive films 85a to 85c are selectively etched. The source and drain electrodes 92a to 92c are formed with an area smaller than that of the resist mask 86. It can be achieved.

[0231] Next, using a resist mask 86, a semiconductor film doped with an impurity that gives one conductivity type is 63 is etched to form a pair of source and drain regions 88. In the etching process, a part of the buffer layer 62 is also etched. The buffer layer is referred to as a buffer layer 87. A recess is formed in the buffer layer 87. The source and drain regions are formed in the same process as the recess (groove) in the buffer layer. Here, a part of the buffer layer 87 is formed on the surface of the resist mask 81. The resist mask 86 has been partially etched away, so that the source and drain regions The buffer layer 87 is formed to protrude outside the region 88. After this, the resist mask 86 is removed. Also, the ends of the source and drain electrodes 92a to 92c and the source and drain regions are removed. The ends of the drain region 88 are not aligned but are offset, and the source and drain electrodes 92a to 92c are aligned. Outside the ends of 2c, the ends of the source and drain regions 88 are formed.

[0232] As shown in FIG. 17(C), the ends of the source and drain electrodes 92a to 92c and the source The ends of the source and drain regions 88 are not aligned but are offset, so that the source electrode and Since the distance between the ends of the drain electrodes 92a to 92c is large, In addition, the source electrode and the drain electrode 9 can be prevented from leaking current or shorting. The ends of the electrodes 2a to 92c and the ends of the source and drain regions 88 are not aligned but are shifted. Therefore, the source and drain electrodes 92a to 92c and the source and drain regions The electric field is not concentrated at the end of the gate electrode 51 and the source and drain electrodes 92a to 88. This can prevent leakage current between 92c and 92d.

[0233] By the above steps, the thin film transistor 83 can be formed. A thin film transistor can be formed using a photomask.

[0234] Next, as shown in FIG. 18(A), the source and drain electrodes 92a to 92c, the source The gate insulating film 5 is formed of a gate electrode 84 and a drain region 88, a buffer layer 87, a microcrystalline semiconductor film 90, and a gate insulating film 5. An insulating film 76 is formed on 2c.

[0235] Next, a resist mask formed using a third photomask is used to remove a portion of the insulating film 76. Then, a contact hole is formed by etching. A pixel electrode 77 is formed in contact with the source or drain electrode 71c. As for 77, an indium tin oxide film is formed by sputtering, and then indium A resist is applied onto the tin oxide film. Then, the resist is exposed using a fourth photomask. and developing to form a resist mask. The oxide film is etched to form pixel electrodes 77.

[0236] As a result, the number of masks can be reduced by using a multi-tone mask, and a device that can be used in a display device can be obtained. A daughter board can be formed.

[0237] This embodiment includes the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the It can be freely combined with embodiment 5, embodiment 6, or embodiment 7.

[0238] (Embodiment 9) In this embodiment, a process for forming a storage capacitor using a multi-tone mask and a process for forming a thin film transistor are performed. The process of forming contacts for pixel electrodes is shown in FIG. The same parts as in embodiment 6 are designated by the same reference numerals.

[0239] According to the sixth embodiment, after the process up to forming the insulating film 76 is completed, a multi-tone mask is used. A first interlayer insulating film 84a having openings of different depths is formed. As shown in FIG. 19(A), the angle of the side surface of the wiring is larger than the angle of the side surface of the gate electrode. By using a multi-tone mask to change the angle of the wiring side surface and control the wiring width for each location, The aperture ratio of the elemental portion is improved. The cross section at this stage is shown in Figure 19(A).

[0240] As shown in FIG. 19(A), an insulating film 76 is formed above the source or drain electrode 71c. A first opening exposing the surface and a laminate of a first conductive layer 78a and a second conductive layer 78b are formed. A second opening having a depth shallower than that of the first opening is provided on the capacitance wiring. The first conductive layer 78a and the second conductive layer 78b are respectively connected to the first conductive layer 51a of the gate electrode. The second conductive layer 51b is formed in the same process as the first conductive layer 51a.

[0241] Next, a portion of the insulating film 76 is selectively etched using the first interlayer insulating film 84a as a mask. This exposes a part of the source or drain electrode 71c.

[0242] Next, the first interlayer insulating film 84a is opened until the second opening is enlarged and the surface of the insulating film 76 is exposed. At the same time, the first opening is also enlarged, but the size of the opening formed in the insulating film 76 is does not change, a step is formed.

[0243] Next, the pixel electrode 77 is formed. The cross section at this stage corresponds to FIG. 19(C). By this process, the first interlayer insulating film is reduced to the second interlayer insulating film 84b. 5 uses an insulating film 76 and a gate insulating film 52 as a dielectric, and a capacitance wiring and a gate insulating film 52 as a pair of electrodes. A pixel electrode 77 is used.

[0244] In this way, the storage capacitor can be formed with a small number of steps using a multi-tone mask.

[0245] This embodiment includes the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the It can be freely combined with embodiment 5, embodiment 6, embodiment 7, or embodiment 8. Cut.

[0246] (Embodiment 10) In this embodiment mode, a display device including the thin film transistor described in Embodiment Mode 6 is used. The liquid crystal display device will be described below.

[0247] First, we will explain the VA (Vertical Alignment) type liquid crystal display device. VA type LCD devices are a type of LCD panel that controls the alignment of liquid crystal molecules. In VA type LCD devices, the liquid crystal molecules are aligned with the panel surface when no voltage is applied. In this embodiment, pixels are divided into several regions. The molecules are divided into sub-pixels (sub-pixels) and tilted in different directions. This is called multi-domain or multi-domain design. In the following explanation, multi-domain design A liquid crystal display device that takes into consideration the above will be described.

[0248] 21 and 22 show the pixel electrode and the counter electrode, respectively. 1 is a plan view of the substrate side on which the element electrodes are formed, and shows a cross-sectional structure corresponding to the cutting line AB shown in the figure. This is shown in FIG. 20. Also, FIG. 22 is a plan view of the substrate side on which the counter electrode is formed. The following description will refer to these figures.

[0249] FIG. 20 shows a configuration of a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor 630. The substrate 600 on which the counter electrode 640 and the like are formed is superimposed on the counter substrate 601. The figure shows the state after the liquid crystal is injected.

[0250] The opposing substrate 601 has a light-shielding film 632 and a first adhesive film 642 formed at a position where the spacer 642 is to be formed. A color film 634, a second color film 636, a third color film 638, and a counter electrode 640 are formed. This structure allows the heights of the protrusions 644 and spacers 642 to be different for controlling the alignment of the liquid crystal. An alignment film 648 is formed on the pixel electrode 624, and similarly, an alignment film 648 is formed on the counter electrode 640. An alignment film 646 is also formed on the first and second electrodes 642. A liquid crystal layer 650 is formed between them.

[0251] Although the spacers 642 are shown as columnar spacers here, bead spacers may also be scattered. Furthermore, the spacers 642 are formed on the pixel electrodes 624 formed on the substrate 600. Good too.

[0252] On the substrate 600, a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor 63 are provided. The pixel electrode 624 covers the TFT 628, the wiring, and the storage capacitor 630. A contact hole 62 penetrates the insulating film 620 and a third insulating film 622 covering the insulating film. 3, it is connected to the wiring 618. Also, using a multi-tone mask, the wiring 618 and the TFT 628 The source electrode or drain electrode of the wiring 618 is selectively etched, and the side angle of the wiring 618 is set to T The side angle of the source electrode or drain electrode of the FT628 is made larger than that of the FT628, which contributes to improving the aperture ratio. The thin film transistor described in Embodiment Mode 6 can be used as the TFT 628 as appropriate. The storage capacitor 630 can be connected to the gate wiring 60 of the TFT 628 according to the second embodiment. The first capacitor wiring 604, the gate insulating film 606, and the wiring The second capacitor wiring 617 is formed in the same manner as the first capacitor wiring 616 and the second capacitor wiring 617. The side angle of the wiring 604 is set larger than the side angle of the wirings 616 and 618 of the TFT 628. This contributes to improving the aperture ratio.

[0253] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a liquid crystal element. It is being done.

[0254] 21 shows the structure on the substrate 600. The pixel electrode 624 is made of the material shown in the sixth embodiment. The pixel electrode 624 is provided with a slit 625. The slit 625 is formed by This is to control the

[0255] The TFT 629 and the pixel electrode 626 and storage capacitor 631 connected thereto shown in FIG. The TFT 628, the pixel electrode 624, and the storage capacitor 630 can be formed in the same manner. Both TFT 628 and TFT 629 are connected to wiring 616. A pixel is composed of a pixel electrode 624 and a pixel electrode 626. 624 and pixel electrode 626 are sub-pixels.

[0256] 22 shows the structure on the opposing substrate side. An opposing electrode 640 is formed on a light-shielding film 632. The counter electrode 640 is preferably formed using the same material as the pixel electrode 624. On the counter electrode 640, a protrusion 644 for controlling the alignment of the liquid crystal is formed. A spacer 642 is formed in accordance with the position of 32.

[0257] The equivalent circuit of this pixel structure is shown in Figure 23. TFT628 and TFT629 are both gate The wiring 602 and the wiring 616 are connected. In this case, the first capacitance wiring 604 and the third capacitance wiring By making the potential of the wiring 605 different, the operation of the liquid crystal element 651 and the liquid crystal element 652 can be made different. That is, the potentials of the first capacitance wiring 604 and the third capacitance wiring 605 can be individually set. By controlling it separately, the orientation of the liquid crystal can be precisely controlled to widen the viewing angle.

[0258] When a voltage is applied to the pixel electrode 624 in which the slit 625 is provided, The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (oblique electric field). By arranging the 644 in an alternating interdigitated manner, a diagonal electric field is effectively generated, By controlling the orientation, the direction in which the liquid crystal is oriented varies depending on the location. The multi-domain technology widens the viewing angle of the LCD panel.

[0259] Although an example of a VA type liquid crystal display device has been described above, it is not particularly limited to the pixel electrode structure shown in FIG. It will not be done.

[0260] Next, the configuration of a TN type liquid crystal display device will be described.

[0261] 24 and 25 show the pixel structure of a TN type liquid crystal display device. The cross-sectional structure corresponding to the cutting line AB shown in the figure is shown in FIG. 24 and 25, the same parts as in FIG. 20 are uses the same sign.

[0262] The pixel electrode 624 is connected to the TFT 628 via the wiring 618 through the contact hole 623. The wiring 616, which functions as a data line, is connected to the TFT 628. Any of the TFTs shown in the second embodiment can be applied to 28.

[0263] The pixel electrode 624 is formed using the pixel electrode 77 shown in the second embodiment.

[0264] On the counter substrate 601, a light-shielding film 632, a second colored film 636, and a counter electrode 640 are formed. In addition, a flattening film 637 is formed between the second colored film 636 and the counter electrode 640. The liquid crystal layer 650 is disposed between the pixel electrode 624 and the counter electrode 640. It is formed.

[0265] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a liquid crystal element. It is being done.

[0266] In addition, the substrate 600 or the counter substrate 601 may have a color filter or a disclination. A shielding film (black matrix) or the like may be formed on the substrate 60 to prevent the A polarizing plate is attached to the surface opposite to the surface on which the thin film transistor of 0 is formed, and the opposing substrate A polarizing plate is attached to the surface of the plate 601 opposite to the surface on which the counter electrode 640 is formed. .

[0267] Through the above steps, a liquid crystal display device can be manufactured. The device uses thin film transistors with low off-state current, excellent electrical characteristics, and high reliability. Therefore, the liquid crystal display device has high contrast and high visibility. By adjusting the side angle of the wiring for each location, a liquid crystal display device with a high aperture ratio is realized. In addition, by using a multi-tone mask to adjust the side angle of the wiring for each location, the wiring end This reduces the risk of breaks or short circuits above the wire.

[0268] The present invention can also be applied to a liquid crystal display device of the in-plane switching type. This method applies an electric field horizontally to the liquid crystal molecules inside the display to drive the liquid crystal and express gradation. This method can widen the viewing angle to approximately 180 degrees.

[0269] This embodiment includes the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the It can be freely combined with embodiment 5, embodiment 6, embodiment 7, embodiment 8, or embodiment 9. It can be combined.

[0270] (Embodiment 11) A structure of a display panel, which is one mode of a liquid crystal display device of the present invention, will be described below.

[0271] In FIG. 26A, only a signal line driver circuit 6013 is formed separately and is formed on a substrate 6011. 6 shows a configuration of a display panel connected to a pixel portion 6012. The driver circuit 6014 is formed using a thin film transistor using a microcrystalline semiconductor film. A transistor that can achieve higher mobility than a thin-film transistor using a crystalline semiconductor film. By forming a driving circuit, it is possible to realize a signal line driving circuit which requires a driving frequency higher than that of the scanning line driving circuit. The signal line driver circuit 6013 is made of a single crystal semiconductor. Transistors using conductors, thin film transistors using polycrystalline semiconductors, or SOI The pixel portion 6012, the signal line driver circuit 6013, and the driving circuit 6014 may be the same. The power supply potential and various signals are transmitted to the scanning line driving circuit 6014 via the FPC 6015. are supplied.

[0272] The signal line driver circuit and the scanning line driver circuit may both be formed on the same substrate as the pixel portion. stomach.

[0273] In addition, when a driver circuit is formed separately, the substrate on which the driver circuit is formed is not necessarily the same as the substrate on which the pixel portion is formed. It is not necessary to attach it to the substrate on which it is formed, but it can be attached to, for example, an FPC. In FIG. 26B, only a signal line driver circuit 6023 is separately formed on a substrate 6021. The liquid crystal display panel connected to the formed pixel portion 6022 and the scanning line driver circuit 6024 The pixel portion 6022 and the scanning line driver circuit 6024 are formed using a microcrystalline semiconductor film. The signal line driver circuit 6023 is formed using a thin film transistor. The pixel portion 6022 and the signal line driver circuit 6023 are connected to each other. The scanning line driver circuit 6024 is connected to the power supply potential and various signals via the FPC 6025. and supplied.

[0274] In addition, only a part of a signal line driver circuit or a part of a scanning line driver circuit may be formed using a microcrystalline semiconductor film. The remaining thin film transistors are formed on the same substrate as the pixel section, and the remaining thin film transistors are formed separately. 26C shows an analog signal line driver circuit. The switch 6033a is connected to the same substrate 6031 as the pixel portion 6032 and the scanning line driver circuit 6034. The shift register 6033b of the signal line driver circuit is formed on a separate substrate. The pixel portion 6032 and the scanning line driver circuit are shown. The signal line driver circuit 6034 is formed using a thin film transistor using a microcrystalline semiconductor film. The shift register 6033b of the circuit is connected to the pixel section 6032 via the FPC 6035. The pixel portion 6032, the signal line driver circuit, and the scanning line driver circuit 6034 are The power supply potential, various signals, etc. are supplied via FPC6035.

[0275] As shown in FIG. 26, the liquid crystal display device has a part or all of the driving circuit on the same substrate as the pixel section. A thin film transistor using a microcrystalline semiconductor film can be formed over the plate.

[0276] The method for connecting the separately formed substrate is not particularly limited, and may be a known COG method. The method of connection may be a wire bonding method, a TAB method, or the like. The position is not limited to the position shown in FIG. 26, as long as electrical connection is possible. Alternatively, a controller, a CPU, a memory, etc. may be separately formed and connected.

[0277] Note that the signal line driver circuit used in this embodiment mode includes only a shift register and an analog switch. In addition to the shift register and analog switch, It may also have other circuits such as a bell shifter, a source follower, etc. The analog switch does not necessarily have to be provided. For example, a decoder can be used instead of a shift register. It is also possible to use another circuit that can select a signal line, such as a digital amplifier circuit, or to use an analog switch instead. Instead, a latch or the like may be used.

[0278] This embodiment includes the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the Embodiment 5, Embodiment 6, Embodiment 7, Embodiment 8, Embodiment 9 or Embodiment 10 can be freely combined.

[0279] (Embodiment 12) FIG. 27 shows the appearance and cross section of a liquid crystal display panel, which corresponds to one embodiment of the display device of the present invention. 27A shows a microcrystalline semiconductor film formed on a first substrate 4001. A thin film transistor 4010 and a liquid crystal element 4013 are disposed between the second substrate 4006 and the 27(B) is a top view of the panel sealed with the sealant 4005. A) corresponds to the cross-sectional view taken along line A-A'.

[0280] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. A sealing material 4005 is provided so as to cover the pixel portion 4002. A second substrate 4006 is provided on the circuit 4004. The scanning line driving circuit 4004 is a circuit board including a first substrate 4001, a sealing material 4005, and a second substrate 400. 6, the liquid crystal 4008 is sealed together with the sealant 4006 on the first substrate 4001. In a region different from the region surrounded by the material 4005, a polycrystalline silicon layer is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film is mounted. A signal line driver circuit having a thin film transistor using a polycrystalline semiconductor film is formed on the first substrate 40. 01, but a thin film transistor using a single crystal semiconductor is used. In FIG. 27, a signal line driving circuit 4 is formed on the substrate. 40. A thin film transistor 4009 formed of a polycrystalline semiconductor film included in the semiconductor device 003 is shown as an example.

[0281] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 27B, the thin film transistor included in the pixel portion 4002 is The thin film transistor 4010 is a microcrystalline semiconductor film. This corresponds to a thin film transistor using

[0282] The pixel electrode 4030 of the liquid crystal element 4013 is a thin film. The film transistor 4010 is electrically connected to the liquid crystal element 4041. The counter electrode 4031 of the pixel 4013 is formed on the second substrate 4006. The overlapping portion of the counter electrode 4031 and the liquid crystal 4008 corresponds to the liquid crystal element 4013. Correct.

[0283] The first substrate 4001 and the second substrate 4006 are made of glass, metal (typically Stainless steel, ceramics, and plastics can be used. is a FRP (Fiberglass-Reinforced Plastics) plate, P VF (polyvinyl fluoride) film, polyester film, or acrylic resin Also, aluminum foil can be used as a PVF film or polyester film. A sheet sandwiched between two polyester films can also be used.

[0284] Also, 4035 is a spherical spacer, which is located between the pixel electrode 4030 and the counter electrode 4031. The insulating film is selectively etched to control the distance (cell gap). Alternatively, a spacer obtained by bonding may be used.

[0285] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section Various signals and potentials given to 4002 are transmitted through wirings 4014 and 4015. Powered by FPC4018.

[0286] In this embodiment, the connection terminal 4016 is connected to the pixel electrode 4030 of the liquid crystal element 4013. The lead wirings 4014 and 4015 are formed from the same conductive film as the wiring 40. It is formed of the same conductive film as 41. As shown in the first embodiment, a multi-tone mask is used. As a result, the angle of the side surfaces of the lead wirings 4014 and 4015 is larger than that of the wiring 4041. It is effective to process both sides vertically to prevent short circuits between adjacent wiring. It is effective.

[0287] The connection terminal 4016 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0288] Although not shown, the liquid crystal display device shown in this embodiment has an alignment film and a polarizing plate. Furthermore, a color filter and a shielding film may be provided.

[0289] In addition, in FIG. 27, a signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001. However, this embodiment is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed and mounted. It may be formed separately and mounted.

[0290] This embodiment can be implemented in combination with the configurations described in other embodiments. be.

[0291] (Embodiment 13) The display device obtained by the present invention is used to manufacture an active matrix display module. That is, the present invention can be applied to all electronic devices that incorporate such a display unit. can.

[0292] Such electronic devices include cameras such as video cameras and digital cameras, head-mounted cameras, displays (goggle-type displays), car navigation systems, projectors, car Stereos, personal computers, personal digital assistants (mobile computers, mobile phones, etc.) Examples of such applications are shown in Figure 28.

[0293] FIG. 28(A) is a television device. The display module is as shown in FIG. The TV set can be completed by installing it in a housing. The display panel is also called a display module. 03 is formed, and other accessories include a speaker unit 2009 and an operation switch. In this way, the television device can be completed.

[0294] As shown in FIG. 28(A), a display panel 2002 using a display element is mounted on a housing 2001. The receiver 2005 can receive general television broadcasts, and the modem 2004 By connecting to a wired or wireless communication network via It can also be used for two-way (between sender and receiver, or between receivers) information communication. The television set can be operated using a switch built into the housing or a separate remote control. This can be done by the remote control device 2006, and the information to be output is also displayed on this remote control device. A display unit 2007 may also be provided.

[0295] In addition to the main screen 2003, the television device also has a sub-screen 2008 for second display. It may be formed of a panel and may have a configuration for displaying the channel, volume, etc. The main screen 2003 is formed by a liquid crystal display panel with a good viewing angle, and the sub-screen 2008 The display may be formed of a light-emitting display panel that can display with low power consumption. In order to achieve this, the main screen 2003 is formed of a light-emitting display panel, and the sub-screen is formed of a light-emitting display panel. The sub-screen may be configured to be able to blink.

[0296] Of course, the present invention is not limited to television devices, and may be applied to monitors of personal computers. In addition, large-area displays such as information display boards at train stations and airports, and advertising display boards on the street are also used. It can also be used as a display medium for a variety of purposes.

[0297] FIG. 28(B) shows an example of a mobile phone 2301. This mobile phone 2301 has a display The display unit 2302 includes an operation unit 2303. By applying the display device described in the above embodiment, mass productivity can be improved.

[0298] The portable computer shown in FIG. 28C includes a main body 2401, a display unit 2402, etc. By applying the display device described in the above embodiment to the display portion 2402, , and mass productivity can be improved. [Explanation of symbols]

[0299] 101: Circuit board 102: Gate insulating film 103: First conductive layer 106: Source and drain regions 107a: First wiring layer 107b: Second wiring layer 108: Source and drain regions 109: Source electrode or drain electrode 110: Source electrode or drain electrode 111: insulating film 112: pixel electrode 113: Connection electrode 116: First connection electrode 117: Second connection electrode 118: Pixel electrode 119: Third connection electrode

Claims

1. A display device including a transistor and a liquid crystal element electrically connected to one of a source electrode and a drain electrode of the transistor, a first conductive film that functions as a gate electrode of the transistor; a first insulating film having a region disposed above the first conductive film; a semiconductor film having a region disposed above the first insulating film and having a channel formation region of the transistor; a first layer having a region disposed above the semiconductor film and functioning as one of a source electrode and a drain electrode of the transistor; a second layer having a region disposed above the semiconductor film and functioning as the other of the source electrode and the drain electrode of the transistor; a second conductive film having a region in contact with an upper surface of the first layer and electrically connected to the semiconductor film via the first layer; a third conductive film having a region in contact with an upper surface of the second layer and electrically connected to the semiconductor film via the second layer; a second insulating film having a region disposed above the second conductive film, a region disposed above the third conductive film, and a region in contact with an upper surface of the first insulating film; a pixel electrode of the liquid crystal element, the pixel electrode having a region disposed above the second insulating film and electrically connected to the second conductive film; each of the second conductive film and the third conductive film is a single layer; the second conductive film has a first region overlapping with the first conductive film and a second region not overlapping with the first conductive film; a side surface of the second conductive film in the first region has a smaller taper angle than a side surface of the second conductive film in the second region; Display device.

2. A display device including a transistor and a liquid crystal element electrically connected to one of a source electrode and a drain electrode of the transistor, a first conductive film that functions as a gate electrode of the transistor; a first insulating film having a region disposed above the first conductive film; a semiconductor film having a region disposed above the first insulating film and having a channel formation region of the transistor; a first layer having a region in contact with a top surface of the semiconductor film and functioning as one of a source electrode and a drain electrode of the transistor; a second layer having a region in contact with a top surface of the semiconductor film and functioning as the other of the source electrode and the drain electrode of the transistor; a second conductive film having a region in contact with an upper surface of the first layer and electrically connected to the semiconductor film via the first layer; a third conductive film having a region in contact with an upper surface of the second layer and electrically connected to the semiconductor film via the second layer; a second insulating film having a region disposed above the second conductive film, a region disposed above the third conductive film, and a region in contact with an upper surface of the first insulating film; a pixel electrode of the liquid crystal element, the pixel electrode having a region disposed above the second insulating film and electrically connected to the second conductive film; each of the second conductive film and the third conductive film is a single layer; the second conductive film has a first region overlapping with the first conductive film and a second region not overlapping with the first conductive film; a side surface of the second conductive film in the first region has a smaller taper angle than a side surface of the second conductive film in the second region; Display device.

3. A display device including a transistor and a liquid crystal element electrically connected to one of a source electrode and a drain electrode of the transistor, a first conductive film that functions as a gate electrode of the transistor; a first insulating film having a region disposed above the first conductive film; a semiconductor film having a region disposed above the first insulating film and having a channel formation region of the transistor; a first layer having a region disposed above the semiconductor film and functioning as one of a source electrode and a drain electrode of the transistor; a second layer having a region disposed above the semiconductor film and functioning as the other of the source electrode and the drain electrode of the transistor; a second conductive film having a region in contact with an upper surface of the first layer and electrically connected to the semiconductor film via the first layer; a third conductive film having a region in contact with an upper surface of the second layer and electrically connected to the semiconductor film via the second layer; a second insulating film having a region disposed above the second conductive film, a region disposed above the third conductive film, and a region in contact with an upper surface of the first insulating film; a third insulating film having a region disposed above the second insulating film; a pixel electrode of the liquid crystal element, the pixel electrode having a region disposed above the third insulating film and electrically connected to the second conductive film via a contact hole disposed in the second insulating film and the third insulating film; each of the second conductive film and the third conductive film is a single layer; the second conductive film has a first region overlapping with the first conductive film and a second region not overlapping with the first conductive film; the contact hole has a region overlapping with the second region, a side surface of the second conductive film in the first region has a smaller taper angle than a side surface of the second conductive film in the second region; Display device.

4. A display device including a transistor and a liquid crystal element electrically connected to one of a source electrode and a drain electrode of the transistor, a first conductive film that functions as a gate electrode of the transistor; a first insulating film having a region disposed above the first conductive film; a semiconductor film having a region disposed above the first insulating film and having a channel formation region of the transistor; a first layer having a region in contact with a top surface of the semiconductor film and functioning as one of a source electrode and a drain electrode of the transistor; a second layer having a region in contact with a top surface of the semiconductor film and functioning as the other of the source electrode and the drain electrode of the transistor; a second conductive film having a region in contact with an upper surface of the first layer and electrically connected to the semiconductor film via the first layer; a third conductive film having a region in contact with an upper surface of the second layer and electrically connected to the semiconductor film via the second layer; a second insulating film having a region disposed above the second conductive film, a region disposed above the third conductive film, and a region in contact with an upper surface of the first insulating film; a third insulating film having a region disposed above the second insulating film; a pixel electrode of the liquid crystal element, the pixel electrode having a region disposed above the third insulating film and electrically connected to the second conductive film via a contact hole disposed in the second insulating film and the third insulating film; each of the second conductive film and the third conductive film is a single layer; the second conductive film has a first region overlapping with the first conductive film and a second region not overlapping with the first conductive film; the contact hole has a region overlapping with the second region, a side surface of the second conductive film in the first region has a smaller taper angle than a side surface of the second conductive film in the second region; Display device.

5. In any one of claims 1 to 4, the second conductive film contains copper or aluminum; Display device.

Images