Computer-readable recording medium, conversion method, and conversion apparatus

Abstract

To provide a conversion program, a conversion method and a conversion device for improving processing capability.SOLUTION: Acquiring a mapping result including a predetermined DFG and information on assignment of operations to respective computing units and wiring between the computing units determined so as to correspond to the predetermined DFG for a CGRA having a plurality of computing units, and extracting a portion corresponding to a predetermined DFG pattern from the predetermined DFG; A computer is made to execute processing for determining a conversion candidate DFG from among DFGs corresponding to a pattern of an extraction place on the basis of a position to which the extraction place in a mapping result is assigned and the number of transmission paths of data to be used between arithmetic units, and generating a converted DFG by converting a predetermined DFG on the basis of the conversion candidate DFG.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a conversion program, a conversion method, and a conversion device. [Background technology]

[0002] In recent years, Coarse-Grained Reconfigurable Architectures (CGRAs) have been attracting attention as a type of data processing device that offers excellent computational performance and energy efficiency in data processing. CGRA is a processor technology with a structure in which processing elements called PEs (Processing Elements), each equipped with an arithmetic unit and registers, are arranged in a two-dimensional array. CGRAs can reconfigure the calculations performed by the PEs and the data transfer paths between PEs during operation. A processor with PEs arranged in a two-dimensional array is sometimes called a CGRA.

[0003] A program is executed using a CGRA as follows: The program to be executed is converted into a DFG (Data Flow Graph) using a compiler. The DFG contains nodes that indicate operations and directed edges that indicate data dependencies between operations. A directed edge indicates that output data from a source node is used as input data for a destination node. Next, based on the DFG, the operations to be performed by each PE and the data wiring between PEs are determined according to the configuration of each PE in the CGRA. This determination of the operations and the data wiring between PEs is called mapping. After that, data is input to the CGRA after mapping is complete, and the CGRA performs operations using the input data.

[0004] As a mapping technique, a technique has been proposed in which grid points obtained by spatially dividing a field described by a governing equation are assigned to each element processor, and the element processors are operated asynchronously and independently to solve partial differential equations. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 08-087475 Summary of the Invention [Problem to be solved by the invention]

[0006] However, some DFGs perform mapping that results in inefficient PE utilization, making it difficult to increase the number of computations using CGRAs and improving processing power. For example, when sending more data than can be transmitted between PEs, some PEs are used to pass data without performing calculations, reducing the number of PEs used for calculations.

[0007] Furthermore, when data flow is limited to one direction, it is preferable to map with as few columns as possible, since reducing the number of columns in one direction to be mapped makes it easier to expand by combining them and is expected to improve throughput. However, depending on the DFG, the number of columns in one direction may be large, making it difficult to achieve expansion by combining them and improving processing power.

[0008] The disclosed technology has been made in view of the above, and aims to provide a conversion program, a conversion method, and a conversion device that improve processing performance. [Means for solving the problem]

[0009] In one aspect of the conversion program, conversion method, and conversion device disclosed in the present application, a computer is caused to execute a process of obtaining a predetermined DFG and a mapping result including information on the allocation of operations to each arithmetic unit determined to correspond to the predetermined DFG for a CGRA having multiple arithmetic units and information on the wiring between the arithmetic units, extracting a portion corresponding to a predetermined DFG pattern from the predetermined DFG, determining a conversion candidate DFG from among the DFGs corresponding to the pattern of the extracted portion based on the position to which the extracted portion is assigned in the mapping result and the number of data transmission paths used between the arithmetic units, and converting the predetermined DFG based on the conversion candidate DFG to generate a converted DFG. [Effects of the Invention]

[0010] In one aspect, the present invention can improve processing performance. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram of an automatic mapping system according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating information on the architecture of a CGRA according to an embodiment. [Figure 3] FIG. 3 is a block diagram of a DFG conversion device. [Figure 4] FIG. 4 is a diagram showing a first pattern of a DFG that is a conversion candidate. [Figure 5] FIG. 5 is a diagram showing a DFG after conversion of the DFG of the first pattern. [Figure 6] FIG. 6 is a diagram showing an example of conversion of a DFG including a DFG of the first pattern. [Figure 7] FIG. 7 is a diagram showing a second pattern of a DFG that is a conversion candidate. [Figure 8] FIG. 8 is a diagram showing a DFG after conversion of the DFG of the second pattern. [Figure 9] FIG. 9 is a diagram showing an example of a DFG including a DFG of the second pattern. [Figure 10]FIG. 10 is a diagram showing an example of a converted DFG including a DFG of the second pattern. [Figure 11] FIG. 11 is a diagram showing a third pattern of DFG that is a conversion candidate. [Figure 12] FIG. 12 is a diagram showing a DFG after conversion of the DFG of the third pattern. [Figure 13] FIG. 13 is a diagram showing an application example of the DFG transformation. [Figure 14] FIG. 14 is a flowchart of the process of generating DFG conversion candidates. [Figure 15] FIG. 15 is a flowchart of the process of extracting the DFG portion of the first pattern. [Figure 16] FIG. 16 is a flowchart of the process of extracting the DFG portion of the second pattern. [Figure 17] FIG. 17 is a flowchart of the process of extracting the DFG portion of the third pattern. [Figure 18] FIG. 18 is a flowchart of the DFG candidate determination process and the converted DFG generation process. [Figure 19] FIG. 19 is a flowchart of the conversion process of the first pattern DFG. [Figure 20] FIG. 20 is a flowchart of the conversion process of the second pattern DFG. [Figure 21] FIG. 21 is a flowchart of the conversion process of the third pattern of DFG. [Figure 22] FIG. 22 is a hardware configuration diagram of the DFG conversion device. DETAILED DESCRIPTION OF THE INVENTION

[0012] The following describes in detail embodiments of the conversion program, conversion method, and conversion device disclosed herein with reference to the accompanying drawings. Note that the conversion program, conversion method, and conversion device disclosed herein are not limited to the following embodiments. [Example]

[0013] 1 is a block diagram of an automatic mapping system according to an embodiment. The automatic mapping system 4 according to this embodiment includes an automatic mapper 1, a user terminal device 2, and an information processing device 3. The automatic mapper 1 is connected to the user terminal device 2 and the information processing device 3.

[0014] The information processing device 3 is a computer equipped with a CGRA. The information processing device 3 executes processing suited to a specific application by mapping a DFG (Data Flow Graph) designed for that specific application onto the CGRA. The CGRA has multiple PEs, which are computing units. The PEs are arranged in a two-dimensional array.

[0015] Users design DFGs to run CGRAs. A DFG is a diagram showing the data flow and operations performed in a system that performs computations. Here, the object performed by the DFG as a whole is called a "computation," and that "computation" contains multiple "operations." Also, a portion of a DFG included in another DFG may be called a "partial DFG."

[0016] The user terminal device 2 is a terminal device of a user who uses an information processing device 3 equipped with a CGRA. The user terminal device 2 transmits a DFG specified by the user to the automatic mapper 1, which then performs mapping to the CGRA equipped in the information processing device 3.

[0017] The automatic mapper 1 maps a DFG provided by a user to a CGRA. Mapping is a process of assigning operations defined in the DFG to one of the PEs in the CGRA, determining the connections between PEs so that each operation is performed according to the data flow defined in the DFG, and configuring the CGRA so that the calculation of the DFG can be executed. As shown in Figure 1, the automatic mapper 1 has a mapping device 11 and a DFG conversion device 10.

[0018] The mapping device 11 has in advance information about the architecture of the CGRA installed in the information processing device 3. The information about the CGRA architecture includes the number of PEs held by the CGRA, the number of wires between the PEs, connection information, etc. The mapping device 11 acquires the DFG transmitted from the user terminal device 2.

[0019] The mapping device 11 then maps the acquired DFG to the CGRA installed in the information processing device 3 according to a predetermined optimization algorithm. The mapping result is then output to the DFG conversion device 10 together with the DFG provided by the user. The mapping result is information indicating the allocation of operations to each PE, which is a plurality of arithmetic units determined to correspond to the DFG, and the wiring between the PEs.

[0020] Then, the mapping device 11 receives an input of a transformed DFG from the DFG transformation device 10, which is a DFG provided by a user that is transformed so as to reduce the data transmission sequence based on the output mapping result. Then, the mapping device 11 re-executes mapping using the transformed DFG. Then, the mapping device 11 outputs the mapping result to the information processing device 3, and causes the information processing device 3 to execute actual mapping for the CGRA in accordance with the mapping result.

[0021] The DFG conversion device 10 receives the mapping result and the DFG provided by the user from the mapping device 11. The DFG provided by the user is an example of a "predetermined DFG." The DFG conversion device 10 also has information about the architecture of the CGRA installed in the information processing device 3 in advance.

[0022] Then, the DFG conversion device 10 generates a DFG conversion candidate for reducing the data transmission sequence of the given DFG using information on the DFG, the mapping result, and the CGRA architecture. The DFG conversion candidate is a partial DFG of the given DFG, which, when converted into another configuration, enables mapping that reduces the data transmission sequence more than the mapping result.

[0023] Here, we will explain the data transmission sequence. Figure 2 is a diagram showing information on the architecture of a CGRA according to an embodiment. Here, the vertical direction on the paper surface of Figure 2 is called a column, and the horizontal direction is called a row. The explanation will be made using the up, down, left, and right directions on the paper surface.

[0024] 2 illustrates 16 PEs 100 arranged in 4 rows and 4 columns, which are part of the CGRA 110. In FIG. 2, the connection of the right-most PE 100 to the PE 100 to the right thereof and the connection of the left-most PE 100 from the PE 100 to the left thereof are omitted. Also, in FIG. 2, the connection of the bottom-most PE 100 to the PE 100 below it and the connection of the top-most PE 100 from the PE 100 above it are omitted.

[0025] The PEs 100 form a two-dimensional array with the column direction and row direction as two dimensions. Each PE 100 is connected to the PE 100 directly below it in the column direction by three wires. Furthermore, each PE 100 is connected to each PE 100 in the adjacent column in the row below. However, one of the wires connected to the PE 100 directly below and the wires connected to the PEs 100 to the lower left and right are wires that output a single value. That is, each PE 100 can output the same data to the PE 100 directly below, to the lower left, or to the lower right, or any combination thereof, using that wire. In other words, the PEs 100 other than those at the rightmost, leftmost, and bottommost ends of the CGRA 110 can simultaneously output a maximum of three types of output values.

[0026] While FIG. 2 shows only a portion of the CGRA 110, the input of the PE 100 at the top of the entire CGRA 110 is connected to an input node that inputs data. The PE 100 at the right end of the entire CGRA 110 has no connection from the PE 100 at the top right, and the PE 100 at the left end has no connection from the PE 100 at the top left. The PE 100 at the bottom of the entire CGRA 110 is not connected to any other PE 100 and outputs calculation result data. Thus, all PEs 100 except for the PEs 100 at the ends have input ports that receive five different input values ​​and output three different output values.

[0027] Between the PEs 100 according to this embodiment, data flows in one direction along the columns. That is, in FIG. 2, data flows from top to bottom along the columns. At this time, data can move freely along the rows. In FIG. 2, data can flow from any PE 100 to the PE 100 directly below, the PE 100 to the lower right, or the PE 100 to the lower left.

[0028] Here, a path for sending one piece of data among the PEs 100 arranged in the column direction shown in Figure 2 corresponds to a data transmission column. That is, in Figure 2, the PEs 100 arranged in the column direction have three data transmission columns. Reducing the data transmission columns means reducing the number of data transmission paths in the column direction used to transmit data at a certain timing. In the following explanation, the arrangement of PEs 100 in the direction in which data flows is called a column, and the dimension other than the column in the two-dimensional array is called a row.

[0029] Continuing the explanation, returning to Figure 1, the DFG conversion device 10 selects an application DFG to be used for conversion from the generated DFG conversion candidates, and converts the given DFG with the selected application DFG to generate a converted DFG. The DFG conversion device 10 then transmits the generated converted DFG to the mapping device 11 and instructs the mapping device 11 to perform mapping using the transmitted converted DFG.

[0030] The following describes the details of the DFG conversion device 10. Fig. 3 is a block diagram of the DFG conversion device 10. As shown in Fig. 3, the DFG conversion device 10 includes a data collection unit 101, an extraction unit 102, a candidate determination unit 103, a DFG conversion unit 104, and a notification unit 105.

[0031] The data collection unit 101 receives the mapping result and the DFG provided by the user as input from the mapping device 11. Then, the data collection unit 101 outputs the mapping result and the DFG provided by the user to the extraction unit .

[0032] The extraction unit 102 receives the mapping result and the DFG input provided by the user from the data collection unit 101. The extraction unit 102 has a plurality of types of DFG patterns that are conversion candidates in advance. In this embodiment, the extraction unit 102 has three types of patterns.

[0033] Here, three patterns of DFGs that can be conversion candidate DFGs will be explained. Fig. 4 is a diagram showing a first pattern of DFGs that are conversion candidates. Fig. 4 shows a DFG 201 of the first pattern and a mapping result 202 of the DFG 201.

[0034] Here, in the DFG 201, a circle represents one node. Furthermore, a square with rounded corners represents a partial DFG included in the DFG 201. A partial DFG may be one node, or may include multiple nodes and edges connecting them. Because the mapping for a partial DFG is not subject to change, a partial DFG can also be considered as one node. One of the PEs 100 is assigned to each node by mapping. Furthermore, symbols shown near the connection paths between nodes are output values ​​from the connection source and indicate values ​​input to the connection destination.

[0035] For example, DFG201 has node 211, node 212, partial DFG213, partial DFG214, and node 215. Node 211 outputs s as an output value of the operation result to partial DFGs 213 and 214. Partial DFG213 executes an operation of function f1(s, c1) using s, which is the output value from node 211. Partial DFG214 executes an operation of function f1(s, c2) using s, which is the output value from node 211. Here, c1 is a constant and is a value held by partial DFG213. Also, c2 is a constant and is a value held by partial DFG214. In other words, partial DFG213 and partial DFG214 execute the operation of the same function f1 except for the constants used as arguments.

[0036] Partial DFG 213 outputs q to node 215 as an output value based on the operation result. Furthermore, partial DFG 214 outputs r as an output value based on the operation result. Furthermore, node 212 outputs p to node 215 as an output value. Node 215 uses p, which is the output value of node 212, as a branching condition, and if p satisfies a predetermined condition, node 215 takes q, which is the output value of partial DFG 213, as the operation result. Furthermore, if p, which is the output value of node 212, does not satisfy the predetermined condition, node 215 takes r, which is the output value of partial DFG 214, as the operation result. The operation performed by node 215 is called predication. Node 215 outputs t as an output value based on the operation result.

[0037] DFG201 is mapped as shown in mapping result 202. Mapping result 202 uses five PEs 100, PE121 to PE125. In this case, node 211 is assigned to PE121, node 212 is assigned to PE122, partial DFG 213 is assigned to PE123, partial DFG 214 is assigned to PE124, and node 215 is assigned to PE125. In mapping result 202, the same data is sent using lines of the same line type as the line type indicating the data flow used in DFG201. Furthermore, gray lines are paths through which any data can pass. That is, in the case of mapping result 202, a maximum of three data transmission sequences are used simultaneously.

[0038] FIG. 5 is a diagram showing a DFG after transformation obtained by transforming the DFG of the first pattern. DFG 201 can be replaced with DFG 203. Node 216 executes an operation in which the values ​​of then and else in the predication of node 215 are replaced with c1 and c2, which are constants used by partial DFGs 213 and 214. The output value of node 212 is input to node 216. Furthermore, partial DFG 217 executes an operation in which the constants in the operations executed by partial DFGs 213 and 214 have been changed to variables. Partial DFG 217 uses the output value of node 211 and the output value of node 216 as arguments. In this case, partial DFG 217 uses the output value of node 216 instead of the constants in the operations executed by partial DFGs 213 and 214.

[0039] In general, the conditions for a DFG to be a first pattern are as follows: There is a node that executes a predication, and the node that outputs the output value used as an argument in each of the partial DFGs that calculate the value for the then case and the value for the else case in that predication is the same node. Furthermore, the operations performed by each partial DFG are identical except for the constant part. That is, if node 211 in DFG 201 is the first node, node 212 is the second node, partial DFG 213 is the third node, partial DFG 214 is the fourth node, and node 215 is the fifth node, then the first pattern can be expressed as follows: The first pattern has the first node and the second node. Furthermore, the first pattern is an operation of a first function using two arguments, and has the third and fourth nodes that execute an operation in which one of the two arguments is a fixed value and use the output value from the first node for the other of the two arguments. This first function corresponds to function f1 on which the partial DFGs 213 and 214 perform the operations described above. Furthermore, the first pattern has a fifth node that uses the output value of the second node as a determination condition and sets either the output value of the third node or the output value of the fourth node as an output value according to the determination result.

[0040] A DFG of the first pattern that satisfies the above conditions can be transformed as follows. The values ​​for the then and else cases of the node that executes the predication are set to the constants used in the operations of the two partial DFGs of the first pattern. The input to the node that executes the predication is set to the same input as in the partial DFG of the first pattern. Furthermore, one of the two partial DFGs is deleted, and the constant in the operation of the remaining partial DFG is replaced with a variable that takes the output value from the node that executes the predication as an argument. Furthermore, the arguments in that partial DFG are set to the output value of the node that the partial DFG takes as an argument in the DFG of the first pattern and the output value from the node that executes the predication. This transformation is equivalent to transforming "if p f1(x,c1) else f1(x,c2)" to "f1(x, if p then c1 else c2)".

[0041] When this conversion is performed, for example, the converted DFG 203 is mapped as shown in mapping result 204. For mapping result 204, four PEs 100, PE121 to PE124, are used. In this case, node 211 is assigned to PE121, node 212 is assigned to PE122, node 216 is assigned to PE123, and partial DFG 217 is assigned to PE124. In mapping result 204, the same data is sent using lines of the same line type as the line type indicating the data flow used in DFG 203. Furthermore, gray lines are paths through which any data can pass. That is, for mapping result 204, a maximum of two data transmission streams are used simultaneously.

[0042] The mapping result 204 can reduce the number of data transmission streams by one compared to the mapping result 204 in Fig. 4. In other words, data of another DFG can be transmitted in the reduced one data transmission stream, thereby improving the utilization efficiency of the PE 100 as a whole.

[0043] Here, the effect of reducing the data transmission sequence by converting the DFG of the first pattern will be described in detail. Fig. 6 is a diagram showing an example of converting a DFG including the DFG of the first pattern.

[0044] For example, the case of converting DFG221 shown in Fig. 6 will be described. DFG221 is a DFG in which node 218 that executes the operation s*t using s, which is the output value of node 211, and t, which is the output value of DFG201, as arguments is added to DFG201, which is the first pattern DFG shown in Fig. 4.

[0045] The DFG 221 is mapped as shown in the mapping result 222. In the mapping result 222, eight PEs 100, namely, PEs 121 to 125 and 131 to 134, are used. In the mapping result 222, three output values ​​are used in the calculation of the PE 124. Furthermore, the PE 125 performs calculations using s, which is the output value of the node 211, as an argument. In this case, a total of four data are held at the start of the calculation of the PE 124. Therefore, when data is input to the PE 124, one data transmission sequence is added to the three types of data transmission sequences that the PE 124 can transmit. As a result, two PE 100 sequences, namely, the sequence of PEs 121 to 125 and the sequence of PEs 131 to 134, are used.

[0046] Therefore, DFG223 is generated by converting the DFG of the first pattern of DFG221. DFG223 is mapped as shown in mapping result 224. In mapping result 224, four PEs 100, PE121 to PE124, are used. In the converted DFG of the first pattern, a maximum of two data transmission sequences are used simultaneously, and one of the three data transmission sequences connecting PE121 to PE124 is left over. Therefore, data used in the calculation of node 218 can be transmitted to PE125 using this left over data transmission sequence. As a result, as shown in mapping result 224, the mapping target can be limited to PE121 to PE124, which is the sequence of one PE100. In this case, the PE100 sequences of PE131 to PE134 that were to be used in the mapping of the original DFG221 can be freely used in the mapping of another DFG.

[0047] 7 is a diagram showing a second pattern of a DFG that is a conversion candidate, and shows a DFG 205 of the second pattern and a mapping result 206 of the DFG 205.

[0048] For example, DFG205 has node 251, node 252, partial DFG253, partial DFG254, and node 255. Node 251 outputs u to node 252 and partial DFG253 as an output value of the operation result. Node 251 also outputs the output value to partial DFG254. Node 252 executes the operation of function f2(u,u) using the same variable as two arguments, using u, which is the output value from node 211, and outputs v to node 255 as an output value based on the operation result. Here, f2(x,y) satisfies the associative law expressed as f2(f2(x,y),z)=f2(x,f2(y,z)). For example, f2(x,y) is x×y, x+y, x&y, etc.

[0049] Furthermore, partial DFG 253 executes an operation g1(u) using u, which is an output value from node 251, and outputs w as an output value based on the operation result to node 255. Node 255 executes an operation f2(v, w), which is the same as the operation executed by node 211 but uses two different variables as arguments. Partial DFG 254 executes a predetermined operation using the output value from node 211.

[0050] DFG 205 is mapped as shown in mapping result 206. Here, mapping is performed so that the operation of partial DFG 254 is executed last. Mapping result 206 uses five PEs 100, PEs 121 to 125. In this case, node 251 is assigned to PE 121, node 252 is assigned to PE 122, partial DFG 253 is assigned to PE 123, node 255 is assigned to PE 124, and partial DFG 254 is assigned to PE 125. Partial DFG 254 is mapped to PE 125 and subsequent PEs with the same pattern.

[0051] In the mapping result 206, the same data is sent using lines of the same type as the lines used to indicate the data flow in the DFG 205. The gray lines are paths through which any data can pass. That is, in the case of the mapping result 206, the number of data transmission sequences used is the maximum between PE123 and PE124, and three data transmission sequences are used simultaneously.

[0052] FIG. 8 is a diagram showing a DFG after transformation obtained by transforming the DFG of the second pattern. DFG 205 can be replaced with DFG 207. Like DFG 205, partial DFGs 253 and 254 receive the output value of node 251 as input. Partial DFG 253 executes the same operation g1(u) as partial DFG 253, and outputs w as an output value based on the operation result. Node 256 executes the operation of function f2(u, w) using u, which is the output value of node 251, and w, which is the output value of partial DFG 253, and outputs k as an output value based on the operation result. Node 257 executes the operation of function f2(k, u) using u, which is the output value of node 251, and k, which is the output value of node 256.

[0053] In general, the conditions for a DFG to conform to the second pattern are as follows: There exists a node that executes the operation f2(x,y) that satisfies the associative law using the output value of the start node as an argument, and the two variables used in the operation at the node that executes the operation f2(x,y) both take the output value of a specific node as an argument. In other words, the node that executes the operation f2(x,y) executes the operation f2(x,x). The operation result of the node that executes the operation f2(x,y) becomes an argument of another node that executes the same operation f2(x,y). Furthermore, the other node that executes the operation f2(x,y) uses the output value of the first partial DFG that executes the operation using the output value of the start node as an argument as another argument. The output value of the start node is input to a second partial DFG that is different from the first partial DFG.

[0054] That is, if node 251 in DFG205 is the first node, node 252 is the second node, partial DFG253 is the third node, partial DFG254 is the fourth node, and node 255 is the fifth node, then the second pattern can be expressed as follows: The second pattern has the first node. The second pattern also has a second node that executes an operation of a second function that satisfies the associative law using two arguments, using the output values ​​from the first node as two arguments. The second pattern also has a third node that executes an operation using the output value of the first node as an argument. The second pattern also has a fourth node that executes an operation of the second function using the output value from the second node and the output value from the third node as two arguments. The second pattern also has a fifth node that receives an input of the output value of the first node.

[0055] The DFG of the second pattern that satisfies the above conditions can be transformed as follows: Delete the two nodes that perform the operation f2(x,y). Add a first additional node that performs the operation f(x,y) using the first partial DFG and the output value of the start node as arguments. Then, add a second additional node that performs the operation f(x,y) using the output value of the first additional node and the output value of the start node. This transformation is equivalent to transforming "f2(f2(x,x),g(x))" to "f2(x,f2(x,g(x)))". Furthermore, if f2(x,y) is commutative, the same transformation is possible when the expression to be transformed is "f2(g(x),f2(x,x))".

[0056] When this conversion is performed, for example, the converted DFG 207 is mapped as shown in mapping result 208. For mapping result 208, five PEs 100, PE121 to PE125, are used. In this case, node 251 is assigned to PE121, partial DFG 253 is assigned to PE122, node 256 is assigned to PE123, node 257 is assigned to PE124, and nodes after node 257 are assigned to PE125. In FIG. 8, nodes after node 257 are not shown, so the nodes assigned to PE125 are not directly shown. Furthermore, partial DFG 254 is mapped to PE125 and subsequent PEs, which are given the same pattern. In mapping result 208, the same data is sent using lines of the same line type as the line type indicating the data flow used in DFG 207. Furthermore, gray lines are paths through which any data can pass. That is, in the case of mapping result 208, two data transmission sequences are used.

[0057] The mapping result 208 can reduce the number of data transmission streams by one compared to the mapping result 206 in Fig. 7. In other words, data of another DFG can be transmitted in the reduced one data transmission stream, thereby improving the utilization efficiency of the PE 100 as a whole.

[0058] Here, the effect of reducing the data transmission sequence by converting the DFG of the second pattern will be explained in detail. Fig. 9 is a diagram showing an example of a DFG including the DFG of the second pattern. Fig. 10 is a diagram showing an example of a converted DFG including the DFG of the second pattern.

[0059] For example, the following describes the case where DFG291 shown in Fig. 9 is converted. DFG291 is a DFG in which node 258 that executes an operation h(i, j) using j, which is the output value of DFG205, as an argument and i as the other argument, is added to DFG205, which is the second pattern DFG shown in Fig. 7.

[0060] The DFG 291 is mapped as shown in the mapping result 292. Here too, the mapping is performed so that the operation of the partial DFG 254 is executed last. In the mapping result 292, 12 PEs 100, namely PEs 121 to 126 and 131 to 136, are used. The partial DFG 254 is mapped to PEs 126 and onwards, which are given the same pattern.

[0061] In the mapping result 292, three different output values ​​are transmitted between PE123 and PE124 for the data transmission of the second pattern DFG. Therefore, in order to transmit data used in the calculation of node 258 to PE125, one more data transmission sequence is added to the three types of data transmission sequences that PE124 can transmit. As a result, two sequences of PE100 are used: a sequence of PE121 to PE126 and a sequence of PE131 to PE136.

[0062] Therefore, by converting the DFG of the second pattern of DFG 291, DFG 293 in Fig. 10 is generated. DFG 293 is mapped as in mapping result 294. In mapping result 294, PEs 121 to 126, which are six PEs 100, are used. Partial DFG 254 is mapped to PE 126 and onwards, which are given the same pattern.

[0063] Since the converted second pattern DFG has a maximum of two data transmission sequences, one of the three data transmission sequences connecting PE121 to PE125 is left over. Therefore, this left over data transmission sequence can be used to transmit data to be input to PE125, which executes the operation of node 258. As a result, as shown in mapping result 294, the mapping target can be limited to PE121 to PE126, which is the sequence of one PE100. In this case, the PE100 sequence of PE131 to PE136 that was to be used in the mapping of the original DFG 291 can be freely used in the mapping of other DFGs.

[0064] Fig. 11 is a diagram showing a third pattern of DFGs that are candidates for conversion, which shows a DFG 301 of the third pattern and a mapping result 302 of the DFG 301.

[0065] For example, DFG301 has node 311, node 312, partial DFG313, partial DFG314, partial DFG315, partial DFG316, partial DFG317, and node 318. Node 311 outputs α as an output value to partial DFG313. Node 311 also outputs an output value to partial DFG314. This output value is, for example, the result of the operation of node 311. Node 312 also outputs ε as an output value to partial DFG316. This output value is, for example, the result of the operation of node 312.

[0066] Furthermore, partial DFG 313 executes the operation of function K(α) using α, which is the output value from node 311, as an argument, and outputs β as an output value based on the operation result to partial DFG 315. Furthermore, partial DFG 313 executes the operation of function K(α) using α, which is the output value from node 311, as an argument, and outputs γ as an output value based on the operation result to partial DFG 317.

[0067] Partial DFG 315 executes the operation of function f3(β) using β, which is the output value from partial DFG 313, as an argument, and outputs δ to partial DFG 316 as an output value based on the operation result. Partial DFG 317 executes the operation of function g2(γ) using γ, which is the output value from partial DFG 313, as an argument, and outputs θ to node 318 as an output value based on the operation result. Furthermore, partial DFG 316 executes the operation of function f4(δ,ε) using ε, which is the output value of node 312, and δ, which is the output value of partial DFG 315, as arguments, and outputs φ to node 318 as an output value based on the operation result.

[0068] Node 318 executes the operation h(θ,φ) using as arguments φ, which is the output value of partial DFG 316, and θ, which is the output value of partial DFG 317. Partial DFG 314 executes a predetermined operation using the output value from node 311.

[0069] DFG301 is mapped as shown in mapping result 302. Here, mapping is performed so that the operation of partial DFG 314 is executed last. Furthermore, in mapping result 302, nodes 311 and 312 that output the first data in DFG 301 are omitted to make the data transmission sequence easier to see. Mapping result 302 uses 12 PEs 100, namely PEs 121 to 126 and 131 to 136. In this case, partial DFG 313 is assigned to PE 121, partial DFG 315 is assigned to PE 122, partial DFG 316 is assigned to PE 123, partial DFG 317 is assigned to PE 124, and node 318 is assigned to PE 125. Partial DFG 314 is mapped to PE 126 and subsequent PEs to which the same pattern is assigned.

[0070] In this case, because the output value of partial DFG 313 is used in partial DFG 317, the output value of partial DFG 313 is held when the calculation of f2(δ,ε) in partial DFG 316 starts. Therefore, three data transmission sequences are used between PE122 and PE123. Therefore, to transmit data used in the calculation of partial DFG 314 to PE126, one more data transmission sequence is added to the three types of data transmission sequences that PE122 can transmit. As a result, two sequences of PE100 are used: a sequence of PE121 to PE126 and a sequence of PE131 to PE136.

[0071] 12 is a diagram showing a DFG after conversion of the DFG of the third pattern. DFG301 can be replaced with DFG303. In this case, partial DFG320, which is a copy of partial DFG313 in DFG301 of the third pattern, is added. Partial DFG313 executes the operation of function K(α) using α, which is the output value from node 311, as an argument, and outputs β, which is an output value based on the operation result, to partial DFG315. Furthermore, partial DFG320 executes the operation of function K(α) using α, which is the output value from node 311, as an argument, and outputs γ, which is an output value based on the operation result, to partial DFG317. Other processing is the same as that of DFG301 of the third pattern.

[0072] In general, the conditions for a DFG to fall under the third pattern are as follows: There exists a first partial DFG whose output value is used in two different partial DFGs. Here, the two paths through which the output value of the first partial DFG is used are referred to as the first path and the second path. The first path and the second path ultimately connect to one node or partial DFG. Either the first path or the second path has a multi-stage configuration formed by a set of multiple nodes or DFGs. In the first path or the second path having a multi-stage configuration, it is not necessary to retain at least one input value at any stage. For example, partial DFG 313 is an example of a first partial DFG, and the path in which the output value of partial DFG 313 is sent to node 318 via operations by partial DFGs 315 and 316 is an example of a "first path." The path in which the output value of partial DFG 313 is sent to node 318 via operations by partial DFG 317 is an example of a "second path." The output value input to the first partial DFG is used in another partial DFG or node. Furthermore, when converting a DFG that is too large, the number of operations may increase significantly, so it is desirable to add a condition that the number of nodes included in the first partial DFG is equal to or less than a threshold.

[0073] That is, in DFG301, node 311 is the first node, partial DFG313 is the second node, and partial DFG315 and partial DFG316 are the third node. Furthermore, if partial DFG317 is the fourth node, node 318 is the fifth node, and partial DFG314 is the sixth node, then the third pattern can be expressed as follows: The third pattern has a first node. The third pattern also has a second node that performs an operation using the output value of the first node. The third pattern also has a third node, which is a plurality of nodes that perform successive operations using the output value of the second node, and in which one of the values ​​used in the operation at each node can be discarded after the operation. The third pattern also has a fourth node that performs an operation using the output value of the second node. The third pattern also has a fifth node that performs an operation using the output value of the third node and the output value of the fourth node as arguments. The third pattern also has a sixth node that receives the output value of the first node as input.

[0074] A DFG of the third pattern that satisfies the above conditions can be transformed as follows: The first partial DFG is duplicated to generate the first' partial DFG. The input of the first' partial DFG is set to the same input as the first partial DFG. Furthermore, connections are made so that the output value of the first' partial DFG is used in the second path instead of the output value of the first partial DFG.

[0075] When this conversion is performed, for example, the converted DFG 303 is mapped as shown in mapping result 304. Here too, mapping is performed so that the operation of partial DFG 314 is executed last. In mapping result 304, nodes 311 and 312 that output the first data in DFG 303 are omitted to make the data transmission sequence easier to see. Mapping result 304 uses PE121 to PE126, which are six PEs 100. In this case, partial DFG 313 is assigned to PE121, partial DFG 315 is assigned to PE122, and partial DFG 316 is assigned to PE123. Furthermore, partial DFG 320 is assigned to PE124, partial DFG 317 is assigned to PE125, and node 318 is assigned to PE126. Partial DFG 314 is assigned to PE127 and subsequent PEs to which the same pattern is assigned. In the mapping result 304, the same data is sent using lines of the same type as the lines used to indicate the data flow in the DFG 303. Also, the gray lines are paths through which any data can pass. In other words, in the case of the mapping result 304, three data transmission sequences are used.

[0076] The mapping result 304 can reduce the number of data transmission streams by one compared to the mapping result 302 in Fig. 11. In other words, data of another DFG can be transmitted in the reduced one data transmission stream, thereby improving the utilization efficiency of the PE 100 as a whole.

[0077] In this embodiment, the three DFG patterns described above are used as DFG conversion candidate patterns that can reduce the data transmission sequence, but the DFG conversion candidate patterns are not limited to these three. Various patterns are possible as patterns that can reduce the data transmission sequence, and it is preferable to select the pattern to be used depending on the size of the DFG and the calculation to be performed.

[0078] Continuing the explanation, returning to Fig. 3, the extraction unit 102 extracts the DFG locations of the first to third patterns described above from the DFG provided by the user, and outputs information on the extracted locations and information on the DFG patterns corresponding to each location to the candidate determination unit 103.

[0079] The candidate determination unit 103 receives input of information on locations extracted from a given DFG and information on DFG patterns corresponding to each location from the extraction unit 102. The candidate determination unit 103 also has in advance priority information according to the type of conversion pattern. In this embodiment, the candidate determination unit 103 has priority information in which the first pattern has the highest priority, the second pattern has the next highest priority, and the third pattern has the lowest priority. The candidate determination unit 103 then generates information on DFG conversion candidates, which are DFGs that can be applied to each extracted location in the given DFG.

[0080] Here, it is also possible to apply DFG conversions of multiple patterns to the same location. When applying DFG conversions of multiple patterns to the same location, the candidate determination unit 103 generates DFG conversion candidates so as to apply the minimum number required to reduce the data transmission sequence. For example, even if a first pattern is included in a DFG of a second pattern, there may be a case where the reduction in the data transmission sequence of the DFG as a whole due to the conversion of the data sequence to the DFG of the second pattern is not affected by the reduction in the data transmission sequence due to the application of the first pattern. In this case, the candidate determination unit 103 selects the DFG of the second pattern as a DFG conversion candidate for that location, but does not select the DFG of the first pattern as a DFG conversion candidate. Furthermore, when DFG conversions of patterns that cannot be applied simultaneously to the same location compete with each other, the candidate determination unit 103 selects the DFG of the pattern with the highest priority as the DFG conversion candidate.

[0081] Next, the candidate determination unit 103 selects, from the generated DFG conversion candidates, a DFG conversion candidate that can actually be used to convert the given DFG, using the following method, and sets the selected DFG as the applied DFG.

[0082] Here, converting a given DFG using all of the DFG conversion candidates identified by the extraction unit 102 does not necessarily result in an efficient DFG. For example, when converting a DFG of the first pattern, the critical path may be extended. When converting a DFG of the second pattern, the critical path length of the converted portion may be extended. When converting a DFG of the third pattern, the number of operations may increase. As a result of the extension of the critical path length or the increase in the number of operations, the number of data transmission sequences may become greater than before conversion, or mapping to the CGRA 110 may become difficult.

[0083] Therefore, the candidate determination unit 103 selects an applicable DFG to be used for conversion from among the DFG conversion candidates according to priority so that the critical path length after conversion of the DFG provided by the user falls within a range that can be executed by the CGRA 110.

[0084] Thereafter, the candidate determination unit 103 outputs information on the portion to be converted in the DFG provided by the user and the pattern of the DFG to be applied to that portion to the DFG conversion unit 104 together with the DFG provided by the user.

[0085] The DFG conversion unit 104 receives input from the candidate determination unit 103 of information on the location to be converted in the DFG provided by the user and the pattern of the DFG to be applied to that location. Next, the DFG conversion unit 104 converts the DFG according to the type of pattern of the applied DFG for each specified location to be converted. If there are multiple patterns of applied DFGs for one location, the DFG conversion unit 104 converts all of the DFGs according to each pattern. Thereafter, the DFG conversion unit 104 outputs to the notification unit 105 a converted DFG that adds a conversion to the DFG provided by the user to reduce the data transmission sequence.

[0086] Fig. 13 is a diagram showing an application example of DFG conversion. For example, a case will be described where DFG 401 in Fig. 13 is provided by a user. In DFG 401, application point 411 is a point where DFG conversion of a first pattern can be applied. Furthermore, application point 412 is a point where DFG conversion of a second pattern can be applied. Furthermore, application point 413 is a point where DFG conversion of a third pattern can be applied.

[0087] Therefore, the DFG conversion unit 104 performs a DFG conversion of a first pattern on the application point 411, converting the application point 411 into a converted DFG 421 in the converted DFG 402. The DFG conversion unit 104 also performs a DFG conversion of a second pattern on the application point 412, converting the application point 412 into a converted DFG 422 in the converted DFG 402. The DFG conversion unit 104 also performs a DFG conversion of a third pattern on the application point 413, converting the application point 413 into a converted DFG 423 in the converted DFG 402. In this way, the DFG conversion unit 104 converts the DFG 401 provided by the user to generate a converted DFG 402. In this case, the converted DFG 402 can be mapped in a form that holds up to three pieces of data simultaneously, and can be mapped to one column of PEs 100.

[0088] The notification unit 105 receives an input of a transformed DFG, which is a DFG provided by a user and which has been subjected to a transformation to reduce the data transmission sequence, from the DFG transformation unit 104. Then, the notification unit 105 transmits the transformed DFG to the mapping device 11 and instructs the mapping device 11 to perform mapping using the transmitted transformed DFG.

[0089] 14 is a flowchart of the process of generating DFG conversion candidates. Next, the flow of the process of generating DFG conversion candidates will be described with reference to FIG.

[0090] The extraction unit 102 extracts a portion corresponding to a DFG of a predetermined pattern from a DFG given by a user (step S1).

[0091] The candidate determination unit 103 selects one location from the locations extracted by the extraction unit 102 (step S2).

[0092] Next, the candidate determination unit 103 identifies a mapping position corresponding to the selected extraction point in the mapping result acquired from the mapping device 11 (step S3).

[0093] Next, the candidate determination unit 103 identifies all other extraction locations that are mapped to the row of the PE 100 included in the identified position (step S4).

[0094] Next, the candidate determination unit 103 determines the number of simultaneous data storages that is reduced when all DFG transformations of the patterns for the selected extraction point and the identified extraction point are applied to the selected extraction point as n (step S5).

[0095] Next, the candidate determination unit 103 sets the number of wires used for data transfer in the row of the PE 100 that holds the largest number of simultaneous data items as k, and sets the remainder when k is divided by 3 as m (step S6). That is, m=k mod 3. Here, the division value "3" indicates the number of types of data that can be transmitted between the PEs 100 in this embodiment. This number depends on the architecture of the CGRA 110.

[0096] Next, the candidate determination unit 103 determines whether m is equal to or less than n (step S7). If m is greater than n (step S7: No), the candidate determination unit 103 proceeds to step S10.

[0097] On the other hand, if m is less than or equal to n (step S7: Yes), the candidate determination unit 103 adds the DFG conversions of the m patterns with the highest priority from the DFG conversions of the patterns for the selected extraction location and the identified extraction location to the DFG conversion candidates (step S8).

[0098] Next, the candidate determination unit 103 adds DFG conversions of (nm)-((nm) mod 3) patterns with high priorities among the patterns other than the DFG conversion candidates to the DFG conversion candidates (step S9).

[0099] The candidate determination unit 103 determines whether or not the selection of DFG conversion candidates for all extraction locations has been completed (step S10). If there are extraction locations for which DFG conversion candidates have not been selected (step S10: No), the candidate determination unit 103 returns to step S2.

[0100] On the other hand, when the selection of DFG conversion candidates for all extraction locations has been completed (step S10: Yes), the candidate determination unit 103 determines the DFG conversion candidates at that time as DFG conversion candidates that may actually be applied (step S11).

[0101] Here, the process of extracting the DFG portions of the first to third patterns will be described. The process described below is an example of the process carried out in step S1 of FIG.

[0102] 15 is a flowchart of the process of extracting the DFG portion of the first pattern. An example of the flow of the process of extracting the DFG portion of the first pattern will be described with reference to FIG.

[0103] The extraction unit 102 identifies a first node that executes predication in a given DFG (step S101).

[0104] Next, the extraction unit 102 determines whether or not the second and third nodes that are output sources of the then and else values ​​of the predication have a common ancestor (step S102). That is, the extraction unit 102 determines whether or not the same node is reached by tracing back the DFG from the second and third nodes.

[0105] If the second node and the third node have a common ancestor (step S102: Yes), the extraction unit 102 determines whether the functions of the second node and the third node are identical except for the constant parts that serve as arguments (step S103).

[0106] If the functions are identical except for the constant parts that serve as arguments (step S103: Yes), the extraction unit 102 extracts a portion corresponding to the DFG of the first pattern that includes the first to third nodes (step S104).

[0107] On the other hand, if the second node and the third node do not have a common ancestor (step S102: No) or the functions are not identical except for the constant parts that serve as arguments (step S103: No), the extraction unit 102 executes the following process: The extraction unit 102 determines that there is no part that corresponds to the DFG of the first pattern that includes the first to third nodes (step S105).

[0108] 16 is a flowchart of the process of extracting the DFG portion of the second pattern. An example of the flow of the process of extracting the DFG portion of the second pattern will be described with reference to FIG.

[0109] The extraction unit 102 identifies a second node that executes the operation of the function f that satisfies the associative rule (step S111).

[0110] The extraction unit 102 determines whether the two values ​​used by the second node in the calculation of the function f are the same or not (step S112).

[0111] If the two values ​​used by the second node in the calculation of the function f are the same (step S112: Yes), the extraction unit 102 identifies the first node whose output value is input to the second node (step S113).

[0112] It is determined whether the operation result of the second node is an argument of a third node that executes the same operation (step S114).

[0113] If the operation result of the second node is an argument of a third node that executes the same operation (step S114: Yes), the extraction unit 102 identifies a fourth node that uses the other argument of the third node as an output value (step S115).

[0114] The extraction unit 102 determines whether the output value of the first node is input to the fourth node (step S116).

[0115] If the output value of the first node is input to the fourth node (step S116: Yes), the extraction unit 102 extracts a portion corresponding to the DFG of the second pattern including the first to fourth nodes (step S117).

[0116] On the other hand, if the two values ​​used in the calculation of the function f by the second node are different (step S112: No), the extraction unit 102 executes the following process. Similarly, if the calculation result of the second node is not an argument of the third node that executes the same calculation (step S114: No) and if the output value of the first node is not input to the fourth node (step S116: No), the extraction unit 102 executes the following process. The extraction unit 102 determines that there is no location corresponding to the DFG of the second pattern including the first to fourth nodes (step S118).

[0117] 17 is a flowchart of the process of extracting the DFG portion of the third pattern. An example of the flow of the process of extracting the DFG portion of the third pattern will be described with reference to FIG.

[0118] The extraction unit 102 identifies a subgraph whose output value is used in two paths, the first and the second paths (step S121).

[0119] Next, the extraction unit 102 determines whether the number of nodes included in the identified subgraph is equal to or less than a threshold value (step S122).

[0120] If the number of nodes included in the subgraph is equal to or less than the threshold (step S122: Yes), the extraction unit 102 determines whether the calculation results of the first and second routes merge (step S123). That is, the extraction unit 102 determines whether the first route and the second route connect to the same node or subDFG.

[0121] If the calculation results of the first and second routes converge (step S123: Yes), the extraction unit 102 determines whether any of the routes is multi-stage and whether there is an input value that can be discarded before the confluence in the multi-stage route (step S124).

[0122] If any of the paths is multi-stage and there is an input value that can be discarded before the junction in the multi-stage path (step S124: Yes), the extraction unit 102 determines whether the output value input to the subgraph is input to another subDFG (step S125).

[0123] If the output value input to the subgraph is input to another subDFG (step S125: Yes), the extraction unit 102 extracts a part corresponding to a third pattern DFG including the subgraph, the first path, and the second path (step S126).

[0124] On the other hand, if the number of nodes included in the subgraph is equal to or greater than the threshold (step S122: No), the extraction unit 102 determines that there is no location corresponding to the DFG of the third pattern (step S127). Also, if the calculation results of the first and second paths do not converge (step S123: No), the extraction unit 102 also determines that there is no location corresponding to the DFG of the third pattern (step S127). Also, if none of the paths is multi-stage, or if there is no discardable input value before the convergence in a multi-stage path (step S124: No), the extraction unit 102 also determines that there is no location corresponding to the DFG of the third pattern (step S127). Also, if an output value input to a subgraph is not input to another subgraph (step S125: No), the extraction unit 102 also determines that there is no location corresponding to the DFG of the third pattern including the subgraph, the first path, and the second path (step S127).

[0125] 18 is a flowchart of the DFG candidate determination process and the converted DFG generation process. Next, the flow of the DFG candidate determination process and the converted DFG generation process will be described with reference to FIG.

[0126] The candidate determination unit 103 generates DFG conversion candidates (step S21). The processing executed by the candidate determination unit 103 in steps S2 to S11 in the flow shown in FIG. 14 corresponds to an example of this processing.

[0127] Next, the candidate determination unit 103 obtains the priority of each pattern of the DFG to be converted (step S22).

[0128] Next, the candidate determination unit 103 selects the pattern with the highest priority from among the unselected patterns (step S23).

[0129] The candidate determination unit 103 determines whether or not the path length exceeds the number of lines in the CGRA 110 when conversion is performed on the corresponding extracted portion using the DFG conversion candidate of the selected pattern (step S24). If there is no extracted portion whose path length does not exceed the number of lines in the CGRA 110 when conversion is performed (step S24: No), the candidate determination unit 103 proceeds to step S26.

[0130] On the other hand, if there is an extraction point whose path length does not exceed the number of rows of the CGRA 110 (step S24: Yes), the candidate determination unit 103 selects the DFG conversion candidate of the pattern selected for the corresponding extraction point as the application DFG (step S25).

[0131] Thereafter, the candidate determination unit 103 determines whether or not the application DFG has been considered for all patterns (step S26). If there is a pattern for which the application DFG has not been considered (step S26: No), the candidate determination unit 103 returns to step S23.

[0132] On the other hand, if the selection of the applicable DFG has been performed for all patterns (step S26: Yes), the candidate determination unit 103 notifies the DFG to be applied for each extraction point to the DFG conversion unit 104 (step S27).

[0133] The DFG conversion unit 104 performs conversion on each extracted portion in the given DFG based on the applied DFG, and generates a converted DFG (step S28).

[0134] Next, a description will be given of the conversion processing of the first to third patterns of DFG by the DFG conversion unit 104. The processing described below corresponds to an example of the processing carried out in step S28 of FIG.

[0135] Fig. 19 is a flowchart of the conversion process of the DFG of the first pattern. An example of the flow of the conversion process of the DFG of the first pattern will be described with reference to Fig. 19. Here, the node that executes predication is the first node, the node that outputs an output value used as the then value of the first node is the second node, and the node that outputs an output value used as the else value of the first node is the third node. Also, the constant used by the second node in the calculation of the function f is c1, and the constant used by the third node in the calculation of the function f is c2. Furthermore, the node that receives the input of the output value of the first node is the fourth node.

[0136] The DFG conversion unit 104 replaces "then" in the predication of the first node with c1 and "else" with c2 (step S201).

[0137] Next, the DFG conversion unit 104 deletes the second node or the third node. Then, the DFG conversion unit 104 sets the input of the remaining node of the second node or the third node as the output of the first node. Furthermore, the DFG conversion unit 104 replaces the constant part of the function f in the remaining node of the second node or the third node with the output value of the first node (step S202).

[0138] Next, the DFG conversion unit 104 replaces the input to the fourth node from the output of the first node with the output of the remaining node out of the second node and the third node (step S203).

[0139] 20 is a flowchart of the conversion process of the DFG of the second pattern. An example of the flow of the conversion process of the DFG of the second pattern will be described with reference to FIG. 20. Here, node 252 in FIG. 7 that executes the operation of function f that satisfies the associative law is defined as the second node. Node 251 in FIG. 7, whose output value is input to the second node, is defined as the first node. Node 255 in FIG. 7, to which the output value of the second node is input, is defined as the third node. Node 253 in FIG. 7, which receives the output value of the first node and outputs the output value to the third node, is defined as the fourth node.

[0140] The DFG conversion unit 104 deletes the second and third nodes (step S211).

[0141] Next, the DFG conversion unit 104 adds, as a sixth node, a node that performs an operation of a function f that satisfies the associative rule using the output of the fourth node and the output of the first node (step S212). This sixth node corresponds to node 256 in FIG. 8.

[0142] Next, the DFG conversion unit 104 adds a seventh node that performs the operation of the function f using the output of the sixth node and the output of the first node (step S213). This sixth node corresponds to node 257 in FIG.

[0143] Furthermore, the DFG conversion unit 104 sets the input of the node that previously had the output of the third node as the output of the seventh node (step S214).

[0144] Fig. 21 is a flowchart of the conversion process of a DFG of the third pattern. An example of the flow of the conversion process of a DFG of the third pattern will be described with reference to Fig. 21. Here, the partial DFG 313 in Fig. 11, whose output value is used in two paths, is defined as the second node. Also, the node 311 in Fig. 11, whose output value is input to the third node, is defined as the first node. Also, of the first and second paths that use the output value of the second node, the partial DFG 317 in Fig. 11, which receives the input of the output value of the second node in a path that is not multi-stage, is defined as the third node.

[0145] The DFG conversion unit 104 replicates the second node to generate a fourth node (step S221). This fourth node corresponds to the partial DFG 320 in FIG.

[0146] Next, the DFG conversion unit 104 sets the input of the fourth node as the output of the first node (step S222).

[0147] Next, the DFG conversion unit 104 replaces the input of the third node with the output of the fourth node instead of the output of the second node (step S223).

[0148] As described above, the DFG conversion device 10 according to this embodiment extracts a DFG of a predetermined pattern from a given DFG and identifies the location where the extracted DFG is mapped from the mapping result. The DFG conversion device 10 then extracts other patterns that use the same row of the PE 100 at the identified location and determines a conversion candidate DFG according to the reduction in the number of data transmission columns. Furthermore, the DFG conversion device 10 identifies, according to priority, one of the conversion candidate DFGs whose path length fits within the CGRA 110, and uses the application DFG to generate a converted DFG by converting the given DFG.

[0149] This allows for efficient mapping, reducing the number of data transmissions while maintaining the same computational complexity for a given DFG. This efficient mapping improves the utilization efficiency of the PE 100 and the processing power of the CGRA 110.

[0150] (Hardware configuration) Fig. 22 is a diagram showing the hardware configuration of the DFG conversion device. Next, an example of a hardware configuration for realizing each function of the DFG conversion device 10 will be described with reference to Fig. 22.

[0151] 22, the DFG conversion device 10 includes, for example, a CPU (Central Processing Unit) 91, a memory 92, a hard disk 93, and a network interface 94. The CPU 91 is connected to the memory 92, the hard disk 93, and the network interface 94 via a bus.

[0152] The network interface 94 is an interface for communication between the DFG conversion device 10 and an external device. The network interface 94 relays communication between the mapping device 11 and the CPU 91, for example.

[0153] The hard disk 93 is an auxiliary storage device that stores various programs, including programs for realizing the functions of the data collection unit 101, extraction unit 102, candidate determination unit 103, DFG conversion unit 104, and notification unit 105, as illustrated in FIG.

[0154] The memory 92 is a main storage device and may be, for example, a dynamic random access memory (DRAM).

[0155] The CPU 91 reads various programs from the hard disk 93, expands them into the memory 92, and executes them. As a result, the CPU 91 realizes the functions of the data collection unit 101, extraction unit 102, candidate determination unit 103, DFG conversion unit 104, and notification unit 105 illustrated in FIG.

[0156] Here, the DFG conversion device 10 and the mapping device 11 included in the automatic mapper 1 have been described as separate devices, but this is not limited to this, and the DFG conversion device 10 and the mapping device 11 can also be combined into a single device. [Explanation of symbols]

[0157] 1 Automapper 2. User terminal device 3. Information processing equipment 4. Automated Mapping System 10 DFG conversion device 11 Mapping equipment 100 PE 110 CGRA 101 Data Collection Department 102 Extraction part 103 Candidate determination section 104 DFG conversion unit 105 Notification Department

Claims

1. A mapping result is obtained, which includes information on allocation of operations to each arithmetic unit and wiring between the arithmetic units, determined so as to correspond to a predetermined DFG (Data Flow Graph) and a CGRA (Coarse-Grained Reconfigurable Architecture) having a plurality of arithmetic units; extracting a portion corresponding to a predetermined DFG pattern from the predetermined DFG; determining a conversion candidate DFG from among DFGs corresponding to the pattern of the extraction points based on the positions to which the extraction points are assigned in the mapping result and the number of data transmission paths used between the arithmetic units; Based on the transformation candidate DFG, the predetermined DFG is transformed to generate a transformed DFG. A conversion program that causes a computer to execute a process.

2. selecting an application DFG from the conversion candidate DFGs, which is a DFG obtained by performing a predetermined conversion on the conversion candidate DFG in the predetermined DFG, and which can be mapped to the CGRA; The process of generating the transformed DFG includes a process of generating the transformed DFG by transforming the predetermined DFG using the applied DFG.

2. The conversion program according to claim 1.

3. 2. The conversion program according to claim 1, wherein the extraction process extracts at least a portion corresponding to a first pattern having a first node, a second node, and a third node and a fourth node that executes an operation of a first function using two arguments, one of which is a fixed value, and that uses an output value from the first node for the other of the two arguments, and a fifth node that uses the output value of the second node as a judgment condition and sets either the output value of the third node or the output value of the fourth node as an output value according to the judgment result.

4. 2. The conversion program according to claim 1, wherein the extraction process extracts at least a portion corresponding to a second pattern having a first node, a second node that executes an operation of a second function that satisfies an associative rule using two arguments, with output values ​​from the first node as the two arguments, a third node that executes an operation with the output value of the first node as an argument, a fourth node that executes an operation of the second function with the output value from the second node and the output value from the third node as the two arguments, and a fifth node that receives an input of the output value of the first node.

5. 2. The conversion program according to claim 1, wherein the extraction process extracts at least a portion corresponding to a third pattern having a first node, a second node that performs an operation using an output value of the first node, a plurality of nodes that perform successive operations using the output value of the second node, wherein one of the values ​​used in the operation at each node can be discarded after the operation, a fourth node that performs an operation using the output value of the second node, a fifth node that performs an operation using the output value of the third node and the output value of the fourth node as arguments, and a sixth node that receives as input the output value of the first node.

6. The conversion device is A mapping result including information on a predetermined DFG, an allocation of operations to each arithmetic unit determined to correspond to the predetermined DFG for a CGRA having a plurality of arithmetic units, and information on wiring between the arithmetic units is acquired; extracting a portion corresponding to a predetermined DFG pattern from the predetermined DFG; determining a conversion candidate DFG from among DFGs corresponding to the pattern of the extraction points based on the positions to which the extraction points are assigned in the mapping result and the number of data transmission paths used between the arithmetic units; Based on the transformation candidate DFG, the predetermined DFG is transformed to generate a transformed DFG. A conversion method characterized by performing a process.

7. a data collection unit that acquires a mapping result including information on a predetermined DFG, an allocation of operations to each arithmetic unit determined to correspond to the predetermined DFG for a CGRA having a plurality of arithmetic units, and information on wiring between the arithmetic units; an extracting unit that extracts a portion corresponding to a predetermined DFG pattern from the predetermined DFG; a candidate determination unit that determines a conversion candidate DFG from among DFGs corresponding to patterns of extraction points based on positions to which extraction points are assigned in the mapping result and the number of data transmission paths used between the computing units; a DFG conversion unit that converts the predetermined DFG based on the conversion candidate DFG to generate a converted DFG; A conversion device comprising:

Images