Semiconductor device

Abstract

To suppress the occurrence of damage to a bonding member for bonding a semiconductor chip to a wiring board.SOLUTION: An insulating substrate 11 including an insulating plate 11a and a wiring board 11a formed on an upper surface of the insulating plate 11b1, a semiconductor-chip 11b1 having a lower surface disposed on an upper surface side of the wiring board 12a, and a joining member 14c including a conductive support member 11b1 and joining the upper surface of the wiring board 12a and the lower surface of the semiconductor-chip 14b. Further, the upper surface of the wiring board 11b1 is formed with the restricting portion 14c which is brought into contact with the support member 14c to restrict the movement of the support member 11d, and the support member 14c stays at a position overlapping with the semiconductor element 12a as viewed in a plan view.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] In a semiconductor device, a semiconductor chip and an insulating substrate, or a semiconductor chip and a lead frame are bonded together using a bonding material such as solder.

[0003] Also, a semiconductor device having a solder layer containing a plurality of support particles has been proposed (see, for example, Patent Document 1). Also, an electronic component having a bonding layer in which a plurality of conductive solid spacers are embedded has been proposed (see, for example, Patent Document 2). Furthermore, a semiconductor device having a solder layer in which a low-melting-point solder portion containing fine particles has been formed has been proposed (see, for example, Patent Document 3). Also, a semiconductor device having a solder bonding layer containing a filler has been proposed (see, for example, Patent Document 4). Also, a power semiconductor module has been proposed in which a power semiconductor element and a conductor plate are soldered together with a metal spacer in contact with the power semiconductor element (see, for example, Patent Document 5). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-92232 [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-28433 [Patent Document 3] Japanese Patent Application Publication No. 2019-67976 [Patent Document 4] Japanese Patent Application Laid-Open No. 2008-270846 [Patent Document 5] Japanese Patent Application Laid-Open No. 2014-67809 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device in which damage to a joining member that joins a semiconductor chip to a wiring board is suppressed. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a semiconductor device comprising: an insulating substrate including an insulating plate and a wiring board formed on an upper surface of the insulating plate; a semiconductor chip having a lower surface arranged on the upper surface side of the wiring board; and a joining member containing a conductive support member and joining the upper surface of the wiring board and the lower surface of the semiconductor chip, wherein a regulating portion is formed on the upper surface of the wiring board to contact the support member and regulate movement of the support member, and the support member remains in a position overlapping the semiconductor chip in a planar view.

[0007] The restricting portion may be formed in a region of the upper surface of the wiring board that faces the outer edge of the lower surface of the semiconductor chip.

[0008] The lower surface of the semiconductor chip may be rectangular in plan view, and the restricting portion may be formed on the upper surface of the wiring board at a position facing a corner area of ​​the lower surface of the semiconductor chip.

[0009] The restricting portion may have a curved shape that is convex in a direction from the center of the lower surface of the semiconductor chip toward the outer edge of the lower surface of the semiconductor chip in a plan view.

[0010] The lower surface of the semiconductor chip may be rectangular in plan view, and the restricting portion may be arranged in a region of the upper surface of the wiring board facing an edge along one side of the lower surface of the semiconductor chip, extending in a direction along the one side.

[0011] The lower surface of the semiconductor chip may be rectangular in plan view, and the restricting portions may be arranged at intervals in a direction along one side in an area of ​​the upper surface of the wiring board facing an edge portion along one side of the lower surface of the semiconductor chip.

[0012] The restricting portions may be formed in a staggered pattern in a region of the upper surface of the wiring board that faces the lower surface of the semiconductor chip.

[0013] The wiring board may include an inclined surface on its upper surface that is inclined due to the warping of the insulating substrate, the joining member joins the lower surface of the semiconductor chip to the inclined surface of the wiring board, and the regulating portion may be formed in an area on the upper surface of the wiring board that faces the lower surface of the semiconductor chip, the area being closer to the apex of the warping of the insulating substrate.

[0014] The restricting portion may be formed in a convex shape extending from the upper surface of the wiring board toward the semiconductor chip.

[0015] The restricting portion may have a recessed shape recessed from the upper surface of the wiring board toward the insulating plate. The restricting portion may be a roughened area in which the upper surface of the wiring board is roughened.

[0016] The support member may be spherical. The bottom surface of the semiconductor chip may be in contact with the support member.

[0017] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Effects of the Invention]

[0018] According to the disclosed technique, it is possible to suppress damage to the bonding member that bonds the semiconductor chip to the wiring board. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a plan view of a semiconductor device according to an embodiment; [Figure 2] 1 is a side view of a semiconductor device according to an embodiment; [Figure 3] FIG. 2 is a plan view of a semiconductor unit according to the embodiment. [Figure 4] FIG. 2 is a cross-sectional view of a semiconductor unit according to the embodiment. [Figure 5] FIG. 2 is a cross-sectional view of a semiconductor unit according to a first comparative example. [Figure 6] FIG. 10 is a cross-sectional view of a second comparative example of a semiconductor unit. [Figure 7] 3A and 3B are a plan view and a cross-sectional view of a first example of a restricting portion. [Figure 8] FIG. 4 is an enlarged cross-sectional view of a region including a restricting portion. [Figure 9] FIG. 10 is a plan view of a second example of a restricting portion. [Figure 10] FIG. 10 is a plan view of a third example of a restricting portion. [Figure 11] FIG. 10 is a plan view of a fourth example of a restricting portion. [Figure 12] FIG. 10 is a plan view of a fifth example of a restricting portion. [Figure 13] FIG. 10 is a plan view of a sixth example of a restricting portion. [Figure 14] 10 is a cross-sectional view showing the positional relationship between a convex restricting portion and a semiconductor chip. FIG. [Figure 15] 10A and 10B are a plan view and a cross-sectional view of a seventh example of a restricting portion. [Figure 16] 10 is a cross-sectional view showing the positional relationship between a recessed restricting portion and a semiconductor chip. FIG. [Figure 17] FIG. 13 is a plan view of an eighth example of a restricting portion. [Figure 18] FIG. 10 is a side view of a semiconductor unit in which warpage occurs. [Figure 19] FIG. 13 is a plan view of a ninth example of a restricting portion. [Figure 20] 1 is a flowchart showing a manufacturing process of a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "top surface" refer to the XY plane facing upward (+Z direction) in the semiconductor device shown in the drawings. Similarly, "top" refers to the upward (+Z direction) direction in the semiconductor device shown in the drawings. The terms "back surface" and "bottom surface" refer to the XY plane facing downward (-Z direction) in the semiconductor device shown in the drawings. Similarly, the term "bottom" refers to the downward (-Z direction) direction in the semiconductor device shown in the drawings. Similar directions will be used in other drawings as necessary. The terms "front surface," "top surface," "top," "back surface," "bottom surface," "bottom," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "top" and "bottom" do not necessarily refer to the vertical direction relative to the ground. In other words, the "top" and "bottom" directions are not limited to the direction of gravity.

[0021] First, an example of the overall configuration of a semiconductor device according to an embodiment will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a plan view of the semiconductor device according to the embodiment. Fig. 2 is a side view of the semiconductor device according to the embodiment. Fig. 2 is a side view of the semiconductor device 1 of Fig. 1 as viewed in the +Y direction.

[0022] The semiconductor device 1 includes a semiconductor module 2 and a cooling device 3. The semiconductor module 2 includes semiconductor units 10a, 10b, and 10c and a case 20 that houses the semiconductor units 10a, 10b, and 10c. The case 20 is disposed above the cooling device 3, and the semiconductor units 10a, 10b, and 10c are arranged in a row in the +X direction inside the case 20. The semiconductor units 10a, 10b, and 10c housed in the case 20 are sealed with a sealing member (not shown).

[0023] The semiconductor units 10a, 10b, and 10c all have the same configuration. Therefore, when there is no need to distinguish between the semiconductor units 10a, 10b, and 10c, they will be referred to as "semiconductor unit 10." Details of the semiconductor unit 10 will be described later.

[0024] The case 20 includes an outer frame 21, first connection terminals 22a, 22b, and 22c, second connection terminals 23a, 23b, and 23c, a U-phase output terminal 24a, a V-phase output terminal 24b, a W-phase output terminal 24c, and control terminals 25a and 25b.

[0025] The outer frame 21 has a substantially rectangular shape in plan view and is surrounded on all four sides by side walls 21a, 21b, 21c, and 21d. The side walls 21a and 21c are the long sides of the outer frame 21, and the side walls 21b and 21d are the short sides of the outer frame 21. In plan view, the corners where the side walls 21a, 21b, 21c, and 21d are connected do not necessarily have to be right angles. Such connection points may be rounded, for example, as shown in FIG. 1. The back surfaces of the outer frame 21 (side walls 21a, 21b, 21c, and 21d) may be flush with each other and parallel to the XY plane.

[0026] The outer frame 21 includes unit storage compartments 21e, 21f, and 21g at the center of the extension direction (±Y direction) of side walls 21b and 21d on the front surface, along side walls 21a and 21c (±X direction). The unit storage compartments 21e, 21f, and 21g are each defined by a substantially rectangular shape in a plan view on the front surface of the outer frame 21, and are open. The unit storage compartments 21e, 21f, and 21g store the semiconductor units 10a, 10b, and 10c, respectively. Therefore, the size of the unit storage compartments 21e, 21f, and 21g may be large enough to store the semiconductor units 10a, 10b, and 10c.

[0027] In a plan view, the outer frame 21 is provided with first connection terminals 22a, 22b, 22c and second connection terminals 23a, 23b, 23c along the side wall 21a (±X direction) on the side wall 21a side of the front surface. The first connection terminals 22a, 22b, 22c are positive input terminals (P terminals), and the second connection terminals 23a, 23b, 23c are negative input terminals (N terminals).

[0028] Furthermore, outer frame 21 is provided with a U-phase output terminal 24a, a V-phase output terminal 24b, and a W-phase output terminal 24c on the side wall 21c of the front surface along side wall 21c (±X directions). In this case, first connection terminal 22a, second connection terminal 23a, and U-phase output terminal 24a are provided on either side of unit storage section 21e. First connection terminal 22b, second connection terminal 23b, and V-phase output terminal 24b are provided on either side of unit storage section 21f. First connection terminal 22c, second connection terminal 23c, and W-phase output terminal 24c are provided on either side of unit storage section 21g.

[0029] In addition, in a plan view, control terminals 25a and 25b are provided between the unit storage sections 21e, 21f, and 21g on the front surface of the outer frame 21 and the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c. The control terminals 25a and 25b are provided for each of the unit storage sections 21e, 21f, and 21g.

[0030] The outer frame 21 includes first connection terminals 22a, 22b, and 22c, second connection terminals 23a, 23b, and 23c, U-phase output terminal 24a, V-phase output terminal 24b, W-phase output terminal 24c, and control terminals 25a and 25b, and is integrally formed by injection molding using a thermoplastic resin, thereby forming the case 20. The thermoplastic resin may be, for example, polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin.

[0031] The first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b are made of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or an alloy containing at least one of these as a main component. The surfaces of the first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b may be plated. Examples of plating materials used in this case include nickel, nickel-phosphorus alloys, and nickel-boron alloys. The plated first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, U-phase output terminal 24a, V-phase output terminal 24b, W-phase output terminal 24c, and control terminals 25a, 25b have improved corrosion resistance.

[0032] In the following description, when there is no need to distinguish between the first connection terminals 22a, 22b, and 22c, they will be referred to as "first connection terminals 22." Similarly, the second connection terminals 23a, 23b, and 23c will be referred to as "second connection terminals 23," and the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c will be referred to as "output terminals 24."

[0033] The sealing material that seals the semiconductor units 10a, 10b, and 10c may be a thermosetting resin. Examples of the thermosetting resin include epoxy resin, phenol resin, maleimide resin, and polyester resin. Epoxy resin is preferable. Furthermore, a filler may be added to the sealing material. The filler may be ceramics that are insulating and have high thermal conductivity. Alternatively, the sealing material may be a gel, such as a silicone gel.

[0034] The cooling device 3 includes an inlet 33a through which a refrigerant flows into the interior and an outlet 33b through which the refrigerant that has circulated inside flows out to the outside. The cooling device 3 cools the semiconductor unit 10 by dissipating heat from the semiconductor unit 10 via the refrigerant. Examples of the refrigerant used here include water, antifreeze (aqueous ethylene glycol solution), and long-life coolant. The cooling device 3 may also include a pump and a heat dissipation device (radiator). The pump introduces the refrigerant into the inlet 33a of the cooling device 3 and circulates the refrigerant by causing the refrigerant that flows out from the outlet 33b to flow back into the inlet 33a. The heat dissipation device receives the refrigerant that flows out of the cooling device 3 and dissipates the heat of the refrigerant, which has conducted heat from the semiconductor unit 10, to the outside.

[0035] The cooling device 3 has a top plate 31, a side wall 32 connected in an annular shape to the back surface of the top plate 31, and a cooled bottom plate 33 facing the top plate 31 and connected to the back surface of the side wall 32. The top plate 31 has a rectangular shape surrounded on all four sides by long and short sides in a plan view. The corners of the top plate 31 may be rounded in a plan view. The semiconductor units 10a, 10b, and 10c are joined to the front surface of the top plate 31 along the ±X directions. The side wall 32 is formed in an annular shape continuously on the back surface of the top plate 31. The cooled bottom plate 33 has a flat plate shape and has the same shape as the top plate 31 in a plan view. The corners of the cooled bottom plate 33 may also be rounded.

[0036] A plurality of heat dissipation fins (not shown) are formed on the back surface of the top plate 31. Each heat dissipation fin is, for example, a flat plate parallel to the XZ plane and arranged in parallel in the Y direction. In addition, an inlet 33a and an outlet 33b through which the refrigerant flows in and out are formed on the bottom surface of the cooling bottom plate 33. Water distribution heads are attached to the inlet 33a and the outlet 33b via annular rubber packings in sealing areas surrounding the inlet 33a and the outlet 33b. A water distribution pipe connected to a pump is attached to the water distribution head.

[0037] Next, the semiconductor unit 10 will be described with reference to FIGS. 3 and 4. FIG. 3 is a plan view of the semiconductor unit according to the embodiment. FIG. 4 is a cross-sectional view of the semiconductor unit according to the embodiment. Note that FIG. 3 shows a case where a first connection terminal 22, a second connection terminal 23, and an output terminal 24 are connected to the semiconductor unit 10. Also, FIG. 4 shows a cross-sectional view of the semiconductor unit 10 taken along line I1-I1 in FIG. 3.

[0038] The semiconductor unit 10 includes an insulating substrate 11, semiconductor chips 12a and 12b, and lead frames 13a and 13b. The semiconductor chips 12a and 12b are bonded to the insulating substrate 11 via bonding members. The lead frames 13a and 13b are bonded to the semiconductor chips 12a and 12b, respectively, via bonding members. The bonding members and bonding members 14a, 14b, and 14d described below are, for example, solder. Lead-free solder is used as the solder. Lead-free solder is primarily composed of an alloy containing at least two of tin, silver, copper, zinc, antimony, indium, and bismuth. The solder may further contain additives, such as nickel, germanium, cobalt, or silicon. The addition of additives to the solder improves wettability, gloss, and bonding strength, thereby improving reliability.

[0039] The insulating substrate 11 includes an insulating plate 11a, wiring plates 11b1, 11b2, and 11b3, and a metal plate 11c. The insulating plate 11a and the metal plate 11c are rectangular in plan view. The corners of the insulating plate 11a and the metal plate 11c may be round-chamfered or C-chamfered. The size of the metal plate 11c is smaller than the size of the insulating plate 11a in plan view, and it is formed inside the insulating plate 11a.

[0040] The insulating plate 11a is made of a material that has insulating properties and excellent thermal conductivity. Such insulating plate 11a may be made of ceramics or insulating resin. Examples of ceramics include aluminum oxide, aluminum nitride, silicon nitride, and silicon nitride. Examples of insulating resins include paper phenol substrates, paper epoxy substrates, glass composite substrates, and glass epoxy substrates.

[0041] Wiring boards 11b1, 11b2, and 11b3 are formed on the front surface of insulating board 11a. Wiring boards 11b1, 11b2, and 11b3 are made of a metal containing copper and having excellent conductivity. Such a metal may be, for example, an alloy containing aluminum in addition to copper.

[0042] Wiring board 11b2 occupies approximately half of the area on the +X side of the front surface of insulating board 11a, extending from the -Y side to the +Y side. Wiring board 11b1 occupies approximately half of the area on the -X side of the front surface of insulating board 11a. Wiring board 11b3 occupies the area on the front surface of insulating board 11a surrounded by wiring boards 11b1 and 11b2.

[0043] Such wiring boards 11b1, 11b2, and 11b3 are formed on the front surface of insulating plate 11a as follows. A metal plate is formed on the front surface of insulating plate 11a, and then etching or other processes are performed on this metal plate to obtain wiring boards 11b1, 11b2, and 11b3 of a predetermined shape. Alternatively, wiring boards 11b1, 11b2, and 11b3 may be pre-cut from a metal plate and then pressure-bonded to the front surface of insulating plate 11a. Note that wiring boards 11b1, 11b2, and 11b3 are merely examples. The number, shape, size, and position of the wiring boards may be selected as needed.

[0044] The metal plate 11c is formed on the back surface of the insulating plate 11a. The metal plate 11c is rectangular. The area of ​​the metal plate 11c in a plan view is smaller than that of the insulating plate 11a and larger than the area of ​​the region where the wiring plates 11b1, 11b2, and 11b3 are formed. The corners of the metal plate 11c may be round-chamfered or C-chamfered. For example, the metal plate 11c is formed on the entire surface of the insulating plate 11a except for the edges. The metal plate 11c is mainly composed of a metal with excellent thermal conductivity. The metal is, for example, copper, aluminum, or an alloy containing at least one of these.

[0045] As the insulating substrate 11 having such a configuration, if the insulating plate 11a is made of ceramics, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate may be used. If the insulating plate 11a is made of insulating resin, a resin insulating substrate may be used. The insulating substrate 11 may be attached to the front surface of the top plate 31 of the cooling device 3 via a bonding member (not shown). Heat generated in the semiconductor chips 12a and 12b can be conducted to the cooling device 3 via the wiring boards 11b1 and 11b2, the insulating plate 11a, and the metal plate 11c, and dissipated.

[0046] The semiconductor chips 12a and 12b include power device elements made of silicon. The power device elements are reverse-conducting (RC)-insulated gate bipolar transistors (IGBTs). The RC-IGBTs combine the functions of an IGBT, which is a switching element, and a free-wheeling diode (FWD).

[0047] The front surface of the semiconductor chip 12a is rectangular in plan view and includes a gate electrode 12a1 and an emitter electrode 12a2 (output electrode) serving as a main electrode. In this example, the gate electrode 12a1 is provided on one short side of the front surface of the semiconductor chip 12a. The gate electrode 12a1 is connected to a control terminal 25a via a wire 26a. The emitter electrode 12a2 is provided on the other short side of the front surface of the semiconductor chip 12a. The back surface of the semiconductor chip 12a includes a collector electrode 12a3 (input electrode) serving as a main electrode. The collector electrode 12a3 is joined to the wiring board 11b1 via a joining member 14b.

[0048] Semiconductor chip 12b has a similar configuration to semiconductor chip 12a, with gate electrode 12b1 and emitter electrode 12b2 provided on the front surface of semiconductor chip 12b, and a collector electrode (not shown) provided on the back surface of semiconductor chip 12b. Gate electrode 12b1 is connected to control terminal 25b via wire 26b (see FIG. 1). The collector electrode is bonded to wiring board 11b2 via a bonding member (not shown).

[0049] As will be described in more detail later, the bonding member 14b that bonds the collector electrode 12a3 of the semiconductor chip 12a to the wiring board 11b1, and the bonding member that bonds the collector electrode of the semiconductor chip 12b to the wiring board 11b2, each contain a conductive spherical support member 14c.

[0050] The wires 26a, 26b are primarily made of a highly conductive material, such as gold, copper, aluminum, or an alloy containing at least one of these metals. Preferably, the wires 26a, 26b are an aluminum alloy containing a trace amount of silicon.

[0051] The semiconductor chips 12a and 12b may each include a pair of a switching element and a diode element instead of the RC-IGBT. The switching element is, for example, an IGBT or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Such semiconductor chips 12a and 12b each include, for example, an input electrode (drain electrode or collector electrode) as a main electrode on the back surface, and a control electrode (gate electrode) and an output electrode (source electrode or emitter electrode) as a main electrode on the front surface. The diode element is, for example, an SBD (Schottky Barrier Diode) or a PiN (P-intrinsic-N) diode, which are used as FWDs. Such semiconductor chips 12a and 12b each include an output electrode (cathode electrode) as a main electrode on the back surface, and an input electrode (anode electrode) as a main electrode on the front surface.

[0052] The semiconductor chips 12a and 12b may include switching elements made of power MOSFETs primarily composed of silicon carbide. In this case, the semiconductor chips 12a and 12b include FWDs as well as power MOSFETs. The semiconductor chips 12a and 12b each include a control electrode (gate electrode) and a main output electrode (source electrode) on their front surfaces. The semiconductor chips 12a and 12b also include a main input electrode (drain electrode) on their back surfaces.

[0053] Lead frame 13a connects emitter electrode 12a2 on the front surface of semiconductor chip 12a to wiring board 11b3. Second connection terminal 23 is connected to wiring board 11b3. Meanwhile, lead frame 13b connects emitter electrode 12b2 on the front surface of semiconductor chip 12b to wiring board 11b1. Output terminal 24 is connected to wiring board 11b1, and first connection terminal 22 is connected to wiring board 11b2.

[0054] With the above configuration, semiconductor unit 10 forms a one-phase inverter circuit. Wiring board 11b2, semiconductor chip 12b, lead frame 13b, and wiring board 11b1 form an upper arm of a half-bridge circuit. Wiring board 11b1, semiconductor chip 12a, lead frame 13a, and wiring board 11b3 form a lower arm of the half-bridge circuit. Output terminal 24 connected to wiring board 11b1 serves as the M terminal, which constitutes the output terminal of the half-bridge circuit. First connection terminal 22 connected to wiring board 11b2 serves as the P terminal, which constitutes the positive input terminal of the half-bridge circuit, and second connection terminal 23 connected to wiring board 11b3 serves as the N terminal, which constitutes the negative output terminal of the half-bridge circuit. The switching operations of semiconductor chips 12a and 12b are controlled in response to control signals input from control terminals 25a and 25b to gate electrodes 12a1 and 12b1.

[0055] The lead frames 13a and 13b integrally include main electrode joints 13a1 and 13b1, first vertical linkages 13a2 and 13b2, horizontal linkages 13a3 and 13b3, second vertical linkages 13a4 and 13b4, and wiring joints 13a5 and 13b5. The lead frames 13a and 13b have the same overall thickness and are flat. The lead frames 13a and 13b may be configured by bending the above-mentioned portions.

[0056] The lead frames 13a and 13b are made of a copper-containing metal with excellent conductivity. Such a metal may be, for example, an alloy containing aluminum in addition to copper. Furthermore, to improve corrosion resistance, the surfaces of the lead frames 13a and 13b may be plated. Examples of plating materials used in this case include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0057] The main electrode bonding portions 13a1 and 13b1 are flat. The main electrode bonding portions 13a1 and 13b1 are bonded to the emitter electrodes 12a2 and 12b2 of the semiconductor chips 12a and 12b via bonding members. For example, as shown in FIG. 4, the main electrode bonding portion 13a1 is bonded to the emitter electrode 12a2 via a bonding member 14a. The main electrode bonding portions 13a1 and 13b1 have a rectangular shape in plan view, similar to the emitter electrodes 12a2 and 12b2. The main electrode bonding portions 13a1 and 13b1 may each have a boss (not shown) formed on the surface facing the semiconductor chips 12a and 12b.

[0058] The first vertical linkages 13a2 and 13b2 have their lower ends integrally connected to the ends of the main electrode junctions 13a1 and 13b1, and their upper ends extending vertically upward (in the +Z direction) relative to the main electrode junctions 13a1 and 13b1. The first vertical linkage 13a2 is joined to the end of the main electrode junction 13a1 joined to the semiconductor chip 12a on the wiring board 11b3 (-Y direction) side. The first vertical linkage 13b2 is joined to the end of the main electrode junction 13b1 joined to the semiconductor chip 12b on the wiring board 11b1 (-X direction) side.

[0059] The horizontal linking portions 13a3 and 13b3 are integrally connected to the upper ends of the first vertical linking portions 13a2 and 13b2 and extend to the wiring boards 11b3 and 11b1, respectively. The horizontal linking portions 13a3 and 13b3 are flat. The horizontal linking portions 13a3 and 13b3 extend in the ±Y direction and the ±X direction, respectively. The horizontal linking portions 13a3 and 13b3 may have one end and the other end misaligned. In this case, the horizontal linking portions 13a3 and 13b3 span the gaps between the wiring boards 11b1 and 11b3 and the wiring boards 11b1 and 11b2. The horizontal linking portions 13a3 and 13b3 are parallel to the insulating substrate 11. The horizontal linking portions 13a3 and 13b3 may be at the same height. In this way, the heights of the first vertical linkages 13a2, 13b2 and the second vertical linkages 13a4, 13b4 are appropriately selected so that the horizontal linkages 13a3, 13b3 are formed.

[0060] The upper ends of second vertical linkages 13a4 and 13b4 are integrally connected to the ends of horizontal linkages 13a3 and 13b3, and their lower ends extend vertically downward (in the -Z direction) and are integrally connected to wiring joints 13a5 and 13b5. Wiring joints 13a5 and 13b5 are joined to wiring boards 11b3 and 11b1, respectively, via joining members, and are integrally connected to the lower ends of second vertical linkages 13a4 and 13b4.

[0061] As shown in FIG. 4, bonding member 14b, which bonds the underside of semiconductor chip 12a to the upper surface of wiring board 11b1, includes conductive support member 14c. Support member 14c is made of a conductive material with a higher melting point than bonding member 14b. Examples of such conductive materials include nickel. Support member 14c may be spherical, sometimes referred to as a "solder ball." Contacting the upper end of support member 14c with the underside of semiconductor chip 12a and the lower end of support member 14c with the upper surface of wiring board 11b1 allows for a constant distance between the underside of semiconductor chip 12a and the upper surface of wiring board 11b1. Note that the "spherical" shape in this case does not necessarily have to be a perfect sphere; the lengths of the semi-axes of support member 14c in the X, Y, and Z directions from the center of support member 14c may be different.

[0062] Furthermore, on the upper surface of wiring board 11b1, there is formed restricting portion 11d that contacts support member 14c and restricts movement of support member 14c so that support member 14c remains below semiconductor chip 12a. That is, on the upper surface, there is formed restricting portion 11d that restricts movement of support member 14c so that semiconductor chip 12a and support member 14c overlap in plan view. The shape and position of restricting portion 11d will be described later.

[0063] The bonding member that bonds the lower surface of semiconductor chip 12b to the upper surface of wiring board 11b2 also includes support member 14c similar to the above, and restricting portion 11d that restricts movement of support member 14c so that support member 14c remains below semiconductor chip 12b is also formed on the upper surface of wiring board 11b2. The following mainly describes the bonding member, support member 14c, and restricting portion 11d between the lower surface of semiconductor chip 12a and the upper surface of wiring board 11b1, but the same applies to the bonding member, support member 14c, and restricting portion 11d between the lower surface of semiconductor chip 12b and the upper surface of wiring board 11b2.

[0064] Fig. 5 is a cross-sectional view of a first comparative example of a semiconductor unit. Fig. 5 shows a comparative example in which a bonding member 14d that does not include a support member 14c is used to bond the lower surface of semiconductor chip 12a to the upper surface of wiring board 11b1, and no restricting portion 11d is formed on the upper surface of wiring board 11b1. Fig. 5 corresponds to an enlarged view of the area near semiconductor chip 12a in the cross-sectional view of Fig. 4.

[0065] In the semiconductor unit 10, heating during manufacturing may cause warping of the insulating substrate 11. Such warping may cause the upper surfaces of the wiring boards 11b1 and 11b2 on which the semiconductor chips 12a and 12b are arranged to be inclined. In addition to such warping, the upper surfaces of the wiring boards 11b1 and 11b2 may also be inclined due to, for example, poor positioning accuracy of a jig that holds each component during manufacturing.

[0066] 5, for example, the upper surface of wiring board 11b1 is inclined downward in the -Y direction. When semiconductor chip 12a is bonded to such an inclined surface of wiring board 11b1 via bonding member 14d, if bonding member 14d melts due to heating, semiconductor chip 12a also inclines downward in the -Y direction. The downward inclination angle of semiconductor chip 12a with respect to the horizontal plane (XY plane) is greater than the downward inclination angle of wiring board 11b1. Therefore, thickness D1 of the portion of bonding member 14d located on the -Y direction side is thinner than thickness D2 of the portion located on the +Y direction side, resulting in an uneven thickness of bonding member 14d.

[0067] When the bonding member 14d hardens while its thickness is uneven, external stress can easily cause cracks to form in the thinner portions of the bonding member 14d, and the cracks can easily propagate. Furthermore, the thicker portions of the bonding member 14d have poorer heat dissipation than the thinner portions. The inclusion of the bonding member 14d with an uneven thickness can lead to a decrease in the reliability of the semiconductor device 1.

[0068] Fig. 6 is a cross-sectional view of a second comparative example of a semiconductor unit. The second comparative example differs from the first comparative example in that a bonding member 14b including a support member 14c is used to bond the lower surface of semiconductor chip 12a to the upper surface of wiring board 11b1. Note that Fig. 6, like Fig. 5, corresponds to an enlarged view of the area near semiconductor chip 12a in the cross-sectional view of Fig. 4.

[0069] When bonding member 14b containing support member 14c is used, as described above, the upper end of support member 14c contacts the lower surface of semiconductor chip 12a, and the lower end of support member 14c contacts the upper surface of wiring board 11b1, thereby maintaining a constant distance between the lower surface of semiconductor chip 12a and the upper surface of wiring board 11b1 and making the thickness of bonding member 14b uniform. Note that support member 14c is dispersed throughout bonding member 14b.

[0070] However, if the top surface of wiring board 11b1 is inclined, there is a possibility that support member 14c will move along the inclination when bonding member 14b is melted. As a result, support member 14c will be biased toward the lower side of the inclined surface below semiconductor chip 12a, and may leak out from directly below semiconductor chip 12a in this direction. For example, if the top surface of wiring board 11b1 is inclined downward in the -Y direction as shown in Figure 5, support member 14c may leak out from directly below semiconductor chip 12a in the -Y direction, which may result in an inconsistent thickness of bonding member 14b.

[0071] In response to this problem, in this embodiment, as shown in Fig. 4, restricting portions 11d are formed on the upper surface of wiring board 11b1 to contact support member 14c and restrict movement of support member 14c so that support member 14c remains below semiconductor chip 12a. That is, restricting portions 11d are formed on the upper surface to restrict movement of support member 14c so that semiconductor chip 12a and support member 14c overlap in a plan view. Examples of the shape and position of restricting portion 11d are described below.

[0072] FIG. 7 shows a plan view and a cross-sectional view of a first example of a restricting portion. The plan view of FIG. 7 is an enlarged view of region A shown in FIG. 3 on the upper surface of wiring board 11b1. In this plan view, the region on wiring board 11b1 facing the lower surface region of semiconductor chip 12a is shown as chip lower surface region 15a by a dashed rectangle. This also applies to the plan views shown in FIGS. 9 to 13, 15, and 17. The cross-sectional view of FIG. 7 shows the region of the plan view of FIG. 7 cut along line I2-I2.

[0073] 7, the restricting portion 11d has a convex shape extending (protruding) from the upper surface of the wiring board 11b1 in a direction toward the semiconductor chip 12a. In the case of such a shape, the support member 14c abuts against the side portion of the convex restricting portion 11d, thereby restricting the movement of the support member 14c.

[0074] Restriction portion 11d having the above shape is formed, for example, by the following procedure. First, wiring board 11b1 having a flat upper surface is formed on the upper surface of insulating plate 11a. Next, a region of the upper surface of wiring board 11b1 excluding the position of restriction portion 11d is pressed using a mold or the like to form convex restriction portion 11d. Alternatively, convex restriction portion 11d may be formed by cutting the region of the upper surface of wiring board 11b1 excluding the position of restriction portion 11d using a laser or the like. Furthermore, convex restriction portion 11d may be formed simultaneously with wiring board 11b1 by etching a metal plate formed on the front surface of insulating plate 11a.

[0075] In the first example, the restricting portion 11d is formed on the outer edge of the chip undersurface region 15a on the upper surface of the wiring board 11b1. This reduces the possibility that the support member 14c in the bonding member 14b will move from the inside to the outside of the chip undersurface region 15a and leak out of the chip undersurface region 15a. That is, the movement of the support member 14c is restricted by the restricting portion 11d, so the support member 14c can be kept within the chip undersurface region 15a. Therefore, the semiconductor chip 12a is aligned substantially parallel to the chip undersurface region 15a on the wiring board 11b1 by the support member 14c, and the thickness of the bonding member 14b below the semiconductor chip 12a can be maintained at a constant level or more and made uniform. As a result, cracks can be prevented from occurring in the hardened bonding member 14b, and localized deterioration of the heat dissipation performance of the bonding member 14b can be prevented, thereby improving the reliability of the semiconductor device 1.

[0076] Furthermore, the restricting portions 11d are formed at the corner positions of the rectangular chip lower surface area 15a, more specifically, the restricting portions 11d are formed at the four corner positions of the rectangular chip lower surface area 15a, respectively. As a result, the corners of the semiconductor chip 12a are supported by the support members 14c, so that the semiconductor chip 12a can more stably maintain an attitude approximately parallel to the chip lower surface area 15a.

[0077] It is preferable that the heights of the restricting portions 11d formed at the four corners are approximately equal, but the heights of the restricting portions 11d may be different. This height may be a height that can restrict the movement of the support member 14c. The relationship between the diameter of the support member 14c and the height of the restricting portions 11d will be described later. The shape of the restricting portions 11d in a plan view may be rectangular (square or oblong), circular, or elliptical. Alternatively, the restricting portions 11d may be rectangular or trapezoidal in a side view. It is also preferable that the size of the restricting portions 11d in a plan view is sufficiently larger than the diameter of the support member 14c, for example.

[0078] Fig. 8 is an enlarged cross-sectional view of a region including the restricting portion. Fig. 8 shows an enlarged view of the peripheral region of restricting portion 11d formed on the -Y side of restricting portion 11d shown in the cross-sectional view of Fig. 7. However, Fig. 8 does not show bonding member 14a and lead frame 13a on the top surface of semiconductor chip 12a.

[0079] 8, similar to FIG. 5, shows a state in which the top surface of wiring board 11b1 is tilted downward in the -Y direction from the +Y direction toward the -Z direction. In this state, if bonding member 14b melts, support member 14c may move in the -Y direction along the slope. However, the movement of support member 14c is restricted by contact with restricting portion 11d, which reduces the possibility of support member 14c leaking out from directly below semiconductor chip 12a to the outside (the -Y direction). In other words, because the movement of support member 14c is restricted by restricting portion 11d, support member 14c can be kept inside chip undersurface region 15a.

[0080] Furthermore, by forming restricting portion 11d on the outer edge of chip undersurface region 15a, it becomes more likely that support member 14c can be positioned near the lower end of the inclined surface of chip undersurface region 15a. Therefore, the outer edge of semiconductor chip 12a is supported by support member 14c, and the undersurface of semiconductor chip 12a becomes approximately parallel to chip undersurface region 15a on wiring board 11b1. This reduces the possibility that the inclination angle of the undersurface of semiconductor chip 12a with respect to the horizontal plane (XY plane) becomes larger than the inclination angle of the upper surface of wiring board 11b1, and the thickness of the portion of bonding member 14b located on the -Y direction side (corresponding to thickness D1 in FIG. 5) becomes thinner than the thickness of the portion located on the +Y direction side (corresponding to thickness D2 in FIG. 5).

[0081] Fig. 9 is a plan view of a second example of the restriction portion. In the second example shown in Fig. 9, restriction portion 11d has a curved shape that is convex in a direction from the center of chip undersurface region 15a toward its outer edge in a plan view. More specifically, in Fig. 9, restriction portion 11d is formed at each corner position (positions of the four corners) of rectangular chip undersurface region 15a, and has a curved shape that is concave toward the center of chip undersurface region 15a and convex toward the corresponding vertex of chip undersurface region 15a.

[0082] In Fig. 9, the bent shape is an L-shape having portions extending from a corner in two directions perpendicular to each other. The bent shape may be a right angle (90°) as shown in Fig. 9, or may be at an angle somewhat greater than 90°. Alternatively, the inner corner of the bent shape may form an R-surface or a C-surface.

[0083] The shape and position of the restricting portion 11d reduce the possibility of the support member 14c in the bonding member 14b moving from the inside to the outside of the chip undersurface region 15a and leaking out. This makes it possible to maintain a uniform thickness of the bonding member 14b below the semiconductor chip 12a. Furthermore, the restricting portion 11d has a curved shape that is convex from the center of the chip undersurface region 15a toward its outer edge in a plan view, allowing the support member 14c to be accommodated in the curved portion. This makes it possible to more reliably restrict the movement of the support member 14c.

[0084] In the first and second examples, the restricting portions 11d are formed at the four corners of the chip lower surface area 15a, which reduces the possibility that the support members 14c will move from the inside to the outside of the chip lower surface area 15a and leak, regardless of the direction in which the wiring board 11b1 is tilted. In contrast, an example of the shape and position of the restricting portions 11d that is suitable for cases in which the tilt direction of the wiring board 11b1 can be predicted is shown in the following Figure 10.

[0085] FIG. 10 is a plan view of a third example of the restricting portion. In the third example shown in FIG. 10, restricting portion 11d is disposed on the upper surface of wiring board 11b1 at an edge along one side of chip lower surface region 15a, extending in a direction along that side. For example, if wiring board 11b1 is predicted to tilt downward toward a specific side of chip lower surface region 15a, restricting portion 11d can be disposed on the edge along that side, extending in a direction along that side. This reduces the possibility that support member 14c will move along the tilt and leak outside chip lower surface region 15a if tilting actually occurs. Furthermore, because support member 14c can be fastened between adjacent corners of chip lower surface region 15a, the side of semiconductor chip 12a on which restricting portion 11d is disposed is supported by support member 14c, making it possible to maintain a uniform thickness of bonding member 14b.

[0086] 10, restricting portions 11d extending along the edges of opposing sides of chip underside region 15a are formed. This example is for a case where the underside of wiring board 11b1 is expected to be tilted downward in the +Y direction or the −Y direction (the direction of arrow AR1).

[0087] 10 has a shape that extends linearly in a plan view. The side surface of this restricting portion 11d (when viewed in the ±X direction) may be rectangular, trapezoidal in shape with the upper base shorter than the lower base, or substantially triangular.

[0088] 10, if the restricting portion 11d has a linear extension, gas generated when the bonding member 14b melts is difficult to exhaust from the region between the underside of the semiconductor chip 12a and the upper surface of the wiring board 11b1, which results in the problem that voids are likely to occur. Therefore, as shown in the following Figure 11, the restricting portions 11d may be arranged at intervals along the sides of the chip underside region 15a.

[0089] FIG. 11 is a plan view of a fourth example of the restricting portion. In the fourth example shown in FIG. 11, a plurality of restricting portions 11d are formed at the edges along opposing sides of the chip underside region 15a, spaced apart by a distance 11e in the direction along the sides. That is, a plurality of restricting portions 11d may be formed in a dashed line along the edges. Alternatively, the plurality of restricting portions 11d may be formed along the edges, shifted sequentially in the ±Y direction. This reduces the possibility of the support member 14c leaking from inside the chip underside region 15a in the direction of arrow AR1, and allows gas generated when the joining members 14b melt to be discharged to the outside through the distance 11e. As a result, the possibility of damage to the joining members 14b can be further reduced.

[0090] FIG. 12 is a plan view of a fifth example of the restricting portion. In the fifth example shown in FIG. 12, restricting portion 11d is arranged along the four edges of chip undersurface region 15a in the case shown in FIG. 9. However, as in FIG. 11, restricting portion 11d is arranged at intervals 11e in the direction along the four sides of chip undersurface region 15a. This reduces the possibility of support member 14c leaking from the inside to the outside of chip undersurface region 15a regardless of the direction in which wiring board 11b1 is tilted, and also allows gas generated when bonding member 14b melts to be discharged to the outside through interval 11e. As a result, the possibility of bonding member 14b being damaged can be further reduced.

[0091] FIG. 13 is a plan view of a sixth example of the restricting portion. In the sixth example shown in FIG. 13, a plurality of restricting portions 11d are formed and dispersed in the chip undersurface region 15a. As an example, in FIG. 13, a plurality of restricting portions 11d are formed in a staggered pattern in the chip undersurface region 15a. This allows the support members 14c in the bonding members 14b to be uniformly arranged in the chip undersurface region 15a, making it possible to uniformize the thickness of the bonding members 14b below the semiconductor chip 12a. As a result, cracks can be prevented from occurring in the bonding members 14b after hardening, and localized deterioration in the heat dissipation performance of the bonding members 14b can also be prevented, thereby improving the reliability of the semiconductor device 1.

[0092] The shape of the restricting portion 11d in a plan view may be rectangular. For example, if the chip undersurface region 15a is inclined as described in FIG. 10, it is desirable to form the restricting portion 11d so that its longitudinal side faces the inclination direction. This ensures that, when an inclination actually occurs, the support member 14c moving along the inclination can be reliably restricted.

[0093] FIG. 14 is a cross-sectional view showing the positional relationship between the convex restricting portion and the semiconductor chip. First, the height Db of the convex restricting portion 11d will be described. If the height Db of the restricting portion 11d from the upper surface of the wiring board 11b1 of the insulating substrate 11 is too low, the force restricting the movement of the support member 14c will be weak, while if it is too high, the fluidity of the bonding member 14b will decrease. For this reason, the height Db of the restricting portion 11d is preferably about 1 / 3 or more and 1 / 2 or less of the diameter Da of the spherical support member 14c. The diameter Da of the support member 14c is about several tens to several hundreds of μm.

[0094] Next, the positional relationship between the side end surface 12a4 of the semiconductor chip 12a and the side end portion 11d1 of the restricting portion 11d relative to the inside of the semiconductor chip 12a will be described. Here, the side surface of the semiconductor chip 12a on the -Y direction side is the side end surface 12a4, and the rising portion of the restricting portion 11d on the +Y direction side is the side end portion 11d1.

[0095] When the upper surface of the wiring board 11b1 of the insulating substrate 11 is horizontal, and the uppermost point 14c1 of the support member 14c remains directly below the semiconductor chip 12a, the restricting portion 11d may be formed so that the side end 11d1 of the support member 14c is positioned outward (in the -Y direction) from the side end surface 12a4 of the semiconductor chip 12a, as shown in Fig. 14. That is, when the uppermost point 14c1 of the support member 14c overlaps with the semiconductor chip 12a in a plan view, the restricting portion 11d may be formed so that the side end 11d1 of the support member 14c is positioned outward (in the -Y direction) from the side end surface 12a4 of the semiconductor chip 12a. This allows the end of the semiconductor chip 12a to be supported by the support member 14c, and the semiconductor chip 12a can maintain an orientation approximately parallel to the chip undersurface region 15a. As a result, the thickness of the bonding member 14b can be maintained at a certain level and made uniform.

[0096] The maximum value of gap D3 of side end 11d1 of restriction portion 11d from the side end surface 12a4 of semiconductor chip 12a to the outside is when height Db of restriction portion 11d is 1 / 2 the diameter Da of support member 14c, as shown in Figure 14, and gap D3 at that time is Da / 2. If height Db of restriction portion 11d is smaller than 1 / 2 the diameter Da of support member 14c, the outermost point (negative Y direction side) of spherical support member 14c may be located outside side end 11d1 of restriction portion 11d, and gap D3 becomes smaller than Da / 2. As height Db of restriction portion 11d becomes smaller than Da / 2, gap D3 also becomes smaller.

[0097] Fig. 15 shows a plan view and a cross-sectional view of a seventh example of the restriction portion, in which the cross-sectional view of Fig. 15 is taken along line I3-I3 in the plan view of Fig. 15.

[0098] 15, restricting portion 11d has a concave shape recessed in a direction from the upper surface of wiring board 11b1 toward insulating plate 11a (-Z direction). In the case of such a shape, the lower part of support member 14c fits into concave restricting portion 11d, thereby restricting movement of support member 14c.

[0099] Restriction portion 11d having the above shape is formed, for example, by the following procedure. First, wiring board 11b1 having a flat upper surface is formed on the upper surface of insulating plate 11a. Next, a region of the upper surface of wiring board 11b1 where restriction portion 11d is to be formed is pressed using a mold or the like to form recessed restriction portion 11d. Alternatively, recessed restriction portion 11d may be formed by cutting the region of the upper surface of wiring board 11b1 where restriction portion 11d is to be formed using a laser or the like. Alternatively, recessed restriction portion 11d may be formed simultaneously with wiring board 11b1 by etching a metal plate formed on the front surface of insulating plate 11a.

[0100] 15, recessed restriction portions 11d are formed on the outer edge of chip lower surface region 15a on the upper surface of wiring board 11b1, similar to the first example shown in FIG. 7. More specifically, restriction portions 11d are formed at the corner positions (four corner positions) of rectangular chip lower surface region 15a. However, the position of recessed restriction portions 11d and the shape of the recess in plan view may be the position and shape shown in FIGS. 9 to 13. Alternatively, recessed restriction portions 11d may be formed as grooves in chip lower surface region 15a at predetermined intervals.

[0101] FIG. 16 is a cross-sectional view showing the positional relationship between the recessed restricting portion and the semiconductor chip. First, we will explain the depth Dc of the recessed restricting portion 11d. If the depth Dc of the restricting portion 11d from the upper surface of the wiring board 11b1 of the insulating substrate 11 is too shallow, the force restricting the movement of the support member 14c will be weak, while if it is too deep, the distance between the lower surface of the semiconductor chip 12a and the upper surface of the wiring board 11b1 (i.e., the thickness of the bonding member 14b) will be small. For this reason, it is desirable that the depth Dc of the restricting portion 11d be approximately 1 / 3 or more and 1 / 2 or less of the diameter Da of the spherical support member 14c.

[0102] Next, the positional relationship between the side end surface 12a4 of the semiconductor chip 12a and the side end portion 11d2 of the restricting portion 11d relative to the outside of the semiconductor chip 12a will be described. Here, the side surface on the -Y direction side of the semiconductor chip 12a is the side end surface 12a4, and the rising portion on the -Y direction side of the restricting portion 11d is the side end portion 11d2.

[0103] When the upper surface of the wiring board 11b1 of the insulating substrate 11 is horizontal, if the uppermost point 14c1 of the support member 14c remains directly below the semiconductor chip 12a, the restricting portion 11d may be formed so that the side end portion 11d2 of the support member 14c is positioned outside (towards the -Y direction) the side end surface 12a4 of the semiconductor chip 12a, as shown in FIG. 16.

[0104] The maximum value of gap D4 of side end 11d2 of restriction portion 11d from the side end surface 12a4 of semiconductor chip 12a to the outside is when depth Dc of restriction portion 11d is 1 / 2 the diameter Da of support member 14c, as shown in Figure 16, and gap D4 at that time is Da / 2. If depth Dc of restriction portion 11d is smaller than 1 / 2 the diameter Da of support member 14c, the outermost point (negative Y direction side) of spherical support member 14c may be located outside side end 11d2 of restriction portion 11d, and gap D4 becomes smaller than Da / 2. As depth Dc of restriction portion 11d becomes smaller than Da / 2, gap D4 also becomes smaller.

[0105] FIG. 17 is a plan view of an eighth example of the restricting portion. In the eighth example shown in FIG. 17, restricting portion 11d is a roughened region in which the upper surface of wiring board 11b1 is roughened. With this shape, the movement of support member 14c is restricted by frictional resistance between the lower part of support member 14c and the roughened upper surface of restricting portion 11d. Furthermore, the roughening treatment of the upper surface of wiring board 11b1 may be performed by, for example, laser, blasting, shot peening, or roughening plating.

[0106] The position and shape of the roughened restricting portion 11d in plan view may be the positions and shapes shown in FIGS. 7 and 9 to 13. Alternatively, as shown in FIG. 17, the roughened restricting portion 11d may be formed over substantially the entire chip undersurface region 15a of the wiring board 11b1. In FIG. 17, the roughened region is indicated by hatching. In this case, the arithmetic mean roughness may be any value that is sufficient to restrict the movement of the support member 14c.

[0107] The support members 14c are dispersed within the bonding members 14b. When such bonding members 14b are provided on the wiring board 11b1, the support members 14c are also dispersed in the chip undersurface region 15a. If the entire chip undersurface region 15a is roughened as shown in FIG. 17, the support members 14c are more likely to remain in their dispersed positions. Even if the insulating substrate 11 warps and the wiring board 11b1 tilts, the support members 14c are likely to be restricted from moving in their original positions. Therefore, even if the insulating substrate 11 warps, the support members 14c are dispersed in the chip undersurface region 15a, which prevents a decrease in the uniformity of heat dissipation on the back surface (collector electrode 12a3 side) of the semiconductor chip 12a. Furthermore, the thickness between the semiconductor chip 12a and the chip undersurface region 15a is more reliably maintained.

[0108] Furthermore, such a roughened restricting portion 11d may be further combined with the case of Figures 7 and 9 to 13. In this case, movement of the support member 14c that is not restricted by the roughened restricting portion 11d can be restricted by the restricting portion 11d of Figures 7 and 9 to 13. Therefore, by including the restricting portion 11d of Figures 7 and 9 to 13, leakage from directly below the semiconductor chip 12a of the support member 14c can be more reliably prevented.

[0109] Fig. 18 is a side view of a warped semiconductor unit. Similar to Fig. 4, Fig. 18 shows a side view of the warped semiconductor unit 10 when viewed in the +X direction. Note that Fig. 18 shows the warpage of the insulating substrate 11 in a schematic manner, and the angle of the warpage is exaggerated from the actual angle.

[0110] As described above, in semiconductor unit 10, heating during manufacturing may cause warping of insulating substrate 11. Such warping may cause the upper surfaces, including chip undersurface regions 15a and 15b, of wiring boards 11b1 and 11b2 on which semiconductor chips 12a and 12b are arranged to become inclined. The state of warping of insulating substrate 11 depends, for example, on the volumes and formation positions of wiring boards 11b1, 11b2, and 11b3 and metal plate 11c of insulating substrate 11, semiconductor chip 12, lead frames 13a and 13b, and heating temperature and time.

[0111] FIG. 18 shows an example of warpage occurring in insulating substrate 11. In the example of FIG. 18, apex 16a of the warpage occurs at a position on the -X side surface of insulating substrate 11 corresponding to the region between wiring board 11b1 and wiring board 11b3. In this case, insulating substrate 11 is warped so as to be convex downward (in the -Z direction) at apex 16a in a side view looking in the +X direction. Therefore, the top surface of wiring board 11b1 on which semiconductor chip 12a is disposed forms inclined surface 11f that is lowered toward the -Y direction. Furthermore, as shown in the following FIG. 19, the region of the top surface of wiring board 11b2 on the +Y direction side of apex 16a where semiconductor chip 12b is disposed also forms inclined surface 11f.

[0112] Fig. 19 is a plan view of a ninth example of a restricting portion. Fig. 19 shows a plan view of the semiconductor unit 10 with the semiconductor chips 12a and 12b and the lead frames 13a and 13b removed. Also, on the upper surface of the wiring board 11b1, a chip lower surface area 15a facing the lower surface area of ​​the semiconductor chip 12a is indicated by a dashed rectangle. Also, on the upper surface of the wiring board 11b2, a chip lower surface area 15b facing the lower surface area of ​​the semiconductor chip 12b is indicated by a dashed rectangle.

[0113] If the position of the warpage peak can be predicted, the direction of the inclination of the wiring board of insulating substrate 11 can also be predicted. In such a case, a restricting portion may be formed in the region of the inclined surface of the wiring board facing the underside of the semiconductor chip, on the side of the inclined surface where the height of the inclined surface is lower (the direction of arrow AR2). For example, if it is predicted that warpage peak 16a as shown in FIG. 18 will occur, it is predicted that the upper surface of wiring board 11b1 on which semiconductor chip 12a is mounted will become inclined surface 11f, which is lower in the -Y direction. Therefore, as shown in FIG. 19, a restricting portion 11d may be formed on the upper surface of wiring board 11b1 at the edge of chip underside region 15a corresponding to semiconductor chip 12a, on the side of warpage peak 16a. This reduces the possibility that support member 14c included in bonding member 14b below semiconductor chip 12a will leak out of chip underside region 15a when inclined surface 11f occurs.

[0114] Furthermore, if it is predicted that vertex 16a of the warp will occur, it is predicted that the region of the upper surface of wiring board 11b2, located on the +Y side of vertex 16a and where semiconductor chip 12b is located, will also have inclined surface 11f. Therefore, as shown in FIG. 19, on the upper surface of wiring board 11b2, restricting portion 11d may be formed on the edge portion on the side of vertex 16a of the warp in chip undersurface region 15b corresponding to semiconductor chip 12b. This reduces the possibility that support member 14c included in the bonding member below semiconductor chip 12b will leak out from the underside of semiconductor chip 12b in the -Y direction when inclined surface 11f occurs.

[0115] In addition, even if it is predicted that the warp peak 16b will occur at a position on the +X side surface of the insulating substrate 11 corresponding to the region between the wiring board 11b1 and the wiring board 11b3, the restricting portion 11d may be formed at the same position as above.

[0116] Next, a method for manufacturing the semiconductor device 1 as described above will be described with reference to Fig. 20. Fig. 20 is a flowchart showing the manufacturing process of the semiconductor device.

[0117] First, a preparation step is performed to prepare the components of the semiconductor device 1 (step S1). The components prepared include, for example, semiconductor chips 12a and 12b, insulating substrate 11, lead frames 13a and 13b, case 20, cooling device 3, and sealing material. A restricting portion 11d is formed at a predetermined position on the upper surface of the wiring board of insulating substrate 11. Other components necessary for manufacturing the semiconductor device 1 are also prepared. Furthermore, manufacturing equipment and manufacturing jigs necessary for manufacturing the semiconductor device 1 may be prepared.

[0118] Next, a setting process is performed in which semiconductor chip 12 is set on insulating substrate 11, and then lead frames 13a and 13b are set in that order (step S2). In this setting process, bonding members containing support members 14c are placed on wiring boards 11b1 and 11b2 of insulating substrate 11, and semiconductor chips 12a and 12b are placed via such bonding members. The bonding members containing support members 14c are placed on wiring boards 11b1 and 11b2, for example, as plate-shaped bonding members. Typically, such plate-shaped bonding members contain support members 14c dispersed in a planar view. Alternatively, the bonding members containing support members 14c may be applied to wiring boards 11b1 and 11b2 as a paste-like bonding member.

[0119] Next, the components set in step S2 are heated to bond them together in a first bonding step (step S3) to form semiconductor unit 10. In this step, the bonding material between the lower surfaces of semiconductor chips 12a and 12b and the upper surfaces of wiring boards 11b1 and 11b2 melts and then hardens. This bonds the lower surfaces of semiconductor chips 12a and 12b and the upper surfaces of wiring boards 11b1 and 11b2 together via the bonding material containing support member 14c.

[0120] During heating in the first bonding step, warping may occur in insulating substrate 11. Even if the upper surfaces of wiring boards 11b1 and 11b2 on which semiconductor chips 12a and 12b are mounted are tilted due to such warping, movement of support member 14c included in the bonding material is restricted by restricting portions 11d formed on wiring boards 11b1 and 11b2. This allows support member 14c to be secured below semiconductor chips 12a and 12b, ensuring sufficient and uniform spacing between the lower surfaces of semiconductor chips 12a and 12b and the upper surfaces of wiring boards 11b1 and 11b2. As a result, the possibility of damage to the bonding material after hardening is reduced.

[0121] Next, a second joining step is performed to join the semiconductor unit 10 to the top plate 31 of the cooling device 3 (step S4). The semiconductor unit 10 is joined to the top plate 31 of the cooling device 3 via a joining member such as a brazing material or a thermal interface material.

[0122] Next, a housing attachment process is performed to attach the case 20 to the cooling device 3 (step S5). The case 20 is attached with an adhesive to the top plate 31 of the cooling device 3 to which the semiconductor units 10 are joined, and the semiconductor units 10 are housed in the unit housing portions 21e, 21f, and 21g of the case 20. Note that, for example, the first and second joining processes may be performed simultaneously.

[0123] Next, a wiring and sealing process is performed in which wiring is performed on the semiconductor unit 10 and the unit housing portions 21e, 21f, and 21g are sealed with a sealing member (step S6). Inner ends of the first connection terminals 22a, 22b, and 22c exposed from the case 20 to the unit housing portions 21e, 21f, and 21g are joined to the wiring board 11b2 of the insulating substrate 11 of the semiconductor unit 10, for example, by ultrasonic bonding. Similarly, inner ends of the second connection terminals 23a, 23b, and 23c are joined to the wiring board 11b3 of the insulating substrate 11 of the semiconductor unit 10. Similarly, inner ends of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c are joined to the wiring board 11b1 of the insulating substrate 11 of the semiconductor unit 10. Furthermore, inner ends of control terminals 25a, 25b of case 20 are connected to gate electrodes 12a1, 12b1 of semiconductor chips 12a, 12b by wires 26a, 26b. Then, a sealing material is filled into unit storage portions 21e, 21f, 21g to seal semiconductor unit 10. In this manner, semiconductor device 1 shown in FIGS. 1 and 2 is obtained. [Explanation of symbols]

[0124] 1. Semiconductor device 2. Semiconductor Module 3 Cooling device 10, 10a, 10b, 10c semiconductor unit 11 Insulating substrate 11a Insulating plate 11b1,11b2,11b3 Wiring board 11c metal plate 11d Regulatory Department 11d1,11d2 Side edge 11e spacing 11f slope 12, 12a, 12b Semiconductor chip 12a1, 12b1 Gate electrode 12a2, 12b2 Emitter electrodes 12a3 Collector electrode 12a4 side end surface 13a, 13b Lead frame 13a1,13b1 Main electrode junction 13a2, 13b2 First vertical link 13a3, 13b3 Horizontal connection section 13a4, 13b4 Second vertical link 13a5,13b5 Wiring joint 14a, 14b, 14d Joining members 14c Support member 14c1 Top point 15a,15b Chip bottom area 16a,16b Vertex 20 cases 21 Outer Frame 21a,21b,21c,21d Side wall 21e, 21f, 21g Unit storage area 22, 22a, 22b, 22c First connection terminal 23, 23a, 23b, 23c Second connection terminal 24 output terminals 24a U phase output terminal 24b V phase output terminal 24c W phase output terminal 25a, 25b control terminals 26a, 26b Wire 31 Top plate 32 Side wall 33 Cooling bottom plate 33a Inlet 33b Outlet

Claims

1. an insulating substrate including an insulating plate and a wiring board formed on an upper surface of the insulating plate; a semiconductor chip having a lower surface disposed on the upper surface side of the wiring board; a bonding member that includes a conductive support member and bonds an upper surface of the wiring board to a lower surface of the semiconductor chip; and a restricting portion that comes into contact with the support member and restricts movement of the support member is formed on the upper surface of the wiring board; the support member remains at a position overlapping the semiconductor chip in a plan view; Semiconductor device.

2. the restricting portion is formed in a region of the upper surface of the wiring board that faces an outer edge portion of the lower surface of the semiconductor chip; The semiconductor device according to claim 1.

3. the lower surface of the semiconductor chip is rectangular in plan view, the restricting portion is formed on the upper surface of the wiring board at a position facing a corner region of the lower surface of the semiconductor chip; The semiconductor device according to claim 1 .

4. the restricting portion has a curved shape that is convex in a direction from the center of the lower surface of the semiconductor chip toward the outer edge of the lower surface of the semiconductor chip in a plan view. The semiconductor device according to claim 1 .

5. the lower surface of the semiconductor chip is rectangular in plan view, the restricting portion is disposed in a region of the upper surface of the wiring board facing an edge portion along one side of the lower surface of the semiconductor chip, and extends in a direction along the one side. The semiconductor device according to claim 1 .

6. the lower surface of the semiconductor chip is rectangular in plan view, a plurality of the restricting portions are arranged at intervals in a direction along one side of the lower surface of the semiconductor chip in a region of the upper surface of the wiring board facing an edge portion along the one side of the lower surface of the semiconductor chip; The semiconductor device according to claim 1 .

7. a plurality of the restricting portions are formed in a staggered pattern in an area of ​​the upper surface of the wiring board facing the lower surface of the semiconductor chip; The semiconductor device according to claim 1 .

8. the wiring board includes an inclined surface on its upper surface that is inclined due to warping of the insulating substrate; the bonding member bonds the lower surface of the semiconductor chip to the inclined surface of the wiring board; the restricting portion is formed in a region of the upper surface of the wiring board facing the lower surface of the semiconductor chip, the region being closer to the apex of the warp of the insulating substrate; The semiconductor device according to claim 1 .

9. the restricting portion has a convex shape extending from the upper surface of the wiring board toward the semiconductor chip; The semiconductor device according to claim 1 .

10. the restricting portion has a recessed shape recessed in a direction from the upper surface of the wiring board toward the insulating plate, The semiconductor device according to claim 1 .

11. the restricting portion is a roughened region in which the upper surface of the wiring board is roughened; The semiconductor device according to claim 1 .

12. The support member is spherical. The semiconductor device according to claim 1 .

13. The bottom surface of the semiconductor chip is in contact with the support member. The semiconductor device according to claim 1 .

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