Semiconductor device

Abstract

To provide a semiconductor device capable of reducing parasitic oscillation caused by inductance generated between semiconductor chips.SOLUTION: The first gate pattern 4 and the first source pattern 6 are linearly formed in parallel with each other along a first side of the insulating substrate 1. The second gate pattern 5 extends from a first side of the insulating substrate 1 to a second side opposite to the first side and is formed in a rectangular shape in a top view. The drain pattern 8 is formed so as to surround at least three sides of the square shape of the second gate pattern 5. The second source pattern 7 is formed along sides other than the first side of the insulating substrate 1 so as to surround the drain pattern 8. The first and second groups of semiconductor chips 1112 and are arranged at positions adjacent to the second source pattern 7. The first and second groups of semiconductor chips 1112 and and the second source pattern 7 are connected via a plurality of first source wires 23.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] For example, in the semiconductor device described in Patent Document 1, a collector wiring on the ceramic substrate and multiple sets of IGBT chips (corresponding to semiconductor chips) and diode chips (corresponding to semiconductor chips) are bonded to each other on a ceramic substrate by a lower sintered bonding layer. Separate conductive members are connected above the IGBT chips and diode chips by the upper sintered bonding layer, and the emitter wiring on the ceramic substrate, the emitter of the IGBT chip, and the anode of the diode chip are connected by bonding wires, while the IGBT chips and the emitter sense wiring on the ceramic substrate are connected by another bonding wire. The sintered bonding layer is composed of a lower layer and an upper layer that are separated from each other, thereby realizing a semiconductor device that is less likely to generate excessive stress in the gate wiring portion and has reduced characteristic defects. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-117054 Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device in which the gate, collector (or drain), and emitter (or source) of a semiconductor chip are connected in parallel, a positive feedback circuit is formed by the parasitic capacitance and stray inductance of the semiconductor chip, which can cause parasitic oscillation. Parasitic oscillation occurs particularly when the source impedance is large, i.e., when the source wire route is long.

[0005] In the semiconductor device described in Patent Document 1, the emitter wiring on the ceramic substrate, the diode chip, and the IGBT chip are arranged in this order, and because the distance between the emitter wiring on the ceramic substrate and the IGBT chip is long, the path of the bonding wire (corresponding to the source wire) connecting the emitter wiring on the ceramic substrate and the IGBT chip becomes long. This causes variations in inductance between the semiconductor chips, which creates a high possibility of causing parasitic oscillation between the semiconductor chips.

[0006] Therefore, an object of the present disclosure is to provide a semiconductor device that can reduce parasitic oscillation caused by inductance occurring between semiconductor chips. [Means for solving the problem]

[0007] A semiconductor device according to the present disclosure includes an insulating substrate formed in a quadrangular shape in a top view and having a first gate pattern, a second gate pattern, a first source pattern, a second source pattern, and a drain pattern formed on an upper surface thereof, and a first and second semiconductor chip group mounted on the drain pattern, wherein the first gate pattern and the first source pattern are formed in a straight line parallel to each other along a first side of the insulating substrate, the second gate pattern extends from the first side of the insulating substrate to a second side opposite to the first side and is formed in a quadrangular shape in a top view, the drain pattern is formed so as to surround at least three sides of the quadrangular shape of the second gate pattern, and the second source pattern is formed along the sides of the insulating substrate other than the first side so as to surround the drain pattern, and a semiconductor chip group is disposed adjacent to the second source pattern, the first gate pattern and the second gate pattern are connected via a first gate wire, the second gate pattern and the first and second semiconductor chip groups are connected via a plurality of second gate wires, the first and second semiconductor chip groups and the second source pattern are connected via a plurality of first source wires, the first semiconductor chip group and the second semiconductor chip group are connected via a plurality of second source wires, the first and second semiconductor chip groups and the first source pattern are connected via a plurality of third source wires, the semiconductor chips included in the first and second semiconductor chip groups are connected via a plurality of fourth source wires, and a drain main terminal and a source main terminal are connected to the drain pattern and the second source pattern, respectively. [Effects of the Invention]

[0008] According to the present disclosure, the first and second semiconductor chip groups are arranged adjacent to the second source pattern, and therefore the lengths of the multiple first source wires connecting the first and second semiconductor chip groups to the second source pattern are shortened. This configuration can suppress variations in inductance between the semiconductor chips included in the first and second semiconductor chip groups, thereby reducing parasitic oscillation caused by the inductance between the semiconductor chips. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic cross-sectional view for explaining the overall structure of a semiconductor device according to a first embodiment. [Figure 2] 1 is a top view of an insulating substrate included in the semiconductor device according to the first embodiment. [Figure 3] 2 is an enlarged top view of first and second semiconductor chip groups mounted on an insulating substrate and their periphery in the first embodiment. FIG. [Figure 4] 4 is a top view of an insulating substrate for explaining the positions of first and second semiconductor chip groups, the length of a first source wire, and the length of a second source wire in the first embodiment. FIG. [Figure 5] FIG. 10 is a top view of an insulating substrate included in a semiconductor device according to a second embodiment. [Figure 6] FIG. 11 is a top view of an insulating substrate included in a semiconductor device according to a third embodiment. [Figure 7] FIG. 10 is a top view of an insulating substrate included in a semiconductor device according to a fourth embodiment. [Figure 8] FIG. 10 is a top view of an insulating substrate included in a semiconductor device according to a fifth embodiment. [Figure 9] 13 is a top view of an insulating substrate included in a semiconductor device according to a sixth embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] <First Embodiment> The first embodiment will be described below with reference to the drawings. Fig. 1 is a schematic cross-sectional view for explaining the overall structure of a semiconductor device 100 according to the first embodiment. Fig. 2 is a top view of an insulating substrate 1 provided in the semiconductor device 100 according to the first embodiment. Fig. 3 is an enlarged top view of first and second semiconductor chip groups 11 and 12 mounted on the insulating substrate 1 in the first embodiment and their surroundings.

[0011] 1, the semiconductor device 100 includes an insulating substrate 1, a first semiconductor chip group 11, a second semiconductor chip group 12, a drain main terminal 31, a source main terminal 32, a case 41, a sealing material 42, and a lid 43. Note that Fig. 1 shows a schematic cross section to explain the overall structure of the semiconductor device 100, and does not correspond to the top view of Fig. 2.

[0012] 1 and 2, insulating substrate 1 is formed in a rectangular shape when viewed from above, and has a base plate 2, an insulating layer 3 formed on base plate 2, and a circuit pattern formed on insulating layer 3. As shown in FIG. 2, the circuit pattern is formed of a metal such as copper, and includes a first gate pattern 4, a second gate pattern 5, a first source pattern 6, a second source pattern 7, and a drain pattern 8.

[0013] The first gate pattern 4 and the first source pattern 6 are formed in parallel and linear fashion along a first side (the lower side in FIG. 2) of the insulating substrate 1. The first source pattern 6 and the first gate pattern 4 are arranged in this order from the first side of the insulating substrate 1 toward a second side (the upper side in FIG. 2) opposite the first side.

[0014] The second gate pattern 5 extends from the first side to the second side of the insulating substrate 1 and has an elongated rectangular shape in top view. The second gate pattern 5 is disposed closer to the second side than the first gate pattern 4.

[0015] The drain pattern 8 is formed so as to surround at least three sides of the quadrangular shape of the second gate pattern 5. More specifically, the drain pattern 8 is formed so as to surround the four sides of the quadrangular shape of the second gate pattern 5.

[0016] The second source pattern 7 is formed along the sides other than the first side of the insulating substrate 1 so as to surround the drain pattern 8. More specifically, the second source pattern 7 is formed along the second, third, and fourth sides of the insulating substrate 1 so as to surround the drain pattern 8. The portion of the second source pattern 7 on the first side and the portion of the drain pattern 8 on the first side face the first gate pattern 4. Here, the third side is the side connecting the first side and the second side (the left side in FIG. 2), and the fourth side is the side opposite the third side (the right side in FIG. 2).

[0017] As shown in FIG. 1, the first and second semiconductor chip groups 11 and 12 are mounted on the drain pattern 8 via a bonding material 13 such as solder. More specifically, as shown in FIGS. 2 and 3, the first and second semiconductor chip groups 11 and 12 are arranged at positions adjacent to the second source pattern 7 on the drain pattern 8. The first and second semiconductor chip groups 11 and 12 face each other with the second gate pattern 5 interposed therebetween. Specifically, the first semiconductor chip group 11 is arranged on the third side, and the second semiconductor chip group 12 is arranged on the fourth side.

[0018] The first and second semiconductor chip groups 11 and 12 each include a plurality of semiconductor chips. The semiconductor chips are formed of a wide bandgap semiconductor such as SiC, and are, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The semiconductor chips may also be IGBTs (Insulated Gate Bipolar Transistors) or RC-IGBTs (Reverse-Conducting IGBTs) in which an IGBT and a freewheeling diode are formed within a single semiconductor substrate.

[0019] As shown in FIG. 1, the case 41 is formed in a rectangular frame shape when viewed from above, and is adhered to the peripheral edge of the insulating substrate 1 with an adhesive (not shown). One ends of the drain main terminal 31 and the source main terminal 32 are fixed to the case 41. The case 41 is filled with a sealing material 42. The sealing material 42 seals the upper surface of the insulating substrate 1 and the first and second semiconductor chip groups 11, 12, etc. The sealing material 42 is, for example, an epoxy resin. A lid 43 that covers the upper surface of the sealing material 42 is attached to the top of the case 41.

[0020] Next, the connections between the first and second semiconductor chip groups 11 and 12 and the circuit patterns will be described.

[0021] 2, the first gate pattern 4 and the second gate pattern 5 are connected via a first gate wire 21. The second gate pattern 5 and the first and second semiconductor chip groups 11 and 12 are connected via a plurality of second gate wires 22.

[0022] The first and second semiconductor chip groups 11, 12 and the second source pattern 7 are connected via a plurality of first source wires 23. The first semiconductor chip group 11 and the second semiconductor chip group 12 are connected in parallel via a plurality of second source wires 24. The first and second semiconductor chip groups 11, 12 and the first source pattern 6 are connected via a plurality of third source wires 25. The semiconductor chips included in the first and second semiconductor chip groups 11, 12 are connected via a plurality of fourth source wires 26.

[0023] Furthermore, a drain main terminal 31 and a source main terminal 32 are connected to the drain pattern 8 and the second source pattern 7, respectively, via a bonding material (not shown) such as solder or a wire (not shown).

[0024] Next, the positional relationship between the first and second semiconductor chip groups 11 and 12 and the lengths of the source wires connected thereto will be described. Fig. 4 is a top view of the insulating substrate 1 for explaining the positions of the first and second semiconductor chip groups 11 and 12, the lengths of the first source wires 23, and the lengths of the second source wires 24 in the first embodiment.

[0025] As shown in FIG. 4, the semiconductor chips included in the first semiconductor chip group 11 and the semiconductor chips included in the second semiconductor chip group 12 have the same structure. The first semiconductor chip group 11 is arranged rotated 180° in the horizontal direction relative to the second semiconductor chip group 12. In other words, the first semiconductor chip group 11 is arranged in the opposite horizontal direction relative to the second semiconductor chip group 12. Furthermore, the first semiconductor chip group 11 is arranged offset from the second semiconductor chip group 12 by a length a corresponding to 20% of the length of the third side of the insulating substrate 1 in a direction parallel to the third side. If the first semiconductor chip group 11 were not arranged offset from the second semiconductor chip group 12, the length of the multiple second source wires 24 would be long. However, by arranging the first semiconductor chip group 11 offset from the second semiconductor chip group 12, the multiple second source wires 24 can be connected in the shortest possible manner.

[0026] The lengths b of the first source wires 23 are the same or have an error of ±3% or less in consideration of manufacturing variations. The lengths c of the second source wires 24 are the same or have an error of ±3% or less in consideration of manufacturing variations.

[0027] As described above, in the first embodiment, the semiconductor device 100 includes an insulating substrate 1 having a rectangular shape in top view and a first gate pattern 4, a second gate pattern 5, a first source pattern 6, a second source pattern 7, and a drain pattern 8 formed on its top surface, and first and second semiconductor chip groups 11 and 12 mounted on the drain pattern 8. The first gate pattern 4 and the first source pattern 6 are formed in parallel linear fashion along a first side of the insulating substrate 1. The second gate pattern 5 extends from the first side of the insulating substrate 1 to a second side opposite the first side and is formed in a rectangular shape in top view. The drain pattern 8 is formed so as to surround at least three sides of the rectangular shape of the second gate pattern 5. The second source pattern 7 is formed along the sides of the insulating substrate 1 other than the first side so as to surround the drain pattern 8. The first and second semiconductor chip groups 11 and 12 are disposed adjacent to the second source pattern 7. The first gate pattern 4 and the second gate pattern 5 are connected via a first gate wire 21. The second gate pattern 5 and the first and second semiconductor chip groups 11 and 12 are connected via a plurality of second gate wires 22. The first and second semiconductor chip groups 11 and 12 are connected to the second source pattern 7 via a plurality of first source wires 23. The first semiconductor chip group 11 and the second semiconductor chip group 12 are connected via a plurality of second source wires 24. The first and second semiconductor chip groups 11 and 12 are connected to the first source pattern 6 via a plurality of third source wires 25. The semiconductor chips included in the first and second semiconductor chip groups 11 and 12 are connected via a plurality of fourth source wires 26. A drain main terminal 31 and a source main terminal 32 are connected to the drain pattern 8 and the second source pattern 7, respectively.

[0028] Specifically, the drain pattern 8 is formed so as to surround the four sides of the quadrangular shape of the second gate pattern 5.

[0029] Therefore, since the first and second semiconductor chip groups 11 and 12 are arranged adjacent to the second source pattern 7, the lengths of the multiple first source wires 23 connecting the first and second semiconductor chip groups 11 and 12 to the second source pattern 7 are shortened. This configuration makes it possible to suppress variations in inductance occurring between the semiconductor chips included in the first and second semiconductor chip groups 11 and 12, thereby reducing parasitic oscillation caused by the inductance occurring between the semiconductor chips.

[0030] Furthermore, using multiple second gate wires 22 to connect the second gate pattern 5 to the first and second semiconductor chip groups 11, 12 via two second gate wires 22 respectively is less susceptible to induction than stitching with a single wire, and therefore can be more effective as an anti-oscillation measure.

[0031] Furthermore, first semiconductor chip group 11 is arranged offset with respect to second semiconductor chip group 12 by a length corresponding to 20% of the length of a third side connecting the first side and the second side of insulating substrate 1 in a direction parallel to the third side. Therefore, the plurality of second source wires 24 can be made shorter than when first semiconductor chip group 11 is not arranged offset with respect to second semiconductor chip group 12.

[0032] Furthermore, the lengths of the multiple first source wires 23 are the same or have an error of ±3% or less. Similarly, the lengths of the multiple second source wires 24 are the same or have an error of ±3% or less. Therefore, the variation in inductance occurring between semiconductor chips can be further suppressed, and parasitic oscillation caused by the inductance occurring between semiconductor chips can be further reduced.

[0033] The semiconductor chips included in the first and second semiconductor chip groups 11 and 12 are formed of wide bandgap semiconductors. Since semiconductor chips formed of wide bandgap semiconductors are driven at high speeds, variations in inductance between the semiconductor chips are likely to occur. However, the configuration of the semiconductor device 100 according to the first embodiment can suppress variations in inductance, thereby providing excellent effects in this case.

[0034] <Embodiment 2> Next, a description will be given of a second embodiment. Fig. 5 is a top view of an insulating substrate 1 included in a semiconductor device 100 according to the second embodiment. Note that in the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals and description thereof will be omitted.

[0035] 5, in the second embodiment, the first gate pattern 4 and the second gate pattern 5 are integrally formed, instead of the first gate wire 21. In other words, the first gate wire 21 is not used. In addition, the drain pattern 8 is formed so as to surround three sides of the rectangular shape of the second gate pattern 5.

[0036] As described above, the second embodiment provides the same effects as the first embodiment. Furthermore, since the first gate wire 21 can be eliminated, it is possible to contribute to reducing the number of steps in the manufacturing process of the semiconductor device 100.

[0037] <Third Embodiment> Next, a third embodiment will be described. Fig. 6 is a top view of an insulating substrate 1 included in a semiconductor device 100 according to the third embodiment. In the third embodiment, the same components as those described in the first and second embodiments are denoted by the same reference numerals, and the description thereof will be omitted.

[0038] As shown in FIG. 6, the third embodiment has a configuration in which two of the configurations of the first embodiment are arranged in parallel. Specifically, when the second gate pattern 5 and the drain pattern 8 are considered to be one block, the insulating substrate 1 has two blocks 51 and 52 formed adjacent to each other. The two blocks 51 and 52 are arranged in parallel in a direction parallel to the first side. The two blocks 51 and 52 have first and second semiconductor chip groups 11 and 12 mounted thereon. The second source pattern 7 is formed along the sides other than the first side so as to surround the two blocks 51 and 52, and extends into the region between the two blocks 51 and 52.

[0039] The semiconductor chip groups 11, 12 of the first and second semiconductor chip groups 11, 12 that are adjacent to the region on both sides are connected to the portion of the second source pattern 7 that extends into the region via a plurality of fifth source wires 27 or a plurality of sixth source wires 28, respectively, instead of the plurality of first source wires 23. Therefore, the plurality of first source wires 23 connect the semiconductor chip groups 11, 12 of the first and second semiconductor chip groups 11, 12 that are not adjacent to the region to the second source pattern 7.

[0040] As described above, in the third embodiment, not only can the same effects as in the first embodiment be obtained, but also an increased capacity can be realized.

[0041] <Fourth Embodiment> Next, a fourth embodiment will be described. Fig. 7 is a top view of an insulating substrate 1 included in a semiconductor device 100 according to the fourth embodiment. In the fourth embodiment, the same components as those described in the first to third embodiments are denoted by the same reference numerals, and the description thereof will be omitted.

[0042] 7, in the fourth embodiment, two blocks 51 and 52 in the third embodiment are replaced with the configuration of the second embodiment. Specifically, in the two blocks 51 and 52, the first gate pattern 4 and the second gate pattern 5 are integrally formed in place of the first gate wire 21. The drain pattern 8 is formed so as to surround three sides of the rectangular shape of the second gate pattern 5.

[0043] As described above, the fourth embodiment provides the same effects as the third embodiment. Furthermore, since the first gate wire 21 can be eliminated, the number of steps in the manufacturing process of the semiconductor device 100 can be reduced.

[0044] <Fifth Embodiment> Next, a fifth embodiment will be described. Fig. 8 is a top view of an insulating substrate 1 included in a semiconductor device 100 according to the fifth embodiment. In the fifth embodiment, the same components as those described in the first to fourth embodiments are denoted by the same reference numerals, and the description thereof will be omitted.

[0045] 8, in the fifth embodiment, when the second gate pattern 5 and the drain pattern 8 are formed as one block, the insulating substrate 1 has three first blocks 53, 54, and 55 formed adjacent to each other on the first side and three second blocks 56, 57, and 58 formed adjacent to each other on the second side. The three first blocks 53, 54, and 55 and the three second blocks 56, 57, and 58 face each other.

[0046] The first semiconductor chip group 11 is mounted on three first blocks 53, 54, and 55, and the second semiconductor chip group 12 is mounted on three second blocks 56, 57, and 58. Therefore, the first and second semiconductor chip groups 11 and 12 also face each other, and the facing first and second semiconductor chip groups 11 and 12 are connected in series.

[0047] A first drain main terminal 31a is connected to the three first blocks 53, 54, and 55. A second drain main terminal 31b, which serves as a first source main terminal 32a, and a second source main terminal 32b are connected to the three second blocks 56, 57, and 58.

[0048] As described above, a half-bridge circuit can be configured in the fifth embodiment. Furthermore, by arranging the semiconductor devices 100 according to the fifth embodiment in parallel, it becomes easier to configure a multi-phase inverter.

[0049] <Sixth Embodiment> Next, a sixth embodiment will be described. Fig. 9 is a top view of an insulating substrate 1 included in a semiconductor device 100 according to the sixth embodiment. In the sixth embodiment, the same components as those described in the first to fifth embodiments are denoted by the same reference numerals, and the description thereof will be omitted.

[0050] 9, in the sixth embodiment, the insulating substrate 1 has a first ceramic substrate 3a and a second ceramic substrate 3b instead of the insulating layer 3. In other words, the insulating layer 3 is divided into two ceramic substrates 3a and 3b.

[0051] The three first blocks 53, 54, 55 and the three second blocks 56, 57, 58 are formed on the first and second ceramic substrates 3a, 3b, respectively. The first ceramic substrate 3a and the second ceramic substrate 3b are connected by a plurality of first drain wires 35, a plurality of second drain wires 36, and a plurality of third drain wires 37.

[0052] As described above, in embodiment 6, the insulating layer 3 of the insulating substrate 1 is divided into two ceramic substrates 3a and 3b, which improves the heat dissipation properties of the insulating substrate 1 and contributes to improving the power cycle life.

[0053] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate.

[0054] Various aspects of the present disclosure are summarized below as appendices.

[0055] (Appendix 1) an insulating substrate formed in a quadrangular shape in top view and having a first gate pattern, a second gate pattern, a first source pattern, a second source pattern, and a drain pattern formed on an upper surface thereof; a first and second semiconductor chip group mounted on the drain pattern; the first gate pattern and the first source pattern are formed linearly parallel to each other along a first side of the insulating substrate; the second gate pattern extends from the first side of the insulating substrate to a second side opposite to the first side and is formed in a quadrangular shape in a top view, the drain pattern is formed so as to surround at least three sides of the quadrangular shape of the second gate pattern, the second source pattern is formed along a side of the insulating substrate other than the first side so as to surround the drain pattern; the first and second semiconductor chip groups are arranged adjacent to the second source pattern; the first gate pattern and the second gate pattern are connected via a first gate wire; the second gate pattern and the first and second semiconductor chip groups are connected via a plurality of second gate wires; the first and second semiconductor chip groups and the second source pattern are connected via a plurality of first source wires; the first semiconductor chip group and the second semiconductor chip group are connected via a plurality of second source wires; the first and second semiconductor chip groups and the first source pattern are connected via a plurality of third source wires; the semiconductor chips included in the first and second semiconductor chip groups are connected to each other via a plurality of fourth source wires; a drain main terminal and a source main terminal are connected to the drain pattern and the second source pattern, respectively.

[0056] (Appendix 2) 2. The semiconductor device according to claim 1, wherein the drain pattern is formed so as to surround four sides of the quadrangular shape of the second gate pattern.

[0057] (Appendix 3) Instead of the first gate wire, the first gate pattern and the second gate pattern are integrally formed; 2. The semiconductor device according to claim 1, wherein the drain pattern is formed so as to surround three sides of the quadrangular shape of the second gate pattern.

[0058] (Appendix 4) The semiconductor device according to any one of claims 1 to 3, wherein the first group of semiconductor chips is arranged offset from the second group of semiconductor chips by a length corresponding to 20% of the length of a third side connecting the first side and the second side of the insulating substrate in a direction parallel to the third side.

[0059] (Appendix 5) 5. The semiconductor device according to claim 1, wherein the lengths of the first source wires are the same or have an error of ±3% or less.

[0060] (Appendix 6) 6. The semiconductor device according to any one of appendices 1 to 5, wherein the lengths of the second source wires are the same or have an error of ±3% or less.

[0061] (Appendix 7) the second gate pattern and the drain pattern are defined as one block; the insulating substrate has two of the blocks formed adjacent to each other, the second source pattern extends into an area between two of the blocks; A semiconductor device as described in Appendix 1, wherein the semiconductor chip groups adjacent to the region on both sides of the first and second semiconductor chip groups and the portion of the second source pattern extending into the region are connected via a plurality of fifth source wires or a plurality of sixth source wires, respectively.

[0062] (Appendix 8) Instead of the first gate wire, the first gate pattern and the second gate pattern are integrally formed; 8. The semiconductor device according to claim 7, wherein the drain pattern is formed so as to surround three sides of the quadrangular shape of the second gate pattern.

[0063] (Appendix 9) the second gate pattern and the drain pattern are defined as one block; the insulating substrate has three first blocks formed adjacent to each other on the first side and three second blocks formed adjacent to each other on the second side, the first and second semiconductor chip groups are mounted on three of the first blocks and three of the second blocks, respectively; the drain main terminals include first and second drain main terminals; the source main terminals include first and second source main terminals; The first drain main terminals are connected to the three first blocks, The semiconductor device described in Appendix 1, wherein the three second blocks are connected to the second drain main terminal that serves as the first source main terminal and the second source main terminal.

[0064] (Appendix 10) the insulating substrate includes a first ceramic substrate and a second ceramic substrate; the three first blocks and the three second blocks are formed on the first and second ceramic substrates, respectively; 10. The semiconductor device according to claim 9, wherein the first ceramic substrate and the second ceramic substrate are connected by a first drain wire, a second drain wire, and a third drain wire.

[0065] (Appendix 11) 11. The semiconductor device according to claim 1, wherein the semiconductor chips included in the first and second semiconductor chip groups are formed of a wide bandgap semiconductor. [Explanation of symbols]

[0066] 1 insulating substrate, 3a first ceramic substrate, 3b second ceramic substrate, 4 first gate pattern, 5 second gate pattern, 6 first source pattern, 7 second source pattern, 8 drain pattern, 11 first semiconductor chip group, 12 second semiconductor chip group, 21 first gate wire, 22 second gate wire, 23 first source wire, 24 second source wire, 25 third source wire, 26 fourth source wire, 27 fifth source wire, 28 sixth source wire, 31 drain main terminal, 31a first drain main terminal, 31b second drain main terminal, 32 source main terminal, 32a first source main terminal, 32b second source main terminal, 35 first drain wire, 36 second drain wire, 37 third drain wire, 51, 52 block, 53, 54, 55 first block, 56, 57, 58 Second block.

Claims

1. an insulating substrate formed in a quadrangular shape in top view and having a first gate pattern, a second gate pattern, a first source pattern, a second source pattern, and a drain pattern formed on an upper surface thereof; a first and second semiconductor chip group mounted on the drain pattern; the first gate pattern and the first source pattern are formed linearly parallel to each other along a first side of the insulating substrate; the second gate pattern extends from the first side of the insulating substrate to a second side opposite to the first side and is formed in a quadrangular shape in a top view; the drain pattern is formed so as to surround at least three sides of the quadrangular shape of the second gate pattern, the second source pattern is formed along a side of the insulating substrate other than the first side so as to surround the drain pattern; the first and second semiconductor chip groups are arranged adjacent to the second source pattern; the first gate pattern and the second gate pattern are connected via a first gate wire; the second gate pattern and the first and second semiconductor chip groups are connected via a plurality of second gate wires; the first and second semiconductor chip groups and the second source pattern are connected via a plurality of first source wires; the first semiconductor chip group and the second semiconductor chip group are connected via a plurality of second source wires; the first and second semiconductor chip groups and the first source pattern are connected via a plurality of third source wires; the semiconductor chips included in the first and second semiconductor chip groups are connected to each other via a plurality of fourth source wires; a drain main terminal and a source main terminal are connected to the drain pattern and the second source pattern, respectively.

2. 2. The semiconductor device according to claim 1, wherein said drain pattern is formed so as to surround four sides of said quadrangular shape of said second gate pattern.

3. Instead of the first gate wire, the first gate pattern and the second gate pattern are integrally formed; 2. The semiconductor device according to claim 1, wherein said drain pattern is formed so as to surround three sides of said quadrangular shape of said second gate pattern.

4. 2. The semiconductor device according to claim 1, wherein the first group of semiconductor chips is arranged offset from the second group of semiconductor chips by a length corresponding to 20% of the length of a third side connecting the first side and the second side of the insulating substrate in a direction parallel to the third side.

5. 2. The semiconductor device according to claim 1, wherein the lengths of the plurality of first source wires are the same or have an error within ±3%.

6. 2. The semiconductor device according to claim 1, wherein the lengths of the plurality of second source wires are the same or have an error within ±3%.

7. the second gate pattern and the drain pattern are defined as one block; the insulating substrate has two of the blocks formed adjacent to each other, the second source pattern extends into an area between two of the blocks; 2. The semiconductor device according to claim 1, wherein the semiconductor chip groups adjacent to the region on both sides of the first and second semiconductor chip groups and the portion of the second source pattern extending into the region are connected via a plurality of fifth source wires or a plurality of sixth source wires, respectively.

8. Instead of the first gate wire, the first gate pattern and the second gate pattern are integrally formed; 8. The semiconductor device according to claim 7, wherein said drain pattern is formed so as to surround three sides of said quadrangular shape of said second gate pattern.

9. the second gate pattern and the drain pattern are formed as one block; the insulating substrate has three first blocks formed adjacent to each other on the first side and three second blocks formed adjacent to each other on the second side, the first and second semiconductor chip groups are mounted on three of the first blocks and three of the second blocks, respectively; the drain main terminals include first and second drain main terminals; the source main terminals include first and second source main terminals; the first drain main terminals are connected to the three first blocks; 2. The semiconductor device according to claim 1, wherein the second drain main terminal serving as the first source main terminal and the second source main terminal are connected to three of the second blocks.

10. the insulating substrate includes a first ceramic substrate and a second ceramic substrate; the three first blocks and the three second blocks are formed on the first and second ceramic substrates, respectively; 10. The semiconductor device according to claim 9, wherein the first ceramic substrate and the second ceramic substrate are connected by a first drain wire, a second drain wire, and a third drain wire.

11. 11. The semiconductor device according to claim 1, wherein the semiconductor chips included in the first and second semiconductor chip groups are formed of a wide bandgap semiconductor.

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