Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device including a power semiconductor element having a low loss and a large load short circuit resistance.SOLUTION: Le / L> 0.2, where a first boundary is a boundary between the body contact region 7a and the emitting region 6a, a second boundary is a boundary between the body contact region 7b and the emitting region 6b, a portion of the drift region 4 sandwiched between the body region 5a and the body region 5b is referred to as a JFET region 12, a third boundary is a boundary between the body region 5a and the JFET region 12, L is a length between the first boundary and the second boundary, and Le is a length between the first boundary and the third boundary.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device having an insulated gate bipolar transistor (IGBT) and a manufacturing technique thereof that is effective when applied to such a semiconductor device. [Background technology]

[0002] To improve the energy efficiency of power electronics devices, low-loss power semiconductor elements using wide bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), or diamond are being researched.

[0003] Silicon carbide or gallium nitride has a breakdown field strength about 10 times higher than that of silicon (Si). Therefore, for a power semiconductor device with the same breakdown voltage, the film thickness of the drift region can be one-tenth that of silicon. In this way, by thinning the drift region, power semiconductor devices using silicon carbide or gallium nitride can significantly reduce the resistance of the drift region, thereby reducing the on-resistance of the entire power semiconductor device.

[0004] Applications of wide-gap semiconductor materials include unipolar elements such as Schottky barrier diodes (SBDs) or power metal oxide field effect transistors (MOSFETs), as well as bipolar elements such as PN junction diodes and IGBTs. In particular, bipolar elements using silicon carbide are expected to achieve low conduction losses in ultra-high voltage applications exceeding 6.5 kV.

[0005] Power semiconductor elements are used in power conversion devices such as inverters. Power conversion devices can suffer from load short circuits due to malfunctions or incorrect connections. However, typical power conversion devices use a control system to monitor the load current and protect the device by shutting off the circuit if a load short circuit occurs.

[0006] However, it takes several microseconds for a control system to detect a load short circuit and activate a protection circuit. Therefore, during the time between the detection of a load short circuit and the activation of the protection circuit, the power semiconductor device is exposed to high voltage and large current stress. Therefore, it is desirable for the power semiconductor device to have load short circuit resistance.

[0007] Load short circuit capability is an index that indicates the period during which a power semiconductor element can withstand high voltage and large current stress before a protection circuit operates in the event of a load short circuit. Generally, a power semiconductor element is required not to break down even if the on-state continues for 10 microseconds during a load short circuit. For example, Japanese Patent No. 5736683 (Patent Document 1) discloses a technology for improving load short circuit capability by limiting the spacing between body regions. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent No. 5736683 Summary of the Invention [Problem to be solved by the invention]

[0009] As described above, when a power conversion device such as an inverter is operated using power semiconductor elements, there is a possibility that the power semiconductor elements will be damaged by heat generated when a load is short-circuited.

[0010] In particular, power semiconductor elements using wide bandgap semiconductor materials experience a large temperature rise when a load is short-circuited. For this reason, it is necessary to ensure that the power semiconductor elements have sufficient short-circuit resistance to prevent damage to the power semiconductor elements.

[0011] In this regard, when reducing the saturation current of a power semiconductor device alone to suppress losses during a load short circuit, the saturation current is significantly affected by the channel characteristics. Therefore, it is possible to reduce the saturation current by increasing the channel length or by increasing the length of the unit cell in the repeating direction, i.e., the cell pitch, thereby reducing the channel per unit area. However, since there is a trade-off between reducing the saturation current and reducing the on-resistance, reducing the saturation current using the above methods will increase the on-resistance.

[0012] Thus, in order to achieve low loss in power semiconductor elements, it is desirable to reduce the saturation current without increasing the on-resistance.

[0013] For example, in the technology described in Patent Document 1, the depletion layer extends from the well region to the drift region even during normal operation. As a result, the path of the current flowing from the channel to the drift region is restricted by the depletion layer extending from the well region, increasing the on-resistance during normal operation.

[0014] Furthermore, if the impurity concentration in the drift region is reduced in order to ensure the breakdown voltage of the power semiconductor element, the depletion layer will extend further into the drift region, which is disadvantageous in achieving a high breakdown voltage.

[0015] In view of the above, it is desired to realize a semiconductor device having a power semiconductor element with low loss and high load short circuit resistance. [Means for solving the problem]

[0016] One embodiment of the semiconductor device includes an insulated gate bipolar transistor (IGBT) having a drift region of a first conductivity type, a first body region of a second conductivity type formed in the drift region, a second body region of the second conductivity type formed in the drift region and spaced apart from the first body region, a first emitter region of the first conductivity type formed in the first body region, a second emitter region of the first conductivity type formed in the second body region, a first body contact region of the second conductivity type formed in the first body region and in contact with the first emitter region, the first body contact region having an impurity concentration higher than that of the first body region, and a second body contact region of the second conductivity type formed in the second body region and in contact with the second emitter region, the second body contact region having an impurity concentration higher than that of the second body region.

[0017] Here, the boundary between the first body contact region and the first emitter region is defined as the first boundary, the boundary between the second body contact region and the second emitter region is defined as the second boundary, the portion of the drift region sandwiched between the first body region and the second body region is called the JFET region, the boundary between the first body region and the JFET region is defined as the third boundary, the distance between the first boundary and the second boundary is defined as L, and the distance between the first boundary and the third boundary is defined as Le, then Le / L>0.2.

[0018] One embodiment of a semiconductor device manufacturing method is a method for manufacturing a semiconductor device including an insulated gate bipolar transistor, the method including the steps of: (a) forming a drift region of a first conductivity type, (b) forming a first body region of a second conductivity type in the drift region, (c) forming a second body region of the second conductivity type in the drift region, (d) forming a first emitter region of the first conductivity type in the first body region, (e) forming a second emitter region of the first conductivity type in the second body region, (f) forming a first body contact region of the second conductivity type in the first body region, the first body contact region having an impurity concentration higher than that of the first body region, and (g) forming a second body contact region of the second conductivity type in the second body region, the second body contact region having an impurity concentration higher than that of the second body region.

[0019] Here, the boundary between the first body contact region and the first emitter region is defined as the first boundary, the boundary between the second body contact region and the second emitter region is defined as the second boundary, the portion of the drift region sandwiched between the first body region and the second body region is called the JFET region, the boundary between the first body region and the JFET region is defined as the third boundary, the distance between the first boundary and the second boundary is defined as L, and the distance between the first boundary and the third boundary is defined as Le, then Le / L>0.2. [Effects of the Invention]

[0020] According to one embodiment, a semiconductor device having a power semiconductor element with low loss and high load short circuit resistance can be realized. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a top view showing a semiconductor chip CHP on which an n-type IGBT using silicon carbide, which is one of wide bandgap semiconductor materials, is formed. [Figure 2] FIG. 2 is an enlarged top view for explaining a unit cell. [Figure 3] FIG. 3 is a cross-sectional view taken along line AA in FIG. 2. [Figure 4]2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 5] 5 is a cross-sectional view showing a manufacturing process of the semiconductor device following FIG. 4. [Figure 6] 6A to 6C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. 5. [Figure 7] 7A to 7C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. 6. [Figure 8] 10 is a graph showing the relationship between the cell pitch and the collector-emitter voltage (on-state voltage) when on at a collector current of 100 A / cm 2 for a prototype n-type IGBT using silicon carbide. [Figure 9] 10 is a graph showing the relationship between the ratio of Le to L (Le / L) and the on-voltage at a collector current of 100 A / cm 2 . [Figure 10] FIG. 10 is a top view showing a plurality of unit cells according to the second embodiment. [Figure 11] 10 is a graph showing the relationship between the ratio of Le to L (Le / L) and the on-voltage at a collector current of 100 A / cm 2 in the second embodiment. [Figure 12] FIG. 11 is a top view showing a unit cell according to a third embodiment. [Figure 13] FIG. 13 is a cross-sectional view taken along line AA in FIG. [Figure 14] FIG. 13 is a cross-sectional view taken along line BB in FIG. [Figure 15] FIG. 10 is a top view showing a unit cell according to a fourth embodiment. [Figure 16] FIG. 16 is a cross-sectional view taken along line AA in FIG. [Figure 17] FIG. 16 is a cross-sectional view taken along line BB in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0022] In all the drawings for explaining the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations thereof will be omitted. In addition, hatching may be used even in plan views to make the drawings easier to understand.

[0023] In this embodiment, a semiconductor device including an IGBT having an n-type channel structure in which the drift region and emitter region are made of n-type semiconductor regions and the body region is made of p-type semiconductor regions will be described as an example. However, it goes without saying that the technical ideas of the embodiment can also be applied to an IGBT having a p-type channel structure in which the conductivity type is reversed.

[0024] <Basic philosophy> When an IGBT is turned on by applying a gate voltage equal to or greater than the threshold voltage to the gate electrode, holes, which are minority carriers, are injected from the collector region to the drift region. As a result, electrons, which are majority carriers, are injected from the emitter region into the drift region, as if attracted by the injected holes. As a result, a conductivity modulation phenomenon occurs in the drift region, reducing the on-resistance of the IGBT.

[0025] On the other hand, when an IGBT is turned from on to off by applying a gate voltage to the gate electrode that is smaller than the threshold voltage, the IGBT turns off after all of the electrons and holes injected into the drift region are swept out of the drift region. In other words, when an IGBT is turned off, all of the electrons and holes injected into the drift region must be swept out of the drift region, and the tail current caused by this sweeping flows before the IGBT turns off.

[0026] In an IGBT that operates as described above, reducing the saturation current that flows through the IGBT is effective in suppressing loss during a load short circuit.

[0027] The saturation current is greatly affected by the channel characteristics. Therefore, for example, the saturation current can be reduced by increasing the length of the unit cells constituting the IGBT in the repeating direction, i.e., the cell pitch, and thereby reducing the channel per unit area.

[0028] However, since there is a trade-off between reducing the saturation current and reducing the on-resistance, if the saturation current is reduced by increasing the cell pitch, the on-resistance increases.

[0029] Therefore, the basic idea is to increase the conductivity modulation phenomenon while increasing the cell pitch to reduce the saturation current, thereby reducing the on-resistance of the IGBT.

[0030] Specifically, in an IGBT, minority carriers are injected from the collector region into the drift region during on-state operation. As a result, majority carriers are injected from the emitter region into the drift region, as if attracted by the injected minority carriers. As a result, conductivity modulation occurs in the drift region, reducing the on-state resistance of the IGBT. At this time, some of the minority carriers injected into the drift region are swept to the emitter electrode via the body region and body contact region. Therefore, to increase the conductivity modulation phenomenon and reduce the on-state resistance, it is necessary to make it more difficult for minority carriers to be swept to the emitter electrode via the body region and body contact region.

[0031] From this perspective, the basic idea is to make it difficult for minority carriers to be swept from the drift region to the emitter electrode via the body region and body contact region by modifying the IGBT structure. This increases the conductivity modulation phenomenon while increasing the cell pitch, thereby reducing the IGBT's on-resistance. In other words, this basic idea makes it possible to achieve both a reduction in saturation current and a reduction in on-resistance, which are in a trade-off relationship.

[0032] An embodiment that embodies the basic concept will be described below.

[0033] <First Embodiment> <<Configuration of semiconductor device>> FIG. 1 is a top view showing a semiconductor chip CHP on which an n-type IGBT is formed using silicon carbide (SiC), which is one of wide bandgap semiconductor materials.

[0034] In FIG. 1, the semiconductor chip CHP has a termination region 101 , an active region 102 , a gate pad region 103 and a unit cell 104 .

[0035] A termination region 101 is provided in the peripheral region of the semiconductor chip CHP so as to surround the edge of the semiconductor chip CHP. Most of the area inside the termination region 101 is made up of an active region 102 and a gate pad region 103. A plurality of unit cells 104 that constitute the IGBT are spread throughout the active region 102. Although the unit cells 104 are spread throughout the entire active region 102, in FIG. 1, only the unit cells 104 in the center are shown to make the drawing easier to see.

[0036] FIG. 2 is an enlarged top view illustrating the unit cell 104. As shown in FIG.

[0037] In FIG. 2, the unit cell 104 has a drift region 4, a body region 5a, a body region 5b, an emitter region 6a, an emitter region 6b, a body contact region 7a, and a body contact region 7b.

[0038] A channel is formed at the end of the body region 5 along the X direction, which is the horizontal direction on the paper surface of Fig. 2. Unit cells 104 are repeatedly arranged to form blocks along the Y direction, which is the vertical direction on the paper surface of Fig. 2. These blocks form the active region 102.

[0039] FIG. 3 is a cross-sectional view taken along line AA in FIG.

[0040] In FIG. 3, a semiconductor device 100 includes an IGBT.

[0041] The semiconductor device 100 has a collector electrode 1, p + n-type collector region 2, n-type buffer region 3, n - p-type drift region 4, p-type body region 5a, p-type body region 5b, n+ Type emitter region 6a,n + Type emitter region 6b, p + Body contact regions 7a, p + The semiconductor device includes a body contact region 7b, a gate insulating film 8, a gate electrode 9, an emitter electrode 10, an interlayer insulating film 11, and a JFET region 12.

[0042] 3, the material of drift region 4 is silicon carbide, into which n-type impurities (donors) such as nitrogen and phosphorus are introduced. An n-type buffer region 3 containing n-type impurities such as nitrogen and phosphorus is formed below drift region 4. Buffer region 3 is not necessarily required, but is provided to improve breakdown voltage and suppress conduction loss.

[0043] The lower part of the buffer region 3 is formed with a p-type impurity (acceptor) containing aluminum or boron. + A collector region 2 is formed on the semiconductor substrate 1. A collector electrode 1 made of, for example, a metal film is formed below the collector region 2.

[0044] P-type body regions 5a and 5b containing p-type impurities such as aluminum and boron are formed inside the drift region 4. The body regions 5a and 5b are formed separately, and the portion of the drift region 4 sandwiched between the body regions 5a and 5b is called a JFET region 12.

[0045] The body region 5a contains n-type impurities such as nitrogen and phosphorus. + The body region 5b includes an n-type emitter region 6a containing n-type impurities such as nitrogen and phosphorus. + A mold emitter region 6b is formed.

[0046] The contact opening of the body region 5a is provided with p +A body contact region 7a having a SiO 2 structure is formed in the body region 5a. The body contact region 7a is formed inside the body region 5a. The body contact region 7a is formed so as to be in contact with the emitter region 6a. The impurity concentration of the body contact region 7a is higher than the impurity concentration of the body region 5a.

[0047] The contact opening of the body region 5b is provided with p + A body contact region 7b having a SiO 2 structure is formed in the body region 5b. The body contact region 7b is formed inside the body region 5b. The body contact region 7b is formed so as to be in contact with the emitter region 6b. The impurity concentration of the body contact region 7b is higher than the impurity concentration of the body region 5b.

[0048] A gate insulating film 8 is formed to cover parts of the emitter region 6a, part of the emitter region 6b, part of the body region 5a, part of the body region 5b, and part of the drift region 4 (JFET region 12). A gate electrode 9 is formed to cover the gate insulating film 8. An emitter electrode 10 is formed to cover parts of the emitter region 6a, part of the emitter region 6b, body contact region 7a, and body contact region 7b. An interlayer insulating film 11 is formed between the gate electrode 9 and the emitter electrode 10 to insulate the gate electrode 9 from the emitter electrode 10.

[0049] Here, the boundary between the body contact region 7a and the emitter region 6a is defined as the first boundary, the boundary between the body contact region 7b and the emitter region 6b is defined as the second boundary, the boundary between the body region 5a and the JFET region 12 is defined as the third boundary, the distance between the first and second boundaries is defined as L, and the distance between the first and third boundaries is defined as Le. In this case, Le / L>0.2 holds.

[0050] 3, "Lp" represents the cell pitch, and "Lj" represents the distance between the body region 5a and the body region 5b, that is, the width of the JFET region 12.

[0051] <<Semiconductor Device Manufacturing Method>> Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described.

[0052] First, an n-type bulk substrate SUB made of, for example, silicon carbide is prepared as shown in Fig. 4. Then, a collector region 2, a buffer region 3, and a drift region 4 are grown in this order on the upper surface of the bulk substrate SUB by epitaxial growth.

[0053] The impurity concentration of the collector region 2 is, for example, 1×10 18 / cm 3 The impurity concentration of the buffer region 3 is higher than the impurity concentration of the drift region 4. The impurity concentration of the drift region 4 is, for example, 5×10 15 / cm 3 is less than.

[0054] The temperature during epitaxial growth is, for example, 1700 degrees Celsius or higher, and the collector region 2, buffer region 3, and drift region 4 are grown.

[0055] The film thickness of the drift region 4 is, for example, about 50 μm to 100 μm when the withstand voltage is 6.5 kV class, and about 180 μm to 250 μm when the withstand voltage is 20 kV class.

[0056] 5, body regions 5a, body regions 5b, emitter regions 6a, emitter regions 6b, body contact regions 7a, and body contact regions 7b are formed in the upper surface of the drift region 4. These regions can be formed by, for example, ion implantation using, for example, photoresist as a patterning mask.

[0057] The impurity concentration of each of the body regions 5a and 5b is, for example, 2×10 16 / cm 3 Over 2×10 18 / cm 3 Each of the emitter regions 6a and 6b is doped with an n-type impurity of, for example, 1×1019 / cm 3 The body contact region 7a and the body contact region 7b are each formed by implanting a p-type impurity at a high concentration of, for example, 1×10 19 / cm 3 The conductive impurities introduced by ion implantation are formed by implanting ions at a high concentration of about 1700 to 1900 degrees Celsius. After that, a protective film made of carbon is formed on the surface, and then annealing is performed at a temperature of about 1700 to 1900 degrees Celsius to activate the conductive impurities introduced by ion implantation. After that, the protective film is removed by oxygen plasma treatment, for example.

[0058] Then, a gate insulating film 8 is formed on the drift region 4 by, for example, wet oxidation, dry oxidation, or a silicon oxide film formed by CVD (Chemical Vapor Deposition). After the gate insulating film 8 is formed, a polysilicon film or an amorphous silicon film formed by CVD is formed directly on the gate insulating film 8, and the film is transformed into polysilicon by heat treatment. The gate electrode 9 is then formed by patterning the film by, for example, dry etching using a photoresist as a patterning mask. Then, an interlayer insulating film 11 is formed by, for example, a silicon oxide film formed by CVD, and a contact portion is opened by, for example, dry etching. As a result, a part of the emitter region 6a, a part of the emitter region 6b, the body contact region 7a, and the body contact region 7b are exposed from the interlayer insulating film 11 at the bottom of the opening.

[0059] Next, the emitter electrode 10 is formed by sputtering or metal vapor deposition using a metal film such as aluminum, titanium, or nickel. A portion of the emitter electrode 10 is embedded in the opening and is electrically connected to the emitter electrode 10, the emitter region 6a, the emitter region 6b, the body contact region 7a, and the body contact region 7b. Before forming the emitter electrode 10, a silicide film may be formed to cover the portion of the emitter region 6a exposed at the bottom of the opening, the portion of the emitter region 6b, and the upper surfaces of the body contact region 7a and the body contact region 7b. The silicide film can be formed by, for example, salicide technology.

[0060] 6, the bulk substrate SUB is removed by a grinding process to expose the lower surface of the collector region 2. In this way, a semiconductor substrate including the collector region 2, the buffer region 3, and the drift region 4 is prepared.

[0061] Here, an example has been described in which the bulk substrate SUB is removed after forming device structures such as a gate electrode on a semiconductor substrate. However, if the epitaxial layer on the bulk substrate SUB has sufficient strength, the bulk substrate SUB may be removed after forming the epitaxial layer, and then the body regions 5a, 5b, emitter regions 6a, 6b, body contact regions 7a, 7b, gate insulating film 8, gate electrode 9, emitter electrode 10, and interlayer insulating film 11 may be formed.

[0062] 7, a collector electrode 1 is formed by sputtering, metal vapor deposition, or the like using a metal film such as aluminum, titanium, nickel, or gold. This completes the manufacture of the semiconductor device 100 of the first embodiment. Note that, before forming the collector electrode 1, a silicide film covering the lower surface of the collector region 2 may be formed. The silicide film can be formed by, for example, laser annealing.

[0063] <<Features of the First Embodiment>> Next, the features of the first embodiment will be described.

[0064] One of the features of the first embodiment is that, for example, as shown in FIG. 3, the length of the body region in the IGBT is increased to increase the cell pitch Lp. Increasing the cell pitch Lp reduces the channel width per unit area. As a result, the saturation current can be suppressed. However, increasing the cell pitch Lp increases the on-resistance.

[0065] In this regard, another feature of the first embodiment is as follows. That is, in the IGBT, when the IGBT is turned on, the pn junction formed by the collector region 2 and the buffer region 3 (drift region 4) is purely biased. As a result, holes are injected from the collector region 2 into the drift region 4, causing a conductivity modulation phenomenon. The electron concentration in the drift region 4 increases, and the on-resistance decreases. Here, it is important to note that the on-resistance reduction effect based on the conductivity modulation phenomenon depends on the number of holes accumulated in the drift region 4. In other words, the on-resistance reduction effect is determined by the number of holes injected from the collector region 2 into the drift region 4 and the number swept from the drift region 4 to the emitter electrode 10 via the body regions 5a, 5b and the body contact regions 7a, 7b. Therefore, in the embodiment, by increasing the lengths of the body regions 5a and 5b, the outflow of holes to the emitter electrode 10 is suppressed, thereby increasing the conductivity modulation phenomenon and reducing the on-resistance. That is, in the first embodiment, by increasing Le shown in FIG. 3, the resistance of the hole outflow path increases, and as a result, the outflow amount of holes is suppressed, and the effect of increasing the conductivity modulation phenomenon is obtained.

[0066] Therefore, according to the first embodiment, the saturation current can be suppressed by increasing the cell pitch Lp, and the increase in on-resistance caused by the increase in the cell pitch Lp can be suppressed by the effect of reducing the amount of hole outflow. In this way, according to the first embodiment, it is possible to improve the reduction in saturation current and the reduction in on-resistance, which are in a trade-off relationship with each other.

[0067] Figure 8 shows the cell pitch Lp and collector current of a silicon carbide n-type IGBT prototype. 2 1 is a graph showing the relationship between the collector-emitter voltage (on-state voltage) when the transistor is on.

[0068] In Figure 8, when the cell pitch Lp is changed, plots are made for the case where Le is changed (shown by the solid line) and for the case where the length Lj of the region (JFET region 12) sandwiched between adjacent body regions 5a and 5b is changed (shown by the dotted line).

[0069] 8, the increase in on-state voltage due to an increase in the cell pitch Lp is more suppressed when Le is changed than when the length Lj of the JFET region 12 is changed. Therefore, from the viewpoint of reducing the on-state resistance, when increasing the cell pitch Lp, it is found that increasing Le is more effective than increasing Lj.

[0070] FIG. 9 shows the relationship between the ratio of Le to L (Le / L) shown in FIG. 3 and the collector current of 100 A / cm 2 10 is a graph showing the relationship between the ON voltage and the ON state.

[0071] As shown in Figure 9, increasing "Le / L" reduces the on-state voltage due to the increased effect of the conductivity modulation phenomenon. In particular, when "Le / L ≥ 0.2," the increased effect of the conductivity modulation phenomenon becomes sufficient, and the decrease in on-state voltage saturates. In other words, by setting "Le / L ≥ 0.2," it is possible to increase the cell pitch while suppressing the increase in on-state resistance.

[0072] In the first embodiment, when "Le / L≧0.35", the influence of the increase in on-resistance due to the increase in cell pitch Lp becomes significant, and the on-voltage increases.

[0073] IGBTs are susceptible to a phenomenon known as latch-up. This latch-up occurs when a parasitic PNP bipolar transistor formed by the collector region 2 (p-type), drift region 4 (n-type), and body regions 5a and 5b (p-type) turns on, causing current to flow through a path separate from the channel controlled by the gate electrode 9, resulting in a loss of current control by the gate electrode 9. The condition for this parasitic PNP bipolar transistor to turn on is when the voltage drop caused by the resistance in the body regions 5a and 5b exceeds the built-in voltage (built-in potential) at the pn junction of the semiconductor material.

[0074] Therefore, when the cell pitch Lp is increased by increasing the length of each of the body regions 5a and 5b to increase Le, the resistance of the body regions 5a and 5b increases, making latch-up more likely to occur.

[0075] In this regard, in the first embodiment, silicon carbide is used as the semiconductor material. Silicon carbide has a larger band gap than silicon, and therefore has a built-in voltage of approximately 3 V, which is higher than the approximately 0.7 V of silicon. This makes it possible to improve the relationship between the reduction in saturation current and the reduction in on-resistance, which are in a trade-off relationship, while suppressing the occurrence of latch-up.

[0076] As described above, according to the first embodiment, the trade-off between reducing the saturation current and the on-resistance of the IGBT can be improved. As a result, according to the first embodiment, the load short circuit capability can be improved while suppressing an increase in the on-voltage.

[0077] In the first embodiment, a periodic structure of unit cells 104 having a cell pitch Lp is used for explanation, but the present invention can also be applied to a configuration in which the active region 102 does not have a periodic structure of unit cells 104, as long as "Le / L≧0.2".

[0078] <Embodiment 2> FIG. 10 is a top view showing a plurality of unit cells according to the second embodiment.

[0079] 10, unit cells CL1, CL2, CL3, CL4, and CL5 included in the plurality of unit cells are arranged in a staggered pattern. For example, unit cell CL1 has a body region 5a, an emitter region 6a, and a body contact region 7a. Unit cell CL2 has a body region 5a, an emitter region 6b, and a body contact region 7b.

[0080] The cross-sectional view corresponding to the line AA in FIG. 10 is the same as that in the first embodiment, and is as shown in FIG.

[0081] The difference between the second embodiment and the first embodiment is that in the second embodiment, the body regions 5a and 5b have a rectangular shape and channels are formed in both the X and Y directions. As a result, the channel width per unit area is increased in the second embodiment compared to the first embodiment, in which the channel is formed only in the X direction, and as a result, electron injection from the emitter regions 6a and 6b is increased. Such a semiconductor device configuration can be achieved by changing the mask used in the photolithography technique used for patterning.

[0082] In the IGBT according to the second embodiment, the channel width per unit area is large, and therefore an increase in on-resistance due to an increase in the cell pitch Lp is suppressed compared to the IGBT according to the first embodiment. Therefore, according to the second embodiment, an increase in on-voltage when "Le / L" is large can be suppressed.

[0083] FIG. 11 shows the relationship between the ratio of Le to L (Le / L) and the collector current of 100 A / cm in the second embodiment. 2 10 is a graph showing the relationship between the ON voltage and the ON state.

[0084] In the second embodiment, as in the first embodiment, the on-state voltage decreases as "Le / L" increases. In particular, when "Le / L≧0.25", the effect of increasing the conductivity modulation phenomenon becomes sufficient, and the decrease in the on-state voltage saturates. Furthermore, in the second embodiment, even when "Le / L≧0.35", the on-state voltage does not increase and remains at a nearly constant value.

[0085] Therefore, according to the second embodiment, the cell pitch can be increased to suppress the saturation current while suppressing the increase in the on-state voltage more than in the first embodiment. That is, according to the second embodiment, the load short circuit resistance can be improved while suppressing the increase in the on-state voltage more than in the first embodiment.

[0086] In the second embodiment, the body regions 5a and 5b are described as having a rectangular shape. However, the technical idea of ​​the second embodiment can be applied to cases where the body regions 5a and 5b have a polygonal shape, such as a hexagon or an octagon, as long as the channels are formed in multiple directions on the wafer main surface.

[0087] <Third Embodiment> FIG. 12 is a top view showing a unit cell 104A according to the third embodiment.

[0088] In FIG. 12, the unit cell 104A has a body region 5a, a body region 5b, an emitter region 6a, an emitter region 6b, a body contact region 7a, a body contact region 7b, a p-type semiconductor region 21, a trench 22a, and a trench 22b.

[0089] FIG. 13 is a cross-sectional view taken along the line AA in FIG.

[0090] The semiconductor device 100A has a collector electrode 1, p + n-type collector region 2, n-type buffer region 3, n - p-type drift region 4, p-type body region 5a, p-type body region 5b, n + Type emitter region 6a,n + Type emitter region 6b, p +Body contact regions 7a, p + The semiconductor device has a body contact region 7b, a gate insulating film 8, a gate electrode 9, an emitter electrode 10, an interlayer insulating film 11, a JFET region 12, an n-type current diffusion region 20, a p-type semiconductor region 21, a trench 22a, and a trench 22b.

[0091] FIG. 14 is a cross-sectional view taken along line BB in FIG.

[0092] In the cross-sectional view shown in FIG. 14, trenches 22a and 22b are absent.

[0093] 13, trench 22a is formed so as to contact emitter region 6a. Trench 22a has a bottom surface located within body region 5a. Trench 22b is formed so as to contact emitter region 6b. Trench 22b has a bottom surface located within body region 5b.

[0094] Between the trenches 22a and 22b, an n-type current diffusion region 20 is formed. The impurity concentration of the current diffusion region 20 is higher than the impurity concentration of the drift region 4.

[0095] A p-type semiconductor region 21 is formed on the current spreading region 20. The gate insulating film 8 includes a first portion formed on the inner wall of the trench 22a, a second portion formed on the inner wall of the trench 22b, and a third portion formed on the semiconductor region 21. The gate electrode 9 is formed so as to be in contact with the gate insulating film 8. The gate electrode 9 has a portion embedded in the trench 22a and a portion embedded in the trench 22b.

[0096] The semiconductor device 100A according to the third embodiment differs from the semiconductor device 100 according to the first embodiment in the following respects.

[0097] In the semiconductor device 100A of the third embodiment, an n-type current diffusion region 20 containing n-type impurities such as nitrogen or phosphorus is formed apart from the emitter region 6a and the emitter region 6b. In addition, a p-type semiconductor region 21 containing p-type impurities such as aluminum or boron is formed on the current diffusion region 20. The current diffusion region 20 is formed so as to be electrically connected to the drift region 4.

[0098] The semiconductor device 100A has trenches 22a and 22b formed therein. The left side surface of the trench 22a is in contact with the emitter region 6a, while the right side surface is in contact with the current spreading region 20 and the semiconductor region 21. The bottom of the trench 22a is in contact with the body region 5a. The right side surface of the trench 22b is in contact with the emitter region 6b, while the left side surface is in contact with the current spreading region 20 and the semiconductor region 21. The bottom of the trench 22b is in contact with the body region 5b.

[0099] The gate insulating film 8 is formed on the inner walls of the trenches 22a and 22b, and over the semiconductor region 21. Channels are formed on the side surfaces of the trenches 22a and 22b. As a result, electrons injected from the emitter electrode 10 flow from the emitter region 6a through the channel formed on the side surface of the trench 22a to the current diffusion region 20, and are injected into the drift region 4 electrically connected to the current diffusion region 20. Similarly, electrons injected from the emitter electrode 10 flow from the emitter region 6b through the channel formed on the side surface of the trench 22b to the current diffusion region 20, and are injected into the drift region 4 electrically connected to the current diffusion region 20.

[0100] The semiconductor device 100A configured as described above is manufactured as follows: In the first embodiment, when the body regions 5a, 5b, the emitter regions 6a, 6b, and the body contact regions 7a, 7b are formed on the upper surface of the drift region 4, the current spreading region 20 and the semiconductor region 21 are also formed.

[0101] The current spreading region 20 and the semiconductor region 21 can be formed by, for example, ion implantation using, for example, a photoresist as a patterning mask. The impurity concentration of the current spreading region 20 is, for example, 5×10 16 / cm 3 5x10 or more 18 / cm 3 The impurity concentration of the semiconductor region 21 is, for example, 5×10 16 / cm 3 5x10 or more 18 / cm 3 It is about the following.

[0102] Each of trenches 22a and 22b can be formed by, for example, performing annealing to activate conductive impurities introduced by ion implantation, and then performing dry etching or the like using a silicon oxide film or the like as a patterning mask. The silicon oxide film patterning mask can be formed by, for example, depositing a silicon oxide film by CVD or the like, and then performing dry etching or the like using a photoresist or the like as a patterning mask.

[0103] The depth of the trench 22a is shallower than that of the body region 5a and deeper than that of the semiconductor region 21. Similarly, the depth of the trench 22b is shallower than that of the body region 5b and deeper than that of the semiconductor region 21. The length of the trench 22a in a direction parallel to the channel length is, for example, about 1 μm or more and 3 μm or less. The length of the trench 22b in a direction parallel to the channel length is, for example, about 1 μm or more and 3 μm or less. The length of the trench 22a in a direction parallel to the channel width is, for example, about 0.1 μm or more and 1 μm or less. The length of the trench 22b in a direction parallel to the channel width is, for example, about 0.1 μm or more and 1 μm or less. The spacing between the trenches 22a in a direction parallel to the channel width is, for example, about 0.1 μm or more and 1 μm or less. The spacing between the trenches 22b in a direction parallel to the channel width is, for example, about 0.1 μm or more and 1 μm or less.

[0104] In the semiconductor device 100A according to the second embodiment, the trenches 22a and 22b form a fin structure, so that the side surfaces of the trenches 22a and 22b become channels. Therefore, the channel width per unit area is larger than that of the semiconductor device 100 according to the first embodiment, in which the trenches 22a and 22b are not formed. As a result, in the third embodiment, as in the second embodiment, an increase in on-resistance due to an increase in the cell pitch Lp is suppressed compared to that in the first embodiment. Therefore, in the third embodiment, an increase in on-voltage when "Le / L" is large can also be suppressed.

[0105] From the above, the third embodiment can reduce the saturation current by increasing the cell pitch while suppressing the increase in on-voltage more than the first embodiment. That is, the third embodiment can improve the load short circuit resistance while suppressing the increase in on-voltage more than the first embodiment.

[0106] Furthermore, according to the third embodiment, the following advantages are obtained.

[0107] (1) By reducing the length and spacing of trenches 22a and 22b parallel to the channel width, the channel width per unit area can be further increased, and electron injection from emitter regions 6a and 6b can be increased, resulting in a reduction in on-resistance.

[0108] (2) The bottom surface of trench 22a is formed within body region 5a, and the bottom surface of trench 22b is formed within body region 5b. Therefore, compared to a normal trench gate structure having a portion exposed from the body region, the electric field applied to gate insulating films 8 formed on the surfaces of trench 22a and trench 22b when maintaining a breakdown voltage can be significantly alleviated.

[0109] (3) The p-type semiconductor region 21 is provided between the n-type current diffusion region 20 and the gate insulating film 8, and the semiconductor region 21 shields the electric field. As a result, the electric field applied to the gate insulating film 8 near the current diffusion region 20 can be significantly alleviated.

[0110] <Fourth Embodiment> FIG. 15 is a top view showing a unit cell 104B according to the fourth embodiment.

[0111] 15, the unit cell 104B has a body region 5a, a body region 5b, an emitter region 6a, an emitter region 6b, a body contact region 7a, a body contact region 7b, a p-type channel region 31, and a trench 32. In FIG.

[0112] FIG. 16 is a cross-sectional view taken along the line AA in FIG.

[0113] The semiconductor device 100B has a collector electrode 1, p + n-type collector region 2, n-type buffer region 3, n - p-type drift region 4, p-type body region 5a, p-type body region 5b, n + Type emitter region 6a,n + Type emitter region 6b, p + Body contact regions 7a, p + a body contact region 7b, a gate insulating film 8, a gate electrode 9, an emitter electrode 10, an interlayer insulating film 11, a JFET region 12, an n + The semiconductor device has a p-type auxiliary emitter region 30 , a p-type channel region 31 and a trench 32 .

[0114] FIG. 17 is a cross-sectional view taken along line BB in FIG.

[0115] In the cross-sectional view shown in FIG. 17, trench 32 is absent.

[0116] 16, the semiconductor device 100B has a trench 32. The trench 32 has a bottom surface consisting of a first bottom portion, a second bottom portion, and a third bottom portion. The first bottom portion is located in the body region 5a. The second bottom portion is located in the drift region 4 (in the JFET region 12). The third bottom portion is located in the body region 5b.

[0117] A gate insulating film 8 is formed on the inner wall of the trench 32. A gate electrode 9 is formed in contact with the gate insulating film 8.

[0118] The auxiliary emitter region 30 is formed in the body region 5a and includes a first region portion formed between the emitter region 6a and the trench 32, and a second region portion formed in the body region 5b and between the emitter region 6b and the trench 32. The auxiliary emitter region 30 is doped with n-type impurities such as nitrogen or phosphorus.

[0119] The bottom surface of the auxiliary emitter region 30 is located shallower than the bottom surface of the emitter region 6a, and the bottom surface of the auxiliary emitter region 30 is located shallower than the bottom surface of the emitter region 6b. The impurity concentration of the auxiliary emitter region 30 is lower than the impurity concentration of the emitter region 6a, and the impurity concentration of the auxiliary emitter region 30 is lower than the impurity concentration of the emitter region 6b.

[0120] The channel region 31 includes a third region portion formed in the body region 5a, in contact with the first region portion of the auxiliary emitter region 30, and in contact with the trench 32, and a fourth region portion formed in the body region 5b, in contact with the second region portion of the auxiliary emitter region 30, and in contact with the trench 32. P-type impurities such as aluminum or boron are introduced into the channel region 31. The channel is formed by inverting the p-type channel region 31 formed on the side surface of the trench 32 to n-type by applying a gate voltage equal to or higher than the threshold voltage to the gate electrode 9. Electrons injected from the emitter electrode 10 flow from the emitter region 6a to the auxiliary emitter region 30 and then pass through a channel (inversion layer) formed on the side surface of the trench 32 and are injected into the drift region 4.

[0121] The semiconductor device 100B configured as described above is manufactured as follows: In the first embodiment, when the body regions 5a, 5b, the emitter regions 6a, 6b, and the body contact regions 7a, 7b are formed on the upper surface of the drift region 4, the auxiliary emitter region 30 and the channel region 31 are also formed.

[0122] The method for manufacturing the semiconductor device 100B according to the fourth embodiment includes the following steps.

[0123] The method includes the steps of: forming an n-type first impurity region between emitter region 6a and emitter region 16b; forming a p-type second impurity region in body region 5a, drift region 4, and body region 5b, the p-type second impurity region being in contact with the first impurity region and located below the first impurity region; forming a trench 32 that penetrates the first impurity region and the second impurity region and has a bottom surface consisting of a first bottom surface portion, a second bottom surface portion, and a third bottom surface portion, the first bottom surface portion being in body region 5a, the second bottom surface portion being in drift region 4, and the third bottom surface portion being in body region 5b; forming a gate insulating film 8 having a portion in contact with an inner wall of trench 32; and forming a gate electrode 9 that is formed so as to be in contact with the gate insulating film 8 and includes a portion embedded in trench 32.

[0124] Here, by forming trench 32 so as to penetrate the first impurity region, a first region portion and a second region portion of auxiliary emitter region 30 are formed from the first impurity region. In addition, by forming trench 32 so as to penetrate the second impurity region, a third region portion and a fourth region portion of channel region 31 are formed from the second impurity region.

[0125] The bottom surface of the first impurity region is located shallower than the bottom surfaces of the emitter regions 6 a and 6 b. The impurity concentration of the first impurity region is lower than the impurity concentration of the emitter region 6 a, and lower than the impurity concentration of the emitter region 6 b.

[0126] The auxiliary emitter region 30 and the channel region 31 can be formed by, for example, ion implantation using, for example, a photoresist as a patterning mask.

[0127] The impurity concentration of the auxiliary emitter region 30 is, for example, 1×10 18 / cm 3 More than 1×10 19 / cm 3 The impurity concentration of the channel region 31 is, for example, 5×10 16 / cm 3 5x10 or more 18 / cm 3 It is about the following.

[0128] The trenches 32 can be formed, for example, by dry etching using a silicon oxide film as a patterning mask after annealing to activate the conductive impurities introduced by ion implantation. The silicon oxide film patterning mask can be formed, for example, by depositing a silicon oxide film by CVD or the like, and then dry etching using a photoresist or the like as a patterning mask.

[0129] The depth of the trench 32 is shallower than that of the body regions 5a, 5b and deeper than that of the auxiliary emitter region 30 and the channel region 31. The length of the trench 32 in a direction parallel to the direction in which the body regions 5a, 5b face each other is, for example, about 1 μm to 5 μm. The length of the trench 32 in a direction perpendicular to the direction in which the body regions 5a, 5b face each other is, for example, about 0.1 μm to 1 μm. The trench spacing in the direction perpendicular to the direction in which the body regions 5a, 5b face each other is, for example, about 0.1 μm to 1 μm.

[0130] In the semiconductor device 100B according to the fourth embodiment, the trench 32 forms a fin structure, and the side surface of the trench 32 serves as a channel. Therefore, by reducing the length and spacing of the trench in the direction perpendicular to the direction in which the body regions 5a, 5b face each other, the channel width per unit area can be increased. Therefore, in the fourth embodiment, as in the second embodiment, an increase in on-resistance due to an increase in the cell pitch Lp is suppressed compared to the first embodiment. In particular, in the fourth embodiment, an increase in on-voltage when "Le / L" is large can be suppressed, and the on-resistance can be further reduced.

[0131] From the above, the fourth embodiment can reduce the saturation current by increasing the cell pitch while suppressing the increase in on-voltage more than the first embodiment. That is, the fourth embodiment can improve the load short circuit resistance while suppressing the increase in on-voltage more than the first embodiment.

[0132] Furthermore, according to the fourth embodiment, the following advantages are obtained.

[0133] (1) The trench 32 is formed shallower than the body regions 5a and 5b. Therefore, the electric field applied to the gate insulating film 8 formed on the inner wall of the trench 32 when the breakdown voltage is maintained can be significantly alleviated by the depletion layer extending from the body regions 5a and 5b.

[0134] (2) The auxiliary emitter region 30 is formed shallower than the emitter regions 6a and 6b, and the impurity concentration of the auxiliary emitter region 30 is set lower than the impurity concentration of the emitter regions 6a and 6b. This increases the resistance of the auxiliary emitter region 30. As a result, the potential of the drift region 4 near the body regions 5a and 5b can be increased when a load short circuit occurs.

[0135] Therefore, the depletion by the body regions 5a and 5b can be strengthened, and the saturation current can be reduced.

[0136] (3) In the semiconductor device 100B according to the fourth embodiment, the channel length is determined by the difference in depth between the channel region 31 and the auxiliary emitter region 30. Therefore, by forming the auxiliary emitter region 30 shallower than the emitter regions 6a and 6b, the channel length can be increased without increasing the depth of the trench 32. Therefore, according to the fourth embodiment, the degree of freedom in designing the channel length can be improved while maintaining the depth of the body regions 5a and 5b.

[0137] As described above, the technical concept of the embodiment can improve the trade-off between reducing the saturation current and the on-resistance of the IGBT, thereby improving the load short circuit resistance while suppressing an increase in the on-voltage. Furthermore, it is possible to provide a semiconductor device that has high insulation film reliability while realizing low on-resistance.

[0138] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0139] 1 Collector electrode 2 Collector region 3 Buffer Area 4 Drift Region 5a Body Region 5b Body region 6a Emitter region 6b Emitter region 7a Body contact area 7b Body contact area 8 Gate insulating film 9 Gate electrode 10 Emitter electrode 11 Interlayer insulating film 12 JFET area 20 Current spreading region 21 Semiconductor area 22a Trench 22b Trench 30 Auxiliary emitter area 31 Channel Region 32 Trench 100 Semiconductor device 100A Semiconductor Device 100B Semiconductor device 101 Termination Area 102 Active Area 103 Gate pad area 104 unit cells 104A unit cell 104B unit cell CHP semiconductor chip CL1 unit cell CL2 unit cell CL3 unit cell CL4 unit cell CL5 unit cell SUB bulk substrate

Claims

1. A semiconductor device including an insulated gate bipolar transistor, The insulated gate bipolar transistor is a drift region of a first conductivity type; a first body region of a second conductivity type formed in the drift region; a second body region of the second conductivity type formed in the drift region and separated from the first body region; a first emitter region of the first conductivity type formed in the first body region; a second emitter region of the first conductivity type formed in the second body region; a first body contact region of the second conductivity type formed in the first body region, in contact with the first emitter region, and having an impurity concentration higher than an impurity concentration of the first body region; a second body contact region of the second conductivity type formed in the second body region, in contact with the second emitter region, and having an impurity concentration higher than an impurity concentration of the second body region; and a boundary between the first body contact region and the first emitter region is defined as a first boundary; a boundary between the second body contact region and the second emitter region is defined as a second boundary; a portion of the drift region sandwiched between the first body region and the second body region is called a JFET region, and a boundary between the first body region and the JFET region is called a third boundary; The distance between the first boundary and the second boundary is L, When the distance between the first boundary and the third boundary is Le, A semiconductor device in which Le / L>0.

2.

2. 2. The semiconductor device according to claim 1, the insulated gate bipolar transistor has a plurality of cells arranged in a staggered manner; the plurality of cells includes a first cell and a second cell; The first cell is the first body region; the first emitter region; the first body contact region; and The second cell is the second body region; the second emitter region; the second body contact region; It has.

3. 2. The semiconductor device according to claim 1, The insulated gate bipolar transistor is a first trench formed to contact the first emitter region and having a first bottom surface within the first body region; a second trench formed to contact the second emitter region and having a second bottom surface within the second body region; a current diffusion region of the first conductivity type formed between the first trench and the second trench and having an impurity concentration higher than an impurity concentration of the drift region; a gate insulating film having a first portion formed on an inner wall of the first trench and a second portion formed on an inner wall of the second trench; a gate electrode in contact with the gate insulating film, the gate electrode including a portion embedded in the first trench and a portion embedded in the second trench; It has.

4. 4. The semiconductor device according to claim 3, The insulated gate bipolar transistor is the second conductivity type semiconductor region formed on the current diffusion region; the gate insulating film including a third portion formed on the semiconductor region; It has.

5. 2. The semiconductor device according to claim 1, The insulated gate bipolar transistor is a trench having a bottom surface consisting of a first bottom portion, a second bottom portion, and a third bottom portion, the trench being formed such that the first bottom portion is in the first body region, the second bottom portion is in the drift region, and the third bottom portion is in the second body region; a first semiconductor region of the first conductivity type, the first semiconductor region including a first region portion formed in the first body region and between the first emitter region and the trench, and a second region portion formed in the second body region and between the second emitter region and the trench; a second semiconductor region of the second conductivity type, including a third region portion formed in the first body region, in contact with the first region portion of the first semiconductor region, and in contact with the trench; and a fourth region portion formed in the second body region, in contact with the second region portion of the first semiconductor region, and in contact with the trench; a gate insulating film formed on an inner wall of the trench; a gate electrode in contact with the gate insulating film; It has.

6. 6. The semiconductor device according to claim 5, a bottom surface of the first semiconductor region is located shallower than a bottom surface of the first emitter region, The bottom surface of the first semiconductor region is located shallower than the bottom surface of the second emitter region.

7. 6. The semiconductor device according to claim 5, an impurity concentration of the first semiconductor region is lower than an impurity concentration of the first emitter region; The impurity concentration of the first semiconductor region is lower than the impurity concentration of the second emitter region.

8. 2. The semiconductor device according to claim 1, The material of the drift region is silicon carbide.

9. A method for manufacturing a semiconductor device including an insulated gate bipolar transistor, comprising: (a) forming a drift region of a first conductivity type; (b) forming a first body region of a second conductivity type within the drift region; (c) forming a second body region of the second conductivity type within the drift region; (d) forming a first emitter region of the first conductivity type within the first body region; (e) forming a second emitter region of the first conductivity type within the second body region; (f) forming a first body contact region of the second conductivity type in the first body region, the first body contact region having an impurity concentration higher than an impurity concentration of the first body region; (g) forming a second body contact region of the second conductivity type in the second body region, the second body contact region having an impurity concentration higher than an impurity concentration of the second body region; and a boundary between the first body contact region and the first emitter region is defined as a first boundary; a boundary between the second body contact region and the second emitter region is defined as a second boundary; a portion of the drift region sandwiched between the first body region and the second body region is called a JFET region, and a boundary between the first body region and the JFET region is called a third boundary; The distance between the first boundary and the second boundary is L, When the distance between the first boundary and the third boundary is Le, A method for manufacturing a semiconductor device, wherein Le / L>0.

2.

10. 10. The method for manufacturing a semiconductor device according to claim 9, (h) forming a current spreading region of the first conductivity type extending within the first body region, the drift region, and the second body region; (i) forming a first trench disposed between the first emitter region and the current spreading region, in contact with the first emitter region and in contact with the current spreading region, and having a first bottom surface within the first body region; (j) forming a second trench disposed between the second emitter region and the current spreading region, in contact with the second emitter region and in contact with the current spreading region, and having a second bottom surface within the second body region; (k) forming a gate insulating film having a first portion in contact with an inner wall of the first trench and a second portion in contact with an inner wall of the second trench; (l) forming a gate electrode formed to be in contact with the gate insulating film, the gate electrode including a portion embedded in the first trench and a portion embedded in the second trench; It has.

11. 11. The method for manufacturing a semiconductor device according to claim 10, (m) forming a semiconductor region of the second conductivity type on the current spreading region before the step (k), The gate insulating film includes a third portion formed on the semiconductor region.

12. 10. The method for manufacturing a semiconductor device according to claim 9, (n) forming a first impurity region of the first conductivity type between the first emitter region and the second emitter region; (o) forming a second impurity region of the second conductivity type in contact with the first impurity region and located below the first impurity region, across the first body region, the drift region, and the second body region; (p) forming a trench that penetrates the first impurity region and the second impurity region, has a bottom surface consisting of a first bottom surface portion, a second bottom surface portion, and a third bottom surface portion, and the first bottom surface portion is located in the first body region, the second bottom surface portion is located in the drift region, and the third bottom surface portion is located in the second body region; (q) forming a gate insulating film having a portion in contact with the inner wall of the trench; (r) forming a gate electrode formed so as to be in contact with the gate insulating film, the gate electrode including a portion embedded in the trench; It has.

13. 13. The method for manufacturing a semiconductor device according to claim 12, The bottom surface of the first impurity region is located shallower than the bottom surface of the first emitter region.

14. 13. The method for manufacturing a semiconductor device according to claim 12, an impurity concentration of the first impurity region is lower than an impurity concentration of the first emitter region; The impurity concentration of the first impurity region is lower than the impurity concentration of the second emitter region.

15. 10. The method for manufacturing a semiconductor device according to claim 9, The material of the drift region is silicon carbide.

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