Semiconductor device

Abstract

To improve the breakdown voltage of a semiconductor device.SOLUTION: A semiconductor device 10 includes a semiconductor layer 12 having a body region, a plurality of cell trenches 14, an insulating layer 16, a plurality of gate electrodes 58 embedded in the plurality of cell trenches 14 via the insulating layer 16, a gate pad 25 provided on the insulating layer 16 and electrically connected to the plurality of gate electrodes 58, a source wiring 22 provided on the insulating layer 16, and a plurality of contacts 62 each disposed between two adjacent cell trenches 14 among the plurality of cell trenches 14 in plan view and connecting the source wiring 22 and the body region. The plurality of contacts 62 include an isolated contact 63 disposed at a position isolated from the gate pad 25 and having a first widthwise W1, and a proximal contact 65 disposed at a position closer to the gate pad 25 than the isolated contact 63 and having a second widthwise W1 larger than the first widthwise W2.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] A transistor having a trench gate structure in which a gate electrode is buried in a gate trench is known. Patent Document 1 discloses a semiconductor device in which a plurality of source contact holes for forming source plug electrodes are formed alternately with a plurality of gate trenches. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-125649

[0004] [overview] There is a demand for improved breakdown voltage of semiconductor devices.

[0005] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor layer having a body region, a plurality of cell trenches provided in the semiconductor layer, an insulating layer provided in the cell trenches and on the semiconductor layer, a plurality of gate electrodes embedded in the cell trenches via the insulating layer, a gate pad provided on the insulating layer and electrically connected to the gate electrodes, a source wiring provided on the insulating layer, and a plurality of contacts each disposed between two adjacent ones of the cell trenches in a plan view, the plurality of contacts connecting the source wiring to the body region. The plurality of contacts include a remote contact having a first width and disposed at a position spaced apart from the gate pad, and a proximal contact having a second width greater than the first width and disposed closer to the gate pad than the remote contact. [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 is an exemplary schematic plan view of a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing the arrangement of cell trenches and field plate trenches provided in a semiconductor layer of the semiconductor device shown in FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view taken along line F3-F3 of the semiconductor device shown in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view taken along line F4-F4 of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view taken along line F5-F5 of the semiconductor device shown in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view taken along line F6-F6 of the semiconductor device shown in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view taken along line F7-F7 of the semiconductor device shown in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view taken along line F8-F8 of the semiconductor device shown in FIG. [Figure 9] FIG. 9 is an exemplary schematic plan view of the semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a schematic plan view showing the arrangement of cell trenches and field plate trenches provided in the semiconductor layer of the semiconductor device shown in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view taken along line F11-F11 of the semiconductor device shown in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view taken along line F12-F12 of the semiconductor device shown in FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view taken along line F13-F13 of the semiconductor device shown in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view taken along line F14-F14 of the semiconductor device shown in FIG. [Figure 15] FIG. 15 is an exemplary schematic plan view of the semiconductor device according to the third embodiment. [Figure 16]FIG. 16 is a schematic cross-sectional view taken along line F16-F16 of the semiconductor device shown in FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view taken along line F17-F17 of the semiconductor device shown in FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view of a semiconductor device according to a modified example.

[0007] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] First Embodiment [Planar structure of semiconductor device] The planar structure of a semiconductor device 10 according to a first embodiment will be described with reference to Figures 1 and 2. Figure 1 is a schematic plan view of an exemplary semiconductor device 10 according to the first embodiment. Figure 2 is a schematic plan view showing the arrangement of cell trenches and field plate trenches provided in a semiconductor layer of the semiconductor device shown in Figure 1.

[0010] As shown in FIG. 1, the semiconductor device 10 may be, for example, a metal insulator semiconductor field effect transistor (MISFET) having a trench gate structure. The semiconductor device 10 may include a semiconductor layer 12 and an insulating layer 16 provided on the semiconductor layer 12. The Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in FIG. 1 is a direction perpendicular to the plane of the semiconductor layer 12. Note that the term "plan view" used in this disclosure refers to viewing the semiconductor device 10 from above along the Z-axis direction, unless explicitly stated otherwise.

[0011] 1, the semiconductor layer 12 is covered with an insulating layer 16, and therefore the reference numeral 12 indicates the rectangular outer edge of the semiconductor layer 12. The area defined by the outer edge of the semiconductor layer 12 shown in FIG. 1 may correspond to one chip (die). The insulating layer 16 may include at least one of a silicon oxide (SiO2) layer and a silicon nitride (SiN) layer.

[0012] The semiconductor device 10 may further include a gate wiring 24 provided on the insulating layer 16, and a source wiring 22 provided on the insulating layer 16 and spaced apart from the gate wiring 24. The source wiring 22 may be spaced apart from the gate wiring 24 by a predetermined distance (determined, for example, in consideration of the breakdown voltage, etc.). The gate wiring 24 and the source wiring 22 may be made of at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a copper alloy, and an aluminum alloy.

[0013] The semiconductor layer 12 includes a first side surface 101 and a second side surface 102 which are both side surfaces in the Y-axis direction in a plan view, and a third side surface 103 and a fourth side surface 104 which are both side surfaces in the X-axis direction. The semiconductor layer 12 has a rectangular shape with its short side direction in the X-axis direction and its long side direction in the Y-axis direction.

[0014] The semiconductor layer 12 includes an outer peripheral region 34 and an inner region 32 having a rectangular outer edge surrounded by the outer peripheral region 34 in a planar view. The boundary between the outer peripheral region 34 and the inner region 32 is indicated by a two-dot chain line in FIG. 1 . The outer edge of the outer peripheral region 34 may coincide with the outer edge of the semiconductor layer 12 in a planar view, or may be located inside the outer edge of the semiconductor layer 12. In one example, the outer peripheral region 34 may be located between the outer edge of the semiconductor layer 12 and the inner region 32. The rectangular outer edge of the inner region 32 has two sides extending along the Y-axis direction and two sides extending along the X-axis direction in a planar view. Note that in this specification, the Y-axis direction may be referred to as the first direction, and the X-axis direction may be referred to as the second direction. The second direction is a direction perpendicular to the first direction in a planar view.

[0015] The gate wiring 24 may include a plurality of outer periphery gate fingers 26 arranged in the outer periphery region 34. In the example of Fig. 1, the plurality of outer periphery gate fingers 26 may include four outer periphery gate fingers 26A to 26D. More specifically, the plurality of outer periphery gate fingers 26 may include a first outer periphery gate finger 26A and a second outer periphery gate finger 26B extending along the Y-axis direction, and a third outer periphery gate finger 26C and a fourth outer periphery gate finger 26D extending along the X-axis direction.

[0016] The first outer peripheral gate finger 26A may be arranged on the third side 103 side of the semiconductor layer 12 in a planar view, the second outer peripheral gate finger 26B on the fourth side 104 side, the third outer peripheral gate finger 26C on the first side 101 side, and the fourth outer peripheral gate finger 26D on the second side 102 side.

[0017] The third outer peripheral gate finger 26C may be connected to the second outer peripheral gate finger 26B at a corner portion defined by the first side surface 101 and the fourth side surface 104 of the semiconductor layer 12 in plan view. The first outer peripheral gate finger 26A may be connected to the fourth outer peripheral gate finger 26D at a corner portion defined by the second side surface 102 and the third side surface 103.

[0018] The gate wiring 24 may include a gap 30 that separates the outer peripheral gate fingers 26. The tip of the first outer peripheral gate finger 26A and the tip of the third outer peripheral gate finger 26C are located at the same position in the X-axis direction. The first outer peripheral gate finger 26A and the third outer peripheral gate finger 26C may be separated from each other by the gap 30 that is located along the outer edge of the inner region 32.

[0019] The gate wiring 24 may include a gate pad 25 arranged in a corner portion defined by the second side surface 102 and the fourth side surface 104 of the semiconductor layer 12 in a plan view. The gate pad 25 may be rectangular. The gate pad 25 may be provided on the insulating layer 16. The gate pad 25 is electrically connected to a plurality of gate electrodes 58 (described later) via the peripheral gate fingers 26. In the example of FIG. 1 , the gate pad 25 may be connected to the second peripheral gate finger 26B and the fourth peripheral gate finger 26D.

[0020] 1, the multiple outer periphery segments 28 may include four outer periphery segments 28A to 28D. More specifically, the multiple outer periphery segments 28 may include a first outer periphery segment 28A and a second outer periphery segment 28B extending along the Y-axis direction, and a third outer periphery segment 28C and a fourth outer periphery segment 28D extending along the X-axis direction.

[0021] The first outer perimeter segment 28A may be disposed between the first outer perimeter gate finger 26A and the third side surface 103 of the semiconductor layer 12 in the X-axis direction in a plan view. The first outer perimeter segment 28A is disposed spaced apart from both the first outer perimeter gate finger 26A and the third side surface 103 in a plan view. The second outer perimeter segment 28B may be disposed between the second outer perimeter gate finger 26B and the fourth side surface 104 of the semiconductor layer 12 in the X-axis direction. The second outer perimeter segment 28B is disposed spaced apart from both the second outer perimeter gate finger 26B and the fourth side surface 104. The third outer perimeter segment 28C may be disposed between the third outer perimeter gate finger 26C and the semiconductor layer 12 in the Y-axis direction. The third outer perimeter segment 28C is disposed spaced apart from both the third outer perimeter gate finger 26C and the first side surface 101. The fourth outer perimeter segment 28D may be disposed between the fourth outer perimeter gate finger 26D and the second side surface 102 of the semiconductor layer 12 in the Y-axis direction. The fourth perimeter segment 28D is spaced apart from both the fourth perimeter gate finger 26D and the second side surface 102.

[0022] Third perimeter segment 28C may be connected to second perimeter segment 28B at a corner formed by first side surface 101 and fourth side surface 104 of semiconductor layer 12 in a plan view. First perimeter segment 28A may be connected to fourth perimeter segment 28D at a corner formed by second side surface 102 and third side surface 103. First perimeter segment 28A may be connected to third perimeter segment 28C at a corner formed by first side surface 101 and third side surface 103.

[0023] The inner segment 23 may be disposed in the inner region 32, spaced apart from the first outer periphery gate finger 26A, the second outer periphery gate finger 26B, the third outer periphery gate finger 26C, the fourth outer periphery gate finger 26D, and the gate pad 25. The inner segment 23 and the first outer periphery segment 28A may be connected to each other across a gap 30 while being spaced apart from the first outer periphery gate finger 26A and the third outer periphery gate finger 26C. The inner segment 23 and the outer periphery segment 28 may be provided integrally.

[0024] As shown in FIG. 2 , the semiconductor layer 12 includes an isolation region 38 located away from the gate pad 25 and a proximity region 36 located closer to the gate pad 25 than the isolation region 38. In the example shown in FIG. 2 , the isolation region 38 includes a first isolation region 38A, a second isolation region 38B, and a third isolation region 38C. The proximity region 36 includes a first proximity region 36A and a second proximity region 36B. Each of the proximity region 36 and the isolation region 38 is a region where a plurality of cell trenches 14 (described later) is provided. The plurality of cell trenches 14 is provided in the semiconductor layer 12. Therefore, it can be said that the semiconductor device 10 includes a plurality of cell trenches 14 provided in the semiconductor layer 12.

[0025] The first proximity region 36A is disposed closer to the third side surface 103 than the gate pad 25. The first proximity region 36A is adjacent to the gate pad 25. In the example shown in FIG. 2, the first proximity region 36A has a rectangular shape with its longer side in the X-axis direction and its shorter side in the Y-axis direction in a plan view. The dimension of the first proximity region 36A in the X-axis direction is larger than the dimension of the gate pad 25 in the X-axis direction. The dimension of the first proximity region 36A in the Y-axis direction is approximately equal to the dimension of the gate pad 25 in the Y-axis direction.

[0026] The second proximity region 36B is arranged closer to the first side surface 101 than the gate pad 25. The second proximity region 36B is adjacent to the gate pad 25. That is, the second proximity region 36B is arranged at a position adjacent to the gate pad 25, but at a different position from the first proximity region 36A, relative to the gate pad 25. The second proximity region 36B is arranged shifted in the Y-axis direction relative to the first proximity region 36A. More specifically, the second proximity region 36B is arranged closer to the first side surface 101 than the first proximity region 36A in the semiconductor layer 12. The second proximity region 36B includes a portion overlapping with the first proximity region 36A when viewed from the Y-axis direction.

[0027] 2, the second proximity region 36B has a rectangular shape with its short side in the X-axis direction and its long side in the Y-axis direction in plan view. In plan view, the area of ​​the second proximity region 36B may be larger than the area of ​​the first proximity region 36A. In the example shown in FIG. 2, the dimension of the second proximity region 36B in the X-axis direction is larger than the dimension of the first proximity region 36A in the X-axis direction. The dimension of the second proximity region 36B in the Y-axis direction is larger than the dimension of the first proximity region 36A in the Y-axis direction. In one example, in plan view, the area of ​​the second proximity region 36B may be at least twice the area of ​​the first proximity region 36A.

[0028] The first to third isolated regions 38A to 38C are provided at positions farther away from the gate pad 25 than the first proximity region 36A and the second proximity region 36B. The second isolated region 38B may be disposed on the opposite side of the gate pad 25 from the second proximity region 36B. The second isolated region 38B is located closer to the first side surface 101 than the second proximity region 36B. The second isolated region 38B is adjacent to the second proximity region 36B. When viewed from the Y-axis direction, the second isolated region 38B can be said to include a portion that overlaps with the second proximity region 36B. Furthermore, when viewed from the Y-axis direction, the second isolated region 38B may include a region that extends beyond the second proximity region 36B toward the third side surface 103.

[0029] In the example shown in FIG. 2, the second distant region 38B has a rectangular shape with its longer side in the X-axis direction and its shorter side in the Y-axis direction. In a plan view, the area of ​​the second distant region 38B may be larger than the area of ​​the second nearby region 36B. In the example shown in FIG. 2, the dimension of the second distant region 38B in the X-axis direction is larger than the dimension of the second nearby region 36B in the X-axis direction. The dimension of the second distant region 38B in the Y-axis direction is approximately equal to the dimension of the second nearby region 36B in the Y-axis direction. In one example, in a plan view, the area of ​​the second distant region 38B may be 1.5 to 2 times the area of ​​the second nearby region 36B.

[0030] The first isolated region 38A may be located on the opposite side of the first proximity region 36A from the gate pad 25. The first isolated region 38A may be located closer to the third side surface 103 than the first proximity region 36A. The first isolated region 38A may be adjacent to the first proximity region 36A. Therefore, the first isolated region 38A is separated from the second isolated region 38B in the Y-axis direction.

[0031] 2, the first distant region 38A has a rectangular shape with its long side in the X-axis direction and its short side in the Y-axis direction in plan view. In plan view, the area of ​​the first distant region 38A may be smaller than the area of ​​the first nearby region 36A. The dimension of the first distant region 38A in the X-axis direction is approximately equal to the dimension of the first nearby region 36A in the X-axis direction. The dimension of the first distant region 38A in the Y-axis direction is smaller than the dimension of the first nearby region 36A in the Y-axis direction.

[0032] The third isolated region 38C may be located on the opposite side of the gate pad 25 with respect to the first proximity region 36A and the second proximity region 36B. The third isolated region 38C may be located adjacent to the second proximity region 36B in the X-axis direction. In the example shown in FIG. 2 , the third isolated region 38C is located in the semiconductor layer 12 closer to the third side surface 103 than the second proximity region 36B. The third isolated region 38C may be located in the same position as the second proximity region 36B in the Y-axis direction. The third isolated region 38C may be located adjacent to the first proximity region 36A in the Y-axis direction. The third isolated region 38C may be located adjacent to the first isolated region 38A in the Y-axis direction. The third isolated region 38C is located in the semiconductor layer 12 closer to the first side surface 101 than the first proximity region 36A and the first isolated region 38A. The third isolated region 38C may be disposed in a position adjacent to the second isolated region 38B in the Y-axis direction. The third isolated region 38C is located closer to the second side surface 102 than the second isolated region 38B in the semiconductor layer 12. In this way, the third isolated region 38C may be located between the second isolated region 38B and the first isolated region 38A and the first adjacent region 36A in the Y-axis direction.

[0033] 2, the third separate region 38C has a rectangular shape with its short side oriented in the X-axis direction and its long side oriented in the Y-axis direction in plan view. In plan view, the area of ​​the third separate region 38C may be equal to the area of ​​the second proximity region 36B.

[0034] [Configuration of the second proximity region] The configuration of the second proximity region 36B will be described with reference to Figures 2 to 4. Figure 3 is a schematic cross-sectional view of the semiconductor device 10 taken along line F3-F3 in Figure 2. Figure 3 shows three cell trenches 14 provided in the second proximity region 36B. Figure 4 is a schematic cross-sectional view of the semiconductor device shown in Figure 3 taken along line F4-F4.

[0035] First, the configuration of the semiconductor layer 12 will be described with reference to Fig. 3. The configuration of the semiconductor layer 12 is common to the proximity region 36 and the isolation region 38. As shown in FIG. 3 , the semiconductor layer 12 may include a top surface 12A and a bottom surface 12B opposite the top surface 12A. The Z-axis direction may be perpendicular to the top surface 12A and the bottom surface 12B of the semiconductor layer 12. The semiconductor layer 12 may include a semiconductor substrate 40 and an epitaxial layer 42 provided on the semiconductor substrate 40. The semiconductor substrate 40 may include the bottom surface 12B of the semiconductor layer 12. The epitaxial layer 42 may include the top surface 12A of the semiconductor layer 12. In this embodiment, the semiconductor substrate 40 may be a Si substrate. Furthermore, the epitaxial layer 42 may be a Si epitaxial layer. The semiconductor substrate 40 may correspond to the drain region of the MISFET.

[0036] In the semiconductor layer 12 in which the cell trench 14 is arranged, the epitaxial layer 42 may include a drift region 44 provided on the semiconductor substrate 40 (drain region), a body region 46 provided on the drift region 44, and a source region 48 provided on the body region 46. In other words, the semiconductor layer 12 has the body region 46.

[0037] The drain region provided in the semiconductor substrate 40 may be an n-type region containing n-type impurities. The n-type impurity concentration of the semiconductor substrate 40 is 1×1018 cm -3 More than 1×10 20 cm -3 The semiconductor substrate 40 may have a thickness of 50 μm or more and 450 μm or less.

[0038] The drift region 44 may be an n-type region containing n-type impurities at a concentration lower than that of the semiconductor substrate 40 (drain region). The n-type impurity concentration of the drift region 44 is 1×10 15 cm -3 More than 1×10 18 cm -3 The drift region 44 may have a thickness of 1 μm or more and 25 μm or less.

[0039] The body region 46 may be a p-type region containing p-type impurities. The p-type impurity concentration of the body region 46 is 1×10 16 cm -3 More than 1×10 18 cm -3 The body region 46 may have a thickness of not less than 0.2 μm and not more than 1.0 μm.

[0040] The source region 48 may be an n-type region containing n-type impurities at a higher concentration than the drift region 44. The n-type impurity concentration of the source region 48 is 1×10 19 cm -3 More than 1×10 21 cm -3 The source region 48 may have a thickness of 0.1 μm or more and 1 μm or less.

[0041] In this disclosure, n-type is also referred to as the first conductivity type, and p-type is also referred to as the second conductivity type. The n-type impurity may be, for example, phosphorus (P) or arsenic (As). The p-type impurity may be, for example, boron (B) or aluminum (Al).

[0042] The semiconductor device 10 may further include a drain wiring 50 provided on the bottom surface 12B of the semiconductor layer 12. The drain wiring 50 is electrically connected to the semiconductor substrate 40 (drain region). The drain wiring 50 may be made of at least one of Ti, Ni, Au, Ag, Cu, Al, a Cu alloy, and an Al alloy.

[0043] Next, the configuration of the multiple cell trenches 14 in the second proximity region 36B will be described. As shown in FIG. 2, each of the multiple cell trenches 14 extends along the X-axis direction in plan view. The multiple cell trenches 14 are arranged at the same positions as each other in the X-axis direction and spaced apart from each other in the Y-axis direction. The multiple cell trenches 14 are arranged across the inner region 32 and the outer periphery region 34. The multiple cell trenches 14 intersect with the second outer periphery gate fingers 26B in plan view. Each cell trench 14 has a strip shape that has a width in the Y-axis direction and extends in the X-axis direction in plan view. The following describes the configuration of one cell trench 14 and its surroundings.

[0044] As shown in FIG. 3 , the cell trench 14 provided in the semiconductor layer 12 may have an opening in the upper surface 12A of the semiconductor layer 12 and may have a depth in the Z-axis direction. The cell trench 14 may have sidewalls 14A and a bottom wall 14B. The cell trench 14 may extend through the source region 48 and the body region 46 of the epitaxial layer 42 to reach the drift region 44. Therefore, the bottom wall 14B of the cell trench 14 may be adjacent to the drift region 44. The cell trench 14 may have a depth of 1 μm or more and 10 μm or less. The depth of the cell trench 14 may correspond to the distance in the Z-axis direction from the upper surface 12A of the semiconductor layer 12 to the bottom wall 14B of the cell trench 14. Hereinafter, the Z-axis direction may be referred to as the "depth direction of the cell trench 14" or the "trench depth direction."

[0045] The sidewalls 14A of the cell trench 14 may extend in the Z-axis direction (a direction perpendicular to the upper surface 12A of the semiconductor layer 12) or may be inclined with respect to the Z-axis direction. In one example, the sidewalls 14A may be inclined with respect to the Z-axis direction so that the width of the cell trench 14 decreases toward the bottom wall 14B. The bottom wall 14B of the cell trench 14 does not necessarily have to be flat; for example, it may be partially or entirely curved. Here, the width of the cell trench 14 is the dimension in a direction perpendicular to the direction in which the cell trench 14 extends in a plan view. In the example shown in FIG. 3, the width of the cell trench 14 may correspond to the dimension of the cell trench 14 in the Y-axis direction.

[0046] The semiconductor device 10 may further include a plurality of gate electrodes 58 and a plurality of first field plate electrodes 60. In one example, the plurality of gate electrodes 58 and the plurality of first field plate electrodes 60 may be made of conductive polysilicon. In another example, the plurality of gate electrodes 58 and the plurality of first field plate electrodes 60 may be made of any other metallic material. An insulating layer 16 may be provided within the plurality of cell trenches 14.

[0047] The gate electrode 58 may be embedded in the multiple cell trenches 14 via the insulating layer 16. The multiple gate electrodes 58 are electrically connected to the gate wiring 24 (see FIG. 2). The first field plate electrode 60 may be embedded in the cell trench 14 via the insulating layer 16 while being spaced apart from the gate electrode 58. The gate electrode 58 may be configured to receive a gate voltage, and the first field plate electrode 60 may be configured to receive a source voltage or a voltage different from the source voltage. In one example, the first field plate electrode 60 may be configured to receive a gate voltage.

[0048] 3, a gate electrode 58 and a first field plate electrode 60 are buried in the cell trench 14. In another example, only the gate electrode 58 may be buried in the cell trench 14.

[0049] The gate electrode 58 may include an upper surface 58A covered by the insulating layer 16 and a bottom surface 58B opposite the upper surface 58A. The first field plate electrode 60 may be disposed below the gate electrode 58 in the cell trench 14. More specifically, the first field plate electrode 60 may be disposed between the bottom surface 58B of the gate electrode 58 and the bottom wall 14B of the cell trench 14. At least a portion of the bottom surface 58B of the gate electrode 58 may face the first field plate electrode 60 with the insulating layer 16 interposed therebetween. The gate electrode 58 may further include a side surface 58C facing the sidewall 14A of the cell trench 14.

[0050] An upper surface 58A of the gate electrode 58 may be located lower than an upper surface 12A of the semiconductor layer 12. A bottom surface 58B of the gate electrode 58 may be located near the interface between the drift region 44 and the body region 46 in the Z-axis direction, and preferably lower than the interface. The upper surface 58A and the bottom surface 58B of the gate electrode 58 may be flat or curved.

[0051] The gate electrode 58 and the first field plate electrode 60 may be surrounded by an insulating layer 16. The first field plate electrode 60 may have a smaller width than the gate electrode 58 when viewed in the X-axis direction. Because the first field plate electrode 60 has a smaller width than the gate electrode 58, the thickness of the insulating layer 16 surrounding the first field plate electrode 60 is greater than the thickness of the insulating layer 16 surrounding the gate electrode 58.

[0052] The insulating layer 16 may include a gate insulating portion 66 interposed between the gate electrode 58 and the semiconductor layer 12 and covering the sidewall 14A of the cell trench 14. The gate insulating portion 66 is a portion of the insulating layer 16 located between the side surface 58C of the gate electrode 58 and the sidewall 14A of the cell trench 14. The gate electrode 58 faces the semiconductor layer 12 via the gate insulating portion 66. The thickness of the gate insulating portion 66 may be constant or may not be constant. As an example of a configuration in which the thickness of the gate insulating portion 66 is not constant, the thickness of the gate insulating portion 66 at a portion where the side surface 58C of the gate electrode 58 faces the drift region 44 may be greater than the thickness of the portions where the side surface 58C faces the source region 48 and the body region 46. This reduces the electrostatic capacitance Cgd between the gate electrode 58 and the drift region 44.

[0053] When a predetermined voltage is applied to the gate electrode 58, a channel is induced in the p-type body region 46 adjacent to the gate insulating portion 66. The semiconductor device 10 can control the flow of electrons in the Z-axis direction between the n-type source region 48 and the n-type drift region 44 via this channel. Furthermore, because the first field plate electrode 60 is electrically connected to the source wiring 22, it is possible to alleviate electric field concentration in the drift region 44 between the cell trenches 14. This can improve the breakdown voltage of the semiconductor device 10.

[0054] 2 and 4, the semiconductor device 10 may include a gate contact 68 provided in the insulating layer 16. The gate contact 68 connects the gate wiring 24 (peripheral gate finger 26) and the gate electrode 58. As shown in FIG. 4, the gate electrode 58 is disposed above the first field plate electrode 60 and is connected to the peripheral gate finger 26 (second peripheral gate finger 26B in FIG. 4) via the gate contact 68.

[0055] 2 , each of the multiple cell trenches 14 can be arranged to intersect with at least one of the multiple peripheral gate fingers 26 in a plan view. The gate electrode 58 embedded in each cell trench 14 can be connected to at least one of the multiple peripheral gate fingers 26 via at least one of the multiple gate contacts 68. The gate contacts 68 can be arranged in regions where each of the multiple cell trenches 14 intersects with the peripheral gate fingers 26 in a plan view.

[0056] As shown in FIG. 2, the semiconductor device 10 may further include a field plate trench 18. The field plate trench 18 is provided to surround the multiple cell trenches 14 in a plan view. In the example shown in FIG. 2, the field plate trench 18 has a rectangular ring shape in a plan view. The field plate trench 18 is provided on the periphery of the second proximity region 36B. The field plate trench 18 may include two end field plate trenches 18P and two outer field plate trenches 18Q. The end field plate trench 18P communicates with each end of the multiple cell trenches 14. In other words, the end field plate trench 18P can be configured to communicate the multiple cell trenches 14 at their ends. Each outer field plate trench 18Q extends parallel to the cell trench 14. The multiple cell trenches 14 and the outer field plate trench 18Q are arranged at a first interval G1 in the Y-axis direction. The multiple cell trenches 14 intersect with the second outer periphery gate fingers 26B in plan view.

[0057] As shown in FIG. 3 , the field plate trench 18 may have an opening in the upper surface 12A of the semiconductor layer 12 and may have a depth in the Z-axis direction. The field plate trench 18 may have sidewalls 18A and a bottom wall 18B. The field plate trench 18 may extend through the body region 46 of the epitaxial layer 42 to reach the drift region 44. Therefore, the bottom wall 18B of the field plate trench 18 is adjacent to the drift region 44. The field plate trench 18 may have a depth of 1 μm or more and 10 μm or less. The depth of the field plate trench 18 may correspond to the distance in the Z-axis direction from the upper surface 12A of the semiconductor layer 12 to the bottom wall 18B of the field plate trench 18.

[0058] Sidewalls 18A of field plate trench 18 may extend along the Z-axis direction or may be inclined relative to the Z-axis direction. In one example, sidewalls 18A may be inclined relative to the Z-axis direction so that the width of field plate trench 18 decreases toward bottom wall 18B. Bottom wall 18B of field plate trench 18 does not necessarily have to be flat; for example, it may be partially or entirely curved. Here, the width of field plate trench 18 is the dimension in a direction perpendicular to the direction in which field plate trench 18 extends in a plan view. In the example shown in FIG. 3, the width of field plate trench 18 may correspond to the dimension of cell trench 14 in the Y-axis direction.

[0059] The semiconductor device 10 may include a second field plate electrode 80. In one example, the multiple second field plate electrodes 80 may be made of conductive polysilicon. In another example, they may be made of any metal material. An insulating layer 16 is provided in the field plate trench 18. The second field plate electrode 80 is provided corresponding to the field plate trench 18. In one example, the second field plate electrode 80 provided in the rectangular ring-shaped field plate trench 18 may have a rectangular ring shape in a plan view. The second field plate electrode 80 may be embedded in the insulating layer 16 provided in the field plate trench 18. The second field plate electrode 80 may be electrically connected to the source wiring 22.

[0060] The second field plate electrode 80 is surrounded by the insulating layer 16. The second field plate electrode 80 may have a width smaller than that of the gate electrode 58. Because the second field plate electrode 80 has a width smaller than that of the gate electrode 58, the thickness of the insulating layer 16 surrounding the second field plate electrode 80 is greater than the thickness of the insulating layer 16 surrounding the gate electrode 58.

[0061] An upper end 80A of the second field plate electrode 80 may be located higher in the Z direction than the bottom surface 58B of the gate electrode 58. The upper end 80A of the second field plate electrode 80 may be covered with the insulating layer 16.

[0062] As shown in Figure 4, cell trench 14 and end field plate trench 18P are arranged in the cross section of the XZ plane from the center of inner segment 23 in the X-axis direction through second outer gate finger 26B to second outer segment 28B.

[0063] The second field plate electrode 80 includes a first end electrode 81A and a second end electrode 81B provided in two end field plate trenches 18P. The first end electrode 81A is provided in one of the end field plate trenches 18P. The second end electrode 81B is provided in the other end field plate trench 18P. Therefore, the first end electrode 81A and the second end electrode 81B are spaced apart in the X-axis direction. Furthermore, each of the first end electrode 81A and the second end electrode 81B extends in the Y-axis direction in plan view. Furthermore, no gate electrode 58 is present above each of the first end electrode 81A and the second end electrode 81B.

[0064] The first field plate electrode 60 provided in each cell trench 14 includes a first end electrode 61A and a second end electrode 61B that extend from the cell trench 14 into the two end field plate trenches 18P. The first end electrode 61A of the first field plate electrode 60 is connected to the first end electrode 81A in one end field plate trench 18P. The second end electrode 61B of the first field plate electrode 60 is connected to the second end electrode 81B in the remaining end field plate trench 18P. The first field plate electrode 60 and the second field plate electrode 80 may be provided integrally.

[0065] The semiconductor device 10 may further include a plurality of field plate contacts 78. One of the plurality of field plate contacts 78 may penetrate the insulating layer 16 in the Z-axis direction and be connected to the first end electrode 81A. Another of the plurality of field plate contacts 78 may penetrate the insulating layer 16 in the Z-axis direction and be connected to the second end electrode 81B. As a result, the first end electrode 81A may be connected to the second outer peripheral segment 28B via the field plate contact 78. The second end electrode 81B may be connected to the inner segment 23 via the field plate contact 78. In this way, the second field plate electrode 80 is electrically connected to the source wiring 22, thereby alleviating electric field concentration in the drift region 44 adjacent to the field plate trench 18. This improves the breakdown voltage of the semiconductor device 10.

[0066] Next, the mesa region 20 will be described with reference to FIG. The semiconductor device 10 includes a mesa region 20, which is a region between two adjacent cell trenches 14 among the plurality of cell trenches 14 in a plan view.

[0067] The epitaxial layer 42 in the mesa region 20 may include a drift region 44 , a body region 46 , and a source region 48 . The semiconductor device 10 may further include a plurality of source contacts 62 connected to the source wiring 22. The plurality of source contacts 62 are respectively arranged between two adjacent cell trenches 14 among the plurality of cell trenches 14 in a plan view. Each source contact 62 may extend parallel to the cell trench 14 in a plan view. The source contact 62 may be a plug embedded in an insulating layer 16 configured to be rectangular in a plan view and groove-shaped in a cross-sectional view. The source contact 62 penetrates the insulating layer 16 to reach the body region 46 of the mesa region 20.

[0068] The epitaxial layer 42 in the mesa region 20 may further include a contact region 64 in the body region 46. The contact region 64 may be a p-type region containing p-type impurities. The p-type impurity concentration of the contact region 64 may be higher than that of the body region 46. The p-type impurity concentration of the contact region 64 may be, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The source contact 62 extends from the contact portion between the source contact 62 and the source wiring 22, through the insulating layer 16 and the source region 48 provided in the surface portion of the body region 46, and so as to contact the contact region 64.

[0069] [Configuration of the first proximity region] The configuration of the first proximity region 36A will be described with reference to Figures 2 and 5. Figure 5 is a schematic cross-sectional view taken along line F5-F5 of the semiconductor device 10 shown in Figure 2. Figure 5 shows three cell trenches 14 and one peripheral field plate trench 18Q provided in the first proximity region 36A.

[0070] As shown in FIG. 2, the multiple cell trenches 14 provided in the first proximity region 36A extend in the Y-axis direction in plan view and are spaced apart in the X-axis direction. The multiple cell trenches 14 and the peripheral field plate trench 18Q provided in the first proximity region 36A are arranged at a first interval G1 in the X-axis direction. The field plate trench 18 is provided to surround the multiple cell trenches 14 in plan view. In the example shown in FIG. 2, the field plate trench 18 has a quadrangular ring shape in plan view. The end field plate trench 18P provided in the first proximity region 36A communicates with each of the multiple cell trenches 14 provided in the first proximity region 36A. The multiple cell trenches 14 intersect with the fourth peripheral gate finger 26D in plan view. Gate electrodes 58 provided in the multiple cell trenches 14 are connected to the gate wiring 24 via gate contacts 68 arranged at positions intersecting with the fourth peripheral gate finger 26D. The cell trenches 14 are arranged across the inner region 32 and the outer periphery region 34 .

[0071] The widths of the cell trenches 14 and peripheral field plate trenches 18Q in the first proximity region 36A are the same as the widths of the cell trenches 14 and peripheral field plate trenches 18Q in the second proximity region 36B. The planar configurations of the cell trenches 14 and field plate trenches 18 in the first proximity region 36A are the same as those in the second proximity region 36B. However, the number of cell trenches 14 in the first proximity region 36A is fewer than the number of cell trenches 14 in the second proximity region 36B because the length of the first proximity region 36A in the X-axis direction is shorter than the length of the second proximity region 36B in the Y-axis direction. The length of the cell trenches 14 in the first proximity region 36A is shorter than the length of the cell trenches 14 in the second proximity region 36B because the length of the first proximity region 36A in the Y-axis direction is shorter than the length of the second proximity region 36B in the X-axis direction.

[0072] As shown in FIG. 5, an insulating layer 16, a gate electrode 58, and a first field plate electrode 60 are provided in the cell trench 14 in the first proximity region 36A, similar to the second proximity region 36B. Similarly to the second proximity region 36B, an insulating layer 16 and a second field plate electrode 80 are provided in the peripheral field plate trench 18Q in the first proximity region 36A. The first field plate electrode 60 and the second field plate electrode 80 may be integrated, similar to the second proximity region 36B. Also, as shown in FIG. 5, the configuration of the mesa region 20 in the first proximity region 36A is the same as the configuration of the mesa region 20 in the second proximity region 36B. As shown in FIG. 2, the multiple mesa regions 20 in the first proximity region 36A extend in the Y-axis direction.

[0073] The source contacts 62 provided in each of the multiple mesa regions 20 in the first proximity region 36A extend in the Y-axis direction in plan view. As shown in Fig. 5 , the source contacts 62 in the first proximity region 36A, like the second proximity region 36B, penetrate the source region 48 and reach the body region 46. Like the second proximity region 36B, the source contacts 62 are in contact with a contact region 64 provided in the body region 46.

[0074] [Configuration of the first isolated area] The configuration of first isolation region 38A will be described with reference to Figure 2 and Figure 6. Figure 6 is a schematic cross-sectional view taken along line F6-F6 of semiconductor device 10 shown in Figure 2. Figure 6 shows one cell trench 14 and two peripheral field plate trenches 18Q provided in first isolation region 38A.

[0075] As shown in FIG. 2, the cell trench 14 in the first isolation region 38A extends in the X-axis direction in plan view and is spaced apart from the peripheral field plate trench 18Q in the Y-axis direction. The cell trench 14 and the peripheral field plate trench 18Q in the first isolation region 38A are arranged at a first interval G1 in the Y-axis direction. The field plate trench 18 is arranged to surround the cell trench 14 in plan view. In the example shown in FIG. 2, the field plate trench 18 has a quadrangular ring shape in plan view. The end field plate trench 18P in the first isolation region 38A is connected to the cell trench 14 in the first isolation region 38A. The cell trench 14 intersects with the first peripheral gate finger 26A in plan view. The gate electrode 58 in the cell trench 14 is connected to the gate wiring 24 via a gate contact 68 located at a position intersecting the first peripheral gate finger 26A. The cell trench 14 is disposed across the inner region 32 and the outer periphery region 34 .

[0076] The widths of the cell trenches 14 and peripheral field plate trenches 18Q in the first isolation region 38A are the same as the widths of the cell trenches 14 and peripheral field plate trenches 18Q in the second proximity region 36B. The planar configurations of the cell trenches 14 and field plate trenches 18 in the first isolation region 38A are the same as those in the second proximity region 36B. However, the number of cell trenches 14 in the first isolation region 38A is fewer than the number of cell trenches 14 in the second proximity region 36B because the length in the Y-axis direction of the first proximity region 36A is shorter than the length in the Y-axis direction of the second proximity region 36B. The length of the cell trenches 14 in the first isolation region 38A is shorter than the length of the cell trenches 14 in the second proximity region 36B because the length in the X-axis direction of the first proximity region 36A is shorter than the length in the X-axis direction of the second proximity region 36B.

[0077] As shown in FIG. 6, an insulating layer 16, a gate electrode 58, and a first field plate electrode 60 are provided in the cell trench 14 in the first isolation region 38A, similar to the second proximity region 36B. Also, an insulating layer 16 and a second field plate electrode 80 are provided in the peripheral field plate trench 18Q in the first isolation region 38A, similar to the second proximity region 36B. The first field plate electrode 60 and the second field plate electrode 80 may be integrated, similar to the second proximity region 36B. Also, as shown in FIG. 5, the configuration of the mesa region 20 in the first isolation region 38A is the same as the configuration of the mesa region 20 in the second proximity region 36B. As shown in FIG. 2, the multiple mesa regions 20 in the first isolation region 38A extend in the X-axis direction.

[0078] The source contact 62 provided in each of the multiple mesa regions 20 in the first isolation region 38A extends in the X-axis direction in plan view. As shown in Fig. 6, the source contact 62 in the first isolation region 38A, like the second proximity region 36B, penetrates the source region 48 and reaches the body region 46. Like the second proximity region 36B, the source contact 62 is in contact with a contact region 64 provided in the body region 46.

[0079] [Configuration of the second isolated area] The configuration of second isolation region 38B will be described with reference to Figures 2 and 8. Figure 8 is a schematic cross-sectional view taken along line F8-F8 of the semiconductor device shown in Figure 2. Figure 8 shows three cell trenches 14 and one peripheral field plate trench 18Q provided in second isolation region 38B.

[0080] As shown in FIG. 2, the multiple cell trenches 14 provided in the second isolation region 38B extend in the Y-axis direction in plan view and are spaced apart in the X-axis direction. The multiple cell trenches 14 and the peripheral field plate trench 18Q provided in the second isolation region 38B are arranged at a first interval G1 in the X-axis direction. The field plate trench 18 is provided to surround the multiple cell trenches 14 in plan view. In the example shown in FIG. 2, the field plate trench 18 has a quadrangular ring shape in plan view. The end field plate trench 18P provided in the second isolation region 38B communicates with each of the multiple cell trenches 14 provided in the second isolation region 38B. The multiple cell trenches 14 intersect with the third peripheral gate finger 26C in plan view. The gate electrodes 58 provided in the multiple cell trenches 14 are connected to the gate wiring 24 via gate contacts 68 arranged at positions intersecting with the third peripheral gate finger 26C. The cell trenches 14 are arranged across the inner region 32 and the outer periphery region 34 .

[0081] The widths of the cell trenches 14 and peripheral field plate trenches 18Q provided in the second isolation region 38B are the same as the widths of the cell trenches 14 and peripheral field plate trenches 18Q provided in the second proximity region 36B. The planar configurations of the cell trenches 14 and field plate trenches 18 provided in the second isolation region 38B are the same as those in the second proximity region 36B. However, the number of cell trenches 14 provided in the second isolation region 38B is greater than the number of cell trenches 14 provided in the second proximity region 36B because the length of the second isolation region 38B in the Y-axis direction is longer than the length of the second proximity region 36B in the X-axis direction. The length of the cell trenches 14 provided in the second isolation region 38B is longer than the length of the cell trenches 14 provided in the second proximity region 36B because the length of the second isolation region 38B in the X-axis direction is longer than the length of the second proximity region 36B in the X-axis direction.

[0082] As shown in FIG. 8 , an insulating layer 16, a gate electrode 58, and a first field plate electrode 60 are provided in the cell trench 14 in the second isolation region 38B, similar to the second proximity region 36B. Also, an insulating layer 16 and a second field plate electrode 80 are provided in the peripheral field plate trench 18Q in the second isolation region 38B, similar to the second proximity region 36B. The first field plate electrode 60 and the second field plate electrode 80 may be integrated, similar to the second proximity region 36B. Also, as shown in FIG. 8 , the configuration of the mesa region 20 in the second isolation region 38B is the same as the configuration of the mesa region 20 in the second proximity region 36B. As shown in FIG. 2 , the multiple mesa regions 20 in the second isolation region 38B extend in the Y-axis direction.

[0083] The source contact 62 provided in each of the multiple mesa regions 20 in the second isolation region 38B extends in the Y-axis direction in plan view. As shown in Fig. 8, the source contact 62 in the second isolation region 38B, like the second proximity region 36B, penetrates the source region 48 and reaches the body region 46. Like the second proximity region 36B, the source contact 62 is in contact with a contact region 64 provided in the body region 46.

[0084] [Configuration of the third isolated area] The configuration of third isolation region 38C will be described with reference to Figures 2 and 7. Figure 7 is a schematic cross-sectional view taken along line F7-F7 of the semiconductor device shown in Figure 2. Figure 7 shows three cell trenches 14 and one peripheral field plate trench 18Q provided in third isolation region 38C.

[0085] As shown in FIG. 2, the multiple cell trenches 14 provided in the third isolation region 38C extend in the X-axis direction in plan view and are spaced apart in the Y-axis direction. The multiple cell trenches 14 and the peripheral field plate trench 18Q provided in the third isolation region 38C are arranged at a first interval G1 in the Y-axis direction. The field plate trench 18 is provided to surround the multiple cell trenches 14 in plan view. In the example shown in FIG. 2, the field plate trench 18 has a quadrangular ring shape in plan view. The end field plate trench 18P provided in the third isolation region 38C communicates with each of the multiple cell trenches 14. The multiple cell trenches 14 intersect with the first peripheral gate fingers 26A in plan view. Gate electrodes 58 provided in the multiple cell trenches 14 are connected to the gate wiring 24 via gate contacts 68 arranged at positions intersecting with the first peripheral gate fingers 26A. The cell trenches 14 are arranged across the inner region 32 and the outer periphery region 34 .

[0086] The widths of the cell trenches 14 and peripheral field plate trenches 18Q provided in the third isolation region 38C are the same as the widths of the cell trenches 14 and peripheral field plate trenches 18Q provided in the second proximity region 36B. The planar configurations of the cell trenches 14 and field plate trenches 18 provided in the third isolation region 38C are the same as those in the second proximity region 36B. The number of cell trenches 14 provided in the third isolation region 38C is the same as the number of cell trenches 14 provided in the second proximity region 36B. The length of the cell trenches 14 provided in the third isolation region 38C is the same as the length of the cell trenches 14 provided in the second proximity region 36B.

[0087] As shown in FIG. 7 , an insulating layer 16, a gate electrode 58, and a first field plate electrode 60 are provided in the cell trench 14 in the third isolation region 38C, similar to the second proximity region 36B. An insulating layer 16 and a second field plate electrode 80 are provided in the peripheral field plate trench 18Q in the third isolation region 38C, similar to the second proximity region 36B. The first field plate electrode 60 and the second field plate electrode 80 may be integrated, similar to the second proximity region 36B. As shown in FIG. 7 , the configuration of the mesa region 20 in the third isolation region 38C is the same as the configuration of the mesa region 20 in the second proximity region 36B. As shown in FIG. 2 , the multiple mesa regions 20 in the third isolation region 38C extend in the X-axis direction.

[0088] The source contact 62 provided in each of the multiple mesa regions 20 in the third isolation region 38C extends in the X-axis direction in plan view. As shown in Fig. 7, the source contact 62 in the third isolation region 38C, like the second proximity region 36B, penetrates the source region 48 and reaches the body region 46. Like the second proximity region 36B, the source contact 62 is in contact with a contact region 64 provided in the body region 46.

[0089] As described above, each of the proximity regions 36 and the separation regions 38 may include one or more cell trenches 14. Some of the multiple cell trenches 14 provided in each of the proximity regions 36 and the separation regions 38 may be aligned parallel to one another at equal intervals. The number of cell trenches 14 included in each of the proximity regions 36 and the separation regions 38 can be determined appropriately depending on the layout.

[0090] [Source Contact Configuration] The configuration of the source contacts 62 in the isolation region 38 and the proximity region 36 will be described with reference to FIGS.

[0091] As shown in FIG. 2 , the multiple source contacts 62 include remote contacts 63 and proximal contacts 65. The remote contacts 63 are source contacts 62 that are provided in the remote region 38 among the multiple source contacts 62. More specifically, the remote contacts 63 are provided in each of the first to third remote regions 38A to 38C. The proximal contacts 65 are source contacts 62 that are provided in the proximal region 36 among the multiple source contacts 62. More specifically, the proximal contacts 65 are provided in each of the first proximal region 36A and the second proximal region 36B. Here, the first to third remote regions 38A to 38C are provided at positions farther away from the gate pad 25 than the first proximal region 36A and the second proximal region 36B. Therefore, the remote contacts 63 can be said to be located at a position farther away from the gate pad 25. On the other hand, the proximal contacts 65 can be said to be located closer to the gate pad 25 than the remote contacts 63.

[0092] A plurality of remote contacts 63 are provided in the remote region 38. More specifically, a plurality of remote contacts 63 are provided in each of the first to third remote regions 38A to 38C. The plurality of remote contacts 63 can be said to include a plurality of first remote contacts 63A provided in the first remote region 38A, a plurality of second remote contacts 63B provided in the second remote region 38B, and a plurality of third remote contacts 63C provided in the third remote region 38C.

[0093] The first to third remote contacts 63A to 63C (source contacts 62) are provided in the respective mesa regions 20 of the first to third isolated regions 38A to 38C, and therefore the numbers of the first to third remote contacts 63A to 63C differ from one another depending on the numbers of mesa regions 20 in the first to third isolated regions 38A to 38C. The number of second remote contacts 63B in the second isolated region 38B may be greater than the number of first remote contacts 63A in the first isolated region 38A. The number of third remote contacts 63C in the third isolated region 38C may be greater than the number of second remote contacts 63B in the second isolated region 38B.

[0094] The multiple first remote contacts 63A are arranged at the same positions in the X-axis direction and spaced apart from each other in the Y-axis direction. Each first remote contact 63A extends in the X-axis direction in plan view. That is, each first remote contact 63A is strip-shaped in plan view, having a width in the Y-axis direction and extending in the X-axis direction.

[0095] The second remote contacts 63B are arranged at the same positions in the Y-axis direction and spaced apart from one another in the X-axis direction. Each second remote contact 63B extends in the Y-axis direction in plan view. That is, each second remote contact 63B is strip-shaped in plan view, having a width in the X-axis direction and extending in the Y-axis direction.

[0096] The multiple third remote contacts 63C are arranged at the same positions in the X-axis direction and spaced apart from each other in the Y-axis direction. Each third remote contact 63C extends in the X-axis direction in plan view. That is, each third remote contact 63C is strip-shaped in plan view, having a width in the Y-axis direction and extending in the X-axis direction.

[0097] The length of the second remote contact 63B in the Y-axis direction may be longer than the length of the first remote contact 63A in the X-axis direction. The length of the second remote contact 63B in the Y-axis direction may be longer than the length of the third remote contact 63C in the X-axis direction.

[0098] Each of the first to third remote contacts 63A to 63C has a first width W1. That is, in a plan view, the dimension of the first remote contact 63A in the Y-axis direction is the first width W1, in a plan view, the dimension of the second remote contact 63B in the X-axis direction is the first width W1, and in a plan view, the dimension of the third remote contact 63C in the Y-axis direction is the first width W1. Thus, in the first embodiment, the first to third remote contacts 63A to 63C have the same width.

[0099] A plurality of proximity contacts 65 are provided in the proximity region 36. More specifically, a plurality of proximity contacts 65 are provided in each of the first proximity region 36A and the second proximity region 36B. The plurality of proximity contacts 65 can be said to include a plurality of first proximity contacts 65A provided in the first proximity region 36A and a plurality of second proximity contacts 65B provided in the second proximity region 36B.

[0100] The first proximity contacts 65A and second proximity contacts 65B (source contacts 62) are provided in each mesa region 20 in the first proximity region 36A and the second proximity region 36B, and therefore the numbers of the first proximity contacts 65A and second proximity contacts 65B differ depending on the numbers of mesa regions 20 in the first proximity region 36A and the second proximity region 36B. The number of second proximity contacts 65B in the second proximity region 36B may be greater than the number of first proximity contacts 65A in the first proximity region 36A.

[0101] The first proximity contacts 65A are arranged at the same positions in the Y-axis direction and spaced apart from one another in the X-axis direction. Each first proximity contact 65A extends in the Y-axis direction in plan view. Each first proximity contact 65A is strip-shaped in plan view, having a width in the X-axis direction and extending in the Y-axis direction.

[0102] The second proximity contacts 65B are arranged at the same positions in the X-axis direction and spaced apart from each other in the Y-axis direction. Each second proximity contact 65B extends in the X-axis direction in plan view. Each second proximity contact 65B is strip-shaped in plan view, having a width in the Y-axis direction and extending in the X-axis direction.

[0103] The length in the X-axis direction of the second proximity contact 65B may be longer than the length in the Y-axis direction of the first proximity contact 65A. The length in the Y-axis direction of the first proximity contact 65A may be shorter than the length in the X-axis direction of the first remote contact 63A. The length in the X-axis direction of the second proximity contact 65B may be shorter than the length in the Y-axis direction of the second remote contact 63B. The length in the X-axis direction of the second proximity contact 65B may be equal to the length in the X-axis direction of the third remote contact 63C.

[0104] As shown in FIGS. 3 and 5 to 8, each of the first proximity contact 65A and the second proximity contact 65B has a second width W2 that is larger than the first width W1. That is, in plan view, the dimension of the first proximity contact 65A in the X-axis direction is the second width W2, and the dimension of the second proximity contact 65B in the Y-axis direction is the second width W2. Thus, in the first embodiment, the first proximity contact 65A and the second proximity contact 65B have the same width. In one example, the first width W1 may be greater than 0.1 μm and equal to or less than 0.16 μm. The second width W2 may be greater than 0.16 μm and equal to or less than 0.32 μm.

[0105] The far contact 63 and the near contact 65 have similar configurations but different widths. The remote contact 63 includes sidewalls 63X and a bottom 63Y that penetrate the insulating layer 16 and reach the semiconductor layer 12. The sidewalls 63X are arranged opposite each other and spaced apart in the width direction of the remote contact 63. The bottom 63Y connects the opposing sidewalls 63X to each other. The bottom 63Y is provided in the semiconductor layer 12.

[0106] The proximity contact 65 includes sidewalls 65X and a bottom 65Y that penetrate the insulating layer 16 and reach the semiconductor layer 12. The sidewalls 65X are arranged opposite each other and spaced apart in the width direction of the proximity contact 65. The bottom 65Y connects the opposing sidewalls 65X to each other. The bottom 65Y is provided in the semiconductor layer 12.

[0107] The mesa region 20 includes a remote mesa region 20A and a proximal mesa region 20B. The remote mesa region 20A is connected to a bottom 63Y of the remote contact 63. The proximal mesa region 20B is connected to a bottom 65Y of the proximal contact 65. In other words, the proximal mesa region 20B is a mesa region provided in the proximal region 36, and the remote mesa region 20A is a mesa region provided in the remote region 38.

[0108] As shown in FIGS. 6 to 8, the length direction of the remote mesa region 20A is the direction in which two cell trenches 14 adjacent to the remote mesa region 20A are aligned. The remote mesa region 20A has a mesa length L1 in the length direction. The remote contact 63 has a first width W1 as a contact width in the length direction of the remote mesa region 20A. The distance between the remote contact 63 and the ends 14C of the two cell trenches 14 that sandwich the remote contact 63 is defined as D1. The ends 14C of the cell trenches 14 are in contact with the remote mesa region 20A at a depth corresponding to the bottom 63Y of the remote contact 63. In one example, the length L1 of the remote mesa region 20A in the Y-axis direction is 0.7 μm or more and 0.8 μm or less.

[0109] As shown in FIGS. 3 and 5, the length direction of the adjacent mesa region 20B is the direction in which the two cell trenches 14 adjacent to the adjacent mesa region 20B are aligned. The adjacent mesa region 20B has a mesa length L2 in the length direction. The adjacent contact 65 has a second width W2 as a contact width in the length direction of the adjacent mesa region 20B. The distance between the adjacent contact 65 and the ends 14C of the two cell trenches 14 that sandwich the adjacent contact 65 is defined as D2. The ends 14C of the cell trenches 14 are in contact with the adjacent mesa region 20B at a depth corresponding to the bottom 65Y of the adjacent contact 65. In one example, the length L2 of the adjacent mesa region 20B is 0.7 μm or more and 0.8 μm or less.

[0110] As shown in FIGS. 3 and 5 to 8 , the distance D1 between the remote contact 63 and the cell trench 14 may be greater than the distance D2 between the proximal contact 65 and the cell trench 14. The distance D2 between the proximal contact 65 and the cell trench 14 may be set according to the electrical characteristics of the semiconductor device 10. The distance D2 corresponds to the second width W2 of the proximal contact 65. Increasing the second width W2 of the proximal contact 65 increases the size of the contact region 64 accordingly. The contact region 64 and the body region 46 contain p-type impurities. The impurity concentration of the contact region 64 is higher than the impurity concentration of the body region 46. By increasing the second width W2 of the proximal contact 65 relative to the cell trench 14, the contact region 64 approaches the cell trench 14, increasing the impurity concentration of the portion of the body region 46 between the proximal contact 65 and the cell trench 14. This increases the on-resistance of the transistor cell in the proximal region 36 including the proximal contact 65. Therefore, in the proximity region 36, the upper limit of the second width W2 of the proximity contact 65, i.e., the distance D2 between the proximity contact 65 and the cell trench 14, may be set to suppress an increase in the on-resistance of the transistor cell. The distance D2 between the proximity contact 65 and the cell trench 14 may be equal to or greater than 0.22 μm and less than 0.3 μm. In one example, the distance D2 may be 0.24 μm.

[0111] The first width W1 of the remote contact 63 is smaller than the second width W2 of the proximal contact 65. Therefore, in the remote region 38 including the remote contact 63, the distance D1 between the remote contact 63 and the cell trench 14 is larger than the distance D2 in the proximal region 36. Therefore, the on-resistance of the transistor cell in the remote region 38 including the remote contact 63 is lower than the on-resistance of the transistor cell in the proximal region 36.

[0112] [Operation of the first embodiment] The operation of the semiconductor device 10 of the first embodiment will be described with reference to Figures 1 to 3. The semiconductor device 10 is used as an inductive load, for example, to control a motor. The inductive load is called an L load.

[0113] When the semiconductor device 10 is turned on by a gate voltage, a drain current flows and the motor rotates. Next, when the semiconductor device 10 is turned off by applying a gate voltage, the drain current is cut off. At this time, the current becomes zero and the motor stops. However, because the motor is an inductive load, a back electromotive force is generated in a direction that tries to maintain the magnetic field of the coil that constitutes the motor, i.e., in a direction that does not reduce the current.

[0114] If this back electromotive force occurs between the drain and source and exceeds BVDSS (the drain-source breakdown voltage when the gate and source are short-circuited), an avalanche breakdown may occur. When an avalanche breakdown occurs, electrons are multiplied by impact ionization, causing a drain leakage current to flow, while the generated hole current may flow into the body region 46. This may reduce the inductive load resistance of the semiconductor device 10.

[0115] The semiconductor device 10 includes a plurality of gate electrodes 58. Each gate electrode 58, together with the surrounding components of the cell trench 14 in which the gate electrode 58 is disposed, constitutes a transistor cell. In other words, the semiconductor device 10 includes a plurality of transistor cells. A gate control signal applied to the gate pad 25 from an external circuit is supplied to each gate electrode 58 from the gate pad 25 via the peripheral gate fingers 26. Therefore, among the plurality of transistor cells, the transistor cells closer to the gate electrode 58 turn off faster. For this reason, current due to back electromotive force is concentrated in the source contact 62 close to the gate electrode 58. This current concentration can be a factor that reduces the inductive load tolerance of the semiconductor device 10.

[0116] The semiconductor device 10 of the first embodiment includes a remote contact 63 that is located at a position away from the gate pad 25 and has a first width W1, and a proximity contact 65 that is located closer to the gate pad 25 than the remote contact 63 and has a second width W2 that is larger than the first width W1.

[0117] The avalanche current in the semiconductor device 10 flows equivalently from the drain wiring 50 through the drain-body diode and the body-source resistor to the source wiring 22. Therefore, by increasing the second width W2 of the proximity contact 65 electrically connected to the source wiring 22, current concentration can be suppressed. As a result, the semiconductor device 10 can efficiently pass the current generated by an inductive load during the turn-off operation of the semiconductor device 10 through the proximity contact 65 having the second width W2. As a result, the inductive load tolerance of the semiconductor device 10 can be improved.

[0118] As described above, the avalanche current in the semiconductor device 10 flows equivalently from the drain wiring 50 through the drain-body diode and the body-source resistance to the source wiring 22. Increasing the second width W2 of the proximity contact 65 electrically connected to the source wiring 22 reduces the body-source resistance. This can be said to suppress fluctuations in the body voltage. In addition, the proximity contact 65 is electrically connected to the contact region 64 embedded in the body region 46. Therefore, the proximity contact 65 can stabilize the voltage of the body region 46.

[0119] [Effects of the first embodiment] (1-1) A semiconductor device 10 includes a semiconductor layer 12 having a body region 46, a plurality of cell trenches 14 provided in the semiconductor layer 12, an insulating layer 16 provided in the plurality of cell trenches 14 and on the semiconductor layer 12, a plurality of gate electrodes 58 embedded in the plurality of cell trenches 14 via the insulating layer 16, a gate pad 25 provided on the insulating layer 16 and electrically connected to the plurality of gate electrodes 58, a source wiring 22 provided on the insulating layer 16, and a plurality of source contacts 62 arranged between two adjacent cell trenches 14 in a planar view and connecting the source wiring 22 and the body region 46. The plurality of source contacts 62 include a remote contact 63 arranged at a position spaced apart from the gate pad 25 and having a first width W1, and a proximity contact 65 arranged at a position closer to the gate pad 25 than the remote contact 63 and having a second width W2 larger than the first width W1.

[0120] According to this configuration, by increasing the second width W2 of the proximity contact 65 close to the gate pad 25, the current generated by the inductive load when the semiconductor device 10 is turned off can be efficiently passed through the proximity contact 65 with the second width W2. As a result, the inductive load tolerance of the semiconductor device 10 can be improved.

[0121] (1-2) The semiconductor layer 12 includes an isolated region 38 located away from the gate pad 25, and a proximity region 36 located closer to the gate pad 25 than the isolated region 38. A plurality of isolated contacts 63 are provided in the isolated region 38. A plurality of proximity contacts 65 are provided in the proximity region 36. With this configuration, the isolated contacts 63 have a first width W1 that is smaller than the second width W2 of the proximity contacts 65, thereby suppressing an increase in the on-resistance of the semiconductor device 10 and improving the inductive load resistance of the semiconductor device 10.

[0122] (1-3) The proximity region 36 is adjacent to the gate pad 25. This configuration can improve the inductive load resistance of the semiconductor device 10. (1-4) The semiconductor layer 12 has a rectangular shape in a plan view and includes a first side surface 101 and a second side surface 102 that are both side surfaces in the Y-axis direction, and a third side surface 103 and a fourth side surface 104 that are both side surfaces in the X-axis direction. The gate pad 25 is disposed at a corner portion of the semiconductor layer 12 defined by the second side surface 102 and the fourth side surface 104. The proximity region 36 includes a first proximity region 36A that is disposed adjacent to the gate pad 25 in the X-axis direction, and a second proximity region 36B that is disposed adjacent to the gate pad 25 in the Y-axis direction. The multiple proximity contacts 65 include a multiple first proximity contacts 65A provided in the first proximity region 36A and a multiple second proximity contacts 65B provided in the second proximity region 36B.

[0123] With this configuration, for the gate pad 25 provided in the corner portion, it is possible to suppress a decrease in the inductive load resistance in the first proximity region 36A and the second proximity region 36B adjacent in the X-axis direction and the Y-axis direction.

[0124] (1-5) The semiconductor layer 12 includes a mesa region 20, which is a region between two adjacent cell trenches 14 among the plurality of cell trenches 14 in a plan view. A plurality of source contacts 62 penetrate the insulating layer 16 and reach the body region 46 of the mesa region 20. With this configuration, the voltage of the body region 46 of the mesa region 20 can be controlled via the source contacts 62.

[0125] (1-6) The semiconductor layer 12 includes a source region 48 provided in a surface portion of the body region 46. A plurality of source contacts 62 electrically connect the source region 48 and the body region 46. With this configuration, the voltage of the body region 46 in the mesa region 20 can be used as the source potential.

[0126] (1-7) The semiconductor layer 12 includes an isolated region 38 located away from the gate pad 25, a proximal region 36 located closer to the gate pad 25 than the isolated region 38, and a mesa region 20 that is a region between two adjacent cell trenches 14 in a planar view. Both the proximal contact 65 and the distal contact 63 include sidewalls 62X (65X, 63X) that penetrate the insulating layer 16 and reach the semiconductor layer 12, and bottoms 62Y (65Y, 63Y). The mesa region 20 includes an isolated mesa region 20A to which the bottom 63Y of the distal contact 63 is connected, and a proximal mesa region 20B to which the bottom 65Y of the proximal contact 65 is connected. In both the remote mesa region 20A and the proximal mesa region 20B, the distance D2 between the end 14C of the cell trench 14 on the mesa region 20 side and the sidewall 65X of the contact 65 in the proximal region 36 and the distance D1 between the end 14C of the cell trench 14 on the mesa region 20 side and the sidewall 63X of the contact 63 in the remote region 38 are 0.22 μm or more and less than 0.3 μm. With this configuration, the proximal contact 65 having the second width W2 can improve the inductive load tolerance while suppressing an increase in on-resistance.

[0127] (1-8) In the proximal mesa region 20B, the distance D2 between the end 14C of the cell trench 14 on the mesa region 20 side and the sidewall 62X of the source contact 62 in the proximal region 36 is smaller than the distance D1 between the end 14C of the cell trench 14 on the mesa region 20 side in the remote mesa region 20A and the sidewall 62X of the source contact 62 in the remote region 38. This configuration can suppress an increase in the on-resistance of the semiconductor device 10 in the proximal region 36 close to the gate pad 25.

[0128] (1-9) The first width W1 is greater than 0.1 μm and equal to or less than 0.16 μm. The second width W2 is greater than 0.16 μm and equal to or less than 0.32 μm. This configuration can improve the inductive load resistance of the semiconductor device 10 while suppressing an increase in on-resistance.

[0129] Second Embodiment [Planar structure of semiconductor device] A semiconductor device 10 according to a second embodiment will be described with reference to FIGS. 9 to 14. FIG. 9 is an illustrative schematic plan view of the semiconductor device according to the second embodiment. FIG. 10 is a schematic plan view showing the arrangement of cell trenches and field plate trenches provided in a semiconductor layer of the semiconductor device shown in FIG. 9. FIG. 11 is a schematic cross-sectional view of the semiconductor device shown in FIG. 10 taken along line F11-F11. FIG. 12 is a schematic cross-sectional view of the semiconductor device shown in FIG. 10 taken along line F12-F12. FIG. 13 is a schematic cross-sectional view of the semiconductor device shown in FIG. 10 taken along line F13-F13. FIG. 14 is a schematic cross-sectional view of the semiconductor device shown in FIG. 10 taken along line F14-F14.

[0130] The semiconductor device 10 of the second embodiment differs from the semiconductor device 10 of the first embodiment mainly in the position of the gate pad 25, the configuration of the gate wiring 24, and the position of the proximity region 36. In the following, components common to the first embodiment are denoted by the same reference numerals, and their description will be omitted.

[0131] 9, the gate pad 25 of the second embodiment is disposed in a position adjacent to the second side surface 102 in the Y-axis direction in a plan view. The gate pad 25 is disposed in the center of the semiconductor layer 12 in the X-axis direction in a plan view.

[0132] The multiple outer periphery gate fingers 26 constituting the gate wiring 24 may include five outer periphery gate fingers 26A to 26E. More specifically, the multiple outer periphery gate fingers 26 may include a first outer periphery gate finger 26A and a second outer periphery gate finger 26B extending along the Y-axis direction, and a third outer periphery gate finger 26C, a fourth outer periphery gate finger 26D, and a fifth outer periphery gate finger 26E extending along the X-axis direction.

[0133] The first outer peripheral gate finger 26A is arranged closer to the third side surface 103 than the gate pad 25 in a plan view. The second outer peripheral gate finger 26B is arranged closer to the fourth side surface 104 than the gate pad 25 in a plan view. The third outer peripheral gate finger 26C is arranged closer to the first side surface 101 than the gate pad 25 in a plan view. The gate pad 25 is connected to the fourth outer peripheral gate finger 26D and the fifth outer peripheral gate finger 26E. The fourth outer peripheral gate finger 26D is arranged closer to the third side surface 103 than the gate pad 25 in a plan view. The fifth outer peripheral gate finger 26E is arranged closer to the fourth side surface 104 than the gate pad 25 in a plan view.

[0134] The third perimeter gate finger 26C may be connected to the second perimeter gate finger 26B at a corner formed by the first side surface 101 and the fourth side surface 104. The first perimeter gate finger 26A may be connected to the fourth perimeter gate finger 26D at a corner formed by the second side surface 102 and the third side surface 103. The second perimeter gate finger 26B may be connected to the fifth perimeter gate finger 26E at a corner formed by the second side surface 102 and the fourth side surface 104.

[0135] The tip of the first outer periphery gate finger 26A and the tip of the third outer periphery gate finger 26C are located at the same position in the X-axis direction. The first outer periphery gate finger 26A and the third outer periphery gate finger 26C may be separated from each other by a gap 30 arranged along the outer edge of the inner region 32.

[0136] 9, the multiple perimeter segments 28 may include five perimeter segments 28A to 28E. More specifically, the multiple perimeter segments 28 may include a first perimeter segment 28A and a second perimeter segment 28B extending along the Y-axis direction, and a third perimeter segment 28C, a fourth perimeter segment 28D, and a fifth perimeter segment 28E extending along the X-axis direction.

[0137] The first outer perimeter segment 28A may be disposed between the first outer perimeter gate finger 26A and the third side surface 103 of the semiconductor layer 12 in the X-axis direction in a plan view. The first outer perimeter segment 28A is disposed spaced apart from both the first outer perimeter gate finger 26A and the third side surface 103 in a plan view. The second outer perimeter segment 28B may be disposed between the second outer perimeter gate finger 26B and the fourth side surface 104 of the semiconductor layer 12 in the X-axis direction. The second outer perimeter segment 28B is disposed spaced apart from both the second outer perimeter gate finger 26B and the fourth side surface 104. The third outer perimeter segment 28C may be disposed between the third outer perimeter gate finger 26C and the first side surface 101 of the semiconductor layer 12 in the Y-axis direction. The third outer perimeter segment 28C is disposed spaced apart from both the third outer perimeter gate finger 26C and the first side surface 101. The fourth outer perimeter segment 28D may be disposed between the fourth outer perimeter gate finger 26D and the second side surface 102 of the semiconductor layer 12 in the Y-axis direction. The fourth outer perimeter segment 28D is disposed spaced apart from both the fourth outer perimeter gate finger 26D and the second side surface 102. The fifth outer perimeter segment 28E may be disposed between the fifth outer perimeter gate finger 26E and the second side surface 102 of the semiconductor layer 12 in the Y-axis direction. The fifth outer perimeter segment 28E may be disposed spaced apart from both the fifth outer perimeter gate finger 26E and the second side surface 102.

[0138] The third perimeter segment 28C may be connected to the second perimeter segment 28B at a corner defined by the first side surface 101 and the fourth side surface 104. The first perimeter segment 28A may be connected to the fourth perimeter segment 28D at a corner defined by the second side surface 102 and the third side surface 103. The first perimeter segment 28A may be connected to the third perimeter segment 28C at a corner defined by the first side surface 101 and the third side surface 103. The fifth perimeter segment 28E may be connected to the second perimeter segment 28B at a corner defined by the second side surface 102 and the fourth side surface 104.

[0139] The inner segment 23 may be disposed in the inner region 32, spaced apart from the first outer periphery gate finger 26A, the second outer periphery gate finger 26B, the third outer periphery gate finger 26C, the fourth outer periphery gate finger 26D, the fifth outer periphery gate finger 26E, and the gate pad 25. The inner segment 23 and the first outer periphery segment 28A may be connected to each other across a gap 30 while being spaced apart from the first outer periphery gate finger 26A and the third outer periphery gate finger 26C. The inner segment 23 and the outer periphery segment 28 may be provided integrally.

[0140] 10, in the second embodiment, the semiconductor layer 12 includes an isolated region 38 located away from the gate pad 25, and a proximity region 36 located closer to the gate pad 25 than the isolated region 38. Here, being located closer to the gate pad 25 than the isolated region 38 includes a case where the isolated region 38 and the gate pad 25 are close to each other, and a case where the isolated region 38 and the gate pad 25 are located close to each other and are positioned closer to the gate wiring 24. The second embodiment is a case where the isolated region 38 and the gate pad 25 are located close to each other and are positioned closer to the gate wiring 24. The isolated region 38 in the second embodiment includes a fourth isolated region 38D, a fifth isolated region 38E, and a sixth isolated region 38F, instead of the first to third isolated regions 38A to 38C (see FIG. 2) of the first embodiment. The proximity region 36 of the second embodiment includes a third proximity region 36C and a fourth proximity region 36D instead of the first proximity region 36A and the second proximity region 36B of the first embodiment.

[0141] The third proximity region 36C is disposed closer to the third side surface 103 than the gate pad 25. The third proximity region 36C is adjacent to the gate pad 25. In the example shown in FIG. 10, the third proximity region 36C has a rectangular shape with its long side oriented in the X-axis direction and its short side oriented in the Y-axis direction in plan view.

[0142] The dimension in the X-axis direction of the third proximity region 36C may be larger than the dimension in the X-axis direction of the gate pad 25. The dimension in the Y-axis direction of the third proximity region 36C may be smaller than the dimension in the Y-axis direction of the gate pad 25. When viewed in the X-axis direction, the third proximity region 36C overlaps with the gate pad 25 and is closer to the first side surface 101.

[0143] The fourth proximity region 36D is disposed closer to the fourth side surface 104 than the gate pad 25. The fourth proximity region 36D is adjacent to the gate pad 25. In the example shown in FIG. 10, the fourth proximity region 36D has a generally square shape in a plan view.

[0144] The dimension of the fourth proximity region 36D in the X-axis direction may be larger than the dimension of the gate pad 25 in the X-axis direction. The dimension of the fourth proximity region 36D in the Y-axis direction may be approximately equal to the dimension of the gate pad 25 in the Y-axis direction. When viewed in the X-axis direction, the fourth proximity region 36D approximately overlaps with the gate pad 25. The distance between the fourth proximity region 36D and the gate pad 25 in the X-axis direction may be smaller than the distance between the fourth proximity region 36D and the fourth side surface 104 in the X-axis direction.

[0145] 10 , in a plan view, the dimension in the X-axis direction of the fourth proximity region 36D may be smaller than the dimension in the X-axis direction of the third proximity region 36C. The dimension in the Y-axis direction of the fourth proximity region 36D may be larger than the dimension in the Y-axis direction of the third proximity region 36C. In one example, in a plan view, the area of ​​the third proximity region 36C may be approximately equal to the area of ​​the fourth proximity region 36D.

[0146] The fourth to sixth isolated regions 38D to 38F are provided at positions spaced apart from the gate pad 25. The fourth to sixth isolated regions 38D to 38F are arranged closer to the first side surface 101 than the gate pad 25.

[0147] 10 , the fifth isolated region 38E is disposed closer to the first side surface 101 than the fourth proximity region 36D in the semiconductor layer 12. The fifth isolated region 38E is disposed adjacent to the fourth proximity region 36D in the Y-axis direction. More specifically, the fifth isolated region 38E includes a portion overlapping with the fourth proximity region 36D when viewed from the Y-axis direction. Furthermore, the fifth isolated region 38E may include regions that extend beyond the fourth proximity region 36D toward the third side surface 103 and the fourth side surface 104 when viewed from the Y-axis direction.

[0148] The fifth separate region 38E has a rectangular shape with its short side in the X-axis direction and its long side in the Y-axis direction in plan view. The area of ​​the fifth separate region 38E may be larger than the area of ​​the fourth nearby region 36D. The dimension of the fifth separate region 38E in the X-axis direction may be larger than the dimension of the fourth nearby region 36D in the X-axis direction. The dimension of the fifth separate region 38E in the Y-axis direction may be larger than the dimension of the fourth nearby region 36D in the Y-axis direction. For example, the area of ​​the fifth separate region 38E may be two to three times the area of ​​the fourth nearby region 36D in plan view.

[0149] The fourth isolated region 38D is disposed closer to the first side surface 101 than the third nearby region 36C in the semiconductor layer 12. The fourth isolated region 38D is disposed adjacent to the third nearby region 36C in the Y-axis direction. More specifically, the fourth isolated region 38D includes a portion overlapping with the third nearby region 36C when viewed from the Y-axis direction. Furthermore, the fourth isolated region 38D may include a region that protrudes toward the fourth side surface 104 beyond the third nearby region 36C when viewed from the Y-axis direction. The fourth isolated region 38D may be disposed adjacent to the fifth isolated region 38E in the X-axis direction. The fourth isolated region 38D is disposed closer to the third side surface 103 than the fifth isolated region 38E in the semiconductor layer 12. The fourth isolated region 38D may be located in the same position as the fifth isolated region 38E in the Y-axis direction. The fourth isolated region 38D may be disposed at a position adjacent to the sixth isolated region 38F in the Y-axis direction. The fourth isolated region 38D is located closer to the second side surface 102 than the sixth isolated region 38F in the semiconductor layer 12. The fourth isolated region 38D may be located between the sixth isolated region 38F and the third and fourth nearby regions 36C and 36D in the Y-axis direction.

[0150] The fourth isolated region 38D has a rectangular shape with its short side in the X-axis direction and its long side in the Y-axis direction in plan view. The area of ​​the fourth isolated region 38D may be larger than the area of ​​the third adjacent region 36C. The dimension of the fourth isolated region 38D in the X-axis direction may be larger than the dimension of the third adjacent region 36C in the X-axis direction. The dimension of the fourth isolated region 38D in the Y-axis direction may be larger than the dimension of the third adjacent region 36C in the Y-axis direction. In one example, the area of ​​the fourth isolated region 38D may be three to five times the area of ​​the third adjacent region 36C. The dimension of the fourth isolated region 38D in the X-axis direction is approximately equal to the dimension of the fifth isolated region 38E in the X-axis direction. The dimension of the fourth isolated region 38D in the Y-axis direction is approximately equal to the dimension of the fifth isolated region 38E in the Y-axis direction. In one example, the area of ​​the fourth separated region 38D may be equal to the area of ​​the fifth separated region 38E.

[0151] The sixth isolated region 38F may be located on the opposite side of the gate pad 25 from the fourth isolated region 38D and the fifth isolated region 38E. The sixth isolated region 38F is located closer to the first side surface 101 in the semiconductor layer 12 than the fourth isolated region 38D and the fifth isolated region 38E. The sixth isolated region 38F is located adjacent to the fourth isolated region 38D and the fifth isolated region 38E in the Y-axis direction. When viewed from the Y-axis direction, the sixth isolated region 38F can be said to include a portion overlapping with the fourth isolated region 38D and the fifth isolated region 38E. When viewed from the Y-axis direction, the sixth isolated region 38F may include a region that extends toward the fourth side surface 104 relative to the fourth isolated region 38D and a region that extends toward the third side surface 103 relative to the fifth isolated region 38E.

[0152] The sixth isolated region 38F has a rectangular shape with its longer side in the X-axis direction and its shorter side in the Y-axis direction in a plan view. The area of ​​the sixth isolated region 38F may be larger than the areas of the fourth isolated region 38D and the fifth isolated region 38E. The dimension of the sixth isolated region 38F in the X-axis direction may be larger than the dimension of the fourth isolated region 38D in the X-axis direction and the dimension of the fifth isolated region 38E in the X-axis direction. The dimension of the sixth isolated region 38F in the Y-axis direction may be approximately equal to the dimension of the fourth isolated region 38D in the Y-axis direction and the dimension of the fifth isolated region 38E in the Y-axis direction. In one example, the area of ​​the sixth isolated region 38F may be 1.5 to 2 times the area of ​​the fourth isolated region 38D or the fifth isolated region 38E in a plan view.

[0153] [Configuration of the third proximal region] The configuration of the third proximity region 36C will be described with reference to Figures 10 and 12. Figure 12 is a schematic cross-sectional view taken along line F12-F12 of the semiconductor device 10 shown in Figure 10. Figure 12 shows one cell trench 14 and two peripheral field plate trenches 18Q provided in the third proximity region 36C.

[0154] 10, the third proximity region 36C is provided with one cell trench 14 and a field plate trench 18. The planar configuration of the cell trench 14 and the field plate trench 18 provided in the third proximity region 36C may be the same as that of the first isolation region 38A in the first embodiment (see FIG. 2).

[0155] As shown in FIG. 12 , an insulating layer 16, a gate electrode 58, and a first field plate electrode 60 are provided in the cell trench 14 in the third proximity region 36C, similar to the second proximity region 36B in the first embodiment. As shown in FIG. 10 , the cell trench 14 intersects with the first peripheral gate finger 26A in a plan view. The gate electrode 58 provided in the cell trench 14 is connected to the gate wiring 24 via a gate contact 68 located at the intersection with the first peripheral gate finger 26A. Also, as shown in FIG. 12 , an insulating layer 16 and a second field plate electrode 80 are provided in the peripheral field plate trench 18Q in the third proximity region 36C, similar to the second proximity region 36B. The first field plate electrode 60 and the second field plate electrode 80 may be integrated, similar to the second proximity region 36B. The configuration of the mesa region 20 in the third proximity region 36C is the same as the configuration of the mesa region 20 in the second proximity region 36B.

[0156] 10, the source contact 62 provided in each of the multiple mesa regions 20 in the third proximity region 36C extends in the X-axis direction in plan view. As shown in Fig. 12, the source contact 62 in the third proximity region 36C, like the second proximity region 36B, penetrates the source region 48 and reaches the body region 46. Like the second proximity region 36B, the source contact 62 is in contact with the contact region 64 provided in the body region 46.

[0157] [Configuration of the fourth proximal region] The configuration of the fourth proximity region 36D will be described with reference to Figures 10 and 11. Figure 11 is a schematic cross-sectional view taken along line F11-F11 of the semiconductor device 10 shown in Figure 10. Figure 11 shows two cell trenches 14 and two peripheral field plate trenches 18Q provided in the fourth proximity region 36D.

[0158] 10, the fourth proximity region 36D has a plurality of cell trenches 14 and field plate trenches 18. The planar structures of the cell trenches 14 and field plate trenches 18 provided in the fourth proximity region 36D may be the same as those of the first proximity region 36A in the first embodiment (see FIG. 2). However, the number of cell trenches 14 provided in the fourth proximity region 36D is fewer than the number of cell trenches 14 provided in the first proximity region 36A because the length of the fourth proximity region 36D in the X-axis direction is shorter than the length of the first proximity region 36A in the X-axis direction.

[0159] As shown in FIG. 11 , an insulating layer 16, a gate electrode 58, and a first field plate electrode 60 are provided in the cell trenches 14 in the fourth proximity region 36D, similar to the second proximity region 36B. As shown in FIG. 10 , each cell trench 14 intersects with a fifth peripheral gate finger 26E in plan view. The gate electrodes 58 provided in the multiple cell trenches 14 are connected to the gate wiring 24 via gate contacts 68 located at positions intersecting with the fifth peripheral gate fingers 26E. Also, as shown in FIG. 11 , an insulating layer 16 and a second field plate electrode 80 are provided in the peripheral field plate trench 18Q in the fourth proximity region 36D, similar to the first proximity region 36A. The first field plate electrode 60 and the second field plate electrode 80 may be integrated, similar to the first proximity region 36A. The configuration of the mesa region 20 in the fourth proximity region 36D is the same as the configuration of the mesa region 20 in the first proximity region 36A.

[0160] 10, the source contact 62 provided in each of the multiple mesa regions 20 in the fourth proximity region 36D extends in the Y-axis direction in plan view. As shown in Fig. 11, the source contact 62 in the fourth proximity region 36D, like the first proximity region 36A, penetrates the source region 48 and reaches the body region 46. Like the first proximity region 36A, the source contact 62 is in contact with a contact region 64 provided in the body region 46.

[0161] [Configuration of the 4th and 5th isolated regions] The configurations of fourth isolation region 38D and fifth isolation region 38E will be described with reference to Figures 10, 13, and 14. Figure 13 is a schematic cross-sectional view taken along line F13-F13 of the semiconductor device shown in Figure 10. Figure 14 is a schematic cross-sectional view taken along line F14-F14 of the semiconductor device shown in Figure 10. Figures 13 and 14 show three cell trenches 14 and one peripheral field plate trench 18Q provided in fourth isolation region 38D and fifth isolation region 38E, respectively.

[0162] 10, each of the fourth isolation region 38D and the fifth isolation region 38E includes a plurality of cell trenches 14 and field plate trenches 18. As shown in FIGS. 10, 13, and 14, the fourth isolation region 38D and the fifth isolation region 38E have the same configuration. Therefore, the following will describe the configuration of the fourth isolation region 38D, and for the fifth isolation region 38E, the same reference numerals will be used to designate common components, and detailed description thereof will be omitted.

[0163] 13 and 14, an insulating layer 16, a gate electrode 58, and a first field plate electrode 60 are provided in the cell trenches 14 in the fourth isolation region 38D, similar to the second proximity region 36B in the first embodiment. As shown in FIG. 10, each cell trench 14 intersects with the first outer peripheral gate finger 26A in a plan view. The gate electrode 58 provided in each cell trench 14 is connected to the gate wiring 24 via a gate contact 68 arranged at a position where the gate electrode 58 intersects with the first outer peripheral gate finger 26A. Note that each cell trench 14 in the fifth isolation region 38E intersects with the second outer peripheral gate finger 26B in a plan view. The gate electrode 58 provided in each cell trench 14 is connected to the second outer peripheral gate finger 26B via a gate contact 68 arranged at a position where the gate electrode 58 intersects with the second outer peripheral gate finger 26B. 13 and 14, an insulating layer 16 and a second field plate electrode 80 are provided in the peripheral field plate trench 18Q in the fourth isolation region 38D, similar to the second proximity region 36B. The first field plate electrode 60 and the second field plate electrode 80 may be integrated, similar to the second proximity region 36B. The configuration of the mesa region 20 in the fourth isolation region 38D is the same as the configuration of the mesa region 20 in the second proximity region 36B.

[0164] 10, the source contact 62 provided in each of the multiple mesa regions 20 in the fourth isolation region 38D extends in the X-axis direction in plan view. 13 and 14, the source contacts 62 in the fourth isolation region 38D and the fifth isolation region 38E, like the second proximity region 36B, penetrate the source region 48 and reach the body region 46. Like the second proximity region 36B, the source contact 62 is in contact with a contact region 64 provided in the body region 46.

[0165] [Configuration of the 6th isolated area] In the semiconductor device 10 of the second embodiment, the configuration of the sixth isolated region 38F is generally the same as the configuration of the second isolated region 38B (see FIG. 2) of the first embodiment, so a detailed description of the configuration of the sixth isolated region 38F will be omitted.

[0166] [Source Contact Configuration] The configuration of the source contacts 62 in the isolation region 38 and the proximity region 36 will be described with reference to FIGS.

[0167] As shown in FIG. 10 , the source contact 62 includes a proximal contact 65 and a remote contact 63, as in the first embodiment. The remote contact 63 is a source contact 62 among the multiple source contacts 62 that is provided in the remote region 38. In the second embodiment, the remote contact 63 is provided in each of the fourth to sixth remote regions 38D to 38F. The proximal contact 65 is a source contact 62 among the multiple source contacts 62 that is provided in the proximal region 36. In the second embodiment, the proximal contact 65 is provided in each of the third proximal region 36C and the fourth proximal region 36D. Here, the fourth to sixth remote regions 38D to 38F are provided at positions farther away from the gate pad 25 than the third proximal region 36C and the fourth proximal region 36D. Therefore, it can be said that the remote contact 63 is disposed at a position farther away from the gate pad 25. On the other hand, it can be said that the proximal contact 65 is disposed at a position closer to the gate pad 25 than the remote contact 63.

[0168] 10, a plurality of remote contacts 63 are provided in the remote region 38. In the second embodiment, a plurality of remote contacts 63 are provided in each of the fourth to sixth remote regions 38D to 38F. The plurality of remote contacts 63 can be said to include a plurality of fourth remote contacts 63D provided in the fourth remote region 38D, a plurality of fifth remote contacts 63E provided in the fifth remote region 38E, and a plurality of sixth remote contacts 63F provided in the sixth remote region 38F.

[0169] The fourth to sixth remote contacts 63D to 63F (source contacts 62) are provided in the mesa regions 20 of the fourth to sixth remote regions 38D to 38F, and therefore the number of the fourth to sixth remote contacts 63D to 63F differs depending on the number of mesa regions 20 in the fourth to sixth remote regions 38D to 38F. The number of the sixth remote contacts 63F in the sixth remote region 38F may be greater than the number of the fourth remote contacts 63D in the fourth remote region 38D. The number of the sixth remote contacts 63F in the sixth remote region 38F may be greater than the number of the fifth remote contacts 63E in the fifth remote region 38E. The number of the fourth remote contacts 63D in the fourth remote region 38D may be approximately equal to the number of the fifth remote contacts 63E in the fifth remote region 38E.

[0170] The multiple fourth remote contacts 63D are arranged at the same positions in the X-axis direction and spaced apart from each other in the Y-axis direction. Each fourth remote contact 63D extends in the X-axis direction in plan view. That is, each fourth remote contact 63D is strip-shaped and has a width in the Y-axis direction and extends in the X-axis direction in plan view.

[0171] The plurality of fifth remote contacts 63E are arranged at the same positions in the X-axis direction and spaced apart from one another in the Y-axis direction. Each fifth remote contact 63E extends in the X-axis direction in plan view. That is, each fifth remote contact 63E is strip-shaped in plan view, having a width in the Y-axis direction and extending in the X-axis direction.

[0172] The sixth remote contacts 63F are arranged at the same positions in the Y-axis direction and spaced apart from one another in the X-axis direction. Each sixth remote contact 63F extends in the Y-axis direction in plan view. That is, each sixth remote contact 63F is strip-shaped in plan view, having a width in the X-axis direction and extending in the Y-axis direction.

[0173] The length of the sixth remote contact 63F in the Y-axis direction may be longer than the length of the fourth remote contact 63D in the X-axis direction. The length of the sixth remote contact 63F in the Y-axis direction may be longer than the length of the fifth remote contact 63E in the X-axis direction. The length of the fourth remote contact 63D in the X-axis direction may be approximately equal to the length of the fifth remote contact 63E in the X-axis direction.

[0174] Each of the fourth to sixth remote contacts 63D to 63F has a first width W1. That is, in plan view, the dimension in the Y-axis direction of the fourth remote contact 63D is the first width W1, in plan view, the dimension in the Y-axis direction of the fifth remote contact 63E is the first width W1, and in plan view, the dimension in the X-axis direction of the sixth remote contact 63F is the first width W1. Thus, in the second embodiment, the fourth to sixth remote contacts 63D to 63F have the same widths.

[0175] A plurality of proximity contacts 65 are provided in the proximity region 36. In the second embodiment, a plurality of proximity contacts 65 are provided in each of the third proximity region 36C and the fourth proximity region 36D. The plurality of proximity contacts 65 can be said to include a plurality of third proximity contacts 65C provided in the third proximity region 36C and a plurality of fourth proximity contacts 65D provided in the fourth proximity region 36D.

[0176] The third proximity contacts 65C and the fourth proximity contacts 65D (source contacts 62) are provided in each mesa region 20 in the third proximity region 36C and the fourth proximity region 36D, and therefore the numbers of the third proximity contacts 65C and the fourth proximity contacts 65D differ from each other depending on the number of mesa regions 20 in the third proximity region 36C and the fourth proximity region 36D. The number of the fourth proximity contacts 65D in the fourth proximity region 36D may be greater than the number of the third proximity contacts 65C in the third proximity region 36C.

[0177] The multiple fourth proximity contacts 65D are arranged at the same positions in the Y-axis direction and spaced apart from each other in the X-axis direction. Each fourth proximity contact 65D extends in the Y-axis direction in plan view. Each fourth proximity contact 65D is strip-shaped in plan view, having a width in the X-axis direction and extending in the Y-axis direction.

[0178] The third proximity contacts 65C are arranged at the same positions in the X-axis direction and spaced apart from each other in the Y-axis direction. Each third proximity contact 65C extends in the X-axis direction in plan view. Each third proximity contact 65C is strip-shaped and has a width in the Y-axis direction and extends in the X-axis direction in plan view.

[0179] The length in the X-axis direction of the third proximity contact 65C may be longer than the length in the Y-axis direction of the fourth proximity contact 65D. The length in the X-axis direction of the third proximity contact 65C may be shorter than the length in the X-axis direction of the fourth remote contact 63D. The length in the Y-axis direction of the fourth proximity contact 65D may be shorter than the length in the X-axis direction of the fifth remote contact 63E.

[0180] Each of the third proximity contact 65C and the fourth proximity contact 65D has a second width W2 that is larger than the first width W1. That is, in plan view, the dimension of the third proximity contact 65C in the Y-axis direction is the second width W2, and the dimension of the fourth proximity contact 65D in the X-axis direction is the second width W2. Thus, in the second embodiment, the third proximity contact 65C and the fourth proximity contact 65D have the same width. Also, as shown in FIGS. 11 to 14, the distant contacts 63 and the proximity contacts 65 have similar configurations, although their widths are different.

[0181] [Effects of the second embodiment] According to the semiconductor device 10 of the second embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

[0182] (2-1) The semiconductor layer 12 has a rectangular shape in a plan view and includes a first side surface 101 and a second side surface 102, which are both side surfaces in the Y-axis direction, and a third side surface 103 and a fourth side surface 104, which are both side surfaces in the X-axis direction perpendicular to the Y-axis direction. The gate pad 25 is disposed on the second side surface 102 side of the semiconductor layer 12, between the third side surface 103 and the fourth side surface 104. The proximity region 36 includes a third proximity region 36C adjacent to the third side surface 103 side of the gate pad 25, and a fourth proximity region 36D adjacent to the fourth side surface 104 side of the gate pad 25. The multiple proximity contacts 65 include a multiple third proximity contacts 65C provided in the third proximity region 36C and a multiple fourth proximity contacts 65D provided in the fourth proximity region 36D.

[0183] According to this configuration, even if the gate pad 25 is located on the second side surface 102 side of the semiconductor layer 12, between the third side surface 103 and the fourth side surface 104, by increasing the second width W2 of the proximity contact 65 located in the body region 46 of the MISFET close to the gate pad 25, the current generated by an inductive load during the turn-off operation of the semiconductor device 10 can be efficiently conducted by the proximity contact 65 having the second width W2. As a result, the inductive load tolerance of the semiconductor device 10 can be improved.

[0184] Third Embodiment [Plane structure of semiconductor device] A semiconductor device 210 according to the third embodiment will be described with reference to Fig. 15 to Fig. 17. Fig. 15 is an illustrative schematic plan view of the semiconductor device according to the third embodiment. Fig. 16 is a schematic cross-sectional view taken along line F16-F16 of the semiconductor device shown in Fig. 15. Fig. 17 is a schematic cross-sectional view taken along line F17-F17 of the semiconductor device shown in Fig. 15.

[0185] The semiconductor device 210 of the third embodiment differs from the semiconductor device 10 of the first embodiment mainly in that the semiconductor device 210 is a MISFET using a SiC substrate, the position of the gate pad 225, the configuration of the gate wiring 224, and the position of the proximity region 36. In the following, components common to the first embodiment are denoted by the same reference numerals, and their description will be omitted.

[0186] 15, the semiconductor device 210 may be a MISFET. The semiconductor device 210 may include a semiconductor layer 212 and an insulating layer 216 provided on the semiconductor layer 212. The insulating layer 216 may include at least one of a silicon oxide (SiO2) layer and a silicon nitride (SiN) layer.

[0187] The semiconductor device 210 may further include a gate wiring 224 provided on the insulating layer 216, and a source wiring 222 provided on the insulating layer 216 and spaced apart from the gate wiring 224. The source wiring 222 may be spaced apart from the gate wiring 224 by a predetermined distance (determined, for example, in consideration of the breakdown voltage, etc.). The gate wiring 24 and the source wiring 22 may be made of at least one of Ti, Ni, Au, Ag, Cu, Al, a copper alloy, and an aluminum alloy.

[0188] The semiconductor layer 212 includes a first side surface 301 and a second side surface 302 which are both side surfaces in the Y-axis direction in a plan view, and a third side surface 303 and a fourth side surface 304 which are both side surfaces in the X-axis direction. The semiconductor layer 212 has a rectangular shape with its short side direction in the X-axis direction and its long side direction in the Y-axis direction.

[0189] 15, the semiconductor layer 212 includes an isolated region 238 located away from the gate pad 225, and a proximity region 236 located closer to the gate pad 225 than the isolated region 238. Here, being located closer to the gate pad 225 than the isolated region 238 includes a case where the isolated region 238 and the gate pad 225 are close to each other, and a case where the isolated region 238 and the gate pad 225 are located close to each other and are positioned closer to the gate wiring 224. The third embodiment is a case where the isolated region 238 and the gate pad 225 are located close to each other and are positioned closer to the gate wiring 224. The isolated region 238 of the third embodiment includes a seventh isolated region 238G and an eighth isolated region 238H, instead of the first to third isolated regions 38A to 38C (see FIG. 2) of the first embodiment. The proximity region 236 of the third embodiment includes a fifth proximity region 236E and a sixth proximity region 236F instead of the first proximity region 36A and the second proximity region 36B of the first embodiment. Each of the proximity region 236 and the isolation region 238 is a region where a plurality of cell trenches 214 (described later) is provided. The plurality of cell trenches 214 is provided in the semiconductor layer 212. Therefore, it can be said that the semiconductor device 210 includes a plurality of cell trenches 214 provided in the semiconductor layer 212.

[0190] 15, the seventh remote region 238G and the eighth remote region 238H have the same configuration. The fifth proximity region 236E and the sixth proximity region 236F also have the same configuration. Therefore, the following describes the configurations of the fifth proximity region 236E and the seventh remote region 238G, and common components of the fifth proximity region 236E and the eighth remote region 238H are denoted by the same reference numerals and will not be described in detail.

[0191] The fifth proximity region 236E is disposed closer to the third side surface 303 than the gate pad 225. The fifth proximity region 236E is adjacent to the gate pad 225. In the example shown in FIG. 15 , the fifth proximity region 236E has a rectangular shape with its longer sides in the X-axis direction and its shorter sides in the Y-axis direction in plan view. The dimension of the fifth proximity region 236E in the X-axis direction is larger than the dimension of the gate pad 225 in the X-axis direction. The dimension of the fifth proximity region 236E in the Y-axis direction is approximately equal to the dimension of the gate pad 225 in the Y-axis direction. When viewed from the X-axis direction, the fifth proximity region 236E approximately overlaps with the gate pad 225.

[0192] The sixth proximity region 236F is disposed closer to the fourth side surface 304 than the gate pad 225. The sixth proximity region 236F is adjacent to the gate pad 225. The sixth proximity region 236F is located on the opposite side of the gate pad 225 from the fifth proximity region 236E in the X-axis direction, and is disposed at approximately the same position as the fifth proximity region 236E in the Y-axis direction. The area of ​​the sixth proximity region 236F may be approximately equal to that of the fifth proximity region 236E in a plan view.

[0193] The seventh isolated region 238G and the eighth isolated region 238H are provided at positions farther away from the gate pad 25 than the fifth adjacent region 236E and the sixth adjacent region 236F. The seventh isolated region 238G is located in the semiconductor layer 12 closer to the first side surface 301 than the fifth proximity region 236E. The seventh isolated region 238G is located adjacent to the fifth proximity region 236E in the Y-axis direction. When viewed in the Y-axis direction, the seventh isolated region 238G includes a portion overlapping with the fifth proximity region 236E. When viewed in the Y-axis direction, the seventh isolated region 238G may include a region that protrudes toward the fourth side surface 304 beyond the fifth proximity region 236E.

[0194] 15 , the seventh remote region 238G has a rectangular shape with its short side in the X-axis direction and its long side in the Y-axis direction. In plan view, the area of ​​the seventh remote region 238G may be larger than the area of ​​the fifth nearby region 236E. The dimension of the seventh remote region 238G in the X-axis direction is larger than the dimension of the fifth nearby region 236E in the X-axis direction. The dimension of the seventh remote region 238G in the Y-axis direction is larger than the dimension of the fifth nearby region 236E in the Y-axis direction. For example, in plan view, the area of ​​the seventh remote region 238G may be three to five times the area of ​​the fifth nearby region 236E.

[0195] The eighth isolated region 238H is located in the semiconductor layer 12 closer to the first side surface 301 than the sixth proximity region 236F. The eighth isolated region 238H is located adjacent to the sixth proximity region 236F in the Y-axis direction. When viewed in the Y-axis direction, the eighth isolated region 238H includes a portion overlapping with the sixth proximity region 236F. When viewed in the Y-axis direction, the eighth isolated region 238H may include a region that protrudes toward the third side surface 303 beyond the sixth proximity region 236F.

[0196] 15 , the eighth isolated region 238H has a rectangular shape with its short side in the X-axis direction and its long side in the Y-axis direction. The dimension of the eighth isolated region 238H in the X-axis direction is larger than the dimension of the sixth adjacent region 236F in the X-axis direction. The dimension of the eighth isolated region 238H in the Y-axis direction is larger than the dimension of the sixth adjacent region 236F in the Y-axis direction. In a planar view, the area of ​​the eighth isolated region 238H may be larger than the area of ​​the sixth adjacent region 236F. In one example, the area of ​​the eighth isolated region 238H may be three to five times the area of ​​the sixth adjacent region 236F in a planar view.

[0197] The eighth isolated region 238H may be disposed in a position adjacent to the seventh isolated region 238G in the X-axis direction. In the example shown in Fig. 15, the eighth isolated region 238H is located closer to the fourth side surface 304 than the seventh isolated region 238G in the semiconductor layer 212. The eighth isolated region 238H may be in the same position as the seventh isolated region 238G in the Y-axis direction. In a plan view, the area of ​​the eighth isolated region 238H may be approximately equal to the area of ​​the seventh isolated region 238G.

[0198] [Configuration of distant and close regions] 16 and 17 , the semiconductor device 210 includes a semiconductor substrate 240, an epitaxial layer 242 disposed on the semiconductor substrate 240, a plurality of cell trenches 214 provided in the epitaxial layer 242, and a plurality of source contacts 262 provided in the epitaxial layer 242. The cell trenches 214 and the source contacts 262 may be arranged alternately. The semiconductor layer 212 includes the semiconductor substrate 240 and the epitaxial layer 242.

[0199] The semiconductor substrate 240 may be a SiC substrate, and the epitaxial layer 242 may be a SiC epitaxial layer. The semiconductor layer 212 may include a top surface 212A and a bottom surface 212B opposite the top surface 212A. The semiconductor substrate 240 may correspond to a drain region of the MISFET. The Z-axis direction is a direction perpendicular to the top surface 212A and the bottom surface 212B of the semiconductor layer 212.

[0200] The semiconductor layer 212 includes a drift region 244 disposed on a semiconductor substrate (drain region) 240 , a body region 246 disposed on the drift region 244 , and a source region 248 disposed on the body region 246 .

[0201] The drain region formed by the semiconductor substrate 240 may be an n-type region containing n-type impurities. The n-type impurity concentration of the semiconductor substrate 240 may be 1×10 18 cm -3 More than 1×10 21 cm -3The semiconductor substrate 240 may have a thickness of 5 μm or more and 300 μm or less.

[0202] The drift region 244 may be an n-type region containing n-type impurities at a concentration lower than that of the semiconductor substrate (drain region) 240. The n-type impurity concentration of the drift region 244 is 1×10 15 cm -3 More than 1×10 18 cm -3 The drift region 244 may have a thickness of 5 μm or more and 20 μm or less.

[0203] The drift region 244 may include a drift first concentration region 244A (low concentration region) with a relatively low concentration arranged on the semiconductor substrate 240, and a drift second concentration region 244B (high concentration region) arranged on the drift first concentration region 244A and having a higher concentration than the drift first concentration region 244A. The n-type impurity concentration of the drift first concentration region 244A is 1×10 15 cm -3 More than 1×10 17 cm -3 The n-type impurity concentration of the drift second concentration region 244B may be 1×10 16 cm -3 More than 1×10 18 cm -3 It may be the following:

[0204] Although not shown, a buffer region may be disposed between the semiconductor substrate 240 and the drift region 244. The buffer region may have a concentration gradient in which the n-type impurity concentration gradually decreases from the n-type impurity concentration of the semiconductor substrate 240 to the n-type impurity concentration of the drift region 244.

[0205] The body region 246 may be a p-type region containing p-type impurities. The p-type impurity concentration of the body region 246 may be 1×10 16 cm -3 More than 1×10 18 cm -3 It may be the following: The source region 248 may be an n-type region containing n-type impurities at a higher concentration than the drift second concentration region 244B. The n-type impurity concentration of the source region 248 may be 1×10 18 cm -3 More than 1×10 21 cm -3 It may be the following:

[0206] In this disclosure, n-type is also referred to as the first conductivity type, and p-type is also referred to as the second conductivity type. The n-type impurity may be, for example, P or As. The p-type impurity may be, for example, B or Al.

[0207] The semiconductor device 210 may further include a drain electrode 250 disposed on the bottom surface 212B of the semiconductor substrate 240. The drain electrode 250 is electrically connected to the semiconductor substrate (drain region) 240. The drain electrode 250 may be formed from at least one of Ti, Ni, palladium (Pd), Au, and Ag.

[0208] The cell trench 214 has an opening in the upper surface 212A of the semiconductor layer 212 and has a depth in the Z-axis direction. The cell trench 214 may have a depth of 0.1 μm or more and 3 μm or less. The cell trench 214 has a sidewall 214A and a bottom wall 214B. The cell trench 214 penetrates the source region 248 and the body region 246 of the semiconductor layer 212. The semiconductor layer 212 may further include a well region 247 disposed between the drift second concentration region 244B and the sidewall 214A and bottom wall 214B of the cell trench 214. The well region 247 may be a p-type region containing a higher concentration of p-type impurities than the body region 246. The p-type impurity concentration of the well region 247 is 1×10 16 cm -3 More than 1×10 18 cm -3 It may be the following:

[0209] The semiconductor device 210 includes a mesa region 220, which is a region between two adjacent cell trenches 214 among the plurality of cell trenches 214 in a plan view. 15, the multiple source contacts 262 are each disposed in a mesa region 220 between two adjacent cell trenches 214 among the multiple cell trenches 214 in a plan view. Each source contact 262 may extend parallel to the cell trench 214 in a plan view. The source contact 262 may be a plug embedded in an insulating layer 216 configured to be rectangular in a plan view and groove-shaped in a cross-sectional view. As shown in FIGS. 16 and 17, the source contact 262 penetrates the insulating layer 216 and reaches the body region 46 of the semiconductor layer 212.

[0210] The epitaxial layer 242 may further include a contact region 264 in the body region 246. The contact region 264 may be a p-type region containing p-type impurities. The p-type impurity concentration of the contact region 264 may be higher than that of the body region 246. For example, the p-type impurity concentration of the contact region 264 may be 1×10 19 cm -3 More than 1×10 21 cm -3 The source contact 262 extends from the contact portion between the source contact 262 and the source wiring 222, through the insulating layer 216 and the source region 248 provided in the surface portion of the body region 246, and so as to contact the contact region 264. As a result, the source contact 262 electrically connects the source region 248 and the body region 246. The source contact 262 also electrically connects the source wiring 222 and the body region 246.

[0211] The semiconductor device 210 further includes a plurality of gate electrodes 258. Each of the plurality of gate electrodes 258 is embedded in the cell trench 214 via an insulating layer 216. The gate electrodes 258 may be configured to receive a gate voltage, and the source wiring 222 may be configured to receive a reference voltage (or source voltage). In one example, the gate electrodes 258 may be made of conductive polysilicon.

[0212] The semiconductor device 210 may further include a plurality of gate contacts 268. As shown in FIG. 15 , the gate wiring 224 is connected to the gate electrodes 258 provided in the respective cell trenches 214 via the plurality of gate contacts 268. As shown in FIGS. 16 and 17 , the insulating layer 216 is disposed with a trapezoidal cross section so as to cover the opening of the gate electrode 258, and separates the gate electrode 258 from the source wiring 222.

[0213] As shown in FIG. 15 , the semiconductor device 210 may further include a plurality of field plate trenches 218 and a field plate contact 278. A plurality of cell trenches 214 and a field plate trench 218 are provided in each of the fifth proximity region 236E, the sixth proximity region 236F, the seventh isolation region 238G, and the eighth isolation region 238H. Their planar configuration may be the same as that of the first isolation region 38A (see FIG. 2 ) in the first embodiment. Although not shown, a field plate electrode provided in the field plate trench 218 may be connected to the source wiring 222 via the field plate contact 278. Because the field plate electrode is electrically connected to the source wiring 222, it is possible to alleviate electric field concentration in the drift region 244 adjacent to the field plate trench 218.

[0214] In the fifth proximity region 236E, the sixth proximity region 236F, the seventh isolated region 238G, and the eighth isolated region 238H, each cell trench 214 intersects with the gate wiring 224 in a planar view. The gate electrode 258 provided in the cell trench 214 is connected to the gate wiring 224 via a gate contact 68 arranged at a position intersecting with the gate wiring 224. Furthermore, the source contact 62 provided in each mesa region 220 extends in the X-axis direction in a planar view.

[0215] [Source Contact Configuration] 15 to 17, the configuration of the source contacts 262 in the isolated region 238 and the proximal region 236 will be described. As shown in Fig. 15, the source contact 262 includes a proximal contact 265 and a distal contact 263, similar to the first embodiment.

[0216] As shown in FIG. 15 , the remote contact 263 is one of the multiple source contacts 262 that is provided in the remote region 238. In the third embodiment, the remote contact 263 is provided in each of the seventh remote region 238G and the eighth remote region 238H. The proximal contact 265 is one of the multiple source contacts 262 that is provided in the proximal region 236. In the third embodiment, the proximal contact 265 is provided in each of the fifth proximal region 236E and the sixth proximal region 236F. Here, the seventh remote region 238G and the eighth remote region 238H are provided at positions farther away from the gate pad 225 than the fifth proximal region 236E and the sixth proximal region 236F. Therefore, the remote contact 263 can be said to be located at a position farther away from the gate pad 225. On the other hand, the proximal contact 265 can be said to be located closer to the gate pad 225 than the remote contact 263.

[0217] 15, a plurality of remote contacts 263 are provided in the remote region 238. In the third embodiment, a plurality of remote contacts 63 are provided in each of the seventh remote region 238G and the eighth remote region 238H. The plurality of remote contacts 263 can be said to include a plurality of seventh remote contacts 263G provided in the seventh remote region 238G and a plurality of eighth remote contacts 263H provided in the eighth remote region 238H.

[0218] The seventh remote contact 263G (source contact 262) and the eighth remote contact 263H (source contact 262) are provided in each mesa region 220 in the seventh remote region 238G and the eighth remote region 238H. That is, the number of the seventh remote contacts 263G and the eighth remote contacts 263H is equal to the number of the mesa regions 220 in the seventh remote region 238G and the eighth remote region 238H. Therefore, since the numbers of the mesa regions 220 in the seventh remote region 238G and the eighth remote region 238H are different from each other, the numbers of the seventh remote contacts 263G and the eighth remote contacts 263H may differ from each other depending on the numbers of the mesa regions 220 in the seventh remote region 238G and the eighth remote region 238H.

[0219] The seventh remote contacts 263G are arranged at the same positions in the X-axis direction and spaced apart from one another in the Y-axis direction. Each of the seventh remote contacts 263G extends in the X-axis direction in plan view. That is, each of the seventh remote contacts 263G is strip-shaped and has a width in the Y-axis direction and extends in the X-axis direction in plan view.

[0220] The eighth remote contacts 263H are arranged at the same positions in the X-axis direction and spaced apart from one another in the Y-axis direction. Each of the eighth remote contacts 263H extends in the X-axis direction in plan view. That is, each of the eighth remote contacts 263H has a strip shape that has a width in the Y-axis direction and extends in the X-axis direction in plan view.

[0221] The seventh remote contact 263G and the eighth remote contact 263H each have a first width W1. That is, in a plan view, the dimension of the seventh remote contact 263G in the Y-axis direction is the first width W1, and the dimension of the eighth remote contact 263H in the Y-axis direction is also the first width W1. Thus, in the third embodiment, the seventh remote contact 263G and the eighth remote contact 263H have the same width.

[0222] A plurality of proximity contacts 265 are provided in the proximity region 236. In the third embodiment, a plurality of proximity contacts 265 are provided in each of the fifth proximity region 236E and the sixth proximity region 236F. The plurality of proximity contacts 265 can be said to include a plurality of fifth proximity contacts 265E provided in the fifth proximity region 236E and a plurality of sixth proximity contacts 265F provided in the sixth proximity region 236F.

[0223] Since the fifth proximity contact 265E and the sixth proximity contact 265F are provided in each mesa region 220 of the fifth proximity region 236E and the sixth proximity region 236F, the number of the fifth proximity contacts 265E and the sixth proximity contacts 265F may differ from each other depending on the number of mesa regions 220 of the fifth proximity region 236E and the sixth proximity region 236F.

[0224] The multiple fifth proximity contacts 265E are arranged at the same positions in the X-axis direction and spaced apart from each other in the Y-axis direction. Each fifth proximity contact 265E extends in the X-axis direction in plan view. Each fifth proximity contact 265E is strip-shaped and has a width in the Y-axis direction and extends in the X-axis direction in plan view.

[0225] The sixth proximity contacts 265F are arranged at the same positions in the X-axis direction and spaced apart from one another in the Y-axis direction. Each sixth proximity contact 265F extends in the X-axis direction in plan view. Each sixth proximity contact 265F is strip-shaped and has a width in the Y-axis direction and extends in the X-axis direction in plan view.

[0226] The length in the X-axis direction of the fifth proximal contact 265E may be approximately equal to the length in the Y-axis direction of the sixth proximal contact 265F. The length in the X-axis direction of the fifth proximal contact 265E may be shorter than the length in the X-axis direction of the seventh remote contact 263G. The length in the X-axis direction of the sixth proximal contact 265F may be shorter than the length in the X-axis direction of the eighth remote contact 263H. The length in the X-axis direction of the seventh remote contact 263G may be approximately equal to the length in the X-axis direction of the eighth remote contact 263H.

[0227] The fifth proximity contact 265E and the sixth proximity contact 265F each have a second width W2 that is larger than the first width W1. That is, in plan view, the dimension in the Y-axis direction of the fifth proximity contact 265E is the second width W2, and the dimension in the Y-axis direction of the sixth proximity contact 265F is the second width W2. Thus, in the third embodiment, the fifth proximity contact 265E and the sixth proximity contact 265F have the same width.

[0228] 16 and 17, the remote contact 263 and the proximal contact 265 have similar configurations but different widths. The proximal contact 265 shown in FIG. 16 has a second width W2, and the remote contact 263 shown in FIG. 17 has a first width W1.

[0229] [Effects of the third embodiment] According to the semiconductor device 210 of the third embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

[0230] (3-1) The semiconductor layer 212 is made of SiC. With this configuration, even when the semiconductor layer 212 is made of SiC, by increasing the second width W2 of the proximity contact 265 disposed in the body region 246 of the MISFET close to the gate pad 225, the current generated by an inductive load during the turn-off operation of the semiconductor device 210 can be efficiently conducted by the proximity contact 265 having the second width W2. As a result, the inductive load tolerance of the semiconductor device 210 can be improved.

[0231] <Example of change> Each embodiment can be modified as follows: Each embodiment and the following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0232] In the first to third embodiments, the positional relationship between the remote contacts 63 (263) and the proximal contacts 65 (265) and the gate pad 25 (225) can be changed as desired. In one example, the remote contacts 63 (263) may include contacts arranged near the gate pad 25 (225). In another example, the proximal contacts 65 (265) may include contacts arranged at a distance from the gate pad 25 (225).

[0233] In the first to third embodiments, the positional relationship between the isolated region 38 (238) and the adjacent region 36 (236) and the gate pad 25 (225) can be changed as desired. In one example, the isolated region 38 (238) may include a region located near the gate pad 25 (225). In another example, the adjacent region 36 (236) may include a region located at a distance from the gate pad 25 (225).

[0234] In the first to third embodiments, the number of isolated regions 38 (238) and adjacent regions 36 (236) can be changed as desired. In one example, the isolated region 38 (238) may be a single region located near the gate pad 25 (225). In another example, the adjacent region 36 (236) may be a single region located near the gate pad 25 (225).

[0235] In the first to third embodiments, the number of remote contacts 63 (263) provided in the remote region 38 (238) and the number of proximal contacts 65 (265) provided in the proximal region 36 (236) can be changed as desired. In one example, the number of remote contacts 63 (263) may be one. In another example, the number of proximal contacts 65 (265) may be one.

[0236] In the first to third embodiments, the shape of the source contact 62 (262) can be changed as desired. For example, the source contact 62 (262) may be a via hole embedded in the insulating layer 16 (216) that is square in plan view and well-shaped in cross section, rather than a groove-shaped one.

[0237] In the first to third embodiments, the positional relationship between the proximity region 36 (236) and the gate pad 25 (225) can be changed as desired. In one example, the proximity region 36 (236) does not have to be adjacent to the gate pad 25 (225). In another example, the proximity region 36 (236) does not have to be adjacent to the gate pad 25 (225) in the X-axis direction, and does not have to be adjacent to the gate pad 25 (225) in the Y-axis direction.

[0238] In the first to third embodiments, the shape of the semiconductor layer 12 (212) can be changed as desired. The semiconductor layer 12 (212) does not have to be rectangular, and may be polygonal or circular.

[0239] In the first to third embodiments, the arrangement of the proximity contacts 65 (265) in the proximity region 36 (236) can be changed as desired. For example, the proximity contacts 65 (265) do not have to extend in the Y-axis direction, or be arranged in the X-axis direction, or extend in the X-axis direction, or be arranged in the Y-axis direction.

[0240] In the first to third embodiments, the arrangement of the isolated contacts 63 (263) in the isolated region 38 (238) can be changed as desired. In one example, the isolated contacts 63 (263) do not have to extend in the Y-axis direction or be arranged in the X-axis direction. In another example, the isolated contacts 63 (263) do not have to extend in the X-axis direction or be arranged in the Y-axis direction.

[0241] In the first to third embodiments, the position of the gate pad 25 (225) can be changed as desired. For example, it does not have to be located at a corner or near any one side of the semiconductor layer 12 (212).

[0242] In the first embodiment, the number of first proximity contacts 65A and the number of second proximity contacts 65B can be changed as desired. In one example, the number of first proximity contacts 65A may be one. In another example, the number of second proximity contacts 65B may be one.

[0243] In the first embodiment, the arrangement of the first proximity contacts 65A and the second proximity contacts 65B can be changed as desired. In one example, the first proximity contacts 65A may extend in the X-axis direction and be arranged in the Y-axis direction. In another example, the second proximity contacts 65B may extend in the Y-axis direction and be arranged in the X-axis direction.

[0244] In the first to third embodiments, the arrangement of the isolated region 38 (238) and the adjacent region 36 (236) can be changed as desired. For example, the isolated region 38 (238) may or may not be arranged on the opposite side of the adjacent region 36 (236) from the gate pad 25 (225).

[0245] In the first to third embodiments, the position of the source contact 62 (262) within the semiconductor layer 12 (212) can be arbitrarily changed. For example, the source contact 62 (262) may be electrically connected to the body region 46 (246) via the contact region 64 (264) without penetrating the insulating layer 16 (216) to reach the body region 46 (246) of the mesa region 20 (220).

[0246] In the first to third embodiments, the connection between the source contact 62 (262), the source region 48 (248), and the body region 46 (246) can be changed as desired. For example, the connection may be made via wiring on the insulating layer 16, rather than via the source contact 62 (262).

[0247] In the first to third embodiments, the arrangement of the body region 46 (246) can be changed as desired. For example, the body region 46 (246) may be exposed on the upper surface 12A (212A) of the semiconductor layer 12 (212).

[0248] In the first to third embodiments, the positional relationship between the proximal contact 65 (265), which is closer to the gate pad 25 (225) than the distal contact 63 (263), and the gate wiring 24 (224) can be changed as desired. For example, the proximal contact 65 (265) may be closer to the gate contact 68 (268) rather than closer to the gate wiring 24 (224).

[0249] In the first to third embodiments, the distance between the end 14C (214C) on the mesa region 20 (220) side and the sidewall 62X (262X) of the source contact 62 (262) in the isolation region 38 (238) or the proximity region 36 (236) can be changed as desired. For example, it may be less than 0.22 μm, or in another example, it may be 0.3 μm or more.

[0250] In the first to third embodiments, the width of the source contact 62 (262) can be changed arbitrarily. The first width W1 may be 0.1 μm or less or greater than 0.16 μm, and the second width W2 may be 0.16 μm or less or greater than 0.32 μm.

[0251] In the first to third embodiments, in a cross section of the source contact 62 (262), as shown in FIG. 3, for example, the sidewall 62X extends along the Z-axis direction and the bottom 62Y is parallel to the Y-axis direction. In another example, the sidewall 62X may extend along the Z-axis direction or may be inclined with respect to the Z-axis direction. The sidewall 62X may be inclined with respect to the Z-axis direction so that the width W of the source contact 62 decreases toward the bottom 62Y. In addition, the bottom 62Y of the source contact 62 does not necessarily have to be flat; for example, it may be partially or entirely curved.

[0252] Therefore, the first width W1 may vary depending on the depth position of the distant contact 63 (263), and the second width W2 may vary depending on the depth position of the proximal contact 65 (265). In one example, the first width W1 and the second width W2 may be compared using maximum values. In another example, they may be compared using minimum values.

[0253] 18 is a schematic cross-sectional view of a semiconductor device 10 according to a modified example, showing a portion corresponding to the schematic cross-sectional view of the semiconductor device 10 of the first embodiment shown in FIG. In the semiconductor device 10 of this modified example, the source contacts 62A and 62B closer to the gate pad 25 are proximate contacts 65 having a second width W2. The source contact 62C located at a distance from the gate pad 25 is a remote contact 63 having a first width W1.

[0254] In the first to third embodiments, the positions where the proximity contacts 65 (365) are arranged and the positions where the remote contacts 63 (363) are arranged may be separated in the proximity region 36 (236) in this way.

[0255] In the first to third embodiments, the location of the proximal contact 65 (265) can be changed as desired. In one example, the proximal contact 65 (365) may be located closer to the gate pad 25 (225) than the remote contact 63 (363) and closer to the gate wiring 24 (224). In another example, the proximal contact 65 may be a source contact 62 (262) adjacent to the gate electrode 58 (258) that is located closer to the gate wiring 24 (224) even if it is not close to the gate pad 25 (225).

[0256] In the first to third embodiments, the shape of the source contact 62 (262) can be changed as desired. For example, the source contact 62 (262) is a plug embedded in the insulating layer 16 (216) that is rectangular in plan view and groove-shaped in cross section, but the groove width does not need to be constant. The groove width may be increased only in a portion adjacent to the gate electrode 58 (258) that is located near the gate pad 25 (225) and closer to the gate wiring.

[0257] Each embodiment can be modified as follows: Each embodiment and the following modifications can be combined with each other to the extent that no technical contradiction occurs. One or more of the various examples described in the present disclosure may be combined to the extent that they are not technically inconsistent.

[0258] The term "on" as used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is provided between the first element and the second element.

[0259] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, the various structures according to this disclosure are not limited to the "up" and "down" in the Z-axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0260] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0261] [Appendix 1] a semiconductor layer (12) having a body region (46); A plurality of cell trenches (14) provided in the semiconductor layer (12); an insulating layer (16) provided within the plurality of cell trenches (14) and on the semiconductor layer (12); a plurality of gate electrodes (58) embedded in the plurality of cell trenches (14) via the insulating layer (16); a gate pad (25) provided on the insulating layer (16) and electrically connected to the plurality of gate electrodes (58); a source wiring (22) provided on the insulating layer (16); a plurality of contacts (62) that are respectively arranged between two adjacent cell trenches (14) among the plurality of cell trenches (14) in a plan view and connect the source wiring (22) and the body region (46); Equipped with The plurality of contacts (62) a spaced contact (63) disposed at a position spaced from the gate pad (25) and having a first width (W1); a proximity contact (65) disposed closer to the gate pad (25) than the remote contact (63) and having a second width (W2) greater than the first width (W1); A semiconductor device (10) comprising:

[0262] [Appendix 2] The semiconductor layer (12) is a separation region (38) spaced apart from the gate pad (25); a proximity region (36) located closer to the gate pad (25) than the isolation region (38); Including, The separation contact (63) is provided in plurality in the separation region (38), The proximity contacts (65) are provided in plurality in the proximity region (36). The semiconductor device (10) according to appendix 1.

[0263] [Appendix 3] The proximity region (36) is adjacent to the gate pad (25). 3. The semiconductor device according to claim 2.

[0264] [Appendix 4] The semiconductor layer (12) has a rectangular shape in a plan view, and has a first side surface (101) and a second side surface (102) that are both side surfaces in a first direction (Y), and a third side surface (103) and a fourth side surface (104) that are both side surfaces in a second direction (X) that is perpendicular to the first direction (Y), the gate pad (25) is disposed at a corner portion defined by the second side surface (102) and the fourth side surface (104) of the semiconductor layer (12); The adjacent region (36) is a first proximity region (36A) disposed at a position adjacent to the gate pad (25) in the second direction (X); a second proximity region (36B) disposed at a position adjacent to the gate pad (25) in the first direction (Y); Including, The plurality of adjacent contacts (65) a plurality of first proximity contacts (65A) provided in the first proximity region (36A); a plurality of second proximity contacts (65B) provided in the second proximity region (36B); Contains The semiconductor device (10) according to appendix 2 or 3.

[0265] [Appendix 5] The plurality of first proximity contacts (65A) extend in the first direction (Y) and are arranged in the second direction (X). The semiconductor device (10) according to appendix 4.

[0266] [Appendix 6] The plurality of second proximity contacts (65B) extend in the second direction (X) and are arranged in the first direction (Y). A semiconductor device (10) according to appendix 4 or 5.

[0267] [Appendix 7] the isolation region (38) includes a second isolation region (38B) disposed on the opposite side of the second proximity region (36B) from the gate pad (25); the plurality of proximity contacts (65) include a plurality of second proximity contacts (65B) provided in the second proximity region (36B); the plurality of spaced contacts (63) include a plurality of second spaced contacts (63B) provided in the second spaced region (38B); The second width (W2) of the second proximate contact (65B) is greater than the first width (W1) of the second distant contact (63B). A semiconductor device (10) according to any one of appendices 4 to 6.

[0268] [Appendix 8] The semiconductor layer (12) has a rectangular shape in a plan view, and has a first side surface (101) and a second side surface (102) that are both side surfaces in a first direction (Y), and a third side surface (103) and a fourth side surface (104) that are both side surfaces in a second direction (X) that is perpendicular to the first direction (Y), the gate pad (25) is disposed on the second side surface (102) of the semiconductor layer (12) and between the third side surface and the fourth side surface, The adjacent region (36) is a third proximity region (36C) adjacent to the gate pad (25) on the third side surface (103) side; a fourth proximity region (36D) adjacent to the gate pad (25) on the fourth side surface (104) side; Including, The plurality of adjacent contacts (65) a plurality of third proximity contacts (65C) provided in the third proximity region (36C); a plurality of fourth proximity contacts (65D) provided in the fourth proximity region (36D); Contains The semiconductor device (10) according to appendix 2 or 3.

[0269] [Appendix 9] The first width (W1) may vary depending on the depth position of the spaced contact (63), The second width (W2) can vary depending on the position of the proximity contact (65) in the depth direction, The maximum value of the second width (W2) is greater than the maximum value of the first width (W1). A semiconductor device (10) according to any one of appendices 1 to 8.

[0270] [Appendix 10] the semiconductor layer (12) includes a mesa region (20) that is a region between two adjacent cell trenches (14) among the plurality of cell trenches (14) in a plan view; The plurality of contacts (62) penetrate the insulating layer (16) to reach the body region (46) of the mesa region (20). A semiconductor device (10) according to any one of appendices 1 to 9.

[0271] [Appendix 11] the semiconductor layer (12) includes a source region (48) provided in a surface layer portion of the body region (46); The plurality of contacts (62) electrically connect the source region (48) and the body region (46). A semiconductor device (10) according to any one of appendices 1 to 10.

[0272] [Appendix 12] The semiconductor device (10) includes a gate wiring (24) and a gate contact (68) that connect the gate electrode (58) and the gate pad (25), The proximate contact (65) is located closer to the gate pad (25) than the remote contact (63) and closer to the gate wiring (24). A semiconductor device (10) according to any one of appendices 1 to 11.

[0273] [Appendix 13] The semiconductor layer (12) has an isolation region (38) located at a position spaced apart from the gate pad (25); a proximity region (36) located closer to the gate pad (25) than the isolation region (38); a mesa region (20) that is a region between two adjacent cell trenches (14) among the plurality of cell trenches (14) in a plan view, Both the proximal contact (65) and the distal contact (63) have sidewalls (62X) that penetrate the insulating layer (16) and reach the semiconductor layer (12), a bottom (62Y), and Including, The mesa region (20) is an isolated mesa region (20A) to which the bottom (63Y) of the isolated contact (63) is connected; a proximal mesa region (20B) to which the bottom (65Y) of the proximal contact (65) is connected; Including, In the isolated mesa region (20A), the distance between an end (14C) of the cell trench (14) on the mesa region (20) side and a sidewall (65X) of the contact (65) in the adjacent region (36), and the distance between the end (14C) of the cell trench (14) on the mesa region (20) side and a sidewall (63X) of the contact (63) in the isolated region (38) are 0.22 μm or more and less than 0.3 μm; In the adjacent mesa region (20B), the distance between an end (14C) of the cell trench (14) on the mesa region (20) side and a sidewall (65X) of the contact (65) in the adjacent region (36), and the distance between the end (14C) of the cell trench (14) on the mesa region (20) side and a sidewall (63X) of the contact (63) in the isolation region (38) are 0.22 μm or more and less than 0.3 μm. A semiconductor device (10) according to any one of appendices 1 to 12.

[0274] [Appendix 14] The distance between an end (14C) of the cell trench (14) on the mesa region (20) side in the adjacent mesa region (20B) and a sidewall (65X) of the contact (65) in the adjacent mesa region (20B) is smaller than the distance between an end (14C) of the cell trench (14) on the mesa region (20) side in the remote mesa region (20A) and a sidewall (63X) of the contact (63) in the remote mesa region (20A). The semiconductor device (10) according to appendix 13.

[0275] [Appendix 15] the first width (W1) is greater than 0.1 μm and equal to or less than 0.16 μm; The second width (W2) is greater than 0.16 μm and equal to or less than 0.32 μm. A semiconductor device (10) according to any one of appendices 1 to 14.

[0276] [Appendix 16] The semiconductor layer (12) is made of SiC. A semiconductor device (10) according to any one of appendices 1 to 15.

[0277] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0278] 10...Semiconductor device 12...Semiconductor layer 12A…Top surface 12B…Bottom surface 14...Cell trench 14A…Side wall 14B…Bottom wall 14C...end 16...Insulating layer 18...Field plate trench 18A…Side wall 18B…Bottom wall 18P...Edge field plate trench 18Q...Peripheral field plate trench 20...Mesa area 20A...isolated mesa region 20B: Adjacent mesa region 22...Source wiring 23...medial segment 24...Gate wiring 25...Gate pad 26...Periphery gate finger 26A...First outer gate finger 26B...Second outer gate finger 26C...Third outer gate finger 26D...4th outer gate finger 28...Outer segment 28A...First outer segment 28B: Second outer segment 28C…Third outer segment 28D...4th outer segment 30…Gap 32…Inner area 34…Outer area 36...Proximity area 36A...First proximity area 36B...Second proximity area 36C...Third close-in area 36D...4th proximity area 38…isolated area 38A…1st isolation area 38B…Second isolation area 38C...Third isolation area 38D…4th isolation area 38E...5th isolated area 38F…6th isolation area 40...Semiconductor substrate 42...Epitaxial layer 44...Drift region 46...Body area 48...Source region 50...Drain wiring 58...Gate electrode 58A…Top surface 58B…Bottom surface 58C…side 60...First field plate electrode 61A…First end electrode 61B…Second end electrode 62, 62A, 62B, 62C...Source contact 62X…Side wall 62Y…Bottom 63...Separate contact 63A...First isolation contact 63B...Second Separation Contact 63C...Third Separate Contact 63D...4th Separated Contact 63E...5th Separated Contact 63F...6th isolated contact 63X…Side wall 63Y…Bottom 64...Contact area 65...Proximal contact 65A...1st adjacent contact 65B...Second proximity contact 65C...Third adjacent contact 65D...4th proximal contact 65X…Side wall 65Y…Bottom 66...Gate insulation 68...Gate contact 78...Field plate contact 80...Second field plate electrode 80A…Top end 81A…First end electrode 81B…Second end electrode 101…1st side 102…Second side 103…Third side 104…Fourth side 210...Semiconductor device 212...Semiconductor layer 214...Cell trench 214A…Side wall 216...insulating layer 220...Mesa area 222...Source wiring 224...Gate wiring 225...Gate pad 236...Proximity area 238…isolated area 246...Body area 248...Source region 258...Gate electrode 263...Separate Contact 263G...7th Separated Contact 263H...8th isolated contact 265...Proximity Contact 265E…5th proximity contact 265F...6th close contact 268...Gate contact D1,D2…distance G1: First interval L1, L2...Mesa length W: Contact width W1…1st width W2...Second width

Claims

1. a semiconductor layer having a body region; a plurality of cell trenches provided in the semiconductor layer; an insulating layer provided in the plurality of cell trenches and on the semiconductor layer; a plurality of gate electrodes embedded in the plurality of cell trenches via the insulating layer; a gate pad provided on the insulating layer and electrically connected to the plurality of gate electrodes; a source wiring provided on the insulating layer; a plurality of contacts that are respectively arranged between two adjacent ones of the plurality of cell trenches in a plan view and connect the source wiring and the body region; Equipped with The plurality of contacts a spaced contact disposed at a location spaced from the gate pad and having a first width; a proximity contact disposed closer to the gate pad than the remote contact and having a second width greater than the first width; 10. A semiconductor device comprising:

2. The semiconductor layer is an isolation region spaced apart from the gate pad; a proximity region located closer to the gate pad than the isolation region; Including, a plurality of the isolated contacts are provided in the isolated region; A plurality of the proximity contacts are provided in the proximity region. The semiconductor device according to claim 1 .

3. The proximity region is adjacent to the gate pad. The semiconductor device according to claim 2 .

4. the semiconductor layer has a rectangular shape in a plan view, and includes a first side surface and a second side surface which are both side surfaces in a first direction, and a third side surface and a fourth side surface which are both side surfaces in a second direction perpendicular to the first direction, the gate pad is disposed at a corner portion defined by the second side surface and the fourth side surface of the semiconductor layer, The adjacent region is a first proximity region disposed adjacent to the gate pad in the second direction; a second proximity region disposed adjacent to the gate pad in the first direction; Including, The plurality of proximal contacts include: a plurality of first proximity contacts provided in the first proximity region; a plurality of second proximity contacts provided in the second proximity region; Contains The semiconductor device according to claim 2 .

5. The plurality of first proximity contacts extend in the first direction and are arranged in the second direction. The semiconductor device according to claim 4 .

6. The plurality of second proximity contacts extend in the second direction and are arranged in the first direction. The semiconductor device according to claim 4 .

7. the isolation region includes a second isolation region disposed on an opposite side of the second proximity region from the gate pad, the plurality of proximity contacts include a plurality of second proximity contacts provided in the second proximity region; the plurality of spaced contacts include a plurality of second spaced contacts provided in the second spaced region; The second width of the second proximal contact is greater than the first width of the second distal contact. The semiconductor device according to claim 4 .

8. the semiconductor layer has a rectangular shape in a plan view, and includes a first side surface and a second side surface which are both side surfaces in a first direction, and a third side surface and a fourth side surface which are both side surfaces in a second direction perpendicular to the first direction, the gate pad is disposed on the second side surface side of the semiconductor layer and between the third side surface and the fourth side surface, The adjacent region is a third proximity region adjacent to the gate pad on the third side; a fourth proximity region adjacent to the gate pad on the fourth side; Including, The plurality of proximal contacts include: a plurality of third proximity contacts provided in the third proximity region; a plurality of fourth proximity contacts provided in the fourth proximity region; Contains The semiconductor device according to claim 2 .

9. the first width may vary depending on a depth position of the spaced contact; the second width may vary depending on the depth position of the proximity contact; The maximum value of the second width is greater than the maximum value of the first width. The semiconductor device according to any one of claims 1 to 8.

10. the semiconductor layer includes a mesa region that is a region between two adjacent cell trenches among the plurality of cell trenches in a plan view, The contacts extend through the insulating layer to the body region of the mesa region. The semiconductor device according to any one of claims 1 to 8.

11. the semiconductor layer includes a source region provided in a surface layer portion of the body region, The plurality of contacts electrically connect the source region and the body region. The semiconductor device according to any one of claims 1 to 8.

12. the semiconductor device includes a gate wiring and a gate contact that connect the gate electrode and the gate pad; The adjacent contact is disposed closer to the gate pad than the remote contact and closer to the gate wiring. The semiconductor device according to any one of claims 1 to 8.

13. the semiconductor layer includes an isolation region located at a position separated from the gate pad; a proximity region located closer to the gate pad than the isolation region; a mesa region that is a region between two adjacent cell trenches among the plurality of cell trenches in a plan view, Both the proximal contact and the distal contact have sidewalls that penetrate the insulating layer and reach the semiconductor layer, a bottom, and Including, The mesa region is an isolated mesa region to which the bottom of the isolated contact is connected; a proximal mesa region to which the bottom of the proximal contact is connected; Including, In both the remote mesa region and the adjacent mesa region, The distance between the end of the cell trench on the mesa region side and the sidewall of the contact in the proximity region and the distance between the end of the cell trench on the mesa region side and the sidewall of the contact in the isolation region are 0.22 μm or more and less than 0.3 μm. The semiconductor device according to any one of claims 1 to 8.

14. The distance between the end of the cell trench on the mesa region side in the adjacent mesa region and the sidewall of the contact in the adjacent mesa region is smaller than the distance between the end of the cell trench on the mesa region side in the remote mesa region and the sidewall of the contact in the remote mesa region. The semiconductor device according to claim 13.

15. the first width is greater than 0.1 μm and equal to or less than 0.16 μm; The second width is greater than 0.16 μm and equal to or less than 0.32 μm. The semiconductor device according to any one of claims 1 to 8.

16. The semiconductor layer is made of SiC. The semiconductor device according to any one of claims 1 to 8.

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