Semiconductor device

Abstract

To increase a ratio of an active area of a semiconductor device.SOLUTION: The semiconductor device 10 includes a semiconductor layer 12 including a plurality of gate trenches 20 and a plurality of connection trenches 22 connecting the plurality of gate trenches 20. The first gate electrodes 40A extend into the plurality of gate trenches 20 through the plurality of first intermediate connection trenches 18A that overlap the first region 22A of the source wiring 18 in plan view. The first gate electrodes 40A overlap with the gate-finger-portion 16Y in a plan view in the first gate trenches 50 among the plurality of gate trenches 20. The second gate electrodes 40B extend into the plurality of gate trenches 20 through the plurality of second intermediate connection trenches 18B that overlap the second region 22B of the source wiring 18 in plan view. The second gate electrodes 40B overlap the gate-finger-portion 16Y in a plan view in the second gate trenches 52 among the plurality of gate trenches 20.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a metal insulator semiconductor field effect transistor (MISFET) having a trench gate structure. In the semiconductor device of Patent Document 1, a gate electrode embedded in each of a plurality of gate trenches is electrically connected to a gate terminal electrode including gate fingers extending in strip-like shapes in an outer region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-202313

[0004] [overview] In a semiconductor device including a MISFET having a trench gate structure, it is desired to increase the proportion of an active area that can be driven as a transistor.

[0005] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor layer including a plurality of gate trenches extending in a first direction and spaced apart from one another in a second direction intersecting the first direction in a plan view, and a plurality of connection trenches connecting the plurality of gate trenches; an insulating layer located on the semiconductor layer; first and second gate electrodes spaced apart from one another in the first direction within the plurality of gate trenches; a field plate electrode located within the plurality of gate trenches; a gate wiring located on the insulating layer and electrically connected to the first and second gate electrodes; and a source wiring located on the insulating layer and electrically connected to the field plate electrode. The gate wiring includes gate finger portions extending in the second direction, and the gate finger portions intersect the plurality of gate trenches in a plan view. The source wiring includes a first region and a second region spaced apart from one another in the first direction by the gate finger portions. The plurality of connection trenches include a plurality of first intermediate connection trenches overlapping the first region in a plan view and a plurality of second intermediate connection trenches overlapping the second region in a plan view. The first gate electrode extends into the gate trenches through the first intermediate connection trenches and overlaps with the gate finger portions in a first gate trench among the gate trenches in a plan view, and the second gate electrode extends into the gate trenches through the second intermediate connection trenches and overlaps with the gate finger portions in a second gate trench among the gate trenches that is different from the first gate trench in a plan view.

[0006] Other features and aspects will become apparent from the following detailed description, drawings, and claims. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to a first embodiment of the present disclosure. [Figure 2]FIG. 2 is a schematic cross-sectional view of the semiconductor device taken along line F2-F2 in FIG. [Figure 3] FIG. 3 is an enlarged schematic plan view showing an example of the arrangement of the first gate electrodes and the second gate electrodes in the semiconductor device shown in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the semiconductor device taken along line F4-F4 in FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the semiconductor device taken along line F6-F6 in FIG. [Figure 7] FIG. 7 is a schematic plan view of a semiconductor device according to a first modification of the first embodiment. [Figure 8] FIG. 8 is a schematic plan view of a semiconductor device according to a second modification of the first embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view of the semiconductor device taken along line F9-F9 in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view of the semiconductor device taken along line F10-F10 in FIG. [Figure 11] FIG. 11 is a schematic plan view of an exemplary semiconductor device according to the second embodiment of the present disclosure. [Figure 12] FIG. 12 is a schematic plan view of an exemplary semiconductor device according to a third embodiment of the present disclosure. [Figure 13] FIG. 13 is a schematic plan view of an exemplary semiconductor device according to the fourth embodiment of the present disclosure. [Figure 14] FIG. 14 is an enlarged plan view showing an example of the arrangement of the first gate electrodes and the second gate electrodes in the semiconductor device shown in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view of the semiconductor device taken along line F15-F15 in FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a modified example of the field plate electrode. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a modified example of the field plate electrode.

[0008] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. The same reference numerals refer to the same elements throughout the drawings and detailed description. The drawings may not be to scale, and the relative size, proportions, and depictions of elements in the drawings may be exaggerated for clarity, explanation, and convenience.

[0009] The following detailed description provides a comprehensive understanding of the described methods, devices, and / or systems. Modifications and equivalents of the described methods, devices, and / or systems will be apparent to those skilled in the art. Except for operations that necessarily occur in a particular order, the order of operations is illustrative and may be changed as would be apparent to one skilled in the art. Descriptions of functions and structures well known to those skilled in the art may be omitted. Example embodiments may have different forms and are not limited to the described examples.

[0010] First Embodiment An exemplary semiconductor device 10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 6. FIG. 1 is a schematic plan view of the semiconductor device 10. FIG. 2 is a schematic cross-sectional view of the semiconductor device 10 taken along line F2-F2 in FIG. 1. FIG. 3 is an enlarged schematic plan view showing an example of the arrangement of the first gate electrode 40A and the second gate electrode 40B in the semiconductor device 10. In FIG. 3, the insulating layer 14 covering the first gate electrode 40A and the second gate electrode 40B, the gate wiring 16, and the source wiring 18 are transparently shown to facilitate understanding of the arrangement of the first gate electrode 40A and the second gate electrode 40B. FIG. 4 is a schematic cross-sectional view of the semiconductor device 10 taken along line F4-F4 in FIG. 3. FIG. 5 is a schematic cross-sectional view of the semiconductor device 10 taken along line F5-F5 in FIG. 3. FIG. 6 is a schematic cross-sectional view of the semiconductor device 10 taken along line F6-F6 in FIG. 3. As will be understood from the following description, the semiconductor device 10 may be configured as a MISFET having a trench gate structure.

[0011] (Overall structure of semiconductor device) 1 to 6, semiconductor device 10 includes a semiconductor layer 12 and an insulating layer 14 located on semiconductor layer 12. In one example, semiconductor layer 12 may include silicon (Si). In one example, insulating layer 14 may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and hafnium oxide (HfO).

[0012] The semiconductor layer 12 may have a rectangular parallelepiped shape. The semiconductor layer 12 may include a first surface 12A, a second surface 12B opposite the first surface 12A, and a first side surface 12C1, a second side surface 12C2, a third side surface 12C3, and a fourth side surface 12C4 connecting the first surface 12A and the second surface 12B. The Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in FIG. 1 and other drawings intersects (e.g., is perpendicular to) the first surface 12A of the semiconductor layer 12. As used herein, the term "planar view" refers to a view drawn from a perspective looking down on the object from above along the Z-axis direction, unless explicitly stated otherwise. In the example shown in FIG. 1, the first side surface 12C1 and the second side surface 12C2 extend in the X-axis direction in a planar view. The third side surface 12C3 and the fourth side surface 12C4 extend in the Y-axis direction in a planar view. As shown in FIG. 2, the insulating layer 14 may be located on the first surface 12A of the semiconductor layer 12.

[0013] The semiconductor device 10 includes a gate wiring 16 located on an insulating layer 14 and a source wiring 18 located on the insulating layer 14. The gate wiring 16 and the source wiring 18 are spaced apart from each other. The gate wiring 16 and the source wiring 18 may include at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a copper alloy, and an aluminum alloy.

[0014] (Gate and source wiring placement) In this embodiment, the gate wiring 16 includes a gate finger portion 16Y (also referred to as a first gate finger portion 16Y) extending in the Y-axis direction. The gate finger portion 16Y may be located near the center between the third side surface 12C3 and the fourth side surface 12C4 of the semiconductor layer 12 in a plan view. In this disclosure, "near the center" between two components includes a range that is offset from the center position between the two components by no more than 10 μm with respect to each of the two components. For example, "near the center between the third side surface 12C3 and the fourth side surface 12C4 of the semiconductor layer 12" may include a range that is offset from the center position between the third side surface 12C3 and the fourth side surface 12C4 of the semiconductor layer 12 by no more than 10 μm with respect to each of the third side surface 12C3 and the fourth side surface 12C4.

[0015] The gate wiring 16 may include a gate pad portion 16P connected to the gate finger portion 16Y. In the example of FIG. 1, the gate pad portion 16P is located near the center of the second side surface 12C2 of the semiconductor layer 12 in a plan view. The gate pad portion 16P can be used to connect the gate wiring 16 to an external connection terminal (not shown). The gate finger portion 16Y extends from the gate pad portion 16P toward the first side surface 12C1.

[0016] Optionally, the gate wiring 16 may include one or more gate finger portions 16X extending in the X-axis direction. In the example of Fig. 1, two gate finger portions 16X1 and 16X2 (also referred to as the second gate finger portion 16X1 and the third gate finger portion 16X2) extending in the X-axis direction are connected to the gate pad portion 16P.

[0017] In this disclosure, the X-axis direction may be referred to as the first direction, and the Y-axis direction may be referred to as the second direction. The second direction intersects with the first direction in a planar view. The second direction may be perpendicular to the first direction in a planar view.

[0018] The source wiring 18 includes a first region 18A and a second region 18B that are separated from each other in the X-axis direction by the first gate finger portion 16Y. In the example of Fig. 1, the first region 18A is located between the third side surface 12C3 and the first gate finger portion 16Y in a planar view. The second region 18B is located between the fourth side surface 12C4 and the first gate finger portion 16Y in a planar view.

[0019] The source wiring 18 may include a connection portion 18C that connects the first region 18A and the second region 18B. The connection portion 18C may be located between the first gate finger portion 16Y and the first side surface 12C1 in a plan view.

[0020] In the example of FIG. 1 , the source wiring 18 may include a first source finger portion 18D and a connection portion 18E connecting the first source finger portion 18D to the first region 18A. The first source finger portion 18D may be located between the second gate finger portion 16X1 and the second side surface 12C2 in a plan view. The connection portion 18E may be located between the second gate finger portion 16X1 and the third side surface 12C3 in a plan view. The source wiring 18 may also include a second source finger portion 18F and a connection portion 18G connecting the second source finger portion 18F to the second region 18B. The second source finger portion 18F may be located between the third gate finger portion 16X2 and the second side surface 12C2 in a plan view. The connection portion 18G may be located between the third gate finger portion 16X2 and the fourth side surface 12C4 in a plan view.

[0021] (Gate trench placement) 1 to 6, the semiconductor layer 12 includes a plurality of gate trenches 20 that extend in the X-axis direction and are spaced apart from one another in the Y-axis direction. Each gate trench 20 is arranged so as to overlap both the gate wiring 16 and the source wiring 18 in plan view. In the example of FIG. 1, the first gate finger portion 16Y intersects with the plurality of gate trenches 20 in plan view.

[0022] Each of the multiple gate trenches 20 includes a first end 20A and a second end 20B. In the example of FIG. 1 , the first end 20A is located relatively close to the third side surface 12C3. The first end 20A overlaps the first region 18A in a plan view. The second end 20B is located relatively close to the fourth side surface 12C4. The second end 20B overlaps the second region 18B in a plan view. Each of the multiple gate trenches 20 may intersect with the first gate finger portion 16Y in a plan view near the center between the first end 20A and the second end 20B.

[0023] The semiconductor layer 12 includes a plurality of connection trenches 22 that connect the plurality of gate trenches 20. Each of the plurality of connection trenches 22 may extend in the Y-axis direction between two gate trenches 20 adjacent to each other in the Y-axis direction.

[0024] The plurality of connection trenches 22 includes a plurality of first intermediate connection trenches 22A overlapping with the first region 18A in a plan view and a plurality of second intermediate connection trenches 22B overlapping with the second region 18B in a plan view. The plurality of first intermediate connection trenches 22A and the plurality of second intermediate connection trenches 22B are not connected to the first end 20A and the second end 20B of the gate trench 20, but are connected to an intermediate portion of the gate trench 20.

[0025] The multiple first intermediate connection trenches 22A and the multiple second intermediate connection trenches 22B are located relatively close to the first gate finger portion 16Y. More specifically, the multiple first intermediate connection trenches 22A may be located closer to the first gate finger portion 16Y in the X-axis direction between the first end portion 20A and the first gate finger portion 16Y in a plan view. The multiple second intermediate connection trenches 22B may be located closer to the first gate finger portion 16Y in the X-axis direction between the second end portion 20B and the first gate finger portion 16Y in a plan view.

[0026] The plurality of connection trenches 22 may further include a plurality of first end connection trenches 22C and a plurality of second end connection trenches 22D. The plurality of first end connection trenches 22C can connect the first ends 20A of the plurality of gate trenches 20. The plurality of second end connection trenches 22D can connect the second ends 20B of the plurality of gate trenches 20.

[0027] Optionally, the semiconductor layer 12 may include a plurality of gate trenches 24 extending in the Y-axis direction and spaced apart from one another in the X-axis direction. Each gate trench 24 is arranged so as to overlap both the gate wiring 16 and the source wiring 18 in a plan view. In the example of FIG. 1 , each gate trench 24 may intersect with the second gate finger portion 16X1 or the third gate finger portion 16X2 in a plan view.

[0028] Each gate trench 24 has a first end 24A and a second end 24B. The first end 24A of each gate trench 24 overlaps with the first source finger portion 18D or the second source finger portion 18F in a plan view. The second end 24B of each gate trench 24 overlaps with the first region 18A or the second region 18B.

[0029] The semiconductor layer 12 may include a plurality of connection trenches 26 that connect between the plurality of gate trenches 24. The plurality of connection trenches 26 may connect between the first ends 24A or the second ends 24B of the plurality of gate trenches 24, respectively.

[0030] It should be noted that for the plurality of gate trenches 24, an intermediate connection trench such as the first intermediate connection trench 22A or the second intermediate connection trench 22B connected to the intermediate portions of the plurality of gate trenches 20 does not need to be provided.

[0031] (active area) Next, we will explain the cross-sectional structure of the active area that contributes to the operation of the semiconductor device 10 as a MISFET. Figure 2 shows a cross section of the gate trench 20 located below the first region 18A of the source wiring 18 and its surrounding components.

[0032] 2 , the semiconductor layer 12 has a first surface 12A and a second surface 12B opposite the first surface 12A. The semiconductor layer 12 may include an n-type drain region 28, an n-type drift region 30 located on the drain region 28, a p-type body region 32 located on the drift region 30, and an n-type source region 34 located on the body region 32. The drain region 28 may include at least a portion of the second surface 12B of the semiconductor layer 12. The source region 34 may include at least a portion of the first surface 12A of the semiconductor layer 12.

[0033] The drain region 28 is a region containing n-type impurities. The n-type impurity concentration of the drain region 28 is 1×10 18 cm -3 More than 1×10 21 cm -3 The drain region 28 may have a thickness of 10 μm or more and 450 μm or less.

[0034] The drift region 30 is a region containing n-type impurities at a concentration lower than that of the drain region 28. The n-type impurity concentration of the drift region 30 is 1×10 15 cm -3 More than 1×10 18 cm -3 The drift region 30 may have a thickness of 1 μm or more and 25 μm or less.

[0035] The body region 32 is a region containing p-type impurities. The p-type impurity concentration of the body region 32 is 1×10 15 cm -3 More than 1×10 18 cm -3 The body region 32 may have a thickness of not less than 0.5 μm and not more than 1.5 μm.

[0036] The source region 34 is a region containing n-type impurities at a higher concentration than the drift region 30. The n-type impurity concentration of the source region 34 is 1×10 19 cm -3 More than 1×10 21 cm -3 The source region 34 may have a thickness of 0.1 μm or more and 1 μm or less.

[0037] In one example, the drift region 30 may be formed from a Si substrate, and the drift region 30, the body region 32, and the source region 34 may be formed from a Si epitaxial layer.

[0038] In this disclosure, n-type may be referred to as the first conductivity type, and p-type may be referred to as the second conductivity type. The n-type impurities may include, for example, phosphorus (P), arsenic (As), and / or antimony (Sb). The p-type impurities may include, for example, boron (B), aluminum (Al), gallium (Ga), and / or indium (In).

[0039] The semiconductor device 10 may include a drain electrode 36 in contact with the second surface 12B of the semiconductor layer 12. The drain electrode 36 is electrically connected to the drain region 28. The drain electrode 36 may include at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), Al, a Cu alloy, and an Al alloy.

[0040] As mentioned above, the semiconductor device 10 includes multiple gate trenches 20. Although the following description generally focuses on one gate trench 20, such description may be applied to other gate trenches 20 as well.

[0041] The gate trench 20 has sidewalls 38 that extend from the first surface 12A into the semiconductor layer 12. The insulating layer 14 is located on the first surface 12A of the semiconductor layer 12 and covers the sidewalls 38 of the gate trench 20.

[0042] The gate trench 20 may extend through the source region 34 and the body region 32 to the drift region 30. In one example, the gate trench 20 may have a depth of not less than 1 μm and not more than 15 μm.

[0043] The semiconductor device 10 includes a first gate electrode 40A and a field plate electrode 42 located in multiple gate trenches 20. The field plate electrode 42 is separated from the first gate electrode 40A by an insulating layer 14. Within the gate trench 20, the first gate electrode 40A faces the field plate electrode 42 in a depth direction (the Z-axis direction in the illustrated example) that intersects with the first surface 12A of the semiconductor layer 12, with the insulating layer 14 interposed therebetween. The first gate electrode 40A is located between the field plate electrode 42 and the first surface 12A in the depth direction.

[0044] The first gate electrode 40A may be disposed so as to face at least the body region 32 via the insulating layer 14 in the width direction (Y-axis direction) of the gate trench 20. Here, the width direction of the gate trench 20 is a direction perpendicular to the longitudinal direction of the gate trench 20. For example, the longitudinal direction of the gate trench 20 shown in FIGS. 1 and 2 is the X-axis direction, and the width direction is the Y-axis direction.

[0045] The field plate electrode 42 may be disposed to face the drift region 30 across the insulating layer 14 in the width direction of the gate trench 20. Within one gate trench 20, the width dimension of the field plate electrode 42 may be smaller than the width dimension of the first gate electrode 40A. This allows the thickness of the insulating layer 14 between the field plate electrode 42 and the drift region 30 to be greater than the thickness of the insulating layer 14 between the first gate electrode 40A and the body region 32.

[0046] The semiconductor device 10 may include a plurality of mesa contact plugs 44 that penetrate the insulating layer 14 and connect the source wiring 18 to the semiconductor layer 12. Each of the plurality of mesa contact plugs 44 is arranged so as to overlap the source wiring 18 in a plan view. The mesa contact plugs 44 are not provided in a region that overlaps with the gate wiring 16 in a plan view.

[0047] Each of the multiple mesa contact plugs 44 is located between two of the multiple gate trenches 20 in a plan view. A portion of the semiconductor layer 12 defined between the two gate trenches 20 can be referred to as a mesa portion 46. Each mesa contact plug 44 is in contact with the mesa portion 46 of the semiconductor layer 12. As shown in FIG. 1 , the mesa contact plug 44 located between the two gate trenches 20 extends parallel to the two gate trenches 20, but may have a smaller dimension than the two gate trenches 20 in the extending direction (the longitudinal direction of the gate trenches 20).

[0048] 2, the semiconductor layer 12 may include p-type contact regions 48 in contact with each mesa contact plug 44. The contact regions 48 are regions containing p-type impurities at a higher concentration than the body region 32. In one example, the p-type impurity concentration of the contact regions 48 is 1×10 19 cm -3 More than 1×10 21 cm -3 It may be the following:

[0049] 3, the semiconductor device 10 also includes a second gate electrode 40B spaced apart in the X-axis direction from the first gate electrode 40A. A cross section of the gate trench 20 located below the second region 18B of the source wiring 18 and its surrounding components corresponds to a cross section of FIG. 2 in which the first gate electrode 40A is replaced with the second gate electrode 40B.

[0050] The first gate electrode 40A and the second gate electrode 40B embedded in the gate trench 20 face the body region 32 of the semiconductor layer 12 via the insulating layer 14. When a predetermined voltage (e.g., a voltage equal to or greater than the gate threshold voltage) is applied to the first gate electrode 40A and the second gate electrode 40B, an inversion layer is formed in the body region 32 along the sidewall 38 of the gate trench 20. The inversion layer in the p-type body region 32 functions as a channel between the n-type source region 34 and the n-type drift region 30. This puts the semiconductor device 10 in an on state. On the other hand, when the voltage applied to the first gate electrode 40A and the second gate electrode 40B is less than the gate threshold voltage, the semiconductor device 10 is in an off state in which no inversion layer is formed in the body region 32.

[0051] (First gate electrode and second gate electrode) 3, the first gate electrode 40A and the second gate electrode 40B are spaced apart from each other in the X-axis direction within the gate trenches 20. The first gate electrode 40A extends into the gate trenches 20 through the first intermediate connection trenches 22A. The second gate electrode 40B extends into the gate trenches 20 through the second intermediate connection trenches 22B.

[0052] The first gate electrode 40A includes a gate portion 40A1 extending into each gate trench 20 and a connection portion 40A2 extending into each first intermediate connection trench 22A. The second gate electrode 40B includes a gate portion 40B1 extending into each gate trench 20 and a connection portion 40B2 extending into each second intermediate connection trench 22B.

[0053] The first gate electrode 40A overlaps with the gate finger portion 16Y in a plan view in a first gate trench 50 of the multiple gate trenches 20. The first gate electrode 40A has an end 54 in the first gate trench 50 that overlaps with the gate finger portion 16Y in a plan view.

[0054] The second gate electrode 40B overlaps with the gate finger portion 16Y in a plan view in a second gate trench 52 that is different from the first gate trench 50 and is one of the multiple gate trenches 20. The second gate electrode 40B has an end 56 that overlaps with the gate finger portion 16Y in a plan view in the second gate trench 52.

[0055] On the other hand, the first gate electrode 40A does not overlap the gate finger portion 16Y in the second gate trench 52 in a plan view. The first gate electrode 40A has an end portion 58 that does not overlap the gate finger portion 16Y in a plan view in the second gate trench 52 and overlaps with the first region 18A. The end portion 58 is a part of the gate portion 40A1. In the example of FIG. 3, the end portion 58 protrudes toward the gate finger portion 16Y beyond the connection portion 40A2.

[0056] Similarly, the second gate electrode 40B does not overlap the gate finger portion 16Y in the first gate trench 50 in plan view. The second gate electrode 40B has an end portion 60 that does not overlap the gate finger portion 16Y in the first gate trench 50 in plan view and overlaps with the second region 18B. The end portion 60 is a part of the gate portion 40B1. In the example of FIG. 3, the end portion 60 protrudes toward the gate finger portion 16Y beyond the connection portion 40B2.

[0057] Thus, the first gate electrode 40A has an end 54 in the first gate trench 50 and an end 58 in the second gate trench 52, with the ends 54 and 58 being at different positions in the X-axis direction. The second gate electrode 40B has an end 56 in the second gate trench 52 and an end 60 in the first gate trench 50, with the ends 56 and 60 being at different positions in the X-axis direction.

[0058] The multiple gate trenches 20 may include multiple first gate trenches 50 and multiple second gate trenches 52. In this embodiment, the first gate trenches 50 and the second gate trenches 52 may be arranged alternately in the Y-axis direction.

[0059] 3 to 6, the semiconductor device 10 further includes a plurality of source contact plugs 62 that penetrate the insulating layer 14 and connect the source wiring 18 to the field plate electrode 42. The plurality of source contact plugs 62 include a first source contact plug 62A (see FIG. 6, for example) that passes between the first gate electrode 40A and the second gate electrode 40B in the second gate trench 52 and connects the first region 18A to the field plate electrode 42, and a second source contact plug 62B (see FIG. 5, for example) that passes between the first gate electrode 40A and the second gate electrode 40B in the first gate trench 50 and connects the second region 18B to the field plate electrode 42.

[0060] The source contact plugs 62 may further include a third source contact plug 62C connecting the first region 18A to the field plate electrode 42 within the first end 20A and a fourth source contact plug 62D connecting the second region 18B to the field plate electrode 42 within the second end 20B. As shown in FIG. 3 , the third source contact plug 62C may extend in the Y-axis direction through the first ends 20A of the gate trenches 20 and the first-end connection trenches 22C. The fourth source contact plug 62D may extend in the Y-axis direction through the second ends 20B of the gate trenches 20 and the second-end connection trenches 22D.

[0061] In this way, in each gate trench 20, the field plate electrode 42 may be connected to the source wiring 18 via three or more source contact plugs 62. 3, 5, and 6, the semiconductor device 10 further includes a plurality of gate contact plugs 64 that penetrate the insulating layer 14 and connect the gate wiring 16 to the first gate electrode 40A or the second gate electrode 40B. The plurality of gate contact plugs 64 may include a first gate contact plug 64A that connects the gate finger portion 16Y to the first gate electrode 40A in the first gate trench 50 and a second gate contact plug 64B that connects the gate finger portion 16Y to the second gate electrode 40B in the second gate trench 52. The first gate contact plug 64A may be connected to an end 54 of the first gate electrode 40A. The second gate contact plug 64B may be connected to an end 56 of the second gate electrode 40B.

[0062] 5 and 6, the first gate electrode 40A and the second gate electrode 40B are located between the field plate electrode 42 and the source wiring 18 in the multiple gate trenches 20. Since the field plate electrode 42 is located lower than the first gate electrode 40A and the second gate electrode 40B, the source contact plug 62 may have a dimension in the Z-axis direction larger than that of the gate contact plug 64.

[0063] 3 and 5, the first gate trench 50 includes a first non-gate electrode segment S1 extending between the first gate electrode 40A and the second gate electrode 40B. More specifically, the first non-gate electrode segment S1 is located between an end 54 of the first gate electrode 40A and an end 60 of the second gate electrode 40B. At least a portion of the first non-gate electrode segment S1 overlaps the second region 18B in a plan view. The second source contact plug 62B is located in the first non-gate electrode segment S1. The field plate electrode 42 is connected to the second source contact plug 62B in the first non-gate electrode segment S1.

[0064] 3 and 6, the second gate trench 52 includes a second non-gate electrode segment S2 extending between the first gate electrode 40A and the second gate electrode 40B. More specifically, the second non-gate electrode segment S2 is located between an end 58 of the first gate electrode 40A and an end 56 of the second gate electrode 40B. At least a portion of the second non-gate electrode segment S2 overlaps the first region 18A in a plan view. The first source contact plug 62A is located in the second non-gate electrode segment S2. The field plate electrode 42 is connected to the first source contact plug 62A in the second non-gate electrode segment S2.

[0065] 3, the first non-gate electrode segment S1 may overlap both the gate finger portion 16Y and the second region 18B in plan view, and the second non-gate electrode segment S2 may overlap both the gate finger portion 16Y and the first region 18A in plan view.

[0066] (Function of Semiconductor Device) The operation of the semiconductor device 10 will now be described. The semiconductor device 10 includes a semiconductor layer 12 including a plurality of gate trenches 20 extending in a first direction and spaced apart from one another in a second direction intersecting the first direction in a plan view, and a plurality of connection trenches 22 connecting the plurality of gate trenches 20. The source wiring 18 includes a first region 18A and a second region 18B spaced apart from one another in the first direction by a gate finger portion 16Y. The plurality of connection trenches 22 include a plurality of first intermediate connection trenches 22A overlapping the first region 18A in a plan view, and a plurality of second intermediate connection trenches 22B overlapping the second region 18B in a plan view.

[0067] The first gate electrode 40A extends into the plurality of gate trenches 20 through the plurality of first intermediate connection trenches 22A, and overlaps with the gate finger portion 16Y in plan view within a first gate trench 50 of the plurality of gate trenches 20. The second gate electrode 40B extends into the plurality of gate trenches 20 through the plurality of second intermediate connection trenches 22B, and overlaps with the gate finger portion 16Y in plan view within a second gate trench 52 of the plurality of gate trenches 20, which is different from the first gate trench 50.

[0068] In this way, since the first gate electrode 40A extends into the plurality of gate trenches 20 through the plurality of first intermediate connection trenches 22A, the first gate electrode 40A can have a common potential across the plurality of gate trenches 20. Furthermore, since the second gate electrode 40B extends into the plurality of gate trenches 20 through the plurality of second intermediate connection trenches 22B, the second gate electrode 40B can have a common potential across the plurality of gate trenches 20.

[0069] Furthermore, the first gate electrode 40A overlaps with the gate finger portion 16Y in a planar view in a first gate trench 50 of the multiple gate trenches 20, and the second gate electrode 40B overlaps with the gate finger portion 16Y in a planar view in a second gate trench 52 of the multiple gate trenches 20 that is different from the first gate trench 50. Therefore, the first gate electrode 40A and the second gate electrode 40B can share one gate finger portion 16Y.

[0070] This allows active areas to be provided on both sides of one gate finger portion 16Y, thereby increasing the proportion of the active area in the semiconductor device 10. Increasing the proportion of the active area in the semiconductor device 10 may enable, for example, a reduction in the on-resistance of the semiconductor device 10.

[0071] The semiconductor device 10 according to this embodiment has the following advantages. (1) The semiconductor device 10 includes a semiconductor layer 12 including a plurality of gate trenches 20 extending in a first direction and spaced apart from one another in a second direction intersecting the first direction in a plan view, and a plurality of connection trenches 22 connecting the plurality of gate trenches 20. The source wiring 18 includes a first region 18A and a second region 18B spaced apart from one another in the first direction by a gate finger portion 16Y. The plurality of connection trenches 22 include a plurality of first intermediate connection trenches 22A overlapping the first region 18A in a plan view and a plurality of second intermediate connection trenches 22B overlapping the second region 18B in a plan view. The first gate electrode 40A extends into the plurality of gate trenches 20 through the plurality of first intermediate connection trenches 22A and overlaps with the gate finger portion 16Y in a first gate trench 50 of the plurality of gate trenches 20 in a plan view. In addition, the second gate electrode 40B extends into the multiple gate trenches 20 through the multiple second intermediate connection trenches 22B, and overlaps with the gate finger portion 16Y in a planar view within a second gate trench 52, which is different from the first gate trench 50, among the multiple gate trenches 20.

[0072] According to this configuration, the first gate electrode 40A and the second gate electrode 40B can share one gate finger portion 16Y and have a common potential across the multiple gate trenches 20. This allows active areas to be provided on both sides of one gate finger portion 16Y in the semiconductor device 10, thereby increasing the proportion of the active area in the semiconductor device 10.

[0073] (2) The semiconductor device 10 further includes a plurality of source contact plugs 62 that penetrate the insulating layer 14 and connect the source wiring 18 to the field plate electrode 42. The plurality of source contact plugs 62 include a first source contact plug 62A that passes between the first gate electrode 40A and the second gate electrode 40B in the second gate trench 52 and connects the first region 18A to the field plate electrode 42, and a second source contact plug 62B that passes between the first gate electrode 40A and the second gate electrode 40B in the first gate trench 50 and connects the second region 18B to the field plate electrode 42.

[0074] According to this configuration, the source wiring 18 can be connected to the field plate electrode 42 on both sides of the gate finger portion 16Y, so that the influence of the resistance component of the field plate electrode 42 on the operation of the semiconductor device 10 can be reduced.

[0075] (3) The first gate trench 50 includes a first non-gate electrode segment S1 extending between the first gate electrode 40A and the second gate electrode 40B. At least a portion of the first non-gate electrode segment S1 overlaps the second region 18B in a plan view. The second gate trench 52 includes a second non-gate electrode segment S2 extending between the first gate electrode 40A and the second gate electrode 40B. At least a portion of the second non-gate electrode segment S2 overlaps the first region 18A in a plan view.

[0076] According to this configuration, it is possible to provide sections in both the first region 18A and the second region 18B where no gate electrode is present, thereby enabling connection of the field plate electrode 42 to both the first region 18A and the second region 18B.

[0077] (4) The first non-gate electrode section S1 may overlap both the gate finger portion 16Y and the second region 18B in plan view. The second non-gate electrode section S2 may overlap both the gate finger portion 16Y and the first region 18A in plan view.

[0078] According to this configuration, the first non-gate electrode segment S1 and the second non-gate electrode segment S2 can be arranged close to the gate finger portion 16Y, so that the field plate electrode 42 can be connected to the source wiring 18 at a position relatively close to the gate finger portion 16Y.

[0079] (5) The field plate electrode 42 is connected to the second source contact plug 62B in the first non-gate electrode section S1, and is connected to the first source contact plug 62A in the second non-gate electrode section S2.

[0080] According to this configuration, the source contact plug 62 can be placed in the first non-gate electrode segment S1 and the second non-gate electrode segment S2 and connected to the field plate electrode 42 located below the first gate electrode 40A and the second gate electrode 40B.

[0081] (6) The semiconductor device 10 further includes a plurality of gate contact plugs 64 that penetrate the insulating layer 14 and connect the gate wiring 16 to the first gate electrode 40A or the second gate electrode 40B. The plurality of gate contact plugs 64 include a first gate contact plug 64A that connects the gate finger portion 16Y to the first gate electrode 40A in the first gate trench 50, and a second gate contact plug 64B that connects the gate finger portion 16Y to the second gate electrode 40B in the second gate trench 52.

[0082] According to this configuration, the gate finger portion 16Y can be connected to both the first gate electrode 40A and the second gate electrode 40B. (7) Each of the plurality of gate trenches 20 includes a first end 20A overlapping with the first region 18A in a plan view and a second end 20B overlapping with the second region 18B in a plan view. The plurality of source contact plugs 62 include a third source contact plug 62C that connects the first region 18A to the field plate electrode 42 within the first end 20A, and a fourth source contact plug 62D that connects the second region 18B to the field plate electrode 42 within the second end 20B.

[0083] According to this configuration, the field plate electrode 42 can be connected to the source wiring 18 via three source contact plugs 62 within each gate trench 20, thereby reducing the effect of the resistance component of the field plate electrode 42 on the operation of the semiconductor device 10.

[0084] (8) The multiple connection trenches 22 further include multiple first end connection trenches 22C connecting the first ends 20A of the multiple gate trenches 20 and multiple second end connection trenches 22D connecting the second ends 20B of the multiple gate trenches 20. The third source contact plug 62C extends in the second direction through the first ends 20A of the multiple gate trenches 20 and the multiple first end connection trenches 22C. The fourth source contact plug 62D extends in the second direction through the second ends 20B of the multiple gate trenches 20 and the multiple second end connection trenches 22D.

[0085] According to this configuration, the active area of ​​the semiconductor device 10 can be surrounded by the gate trench 20, the first end connection trench 22C, and the second end connection trench 22D, so that the breakdown voltage of the semiconductor device 10 can be improved.

[0086] (9) Each of the plurality of gate trenches 20 includes a first end 20A that overlaps with the first region 18A in a plan view and a second end 20B that overlaps with the second region 18B in a plan view. Each of the plurality of gate trenches 20 intersects with the gate finger portion 16Y in a plan view near the center between the first end 20A and the second end 20B.

[0087] This configuration allows the first gate electrode 40A and the second gate electrode 40B, which are electrically connected to the gate finger portion 16Y, to be provided with approximately the same area, thereby making it possible to make the resistance of the first gate electrode 40A and the resistance of the second gate electrode 40B approximately the same.

[0088] (10) The first gate trenches 50 and the second gate trenches 52 are arranged alternately in the second direction. According to this configuration, it is possible to minimize an increase in the resistance of the first gate electrode 40A and the second gate electrode 40B caused by sharing one gate finger portion 16Y.

[0089] <First Modification of First Embodiment> Next, an exemplary semiconductor device 100 according to a first modification of the first embodiment will be described with reference to Fig. 7. In Fig. 7, components similar to those of the semiconductor device 10 are denoted by the same reference numerals. Detailed description of components similar to those of the semiconductor device 10 will be omitted.

[0090] The semiconductor device 100 includes a first gate electrode 102A and a second gate electrode 102B. Fig. 7 is an enlarged schematic plan view showing an example of the arrangement of the first gate electrode 102A and the second gate electrode 102B. In Fig. 7, to facilitate understanding of the arrangement of the first gate electrode 102A and the second gate electrode 102B, the insulating layer 14 covering the first gate electrode 102A and the second gate electrode 102B, the gate wiring 16, and the source wiring 18 are shown transparently.

[0091] 7, the first gate electrode 102A and the second gate electrode 102B are spaced apart from each other in the X-axis direction within the gate trenches 20. The first gate electrode 102A extends into the gate trenches 20 through the first intermediate connection trenches 22A. The second gate electrode 102B extends into the gate trenches 20 through the second intermediate connection trenches 22B.

[0092] The first gate electrode 102A includes a gate portion 102A1 extending into each gate trench 20 and a connection portion 102A2 extending into each first intermediate connection trench 22A. The second gate electrode 102B includes a gate portion 102B1 extending into each gate trench 20 and a connection portion 102B2 extending into each second intermediate connection trench 22B.

[0093] The first gate electrode 102A overlaps with the gate finger portion 16Y in a plan view in the first gate trench 50 of the multiple gate trenches 20. The first gate electrode 102A has an end 104 in the first gate trench 50 that overlaps with the gate finger portion 16Y in a plan view.

[0094] The second gate electrode 102B overlaps with the gate finger portion 16Y in a plan view in a second gate trench 52 that is different from the first gate trench 50 and is one of the multiple gate trenches 20. The second gate electrode 102B has an end 106 that overlaps with the gate finger portion 16Y in a plan view in the second gate trench 52.

[0095] On the other hand, the first gate electrode 102A does not overlap the gate finger portion 16Y in the second gate trench 52 in a plan view. The first gate electrode 102A has an end portion 108 that does not overlap the gate finger portion 16Y in a plan view in the second gate trench 52 and overlaps with the first region 18A. The end portion 108 is a part of the gate portion 102A1. In the example of FIG. 7, the end portion 108 does not protrude from the connection portion 102A2 toward the gate finger portion 16Y. The end portion 108 is aligned with the connection portion 102A2 in the Y-axis direction.

[0096] Similarly, the second gate electrode 102B does not overlap the gate finger portion 16Y in the first gate trench 50 in a plan view. The second gate electrode 102B has an end portion 110 that does not overlap the gate finger portion 16Y in a plan view in the first gate trench 50 and overlaps with the second region 18B. The end portion 110 is a part of the gate portion 102B1. In the example of FIG. 7, the end portion 110 does not protrude from the connection portion 102B2 toward the gate finger portion 16Y. The end portion 110 is aligned with the connection portion 102B2 in the Y-axis direction.

[0097] Thus, the first gate electrode 102A has an end 104 in the first gate trench 50 and an end 108 in the second gate trench 52, with the end 104 and the end 108 being at different positions in the X-axis direction. The second gate electrode 102B has an end 106 in the second gate trench 52 and an end 110 in the first gate trench 50, with the end 106 and the end 110 being at different positions in the X-axis direction.

[0098] The first gate trench 50 includes a first non-gate electrode segment S1 extending between the first gate electrode 102A and the second gate electrode 102B. More specifically, the first non-gate electrode segment S1 is located between an end 104 of the first gate electrode 102A and an end 110 of the second gate electrode 102B. At least a portion of the first non-gate electrode segment S1 overlaps the second region 18B in a plan view. The second source contact plug 62B is located in the first non-gate electrode segment S1. The field plate electrode 42 is connected to the second source contact plug 62B in the first non-gate electrode segment S1.

[0099] The second gate trench 52 includes a second non-gate electrode segment S2 extending between the first gate electrode 102A and the second gate electrode 102B. More specifically, the second non-gate electrode segment S2 is located between an end 108 of the first gate electrode 102A and an end 106 of the second gate electrode 102B. At least a portion of the second non-gate electrode segment S2 overlaps the first region 18A in a plan view. The first source contact plug 62A is located in the second non-gate electrode segment S2. The field plate electrode 42 is connected to the first source contact plug 62A in the second non-gate electrode segment S2.

[0100] In the semiconductor device 100, the end 108 does not protrude from the connection portion 102A2 toward the gate finger portion 16Y, so the second non-gate electrode section S2 extending between the first gate electrode 102A and the second gate electrode 102B in the second gate trench 52 can be made relatively wide. This makes it easier to arrange the source contact plug 62. Alternatively, because the end 108 does not protrude from the connection portion 102A2 toward the gate finger portion 16Y, the first intermediate connection trench 22A in which the connection portion 102A2 is arranged can be arranged relatively close to the gate finger portion 16Y. This further increases the active area that contributes to operation as a MISFET.

[0101] Furthermore, because the end 110 does not protrude from the connection portion 102B2 toward the gate finger portion 16Y, the first non-gate electrode section S1 extending between the first gate electrode 102A and the second gate electrode 102B in the first gate trench 50 can be made relatively wide. This makes it easier to arrange the source contact plug 62. Alternatively, because the end 110 does not protrude from the connection portion 102B2 toward the gate finger portion 16Y, the second intermediate connection trench 22B in which the connection portion 102B2 is arranged can be arranged relatively close to the gate finger portion 16Y. This further increases the active area that contributes to operation as a MISFET.

[0102] Furthermore, in the semiconductor device 100, the first gate electrode 102A and the second gate electrode 102B can share one gate finger portion 16Y and can have a common potential across multiple gate trenches 20. This allows active areas to be provided on both sides of one gate finger portion 16Y. The semiconductor device 100 has advantages similar to advantages (1) to (10) of the semiconductor device 10 of the first embodiment.

[0103] <Second Modification of First Embodiment> Next, an exemplary semiconductor device 200 according to a second modification of the first embodiment will be described with reference to Figures 8 to 10. In Figures 8 to 10, components similar to those in the semiconductor device 10 are denoted by the same reference numerals. Detailed descriptions of components similar to those in the semiconductor device 10 will be omitted.

[0104] The semiconductor device 200 includes a first gate electrode 202A and a second gate electrode 202B. Fig. 8 is an enlarged schematic plan view showing an example of the arrangement of the first gate electrode 202A and the second gate electrode 202B. In Fig. 8, in order to facilitate understanding of the arrangement of the first gate electrode 202A and the second gate electrode 202B, the insulating layer 14 covering the first gate electrode 202A and the second gate electrode 202B, the gate wiring 16, and the source wiring 18 are shown transparently.

[0105] 8, the first gate electrode 202A and the second gate electrode 202B are spaced apart from each other in the X-axis direction within the gate trenches 20. The first gate electrode 202A extends into the gate trenches 20 through the first intermediate connection trenches 22A. The second gate electrode 202B extends into the gate trenches 20 through the second intermediate connection trenches 22B.

[0106] The first gate electrode 202A includes a gate portion 202A1 extending into each gate trench 20 and a connection portion 202A2 extending into each first intermediate connection trench 22A. The second gate electrode 202B includes a gate portion 202B1 extending into each gate trench 20 and a connection portion 202B2 extending into each second intermediate connection trench 22B.

[0107] The first gate electrode 202A overlaps with the gate finger portion 16Y in a plan view within the first gate trench 50 of the multiple gate trenches 20. The first gate electrode 202A has an end portion 204 that overlaps with the gate finger portion 16Y in a plan view within the first gate trench 50. The end portion 204 may extend beyond the gate finger portion 16Y toward the second region 18B in a plan view.

[0108] The second gate electrode 202B overlaps with the gate finger portion 16Y in a plan view within a second gate trench 52, which is one of the multiple gate trenches 20 and is different from the first gate trench 50. The second gate electrode 202B has an end portion 206 that overlaps with the gate finger portion 16Y in a plan view within the second gate trench 52. The end portion 206 may extend beyond the gate finger portion 16Y toward the first region 18A in a plan view.

[0109] On the other hand, the first gate electrode 202A does not overlap with the gate finger portion 16Y in the second gate trench 52 in a plan view. The first gate electrode 202A has an end portion 208 that does not overlap with the gate finger portion 16Y in a plan view in the second gate trench 52 and overlaps with the first region 18A. The end portion 208 is a part of the gate portion 202A1. In the example of FIG. 8, the end portion 208 protrudes toward the gate finger portion 16Y beyond the connection portion 202A2, but in another example, the end portion 208 may not protrude from the connection portion 202A2 toward the gate finger portion 16Y.

[0110] Similarly, the second gate electrode 202B does not overlap the gate finger portion 16Y in the first gate trench 50 in a plan view. The second gate electrode 202B has an end portion 210 that does not overlap the gate finger portion 16Y in a plan view in the first gate trench 50 and overlaps with the second region 18B. The end portion 210 is a part of the gate portion 202B1. In the example of FIG. 8, the end portion 210 protrudes toward the gate finger portion 16Y beyond the connection portion 202B2, but in another example, the end portion 210 may not protrude from the connection portion 202B2 toward the gate finger portion 16Y.

[0111] Thus, the first gate electrode 202A has an end 204 in the first gate trench 50 and an end 208 in the second gate trench 52, with the end 204 and the end 208 being at different positions in the X-axis direction. The second gate electrode 202B has an end 206 in the second gate trench 52 and an end 210 in the first gate trench 50, with the end 206 and the end 210 being at different positions in the X-axis direction.

[0112] 8 and 9, the first gate trench 50 includes a first non-gate electrode segment S1 extending between the first gate electrode 202A and the second gate electrode 202B. More specifically, the first non-gate electrode segment S1 is located between an end 204 of the first gate electrode 202A and an end 210 of the second gate electrode 202B. At least a portion of the first non-gate electrode segment S1 overlaps the second region 18B in a plan view. The second source contact plug 62B is located in the first non-gate electrode segment S1. The field plate electrode 42 is connected to the second source contact plug 62B in the first non-gate electrode segment S1.

[0113] 8 and 10 , the second gate trench 52 includes a second non-gate electrode segment S2 extending between the first gate electrode 202A and the second gate electrode 202B. More specifically, the second non-gate electrode segment S2 is located between an end 208 of the first gate electrode 202A and an end 206 of the second gate electrode 202B. At least a portion of the second non-gate electrode segment S2 overlaps the first region 18A in a plan view. The first source contact plug 62A is located in the second non-gate electrode segment S2. The field plate electrode 42 is connected to the first source contact plug 62A in the second non-gate electrode segment S2.

[0114] 8, the first non-gate electrode section S1 overlaps the second region 18B in plan view but does not necessarily overlap with the gate finger portion 16Y. Moreover, the second non-gate electrode section S2 overlaps the first region 18A in plan view but does not necessarily overlap with the gate finger portion 16Y.

[0115] In the semiconductor device 200, an end 204 of the first gate electrode 202A may extend beyond the gate finger portion 16Y toward the second region 18B in a plan view, and an end 206 of the second gate electrode 202B may extend beyond the gate finger portion 16Y toward the first region 18A in a plan view. This makes it possible to easily align the first gate electrode 202A and the second gate electrode 202B with the gate finger portion 16Y.

[0116] Furthermore, in the semiconductor device 200, the first gate electrode 202A and the second gate electrode 202B can share one gate finger portion 16Y and have a common potential across multiple gate trenches 20. This allows active areas to be provided on both sides of one gate finger portion 16Y. The semiconductor device 200 has advantages similar to advantages (1) to (3) and (5) to (10) of the semiconductor device 10 of the first embodiment.

[0117] Second Embodiment Next, an exemplary semiconductor device 300 according to a second embodiment will be described with reference to Fig. 11. In Fig. 11, components similar to those in the semiconductor device 10 are denoted by the same reference numerals. Detailed description of components similar to those in the semiconductor device 10 will be omitted.

[0118] The semiconductor device 300 includes a gate wiring 302 located on the insulating layer 14 and a source wiring 304 located on the insulating layer 14. The gate wiring 302 and the source wiring 304 are spaced apart from each other. In this embodiment, the gate wiring 302 includes a gate pad portion 302P located relatively close to a corner of the semiconductor device 300 (a position where the second side surface 12C2 and the third side surface 12C3 of the semiconductor layer 12 intersect in a plan view). The gate wiring 302 also includes gate finger portions 302Y1 and 302Y2 (also referred to as the first gate finger portion 302Y1 and the second gate finger portion 302Y2) extending in the Y-axis direction, and a gate finger portion 302X (also referred to as the third gate finger portion 302X) extending in the X-axis direction between the gate pad portion 302P and the gate finger portions 302Y1 and 302Y2. The first gate finger portion 302Y1 extends from the third gate finger portion 302X toward the first side surface 12C1, and the second gate finger portion 302Y2 extends from the third gate finger portion 302X toward the second side surface 12C2.

[0119] The source wiring 304 includes a first region 304A and a second region 304B that are separated from each other in the X-axis direction by the first gate finger portion 302Y1. In the example of Fig. 11, the first region 304A is located between the third side surface 12C3 and the first gate finger portion 302Y1 in a plan view. The second region 304B is located between the fourth side surface 12C4 and the first gate finger portion 302Y1 in a plan view.

[0120] The source wiring 304 may include a connection portion 304C that connects the first region 304A and the second region 304B. The connection portion 304C may be located between the first gate finger portion 302Y1 and the first side surface 12C1 in a plan view.

[0121] 11, the source wiring 304 may include a third region 304D and a connection portion 304E connecting the third region 304D to the second region 304B. The third region 304D may be surrounded by the second gate finger portion 302Y2, the third gate finger portion 302X, the gate pad portion 302P, and the second side surface 12C2 in a plan view. The connection portion 304E may be located between the second gate finger portion 302Y2 and the second side surface 12C2 in a plan view.

[0122] 3 can also be applied to the gate trench 20 in the vicinity of the first gate finger portion 302Y1 of this embodiment. That is, the multiple gate trenches 20 intersecting with the first gate finger portion 302Y1 and the associated components may be the same as those in the first embodiment.

[0123] The semiconductor layer 12 of the semiconductor device 300 may include additional gate trenches 306, 308, and 310 in addition to the multiple gate trenches 20. The gate trench 306 may overlap with the third gate finger portion 302X in a plan view. The gate trench 306 may have a smaller dimension in the X-axis direction than the gate trench 20 so as not to overlap with the gate pad portion 302P in a plan view. The gate trench 306 overlaps with the fourth source contact plug 62D in a plan view, but may not overlap with the third source contact plug 62C. The gate trenches 308 and 310 may overlap with the second gate finger portion 302Y2 in a plan view. The gate trenches 308 and 310 may have a smaller dimension in the X-axis direction than the gate trench 20 so as not to overlap with the gate pad portion 302P in a plan view. The gate trenches 308 and 310 overlap the fourth source contact plug 62D in plan view, but do not necessarily overlap the third source contact plug 62C.

[0124] Active areas can be provided on both sides of the gate finger portions 302Y1 and 302Y2 in the semiconductor device 300. The semiconductor device 300 has the same advantages (1) to (10) as the semiconductor device 10 of the first embodiment.

[0125] Third Embodiment Next, an exemplary semiconductor device 400 according to a third embodiment will be described with reference to Fig. 12. In Fig. 12, components similar to those in the semiconductor device 10 are denoted by the same reference numerals. Detailed description of components similar to those in the semiconductor device 10 will be omitted.

[0126] The semiconductor device 400 includes a gate wiring 402 located on the insulating layer 14, and a source wiring 404 located on the insulating layer 14. The gate wiring 402 and the source wiring 404 are spaced apart from each other. In this embodiment, the gate wiring 402 includes a gate pad portion 402P located relatively close to a corner of the semiconductor device 400 (a position where the first side surface 12C1 and the fourth side surface 12C4 of the semiconductor layer 12 intersect in a plan view). The gate wiring 402 also includes gate finger portions 402Y1, 402Y2, 402Y3, 402Y4, and 402Y5 (also referred to as the first gate finger portion 402Y1, the second gate finger portion 402Y2, the third gate finger portion 402Y3, the fourth gate finger portion 402Y4, and the fifth gate finger portion 402Y5) extending in the Y-axis direction, and a gate finger portion 402X (also referred to as the sixth gate finger portion 402X) extending in the X-axis direction. The sixth gate finger portion 402X is connected to the gate pad portion 402P by the fifth gate finger portion 402Y5. The first gate finger portion 402Y1, the second gate finger portion 402Y2, the third gate finger portion 402Y3, the fourth gate finger portion 402Y4, and the fifth gate finger portion 402Y5 are each connected to the sixth gate finger portion 402X.

[0127] The first gate finger portion 402Y1 extends from the sixth gate finger portion 402X toward the first side surface 12C1. The second gate finger portion 402Y2 extends from the sixth gate finger portion 402X toward the second side surface 12C2. The first gate finger portion 402Y1 and the second gate finger portion 402Y2 may be aligned in a straight line.

[0128] The third gate finger portion 402Y3 extends from the sixth gate finger portion 402X toward the first side surface 12C1. The fourth gate finger portion 402Y4 extends from the sixth gate finger portion 402X toward the second side surface 12C2. The third gate finger portion 402Y3 and the fourth gate finger portion 402Y4 may be aligned in a straight line.

[0129] The source line 404 includes a first region 404A, a second region 404B, a third region 404C, a fourth region 404D, a fifth region 404E, and a sixth region 404F. The first region 404A is separated in the X-axis direction from the second region 404B by the first gate finger portion 402Y1, and is separated in the X-axis direction from the third region 404C by the second gate finger portion 402Y2. The first region 404A may be surrounded by the first side surface 12C1, the third side surface 12C3, the second side surface 12C2, the first gate finger portion 402Y1, and the second gate finger portion 402Y2 in a plan view.

[0130] The second region 404B is separated from the first region 404A in the X-axis direction by the first gate finger portion 402Y1, separated from the fourth region 404D in the X-axis direction by the third gate finger portion 402Y3, and separated from the third region 404C in the Y-axis direction by the sixth gate finger portion 402X. The second region 404B may be surrounded by the first side surface 12C1, the first gate finger portion 402Y1, the sixth gate finger portion 402X, and the third gate finger portion 402Y3 in a plan view.

[0131] The third region 404C is separated from the first region 404A in the X-axis direction by the second gate finger portion 402Y2, separated from the fifth region 404E in the X-axis direction by the fourth gate finger portion 402Y4, and separated from the second region 404B in the Y-axis direction by the sixth gate finger portion 402X. The third region 404C may be surrounded by the second side surface 12C2, the second gate finger portion 402Y2, the sixth gate finger portion 402X, and the fourth gate finger portion 402Y4 in a plan view.

[0132] The fourth region 404D is separated from the second region 404B in the X-axis direction by the third gate finger portion 402Y3, separated from the sixth region 404F in the X-axis direction by the fifth gate finger portion 402Y5, and separated from the fifth region 404E in the Y-axis direction by the sixth gate finger portion 402X. The fourth region 404D may be surrounded by the first side surface 12C1, the third gate finger portion 402Y3, the sixth gate finger portion 402X, the fifth gate finger portion 402Y5, and the gate pad portion 402P in a plan view.

[0133] The fifth region 404E is separated from the third region 404C in the X-axis direction by the fourth gate finger portion 402Y4, and is separated from the fourth region 404D and the sixth region 404F in the Y-axis direction by the sixth gate finger portion 402X. The fifth region 404E may be surrounded by the second side surface 12C2, the fourth side surface 12C4, the sixth gate finger portion 402X, and the fourth gate finger portion 402Y4 in a plan view.

[0134] The sixth region 404F is separated from the fourth region 404D in the X-axis direction by the fifth gate finger portion 402Y5, and is separated from the fifth region 404E in the Y-axis direction by the sixth gate finger portion 402X. The sixth region 404F may be surrounded by the fourth side surface 12C4, the sixth gate finger portion 402X, the fifth gate finger portion 402Y5, and the gate pad portion 402P in a plan view.

[0135] The source wiring 404 may include a connection portion 404G that connects the first region 404A and the second region 404B. The connection portion 404G may be located between the first gate finger portion 402Y1 and the first side surface 12C1 in a plan view.

[0136] The source wiring 404 may include a connection portion 404H that connects the first region 404A and the third region 404C. The connection portion 404H may be located between the second gate finger portion 402Y2 and the second side surface 12C2 in a plan view.

[0137] The source wiring 404 may include a connection portion 404I that connects the second region 404B and the fourth region 404D. The connection portion 404I may be located between the third gate finger portion 402Y3 and the first side surface 12C1 in a plan view.

[0138] The source wiring 404 may include a connection portion 404J that connects the third region 404C and the fifth region 404E. The connection portion 404J may be located between the fourth gate finger portion 402Y4 and the second side surface 12C2 in a plan view.

[0139] The source wiring 404 may include a connection portion 404K that connects the fifth region 404E and the sixth region 404F. The connection portion 404K may be located between the sixth gate finger portion 402X and the fourth side surface 12C4 in a plan view.

[0140] (Gate trench placement) 12, the semiconductor layer 12 includes a plurality of gate trenches 406 extending in the X-axis direction and spaced apart from one another in the Y-axis direction. Each gate trench 406 is arranged to overlap both the gate wiring 402 and the source wiring 404 in a plan view. The first gate finger portion 402Y1, the second gate finger portion 402Y2, the third gate finger portion 402Y3, the fourth gate finger portion 402Y4, and the fifth gate finger portion 402Y5 may intersect with any of the plurality of gate trenches 406 in a plan view.

[0141] Each of the plurality of gate trenches 406 includes a first end 406A and a second end 406B. The first end 406A is located relatively close to the third side surface 12C3. The first end 406A overlaps the first region 404A in a plan view. The second end 406B is located relatively close to the fourth side surface 12C4. The second end 406B overlaps the fifth region 404E or the sixth region 404F in a plan view. Each of the plurality of gate trenches 406 may intersect with some of the plurality of gate finger portions 402Y1, 402Y2, 402Y3, 402Y4, and 402Y5 between the first end 406A and the second end 406B in a plan view. Specifically, each of the multiple gate trenches 406 intersects with the first gate finger portion 402Y1, the third gate finger portion 402Y3, and the fifth gate finger portion 402Y5, or intersects with the second gate finger portion 402Y2 and the fourth gate finger portion 402Y4.

[0142] The semiconductor layer 12 includes a plurality of connection trenches 408 that connect the plurality of gate trenches 406. Each of the plurality of connection trenches 408 may extend in the Y-axis direction between two gate trenches 406 that are adjacent in the Y-axis direction.

[0143] The plurality of connection trenches 408 includes a plurality of first intermediate connection trenches 408A overlapping the first region 404A in a plan view and a plurality of second intermediate connection trenches 408B overlapping the second region 404B or the third region 404C in a plan view. The plurality of first intermediate connection trenches 408A and the plurality of second intermediate connection trenches 408B are not connected to the first end 406A or the second end 406B of the gate trench 406, but are connected to an intermediate portion of the gate trench 406.

[0144] The plurality of first intermediate connection trenches 408A and the plurality of second intermediate connection trenches 408B are located relatively close to the first gate finger portion 402Y1 or the second gate finger portion 402Y2. More specifically, the plurality of first intermediate connection trenches 408A may be located closer to the first gate finger portion 402Y1 in the X-axis direction between the first end portion 406A and the first gate finger portion 402Y1, or closer to the second gate finger portion 402Y2 in the X-axis direction between the first end portion 406A and the second gate finger portion 402Y2, in a plan view. The multiple second intermediate connection trenches 408B may be located, in a planar view, closer to the first gate finger portion 402Y1 in the X-axis direction between the first gate finger portion 402Y1 and the third gate finger portion 402Y3, or may be located, in a planar view, closer to the second gate finger portion 402Y2 in the X-axis direction between the second gate finger portion 402Y2 and the fourth gate finger portion 402Y4.

[0145] Furthermore, the plurality of connection trenches 408 includes a plurality of third intermediate connection trenches 408C overlapping with the second region 404B or the third region 404C in a plan view, and a plurality of fourth intermediate connection trenches 408D overlapping with the fourth region 404D or the fifth region 404E in a plan view. The plurality of third intermediate connection trenches 408C and the plurality of fourth intermediate connection trenches 408D are not connected to the first end 406A or the second end 406B of the gate trench 406, but are connected to a middle portion of the gate trench 406.

[0146] The plurality of third intermediate connection trenches 408C and the plurality of fourth intermediate connection trenches 408D are located relatively close to the third gate finger portion 402Y3 or the fourth gate finger portion 402Y4. More specifically, the plurality of third intermediate connection trenches 408C may be located closer to the third gate finger portion 402Y3 in the X-axis direction between the first gate finger portion 402Y1 and the third gate finger portion 402Y3 in a plan view, or may be located closer to the fourth gate finger portion 402Y4 in the X-axis direction between the second gate finger portion 402Y2 and the fourth gate finger portion 402Y4 in a plan view. The multiple fourth intermediate connection trenches 408D may be located, in a planar view, closer to the third gate finger portion 402Y3 in the X-axis direction between the second end portion 406B and the third gate finger portion 402Y3, or closer to the fourth gate finger portion 402Y4 in the X-axis direction between the second end portion 406B and the fourth gate finger portion 402Y4.

[0147] The plurality of connection trenches 408 may include a plurality of fifth intermediate connection trenches 408E overlapping with the second region 404B in a plan view and a plurality of sixth intermediate connection trenches 408F overlapping with the third region 404C in a plan view. The plurality of fifth intermediate connection trenches 408E and the plurality of sixth intermediate connection trenches 408F are not connected to the first end 406A and the second end 406B of the gate trench 406, but are connected to an intermediate portion of the gate trench 406. The fifth intermediate connection trench 408E and the plurality of sixth intermediate connection trenches 408F may be located between the plurality of second intermediate connection trenches 408B and the plurality of third intermediate connection trenches 408C in a plan view.

[0148] Optionally, the plurality of connection trenches 408 may further include a plurality of first end connection trenches 408G and a plurality of second end connection trenches 408H. The plurality of first end connection trenches 408G may connect between the first ends 406A of each of the plurality of gate trenches 406. The plurality of second end connection trenches 408H may connect between the second ends 406B of each of the plurality of gate trenches 406.

[0149] In addition to the multiple gate trenches 406, the semiconductor layer 12 of the semiconductor device 400 may also include additional gate trenches 410, 412, and 414. The gate trenches 410, 412 may overlap with the first gate finger portion 402Y1 and the third gate finger portion 402Y3 in a plan view. The gate trenches 410, 412 may have a smaller dimension in the X-axis direction than the gate trench 406 so as not to overlap with the gate pad portion 402P in a plan view. The gate trench 414 may overlap with a portion of the sixth gate finger portion 402X and the first region 404A in a plan view. The gate trench 414 may have a smaller dimension in the X-axis direction than the gate trench 406.

[0150] The arrangement of the first gate electrode 40A, the second gate electrode 40B, and the field plate electrode 42 in the gate trench 20 near the gate finger portion 16Y according to the first embodiment shown in Figure 3 can also be applied to the gate trench 406 near the first gate finger portion 402Y1, the second gate finger portion 402Y2, the third gate finger portion 402Y3, and the fourth gate finger portion 402Y4 of this embodiment.

[0151] The plurality of gate trenches 406 may include a plurality of first gate trenches 416 and a plurality of second gate trenches 418. The first gate trenches 416 and the second gate trenches 418 may be arranged alternately in the Y-axis direction. As will be further described below, the first gate trenches 416 and the second gate trenches 418 differ from the first gate trenches 50 and the second gate trenches 52 according to the first embodiment in the arrangement of the source contact plugs 420.

[0152] The semiconductor device 400 further includes a plurality of source contact plugs 420 that penetrate the insulating layer 14 and connect the source wiring 404 to the field plate electrode 42. The plurality of source contact plugs 420 include a first source contact plug 420A that passes between the first gate electrode 40A and the second gate electrode 40B in the second gate trench 418 and connects the first region 404A to the field plate electrode 42, and a second source contact plug 420B that passes between the first gate electrode 40A and the second gate electrode 40B in the first gate trench 416 and connects the second region 404B or the third region 404C to the field plate electrode 42.

[0153] The plurality of source contact plugs 420 may include a third source contact plug 420C that connects the first region 404A to the field plate electrode 42 within the first end 406A and a fourth source contact plug 420D that connects the fifth region 404E and the sixth region 404F to the field plate electrode 42 within the second end 406B. The third source contact plug 420C may extend in the Y-axis direction through the first ends 406A of each of the plurality of gate trenches 406 and the plurality of first-end connection trenches 408G. The fourth source contact plug 420D may extend in the Y-axis direction through the second ends 406B of each of the plurality of gate trenches 406 and the plurality of second-end connection trenches 408H.

[0154] The plurality of source contact plugs 420 may further include a fifth source contact plug 420E connecting the second region 404B to the field plate electrode 42 and a sixth source contact plug 420F connecting the third region 404C to the field plate electrode 42. The fifth source contact plug 420E may extend in the Y-axis direction through the plurality of gate trenches 406 and the plurality of fifth intermediate connection trenches 408E. The sixth source contact plug 420F may extend in the Y-axis direction through the plurality of gate trenches 406 and the plurality of sixth intermediate connection trenches 408F.

[0155] The semiconductor device 400 further includes a plurality of gate contact plugs 422 that penetrate the insulating layer 14 and connect the gate wiring 402 to the first gate electrode 40A or the second gate electrode 40B. The plurality of gate contact plugs 422 may include a first gate contact plug 422A that connects the first gate finger portion 402Y1 or the second gate finger portion 402Y2 to the first gate electrode 40A in the first gate trench 416, and a second gate contact plug 422B that connects the first gate finger portion 402Y1 or the second gate finger portion 402Y2 to the second gate electrode 40B in the second gate trench 418.

[0156] Such an arrangement of the source contact plugs 420 and the gate contact plugs 422 allows active areas to be provided on both sides of each of the multiple gate finger portions 402Y1, 402Y2, 402Y3, and 402Y4. The semiconductor device 400 has advantages (1) to (10) similar to those of the semiconductor device 10 of the first embodiment.

[0157] <Fourth embodiment> Next, an exemplary semiconductor device 500 according to a fourth embodiment will be described with reference to Figures 13 to 15. In Figures 13 to 15, components similar to those in the semiconductor device 10 are denoted by the same reference numerals. Detailed description of components similar to those in the semiconductor device 10 will be omitted.

[0158] FIG. 13 is a schematic plan view of a semiconductor device 500. FIG. 14 is an enlarged plan view showing an example of the arrangement of the first gate electrode 40A and the second gate electrode 40B in the semiconductor device 500. In FIG. 14, to facilitate understanding of the arrangement of the first gate electrode 40A and the second gate electrode 40B, the insulating layer 14 covering the first gate electrode 40A and the second gate electrode 40B, the gate wiring 16, and the source wiring 18 are shown transparently. FIG. 15 is a schematic cross-sectional view of the semiconductor device 500 taken along line F15-F15 in FIG. 14.

[0159] The semiconductor device 500 differs from the semiconductor device 10 according to the first embodiment in the arrangement of the first gate trenches 50 and the second gate trenches 52. In the semiconductor device 500, the first gate trenches 50 and the second gate trenches 52 are arranged alternately in pairs in the second direction. That is, as shown in FIGS. 13 to 15, two adjacent first gate trenches 50 and two adjacent second gate trenches 52 are arranged alternately in the second direction. As a result, as shown in FIG. 15, for example, two second source contact plugs 62B located in two adjacent first gate trenches 50 are arranged side by side in the Y-axis direction.

[0160] In the semiconductor device 500, the first gate electrode 40A and the second gate electrode 40B can share one gate finger portion 16Y and can have a common potential across multiple gate trenches 20. This allows active areas to be provided on both sides of one gate finger portion 16Y, thereby increasing the proportion of the active area in the semiconductor device 500. The semiconductor device 500 has advantages similar to advantages (1) to (9) of the semiconductor device 10 of the first embodiment.

[0161] <Other change examples> The above embodiment can be modified as follows. 5 and 6, the field plate electrode 42 is connected to the source wiring 18 by a source contact plug 62 that has a dimension in the Z-axis direction larger than that of the gate contact plug 64. However, the dimension in the Z-axis direction of the source contact plug 62 may be equal to the dimension in the Z-axis direction of the gate contact plug 64.

[0162] In this case, as in the semiconductor device 600 shown in Figures 16 and 17, the field plate electrode 42 may include a first pull-up portion 602 that passes between the first gate electrode 40A and the second gate electrode 40B within the first gate trench 50, and a second pull-up portion 604 that passes between the first gate electrode 40A and the second gate electrode 40B within the second gate trench 52.

[0163] The field plate electrode 42 may also include a third raised portion 606 located within the first end 20A and a fourth raised portion 608 located within the second end 20B. The first pull-up portion 602, the second pull-up portion 604, the third pull-up portion 606, and the fourth pull-up portion 608 protrude upward from the base portion 610 of the field plate electrode 42, which is located below the first gate electrode 40A and the second gate electrode 40B.

[0164] The first pull-up portion 602 can be connected to the second region 18B by a second source contact plug 62B. The second pull-up portion 604 can be connected to the first region 18A by a first source contact plug 62A. The third pull-up portion 606 can be connected to the first region 18A by a third source contact plug 62C. The fourth pull-up portion 608 can be connected to the second region 18B by a fourth source contact plug 62D.

[0165] The plurality of connection trenches 22 connecting the plurality of gate trenches 20 may not include the first end connection trench 22C and / or the second end connection trench 22D. 1, the gate wiring 16 does not have to include the second gate finger portion 16X1 and the third gate finger portion 16X2. In that case, the semiconductor layer 12 does not have to include the gate trench 24.

[0166] One or more of the various examples described herein may be combined to the extent that they are not technically inconsistent. In this specification, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."

[0167] The term "on" as used in this disclosure can mean both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer can be placed directly on the second layer in contact with the second layer, while in other embodiments, the first layer can be placed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0168] Directional terms such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "front," "rear," "longitudinal," "lateral," "left," "right," "front," and "rear" used in this disclosure depend on the particular orientation of the device being described and illustrated. Various alternative orientations are contemplated in this disclosure, and therefore these directional terms should not be construed narrowly.

[0169] For example, the Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0170] Terms such as "first," "second," and "third" in this disclosure are used merely to distinguish between objects and do not rank the objects. <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0171] (Appendix 1) a semiconductor layer (12) including a plurality of gate trenches (20) extending in a first direction and spaced apart from one another in a second direction intersecting the first direction in a plan view, and a plurality of connection trenches (22) connecting the plurality of gate trenches (20); an insulating layer (14) located on the semiconductor layer (12); a first gate electrode (40A) and a second gate electrode (40B) spaced apart from each other in the first direction within the plurality of gate trenches (20); a field plate electrode (42) located within the plurality of gate trenches (20); a gate wiring (16) located on the insulating layer (14) and electrically connected to the first gate electrode (40A) and the second gate electrode (40B); a source wiring (18) located on the insulating layer (14) and electrically connected to the field plate electrode (42); Equipped with the gate wiring (16) includes a gate finger portion (16Y) extending in the second direction, the gate finger portion (16Y) intersecting the plurality of gate trenches (20) in a plan view; the source wiring (18) includes a first region (18A) and a second region (18B) spaced apart from each other in the first direction by the gate finger portion (16Y), and the plurality of connection trenches (22) include a plurality of first intermediate connection trenches (22A) overlapping the first region (18A) in a plan view and a plurality of second intermediate connection trenches (22B) overlapping the second region (18B) in a plan view; the first gate electrode (40A) extends into the plurality of gate trenches (20) through the plurality of first intermediate connection trenches (22A), and overlaps with the gate finger portion (16Y) in a plan view within a first gate trench (50) of the plurality of gate trenches (20); the second gate electrode (40B) extends into the plurality of gate trenches (20) through the plurality of second intermediate connection trenches (22B), and overlaps with the gate finger portion (16Y) in a planar view in a second gate trench (52) of the plurality of gate trenches (20) that is different from the first gate trench (50).

[0172] (Appendix 2) a plurality of source contact plugs (62) that penetrate the insulating layer (14) and connect the source wiring (18) to the field plate electrode (42); The plurality of source contact plugs (62) a first source contact plug (62A) that passes between the first gate electrode (40A) and the second gate electrode (40B) in the second gate trench (52) and connects the first region (18A) to the field plate electrode (42); a second source contact plug (62B) that passes between the first gate electrode (40A) and the second gate electrode (40B) in the first gate trench (50) and connects the second region (18B) to the field plate electrode (42); 2. The semiconductor device of claim 1, comprising:

[0173] (Appendix 3) the first gate trench (50) includes a first non-gate electrode section (S1) extending between the first gate electrode (40A) and the second gate electrode (40B), and at least a portion of the first non-gate electrode section (S1) overlaps with the second region (18B) in a plan view; The semiconductor device described in Appendix 2, wherein the second gate trench (52) includes a second non-gate electrode section (S2) extending between the first gate electrode (40A) and the second gate electrode (40B), and at least a portion of the second non-gate electrode section (S2) overlaps with the first region (18A) in a planar view.

[0174] (Appendix 4) The semiconductor device described in Appendix 3, wherein the first non-gate electrode section (S1) overlaps both the gate finger portion (16Y) and the second region (18B) in a planar view, and the second non-gate electrode section (S2) overlaps both the gate finger portion (16Y) and the first region (18A) in a planar view.

[0175] (Appendix 5) 5. The semiconductor device according to claim 3, wherein the field plate electrode (42) is connected to the second source contact plug (62B) in the first non-gate electrode segment (S1) and is connected to the first source contact plug (62A) in the second non-gate electrode segment (S2).

[0176] (Appendix 6) further comprising a plurality of gate contact plugs (64) penetrating the insulating layer (14) and connecting the gate wiring (16) to the first gate electrode (40A) or the second gate electrode (40B); The plurality of gate contact plugs (64) a first gate contact plug (64A) connecting the gate finger portion (16Y) to the first gate electrode (40A) in the first gate trench (50); a second gate contact plug (64B) connecting the gate finger portion (16Y) to the second gate electrode (40B) in the second gate trench (52); 6. The semiconductor device according to any one of appendices 1 to 5, comprising:

[0177] (Appendix 7) each of the plurality of gate trenches (20) includes a first end (20A) overlapping the first region (18A) in a plan view and a second end (20B) overlapping the second region (18B) in a plan view; The plurality of source contact plugs (62) a third source contact plug (62C) connecting the first region (18A) to the field plate electrode (42) within the first end (20A); a fourth source contact plug (62D) connecting the second region (18B) to the field plate electrode (42) within the second end (20B); 6. The semiconductor device according to any one of appendices 2 to 5, comprising:

[0178] (Appendix 8) The plurality of connection trenches (22) are a plurality of first end connection trenches (22C) connecting the first ends (20A) of the plurality of gate trenches (20); a plurality of second end connection trenches (22D) connecting the second ends (20B) of the plurality of gate trenches (20); further comprising the third source contact plug (62C) extends in the second direction through the first ends (20A) of the gate trenches (20) and the first end connection trenches (22C); The semiconductor device described in Appendix 7, wherein the fourth source contact plug (62D) extends in the second direction through the second ends (20B) of each of the plurality of gate trenches (20) and the plurality of second end connection trenches (22D).

[0179] (Appendix 9) each of the plurality of gate trenches (20) includes a first end (20A) overlapping the first region (18A) in a plan view and a second end (20B) overlapping the second region (18B) in a plan view; The semiconductor device according to any one of appendixes 1 to 8, wherein each of the plurality of gate trenches (20) intersects with the gate finger portion (16Y) in a planar view near the center between the first end (20A) and the second end (20B).

[0180] (Appendix 10) 10. The semiconductor device according to any one of claims 1 to 9, wherein the first gate trenches (50) and the second gate trenches (52) are arranged alternately in the second direction.

[0181] (Appendix 11) The semiconductor device according to any one of appendices 1 to 9, wherein the first gate trenches (50) and the second gate trenches (52) are arranged two by two alternately in the second direction.

[0182] (Appendix 12) The field plate electrode (42) is a first lift-up portion (602) passing between the first gate electrode (40A) and the second gate electrode (40B) in the first gate trench (50); a second raised portion (604) passing between the first gate electrode (40A) and the second gate electrode (40B) in the second gate trench (52); 6. The semiconductor device according to any one of appendices 2 to 5, comprising:

[0183] (Appendix 13) 13. The semiconductor device of claim 12, wherein the first pull-up portion (602) is connected to the second region (18B) by the second source contact plug (62B), and the second pull-up portion (604) is connected to the first region (18A) by the first source contact plug (62A).

[0184] (Appendix 14) The semiconductor device according to any one of appendixes 1 to 13, wherein the first gate electrode (40A) and the second gate electrode (40B) are located within the plurality of gate trenches (20) between the field plate electrode (42) and the source wiring (18).

[0185] (Appendix 15) The semiconductor device according to any one of appendixes 2 to 5, wherein the field plate electrode (42) is connected to the source wiring (18) within each gate trench (20) via three or more source contact plugs (62) among the plurality of source contact plugs (62).

[0186] Various changes in form and detail may be made to the above-described examples without departing from the scope of the claims and their equivalents. The above-described examples are illustrative and not limiting. The description of a feature in each example should be considered applicable to similar features or aspects in other examples. Suitable results may be achieved if the sequential events are performed in a different order and / or if components within the described systems, architectures, devices, or circuits are combined in a different manner and / or replaced or supplemented by other components or their equivalents. The scope of the present disclosure is defined not by the detailed description, but by the claims and their equivalents. All variations within the scope of the claims and their equivalents are included herein. [Explanation of symbols]

[0187] 10, 100, 200, 300, 400, 500, 600...Semiconductor device 12...Semiconductor layer 12A…Side 1 12B…Second side 12C1…1st side 12C2…Second side 12C3…Third side 12C4…4th side 14...Insulating layer 16,302,402...Gate wiring 16P, 302P, 402P...Gate pad section 16X...Gate finger part 16Y, 302Y1, 402Y1...First gate finger part 16X1, 302Y2, 402Y2...Second gate finger part 16X2, 302X, 402Y3...Third gate finger part 402Y4...Fourth gate finger part 402Y5...5th gate finger part 402X...6th gate finger part 18,304,404...Source wiring 18A, 304A, 404A…1st area 18B, 304B, 404B…Second area 304D,404C…Third area 404D…Fourth area 404E…5th area 404F…6th area 18C, 304C, 304E, 404G, 404H, 404I, 404J, 404K...Connection 18D...First sauce finger 18E…Connection 18F…Second Sauce Finger Section 18G...Connection 20, 24, 306, 308, 310, 406, 410, 412, 414...Gate trench 20A, 24A, 406A…1st end 20B, 24B, 406B…Second end 22,408...Connection trench 22A, 408A...First intermediate connection trench 22B, 408B...Second intermediate connection trench 408C…Third Intermediate Connection Trench 408D...Fourth Intermediate Connection Trench 408E...5th Intermediate Connection Trench 408F...6th Intermediate Connection Trench 22C, 408G...First end connection trench 22D, 408H...Second end connection trench 26...Connection trench 28...Drain region 30...Drift region 32...Body area 34...Source region 36...Drain electrode 38…Side wall 40A, 102A, 202A...first gate electrode 40A1, 102A1, 202A1...Gate section 40A2, 102A2, 202A2...Connection parts 40B, 102B, 202B...Second gate electrodes 40B1, 102B1, 202B1...Gate section 40B2, 102B2, 202B2...Connection parts 42...Field plate electrode 44...Mesa contact plug 46...Mesa section 48...Contact area 50,416...First gate trench 52,418...Second gate trench 54, 56, 58, 60, 104, 106, 108, 110, 204, 206, 208, 210...End 62,420...Source contact plug 62A, 420A...First source contact plug 62B, 420B...Second source contact plug 62C, 420C...Third source contact plug 62D, 420D...Fourth source contact plug 420E...5th source contact plug 420F...6th source contact plug 64,422...Gate contact plug 64A, 422A...First gate contact plug 64B, 422B...Second gate contact plug 602...First lifting section 604...Second lifting section 606...Third lifting section 608...Fourth lifting section 610...Base S1...first non-gate electrode section S2: Second non-gate electrode section

Claims

1. a semiconductor layer including a plurality of gate trenches extending in a first direction and spaced apart from each other in a second direction intersecting the first direction in a plan view, and a plurality of connection trenches connecting the plurality of gate trenches; an insulating layer located on the semiconductor layer; first and second gate electrodes spaced apart from each other in the first direction within the plurality of gate trenches; a field plate electrode located within the plurality of gate trenches; a gate wiring located on the insulating layer and electrically connected to the first gate electrode and the second gate electrode; a source wiring located on the insulating layer and electrically connected to the field plate electrode; Equipped with the gate wiring includes gate finger portions extending in the second direction, the gate finger portions intersecting the plurality of gate trenches in a plan view; the source wiring includes a first region and a second region spaced apart from each other in the first direction by the gate finger portion, and the plurality of connection trenches include a plurality of first intermediate connection trenches overlapping the first region in a plan view and a plurality of second intermediate connection trenches overlapping the second region in a plan view; the first gate electrode extends into the gate trenches through the first intermediate connection trenches, and overlaps with the gate finger portion in a first gate trench among the gate trenches in a plan view; the second gate electrode extends into the plurality of gate trenches through the plurality of second intermediate connection trenches, and overlaps with the gate finger portion in a planar view in a second gate trench different from the first gate trench among the plurality of gate trenches.

2. a plurality of source contact plugs that penetrate the insulating layer and connect the source wiring to the field plate electrode; The plurality of source contact plugs include: a first source contact plug that passes between the first gate electrode and the second gate electrode in the second gate trench and connects the first region to the field plate electrode; a second source contact plug that passes between the first gate electrode and the second gate electrode in the first gate trench and connects the second region to the field plate electrode; The semiconductor device according to claim 1 , comprising:

3. the first gate trench includes a first non-gate electrode section extending between the first gate electrode and the second gate electrode, and at least a portion of the first non-gate electrode section overlaps with the second region in a plan view; 3. The semiconductor device according to claim 2, wherein the second gate trench includes a second non-gate electrode section extending between the first gate electrode and the second gate electrode, and at least a portion of the second non-gate electrode section overlaps with the first region in a planar view.

4. 4. The semiconductor device according to claim 3, wherein the first non-gate electrode section overlaps both the gate finger portion and the second region in a planar view, and the second non-gate electrode section overlaps both the gate finger portion and the first region in a planar view.

5. 5. The semiconductor device according to claim 3, wherein the field plate electrode is connected to the second source contact plug in the first non-gate electrode section, and is connected to the first source contact plug in the second non-gate electrode section.

6. a plurality of gate contact plugs that penetrate the insulating layer and connect the gate wiring to the first gate electrode or the second gate electrode; The plurality of gate contact plugs include: a first gate contact plug connecting the gate finger portion to the first gate electrode within the first gate trench; a second gate contact plug connecting the gate finger portion to the second gate electrode in the second gate trench; The semiconductor device according to any one of claims 1 to 4, comprising:

7. each of the plurality of gate trenches includes a first end portion overlapping the first region in a plan view and a second end portion overlapping the second region in a plan view; The plurality of source contact plugs include: a third source contact plug connecting the first region to the field plate electrode within the first end; a fourth source contact plug connecting the second region to the field plate electrode within the second end; The semiconductor device according to any one of claims 2 to 4, comprising:

8. The plurality of connection trenches include: a plurality of first end connection trenches connecting the first ends of the plurality of gate trenches; a plurality of second end connection trenches connecting the second ends of the plurality of gate trenches; further comprising the third source contact plug extends in the second direction through the first ends of the gate trenches and the first end connection trenches; The semiconductor device according to claim 7 , wherein the fourth source contact plug extends in the second direction through the second ends of the gate trenches and the second end connection trenches.

9. each of the plurality of gate trenches includes a first end portion overlapping the first region in a plan view and a second end portion overlapping the second region in a plan view; 5. The semiconductor device according to claim 1, wherein each of the plurality of gate trenches intersects with the gate finger portion in a planar view near the center between the first end and the second end.

10. 5. The semiconductor device according to claim 1, wherein the first gate trenches and the second gate trenches are arranged alternately in the second direction.

11. 5. The semiconductor device according to claim 1, wherein the first gate trenches and the second gate trenches are arranged two by two alternately in the second direction.

12. The field plate electrode is a first pull-up portion passing between the first gate electrode and the second gate electrode in the first gate trench; a second pull-up portion passing between the first gate electrode and the second gate electrode in the second gate trench; The semiconductor device according to any one of claims 2 to 4, comprising:

13. The semiconductor device according to claim 12 , wherein the first pull-up portion is connected to the second region by the second source contact plug, and the second pull-up portion is connected to the first region by the first source contact plug.

14. 5. The semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode are located between the field plate electrode and the source wiring within the plurality of gate trenches.

15. 5. The semiconductor device according to claim 2, wherein the field plate electrode is connected to the source wiring via three or more source contact plugs among the plurality of source contact plugs in each gate trench.

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