Heat treatment method

Abstract

To provide a heat treatment method capable of developing larger residual polarization characteristics by a hafnium oxide-based film.SOLUTION: The surface of a semiconductor wafer on which a hafnium oxide-based film exhibiting ferroelectricity in an orthorhombic crystal is formed is irradiated with flash light from a flash lamp to raise the temperature of the surface to a peak temperature in one second or less. The hafnium oxide-based film has many crystal phases, but an orthorhombic crystal is a stable phase in a high temperature range near the peak temperature. Thereafter, when the surface temperature of the semiconductor wafer is decreased at a high temperature decrease rate of 8 °C / msec or more and 300 °C / msec or less, the semiconductor wafer is cooled with the crystalline structure as it is without changing the orthorhombic crystals, and the hafnium-oxide-based film after the temperature decrease maintains the orthorhombic crystals exhibiting ferroelectric properties. As a result, it is possible to allow the hafnium oxide-based film to exhibit larger remanent polarization characteristics even after the temperature is lowered.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] The present invention relates to a heat treatment method for heating a substrate having a hafnium oxide base film formed thereon by irradiating the substrate with flash light. Substrates to be treated include, for example, semiconductor wafers, substrates for liquid crystal displays, substrates for flat panel displays (FPDs), substrates for optical disks, substrates for magnetic disks, and substrates for solar cells. [Background technology]

[0002] In recent years, there has been active research into utilizing the properties of ferroelectrics in memory. Ferroelectrics are insulators that exhibit a property of polarization (remanent polarization) when an external electric field is applied, and the polarization remains even when the external electric field is removed to zero. Attempts are being made to develop high-speed non-volatile memory that takes advantage of the polarization properties of ferroelectrics.

[0003] Hafnium oxide (HfO2)-based materials are attracting attention as an example of ferroelectric materials, due to the fact that they exhibit good ferroelectric properties and can suppress leakage current even when thinned to a thickness of 10 nm or less, that they are compatible with CMOS (Complementary Metal-Oxide-Semiconductor), and that film formation technology using ALD (Atomic Layer Deposition) is mature.

[0004] Patent Documents 1 and 2 disclose that an amorphous hafnium oxide film is formed and then heat-treated to crystallize the hafnium oxide film into a ferroelectric film. Patent Documents 1 and 2 also show that a specific crystalline phase called an orthorhombic crystal must be formed in order for the hafnium oxide film to exhibit ferroelectricity.

[0005] Furthermore, a key challenge in applying hafnium oxide to devices is obtaining a larger remanent polarization value (2Pr). The ferroelectric properties can also be altered by adding other elements such as zirconium (Zr) or aluminum (Al) to hafnium oxide. Zirconium-doped hafnium oxide (HZO), the most widely studied, is known to have a higher remanent polarization than undoped hafnium oxide. Although HZO can be formed at a low temperature of around 500°C, it is vulnerable to thermal stress and prone to dielectric breakdown. On the other hand, aluminum-doped hafnium oxide (HAO) has superior remanent polarization and heat resistance compared to undoped hafnium oxide, and is expected to be used in the future. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2018-195767 [Patent Document 2] Japanese Patent Application Publication No. 2019-201172 Summary of the Invention [Problem to be solved by the invention]

[0007] Hafnium oxide has many crystalline phases, but at room temperature, only the metastable orthorhombic phase exhibits ferroelectricity. At high temperatures, the crystalline phase containing the orthorhombic phase is stable, but as the temperature drops, the orthorhombic phase is lost and the phase changes to a non-ferroelectric phase (the stable phase at room temperature). This has been an obstacle to achieving greater remanent polarization properties.

[0008] The present invention has been made in view of the above-mentioned problems, and has as its object to provide a heat treatment method that can cause a hafnium oxide-based film to exhibit large remanent polarization characteristics. [Means for solving the problem]

[0009] In order to solve the above problems, a first aspect of the present invention is a heat treatment method for heating a substrate having a hafnium oxide base film formed thereon by irradiating the substrate with flash light, the method comprising: a temperature-raising step of irradiating the surface of the substrate with flash light from a flash lamp to raise the temperature of the surface to a peak temperature within one second from the start of irradiation; and a temperature-lowering step of lowering the temperature of the surface of the substrate at a temperature-lowering rate of 8°C / millisecond or more and 300°C / millisecond or less.

[0010] In addition, a second aspect is the heat treatment method according to the first aspect, wherein silicon or aluminum is added to the hafnium oxide-based film.

[0011] In a third aspect, in the heat treatment method according to the first or second aspect, helium is supplied to the surface of the substrate in the temperature lowering step.

[0012] A fourth aspect is the heat treatment method according to the third aspect, wherein the supply flow rate of the helium is 1 liter / minute or more and 100 liters / minute or less.

[0013] In addition, a fifth aspect is the heat treatment method according to any one of the first to fourth aspects, wherein the hafnium oxide-based film has a thickness of 25 nm or less.

[0014] In addition, a sixth aspect is the heat treatment method according to any one of the first to fifth aspects, further comprising irradiating the substrate on which the wiring has been formed with a flash of light. [Effects of the Invention]

[0015] According to the heat treatment methods of the first to sixth aspects, the surface of a substrate on which a hafnium oxide base film has been formed is irradiated with flash light from a flash lamp, and the surface is heated to a peak temperature in one second or less from the start of irradiation, and the surface of the substrate is cooled at a rate of 8°C / millisecond or more and 300°C / millisecond or less. Therefore, the orthorhombic crystal structure of the hafnium oxide base film formed at the peak temperature does not change during cooling, and is cooled with the same crystalline structure, and the hafnium oxide base film after cooling also maintains the orthorhombic crystal structure that exhibits ferroelectricity, and exhibits greater remanent polarization characteristics.

[0016] In particular, according to the heat treatment method of the third aspect, helium is supplied to the surface of the substrate, so that the rate at which the surface temperature of the substrate is lowered can be further increased, and the hafnium oxide-based film can exhibit greater remanent polarization characteristics. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a vertical cross-sectional view showing the configuration of a heat treatment apparatus for carrying out a heat treatment method according to the present invention. [Figure 2] FIG. 2 is a perspective view showing the overall appearance of the holding portion. [Figure 3] FIG. [Figure 4] FIG. 2 is a cross-sectional view of a susceptor. [Figure 5] FIG. [Figure 6] FIG. [Figure 7] FIG. 2 is a plan view showing the arrangement of a plurality of halogen lamps. [Figure 8] FIG. 2 is a diagram showing a driving circuit for a flash lamp. [Figure 9] 1 is a flowchart showing a processing procedure of a heat treatment method according to the present invention. [Figure 10] FIG. 1 is a diagram showing an example of a semiconductor wafer on which a hafnium oxide-based film is formed. [Figure 11] FIG. 1 is a diagram showing temperature changes of a semiconductor wafer. [Figure 12]FIG. 10 is a diagram showing changes in the surface temperature of a semiconductor wafer when irradiated with flash light. [Figure 13] FIG. 10 is a diagram showing the correlation between the temperature decreasing rate and the remanent polarization characteristics. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Hereinafter, expressions indicating relative or absolute positional relationships (e.g., "in one direction," "along one direction," "parallel," "orthogonal," "center," "concentric," "coaxial," etc.) not only strictly represent the positional relationship but also represent a state of relative angular or distance displacement within a tolerance or a range that provides equivalent functionality, unless otherwise specified. Furthermore, expressions indicating an equal state (e.g., "identical," "equal," "homogeneous," etc.) not only represent a state of strict quantitative equality but also represent a state of difference that provides a tolerance or equivalent functionality, unless otherwise specified. Furthermore, expressions indicating a shape (e.g., "circular," "square," "cylindrical," etc.) not only represent a geometrically strict shape but also represent a shape within a range that provides equivalent functionality, such as irregularities or chamfers, unless otherwise specified. Furthermore, expressions such as "comprise," "comprise," "include," "have," etc., regarding components, are not exclusive expressions that exclude the presence of other components. Furthermore, the expression "at least one of A, B, and C" includes "A only," "B only," "C only," "any two of A, B, and C," and "all of A, B, and C."

[0019] FIG. 1 is a longitudinal cross-sectional view showing the configuration of a heat treatment apparatus 1 for carrying out a heat treatment method according to the present invention. The heat treatment apparatus 1 in FIG. 1 is a flash lamp annealing apparatus that heats a disk-shaped semiconductor wafer W as a substrate by irradiating the semiconductor wafer W with flash light. The size of the semiconductor wafer W to be treated is not particularly limited, but may be, for example, φ300 mm or φ450 mm (φ300 mm in this embodiment). Note that in FIG. 1 and the subsequent figures, the dimensions and number of various parts are exaggerated or simplified as necessary for ease of understanding.

[0020] Heat treatment apparatus 1 includes a chamber 6 that accommodates a semiconductor wafer W, a flash heating unit 5 that incorporates multiple flash lamps FL, and a halogen heating unit 4 that incorporates multiple halogen lamps HL. The flash heating unit 5 is provided above chamber 6, and the halogen heating unit 4 is provided below. Heat treatment apparatus 1 also includes, inside chamber 6, a holder 7 that holds the semiconductor wafer W in a horizontal position, and a transfer mechanism 10 that transfers the semiconductor wafer W between the holder 7 and the outside of the apparatus. Heat treatment apparatus 1 also includes a control unit 3 that controls the operating mechanisms provided in the halogen heating unit 4, flash heating unit 5, and chamber 6 to perform heat treatment on the semiconductor wafer W.

[0021] The chamber 6 is constructed by attaching quartz chamber windows to the top and bottom of a cylindrical chamber side portion 61. The chamber side portion 61 has a roughly cylindrical shape with openings at the top and bottom, with an upper chamber window 63 attached to and closing the upper opening, and a lower chamber window 64 attached to and closing the lower opening. The upper chamber window 63, which forms the ceiling of the chamber 6, is a disc-shaped member made of quartz and functions as a quartz window that transmits the flash light emitted from the flash heating unit 5 into the chamber 6. The lower chamber window 64, which forms the floor of the chamber 6, is also a disc-shaped member made of quartz and functions as a quartz window that transmits the light from the halogen heating unit 4 into the chamber 6.

[0022] Furthermore, a reflective ring 68 is attached to the upper part of the inner wall surface of the chamber side 61, and a reflective ring 69 is attached to the lower part. Both reflective rings 68, 69 are formed in an annular shape. The upper reflective ring 68 is attached by fitting it from the upper side of the chamber side 61. On the other hand, the lower reflective ring 69 is attached by fitting it from the lower side of the chamber side 61 and fastening it with screws (not shown). In other words, both reflective rings 68, 69 are detachably attached to the chamber side 61. The internal space of the chamber 6, i.e., the space surrounded by the upper chamber window 63, the lower chamber window 64, the chamber side 61, and the reflective rings 68, 69, is defined as a heat treatment space 65.

[0023] By attaching the reflecting rings 68, 69 to the chamber side portion 61, a recess 62 is formed on the inner wall surface of the chamber 6. That is, the recess 62 is formed by a central portion of the inner wall surface of the chamber side portion 61 where the reflecting rings 68, 69 are not attached, the lower end surface of the reflecting ring 68, and the upper end surface of the reflecting ring 69. The recess 62 is formed in an annular shape along the horizontal direction on the inner wall surface of the chamber 6, and surrounds the holder 7 that holds the semiconductor wafer W. The chamber side portion 61 and the reflecting rings 68, 69 are made of a metal material (e.g., stainless steel) that has excellent strength and heat resistance.

[0024] Furthermore, a transfer opening (furnace port) 66 is formed in the chamber side portion 61, through which a semiconductor wafer W is loaded into and unloaded from the chamber 6. The transfer opening 66 can be opened and closed by a gate valve 185. The transfer opening 66 is connected to the outer peripheral surface of the recessed portion 62. Therefore, when the gate valve 185 opens the transfer opening 66, the semiconductor wafer W can be loaded into and unloaded from the heat treatment space 65 through the transfer opening 66 and the recessed portion 62. Furthermore, when the gate valve 185 closes the transfer opening 66, the heat treatment space 65 in the chamber 6 becomes an airtight space.

[0025] Furthermore, through-holes 61a and 61b are formed in the chamber side portion 61. The through-hole 61a is a cylindrical hole for guiding infrared light radiated from the upper surface of a semiconductor wafer W held on a susceptor 74 (described later) to the infrared sensor 29 of the upper radiation thermometer 25. On the other hand, the through-hole 61b is a cylindrical hole for guiding infrared light radiated from the lower surface of the semiconductor wafer W to the lower radiation thermometer 20. The through-holes 61a and 61b are provided at an angle with respect to the horizontal direction so that their penetrating axes intersect with the main surface of the semiconductor wafer W held on the susceptor 74. A transparent window 26 made of calcium fluoride material that transmits infrared light in a wavelength range measurable by the upper radiation thermometer 25 is attached to the end of the through-hole 61a facing the heat treatment space 65. Furthermore, a transparent window 21 made of barium fluoride material that transmits infrared light in the wavelength range that can be measured by the lower radiation thermometer 20 is attached to the end of the through hole 61b facing the heat treatment space 65.

[0026] Furthermore, gas supply holes 81 are formed in the upper part of the inner wall of the chamber 6 to supply processing gas to the heat treatment space 65. The gas supply holes 81 are formed at a position above the recessed portion 62 and may be provided in the reflecting ring 68. The gas supply holes 81 are connected to a gas supply pipe 83 via a buffer space 82 formed in an annular shape inside the side wall of the chamber 6. The gas supply pipe 83 is connected to a processing gas supply source 85. A valve 84 is inserted in the gas supply pipe 83. When the valve 84 is opened, processing gas is supplied from the processing gas supply source 85 to the buffer space 82. The processing gas that has flowed into the buffer space 82 spreads within the buffer space 82, which has lower fluid resistance than the gas supply holes 81, and is supplied from the gas supply holes 81 into the heat treatment space 65. The processing gas may be, for example, an inert gas such as nitrogen (N2), argon (Ar), or helium (He), or a reactive gas such as hydrogen (H2), ammonia (NH3), or a mixed gas of these.

[0027] Meanwhile, a gas exhaust hole 86 is formed in the lower part of the inner wall of the chamber 6 to exhaust gas from the heat treatment space 65. The gas exhaust hole 86 is formed below the recess 62 and may be provided in the reflecting ring 69. The gas exhaust hole 86 is connected to a gas exhaust pipe 88 via a buffer space 87 formed in an annular shape inside the side wall of the chamber 6. The gas exhaust pipe 88 is connected to an exhaust unit 190. A valve 89 is inserted in the gas exhaust pipe 88. When the valve 89 is opened, the gas in the heat treatment space 65 is exhausted from the gas exhaust hole 86 through the buffer space 87 to the gas exhaust pipe 88. The gas supply hole 81 and the gas exhaust hole 86 may be provided in multiple numbers along the circumferential direction of the chamber 6, or may be slit-shaped. The process gas supply source 85 and the exhaust unit 190 may be mechanisms provided in the heat treatment apparatus 1 or may be utilities of a factory where the heat treatment apparatus 1 is installed.

[0028] A gas exhaust pipe 191 for discharging gas from the heat treatment space 65 is also connected to the tip of the transfer opening 66. The gas exhaust pipe 191 is connected to an exhaust unit 190 via a valve 192. By opening the valve 192, the gas in the chamber 6 is exhausted through the transfer opening 66.

[0029] 2 is a perspective view showing the overall appearance of the holder 7. The holder 7 is configured to include a base ring 71, a connecting portion 72, and a susceptor 74. The base ring 71, the connecting portion 72, and the susceptor 74 are all made of quartz. In other words, the entire holder 7 is made of quartz.

[0030] The base ring 71 is an arc-shaped quartz member with a portion missing from the annular shape. This missing portion is provided to prevent interference between the base ring 71 and a transfer arm 11 of the transfer mechanism 10, which will be described later. The base ring 71 is placed on the bottom surface of the recess 62, and is supported by the wall surface of the chamber 6 (see FIG. 1). A plurality of connecting portions 72 (four in this embodiment) are erected on the upper surface of the base ring 71 along the circumferential direction of the annular shape. The connecting portions 72 are also quartz members, and are fixed to the base ring 71 by welding.

[0031] The susceptor 74 is supported by four connecting portions 72 provided on the base ring 71. FIG. 3 is a plan view of the susceptor 74. FIG. 4 is a cross-sectional view of the susceptor 74. The susceptor 74 includes a holding plate 75, a guide ring 76, and a plurality of substrate support pins 77. The holding plate 75 is a substantially circular, flat member made of quartz. The diameter of the holding plate 75 is larger than the diameter of the semiconductor wafer W. That is, the holding plate 75 has a planar size larger than that of the semiconductor wafer W.

[0032] A guide ring 76 is installed on the periphery of the upper surface of the holding plate 75. The guide ring 76 is an annular member having an inner diameter larger than the diameter of the semiconductor wafer W. For example, if the diameter of the semiconductor wafer W is φ300 mm, the inner diameter of the guide ring 76 is φ320 mm. The inner periphery of the guide ring 76 has a tapered surface that widens upward from the holding plate 75. The guide ring 76 is made of quartz, the same as the holding plate 75. The guide ring 76 may be welded to the upper surface of the holding plate 75, or may be fixed to the holding plate 75 by a separately processed pin or the like. Alternatively, the holding plate 75 and the guide ring 76 may be processed as an integrated member.

[0033] The area of ​​the upper surface of the holding plate 75 that is inside the guide ring 76 is a flat holding surface 75a that holds the semiconductor wafer W. A plurality of substrate support pins 77 are provided on the holding surface 75a of the holding plate 75. In this embodiment, a total of 12 substrate support pins 77 are provided at 30° intervals along a circumference concentric with the outer circumferential circle of the holding surface 75a (the inner circumferential circle of the guide ring 76). The diameter of the circle on which the 12 substrate support pins 77 are arranged (the distance between opposing substrate support pins 77) is smaller than the diameter of the semiconductor wafer W. If the diameter of the semiconductor wafer W is 300 mm, the diameter is 270 mm to 280 mm (270 mm in this embodiment). Each substrate support pin 77 is made of quartz. The plurality of substrate support pins 77 may be provided on the upper surface of the holding plate 75 by welding, or may be machined integrally with the holding plate 75.

[0034] Returning to FIG. 2, four connecting portions 72 erected on the base ring 71 are fixed to the peripheral edge of the holding plate 75 of the susceptor 74 by welding. That is, the susceptor 74 and the base ring 71 are fixedly connected by the connecting portions 72. The base ring 71 of the holding portion 7 is supported on the wall surface of the chamber 6, and the holding portion 7 is thereby attached to the chamber 6. When the holding portion 7 is attached to the chamber 6, the holding plate 75 of the susceptor 74 is in a horizontal position (a position in which the normal line coincides with the vertical direction). That is, the holding surface 75a of the holding plate 75 is a horizontal plane.

[0035] The semiconductor wafer W carried into the chamber 6 is placed and held in a horizontal position on the susceptor 74 of the holder 7 attached to the chamber 6. At this time, the semiconductor wafer W is supported by twelve substrate support pins 77 erected on a holding plate 75 and held on the susceptor 74. More precisely, the upper ends of the twelve substrate support pins 77 contact the underside of the semiconductor wafer W to support the semiconductor wafer W. The heights of the twelve substrate support pins 77 (the distance from the upper ends of the substrate support pins 77 to the holding surface 75a of the holding plate 75) are uniform, so the twelve substrate support pins 77 can support the semiconductor wafer W in a horizontal position.

[0036] Furthermore, the semiconductor wafer W is supported by a plurality of substrate support pins 77 at a predetermined distance from the holding surface 75a of the holding plate 75. The thickness of the guide ring 76 is greater than the height of the substrate support pins 77. Therefore, the guide ring 76 prevents the semiconductor wafer W supported by the plurality of substrate support pins 77 from shifting in the horizontal direction.

[0037] 2 and 3, an opening 78 is formed in the holding plate 75 of the susceptor 74, penetrating vertically. The opening 78 is provided so that the lower radiation thermometer 20 can receive radiation (infrared light) emitted from the underside of the semiconductor wafer W. That is, the lower radiation thermometer 20 receives the light emitted from the underside of the semiconductor wafer W through the opening 78 and a transparent window 21 attached to the through-hole 61b of the chamber side 61, thereby measuring the temperature of the semiconductor wafer W. Furthermore, the holding plate 75 of the susceptor 74 is formed with four through-holes 79 through which lift pins 12 of the transfer mechanism 10, which will be described later, pass to transfer the semiconductor wafer W.

[0038] FIG. 5 is a plan view of the transfer mechanism 10. FIG. 6 is a side view of the transfer mechanism 10. The transfer mechanism 10 includes two transfer arms 11. The transfer arms 11 are arc-shaped so as to fit the generally annular recess 62. Two lift pins 12 are provided on each of the transfer arms 11. The transfer arms 11 and the lift pins 12 are made of quartz. Each transfer arm 11 is rotatable by a horizontal movement mechanism 13. The horizontal movement mechanism 13 horizontally moves the pair of transfer arms 11 between a transfer operation position (position indicated by a solid line in FIG. 5) where the transfer arms 11 transfer the semiconductor wafer W to the holder 7 and a retracted position (position indicated by a two-dot chain line in FIG. 5) where the transfer arms 11 do not overlap the semiconductor wafer W held by the holder 7 in a plan view. The horizontal movement mechanism 13 may be one that rotates each transfer arm 11 using an individual motor, or one that uses a link mechanism to rotate a pair of transfer arms 11 in conjunction with one another using a single motor.

[0039] Furthermore, the pair of transfer arms 11 are raised and lowered together with the horizontal movement mechanism 13 by the lifting mechanism 14. When the lifting mechanism 14 raises the pair of transfer arms 11 to the transfer operation position, a total of four lift pins 12 pass through through holes 79 (see FIGS. 2 and 3 ) formed in the susceptor 74, and the upper ends of the lift pins 12 protrude from the upper surface of the susceptor 74. On the other hand, when the lifting mechanism 14 lowers the pair of transfer arms 11 to the transfer operation position to remove the lift pins 12 from the through holes 79, and the horizontal movement mechanism 13 moves the pair of transfer arms 11 so as to open, each transfer arm 11 moves to a retracted position. The retracted position of the pair of transfer arms 11 is directly above the base ring 71 of the holder 7. Because the base ring 71 is placed on the bottom surface of the recess 62, the retracted position of the transfer arms 11 is inside the recess 62. In addition, an exhaust mechanism (not shown) is also provided near the location where the drive part of the transfer mechanism 10 (horizontal movement mechanism 13 and lifting mechanism 14) is located, and is configured to exhaust the atmosphere around the drive part of the transfer mechanism 10 to the outside of the chamber 6.

[0040] Returning to FIG. 1 , the flash heating unit 5, which is provided above the chamber 6, is configured with a light source made up of multiple (30 in this embodiment) xenon flash lamps FL inside a housing 51, and a reflector 52 provided to cover the light source from above. A lamp light emission window 53 is attached to the bottom of the housing 51 of the flash heating unit 5. The lamp light emission window 53, which forms the floor of the flash heating unit 5, is a plate-shaped quartz window made of quartz. By installing the flash heating unit 5 above the chamber 6, the lamp light emission window 53 faces the upper chamber window 63. The flash lamps FL irradiate a heat treatment space 65 with flash light from above the chamber 6 through the lamp light emission window 53 and the upper chamber window 63.

[0041] The multiple flash lamps FL are each a rod-shaped lamp having a long cylindrical shape, and are arranged in a plane so that their longitudinal directions are parallel to each other along the main surface of the semiconductor wafer W held by the holder 7 (i.e., along the horizontal direction). Therefore, the plane formed by the arrangement of the flash lamps FL is also a horizontal plane.

[0042] 8 is a diagram showing a drive circuit for a flash lamp FL. As shown in the figure, a capacitor 93, a coil 94, a flash lamp FL, and an IGBT (insulated gate bipolar transistor) 96 are connected in series. Also, as shown in FIG. 8, a control unit 3 includes a pulse generator 31 and a waveform setting unit 32, and is connected to an input unit 33. Various known input devices such as a keyboard, a mouse, or a touch panel can be used as the input unit 33. The waveform setting unit 32 sets the waveform of a pulse signal based on the input content from the input unit 33, and the pulse generator 31 generates a pulse signal in accordance with that waveform.

[0043] The flash lamp FL includes a rod-shaped glass tube (discharge tube) 92 filled with xenon gas and having an anode and a cathode at both ends, and a trigger electrode 91 attached to the outer surface of the glass tube 92. A predetermined voltage is applied to a capacitor 93 by a power supply unit 95, and an electric charge corresponding to the applied voltage (charging voltage) is stored in the capacitor 93. A high voltage can be applied to the trigger electrode 91 from a trigger circuit 97. The timing at which the trigger circuit 97 applies a voltage to the trigger electrode 91 is controlled by the control unit 3.

[0044] The IGBT 96 is a bipolar transistor incorporating a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in its gate, and is a switching element suitable for handling large amounts of power. A pulse signal is applied to the gate of the IGBT 96 from the pulse generator 31 of the control unit 3. When a voltage equal to or greater than a predetermined value (high voltage) is applied to the gate of the IGBT 96, the IGBT 96 turns on, and when a voltage less than the predetermined value (low voltage) is applied, the IGBT 96 turns off. In this way, the drive circuit including the flash lamp FL is turned on and off by the IGBT 96. By turning the IGBT 96 on and off, the connection between the flash lamp FL and the corresponding capacitor 93 is interrupted, and the current flowing through the flash lamp FL is controlled on and off.

[0045] Even if the IGBT 96 is turned on and a high voltage is applied to both electrodes of the glass tube 92 while the capacitor 93 is charged, xenon gas is an electrical insulator, so under normal conditions no electricity flows through the glass tube 92. However, if the trigger circuit 97 applies a high voltage to the trigger electrode 91, causing the insulation to break down, a discharge occurs between the electrodes, causing a current to flow instantaneously through the glass tube 92, and light is emitted due to the excitation of xenon atoms or molecules at that time.

[0046] A drive circuit such as that shown in Fig. 8 is provided individually for each of the multiple flash lamps FL provided in the flash heating unit 5. In this embodiment, 30 flash lamps FL are arranged in a plane, and therefore 30 drive circuits such as that shown in Fig. 8 are provided corresponding to these flash lamps FL. Therefore, the current flowing through each of the 30 flash lamps FL is individually on / off controlled by the corresponding IGBT 96.

[0047] Furthermore, reflector 52 is provided above the multiple flash lamps FL so as to cover them entirely. The basic function of reflector 52 is to reflect the flash light emitted from the multiple flash lamps FL toward the heat treatment space 65. Reflector 52 is made of an aluminum alloy plate, and its surface (the surface facing the flash lamps FL) is roughened by blasting.

[0048] The halogen heating unit 4, which is provided below the chamber 6, has a plurality of halogen lamps HL (40 in this embodiment) built into the inside of the housing 41. The halogen heating unit 4 is a light irradiation unit that heats the semiconductor wafer W by irradiating light from the plurality of halogen lamps HL from below the chamber 6 through a lower chamber window 64 into a heat treatment space 65.

[0049] FIG. 7 is a plan view showing the arrangement of multiple halogen lamps HL. 40 halogen lamps HL are arranged in two rows, upper and lower. 20 halogen lamps HL are arranged in the upper row, which is closer to the holder 7, and 20 halogen lamps HL are also arranged in the lower row, which is farther from the holder 7 than the upper row. Each halogen lamp HL is a rod-shaped lamp having a long cylindrical shape. In both the upper and lower rows, the 20 halogen lamps HL are arranged so that their longitudinal directions are parallel to each other along the main surface of the semiconductor wafer W held by the holder 7 (i.e., along the horizontal direction). Therefore, the plane formed by the arrangement of the halogen lamps HL in both the upper and lower rows is a horizontal plane.

[0050] 7, the halogen lamps HL are arranged more densely in the region facing the periphery of the semiconductor wafer W held by the holder 7 on both the upper and lower tiers than in the region facing the center of the semiconductor wafer W. That is, on both the upper and lower tiers, the halogen lamps HL are arranged at a shorter pitch in the periphery of the lamp arrangement than in the center. This allows a greater amount of light to be irradiated onto the periphery of the semiconductor wafer W, which is prone to temperature drop during heating due to light irradiation from the halogen heating unit 4.

[0051] The lamp group consisting of the halogen lamps HL on the upper row and the lamp group consisting of the halogen lamps HL on the lower row are arranged so as to intersect in a grid pattern. That is, a total of 40 halogen lamps HL are arranged so that the longitudinal direction of the 20 halogen lamps HL arranged on the upper row and the longitudinal direction of the 20 halogen lamps HL arranged on the lower row are perpendicular to each other.

[0052] A halogen lamp HL is a filament-type light source that emits light by passing electricity through a filament placed inside a glass tube, causing it to incandescent. The glass tube is filled with an inert gas, such as nitrogen or argon, containing trace amounts of halogen elements (iodine, bromine, etc.). The introduction of halogen elements makes it possible to set the filament temperature at a high temperature while preventing filament breakage. Therefore, compared to standard incandescent light bulbs, halogen lamps HL have the characteristics of a longer lifespan and the ability to continuously emit strong light. In other words, halogen lamps HL are continuous lamps that emit light continuously for at least one second. Furthermore, because halogen lamps HL are rod-shaped, they have a long lifespan, and by arranging them horizontally, they achieve excellent radiation efficiency toward the semiconductor wafer W above.

[0053] Also, a reflector 43 is provided below the two-tiered halogen lamps HL inside the housing 41 of the halogen heating unit 4 (FIG. 1). The reflector 43 reflects the light emitted from the multiple halogen lamps HL toward the heat treatment space 65.

[0054] As shown in FIG. 1, the heat treatment apparatus 1 includes an upper radiation thermometer 25 and a lower radiation thermometer 20. The upper radiation thermometer 25 is installed diagonally above the semiconductor wafer W held on the susceptor 74 and receives infrared light radiated from the top surface of the semiconductor wafer W to measure the temperature of the top surface. The infrared sensor 29 of the upper radiation thermometer 25 includes an InSb (indium antimonide) optical element to respond to the sudden temperature change on the top surface of the semiconductor wafer W at the moment when the flash light is irradiated. On the other hand, the lower radiation thermometer 20 is installed diagonally below the semiconductor wafer W held on the susceptor 74 and receives infrared light radiated from the bottom surface of the semiconductor wafer W to measure the temperature of the bottom surface.

[0055] The control unit 3 controls the various operating mechanisms provided in the heat treatment device 1. The hardware configuration of the control unit 3 is similar to that of a general computer. That is, the control unit 3 includes a CPU, which is a circuit that performs various arithmetic processing, a ROM, which is a read-only memory that stores basic programs, a RAM, which is a read / write memory that stores various information, and a storage unit (e.g., a magnetic disk or SSD) that stores control software, data, and the like. The CPU of the control unit 3 executes a predetermined processing program, thereby causing the heat treatment device 1 to perform processing. The control unit 3 also includes a pulse generator 31 and a waveform setting unit 32 (FIG. 8). The waveform setting unit 32 sets the waveform of a pulse signal based on input from the input unit 33, and the pulse generator 31 outputs a pulse signal to the gate of the IGBT 96 accordingly.

[0056] In addition to the above configuration, the heat treatment apparatus 1 is equipped with various cooling structures to prevent excessive temperature rise in the halogen heating unit 4, flash heating unit 5, and chamber 6 due to the thermal energy generated by the halogen lamps HL and flash lamps FL during heat treatment of the semiconductor wafer W. For example, a water-cooled pipe (not shown) is provided in the wall of the chamber 6. The halogen heating unit 4 and flash heating unit 5 also have an air-cooled structure that creates a gas flow inside to remove heat. Air is also supplied to the gap between the upper chamber window 63 and the lamp light emission window 53 to cool the flash heating unit 5 and upper chamber window 63.

[0057] Next, the procedure of the heat treatment method according to the present invention will be described. Fig. 9 is a flowchart showing the procedure of the heat treatment method according to the present invention. First, prior to heat treatment in the heat treatment apparatus 1, a hafnium oxide base film is formed on the semiconductor wafer W (step S1). The process of step S1 is performed by a film formation apparatus different from the heat treatment apparatus 1.

[0058] FIG. 10 shows an example of a semiconductor wafer W on which a hafnium oxide-based film 103 is formed. After a native oxide film (SiO2) is removed from the surface of a silicon substrate 101 by a cleaning process, a titanium nitride (TiN) lower electrode 102 is formed on the surface. The lower electrode 102 has a thickness of, for example, 50 nm. A hafnium oxide-based film 103 is formed on the lower electrode 102. The hafnium oxide-based film 103 is a thin film made of a material primarily composed of hafnium oxide (HfO2: hafnia) and containing additional elements, and exhibits ferroelectricity when its crystal structure becomes orthorhombic. Examples of the additional elements include zirconium (Zr), silicon (Si), aluminum (Al), and lanthanum (La). The inclusion of these additional elements is expected to improve the polarization characteristics of hafnium oxide. In this embodiment, the hafnium oxide-based film 103 is made of HAO, which is hafnium oxide with aluminum added. The aluminum concentration (X / (Hf+X)%) when the added element is X is 15% or less (6% in this embodiment). In the hafnium oxide-based film 103, hafnium, aluminum, and oxygen are bonded to one another. An upper layer electrode 104 of titanium nitride is further formed on the hafnium oxide-based film 103. The film thickness of the upper layer electrode 104 is, for example, 50 nm.

[0059] The hafnium oxide-based film 103 is formed using ALD (Atomic Layer Deposition) or PVD (Physical Vapor Deposition). Regardless of which method is used, the formed hafnium oxide-based film 103 is amorphous and does not have a crystalline structure. The thickness of the hafnium oxide-based film 103 formed on the semiconductor wafer W is 25 nm or less (10 nm in this embodiment). If the thickness of the hafnium oxide-based film 103 is greater than 25 nm, it becomes difficult for the hafnium oxide-based film 103 to exhibit ferroelectricity. In the following description, the entire layer structure of FIG. 10 including the formed hafnium oxide-based film 103 is referred to as the semiconductor wafer W. In other words, the semiconductor wafer W includes the hafnium oxide-based film 103 formed on the surface. The surface of the semiconductor wafer W also includes the lower electrode 102, the hafnium oxide-based film 103, and the upper electrode 104 formed thereon.

[0060] Next, the semiconductor wafer W on which the hafnium oxide base film 103 has been formed is loaded into the chamber 6 (step S2). When the wafer is loaded, the valve 84 for supplying air is opened, and the exhaust valves 89, 192 are also opened to start supplying and exhausting air to and from the chamber 6. When the valve 84 is opened, nitrogen gas is supplied from the gas supply hole 81 to the heat treatment space 65. When the valve 89 is opened, the gas in the chamber 6 is exhausted from the gas exhaust hole 86. As a result, the nitrogen gas supplied from the upper part of the heat treatment space 65 in the chamber 6 flows downward and is exhausted from the lower part of the heat treatment space 65.

[0061] Furthermore, by opening the valve 192, the gas inside the chamber 6 is also exhausted from the transfer opening 66. Furthermore, the atmosphere around the drive unit of the transfer mechanism 10 is also exhausted by an exhaust mechanism (not shown). Note that during the heat treatment of the semiconductor wafer W in the heat treatment apparatus 1, nitrogen gas is continuously supplied to the heat treatment space 65, and the supply amount is changed as appropriate depending on the treatment process.

[0062] Subsequently, the gate valve 185 is opened to open the transfer opening 66, and the semiconductor wafer W on which the hafnium oxide base film 103 has been formed is carried into the heat treatment space 65 in the chamber 6 through the transfer opening 66 by a transfer robot outside the apparatus. At this time, there is a risk that the atmosphere outside the apparatus may be drawn in as the semiconductor wafer W is carried in, but since nitrogen gas is continuously supplied to the chamber 6, the nitrogen gas flows out from the transfer opening 66, making it possible to minimize the drawing in of such external atmosphere.

[0063] The semiconductor wafer W carried in by the transfer robot advances to a position directly above the holder 7 and stops there. Then, the pair of transfer arms 11 of the transfer mechanism 10 move horizontally from the retracted position to the transfer operation position and rise, causing the lift pins 12 to pass through the through holes 79 and protrude from the upper surface of the holding plate 75 of the susceptor 74 to receive the semiconductor wafer W. At this time, the lift pins 12 rise to a position higher than the upper ends of the substrate support pins 77.

[0064] After the semiconductor wafer W is placed on the lift pins 12, the transfer robot exits the heat treatment space 65, and the transfer opening 66 is closed by the gate valve 185. Then, the pair of transfer arms 11 descend, transferring the semiconductor wafer W from the transfer mechanism 10 to the susceptor 74 of the holder 7, where it is held from below in a horizontal position. The semiconductor wafer W is supported by a plurality of substrate support pins 77 erected on a holding plate 75 and held on the susceptor 74. The semiconductor wafer W is held on the holder 7 with the front surface on which the hafnium oxide base film 103 is formed facing upward. A predetermined gap is formed between the back surface (the main surface opposite to the front surface) of the semiconductor wafer W supported by the plurality of substrate support pins 77 and the holding surface 75a of the holding plate 75. The pair of transfer arms 11, which have descended to below the susceptor 74, are retracted to a retracted position, i.e., inside the recess 62, by the horizontal movement mechanism 13.

[0065] After the semiconductor wafer W is held from below in a horizontal position by the susceptor 74 of the holder 7, which is made of quartz, the 40 halogen lamps HL of the halogen heating unit 4 are simultaneously turned on to begin preheating (assisted heating) (step S3). The halogen light emitted from the halogen lamps HL passes through the lower chamber window 64 and the susceptor 74, both of which are made of quartz, and is irradiated onto the underside of the semiconductor wafer W. The semiconductor wafer W is preheated by being irradiated with light from the halogen lamps HL, and its temperature rises. Note that the transfer arm 11 of the transfer mechanism 10 is retracted inside the recess 62, so it does not interfere with heating by the halogen lamps HL.

[0066] FIG. 11 shows the temperature change of a semiconductor wafer W. At time t1, the halogen lamps HL are turned on, and the temperature of the semiconductor wafer W begins to rise. When preheating is performed by the halogen lamps HL, the temperature of the semiconductor wafer W is measured by the lower radiation thermometer 20. That is, the lower radiation thermometer 20 receives infrared light radiated from the underside of the semiconductor wafer W held on the susceptor 74 through the openings 78 and measures the wafer temperature during heating. The measured temperature of the semiconductor wafer W is transmitted to the control unit 3. The control unit 3 controls the output of the halogen lamps HL while monitoring whether the temperature of the semiconductor wafer W, which is heated by the light irradiation from the halogen lamps HL, has reached a predetermined preheating temperature T1. That is, the control unit 3 performs feedback control of the output of the halogen lamps HL based on the measurement value of the lower radiation thermometer 20 so that the temperature of the semiconductor wafer W becomes the preheating temperature T1. In this way, the lower radiation thermometer 20 is a radiation thermometer for controlling the temperature of the semiconductor wafer W during preheating. The preheating temperature T1 is 100° C. or higher and 600° C. or lower (400° C. in this embodiment).

[0067] After the temperature of the semiconductor wafer W reaches the preheating temperature T1 at time t2, the control unit 3 temporarily maintains the semiconductor wafer W at the preheating temperature T1. Specifically, when the temperature of the semiconductor wafer W measured by the lower radiation thermometer 20 reaches the preheating temperature T1, the control unit 3 adjusts the output of the halogen lamps HL to maintain the temperature of the semiconductor wafer W at approximately the preheating temperature T1.

[0068] By performing preheating using the halogen lamps HL in this manner, the entire semiconductor wafer W, including the hafnium oxide-based film 103, is uniformly heated to the preheating temperature T1. During preheating using the halogen lamps HL, the temperature of the peripheral portion of the semiconductor wafer W, where heat dissipation is more likely, tends to be lower than that of the central portion, but the arrangement density of the halogen lamps HL in the halogen heating unit 4 is higher in the region facing the peripheral portion of the semiconductor wafer W than in the region facing the central portion. As a result, a greater amount of light is irradiated onto the peripheral portion of the semiconductor wafer W, where heat dissipation is more likely, and the in-plane temperature distribution of the semiconductor wafer W during the preheating stage can be made uniform.

[0069] At time t3, when a predetermined time has elapsed since the temperature of the semiconductor wafer W reached the preheating temperature T1, the flash lamps FL of the flash heating unit 5 irradiate the surface of the semiconductor wafer W held on the susceptor 74 with flash light (step S4). At this time, part of the flash light emitted from the flash lamps FL heads directly into the chamber 6, and the other part is reflected by the reflector 52 before heading into the chamber 6, and the semiconductor wafer W is flash-heated by the irradiation of these flash lights.

[0070] When the flash lamp FL emits a flash of light, a charge is stored in advance in the capacitor 93 at a predetermined charging voltage by the power supply unit 95. Then, with the charge stored in the capacitor 93, a pulse signal is output from the pulse generator 31 of the control unit 3 to the IGBT 96 to turn the IGBT 96 on and off.

[0071] The waveform of the pulse signal can be specified by inputting a recipe from input unit 33 in which the pulse width time (on time) and the pulse interval time (off time) are sequentially set as parameters. When an operator inputs such a recipe from input unit 33 to control unit 3, waveform setting unit 32 of control unit 3 sets a pulse waveform that repeats on and off accordingly. Then, pulse generator 31 outputs a pulse signal in accordance with the pulse waveform set by waveform setting unit 32. As a result, a pulse signal of the set waveform is applied to the gate of IGBT 96, controlling the on / off driving of IGBT 96. Specifically, when the pulse signal input to the gate of IGBT 96 is on, IGBT 96 is turned on, and when the pulse signal is off, IGBT 96 is turned off.

[0072] Furthermore, in synchronization with the timing at which the pulse signal output from the pulse generator 31 turns on, the control unit 3 controls the trigger circuit 97 to apply a high voltage (trigger voltage) to the trigger electrode 91. When charge is accumulated in the capacitor 93, a pulse signal is input to the gate of the IGBT 96, and in synchronization with the timing at which the pulse signal turns on, a high voltage is applied to the trigger electrode 91. When the pulse signal is on, a current flows between the electrodes at both ends in the glass tube 92, and light is emitted due to the excitation of xenon atoms or molecules at that time.

[0073] In this way, the 30 flash lamps FL of the flash heating unit 5 emit light, irradiating the surface of the semiconductor wafer W held in the holder 7 with a flash of light. If the flash lamps FL were driven without the IGBT 96, the charge stored in the capacitor 93 would be consumed with each flash, resulting in a simple single-pulse output waveform with a width of approximately 0.1 to 10 milliseconds. In contrast, in this embodiment, the IGBT 96, which functions as a switching element, is connected to the circuit and a pulse signal is output to its gate. This allows the IGBT 96 to intermittently control the supply of charge from the capacitor 93 to the flash lamp FL, thereby controlling the on / off of the current flowing through the flash lamp FL. As a result, the light emission of the flash lamp FL is essentially chopper-controlled, with the charge stored in the capacitor 93 being consumed in parts, causing the flash lamp FL to repeatedly blink for an extremely short period of time. Note that before the current flowing through the circuit reaches zero, the next pulse is applied to the gate of the IGBT 96, causing the current to increase again. Therefore, the light emission output of the flash lamp FL does not become completely zero even while the flash lamp FL is repeatedly blinking.

[0074] By controlling the on / off of the current flowing through the flash lamp FL using the IGBT 96, the light emission pattern (time waveform of the light emission output) of the flash lamp FL can be freely defined, and the light emission time and light intensity can be freely adjusted. The on / off drive pattern of the IGBT 96 is defined by the pulse width and pulse interval time input from the input unit 33. In other words, by incorporating the IGBT 96 into the drive circuit of the flash lamp FL, the light emission pattern of the flash lamp FL can be freely defined simply by appropriately setting the pulse width and pulse interval time input from the input unit 33.

[0075] Specifically, for example, increasing the ratio of the pulse width time to the pulse interval time input from the input unit 33 increases the current flowing through the flash lamp FL, thereby increasing the light emission intensity. Conversely, decreasing the ratio of the pulse width time to the pulse interval time input from the input unit 33 decreases the current flowing through the flash lamp FL, thereby decreasing the light emission intensity. Furthermore, by appropriately adjusting the ratio of the pulse interval time to the pulse width time input from the input unit 33, the light emission intensity of the flash lamp FL can be maintained constant. Furthermore, by lengthening the total combined time of the pulse width time and pulse interval time input from the input unit 33, current continues to flow through the flash lamp FL for a relatively long period of time, thereby extending the light emission time of the flash lamp FL. The light emission time of the flash lamp FL is appropriately set between 0.1 milliseconds and 100 milliseconds. The maximum temperature reached on the surface of the semiconductor wafer W and the amount of heat input to the semiconductor wafer W are determined by the charging voltage to the capacitor 93 and the waveform of the light emission pattern of the flash lamp FL.

[0076] In this embodiment, the pulse signal applied to the gate of the IGBT 96 is set so that the main irradiation time of the flash lamps FL is 5 milliseconds. The main irradiation time is the time from when the flash lamps FL start to emit light until the surface of the semiconductor wafer W, which is the object to be irradiated, reaches its peak temperature (highest attainable temperature). The peak temperature is, for example, 1000°C.

[0077] As soon as the surface temperature of the semiconductor wafer W reaches the peak temperature, the surface temperature begins to decrease (step S5). FIG. 12 is a diagram showing the change in the surface temperature of the semiconductor wafer W during flash light irradiation. At time t31, the flash lamps FL begin to emit light, and the surface temperature of the semiconductor wafer W rapidly rises from the preheating temperature T1. At time t32, the surface temperature of the semiconductor wafer W reaches the peak temperature T2. The period from time t31 to time t32 is the main irradiation time of the flash lamps FL, which is 5 milliseconds in this embodiment. Note that while the horizontal axis (time axis) in FIG. 11 is in seconds, the horizontal axis in FIG. 12 is in milliseconds, so t31 and t32 in FIG. 12 are displayed superimposed on time t3 in FIG. 11.

[0078] Time t32, when the surface temperature of the semiconductor wafer W reaches peak temperature T2, is also the time when the surface temperature begins to decrease. If the IGBT 96 is completely turned off at time t32 and the current flowing through the flash lamps FL is cut off, the rate at which the surface temperature of the semiconductor wafer W decreases after time t32 is the fastest, as shown by the solid line in Figure 12. On the other hand, if the IGBT 96 alternates between a relatively long off state and a relatively short on state after time t32, the current flowing through the flash lamps FL gradually decreases, the light emission intensity gradually weakens, and the surface temperature of the semiconductor wafer W decreases relatively slowly. The rate at which the surface temperature of the semiconductor wafer W decreases can be adjusted by changing the ratio of the on-state time of the IGBT 96 to the off-state time (i.e., the ratio of the pulse width time to the pulse interval time of the pulse input to the IGBT 96). In the example of Figure 12, the rate at which the surface temperature of the semiconductor wafer W decreases increases in the order of the two-dot chain line, dotted line, dashed line, and solid line.

[0079] In this embodiment, the rate of temperature decrease of the surface temperature of the semiconductor wafer W after time t32 is set to be equal to or greater than 8°C / millisecond and equal to or less than 300°C / millisecond. This temperature decrease rate is several thousand times the temperature decrease rate in a typical RTA (Rapid Thermal Anneal). The surface temperature of the semiconductor wafer W, which is rapidly increased and then decreased, may be measured by the upper radiation thermometer 25. The upper radiation thermometer 25 measures the surface temperature of the semiconductor wafer W at extremely short sampling intervals, and therefore is able to follow any sudden changes in the surface temperature of the semiconductor wafer W during flash light irradiation.

[0080] Thereafter, the halogen lamps HL are also turned off. As a result, the temperature of the semiconductor wafer W is rapidly decreased from the preheating temperature T1 (FIG. 11). The temperature of the semiconductor wafer W is measured by the lower radiation thermometer 20 during the decrease, and the measurement result is transmitted to the control unit 3. The control unit 3 monitors, based on the measurement result of the lower radiation thermometer 20, whether the temperature of the semiconductor wafer W has decreased to a predetermined temperature. After the temperature of the semiconductor wafer W has decreased to or below the predetermined temperature, the pair of transfer arms 11 of the transfer mechanism 10 again move horizontally from the retracted position to the transfer operation position and rise, causing the lift pins 12 to protrude from the upper surface of the susceptor 74 and receive the heat-treated semiconductor wafer W from the susceptor 74. Next, the transfer opening 66, which had been closed by the gate valve 185, is opened, and the semiconductor wafer W placed on the lift pins 12 is removed by a transfer robot external to the apparatus, completing the heat treatment of the semiconductor wafer W in the heat treatment apparatus 1 (step S6).

[0081] In this embodiment, a flash light is irradiated from a flash lamp FL onto the surface of a semiconductor wafer W on which a hafnium oxide-based film 103 has been formed, raising the surface temperature to a peak temperature T2 in one second or less, and then the surface temperature is lowered at a rate of 8°C / millisecond to 300°C / millisecond. The hafnium oxide-based film 103 has many crystalline phases, but the stable phase is orthorhombic in the high-temperature range near the peak temperature T2. That is, by raising the surface temperature of the semiconductor wafer W to the peak temperature T2 by irradiating the flash light, the hafnium oxide-based film 103 changes from an amorphous state to an orthorhombic state, and by the time the surface temperature reaches the peak temperature T2 (time t32 in FIG. 12 ), the crystalline structure of the hafnium oxide-based film 103 is orthorhombic. If the hafnium oxide-based film 103 is then slowly lowered, the orthorhombic state is lost and the phase changes to a stable phase that does not have ferroelectricity.

[0082] In this embodiment, the surface temperature of the semiconductor wafer W is lowered from the peak temperature T2 at a temperature lowering rate of 8°C / msec or more and 300°C / msec or less. Lowering the surface temperature of the semiconductor wafer W at such a significantly higher temperature lowering rate compared to RTA and the like results in cooling the semiconductor wafer W while maintaining its crystalline structure without changing its orthorhombic crystal structure. In other words, the orthorhombic crystal structure is not lost as the temperature is lowered, and the hafnium oxide-based film 103 maintains its orthorhombic crystal structure exhibiting ferroelectricity after the temperature is lowered. As a result, the hafnium oxide-based film 103 can exhibit significant remanent polarization characteristics even after the temperature is lowered. Furthermore, by increasing the temperature lowering rate, the total amount of heat input to the semiconductor wafer W can be reduced. In some cases, wiring and transistors may be formed on the semiconductor wafer W before the hafnium oxide-based film 103 is formed. Even if flash light is irradiated on such a semiconductor wafer W after the wiring formation, the amount of heat input associated with flash lamp annealing is small, preventing a large thermal load from being applied to the pre-formed wiring and transistors, thereby degrading their characteristics.

[0083] FIG. 13 shows the correlation between the temperature-decreasing rate and the remanent polarization characteristics. The remanent polarization of the hafnium oxide-based film 103 cooled at the temperature-decreasing rates shown in FIG. 12 by the two-dot chain line, dotted line, single-dot chain line, and solid line is shown in FIG. 13 by a triangle, square, cross, and circle, respectively. As shown in FIG. 13, the remanent polarization of the hafnium oxide-based film 103 after cooling tends to increase as the temperature-decreasing rate increases. This is presumably because the orthorhombic crystal structure exhibiting ferroelectricity is more easily maintained as the temperature-decreasing rate increases. For this reason, in this embodiment, the surface of the semiconductor wafer W heated to a peak temperature T2 by flash light irradiation is cooled at a high temperature-decreasing rate of 8°C / millisecond or more and 300°C / millisecond or less. This allows the hafnium oxide-based film 103 to exhibit greater remanent polarization characteristics.

[0084] In flash lamp annealing, unless additional light irradiation is performed by turning the IGBT 96 on and off, the shorter the main irradiation time of the flash lamp FL, the higher the temperature drop rate. Therefore, based on the trend shown in Figure 13, it would seem that the shorter the main irradiation time, the greater the remanent polarization. However, if the main irradiation time is excessively short, it becomes difficult to form orthorhombic crystals from the amorphous phase during flash light irradiation, and even if the temperature is lowered at a high rate, a large remanent polarization cannot be obtained. Taking these factors into consideration, a more preferable temperature drop rate for the surface temperature of the semiconductor wafer W is between 17°C / millisecond and 182°C / millisecond.

[0085] Although the above describes an embodiment of the present invention, various modifications can be made to the present invention without departing from the spirit and scope of the present invention. For example, in the above embodiment, helium gas may be supplied to the heat treatment space 65 through the gas supply holes 81 when the surface temperature of the semiconductor wafer W is being lowered. By spraying helium gas, which has a high cooling capacity, onto the surface of the semiconductor wafer W heated to peak temperature T2 by flash light irradiation, the rate at which the surface temperature is lowered can be further increased. This allows the hafnium oxide-based film 103 to exhibit significant remanent polarization characteristics. The supply flow rate of helium gas is preferably 1 liter / minute or more and 100 liters / minute or more. In addition to the gas supply holes 81, a dedicated nozzle for spraying helium gas onto the surface of the semiconductor wafer W may be installed in the chamber 6.

[0086] Furthermore, in the above embodiment, the additive element to the hafnium oxide-based film 103 is aluminum, but this is not limited to this and other elements such as silicon, zirconium, lanthanum, etc. In particular, when the additive element is aluminum or silicon, the temperature required to form orthorhombic crystals during flash heating is relatively high, and the effect of cooling at a high cooling rate can be easily obtained, which is suitable for the technology according to the present invention.

[0087] Furthermore, in the above embodiment, the surface temperature of the semiconductor wafer W may be increased at a two-stage temperature increase rate during flash light irradiation. Specifically, the flash lamps FL begin to emit light, and the surface temperature of the semiconductor wafer W is increased from the preheating temperature T1 to an intermediate temperature at a first temperature increase rate. Subsequently, the light emission intensity of the flash lamps FL is increased, and the surface temperature of the semiconductor wafer W is increased from the intermediate temperature to a peak temperature T2 at a second temperature increase rate that is higher than the first temperature increase rate. In this way, by increasing the surface temperature of the semiconductor wafer W at a two-stage temperature increase rate, the amount of heat imparted to the surface of the semiconductor wafer W can be reduced compared to when the temperature is increased at a single temperature increase rate, and the rate at which the surface temperature drops can be increased.

[0088] In the above embodiment, millisecond annealing is performed by irradiating the surface of the semiconductor wafer W with flash light from the flash lamps FL to heat the surface for one second or less, but this is not limiting, and laser annealing may be performed instead of flash lamp annealing. Laser annealing is also millisecond annealing in which laser light is irradiated onto the surface of the semiconductor wafer W to heat the surface for one second or less.

[0089] Furthermore, the thin film formed on the semiconductor wafer W is not limited to the hafnium oxide-based film 103, but may be any thin film that exhibits ferroelectricity when in a metastable phase. Examples of such thin films include thin films based on barium titanate (BaTiO3) in addition to hafnium oxide.

[0090] Furthermore, in the above embodiment, the flash heating unit 5 is provided with 30 flash lamps FL, but this is not limited to this and the number of flash lamps FL can be any number. Furthermore, the flash lamps FL are not limited to xenon flash lamps and may be krypton flash lamps. Furthermore, the number of halogen lamps HL provided in the halogen heating unit 4 is not limited to 40 and can be any number.

[0091] Furthermore, in the above embodiment, the semiconductor wafer W is preheated using a filament-type halogen lamp HL as a continuously lit lamp that emits light continuously for one second or more, but this is not limited to this, and preheating may be performed using a discharge arc lamp (e.g., a xenon arc lamp) or an LED lamp as a continuously lit lamp instead of the halogen lamp HL. [Industrial Applicability]

[0092] The technique according to the present invention can be suitably applied to the manufacture of ferroelectric random access memory (FeRAM) using hafnium oxide-based materials. [Explanation of symbols]

[0093] 1. Heat treatment equipment 3. Control Unit 4 Halogen heating section 5 Flash heating section 6 chambers 7 Holding part 10 Transfer mechanism 20 Lower radiation thermometer 25 Upper radiation thermometer 31 Pulse Generator 32 Waveform setting section 33 Input section 63 Upper chamber window 64 Lower chamber window 65 Heat Treatment Space 74 Susceptor 93 Capacitor 96 IGBT 103 Hafnium oxide based film FL flash lamp HL halogen lamp W Semiconductor wafer

Claims

1. A heat treatment method for heating a substrate having a hafnium oxide base film formed thereon by irradiating the substrate with flash light, comprising: a temperature raising step of irradiating a surface of the substrate with flash light from a flash lamp to raise the temperature of the surface to a peak temperature in 1 second or less from the start of irradiation; a temperature decreasing step of decreasing the temperature of the surface of the substrate at a temperature decreasing rate of 8°C / millisecond or more and 300°C / millisecond or less; A heat treatment method comprising:

2. The heat treatment method according to claim 1, The heat treatment method, wherein the hafnium oxide-based film is doped with silicon or aluminum.

3. The heat treatment method according to claim 1, The heat treatment method includes supplying helium to the surface of the substrate in the temperature lowering step.

4. The heat treatment method according to claim 3, The heat treatment method, wherein the helium supply flow rate is 1 liter / minute or more and 100 liters / minute or less.

5. The heat treatment method according to claim 1, The heat treatment method, wherein the hafnium oxide-based film has a thickness of 25 nm or less.

6. The heat treatment method according to claim 1, Furthermore, a heat treatment method is used in which the substrate on which the wiring has been formed is irradiated with flash light.

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