Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing occurrence of breakdown in a sense element.SOLUTION: A semiconductor device includes a first electrode, a main element region, a fifth semiconductor region of a first conductivity type, a sense element region, an eighth semiconductor region of the first conductivity type, a ninth semiconductor region of the first conductivity type, a second electrode, a third electrode, and a fourth electrode. The fifth semiconductor region is provided around the main element region. The sense element region is separated from the main element region and has an area on the first surface smaller than that of the main element region. The eighth semiconductor region is provided around the sense element region on the first surface. The ninth semiconductor region is provided between the main element region and the sense element region. The ninth semiconductor region is electrically connected to the eighth semiconductor region. The fourth electrode is provided on the ninth semiconductor region via an insulating layer, and is electrically connected to the first gate electrode of the main element region and the second gate electrode of the sense element region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Some semiconductor devices include a sense element for detecting the current in addition to a main element through which the current mainly flows. For such semiconductor devices, there is a demand for a technique that can suppress the occurrence of breakdown in the sense element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-112212 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device that can suppress the occurrence of breakdown in a sense element. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a main element region, a fifth semiconductor region of a first conductivity type, a sense element region, an eighth semiconductor region of the first conductivity type, a ninth semiconductor region of the first conductivity type, a second electrode, a third electrode, and a fourth electrode. The main element region includes a first semiconductor region of the first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, and a first gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided on the third semiconductor region. The first gate electrode faces the third semiconductor region via a first gate insulating layer. The fifth semiconductor region is provided around the main element region in a first plane perpendicular to a first direction extending from the first electrode toward the first semiconductor region. The sense element region includes the first semiconductor region, the second semiconductor region, a sixth semiconductor region of a first conductivity type, a seventh semiconductor region of a second conductivity type, and a second gate electrode. The sixth semiconductor region is provided on the second semiconductor region. The seventh semiconductor region is provided on the sixth semiconductor region. The second gate electrode faces the sixth semiconductor region via a second gate insulating layer. The sense element region is separated from the main element region and has an area on the first surface smaller than that of the main element region. The eighth semiconductor region is provided around the sense element region on the first surface. The ninth semiconductor region is provided between the main element region and the sense element region. The ninth semiconductor region is located on the second semiconductor region and electrically connected to the eighth semiconductor region. The second electrode is provided on the main element region and electrically connected to the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region. The third electrode is provided on the sense element region and electrically connected to the sixth semiconductor region, the seventh semiconductor region, and the eighth semiconductor region. The fourth electrode is provided on the ninth semiconductor region via an insulating layer, and is electrically connected to the first gate electrode and the second gate electrode. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II of FIG. [Figure 3] FIG. 3 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 4] FIG. 4 is a cross-sectional view showing a semiconductor device according to the third embodiment. [Figure 5] FIG. 5 is a cross-sectional view showing a semiconductor device according to the fourth embodiment. [Figure 6] FIG. 6 is a cross-sectional view showing an example of a cross section taken along line VI-VI in FIG. [Figure 7] 7(a) and 7(b) are cross-sectional views showing another example of the VI-VI cross section. [Figure 8] FIG. 8 is a cross-sectional view showing a semiconductor device according to the fifth embodiment. [Figure 9] 9(a) to 9(c) are enlarged cross-sectional views of a part of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and each drawing, elements similar to those already described are designated by the same reference numerals, and detailed description will be omitted as appropriate. In the following description and drawings, n + , n - and p +The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation with neither "+" nor "-" attached, and a notation with "-" indicates a relatively lower impurity concentration than a notation with neither attached. When both p-type and n-type impurities are contained in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other. In each of the embodiments described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] (First embodiment) Fig. 1 is a plan view showing a semiconductor device according to a first embodiment, and Fig. 2 is a cross-sectional view taken along line II-II of Fig. 1. 1 and 2, the semiconductor device 100 according to the first embodiment includes a semiconductor layer 10, a collector electrode 31 (first electrode), an emitter electrode 32 (second electrode), a sense emitter electrode 33 (third electrode), and a gate pad 34 (fourth electrode). + type (first conductivity type) collector region 11 (first semiconductor region), n - a p-type (second conductivity type) base region 12 (second semiconductor region), a p-type base region 13 (third semiconductor region), + emitter region 14 (fourth semiconductor region), p + a p-type guard ring region 15 (fifth semiconductor region), a p-type base region 16 (sixth semiconductor region), + emitter region 17 (seventh semiconductor region), p + Guard ring region 18 (eighth semiconductor region), p + The semiconductor device 100 includes a shaped semiconductor region 19 (ninth semiconductor region), a gate electrode 21 (first gate electrode), and a gate electrode 22 (second gate electrode). The semiconductor device 100 is an insulated gate bipolar transistor (IGBT).

[0009] In the description of the embodiment, an XYZ orthogonal coordinate system is used. +The direction toward the collector region 11 is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and orthogonal to each other are defined as the X direction (second direction) and the Y direction (third direction). + The direction toward the collector region 11 is called "up" and the opposite direction is called "down." These directions are the direction of the collector electrode 31 and the p + The shape is based on the relative position of the collector region 11 and is independent of the direction of gravity.

[0010] 1, an emitter electrode 32, a sense emitter electrode 33, and a gate pad 34 are provided on the upper surface of the semiconductor device 100. The emitter electrode 32, the sense emitter electrode 33, and the gate pad 34 are spaced apart from each other.

[0011] The semiconductor layer 10 includes a main element region R1 and a sense element region R2. In FIG. 1, the main element region R1 and the sense element region R2 are indicated by two-dot chain lines. The main element region R1 and the sense element region R2 are separated from each other in a direction perpendicular to the Z direction. The area of ​​the sense element region R2 in the XY plane (first plane) is smaller than the area of ​​the main element region R1 in the XY plane. The emitter electrode 32 is located on the main element region R1. The sense emitter electrode 33 is located on the sense element region R2.

[0012] 2, a collector electrode 31 is provided on the lower surface of the semiconductor device 100. The collector electrode 31 is located below the main element region R1 and the sense element region R2.

[0013] p + The collector region 11 is provided on the collector electrode 31 and is electrically connected to the collector electrode 31. - The base region 12 is p + The collector region 11 is provided on the substrate. + collector region 11 and n - The base region 12 is provided in both the main element region R1 and the sense element region R2.

[0014] The p-type base region 13 is formed in the main element region R1 as an n - The base region 12 is provided on the substrate 11. + The p-type emitter region 14 is provided on the p-type base region 13. The gate electrode 21 faces the p-type base region 13 in the X direction via a gate insulating layer 21a (first gate insulating layer).

[0015] The emitter electrode 32 is connected to the p-type base region 13, + The p-type base region 13 and the n-type emitter region 14 are located on the gate electrode 21. + The gate electrode 21 is electrically connected to the emitter region 14. The gate electrode 21 and the emitter electrode 32 are electrically separated by a gate insulating layer 21a.

[0016] In the main element region R1, the p-type base regions 13 and the gate electrodes 21 are alternately arranged in the X direction. Each p-type base region 13 and each gate electrode 21 extends in the Y direction. + The p-type emitter regions 14 are provided on the plurality of p-type base regions 13, respectively. + The emitter region 14 may be omitted. A part of the gate electrode 21 may be electrically connected to the emitter electrode 32.

[0017] p + The guard ring region 15 is provided around the main element region R1 in the XY plane. + The p-type impurity concentration of the guard ring region 15 is higher than the p-type impurity concentration of the p-type base region 13. + The lower end of the p-type guard ring region 15 is located lower than the lower end of the p-type base region 13. + The lower end of the guard ring region 15 may be located below the lower end of the gate electrode 21 .

[0018] The p-type base region 16 is formed in the sense element region R2 as follows: - The base region 12 is provided on the substrate 11.+ The p-type emitter region 17 is provided on the p-type base region 16. The gate electrode 22 faces the p-type base region 16 in the X direction via a gate insulating layer 22a (second gate insulating layer).

[0019] The sense emitter electrode 33 is connected to the p-type base region 16, + The p-type base region 16 and the n-type emitter region 17 are located on the gate electrode 22. + The gate electrode 22 and the sense emitter electrode 33 are electrically connected to the gate insulating layer 22a.

[0020] In the sense element region R2, the p-type base regions 16 and the gate electrodes 22 are alternately arranged in the X direction. Each p-type base region 16 and each gate electrode 22 extends in the Y direction. Alternatively, the p-type base regions 16 and the gate electrodes 22 may be alternately arranged in the Y direction, and each p-type base region 16 and each gate electrode 22 may extend in the X direction. + The n-type emitter regions 17 are provided on the plurality of p-type base regions 16. + The emitter region 17 may be omitted, and a part of the gate electrode 22 may be electrically connected to the sense emitter electrode 33 .

[0021] p + The guard ring region 18 is provided around the sense element region R2 in the XY plane. + The p-type impurity concentration of the guard ring region 18 is higher than the p-type impurity concentration of the p-type base region 16. + The lower end of the p-type guard ring region 18 is located lower than the lower end of the p-type base region 16. + The lower end of the guard ring region 18 may be located below the lower end of the gate electrode 22 .

[0022] p + The semiconductor region 19 is provided between the main element region R1 and the sense element region R2. + The semiconductor region 19 is- Located on the base region 12, p + It is electrically connected to the guard ring region 18. + The p-type impurity concentration in the p-type semiconductor region 19 is + The p-type impurity concentration may be the same as that in the guard ring region 18. + The semiconductor region 19 is p + It is away from the guard ring area 15. + Shape guard ring region 15 and p + Between the semiconductor region 19 and the n - A portion of the shaped base region 12 is provided.

[0023] The gate pad 34 is p + The gate pad 34 is provided on the insulating layer 23a on the semiconductor region 19. The gate pad 34 is electrically connected to the plurality of gate electrodes 21 and the plurality of gate electrodes 22.

[0024] As described above, the area of ​​the sense element region R2 in the XY plane is smaller than the area of ​​the main element region R1 in the XY plane. Therefore, the area of ​​the sense emitter electrode 33 in the XY plane is smaller than the area of ​​the emitter electrode 32 in the XY plane. The area of ​​the gate pad 34 in the XY plane may be smaller than the area of ​​the emitter electrode 32 in the XY plane. The number of gate electrodes 22 provided in the sense element region R2 is smaller than the number of first gate electrodes 21 provided in the main element region R1.

[0025] The operation of the semiconductor device 100 will now be described. When a voltage equal to or greater than the threshold is applied to the gate electrodes 21 and 22, a channel (inversion layer) is formed in the p-type base region 13 and the p-type base region 16. When a channel is formed with a positive voltage applied to the collector electrode 31 with respect to the emitter electrode 32 and the sense emitter electrode 33, the semiconductor device 100 is turned on. Electrons pass through the channel and + Shape emitter region 14 to n - The holes are injected into the p-type base region 12. + Collector region 11 to n- implanted into the base region 12. - Conductivity modulation occurs in the base region 12, and n - The resistance of the p-type base region 12 decreases. Thereafter, when the voltage applied to the gate electrodes 21 and 22 becomes lower than the threshold voltage, the channels in the p-type base regions 13 and 16 disappear, and the semiconductor device 100 enters an off state.

[0026] Except for the area, the structure of the sense element region R2 is substantially the same as the structure of the main element region R1. Therefore, when the semiconductor device 100 is in the on state, a current corresponding to the area ratio of the main element region R1 to the sense element region R2 flows through the main element region R1 and the sense element region R2, respectively. The current flowing through the sense element region R2 is smaller than the current flowing through the main element region R1. By detecting the current flowing through the sense element region R2, the current flowing through the main element region R1 can be calculated. The sense element region R2 is provided to monitor the current flowing through the main element region R1.

[0027] The area of ​​the sense element region R2 may be sufficiently smaller than the area of ​​the main element region R1. For example, the area of ​​the main element region R1 is designed to be 3000 to 5000 times the area of ​​the sense element region R2.

[0028] An example of the material of each component will be described. The semiconductor layer 10 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony is used as an n-type impurity. Boron is used as a p-type impurity. The gate electrode 21 and the gate electrode 22 include a semiconductor material such as polysilicon. The polysilicon may be doped with n-type impurities or p-type impurities. The gate insulating layer 21a, the gate insulating layer 22a, and the insulating layer 23a include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The collector electrode 31, the emitter electrode 32, the sense-emitter electrode 33, and the gate pad 34 include metal materials such as aluminum, titanium, or tungsten. As shown in FIG. 2, the gate pad 34 may be composed of a semiconductor portion 34s including polysilicon and a metal portion 34m including a metal. The polysilicon of the semiconductor portion 34s may be doped with n-type impurities or p-type impurities. The semiconductor material contained in the semiconductor portion 34s may be the same as the semiconductor material contained in the gate electrode 21 or the gate electrode 22.

[0029] An example of the impurity concentration of each semiconductor region will be described. p + The p-type impurity concentration in the collector region 11 is 1.0×10 15 atom / cm 3 Over 1.0 x 10 17 atom / cm 3 The following is true: n - The n-type impurity concentration in the base region 12 is 5.0×10 13 atom / cm 3 Over 5.0 x 10 14 atom / cm 3 The p-type impurity concentration in each of the p-type base regions 13 and 16 is 1.0×10 15 atom / cm 3 Over 1.0 x 10 16 atom / cm 3 The following is true: n + emitter region 14 and n + The n-type impurity concentration in each of the emitter regions 17 is 1.0×10 18atom / cm 3 Over 1.0 x 10 21 atom / cm 3 The following is true: + Shape guard ring area 15, p + shaped guard ring region 18, and p + The p-type impurity concentration in the p-type semiconductor region 19 is 5.0×10 17 atom / cm 3 Over 5.0 x 10 18 atom / cm 3 The following is true: + The p-type impurity concentration and p + The p-type impurity concentration in the p-type semiconductor region 19 may be the same, + Shape guard ring region 18 and p + The semiconductor region 19 may be integrally formed.

[0030] The advantages of the first embodiment will be described. Electrostatic discharge (ESD) may occur in a semiconductor device or an electrical circuit to which the semiconductor device is connected. When ESD occurs, a large voltage is temporarily applied to the main element region R1 and the sense element region R2. This may result in destruction of insulating layers such as the gate insulating layer 22a. The inventors of the present application have found a correlation between the area of ​​the element and destruction by ESD. In other words, the smaller the area of ​​the element, the more likely destruction by ESD is. As described above, the area of ​​the sense element region R2 is smaller than the area of ​​the main element region R1. Therefore, destruction by ESD is more likely to occur in the sense element region R2 than in the main element region R1.

[0031] In the first embodiment, a p + A semiconductor region 19 is provided. + The semiconductor region 19 is provided to improve the breakdown voltage of the semiconductor device 100. + The provision of the semiconductor region 19 suppresses electric field concentration in the region directly below the gate pad 34, thereby reducing the possibility of damage to the semiconductor device 100. The gate pad 34 is connected to the p +The semiconductor region 19 faces the p + An insulating film capacitance exists between the semiconductor region 19 and the gate pad 34. In the first embodiment, + The semiconductor region 19 is p + It is electrically connected to the guard ring region 18. + The semiconductor region 19 is p + When connected to the gate guard ring region 18, the insulating film capacitance of the insulating layer 23a is added to the insulating film capacitance of the gate insulating layer 22a. As a result, when ESD occurs, it is possible to suppress the occurrence of breakdown in the sense element region R2. According to the first embodiment, it is possible to increase the ESD tolerance of the sense element region R2.

[0032] (Second embodiment) FIG. 3 is a cross-sectional view showing a semiconductor device according to the second embodiment. The semiconductor device 200 according to the second embodiment shown in FIG. 3 has a p + The p-type impurity concentration in the p-type semiconductor region 19 is different. + The p-type impurity concentration in the p-type semiconductor region 19 is + The concentration of the p-type impurity in the guard ring region 18 is lower than that in the p-type impurity in the guard ring region 18 .

[0033] As shown in FIG. 3, during operation of the semiconductor device 200, holes injected into the region below the gate pad 34 are p + The electrons pass through the semiconductor region 19 and flow toward the sense emitter electrode 33. + Hole current may concentrate in the guard ring region 18, possibly causing breakdown in the sense element region R2.

[0034] According to the second embodiment, p + The low concentration of p-type impurities in the p-type semiconductor region 19 allows + The electrical resistance to holes in the semiconductor region 19 can be increased. + This reduces the hole current flowing in the guard ring region 18, thereby suppressing the occurrence of breakdown in the sense element region R2.

[0035] p + The lower the p-type impurity concentration in the p-type semiconductor region 19, the + Through the semiconductor region 19 + The hole current flowing into the guard ring region 18 can be reduced. + If the p-type impurity concentration in the p-type semiconductor region 19 is excessively low, the insulating film capacitance of the insulating layer 23a is less likely to contribute to the insulating film capacitance of the gate insulating layer 22a. + The p-type impurity concentration in the p-type semiconductor region 19 is preferably equal to or higher than the p-type impurity concentration in the p-type base region 16 .

[0036] (Third embodiment) FIG. 4 is a cross-sectional view showing a semiconductor device according to the third embodiment. The semiconductor device 300 according to the third embodiment shown in FIG. 4 has a p + The semiconductor device 300 has a p + The semiconductor region 19 includes a first portion 19a and a second portion 19b. The first portion 19a is located directly below the gate pad 34. The second portion 19b is located between the first portion 19a and the p + The second portion 19b is located between the first portion 19a and the gate electrode 32. The p-type impurity concentration in the second portion 19b is higher than the p-type impurity concentration in the first portion 19a. For example, the p-type impurity concentration in the second portion 19b is designed to be 10 to 20 times the p-type impurity concentration in the first portion 19a. A part of the emitter electrode 32 is provided on the second portion 19b, and the second portion 19b is electrically connected to the emitter electrode 32.

[0037] According to the third embodiment, by providing the second portion 19b having a high concentration of p-type impurities, + The holes flowing through the semiconductor region 19 can be discharged from the second portion 19b. + This reduces the hole current flowing in the guard ring region 18, thereby suppressing the occurrence of breakdown in the sense element region R2.

[0038] (Fourth embodiment) FIG. 5 is a cross-sectional view showing a semiconductor device according to the fourth embodiment. 5 is different from the semiconductor device 100 according to the first embodiment in the structure of the gate pad 34. In the semiconductor device 400, a part of the gate pad 34 is connected to the p + The semiconductor region 19 faces the semiconductor region 19 .

[0039] FIG. 6 is a cross-sectional view showing an example of a cross section taken along line VI-VI in FIG. As shown in FIG. 6, the gate pad 34 includes a first extending portion 34a extending in the Y direction. A plurality of first extending portions 34a are provided in the X direction. The plurality of first extending portions 34a are spaced apart from one another. Each of the first extending portions 34a is connected to the p-type insulating layer 23a in the X direction via the insulating layer 23a. + The semiconductor region 19 faces the semiconductor region 19 .

[0040] 7(a) and 7(b) are cross-sectional views showing another example of the VI-VI cross section. As shown in FIG. 7(a), the gate pad 34 may include a first extending portion 34a extending in the X direction and a second extending portion 34b extending in the Y direction. The first extending portions 34a are spaced apart from one another in the Y direction. A plurality of second extending portions 34b are provided between adjacent first extending portions 34a in the Y direction. The first extending portions 34a and the second extending portions 34b are arranged in a lattice pattern, and p is provided between these extending portions. + The semiconductor regions 19 are arranged in a staggered pattern.

[0041] In the example shown in FIG. 7(b), the first extending portion 34a extends in the Y direction, and the second extending portion 34b extends in the X direction. The multiple first extending portions 34a are spaced apart from one another in the X direction. Multiple second extending portions 34b are provided between adjacent first extending portions 34a in the X direction. As shown in FIGS. 7(a) and 7(b), the arrangement of the first extending portions 34a and the second extending portions 34b can be changed as appropriate, as long as the first extending portions 34a and the second extending portions 34b extend in directions perpendicular to each other.

[0042] According to the fourth embodiment, compared to the first embodiment, the gate pad 34 and p + In particular, according to the structure shown in FIG. 7(a) or 7(b), the gate pad 34 and the p + This further increases the area facing the insulating semiconductor region 19. This further increases the insulating film capacitance of the insulating layer 23a, making it possible to further suppress the occurrence of damage due to ESD in the sense element region R2.

[0043] (Fifth embodiment) Fig. 8 is a cross-sectional view showing a semiconductor device according to the fifth embodiment, and Figs. 9(a) to 9(c) are enlarged cross-sectional views of a part of Fig. 8. 8 is different from the semiconductor device 100 according to the first embodiment in the thickness of the insulating layer 23a. In the semiconductor device 500, the thickness of the insulating layer 23a is thinner than the thickness of the gate insulating layer 21a and the thickness of the gate insulating layer 22a.

[0044] 9(a) is an enlarged cross-sectional view of the insulating layer 23a and its vicinity. FIG. 9(b) is an enlarged cross-sectional view of the gate insulating layer 21a and its vicinity. FIG. 9(c) is an enlarged cross-sectional view of the gate insulating layer 22a and its vicinity. As shown in FIG. 9(a), the thickness T3 of the insulating layer 23a is p + 9B, the thickness T1 of the gate insulating layer 21a is expressed as the distance in the Z direction between the semiconductor region 19 and the gate pad 34. + The thickness T2 of the gate insulating layer 22a is expressed as the distance in the X direction between the guard ring region 15 and the gate electrode 21. As shown in FIG. 9(c), the thickness T2 of the gate insulating layer 22a is expressed as p + The thickness T3 is represented by the distance in the X direction between the guard ring region 18 and the gate electrode 22. In the fifth embodiment, the thickness T3 is smaller than the thickness T1 and smaller than the thickness T2.

[0045] According to the fifth embodiment, the thickness T3 is small, so that p +This can increase the capacitance of the insulating film between the insulating film region 19 and the gate pad 34. The increased capacitance of the insulating film can further suppress the occurrence of damage due to ESD in the sense element region R2.

[0046] Instead of reducing the thickness T3, the dielectric constant of the insulating material of the insulating layer 23a may be made higher than the dielectric constant of the insulating material of the gate insulating layer 21a or the gate insulating layer 22a. + This can increase the capacitance of the insulating film between the semiconductor region 19 and the gate pad 34. Alternatively, the thickness T3 may be reduced and an insulating material with a large relative dielectric constant may be used for the insulating layer 23a.

[0047] The above-described embodiments can be combined as appropriate. For example, the second or third embodiment can be combined with the fourth or fifth embodiment to increase the insulating film capacitance. The structures of the second to fifth embodiments can also be combined.

[0048] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed using SCM. Furthermore, the impurity concentration in each semiconductor region can be measured using, for example, secondary ion mass spectrometry (SIMS).

[0049] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0050] 10: semiconductor layer, 11: p + Shape collector area, 12:n - 13: p-type base region; 14: n-type base region + Shape emitter area, 15:p + 16: p-type guard ring region, 17: n-type base region + Shape emitter area, 18:p + Shape guard ring area, 19:p + semiconductor region, 19a: first portion, 19b: second portion, 21: gate electrode, 21a: gate insulating layer, 22: gate electrode, 22a: gate insulating layer, 23a: insulating layer, 31: collector electrode, 32: emitter electrode, 33: sense emitter electrode, 34: gate pad, 34a: first extension portion, 34b: second extension portion, 34m: metal portion, 34s: semiconductor portion, 100 to 500: semiconductor device, R1: main element region, R2: sense element region, T1 to T3: thicknesses

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a fourth semiconductor region of the second conductivity type provided on the third semiconductor region; and a first gate electrode facing the third semiconductor region via a first gate insulating layer; a main element region including: a fifth semiconductor region of the first conductivity type provided around the main element region in a first plane perpendicular to a first direction from the first electrode toward the first semiconductor region; the first semiconductor region; the second semiconductor region; a sixth semiconductor region of the first conductivity type provided on the second semiconductor region; a seventh semiconductor region of the second conductivity type provided on the sixth semiconductor region; and a second gate electrode facing the sixth semiconductor region via a second gate insulating layer; a sense element region separated from the main element region and having an area on the first surface smaller than that of the main element region; an eighth semiconductor region of the first conductivity type provided around the sense element region on the first surface; a ninth semiconductor region of the first conductivity type provided between the main element region and the sense element region, positioned on the second semiconductor region, and electrically connected to the eighth semiconductor region; a second electrode provided on the main element region and electrically connected to the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; a third electrode provided on the sense element region and electrically connected to the sixth semiconductor region, the seventh semiconductor region, and the eighth semiconductor region; a fourth electrode provided on the ninth semiconductor region via an insulating layer and electrically connected to the first gate electrode and the second gate electrode; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein a concentration of the impurity of the first conductivity type in said ninth semiconductor region is lower than a concentration of the impurity of the first conductivity type in said eighth semiconductor region.

3. 3. The semiconductor device according to claim 2, wherein the impurity concentration of the first conductivity type in said ninth semiconductor region is equal to or higher than the impurity concentration of the first conductivity type in said sixth semiconductor region.

4. The ninth semiconductor region is a first portion located directly below the fourth electrode; a second portion located between the first portion and the eighth semiconductor region in a direction perpendicular to the first direction and having a higher impurity concentration of the first conductivity type than the first portion; The semiconductor device according to claim 1 , comprising:

5. The semiconductor device according to claim 4 , wherein the second portion is electrically connected to the third electrode.

6. The semiconductor device according to claim 1 , wherein a portion of said fourth electrode faces said ninth semiconductor region via said insulating layer in a direction perpendicular to said first direction.

7. The portion of the fourth electrode is a first extension portion extending in a second direction perpendicular to the first direction; a second extending portion extending in a third direction perpendicular to the first direction and the second direction; Including, a plurality of the first extending portions are provided in the third direction, The semiconductor device according to claim 6 , wherein a plurality of the second extending portions are provided in the second direction between the first extending portions adjacent to each other in the third direction.

8. The semiconductor device according to claim 1 , wherein the thickness of said insulating layer is smaller than the thickness of said second gate insulating layer.

9. The semiconductor device according to claim 1 , wherein the dielectric constant of the insulating material contained in said insulating layer is higher than the dielectric constant of the insulating material contained in said second gate insulating layer.

10. 10. The semiconductor device according to claim 1, wherein the area of ​​said main element region on said first surface is 3000 times or more and 5000 times or less the area of ​​said sense element region on said first surface.

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