Semiconductor device

Abstract

To provide a semiconductor device with improved reliability.SOLUTION: According to example embodiments, a semiconductor device may include a substrate, a first channel pattern and a second channel pattern on the substrate and spaced apart from each other, an insulating structure between the first channel pattern and the second channel pattern, a gate structure surrounding at least a portion of the first channel pattern, the second channel pattern, and the insulating structure, and a source / drain pattern on both sides of each of the first channel pattern and the second channel pattern. The insulating structure may include a first buried insulating layer between the first channel pattern and the second channel pattern and extending in a first direction, and a second buried insulating layer between the first buried insulating layer and the first channel pattern, the second buried insulating layer being spaced apart from the first buried insulating layer in the first direction.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices. [Background technology]

[0002] A semiconductor is a material that is intermediate between a conductor and an insulator and that conducts electricity under certain conditions. Various semiconductor devices, such as memory devices, can be manufactured using such semiconductor materials. These semiconductor devices can be used in a variety of electronic devices.

[0003] As the electronics industry advances, the demands placed on the characteristics of semiconductor devices are increasing. For example, there are increasing demands for higher reliability, higher speed, and / or more functionality. To meet these demands, the structures within semiconductor devices are becoming increasingly complex and integrated. As transistor sizes decrease, coupling occurs between devices, which can reduce the operating speed and reliability of semiconductor devices. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor element with improved reliability. [Means for solving the problem]

[0005] In order to achieve the above-mentioned object, a semiconductor device according to one embodiment of the present invention includes a substrate, a first channel pattern and a second channel pattern located on the substrate and spaced apart from each other, an insulating structure located between the first channel pattern and the second channel pattern, a gate structure surrounding the first channel pattern, the second channel pattern, and at least a portion of the insulating structure, and source / drain patterns located on both sides of each of the first channel pattern and the second channel pattern, wherein the insulating structure includes a first buried insulating layer located between the first channel pattern and the second channel pattern and extending in a first direction, and a second buried insulating layer located between the first buried insulating layer and the first channel pattern, and portions of the second buried insulating layer are arranged spaced apart from each other in the first direction.

[0006] In order to achieve the above object, according to another aspect of the present invention, a semiconductor device includes a substrate, a first lower pattern and a second lower pattern located on the substrate and spaced apart from each other, a first channel pattern located on the first lower pattern, a second channel pattern located on the second lower pattern, an insulating structure located between the first channel pattern and the second channel pattern, a gate structure surrounding at least a portion of the first channel pattern, the second channel pattern, and the insulating structure, a source / drain pattern located on the first lower pattern and including a first source / drain layer including a first material and a second material different from the first material, and a second source / drain layer located on the first source / drain layer, and an iner gate spacer located between the source / drain pattern and the gate structure, wherein the iner gate spacer includes the first material, the second material, and a third material different from the first material and the second material.

[0007] In order to achieve the above object, according to still another aspect of the present invention, a semiconductor device includes a substrate, a first lower pattern and a second lower pattern located on the substrate and spaced apart from each other, a first channel pattern located on the first lower pattern, a second channel pattern located on the second lower pattern, an insulating structure located between the first channel pattern and the second channel pattern, a gate structure surrounding at least a portion of the first channel pattern and the second channel pattern, a first source / drain layer located on the first lower pattern and including a first material and a second material different from the first material, and and a source / drain pattern including a second source / drain layer located on the first source / drain layer, and an iner gate spacer located between the source / drain pattern and the gate structure and including silicon oxide and germanium, wherein the insulating structure includes a first buried insulating layer extending along a first direction and including a material having an etching selectivity with respect to the iner gate spacer, and second buried insulating layers located between the first buried insulating layer and the first channel pattern and arranged at intervals along the first direction, and the gate structure is located between the second buried insulating layers adjacent to each other along the first direction. [Effects of the Invention]

[0008] According to the present invention, the reliability of semiconductor elements can be improved. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view illustrating a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along the line AA' in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along the line BB' in FIG. [Figure 4] FIG. 2 is a cross-sectional view taken along the line CC' in FIG. [Figure 5] FIG. 3 is an enlarged cross-sectional view of a region Q1 in FIG. 2. [Figure 6]FIG. 6 is an enlarged cross-sectional view of an R1 region in FIG. 5. [Figure 7] FIG. 4 is an enlarged cross-sectional view of a region Q2 in FIG. 3. [Figure 8] FIG. 8 is an enlarged cross-sectional view of an R2 region in FIG. 7. [Figure 9] 8 is a cross-sectional view corresponding to region R2 of FIG. 7, illustrating a semiconductor device according to some embodiments. [Figure 10] 8 is a cross-sectional view corresponding to region R2 of FIG. 7, illustrating a semiconductor device according to some embodiments. [Figure 11] 8 is a cross-sectional view corresponding to region R2 of FIG. 7, illustrating a semiconductor device according to some embodiments. [Figure 12] 8 is a cross-sectional view corresponding to region R2 of FIG. 7, illustrating a semiconductor device according to some embodiments. [Figure 13] 3 is a cross-sectional view corresponding to region Q1 of FIG. 2 illustrating a semiconductor device according to some embodiments. [Figure 14] FIG. 14 is an enlarged cross-sectional view of an R3 region in FIG. 13. [Figure 15] 4 is a cross-sectional view corresponding to region Q2 of FIG. 3, illustrating a semiconductor device according to some embodiments. [Figure 16a] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 16b] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 17a] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 17b] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 18] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 19] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 20] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 21]1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 22] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 23] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 24] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 25] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 26a] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 26b] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 27a] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 27b] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 28a] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 28b] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 29] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 30] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 31] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 32] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 33] FIG. 33 is an enlarged cross-sectional view of the S1 region of FIG. 32. [Figure 34a] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 34b] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 35a] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 35b] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 36a] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 36b] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 37a] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 37b] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 38a] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 38b] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 39] FIG. 38b is an enlarged cross-sectional view of region U1 of FIG. [Figure 40] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 41] FIG. 41 is an enlarged cross-sectional view of region U2 in FIG. 40. [Figure 42a] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 42b] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 43] FIG. 42b is an enlarged cross-sectional view of region S2 of FIG. 42a. [Figure 44] FIG. 42b is an enlarged cross-sectional view of the U3 region of FIG. [Figure 45a] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 45b]1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 46] FIG. 45b is an enlarged cross-sectional view of region S3 of FIG. 45a. [Figure 47] FIG. 45b is an enlarged cross-sectional view of the U4 region of FIG. [Figure 48a] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 48b] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 49a] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 49b] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 50] FIG. 49B is an enlarged cross-sectional view of the U5 region of FIG. 49B. [Figure 51a] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 51b] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 52a] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 52b] 1A to 1C are cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings, in which: FIG. 1 is a block diagram of a semiconductor device according to an embodiment of the present invention;

[0011] In order to clearly explain the present invention, parts unnecessary for the explanation are omitted, and the same reference numerals are used throughout the specification to refer to the same or similar components.

[0012] Furthermore, the size and thickness of each component shown in the drawings are arbitrarily shown for the convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings. In the drawings, thicknesses are exaggerated to clearly show multiple layers and regions. In the drawings, thicknesses of some layers and regions are exaggerated for the convenience of explanation.

[0013] Furthermore, when a layer, film, region, plate, or other part is said to be "above" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Furthermore, being "above" a reference part means being located above or below the reference part, and does not necessarily mean being "above" the side opposite to gravity.

[0014] Furthermore, throughout the specification, when a part is said to "comprise" a certain element, this does not mean that it may further include other elements, unless otherwise specified to the contrary.

[0015] Also, throughout the specification, "on a plane" means when the subject part is viewed from above, and "on a cross section" means when the subject part is cut vertically and viewed from the side.

[0016] In the drawings relating to semiconductor devices according to some embodiments, examples include, but are not limited to, a transistor including nanowires or nanosheets, a Multi-Bridge Channel Field Effect Transistor (MBCFET, trademark), and a FinFET including a channel region with a fin-shaped pattern. Of course, semiconductor devices according to some embodiments may also include a tunneling FET, a 3D Stack Field Effect Transistor (3DSFET), a Complementary Field Effect Transistor (CFET), etc.

[0017] A semiconductor device according to an embodiment will be described below with reference to FIGS.

[0018] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view taken along line A-A' in FIG. 1. FIG. 3 is a cross-sectional view taken along line B-B' in FIG. 1. FIG. 4 is a cross-sectional view taken along line C-C' in FIG. 1. FIG. 5 is a cross-sectional view enlarging a Q1 region in FIG. 2. FIG. 6 is a cross-sectional view enlarging an R1 region in FIG. 5.

[0019] First, referring to FIGS. 1 to 4, a semiconductor device according to one embodiment includes a substrate 100, active patterns AP located on the substrate 100, insulating structures 200 located between the active patterns AP, gate structures GS surrounding at least a portion of the active patterns AP, and source / drain patterns 150 located on both sides of the gate structures GS.

[0020] The substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Additionally, the substrate 100 may be a silicon substrate or may include other materials, such as, but not limited to, silicon germanium (SiGe), silicon germanium on insulator (SOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The top surface of the substrate 100 is formed of a plane parallel to a first direction (X-direction) and a second direction (Y-direction) intersecting the first direction (X-direction).

[0021] The active patterns AP are located on the substrate 100. The active patterns AP protrude from the substrate 100. The active patterns AP extend elongatedly in a first direction (X direction). The active patterns AP protrude from the top surface of the substrate 100 in a third direction (Z direction). The active patterns AP are located spaced apart from each other in the second direction (Y direction). As an example, the active patterns AP are located in a region where a PMOS is formed. As another example, the active patterns AP are located in a region where an NMOS is formed. For example, one of the active patterns AP located on both sides of an insulating structure 200 (described later) may be located in a region where a PMOS is formed and the other may be located in a region where an NMOS is formed, but this is not limiting.

[0022] The active patterns AP are multi-channel active patterns. Each active pattern AP includes a lower pattern BP and a channel pattern NS. In one embodiment, the lower pattern BP and the channel pattern NS are semiconductor patterns having a nanosheet shape and including a semiconductor material.

[0023] The lower pattern BP is located on the substrate 100. The lower pattern BP protrudes from the substrate 100. The lower pattern BP extends in a first direction (X direction). The lower pattern BP is separated in a third direction (Z direction) by an insulating structure 200, which will be described later. For example, as shown in FIG. 3, the insulating structure 200 is located between a first lower pattern BP1 and a second lower pattern BP2, which are adjacent to each other in the second direction (Y direction). This will be described later with reference to FIGS. 7 and 8.

[0024] The channel pattern NS is located on the top surface of the lower pattern BP. The channel pattern NS is spaced apart from the lower pattern BP in the third direction (Z direction). On one lower pattern BP, channel patterns NS are located spaced apart from each other in the third direction (Z direction). Here, the third direction (Z direction) is a direction intersecting the first direction (X direction) and the second direction (Y direction). For example, the third direction (Z direction) is the thickness direction of the substrate 100. The second direction (Y direction) is a direction intersecting the first direction (X direction).

[0025] The channel patterns NS are separated in the third direction (Z direction) by an insulating structure 200, which will be described later. For example, as shown in Figure 3, the insulating structure 200 is located between a first channel pattern NS1 and a second channel pattern NS2 that are adjacent to each other in the second direction (Y direction). This will be described later with reference to Figures 7 and 8.

[0026] 2 and 3 show four channel patterns NS stacked at intervals along the third direction (Z direction), but this is for convenience of explanation only and is not limited to this. For example, two or three channel patterns NS may be stacked at intervals along the third direction (Z direction), or five or more channel patterns NS may be stacked at intervals along the third direction (Z direction).

[0027] The lower pattern BP may be formed by etching a portion of the substrate 100 or may include an epitaxial layer grown on the substrate 100. The lower pattern BP may include elemental semiconductor materials such as silicon (Si) or germanium (Ge). The lower pattern BP may also include a compound semiconductor, for example, a IV-IV compound semiconductor or a III-V compound semiconductor.

[0028] The IV-IV compound semiconductor is, for example, a binary compound or a ternary compound containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn).

[0029] The III-V compound semiconductor is, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as a group III element with one of phosphorus (P), arsenic (As), and antimony (Sb) as a group V element.

[0030] The channel patterns NS include one of elemental semiconductor materials, silicon (Si) or silicon germanium (SiGe), a IV-IV compound semiconductor, or a III-V compound semiconductor. In one embodiment, the channel patterns NS include a first material, where the first material is silicon (Si). Each channel pattern NS may include the same material as the lower pattern BP or a different material from the lower pattern BP.

[0031] In the semiconductor device according to the embodiment, the lower pattern BP is a silicon lower pattern including silicon (Si), and the channel pattern NS is a silicon sheet pattern including silicon (Si).

[0032] The semiconductor device according to one embodiment further includes a field insulating layer 105 located on the substrate 100 .

[0033] The field insulating layer 105 is located on the substrate 100. The field insulating layer 105 is located on the side surfaces of the lower pattern BP. The field insulating layer 105 is not located on the upper surface of the lower pattern BP. The field insulating layer 105 covers part of the side surfaces of the lower pattern BP, but is not limited to this. For example, the field insulating layer 105 may completely cover the side surfaces of the lower pattern BP. Each channel pattern NS is located higher than the upper surface of the field insulating layer 105.

[0034] The field insulating layer 105 may include various insulating materials. For example, the field insulating layer 105 may include, but is not limited to, silicon dioxide (SiO2). As another example, the field insulating layer 105 may include silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof. Although the field insulating layer 105 is shown as a single layer, this is for convenience of explanation only and is not limiting.

[0035] The insulating structure 200 is located on the substrate 100. The insulating structure 200 is located between a side of the lower pattern BP and a side of the channel pattern NS on the substrate 100. For example, as shown in FIG. 3, the insulating structure 200 is located between a first lower pattern BP1 and a second lower pattern BP2 adjacent to each other in the second direction (Y direction) and between a first channel pattern NS1 and a second channel pattern NS2 adjacent to each other in the second direction (Y direction). Here, the first lower pattern BP1 and the second lower pattern BP2 refer to the lower patterns BP adjacent to each other in the second direction (Y direction). Also, the first channel pattern NS1 and the second channel pattern NS2 refer to the channel patterns NS adjacent to each other in the second direction (Y direction).

[0036] For ease of explanation, the channel pattern NS located on one side of the insulating structure 200 in the second direction (Y direction) will be referred to as a first channel pattern NS1, and the channel pattern NS located on the other side of the insulating structure 200 in the second direction (Y direction) will be referred to as a second channel pattern NS2. That is, in one embodiment, the insulating structure 200 is located between the first channel pattern NS1 and the second channel pattern NS2. Also, the lower pattern BP located on one side of the insulating structure 200 in the second direction (Y direction) will be referred to as a first lower pattern BP1, and the lower pattern BP located on the other side of the insulating structure 200 in the second direction (Y direction) will be referred to as a second lower pattern BP2. That is, in one embodiment, the insulating structure 200 is located between the first lower pattern BP1 and the second lower pattern BP2.

[0037] In one embodiment, the insulating structure 200 overlaps the bottom pattern BP and the channel pattern NS in the second direction (Y direction). The insulating structure 200 contacts, but is not limited to, the side of the bottom pattern BP and the side of the channel pattern NS. The insulating structure 200 also contacts the side of the gate structure GS located between adjacent channel patterns NS in the third direction (Z direction). That is, the side of the insulating structure 200 contacts the side of the stacked structure in which the gate structures GS and the channel patterns NS are alternately stacked. This will be described in detail later with reference to FIGS. 7 and 8. In one embodiment, the insulating structure 200 extends in the first direction (X direction).

[0038] The top surface of the insulating structure 200 is located at a higher level than the top surface of the uppermost channel pattern NS, i.e., the top surface of the insulating structure 200 is located farther from the top surface of the substrate 100 than the top surface of the uppermost channel pattern NS, i.e., the insulating structure 200 protrudes in the third direction (Z direction) beyond the uppermost channel pattern NS.

[0039] In one embodiment, the top surface of the insulating structure 200 is located at a higher level than the top surfaces of the gate structures GS. The top surface of the insulating structure 200 is located farther from the top surface of the substrate 100 than the top surface of the uppermost gate structure GS. That is, the insulating structure 200 protrudes from the top surface of the gate structure GS in the third direction (Z direction), but is not limited to this. As another example, the insulating structure 200 penetrates the capping layer 145. As a result, the gate structures GS are separated from each other in the second direction (Y direction) based on the insulating structure 200. That is, the gate structure GS located on one side of the insulating structure 200 in the second direction (Y direction) is separated from the gate structure GS located on the other side of the insulating structure 200 in the second direction (Y direction). In other words, the insulating structure 200 functions as a gate isolation structure that insulates the gate structures GS. In addition, in one embodiment, source / drain patterns 150 are located on both sides of the insulating structure 200 in the second direction (Y direction).

[0040] The insulating structure 200 includes a low-dielectric constant material. When the distance between adjacent channel patterns NS in the second direction (Y direction) decreases, coupling occurs between the adjacent channel patterns NS in the second direction (Y direction). This reduces the reliability of the semiconductor device. In the semiconductor device according to an embodiment, the insulating structure 200 includes a low-dielectric constant material, thereby improving the coupling between the adjacent channel patterns NS in the second direction (Y direction). In other words, the integration density of the semiconductor device according to an embodiment can be improved.

[0041] An insulating structure 200 of a semiconductor device according to an embodiment includes a first buried insulating layer 210 located between lower patterns BP adjacent to each other in the second direction (Y direction), a second buried insulating layer 220 located between the first buried insulating layer 210 and the channel pattern NS, and a third buried insulating layer 230 located between the first buried insulating layer 210 and the lower pattern BP. The first to third buried insulating layers 210 to 230 will be described in detail below with reference to FIGS. 7 and 8.

[0042] The gate structures GS are located on the substrate 100. The gate structures GS extend in the second direction (Y direction). The gate structures GS are arranged in the first direction (X direction) to be spaced apart from each other.

[0043] The gate structure GS is located above the active pattern AP, crosses the active pattern AP on a plane, and intersects with the lower pattern BP on a plane.

[0044] The gate structure GS surrounds at least a portion of each channel pattern NS. For example, as shown in FIG. 3, the gate structure GS covers one side, bottom, and top of the first channel pattern NS1 and one side, bottom, and top of the second channel pattern NS2. The gate structure GS also surrounds at least a portion of the insulating structure 200. For example, the gate structure GS surrounds at least a portion of the side of the insulating structure 200. That is, the gate structure GS surrounds at least a portion of the channel pattern NS and the insulating structure 200. As a result, one side, bottom, and top of the channel pattern NS are in contact with the gate structure GS. The other side of the channel pattern NS is in contact with the insulating structure 200.

[0045] 5, the gate structure GS includes a plurality of sub-gate structures S_GS and a main gate structure M_GS. The sub-gate structures S_GS are located between adjacent channel patterns NS in the third direction (Z direction) and between the lower pattern BP and the lowermost channel pattern NS. The main gate structure M_GS is located on the uppermost channel pattern NS.

[0046] Specifically, the sub-gate structures S_GS are located between the top surface of the bottom pattern BP and the bottom surface of the lowest channel pattern NS, and between the top surface of the channel pattern NS facing the third direction (Z direction) and the bottom surface of the channel pattern NS. The sub-gate structures S_GS are adjacent to the source / drain patterns 150, which will be described later. The main gate structure M_GS is located on the top surfaces of the sub-gate structures S_GS and the channel pattern NS.

[0047] According to one embodiment, the active pattern AP includes a plurality of channel patterns NS, and the gate structure GS includes a plurality of sub-gate structures S_GS. In this case, the number of the sub-gate structures S_GS is proportional to the number of the channel patterns NS included in the active pattern AP. For example, the number of the sub-gate structures S_GS is the same as the number of the channel patterns NS. For example, as shown in FIGS. 2 and 5, the number of the sub-gate structures S_GS is four. However, this is not limited thereto, and the sub-gate structures S_GS may include three or five or more sub-gate structures S_GS.

[0048] 5 and 6, the plurality of sub-gate structures S_GS include a sub-gate electrode 120S including a first sub-gate electrode 121S and a second sub-gate electrode 122S, and a sub-gate insulating pattern 130S including a sub-gate insulating layer 131S and a sub-gate dielectric layer 132S.

[0049] The sub-gate electrode 120S is formed on the lower pattern BP, intersects with the lower pattern BP, and surrounds the plurality of channel patterns NS.

[0050] At least a portion of the sub-gate electrode 120S is located on the stacked structure of the sub-gate electrode 120S and the plurality of channel patterns NS. Another portion of the sub-gate electrode 120S is formed to cover both side surfaces of the stacked structure of the sub-gate electrode 120S and the plurality of channel patterns NS in the second direction (Y direction). In this case, the first sub-gate electrode 121S surrounds the plurality of channel patterns NS and at least a portion of the insulating structure 200, and the second sub-gate electrode 122S surrounds the first sub-gate electrode 121S. This will be described later with reference to FIGS. 7 and 8.

[0051] The sub-gate electrode 120S includes at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The first sub-gate electrode 121S and the second sub-gate electrode 122S may include, but are not limited to, different materials, and may include the same material. The sub-gate electrode 120S may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W Conductive metal oxides and conductive metal oxynitrides may include, but are not limited to, at least one of the following: aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. Conductive metal oxides and conductive metal oxynitrides may include, but are not limited to, oxidized forms of the above-mentioned materials.

[0052] The sub-gate insulating film 131S extends along the upper surface of the lower pattern BP. The sub-gate insulating film 131S is positioned along the periphery of the plurality of channel patterns NS. The sub-gate insulating film 131S is in direct contact with the lower pattern BP and the plurality of channel patterns NS. The sub-gate insulating film 131S is interposed between the plurality of channel patterns NS and the sub-gate electrode 120S. The sub-gate insulating film 131S also extends along the upper surface of the field insulating layer 105.

[0053] 3, the sub-gate insulating layer 131S does not surround the first buried insulating layer 210 and the second buried insulating layer 220. The sub-gate insulating layer 131S is spaced apart from the first buried insulating layer 210. That is, the second buried insulating layer 220 is located between the sub-gate insulating layer 131S and the first buried insulating layer 210. The sub-gate insulating layer 131S may include various insulating materials.

[0054] The sub-gate dielectric layer 132S is located on the sub-gate insulating film 131S. The sub-gate dielectric layer 132S is located between the sub-gate insulating film 131S and the sub-gate electrode 120S. The sub-gate dielectric layer 132S is located between inner gate spacers 135, which will be described later. As shown in FIGS. 5 and 6 , the sub-gate dielectric layer 132S surrounds the sub-gate electrode 120S on a cross section formed in the first direction (X direction) and the third direction (Z direction). The sub-gate dielectric layer 132S contacts, but is not limited to, a side surface of an inner gate spacer 135, which will be described later.

[0055] The sub-gate dielectric layer 132S is disposed on the insulating structure 200. For example, as shown in FIG. 3, the sub-gate dielectric layer 132S is disposed on the side of the first buried insulating layer 210 and the top and bottom surfaces of the second buried insulating layer 220. The sub-gate dielectric layer 132S is disposed with a uniform thickness on one side, top, and bottom surfaces of the channel pattern NS, the side of the first buried insulating layer 210, and the top and bottom surfaces of the second buried insulating layer 220. In one embodiment, the sub-gate dielectric layer 132S includes an extension (132_E in FIG. 8) disposed on the side of the first buried insulating layer 210. The extension (132_E in FIG. 8) refers to a portion of the gate dielectric layer (132 in FIG. 7) extending in the third direction (Z direction) on the side of the first buried insulating layer 210. This will be described later with reference to FIGS. 7 and 8.

[0056] The sub-gate dielectric layer 132S includes silicon dioxide (SiO2) and a high-k material, where the high-k material includes a material with a dielectric constant greater than that of silicon dioxide (SiO2), such as hafnium dioxide (HfO), aluminum dioxide (AlO), or tantalum dioxide (TaO).

[0057] In one embodiment, the sub-gate insulating film 131S and the sub-gate dielectric layer 132S are shown as a single layer, but are not limited thereto, and the sub-gate insulating film 131S and the sub-gate dielectric layer 132S may be formed as multiple layers.

[0058] The main gate structure M_GS is located on the sub-gate structure S_GS and the plurality of channel patterns NS. The main gate structure M_GS is located on the upper surface of the plurality of channel patterns NS.

[0059] The main gate structure M_GS includes a main gate electrode 120M including a first main gate electrode 121M and a second main gate electrode 122M, and a main gate insulating pattern 130M including a main gate insulating layer 131M and a main gate dielectric layer 132M.

[0060] The main gate electrode 120M is located on the sub-gate structure S_GS and the plurality of channel patterns NS. The main gate electrode 120M is located on the top surfaces of the plurality of channel patterns NS. The main gate electrode 120M is located between gate spacers 140 (described later). For example, a first main gate electrode 121M is located on the top surface of the uppermost channel pattern NS and on the side surface of a gate spacer 140 (described later), and a second main gate electrode 122M is located on the first main gate electrode 121M.

[0061] The main gate electrode 120M includes the same material as the sub-gate electrode 120S. In one embodiment, the first main gate electrode 121M and the second main gate electrode 122M include different materials, but are not limited to this and may include the same material. For example, the main gate electrode 120M includes at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0062] The main gate insulating film 131M is located on a lower surface of the main gate electrode 120M. The main gate insulating film 131M may include various insulating materials. The main gate insulating film 131M may be integrally formed with the sub-gate insulating film 131S through the same process. The main gate insulating film 131M may be integrally formed with the sub-gate insulating film 131S.

[0063] The main gate dielectric layer 132M is located on the main gate insulating film 131M. The main gate dielectric layer 132M extends along the side of the main gate electrode 120M. The main gate dielectric layer 132M extends along the side of the gate spacer 140, which will be described later. That is, the main gate dielectric layer 132M is located between the gate spacer 140, which will be described later, and the main gate electrode 120M, and between the main gate insulating film 131M and the main gate electrode 120M. The main gate dielectric layer 132M may be formed integrally with the sub-gate dielectric layer 132S in the same process. The main gate dielectric layer 132M may be formed integrally with the sub-gate dielectric layer 132S. The main gate dielectric layer 132M includes silicon oxide (SiO2) and a high-k material. Here, the high-k material includes a material with a higher dielectric constant than silicon oxide (SiO2), such as hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO).

[0064] In one embodiment, the main gate insulating film 131M and the main gate dielectric layer 132M are shown as a single layer, but are not limited thereto, and the main gate insulating film 131M and the main gate dielectric layer 132M may be formed as multiple layers.

[0065] In one embodiment, the sub-gate electrode 120S and the main gate electrode 120M constitute a gate electrode 120 of a semiconductor device according to one embodiment. That is, the first sub-gate electrode 121S and the first main gate electrode 121M constitute a first gate electrode 121, and the second sub-gate electrode 122S and the second main gate electrode 122M constitute a second gate electrode 122. Also, the sub-gate insulation pattern 130S and the main gate insulation pattern 130M constitute a gate insulation pattern 130 of a semiconductor device according to one embodiment. That is, the sub-gate insulation layer 131S and the main gate insulation layer 131M constitute a gate insulation layer 131, and the sub-gate dielectric layer 132S and the main gate dielectric layer 132M constitute a gate dielectric layer 132.

[0066] In other words, the portion of the gate electrode 120 included in the plurality of sub-gate structures S_GS is referred to as the sub-gate electrode 120S, and the portion of the gate insulation pattern 130 included in the plurality of sub-gate structures S_GS is referred to as the sub-gate insulation pattern 130S. Also, the portion of the gate electrode 120 included in the main gate structure M_GS is referred to as the main gate electrode 120M, and the portion of the gate insulation pattern 130 included in the main gate structure M_GS is referred to as the main gate insulation pattern 130M.

[0067] In one embodiment, the gate insulating film 131 surrounds the first channel pattern NS1, the second channel pattern NS2, and the insulating structure 200. For example, on a cross section formed in the second direction (Y direction) and the third direction (Z direction), the gate insulating film 131 is located on the upper and lower surfaces of the second buried insulating layer 220 of the insulating structure 200 and on the side surfaces of the first buried insulating layer 210. The gate insulating film 131 contacts at least a portion of the first channel pattern NS1, the second channel pattern NS2, and the insulating structure 200. In addition, the gate structure GS surrounds the gate insulating film 131. This will be described in detail later with reference to FIGS. 7 and 8.

[0068] The semiconductor device according to one embodiment further includes a gate spacer 140 .

[0069] The gate spacers 140 are located on the side surfaces of the gate structures GS. For example, the gate spacers 140 are located between the main gate structures M_GS and the interlayer insulating layer 190. Also, for example, the gate spacers 140 are located between the source / drain patterns 150 and the gate structures GS.

[0070] The gate spacers 140 are not positioned on the side surfaces of the sub-gate structures S_GS, and are not positioned between adjacent channel patterns NS in the third direction (Z direction), but this is not limiting.

[0071] 2, the gate spacer 140 is shown as being formed of a single layer, but is not limited thereto, and may be formed of, for example, multiple layers.

[0072] The gate spacers 140 may include various insulating materials. For example, the gate spacers 140 may include silicon nitride (SiN). However, without being limited thereto, the gate spacers 140 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0073] According to one embodiment, the semiconductor device further includes a capping layer 145 located over the gate structure GS.

[0074] The capping layer 145 is located on the gate structure GS and the gate spacer 140. Alternatively, the capping layer 145 is located only on the gate structure GS on the side of the gate spacer 140. The capping layer 145 includes, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. The capping layer 145 includes a material having an etching selectivity with respect to the interlayer insulating layer 190.

[0075] The source / drain patterns 150 are located on the lower patterns BP. For example, the source / drain patterns 150 are located on the first lower patterns BP1 and the second lower patterns BP2 located on the substrate 100. The source / drain patterns 150 are located on both sides of the gate structure GS. For example, the source / drain patterns 150 are located on both sides of the gate structure GS in the first direction (X direction). The source / drain patterns 150 are also located on both sides of the channel pattern NS in the first direction (X direction). The source / drain patterns 150 are electrically connected to the channel pattern NS.

[0076] 4, the source / drain patterns 150 are located on both sides of the insulating structure 200 in the second direction (Y direction). For example, the source / drain pattern 150 located on the first lower pattern BP1 and the source / drain pattern 150 located on the second lower pattern BP2 are separated from each other by the insulating structure 200. The source / drain patterns 150 contact the side of the second buried insulating layer 220 of the insulating structure 200, but are not limited thereto.

[0077] The source / drain pattern 150 is positioned within a source / drain recess 150R having a depth along the third direction (Z direction). The source / drain pattern 150 fills the source / drain recess 150R. The bottom of the source / drain recess 150R is defined by the bottom pattern BP. The side of the source / drain recess 150R is defined by the iner gate spacer 135 and the channel pattern NS. However, without being limited thereto, some embodiments of the semiconductor device do not include an iner gate spacer, in which case the side of the source / drain recess 150R is defined by the channel pattern NS and the gate structure GS.

[0078] On a cross section formed in the first direction (X direction) and the third direction (Z direction), the top surface of the source / drain pattern 150 is located at a higher level than the top surface of the channel pattern NS. That is, the top surface of the source / drain pattern 150 is located farther from the top surface of the substrate 100 than the top surface of the channel pattern NS. In addition, the source / drain pattern 150 protrudes in the second direction (Y direction) from the channel pattern NS, but is not limited to this.

[0079] 5 and 6, the outer surfaces of the source / drain patterns 150 contact the channel pattern NS and the iner gate spacer 135. The outer surfaces of the source / drain patterns 150 are formed as uneven curved surfaces. For example, the portions of the outer surfaces of the source / drain patterns 150 that contact the channel pattern NS may have a concave or substantially flat cross section, but are not limited thereto. This is because the shape of the source / drain recesses 150R is formed to be uneven by further performing a process of selectively etching the dummy gate structure after forming the source / drain recesses 150R.

[0080] The source / drain patterns 150 are epitaxial patterns formed by a selective epitaxial growth process using the active patterns AP as a seed. The channel patterns NS are portions of the active patterns AP that extend between the source / drain patterns 150. The source / drain patterns 150 function as the source / drain of a transistor that uses the channel patterns NS as a channel region.

[0081] The source / drain pattern 150 of the semiconductor device according to the embodiment includes a first source / drain layer 151 located on the lower pattern BP and a second source / drain layer 152 located on the first source / drain layer 151 .

[0082] The first source / drain layer 151 is located on the lower pattern BP. The first source / drain layer 151 is formed along the inner wall and bottom surface of the source / drain recess 150R. That is, the first source / drain layer 151 is located on both sides of the gate structure GS in the first direction (X direction). The first source / drain layer 151 is located on both sides of the channel pattern NS in the first direction (X direction). The first source / drain layer 151 formed along the inner wall of the source / drain recess 150R directly contacts the active pattern AP. For example, the first source / drain layer 151 directly contacts the side surfaces of the lower pattern BP and the channel pattern NS. The first source / drain layer 151 also contacts the side surfaces of the iner gate spacer 135, but is not limited thereto. The portion of the first source / drain layer 151 in contact with the iner gate spacer 135 has a bent portion 151B, but is not limited thereto. The bent portion 151B of the first source / drain layer 151 overlaps the iner gate spacer 135 along the first direction (X direction).

[0083] The first source / drain layer 151 includes a first material, which is a semiconductor material, and a second material different from the first material. Here, the first material is silicon (Si), and the second material is germanium (Ge). That is, the first source / drain layer 151 includes silicon germanium (SiGe). At this time, the content (at%) of the second material in the first source / drain layer 151 is 5 at% to 20 at%. Within this range, the inner gate spacer 135 can be easily formed by utilizing the difference in the degree of oxidation between the interface of the first source / drain layer 151 and the interface of the channel pattern NS during the process of forming the inner gate spacer 135 through an oxidation process.

[0084] Specifically, the gate trench (120t in FIG. 42a) exposes a channel pattern NS including a first material and a first source / drain layer 151 including a first material and a second material. An oxidation process is then performed to form an iner gate spacer material layer (135P in FIG. 42a) on the top and bottom surfaces of the exposed channel pattern NS and on the side surfaces of the first source / drain layer 151. In this case, in one embodiment, the first source / drain layer 151 further includes a second material different from the first material constituting the channel pattern NS, so that the degree of oxidation at the interface of the first source / drain layer 151 is greater than the degree of oxidation at the interface of the channel pattern NS. Therefore, an iner gate spacer material layer (135P in FIG. 42a) with different thicknesses can be formed depending on the interface. In a subsequent process, the iner gate spacer material layer (135P in FIG. 42a) is patterned to easily form an iner gate spacer 135 of a semiconductor device according to one embodiment. This will be described in detail below with reference to FIG. 42a and subsequent figures.

[0085] The second source / drain layers 152 are located on both sides of the channel pattern NS in the first direction (X direction). The second source / drain layers 152 are located on both sides of the gate structure GS in the first direction (X direction). The second source / drain layers 152 fill the remaining portions of the source / drain recesses 150R where the first source / drain layers 151 are formed.

[0086] The second source / drain layer 152 includes a semiconductor material. The second source / drain layer 152 includes a first material and / or a second material. The type of material included in the second source / drain layer 152 varies depending on whether the semiconductor device according to an embodiment is an N-type MOSFET or a P-type MOSFET.

[0087] For example, if the semiconductor device according to one embodiment is an N-type device, the second source / drain layer 152 includes a first material but does not include a second material. Here, the first material is silicon (Si) and the second material is germanium (Ge). In this case, the first source / drain layer 151 and / or the second source / drain layer 152 include N-type impurities. For example, the first source / drain layer 151 and the second source / drain layer 152 include P, Sb, As, or a combination thereof. The concentration of the impurities doped into the first source / drain layer 151 may be different from the concentration of the impurities doped into the second source / drain layer 152. For example, the concentration of the N-type impurities doped into the second source / drain layer 152 may be greater than the concentration of the N-type impurities doped into the first source / drain layer 151, but is not limited to this.

[0088] As another example, if the semiconductor device according to an embodiment is a P-type device, the second source / drain layer 152 includes a first material and a second material. That is, the second source / drain layer 152 includes the same material as the first source / drain layer 151. In this case, the concentrations of the constituent materials of the second source / drain layer 152 and the first source / drain layer 151 may be different. For example, if the second source / drain layer 152 and the first source / drain layer 151 include silicon germanium (SiGe), the germanium (Ge) concentration of the second source / drain layer 152 may be higher than the germanium (Ge) concentration of the first source / drain layer 151, but is not limited to this. Furthermore, the first source / drain layer 151 and / or the second source / drain layer 152 include P-type impurities. As an example, the first source / drain layer 151 and the second source / drain layer 152 include B, V, In, Ga, Al, or a combination thereof. The concentration of the impurity doped into the first source / drain layer 151 may be different from the concentration of the impurity doped into the second source / drain layer 152. For example, the concentration of the P-type impurity doped into the second source / drain layer 152 may be higher than the concentration of the P-type impurity doped into the first source / drain layer 151, but is not limited thereto.

[0089] In summary, the type of material contained in the second source / drain layer 152 varies depending on whether the semiconductor device according to an embodiment is an N-type MOSFET or a P-type MOSFET. Meanwhile, the first source / drain layer 151 contains the first material and the second material regardless of whether the semiconductor device according to an embodiment is an N-type MOSFET or a P-type MOSFET. This is because, as described above, the inner gate spacer 135 can be easily formed by utilizing the difference in the degree of oxidation between the interface of the first source / drain layer 151 and the interface of the channel pattern NS.

[0090] However, without being limited thereto, as another example, the second source / drain layer 152 and the first source / drain layer 151 may further include a fourth material different from the first material and the second material. Here, the fourth material is carbon (C), tin (Sn), or a combination thereof. As another example, the second source / drain layer 152 may include the same material as the first source / drain layer 151, and the second source / drain layer 152 and the first source / drain layer 151 may have the same concentration of constituent materials.

[0091] In one embodiment, the source / drain pattern 150 is described as being formed of a double layer, but is not limited thereto, and the source / drain pattern 150 may be formed of a single layer containing a semiconductor material or a multi-layer including three or more layers.

[0092] The semiconductor device according to one embodiment further includes an iner gate spacer 135 .

[0093] The inner gate spacer 135 is located on the side of the sub-gate structure S_GS. The inner gate spacer 135 is located between the source / drain pattern 150 and the sub-gate structure S_GS. For example, as shown in FIGS. 5 and 6, the inner gate spacer 135 is located on the side of the sub-gate dielectric layer 132S. The inner gate spacer 135 contacts the side of the sub-gate dielectric layer 132S and the side of the first source / drain layer 151, but is not limited to this. The inner gate spacer 135 is not located on the side of the main gate structure M_GS. The thickness of the inner gate spacer 135 in the first direction (X direction) is 1 nm to 3 nm. Within this range, the inner gate spacer 135 can effectively block leakage current between the sub-gate electrode 120S and the source / drain pattern 150.

[0094] In one embodiment, but not limited to, the side of the inner gate spacer 135 is aligned with the side of the source / drain pattern 150. For example, the inner gate spacer 135 may include a portion embedded in the source / drain pattern 150. This will be described later with reference to FIGS.

[0095] The iner gate spacer 135 may include various insulating materials. The iner gate spacer 135 includes an insulating material containing a first material and a second material. For example, the iner gate spacer 135 includes a first material, a second material, and a third material different from the first and second materials. Here, the first and second materials are silicon (Si) and germanium (Ge), which constitute the first source / drain layer 151. The third material is oxygen (O). That is, according to one embodiment, the iner gate spacer 135 of the semiconductor device includes silicon oxide (SiO2) containing germanium (Ge). This is due to the process characteristics of forming the iner gate spacer 135 by oxidizing the interface of the first source / drain layer 151. In addition, in one embodiment, the content of the third material included in the iner gate spacer 135 decreases with increasing distance from the side of the first source / drain layer 151, but is not limited thereto. That is, when the iner gate spacer 135 includes silicon oxide (SiO2) containing germanium (Ge), the content of oxygen (O) that bonds with silicon (Si) and / or germanium (Ge) decreases with increasing distance from the side surface of the first source / drain layer 151. This is due to the process characteristics of forming the iner gate spacer 135 by oxidizing the interface of the first source / drain layer 151.

[0096] The semiconductor device according to the embodiment further includes an interlayer insulating layer 190. The interlayer insulating layer 190 is located on the source / drain pattern 150. The interlayer insulating layer 190 does not cover the top surface of the gate structure GS. The interlayer insulating layer 190 is located between the side surfaces of the gate structure GS. The interlayer insulating layer 190 surrounds the source / drain pattern 150.

[0097] The interlayer insulating layer 190 includes, for example, at least one of silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), and a low dielectric constant material. Examples of low dielectric constant materials include Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen Silsesquioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethylCloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSilylBorate (TMSB), DiAcetoxyDitertiaryButoSiloxane (DADBS), TriMethylSilyl Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TonenSilaZen (TOSZ), Fluoride Silicate Glass (FSG), polyimide nanofoams such as polypropylene oxide, Carbon Doped Silicon Oxide (CDO), and Organo Silicate (OSG). Glass, SiLK, amorphous fluorinated carbon, silica aerogels, silica xerogels, mesoporous silica, or combinations thereof.

[0098] According to an embodiment, the semiconductor device further includes an etch stop layer 185 located between the interlayer insulating layer 190 and the source / drain pattern 150 and between the interlayer insulating layer 190 and the gate spacer 140. The etch stop layer 185 is located on the side of the gate spacer 140 and on the top surface of the source / drain pattern 150. The etch stop layer 185 also surrounds at least a portion of the source / drain pattern 150.

[0099] The etch stop layer 185 includes a material having an etch selectivity with respect to the interlayer insulating layer 190. The etch stop layer 185 also includes a material having an etch selectivity with respect to the source / drain pattern 150, which will be described later. The etch stop layer 185 includes, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0100] The semiconductor device according to one embodiment further includes an upper insulating layer 195 .

[0101] The upper insulating layer 195 is located on the upper surface of the interlayer insulating layer 190 , the upper surface of the etch stop layer 185 , and the upper surface of the capping layer 145 .

[0102] Although not shown in the drawings, the semiconductor device according to an embodiment further includes a contact electrode.

[0103] The contact electrode is located on the gate structure GS. The contact electrode is electrically connected to the gate structure GS through the upper insulating layer 195 and the capping layer 145. For example, the lower surface of the contact electrode is surrounded by the gate structure GS. The lower surface of the contact electrode is located at a lower level than the upper surface of the gate structure GS. On a cross section formed in the second direction (Y direction) and the third direction (Z direction), the contact electrode is located on one side and / or the other side of the insulating structure 200.

[0104] The contact electrode includes a conductive material, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material.

[0105] An insulating structure of a semiconductor device according to an embodiment will now be described with further reference to FIGS.

[0106] Fig. 7 is an enlarged cross-sectional view of a region Q2 in Fig. 3. Fig. 8 is an enlarged cross-sectional view of a region R2 in Fig. 7.

[0107] 7 and 8, an insulating structure 200 of a semiconductor device according to one embodiment includes a first buried insulating layer 210 located between lower patterns BP adjacent to each other in the second direction (Y direction), a second buried insulating layer 220 located between the first buried insulating layer 210 and the channel pattern NS, and a third buried insulating layer 230 located between the first buried insulating layer 210 and the lower pattern BP.

[0108] The first buried insulating layer 210 is located between the first channel pattern NS1 and the second channel pattern NS2. That is, the first buried insulating layer 210 is located between adjacent channel patterns NS in the second direction (Y direction). The first buried insulating layer 210 separates the first channel pattern NS1 and the second channel pattern NS2 from each other in the second direction (Y direction).

[0109] The side surface of the first buried insulating layer 210 contacts the gate structure GS and the second buried insulating layer 220. For example, the side surface of the first buried insulating layer 210 contacts the extension 132_E of the gate dielectric layer 132 and the second buried insulating layer 220. In this case, the extension 132_E of the gate dielectric layer 132 refers to a part of the gate dielectric layer 132 extending in the third direction (Z direction) on the side surface of the first buried insulating layer 210.

[0110] The first buried insulating layer 210 extends in the third direction (Z direction). The top surface of the first buried insulating layer 210 is located at a higher level than the top surface of the uppermost channel pattern NS. That is, the top surface of the first buried insulating layer 210 is located farther from the top surface of the substrate 100 than the top surface of the uppermost channel pattern NS. That is, the first buried insulating layer 210 protrudes in the third direction (Z direction) beyond the uppermost channel pattern NS.

[0111] In one embodiment, the top surface of the first buried insulating layer 210 is located at a higher level than the top surfaces of the gate structures GS. The top surface of the first buried insulating layer 210 is located farther from the top surface of the substrate 100 than the top surface of the uppermost gate structure GS. That is, the first buried insulating layer 210 protrudes from the top surface of the gate structure GS in the third direction (Z direction), but is not limited thereto. As another example, the first buried insulating layer 210 is located at substantially the same level as the bottom surface of the capping layer 145. As another example, the first buried insulating layer 210 penetrates the capping layer 145. As a result, the gate structures GS are separated from each other in the second direction (Y direction) based on the first buried insulating layer 210. That is, the gate structure GS located on one side of the first buried insulating layer 210 in the second direction (Y direction) and the gate structure GS located on the other side of the first buried insulating layer 210 in the second direction (Y direction) are separated from each other. In other words, the first buried insulating layer 210 functions as a gate isolation structure that provides insulation between the gate structures GS. In one embodiment, the thickness of the first buried insulating layer 210 along the second direction (Y direction) is 15 nm to 25 nm, but is not limited thereto.

[0112] The first buried insulating layer 210 may include various insulating materials. The first buried insulating layer 210 includes a material different from that of the field insulating layer 105. The first buried insulating layer 210 includes a material having an etching selectivity with respect to the iner gate spacer 135 and the second buried insulating layer 220. The first buried insulating layer 210 includes a nitride-based insulating material. For example, the first buried insulating layer 210 may include at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), and a low-k material, but is not limited to these.

[0113] The second buried insulating layer 220 is located between the first buried insulating layer 210 and the channel pattern NS. For example, the second buried insulating layer 220 is located between the first buried insulating layer 210 and the first channel pattern NS1 and between the first buried insulating layer 210 and the second channel pattern NS2. In other words, the second buried insulating layer 220 is located on both sides of the first buried insulating layer 210 in the second direction (Y direction).

[0114] In one embodiment, a plurality of second buried insulating layers 220 are provided and arranged spaced apart in the third direction (Z direction). Portions of the second buried insulating layers 220 are arranged spaced apart in the third direction (Z direction). Specifically, the second buried insulating layers 220 are positioned between each of the first channel patterns NS1 and the first buried insulating layer 210, but are not positioned between the first buried insulating layer 210 and a gate structure GS positioned between adjacent first channel patterns NS1 in the third direction (Z direction). That is, the second buried insulating layers 220 are positioned on one side of each of the first channel patterns NS1 in the second direction (Y direction), but are not positioned on one side in the second direction (Y direction) of a gate structure GS positioned between adjacent first channel patterns NS1 in the third direction (Z direction).

[0115] As a result, a plurality of second buried insulating layers 220 are provided and protrude in the second direction (Y direction) from the side surfaces of the first buried insulating layer 210. A channel pattern NS is located on the side surfaces of the protruding second buried insulating layers 220, and a gate dielectric layer 132 is located on the upper and lower surfaces of the channel pattern NS and the upper and lower surfaces of the second buried insulating layer 220. At this time, an extension 132_E of the gate dielectric layer 132 is located on the side surfaces of the first buried insulating layer 210. In addition, the extension 132_E of the gate dielectric layer 132 is located directly above the side surfaces of the first buried insulating layer 210 where the second buried insulating layer 220 is not located.

[0116] One side of the second buried insulating layer 220 in the second direction (Y direction) contacts the channel pattern NS, and the other side of the second buried insulating layer 220 in the second direction (Y direction) contacts the first buried insulating layer 210. The top and bottom surfaces of the second buried insulating layer 220 contact the gate dielectric layer 132. The second width D2 of the second buried insulating layer 220 in the second direction (Y direction) is greater than or equal to the first width D1 of the gate dielectric layer 132 in the second direction (Y direction). The first width D1 of the gate dielectric layer 132 in the second direction (Y direction) is substantially equal to the width of the extension 132_E of the gate dielectric layer 132 in the second direction (Y direction) that extends in the third direction (Z direction). To this extent, the area of ​​each channel pattern NS surrounded by the gate structure GS increases. Therefore, the extension 132_E of the gate dielectric layer 132 does not overlap with the channel pattern NS in the third direction (Z direction), but is not limited to this. In one embodiment, at least a portion of the upper surface and the lower surface of the second buried insulating layer 220 contacts the gate insulating film 131, but is not limited to this.

[0117] In one embodiment, the second buried insulating layer 220 overlaps the channel pattern NS in the second direction (Y direction). The second buried insulating layer 220 does not overlap in the second direction (Y direction) with the gate structure GS located between adjacent channel patterns NS in the third direction (Z direction), but this is not limiting. The first thickness TH1 of the second buried insulating layer 220 in the third direction (Z direction) is smaller than the second thickness TH2 of each channel pattern NS in the third direction (Z direction), but this is not limiting.

[0118] The second buried insulating layer 220 can include various insulating materials. The second buried insulating layer 220 includes a different material than the first buried insulating layer 210. The second buried insulating layer 220 includes, but is not limited to, silicon oxide (SiO2). For example, the second buried insulating layer 220 includes silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), or a combination thereof.

[0119] The third buried insulating layer 230 is located between the first buried insulating layer 210 and the lower pattern BP. For example, the third buried insulating layer 230 is located between the first buried insulating layer 210 and the first lower pattern BP1 and between the first buried insulating layer 210 and the second lower pattern BP2. The third buried insulating layer 230 is formed to a uniform thickness on a portion of the side surface and the lower surface of the first buried insulating layer 210. The third buried insulating layer 230 contacts the side surface of the first buried insulating layer 210 and the side surface of the lower pattern BP.

[0120] In one embodiment, the third buried insulating layer 230 includes the same material as the second buried insulating layer 220. The third buried insulating layer 230 is formed in the same process as the second buried insulating layer 220. For example, the third buried insulating layer 230 may include, but is not limited to, silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), or a combination thereof.

[0121] According to an embodiment, a semiconductor device includes a plurality of second buried insulating layers 220, each protruding in the second direction (Y direction) from a side surface of the first buried insulating layer 210. A channel pattern NS is located on the side surface of the protruding second buried insulating layer 220, and a gate dielectric layer 132 is located on the upper and lower surfaces of the channel pattern NS and the upper and lower surfaces of the second buried insulating layer 220. An extension 132_E of the gate dielectric layer 132 is formed directly on the side surface of the first buried insulating layer 210 where the second buried insulating layer 220 is not located. At this time, the width of the extension 132_E of the gate dielectric layer 132 is smaller than or equal to the second width D2 of the second buried insulating layer 220, thereby increasing the area in which the gate electrode 120 formed on the gate dielectric layer 132 surrounds the channel pattern NS.

[0122] On the other hand, when the second buried insulating layer 220 is positioned on the entire side surface of the first buried insulating layer 210, the extension 132_E of the gate dielectric layer 132 is formed directly on the side surface of the first buried insulating layer 210. In this case, the extension 132_E of the gate dielectric layer 132 overlaps with the channel pattern NS in the third direction (Z direction), thereby relatively reducing the area in which the gate electrode 120 formed on the gate dielectric layer 132 surrounds the channel pattern NS. In other words, compared to when the second buried insulating layer 220 is positioned on the entire side surface of the first buried insulating layer 210, the area in which the channel pattern NS is surrounded by the gate electrode 120 in the semiconductor device according to the embodiment is increased, thereby improving the reliability of the semiconductor device.

[0123] Semiconductor devices according to several embodiments will be described below with reference to FIGS.

[0124] 9 to 12 are cross-sectional views corresponding to the R2 region of FIG. 7, showing a semiconductor device according to some embodiments. FIG. 13 is a cross-sectional view corresponding to the Q1 region of FIG. 2, showing a semiconductor device according to some embodiments. FIG. 14 is an enlarged cross-sectional view of the R3 region of FIG. 13. FIG. 15 is a cross-sectional view corresponding to the Q2 region of FIG. 3, showing a semiconductor device according to some embodiments.

[0125] The embodiment shown in FIGS. 9 to 15 corresponds to the same parts as the embodiment shown in FIGS. 1 to 8, so a description thereof will be omitted and the differences will be mainly described.

[0126] 9 and 10, the second buried insulating layer 220 of the semiconductor device according to some embodiments may have various shapes.

[0127] 9, the upper surface 220_S and the lower surface of the second buried insulating layer 220 include curved surfaces. The upper surface of the second buried insulating layer 220 includes, but is not limited to, a curved surface recessed toward the first buried insulating layer 210. In this case, the thickness of the second buried insulating layer 220 along the third direction (Z direction) is greater than the thickness of the channel pattern NS along the third direction (Z direction). Here, the thickness of the second buried insulating layer 220 along the third direction (Z direction) refers to the maximum length of the second buried insulating layer 220 along the third direction (Z direction).

[0128] 10, the upper and lower surfaces of the second buried insulating layer 220 extend in a direction parallel to the upper and lower surfaces of the channel pattern NS. For example, the upper and lower surfaces of the second buried insulating layer 220 extend along the second direction (Y direction), but are not limited thereto. In this case, the thickness of the second buried insulating layer 220 along the third direction (Z direction) is substantially the same as the thickness of the channel pattern NS along the third direction (Z direction). Here, the thickness of the second buried insulating layer 220 along the third direction (Z direction) refers to the maximum length of the second buried insulating layer 220 along the third direction (Z direction). In this case, the second width D2 of the second buried insulating layer 220 along the second direction (Y direction) is greater than or equal to the first width D1 of the gate dielectric layer 132 along the second direction (Y direction).

[0129] 11, a semiconductor device according to some embodiments does not include a second buried insulating layer 220. In this case, a gate dielectric layer 132 is located between the first buried insulating layer 210 and the channel pattern NS. That is, the gate dielectric layer 132 surrounds the top, bottom, and both side surfaces of the channel pattern NS. The gate dielectric layer 132 surrounds all four sides of the channel pattern NS. The gate dielectric layer 132 is also located on the side surfaces of the first buried insulating layer 210. This is due to the process characteristics of forming the second buried insulating layer 220, in which after forming a material layer for forming the second buried insulating layer 220, the material layer is completely removed in the process of removing at least a portion of the material layer.

[0130] 12, an insulating structure 200 of a semiconductor device according to some embodiments further includes a fourth buried insulating layer 240 located on the second buried insulating layer 220. In an exemplary embodiment, the width of the second buried insulating layer 220 along the third direction (Z direction) is smaller than the width of the channel pattern NS along the third direction (Z direction).

[0131] The fourth buried insulating layer 240 is located on the upper and lower surfaces of the second buried insulating layer 220. The fourth buried insulating layer 240 is located between the second buried insulating layer 220 and the gate dielectric layer 132. The fourth buried insulating layer 240 is located between the channel pattern NS and the first buried insulating layer 210. The fourth buried insulating layer 240 contacts the second buried insulating layer 220 and the gate dielectric layer 132. In some embodiments, the fourth buried insulating layer 240 is part of an iner gate spacer material layer formed during the process of forming the iner gate spacer 135.

[0132] In some embodiments, the fourth buried insulating layer 240 includes the same material as the iner gate spacer 135, and the fourth buried insulating layer 240 is formed together with the iner gate spacer 135 in the same process. For example, the fourth buried insulating layer 240 includes a first material, a second material, and a third material different from the first material and the second material, where the first material and the second material are silicon (Si) and germanium (Ge), which constitute the first source / drain layer 151. The third material is oxygen (O).

[0133] 13 and 14, an iner gate spacer 135 of a semiconductor device according to some embodiments includes a first portion 135_P1 embedded in a source / drain pattern 150 and a second portion 135_P2 protruding from a side of the source / drain pattern 150.

[0134] The first portion 135_P1 is buried in the first source / drain layer 151. For example, the first portion 135_P1 protrudes from a reference axis SX connecting a side surface NSa_S of one of the channel patterns NSa and a side surface NSb_S of another channel pattern NSb adjacent to the one of the channel patterns NSa in the third direction (Z direction) toward the source / drain pattern 150. The first portion 135_P1 is located in the first source / drain layer 151. At this time, the reference axis SX is inclined at a predetermined angle from the third direction (Z direction), but is not limited to this and may extend in a direction parallel to the third direction (Z direction). In addition, the second portion 135_P2 protrudes from the reference axis SX toward the gate structure GS in the second direction (Y direction).

[0135] The first portion 135_P1 and the second portion 135_P2 may include various insulating materials. The first portion 135_P1 and the second portion 135_P2 include an insulating material including a first material and a second material. For example, the first portion 135_P1 and the second portion 135_P2 include a first material, a second material, and a third material different from the first material and the second material. Here, the first material and the second material are silicon (Si) and germanium (Ge), which constitute the first source / drain layer 151. The third material is oxygen (O).

[0136] In some embodiments, the content (at %) of the third material in the first portion 135_P1 is less than or equal to the content (at %) of the third material in the second portion 135_P2 due to the process characteristics of forming the iner gate spacer 135 from the interface of the first source / drain layer 151 through an oxidation process.

[0137] 15, in some embodiments, the upper surface 210U of the insulating structure 200 of the semiconductor device is located at substantially the same level as the upper surface of the gate structure GS. That is, the upper surface 210U of the insulating structure 200 is located at substantially the same distance from the upper surface of the gate structure GS and the upper surface of the substrate 100. The insulating structure 200 does not protrude into the capping layer 145. The upper surface 210U of the insulating structure 200 is coplanar with the upper surface of the gate structure GS.

[0138] Hereinafter, a method for manufacturing a semiconductor device according to an embodiment will be described with reference to FIGS. 16a to 52b.

[0139] 16a to 52b are cross-sectional views of intermediate stages illustrating a method for manufacturing a semiconductor device according to an embodiment. Specifically, FIGS. 16a, 17a, 26a, 27a, 28a, 29 to 32, 34a, 35a, 36a, 37a, 38a, 42a, 45a, 48a, 49a, 51a, and 52a are cross-sectional views corresponding to A-A' in FIG. 1 illustrating a method for manufacturing a semiconductor device according to an embodiment. FIGS. 16b, 17b, 18 to 25, 26b, 27b, 28b, 34b, 35b, 36b, 37b, 38b, 40, 42b, 45b, 48b, 49b, 51b, and 52b are cross-sectional views corresponding to B-B' in FIG. 1 illustrating a method for manufacturing a semiconductor device according to an embodiment. FIG. 33 is an enlarged cross-sectional view of region S1 in FIG. 32. FIG. 39 is an enlarged cross-sectional view of region U1 in FIG. 38b. FIG. 41 is an enlarged cross-sectional view of region U2 in FIG. 40. FIG. 43 is an enlarged cross-sectional view of region S2 in FIG. 42a. FIG. 44 is an enlarged cross-sectional view of region U3 in FIG. 42b. FIG. 46 is an enlarged cross-sectional view of region S3 in FIG. 45a. FIG. 47 is an enlarged cross-sectional view of region U4 in FIG. 45b. FIG. 50 is an enlarged cross-sectional view of region U5 in FIG. 49b.

[0140] 16a and 16b, a channel pattern structure U_AP, a first protective layer 271, and a second protective layer 272 are formed on a substrate 100. The channel pattern structure U_AP includes a plurality of gate sacrificial patterns SC_L and a plurality of semiconductor patterns ACT_L that are alternately stacked.

[0141] The substrate 100 may be silicon-on-insulator (SOI) or bulk silicon. Alternatively, the substrate 100 may be a silicon substrate or other materials, including, but not limited to, silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0142] The channel pattern structure U_AP is located on the substrate 100. A plurality of gate sacrificial patterns SC_L and a plurality of semiconductor patterns ACT_L are sequentially stacked to form the channel pattern structure U_AP. Although four gate sacrificial patterns SC_L and four semiconductor patterns ACT_L are alternately stacked in FIGS. 16a and 16b, this is merely an example and may be modified in various ways. That is, the number of stacked gate sacrificial patterns SC_L and the number of stacked semiconductor patterns ACT_L may be less than four or more than four, respectively.

[0143] The channel pattern structure U_AP is formed using an epitaxial growth method. For example, layers made of silicon germanium (SiGe) and layers made of silicon (Si) are alternately formed using the epitaxial growth method. Next, a first protective layer 271 and a second protective layer 272 are formed on the channel pattern structure U_AP. The first protective layer 271 includes, for example, silicon oxide (SiO2), and the second protective layer 272 includes, for example, but is not limited to, polycrystalline silicon.

[0144] As shown in FIGS. 17a and 17b, a third protective layer 273 and a fourth protective layer 274 are sequentially formed on the second protective layer 272 to form a first trench TR1.

[0145] The fourth protective layer 274 functions as a hard mask pattern. The fourth protective layer 274 is made of silicon nitride (SiN). The silicon germanium (SiGe) layer and the silicon layer are patterned using the fourth protective layer 274 as a mask to form a first trench TR1.

[0146] The channel pattern structures U_AP are separated from one another in the second direction (Y direction) by the first trenches TR1. Accordingly, the channel pattern structures U_AP extend in the first direction (X direction). The gate sacrificial patterns SC_L are made of silicon germanium (SiGe), and the semiconductor patterns ACT_L are made of silicon (Si). However, the present invention is not limited thereto, and the materials of the gate sacrificial patterns SC_L and the semiconductor patterns ACT_L may be variously changed.

[0147] By forming the first trench TR1, at least a portion of the substrate 100 is etched to form a lower pattern BP, on which a channel pattern structure U_AP is located.

[0148] As shown in FIG. 18, a second preliminary buried insulating layer 220P is formed in the first trench TR1.

[0149] A second preliminary buried insulating layer 220P is formed on the substrate 100, the channel pattern structure U_AP, and the first to fourth protective layers 271 to 274. Specifically, the second preliminary buried insulating layer 220P is formed on the upper surface of the substrate 100 exposed by the first trench TR1, the side surfaces of the lower pattern BP, and the side surfaces of the channel pattern structure U_AP. The second preliminary buried insulating layer 220P is also formed on the side surfaces of the first to fourth protective layers 271 to 274 and the upper surface of the fourth protective layer 274. The second preliminary buried insulating layer 220P is formed to a uniform thickness on the upper surface of the substrate 100, the side surfaces of the lower pattern BP, and the side surfaces of the channel pattern structure U_AP. The second preliminary buried insulating layer 220P includes the same material as the first protective layer 271 and the third protective layer 273. For example, the second preliminary buried insulating layer 220P may include, but is not limited to, silicon nitride (SiN).

[0150] 19, a first preliminary buried insulating layer 210P is formed in the first trench TR1. In one embodiment, the width of the first trench TR1 is narrowed so that the first preliminary buried insulating layer 210P fills the first trench TR1. For example, the width of the first trench TR1 is 15 to 25 nm.

[0151] The first preliminary buried insulating layer 210P includes a low-k material. The first preliminary buried insulating layer 210P includes a material having a different etching selectivity with respect to the second preliminary buried insulating layer 220P and the semiconductor pattern ACT_L. For example, the first preliminary buried insulating layer 210P includes at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), and a low-k material, but is not limited thereto.

[0152] 20, an etching process is performed to remove at least a portion of the second pre-buried insulating layer 220P. The etching process may be performed by dry or wet etching, but is not limited thereto. The etching process is performed using a material having an etching selectivity with respect to the first pre-buried insulating layer 210P. As a result, the remaining portion of the second pre-buried insulating layer 220P except for the portion located in the first trench TR1 is removed. As a result, the second pre-buried insulating layer 220P is located along the bottom surface and sidewalls of the first trench TR1.

[0153] As shown in FIGS. 21 and 22, a field insulating layer 105 is formed between the plurality of channel pattern structures U_AP.

[0154] 21, a field insulating layer 105 is formed on a substrate 100 on which a lower pattern BP and a channel pattern structure U_AP are formed. The field insulating layer 105 is formed between the plurality of channel pattern structures U_AP. The field insulating layer 105 covers the lower pattern BP, the channel pattern structure U_AP, and all of the side surfaces of the first to fourth protective layers 271 to 274. Next, a chemical mechanical polishing (CMP) process is additionally performed to planarize the top surface of the fourth protective layer 274, the top surface of the first preliminary buried insulating layer 210P, and the top surface of the field insulating layer 105. As a result, at least a portion of the first preliminary buried insulating layer 210P is planarized, forming the first buried insulating layer 210.

[0155] 22, at least a portion of the field insulating layer 105 is etched. The etching process may be performed by, but is not limited to, a dry or wet etching method. This reduces the thickness of the field insulating layer 105 in the third direction (Z direction). The field insulating layer 105 covers a portion of the side surface of the lower pattern BP, but is not limited to this. For example, the field insulating layer 105 may cover the entire side surface of the lower pattern BP.

[0156] The field insulating layer 105 is made of an insulating material that fills voids well. For example, the field insulating layer 105 may include, but is not limited to, silicon dioxide (SiO2). By way of example, the field insulating layer 105 may include silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof. While the field insulating layer 105 is shown as a single layer, this is for convenience of illustration only and is not limiting.

[0157] As shown in FIG. 23, a preliminary gate insulating film EG is formed on the field insulating layer 105 and the channel pattern structure U_AP.

[0158] Specifically, a preliminary gate insulating film EG is formed on the upper surface of the field insulating layer 105, the side surfaces of the channel pattern structure U_AP, the side surfaces of the first to fourth protective layers 271 to 274, and the upper surface of the fourth protective layer 274. The preliminary gate insulating film EG is conformally formed along the upper surface of the field insulating layer 105, the side surfaces of the channel pattern structure U_AP, the side surfaces of the first to fourth protective layers 271 to 274, and the upper surface of the fourth protective layer 274. The preliminary gate insulating film EG includes the same material as the first preliminary buried insulating layer 210P. The preliminary gate insulating film EG also includes the same material as the first protective layer 271 and the third protective layer 273, but is not limited to this. The preliminary gate insulating film EG includes, for example, silicon oxide (SiO2), but is not limited to this.

[0159] As shown in FIGS. 24 and 25, a sacrificial planarization layer PP is formed on the field insulating layer 105, and the fourth protective layer 274 and the third protective layer 273 are removed.

[0160] 24, a sacrificial planarization layer PP is formed on the field insulating layer 105. That is, the sacrificial planarization layer PP is formed to fill the spaces between the plurality of channel pattern structures U_AP. The sacrificial planarization layer PP is a layer for performing a subsequent planarization process. The sacrificial planarization layer PP may include, but is not limited to, polycrystalline silicon.

[0161] 25, a chemical mechanical polishing (CMP) process is performed to remove the fourth protective layer 274 and the third protective layer 273. At this time, the top surface of the sacrificial planarization layer PP is also planarized. In addition, the top surfaces of the second protective layer 272 and the first buried insulating layer 210 are also planarized, but this is not limiting.

[0162] 26a and 26b, the sacrificial planarization layer PP and the second protective layer 272 are removed. As described above, since the sacrificial planarization layer PP and the second protective layer 272 are made of the same material, they are both removed using an etching process. The process of removing the sacrificial planarization layer PP and the second protective layer 272 may be performed by a dry or wet etching method, but is not limited thereto. At this time, a portion of the preliminary gate insulating film EG located between the sacrificial planarization layer PP and the second protective layer 272 is removed. As a result, the top surface of the first buried insulating layer 210 and the top and side surfaces of the preliminary gate insulating film EG are exposed.

[0163] As shown in FIGS. 27a and 27b, a preliminary main gate electrode 120MP and a preliminary capping layer 120_HM are formed on the preliminary gate insulating film EG.

[0164] A preliminary main gate electrode 120MP and a preliminary capping layer 120_HM are formed on the channel pattern structure U_AP. In a plan view, the extension directions of the preliminary main gate electrode 120MP and the preliminary capping layer 120_HM intersect with the extension direction of the channel pattern structure U_AP. The preliminary main gate electrode 120MP and the preliminary capping layer 120_HM extend in a second direction (Y direction) perpendicular to the first direction (X direction). The preliminary main gate electrodes 120MP are positioned to be spaced apart at a predetermined interval along the first direction (X direction).

[0165] 28a and 28b, first preliminary gate spacers 141P and second preliminary gate spacers 140P are sequentially formed on both side surfaces of the preliminary main gate electrode 120MP, both side surfaces of the preliminary capping layer 120_HM, and the top surface of the preliminary capping layer 120_HM. The first preliminary gate spacers 141P are conformally formed along the profiles of both side surfaces of the preliminary main gate electrode 120MP, both side surfaces of the preliminary capping layer 120_HM, the top surface of the preliminary capping layer 120_HM, and the top surface of the uppermost semiconductor pattern ACT_L. The second preliminary gate spacers 140P are conformally formed along the profile of the first preliminary gate spacer 141P. The first preliminary gate spacers 141P and second preliminary gate spacers 140P are formed using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or the like. The first preliminary gate spacer 141P and the second preliminary gate spacer 140P may include different materials, but are not limited thereto, and may include the same material.

[0166] As shown in FIG. 29, at least a portion of the channel pattern structure U_AP is recessed to form a source / drain recess 150R.

[0167] First, an etching process is performed to sequentially etch at least a portion of the exposed first preliminary gate spacer 141P and second preliminary gate spacer 140P. The etching process may be, but is not limited to, a dry etching process. As the etching process is performed, portions of the first preliminary gate spacer 141P and second preliminary gate spacer 140P located between adjacent preliminary main gate electrodes 120MP are removed. This exposes a portion of the top surface of the channel stack structure U_AP. For example, the top surface of the uppermost semiconductor pattern ACT_L is exposed. At this time, portions of the first preliminary gate spacer 141P and second preliminary gate spacer 140P located on the top surface of the preliminary capping layer 120_HM are also etched.

[0168] Next, using the preliminary main gate electrode 120MP and the preliminary gate spacer 140P as a mask, at least a portion of the channel pattern structure U_AP is etched to form the source / drain recess 150R.

[0169] The source / drain recesses 150R are formed to separate the semiconductor patterns ACT_L, thereby forming channel patterns NS. The channel patterns NS are located on both sides of the source / drain recesses 150R. The channel patterns NS and the sacrificial patterns SC_L are alternately stacked.

[0170] As shown in FIG. 30, at least a portion of the sacrificial pattern SC_L exposed by the source / drain recess 150R is etched.

[0171] The process of etching at least a portion of the sacrificial pattern SC_L is performed using, but not limited to, a wet etching method. The process of etching at least a portion of the sacrificial pattern SC_L is performed using an etchant having an etching selectivity with respect to the channel pattern NS. As a result, the channel pattern NS is not etched, but at least a portion of the sacrificial pattern SC_L is etched. A recess pattern RC is formed in the source / drain recess 150R from a side of the channel pattern NS along the first direction (X direction).

[0172] 31, a first source / drain layer 151 is formed in the source / drain recess 150R. The first source / drain layer 151 is formed using an epitaxial growth method. The first source / drain layer 151 is formed conformally along the profile of the recess pattern RC formed in the source / drain recess 150R.

[0173] In one embodiment, the first source / drain layer 151 includes a first material, which is a semiconductor material, and a second material different from the first material. Here, the first material is silicon (Si), and the second material is germanium (Ge). That is, the first source / drain layer 151 includes silicon germanium (SiGe). In this case, the content (at %) of the second material in the first source / drain layer 151 is 5 at % to 20 at %. Within this range, the inner gate spacer 135 (135 in FIG. 45a) can be easily formed by utilizing the difference in the degree of oxidation between the interface of the first source / drain layer 151 and the interface of the channel pattern NS during the process of forming the inner gate spacer 135 through an oxidation process.

[0174] 32 and 33, a second source / drain layer 152 is formed on the first source / drain layer 151. The second source / drain layer 152 fills the portion of the source / drain recess 150R where the first source / drain layer 151 is formed and remains. The second source / drain layer 152 is formed using an epitaxial growth method.

[0175] In one embodiment, the second source / drain layer 152 includes a semiconductor material. The second source / drain layer 152 includes a first material and / or a second material. The type of material included in the second source / drain layer 152 varies depending on whether the semiconductor device according to one embodiment is an N-type MOSFET or a P-type MOSFET.

[0176] For example, if the semiconductor device according to one embodiment is an N-type device, the second source / drain layer 152 includes a first material but does not include a second material. Here, the first material is silicon (Si) and the second material is germanium (Ge). In this case, the first source / drain layer 151 and / or the second source / drain layer 152 include N-type impurities. For example, the first source / drain layer 151 and the second source / drain layer 152 include P, Sb, As, or a combination thereof. The concentration of the impurities doped into the first source / drain layer 151 may be different from the concentration of the impurities doped into the second source / drain layer 152. For example, the concentration of the N-type impurities doped into the second source / drain layer 152 may be greater than the concentration of the N-type impurities doped into the first source / drain layer 151, but is not limited to this.

[0177] As another example, if the semiconductor device according to an embodiment is a P-type device, the second source / drain layer 152 includes a first material and a second material. That is, the second source / drain layer 152 includes the same material as the first source / drain layer 151. In this case, the concentrations of the constituent materials of the second source / drain layer 152 and the first source / drain layer 151 may be different. For example, if the second source / drain layer 152 and the first source / drain layer 151 include silicon germanium (SiGe), the germanium (Ge) concentration of the second source / drain layer 152 may be higher than the germanium (Ge) concentration of the first source / drain layer 151, but is not limited to this. In addition, the first source / drain layer 151 and / or the second source / drain layer 152 includes P-type impurities. As an example, the first source / drain layer 151 and the second source / drain layer 152 include B, V, In, Ga, Al, or a combination thereof. The concentration of the impurity doped into the first source / drain layer 151 may be different from the concentration of the impurity doped into the second source / drain layer 152. For example, the concentration of the P-type impurity doped into the second source / drain layer 152 may be higher than the concentration of the P-type impurity doped into the first source / drain layer 151, but is not limited thereto.

[0178] As shown in FIGS. 34a and 34b, an etch stop layer 185 and an interlayer insulating layer 190 are sequentially formed on the source / drain pattern 150. As shown in FIGS.

[0179] The etch stop layer 185 is formed to a uniform thickness on the top surfaces of the source / drain patterns 150, the side surfaces of the second preliminary gate spacers 140P, and the top surface of the preliminary capping layer 120_HM. The interlayer insulating layer 190 is positioned on the etch stop layer 185. The interlayer insulating layer 190 fills the spaces between the preliminary main gate electrodes 120MP adjacent to each other in the first direction (X direction).

[0180] 35a and 35b, at least a portion of the interlayer insulating layer 190 is removed, and an interlayer capping layer 192 is formed in the removed space. Next, a portion of the interlayer capping layer 192 and the preliminary capping layer 120_HM are etched to expose the top surface of the preliminary main gate electrode 120MP. At this time, a portion of the first preliminary gate spacer 141P and a portion of the second preliminary gate spacer 140P are also removed, forming the sub-gate spacer 141 and the gate spacer 140.

[0181] 36a and 36b, the preliminary main gate electrode 120MP is removed to form a second trench TR2. During the process of forming the second trench TR2, the sub-gate spacer 141 is also removed, and a portion of the gate spacer 140 is also removed. The sidewalls of the second trench TR2 are defined by the gate spacer 140 and the etch stop layer 185. This exposes the preliminary gate insulating film EG.

[0182] 37a, 37b, 38a, 38b, and 39, the preliminary gate insulating film EG is removed to expose the channel pattern structure U_AP between the gate spacers 140. Next, the plurality of gate sacrificial patterns SC_L located between the channel patterns NS are removed to form gate trenches 120t between the channel patterns NS. The channel patterns NS are exposed by the gate trenches 120t.

[0183] In one embodiment, the gate trench 120t exposes at least a portion of the insulating structure 200. For example, as shown in Fig. 39, the gate trench 120t exposes a portion of the side surface of the second preliminary buried insulating layer 220P on a cross section formed in the second direction (Y direction) and the third direction (Z direction). Specifically, the side surface of the second preliminary buried insulating layer 220P that overlaps with the channel pattern NS in the second direction (Y direction) is not exposed, and the side surface of the second preliminary buried insulating layer 220P that does not overlap with the channel pattern NS in the second direction (Y direction) is exposed.

[0184] As shown in FIGS. 40 and 41, at least a portion of the exposed second preliminary buried insulating layer 220P is removed.

[0185] The portion of the second preliminary buried insulating layer 220P that does not overlap the channel pattern NS in the second direction (Y direction) is etched. The portion of the second preliminary buried insulating layer 220P that overlaps the channel pattern NS in the second direction (Y direction) is not etched. Furthermore, the portion of the second preliminary buried insulating layer 220P located between the lower pattern BP and the first buried insulating layer 210 is not etched. The process of removing at least a portion of the second preliminary buried insulating layer 220P is performed by, but is not limited to, wet etching. The second preliminary buried insulating layer 220P includes a material that has an etching selectivity with respect to the first buried insulating layer 210, the lower pattern BP, and the channel pattern NS. Therefore, the first buried insulating layer 210, the lower pattern BP, and the channel pattern NS are not etched during the etching of the second preliminary buried insulating layer 220P.

[0186] As a result, the second preliminary buried insulating layer 220P is patterned to form the second buried insulating layer 220. A plurality of second buried insulating layers 220 are provided and arranged spaced apart in the third direction (Z direction). Specifically, the second buried insulating layer 220 is located between each channel pattern NS and the first buried insulating layer 210, but is not located between the first buried insulating layer 210 and a gate structure GS located between adjacent channel patterns NS in the third direction (Z direction). In other words, the second buried insulating layer 220 is located on one side of each channel pattern NS in the second direction (Y direction), but is not located on one side in the second direction (Y direction) of the gate structure GS located between adjacent channel patterns NS in the third direction (Z direction).

[0187] In addition, the second preliminary buried insulating layer 220P is patterned to form a third buried insulating layer 230 between the lower pattern BP and the first buried insulating layer 210. The third buried insulating layer 230 includes the same material as the first buried insulating layer 210. In addition, a portion of the side surface of the first buried insulating layer 210 is exposed.

[0188] As shown in Figures 42a and 42b, an inner gate spacer material layer 135P is formed in the gate trench 120t.

[0189] Specifically, an inner gate spacer material layer 135P is formed on the upper and lower surfaces of the channel pattern NS exposed by the gate trench 120t and on the side surfaces of the first source / drain layer 151. The inner gate spacer material layer 135P is formed through an oxidation process that oxidizes the exposed interface of the channel pattern NS and the exposed interface of the first source / drain layer 151.

[0190] 43, in one embodiment, the channel pattern NS and the first source / drain layer 151 contain different materials, resulting in different rates of formation of the iner gate spacer material layer 135P at their interface. For example, the channel pattern NS contains a first material, and the first source / drain layer 151 contains a first material and a second material. Here, the first material is silicon (Si) and the second material is germanium (Ge). In this embodiment, the first source / drain layer 151 further contains a second material different from the first material constituting the channel pattern NS, resulting in a greater degree of oxidation at the interface of the first source / drain layer 151 than at the interface of the channel pattern NS.

[0191] Thus, the iner gate spacer material layer 135P includes horizontal portions 135P_H located on the upper and lower surfaces of the channel pattern NS and vertical portions 135P_V located on the side surfaces of the first source / drain layer 151, and the thickness of the horizontal portions 135P_H is smaller than the thickness of the vertical portions 135P_V. For example, the thickness of the horizontal portions 135P_H is 0.5 nm to 1.5 nm, and the thickness of the vertical portions 135P_V is 1.5 nm to 4.5 nm, but is not limited thereto.

[0192] The inner gate spacer material layer 135P may include various insulating materials. The inner gate spacer material layer 135P includes an insulating material containing a first material and a second material. For example, the inner gate spacer material layer 135P includes a first material, a second material, and a third material different from the first and second materials. Here, the first and second materials are silicon (Si) and germanium (Ge), which constitute the first source / drain layer 151. The third material is oxygen (O). That is, according to one embodiment, the inner gate spacer material layer 135P of the semiconductor device includes silicon oxide (SiO2) containing germanium (Ge). This is due to the process characteristics of forming the inner gate spacer material layer 135P by oxidizing the interface of the first source / drain layer 151. In addition, in one embodiment, the content of the third material included in the inner gate spacer material layer 135P decreases with increasing distance from the side of the first source / drain layer 151, but is not limited thereto. That is, when the iner gate spacer material layer 135P includes silicon oxide (SiO2) containing germanium (Ge) elements, the content of oxygen (O) that bonds with silicon (Si) and / or germanium (Ge) decreases with increasing distance from the side of the first source / drain layer 151.

[0193] 44, at this time, the exposed side surfaces of the first buried insulating layer 210 are not oxidized because the first buried insulating layer 210 includes a material that is not oxidized during the oxidation process, different from the channel pattern NS and the first source / drain layer 151. For example, the first buried insulating layer 210 includes, but is not limited to, silicon nitride (SiN).

[0194] As shown in FIGS. 45a and 45b, the iner gate spacer material layer 135P is patterned to form iner gate spacers 135. As shown in FIGS.

[0195] The process of patterning the inner gate spacer material layer 135P is performed using, but is not limited to, a wet etching method. The inner gate spacer material layer 135P includes a material having an etching selectivity with respect to the channel pattern NS, the first source / drain layer 151, and the first buried insulating layer 210. Therefore, even when an etching process is performed, the inner gate spacer material layer 135P is patterned, but the channel pattern NS, the first source / drain layer 151, and the first buried insulating layer 210 are not removed.

[0196] 46 and 47, as described above, the thickness of the horizontal portion (135P_H in FIG. 43) of the iner gate spacer material layer 135P is smaller than the thickness of the vertical portion (135P_V in FIG. 43) of the iner gate spacer material layer 135P. Therefore, when performing an etching process, the horizontal portion (135P_H in FIG. 43) of the iner gate spacer material layer 135P is removed first. Therefore, as shown in FIG. 46, at least a portion of the vertical portion (135P_V in FIG. 43) of the iner gate spacer material layer 135P remains, forming the iner gate spacer 135 located on the first source / drain layer 151.

[0197] Meanwhile, as shown in FIG. 47, the iner gate spacer material layer 135P portions located around the first buried insulating layer 210 and the second buried insulating layer 220 are removed.

[0198] As shown in Figures 48a and 48b, a gate insulating film 131 is formed in the gate trench 120t. The gate insulating film 131 is formed on the upper and lower surfaces of the channel pattern NS. The gate insulating film 131 is also formed on the upper and side surfaces of the lower pattern BP.

[0199] As shown in Figures 49a and 49b, a gate dielectric layer 132 is formed in the gate trench 120t. The gate dielectric layer 132 is formed on the gate insulating film 131. The gate insulating film 131 is formed using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or the like.

[0200] 50, in one embodiment, a gate dielectric layer 132 is formed on both the first buried insulating layer 210 and the second buried insulating layer 220. That is, the gate dielectric layer 132 surrounds the channel pattern NS, the first buried insulating layer 210, and the second buried insulating layer 220.

[0201] As shown in Figures 51a and 51b, the gate electrode 120 is formed on the gate dielectric layer 132. Next, the interlayer capping layer 192 is removed, and the thickness of the interlayer insulating layer 190 is reduced. Next, at least a portion of the gate structure GS is removed, and the capping layer 145 is formed. At this time, the capping layer 145 includes at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. Finally, the interlayer insulating layer 190, the etch stop film 185, and the capping layer 145 are etched to reduce their thicknesses.

[0202] As shown in FIGS. 52a and 52b, an upper insulating layer 195 is formed on the interlayer insulating layer 190, the etch stop layer 185, and the capping layer 145 to form the semiconductor device according to FIGS.

[0203] Although the embodiments of the present invention have been described in detail above, the technical scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention also fall within the technical scope of the present invention. [Explanation of symbols]

[0204] 100 boards 120 gate electrode 121 First gate electrode 122 second gate electrode 130 Gate insulation pattern 131 Gate insulating film 132 Gate dielectric layer 140 Gate spacer BP Lower Pattern NS Channel Pattern GS Gate Structure 150 Source / Drain Pattern 135 Inergate Spacer 200 Insulation Structure 210 First buried insulating layer 220 Second buried insulating layer 230 Third buried insulating layer

Claims

1. A substrate; a first channel pattern and a second channel pattern located on the substrate and spaced apart from each other; an insulating structure located between the first channel pattern and the second channel pattern; a gate structure surrounding the first channel pattern, the second channel pattern, and at least a portion of the insulating structure; source / drain patterns located on both sides of the first channel pattern and the second channel pattern, The insulating structure comprises: a first buried insulating layer located between the first channel pattern and the second channel pattern and extending in a first direction; a second buried insulating layer located between the first buried insulating layer and the first channel pattern; The semiconductor device according to claim 1, wherein the portions of the second buried insulating layer are arranged at intervals from one another in the first direction.

2. a side surface of the second buried insulating layer contacts the first channel pattern; 2. The semiconductor device of claim 1, wherein the upper and lower surfaces of the second buried insulating layer contact the gate structure.

3. The gate structure includes: a gate insulating layer surrounding the first channel pattern and the second channel pattern; a gate dielectric layer surrounding the gate insulating layer; a gate electrode located on the gate dielectric layer; 2. The semiconductor device of claim 1, wherein the upper and lower surfaces of the second buried insulating layer contact the gate dielectric layer.

4. 2. The semiconductor device of claim 1, wherein the width of the second buried insulating layer in the first direction is equal to or smaller than the width of each of the first channel patterns in the first direction.

5. The gate structure includes: a gate insulating layer surrounding the first channel pattern and the second channel pattern; a gate dielectric layer surrounding the side surfaces of the gate insulating layer and the first buried insulating layer; a gate electrode located on the gate dielectric layer; 2. The semiconductor device of claim 1, wherein the upper and lower surfaces of the second buried insulating layer contact the gate dielectric layer.

6. 6. The semiconductor device of claim 5, wherein the thickness of the gate dielectric layer is less than or equal to the thickness of the second buried insulating layer.

7. 6. The semiconductor device according to claim 5, wherein at least a portion of a side surface of the first buried insulating layer is in contact with the second buried insulating layer, and the remaining portion is in contact with the gate dielectric layer.

8. The semiconductor device of claim 5 , wherein the second buried insulating layer does not overlap the gate insulating layer in the first direction.

9. a first lower pattern positioned between the substrate and the first channel pattern; a second lower pattern located between the substrate and the second channel pattern, 2. The semiconductor device of claim 1, wherein the first buried insulating layer is further located between the first lower pattern and the second lower pattern.

10. a third buried insulating layer located between the first lower pattern and the first buried insulating layer and between the second lower pattern and the first buried insulating layer; 10. The semiconductor device of claim 9, wherein the third buried insulating layer includes the same material as the first buried insulating layer.

11. the first channel pattern and the second channel pattern are spaced apart in a first direction; the source / drain patterns are located on both sides of the first channel pattern in a second direction intersecting the first direction, The semiconductor device of claim 1 , wherein the insulating structure extends along the second direction.

12. further comprising an inner gate spacer positioned between the source / drain pattern and the gate structure; 2. The semiconductor device of claim 1, wherein the first buried insulating layer comprises a material having an etching selectivity with respect to the iner gate spacer.

13. a side surface of the second buried insulating layer contacts the first channel pattern; 13. The semiconductor device of claim 12, wherein an upper surface and a lower surface of the second buried insulating layer contact the gate structure.

14. A substrate; a first lower pattern and a second lower pattern located on the substrate and spaced apart from each other; a first channel pattern located above the first lower pattern; a second channel pattern located above the second lower pattern; an insulating structure located between the first channel pattern and the second channel pattern; a gate structure surrounding the first channel pattern, the second channel pattern, and at least a portion of the insulating structure; a source / drain pattern including: a first source / drain layer located on the first lower pattern and including a first material and a second material different from the first material; and a second source / drain layer located on the first source / drain layer; an inner gate spacer located between the source / drain pattern and the gate structure; The semiconductor device, wherein the iner gate spacer includes the first material, the second material, and a third material different from the first material and the second material.

15. The semiconductor device of claim 14 , wherein the first source / drain layer contacts the iner gate spacer.

16. The semiconductor device of claim 15 , wherein the iner gate spacer includes a portion that protrudes toward the first source / drain layer.

17. 15. The semiconductor device of claim 14, wherein the first material comprises silicon, the second material comprises germanium, and the third material comprises oxygen.

18. 18. The semiconductor device of claim 17, wherein the content of the first material in the first source / drain layer is 5 at % to 20 at %.

19. The gate structure includes: a gate insulating layer surrounding the first channel pattern and the second channel pattern; a gate dielectric layer laterally surrounding the gate insulating layer and the insulating structure; a gate electrode located on the gate dielectric layer; 20. The semiconductor device of claim 18, wherein the gate dielectric layer contacts a side of the insulating structure.

20. A substrate; a first lower pattern and a second lower pattern located on the substrate and spaced apart from each other; a first channel pattern located above the first lower pattern; a second channel pattern located above the second lower pattern; an insulating structure located between the first channel pattern and the second channel pattern; a gate structure surrounding the first channel pattern and at least a portion of the second channel pattern; a source / drain pattern including: a first source / drain layer located on the first lower pattern and including a first material and a second material different from the first material; and a second source / drain layer located on the first source / drain layer; an inner gate spacer located between the source / drain pattern and the gate structure, the inner gate spacer including silicon oxide and germanium; The insulating structure comprises: a first buried insulating layer extending along a first direction and including a material having an etching selectivity with respect to the iner gate spacer; second buried insulating layers positioned between the first buried insulating layer and the first channel pattern and spaced apart from each other along the first direction; The semiconductor device, wherein the gate structure is located between the second buried insulating layers adjacent to each other along the first direction.

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