Integrated capacitor for image sensor

Abstract

The present invention relates to improving the quality of an image produced by a pixel circuit.SOLUTION: Some embodiments are directed to a device that includes a photodetector and a pixel circuit. The pixel circuit includes a floating diffusion node and an output node, a transfer transistor electrically coupled from the floating diffusion node to the photodetector, a source follower transistor including a gate electrode electrically coupled to the floating diffusion node, a row select transistor electrically coupled from a source / drain region of the source follower transistor to the output node, and a capacitor electrically coupled from the output node to the floating diffusion node.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates generally to integrated circuits having image sensors. [Background technology]

[0002] Integrated circuits (ICs) with image sensors are used in a wide range of modern electronic devices, such as cameras, mobile phones, etc. Types of image sensors include, for example, complementary metal-oxide semiconductor (CMOS) image sensors and charge-coupled device (CCD) image sensors. Compared with CCD image sensors, CMOS image sensors are increasingly preferred due to their low power consumption, small size, high-speed data processing, direct data output, and low manufacturing costs. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention relates generally to increasing the quality of images produced by image sensors. [Means for solving the problem]

[0004] In an embodiment of the present invention, the device includes a photodetector and a pixel circuit. The pixel circuit includes a floating diffusion node; an output node; a transfer transistor electrically coupled from the floating diffusion node to the photodetector; a source follower transistor including a gate electrode electrically coupled to the floating diffusion node; a row select transistor electrically coupled from the source / drain region of the source follower transistor to an output node; a capacitor electrically coupled from the output node to the floating diffusion node.

[0005] In an embodiment of the invention, the device comprises: a source follower transistor and a row select transistor on a first substrate, the row select transistor electrically coupled from the source follower transistor to an output node; a photodetector and a floating diffusion node in the second substrate; a transfer transistor electrically coupled on the second substrate from the photodetector to the floating diffusion node; a first interconnect structure and a second interconnect structure between the first substrate and the second substrate; a bond structure between the first interconnect structure and the second interconnect structure, the bond structure including a shield electrode and a bond electrode surrounding the shield electrode; A first interconnect structure electrically couples the shield electrode to the output node, and a second interconnect structure electrically couples the bond electrode to the floating diffusion node.

[0006] In an embodiment of the present invention, a method of forming a device comprises: forming an output stage on a first substrate, the output stage including a row select transistor electrically coupled from a source follower transistor to an output node; forming a first interconnect structure above the output stage, the first interconnect structure including a first conductive path electrically coupled to a gate electrode of the source follower transistor and a second conductive path electrically coupled to an output node; forming a first bond layer over the first interconnect structure, the first bond layer including a bond electrode and a shield electrode surrounding the bond electrode, the shield electrode being electrically coupled to the second conductive path; forming a photodetector in a second substrate; forming a transfer transistor on the second substrate, the transfer transistor electrically coupled from the photodetector to the floating diffusion node; forming a second interconnect structure over the transfer transistor, the second interconnect structure including a third conductive path electrically coupled to the floating diffusion node; Bonding the second interconnect structure to the first interconnect structure via the first bond layer, the bonding including electrically coupling the first conductive path and the third conductive path via the bond electrode. [Effects of the Invention]

[0007] Based on the above, at least one of a capacitor and a bond structure is formed on the device. The parasitic capacitance of the image sensor is reduced. This reduction in perceived capacitance reduces the RC delay of the image sensor, increasing the gain and bandwidth of the image sensor in low-information applications. The quality of the image produced by the image sensor is improved. [Brief explanation of the drawings]

[0008] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, various features have not been drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] [Figure 1A] 1A-1C are circuit diagrams of some embodiments of an image sensor having a capacitor between the output node and the floating diffusion node. [Figure 1B] 1A-1C are circuit diagrams of some embodiments of an image sensor having a capacitor between the output node and the floating diffusion node. [Figure 1C] 1A-1C are circuit diagrams of some embodiments of an image sensor having a capacitor between the output node and the floating diffusion node. [Figure 2] 1A-1C are cross-sectional views of the output stage of some embodiments of an image sensor having a capacitor between the output node and the floating diffusion node. [Figure 3]1A-1C are circuit diagrams of some embodiments of an image sensor having a capacitor between an output node and a floating diffusion node with multiple photodetectors coupled to the floating diffusion node. [Figure 4] 1A-1C are cross-sectional views of some embodiments of an image sensor having a shield structure and metal bond pad configured as a capacitor coupled between an output node and a floating diffusion node. [Figure 5A] 1A-1C are top views of several embodiments of multiple shielding structures and metal bond pads in an array of pixel circuits. [Figure 5B] 1A-1C are top views of several embodiments of multiple shielding structures and metal bond pads in an array of pixel circuits. [Figure 6] 1A-1C are a series of cross-sectional views of several embodiments of methods for forming an image sensor having a capacitor between an output node and a floating diffusion node, with a plurality of photodetectors coupled to the floating diffusion node. [Figure 7] 1A-1C are a series of cross-sectional views of several embodiments of methods for forming an image sensor having a capacitor between an output node and a floating diffusion node, with a plurality of photodetectors coupled to the floating diffusion node. [Figure 8] 1A-1C are a series of cross-sectional views of several embodiments of methods for forming an image sensor having a capacitor between an output node and a floating diffusion node, with a plurality of photodetectors coupled to the floating diffusion node. [Figure 9] 1A-1C are a series of cross-sectional views of several embodiments of methods for forming an image sensor having a capacitor between an output node and a floating diffusion node, with a plurality of photodetectors coupled to the floating diffusion node. [Figure 10] 1A-1C are a series of cross-sectional views of several embodiments of methods for forming an image sensor having a capacitor between an output node and a floating diffusion node, with a plurality of photodetectors coupled to the floating diffusion node. [Figure 11]1A-1C are a series of cross-sectional views of several embodiments of methods for forming an image sensor having a capacitor between an output node and a floating diffusion node, with a plurality of photodetectors coupled to the floating diffusion node. [Figure 12] 1A-1C are a series of cross-sectional views of several embodiments of methods for forming an image sensor having a capacitor between an output node and a floating diffusion node, with a plurality of photodetectors coupled to the floating diffusion node. [Figure 13] 1A-1C are a series of cross-sectional views of several embodiments of methods for forming an image sensor having a capacitor between an output node and a floating diffusion node, with a plurality of photodetectors coupled to the floating diffusion node. [Figure 14] 1A-1C are a series of cross-sectional views of several embodiments of methods for forming an image sensor having a capacitor between an output node and a floating diffusion node, with a plurality of photodetectors coupled to the floating diffusion node. [Figure 15] 1A-1C are a series of cross-sectional views of several embodiments of methods for forming an image sensor having a capacitor between an output node and a floating diffusion node, with a plurality of photodetectors coupled to the floating diffusion node. [Figure 16] 1A-1C are a series of cross-sectional views of several embodiments of methods for forming an image sensor having a capacitor between an output node and a floating diffusion node, with a plurality of photodetectors coupled to the floating diffusion node. [Figure 17] 1A-1C are a series of cross-sectional views of several embodiments of methods for forming an image sensor having a capacitor between an output node and a floating diffusion node, with a plurality of photodetectors coupled to the floating diffusion node. [Figure 18] 1A-1C are a series of cross-sectional views of several embodiments of methods for forming an image sensor having a capacitor between an output node and a floating diffusion node, with a plurality of photodetectors coupled to the floating diffusion node. [Figure 19] 1 is a flowchart of some embodiments of a method for forming an image sensor having a capacitor between an output node and a floating diffusion node. DETAILED DESCRIPTION OF THE INVENTION

[0010] The present invention provides many different embodiments, or examples, for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, or may include embodiments in which an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purposes of brevity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0012] It will be understood that in this written description, and in the claims that follow, terms such as "first," "second," "third," etc., are merely general identifiers used for ease of description to distinguish between different elements in a figure or series of figures. These terms do not, in themselves, imply any chronological order or structural proximity to these elements, and are not intended to describe corresponding elements in different illustrated and / or non-illustrated embodiments. For example, a "first dielectric layer" described in connection with a first figure does not necessarily correspond to a "first dielectric layer" described in connection with another figure, or even to a "first dielectric layer" in a non-illustrated embodiment.

[0013] The image sensor includes a pixel array having a plurality of photodetectors and a plurality of pixel circuits coupled to the photodetectors. The plurality of pixel circuits includes a floating diffusion node, a transfer transistor extending between the floating diffusion node and the photodetector, a reset transistor having a source / drain terminal coupled to the floating diffusion node, and an output stage coupled to the floating diffusion node. The output stage includes a source follower transistor having a gate electrode coupled to the floating diffusion node and a row select transistor having a first source / drain terminal coupled to the source / drain terminal of the source follower transistor. The output node is at the second source / drain terminal of the row select transistor. The plurality of pixel circuits are organized into a plurality of rows and columns, and each column of the plurality of pixel circuits has an output node coupled together by an output line.

[0014] In some embodiments, the image sensor spans multiple substrates bonded together through bond layers. The reset transistor and output stage are on a first substrate. The photodetector and floating diffusion node are in a second substrate bonded to the first substrate by a first bond layer. The floating diffusion node is coupled to the output stage through a metal bond pad in the first bond layer. A shield structure is also in the first bond layer and continuously surrounds the metal bond pad.

[0015] Total parasitic capacitance C on the output line tot is the pixel parasitic capacitance value C between the output nodes of multiple pixel circuits connected to the output line js The total capacity C tot increases the RC delay of the image sensor. The increased RC delay results in an increase in the time required to transfer the signal from the pixel circuit to the ISP circuit. The gain of the image sensor in low light environments (e.g., when using a conversion gain circuit to image an image area with a small amount of light) also increases the total capacitance C tot The RC delay further reduces the bandwidth of the image sensor. Therefore, the total capacitance C tot A method to mitigate this is desirable.

[0016] The present invention provides a capacitor included between the output node and the floating diffusion node. Applying Miller's theorem across the capacitor, an output stage with a gain less than unity will have a capacitance C H Therefore, the pixel parasitic capacitance value C js and C H The combination of the pixel parasitic capacitance value C js This result, when applied across a pixel circuit coupled to an output line, results in a reduction in the perceived capacitance seen by the output of the circuit. This reduction in perceived capacitance reduces the RC delay of the image sensor, increasing the gain and bandwidth of the image sensor in low-information applications (e.g., imaging areas with low amounts of light). Increasing the gain in low-information applications increases the dynamic range of the image sensor, resulting in an increase in the quality of the images produced by the image sensor.

[0017] 1A, 1B, and 1C illustrate circuit diagrams 100a, 100b, 100c of several embodiments of image sensors having a capacitor between the output node and the floating diffusion node.

[0018] The photodetector 102 is coupled to a pixel circuit 104. The pixel circuit 104 includes a floating diffusion node 106, a transfer transistor 108 extending between the floating diffusion node 106 and the photodetector 102, a reset transistor 110 having a source / drain terminal 112 coupled to the floating diffusion node 106, and an output stage 114 coupled to the floating diffusion node 106. The output stage 114 includes a source follower transistor 116 having a first gate electrode 118 coupled to the floating diffusion node 106 and a row select transistor 120 having a first source / drain terminal 122 coupled to a second source / drain terminal 124 of the source follower transistor 116. A third source / drain terminal 126 of the source follower transistor is coupled to the power supply rail Vdd. An output node 128 is coupled to a fourth source / drain terminal 130 of the row select transistor 120. An output line 140 is coupled to the output node 128 and a row select line 142 is coupled to the gate electrode of the row select transistor 120 .

[0019] The output node 128 is coupled to a parasitic capacitance C js A second capacitor 134 is coupled between the output node 128 and the floating diffusion node 106 and has a capacitance C H It has a capacity C H and parasitic capacitance C js Both of these affect the capacitance seen at the output node 128. The capacitance seen by the second capacitor 134 depends on the ratio of the voltage at the output node 128 to the voltage at the floating diffusion node 106. The ratio of the voltage at the output node 128 to the voltage at the floating diffusion node 106 is also referred to as the gain of the output stage 114.

[0020] When the gain of the output stage 114 is greater than one (e.g., when the voltage at the output node 128 is greater than the voltage at the floating diffusion node 106), the perceived capacitance of the second capacitor 134 is positive and the total perceived capacitance at the output node is the parasitic capacitance C jsIf the gain of the output stage 114 is less than unity (e.g., if the voltage at the output node 128 is less than the voltage at the floating diffusion node 106), the perceived capacitance of the second capacitor 134 is negative and the total perceived capacitance at the output node is less than the parasitic capacitance C js (See FIG. 1B for details.) The total capacitance seen at output node 128, C tot Reducing the gain reduces the RC delay in the image sensor, thereby increasing the gain in low-information applications. Gain is increased by reducing the time constant of the pixel array, thereby increasing the range of signal magnitudes available within the measurement window and the bandwidth of the image sensor (e.g., reducing the time constant reduces the minimum measurement window for transferring a signal from the pixel circuit to the ISP circuit). Increasing the gain in low-information applications increases the dynamic range of the image sensor and increases the quality of the images produced by the image sensor.

[0021] As shown in circuit diagram 100b of FIG. 1B, a circuit equivalent to that shown in circuit diagram 100a of FIG. 1A is provided. The second capacitor (see 134 in FIG. 1A) can be treated as a third capacitor 136 coupled between the floating diffusion node 106 and ground, and a fourth capacitor 138 coupled between the output node 128 and ground. This results in a circuit in which the perceived capacitance at the output node 128 can be determined by adding the capacitance of the first capacitor 132 and the capacitance of the fourth capacitor 138 for each pixel circuit 104 of a plurality of pixel circuits coupled to an output line 140. The capacitance C4 of the fourth capacitor 138 can be calculated by using Miller's theorem to obtain the capacitance C of the second capacitor (see 134 in FIG. 1A). H (replacing the initial impedance Z of Miller's Theorem with the impedance of the second capacitor, and replacing the output impedance Z2 of Miller's Theorem with the impedance of the fourth capacitor).

number

number

[0022] As shown in equation (2), when k is greater than 1, the capacitance C H The coefficient multiplied to derive C4 is positive, so C4 is positive. Furthermore, when k is less than 1, the capacitance C H The coefficient by which C is multiplied to derive C4 is negative, resulting in a negative C4. js ) and fourth capacitor 138 are in parallel in the equivalent circuit shown in FIG. 1B, the total real capacitance at output node 128 can be found by summing all capacitances coupled to output node 128. In the pixel circuit shown in FIG. 1B, when k is less than 1, the parasitic capacitance C js The sum of the capacitance C and the capacitance C4 is the parasitic capacitance C js , resulting in a reduced realization capacity at the output node 128.

[0023] As shown in the circuit diagram 100c of Figure 1C, a plurality of pixel circuits 145 are organized into a plurality of rows 146, 148 and columns 150, 152. A first row select line 142a is coupled to the gate electrodes 144 of the row select transistors 120 in the first row 146 of pixel circuits. A second row select line 142b is coupled to the gate electrodes 144 of the row select transistors 120 in the second row 148 of pixel circuits. A first output line 140a is coupled to the output node 128 of the first column 150 of pixel circuits. A second output line 140b is coupled to the output node 128 of the second column 152 of pixel circuits.

[0024] The realization capacitance in the first output line 140a is the parasitic capacitance C js and capacity C HThe total capacitance seen by the output line, C tot can be found by summing the parasitic capacitance and capacitance C4 when an equivalent circuit such as that shown in FIG. 1B is used instead of pixel circuit 104 of FIG. 1C. tot is calculated using Equation 3 shown below.

number

[0025] FIG. 2 illustrates a cross-sectional view 200 of the output stage of some embodiments of an image sensor having a capacitor between the output node and the floating diffusion node.

[0026] Parasitic capacitance C js1A , a second capacitor 134 (represented by a first capacitor 132) is between the fourth source / drain terminal 130 of the row select transistor and the body region of the first substrate 202. A first electrode 204 of the second capacitor 134 is coupled to the fourth source / drain terminal 130 by a first contact 206. An interconnect structure 208 further extends between and electrically couples the first electrode 204 and the first contact 206, thereby coupling the first electrode 204 to the output node 128. A second electrode 210 of the second capacitor 134 is coupled to the first gate electrode 118 of the source follower transistor 116 by the interconnect structure 208 and a second contact 212, where the second electrode 210 is coupled to the floating diffusion node (see 106 in FIG. 1A ). The interconnect structure 208 includes one or more wiring levels and one or more via levels that form a first conductive path 214 between the first gate electrode 118 and the second electrode 210, and a second conductive path 216 between the fourth source / drain terminal 130 and the first electrode 204. The interconnect structure 208 is surrounded by multiple interlevel dielectric layers 218. A first insulating layer 220 surrounds the first and second electrodes 204, 210 of the second capacitor 134.

[0027] FIG. 3 illustrates a circuit diagram 300 of some embodiments of an image sensor having a capacitor between a floating diffusion node and an output node with multiple photodetectors coupled to the floating diffusion node.

[0028] In some embodiments, the pixel circuit 104 is formed across multiple different chips bonded together. In some embodiments, the reset transistor 110, the source follower transistor 116, and the row select transistor 120 are on a first chip 306. The multiple photodetectors 302 are coupled to the floating diffusion node 106 by multiple transfer transistors 304 on a second chip 308. The ISP circuit 310 is on a third chip 312. The row select line 142 and the output line 140 are in the first chip 306. The output node 128 is on the first chip 306 and is electrically coupled to the third chip 312. In some embodiments, the first electrode 204 and the second electrode 210 of the second capacitor 134 are in a bond layer between the second chip 308 and the first chip 306.

[0029] FIG. 4 illustrates a cross-sectional view 400 of some embodiments of an image sensor having a shield structure and metal bond pad configured as a capacitor coupled between an output node and a floating diffusion node.

[0030] In some embodiments, the first interconnect structure 208 is on the first surface 202a of the first substrate 202 and includes a first conductive path 214. The first conductive path 214 electrically couples the first gate electrode 118 of the source follower transistor 116 to the second electrode 210 of the second capacitor 134. The first conductive path 214 is further electrically coupled to the source / drain terminal 112 of the reset transistor 110 and to a conversion gain circuit 402. The first conductive path 214 is coupled to the floating diffusion node 106. The conversion gain circuit 402 includes one or more semiconductor devices configured to increase the conversion gain of the pixel circuit in low light environments (e.g., imaging areas with light levels below a specified threshold).

[0031] The first conductive pathway 214 is coupled to a third conductive pathway 404 in a second interconnect structure 406 on the second chip 308. A first bond layer 408 of the first chip 306 and a second bond layer 411 of the second chip 308 mechanically couple the first chip 306 to the second chip 308. The second electrode 210 includes a combination of a first metal bond pad 405 a of the first plurality of metal bond pads 405 in the first bond layer 408 and a second metal bond pad 415 a of the second plurality of metal bond pads 415 in the second bond layer 411. The second metal bond pad 415 a is coupled to the first metal bond pad 405 a at a first bond interface 421. The second electrode 210 electrically couples the first conductive pathway 214 to the third conductive pathway 404. The second electrode 210 is also referred to as a bond electrode. Additionally, the first insulating layer 220 of the first bond layer 408 is mechanically coupled to the second insulating layer 423 of the second bond layer 411. The second interconnect structure 406 further includes one or more additional conductive paths 416 coupled to the plurality of transfer transistors 304. The separate conductive paths 416 for the plurality of transfer transistors 304 coupled to the floating diffusion node 106 allow transfer of charge from individual photodetectors of the plurality of photodetectors 302 during operation and enable charge from the individual photodetectors to be delivered separately to the pixel circuit 104.

[0032] A second conductive path 216 extends from the fourth source / drain terminal 130 of the row select transistor 120 to the first electrode 204. In some embodiments, the second conductive path 216 is the same as the output node 128. In some embodiments, the first electrode 204 surrounds the second electrode 210, increasing the surface area of ​​the second capacitor 134 and isolating the second electrode 210 from electric fields induced by other metal bond pads in the first plurality of metal bond pads 405. The first electrode 204 includes a combination of a first shield structure 407a of the first plurality of shield structures 407 and a second shield structure 413a of the second plurality of shield structures 413. The first electrode 204 is also referred to as a shield electrode. The first shield structure 407a is mechanically coupled to the second shield structure 413a of the second plurality of shield structures 413 at a first bond interface 421. The second shield structure 413a has the same layout as the first shield structure 407a (e.g., the same length and width, and the same distance between the inner walls) to improve bond strength at the first bond interface 421. The combination of the first bond layer 408 and the second bond layer increases the surface area of ​​the inner walls of the first electrode 204 and the outer walls of the second electrode 210. The increased surface area increases the capacitance of the second capacitor 134 without increasing the area used by the second capacitor 134 within the first or second interconnect structure 208, 406. That is, the thickness of the first electrode 204 and the second electrode 210 is greater than the second thickness of the interconnect structure wiring level, resulting in a capacitance between the first electrode 204 and the second electrode 210 that is greater than the capacitance between wiring of the same layout as the first electrode 204 and the second electrode 210.

[0033] The second conductive path 216 is also electrically coupled to an ISP circuit 310 on the third chip 312. The ISP circuit 310 is configured to process signals passed to it from multiple pixel circuits (see 145 in FIG. 1C ) in the image sensor to combine the signals into an image. The ISP circuit 310 includes one or more correlated double sampling (CDS) circuits, analog-to-digital converter (ADC) circuits, and amplifier circuits. One or more TSVs 410 couple the first interconnect structure 208 to a third interconnect structure 412 on the second side 202b of the first substrate 202 opposite the first side 202a. In some embodiments, the third interconnect structure 412 includes one or more wiring levels and one or more via levels electrically coupled to the third chip 312 by a third bond layer 409. The third bond layer 409 includes a third plurality of metal bond pads 414 and a third insulating layer 425. The third bond layer 409 is electrically coupled to a fourth bond layer 417 of the third chip 312 at a second bond interface 426. The fourth plurality of metal bond pads 419 are mechanically and electrically coupled to the third plurality of metal bond pads 414. Additionally, the fourth insulating layer 427 is mechanically coupled to the third insulating layer 425. The third plurality of metal bond pads 414 and the fourth plurality of metal bond pads 419 electrically couple the third interconnect structure 412 to the ISP circuit 310.

[0034] A plurality of photodetectors 302 are disposed within a second substrate 418. A plurality of DTI structures 420 extend around the plurality of photodetectors and separate them from one another. A plurality of color filters 422 and microlenses 424 are disposed above the photodetectors 302 to filter and direct incident light towards the photodetectors 302 before entering the second substrate 418.

[0035] 5A and 5B illustrate top views 500a, 500b of several embodiments of multiple shielding structures and metal bond pads in an array of pixel circuits.

[0036] 5A , the first bond layer 408 includes a first insulating layer 220 surrounding a first plurality of metal bond pads 405, including a first metal bond pad 405a, and a first plurality of shield structures 407, including a first shield structure 407a. In some embodiments, the first plurality of metal bond pads 405 are each surrounded by a first plurality of shield structures 407. For example, in an image sensor having four pixel circuits, the first metal bond pad 405a is surrounded by a first shield structure 407a, the second metal bond pad 405b is continuously surrounded by a second shield structure 407b, the third metal bond pad 405c is continuously surrounded by a third shield structure 407c, and the fourth metal bond pad 405d is continuously surrounded by a fourth shield structure 407d. The number of metal bond pads in the first plurality of metal bond pads 405 is equal to the number of shield structures in the first plurality of shield structures 407.

[0037] As shown in top view 500b of FIG. 5B , in another embodiment, the number of metal bond pads in the first plurality of metal bond pads 405 is greater than the number of shield structures in the first plurality of shield structures 407. The shield structures surround the metal bond pads in a column of the metal bond pads. For example, in an image sensor having four pixel circuits, the first metal bond pad 405a and the second metal bond pad 405b in the first column 150 are continuously surrounded by the first shield structure 407a, and the third metal bond pad 405c and the fourth metal bond pad 405d in the second column 152 are surrounded by the second shield structure 407b. The output nodes (see 128 in FIG. 1C ) of the pixel circuits in the first column 150 are coupled by an output line (see 140 in FIG. 1C ). Because the output node (see 128 in FIG. 1C ) is also coupled to a shielding structure of the first plurality of shielding structures 407 in the first column 150, the electrically coupled shielding structure shown in FIG. 1A may be replaced with the shielding structure shown in FIG. 1B without changing the electrical coupling of the circuit. Using the shielding structure shown in FIG. 5B can reduce the footprint of the shielding structure (e.g., the lateral area of ​​the shielding structure). By removing portions of the shielding structure from between the metal bond pads, the metal bond pads can be placed closer together, reducing the footprint of the pixel circuit.

[0038] 6-18 illustrate a series of cross-sectional views 600-1800 of several embodiments of methods for forming an image sensor with a capacitor between an output node and a floating diffusion node having multiple photodetectors coupled to the floating diffusion node. While FIGS. 6-18 are described as a series of operations, it is understood that these operations are not limiting in that the order of operations may be changed in other embodiments and the disclosed methods are applicable to other structures. In other embodiments, some of the operations shown and / or described may be omitted in whole or in part.

[0039] As shown in cross-sectional view 600 of FIG. 6, third interconnect structure 412 is formed on second side 202b of first substrate 202 as part of first chip 306. Third interconnect structure 412 includes one or more wiring levels and one or more via levels that form conductive paths on first substrate 202. Additionally, multiple interlayer dielectric layers 218 are formed between the formation of the wiring and via levels of third interconnect structure 412. In some embodiments, third interconnect structure 412 includes a conductive material such as copper, aluminum, tungsten, a conductive metal alloy, or the like. In some embodiments, multiple interlayer dielectric layers 218 are or include an insulating material such as silicon dioxide (SiO), silicon nitride (SiN), or the like. Third interconnect structure 412 is formed using one or more of physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), a damascene process, a dual damascene process, or the like.

[0040] As shown in cross-sectional view 700 of FIG. 7, in some embodiments, a third bond layer 409 is formed on the third interconnect structure 412. The third bond layer 409 includes a third insulating layer 425 and a third plurality of metal bond pads 414. In some embodiments, the third plurality of metal bond pads 414 is or includes one or more of aluminum, copper, aluminum-copper, etc. In some embodiments, the third insulating layer 425 is or includes one or more of silicon dioxide (SiO), silicon nitride (SiN), etc. The third insulating layer 425 is formed using one or more of PVD, ALD, CVD, etc. The third plurality of metal bond pads 414 is formed using one or more of PVD, ALD, CVD, a damascene process, etc. In some embodiments, the third plurality of metal bond pads 414 is formed simultaneously with the underlying contact layer by using a dual damascene process.

[0041] 8 , ISP circuit 310 is formed on third chip 312, which is bonded to first chip 306 at third bond layer 409. ISP circuit 310 includes one or more correlated double sampling (CDS) circuits, analog-to-digital converter (ADC) circuits, and amplifier circuits including one or more transistors, passive circuit components, or other circuit components. Formation of ISP circuit 310 includes using one or more of PVD, ALD, CVD, and implantation processes, etc., to form the transistors and circuit components, and using one or more of PVD, ALD, CVD, damascene processes, etc., to form upper layer interconnect structures to form conductive paths between the circuit components and the transistors.

[0042] In some embodiments, the third chip 312 is bonded to the first chip 306 by forming a fourth bond layer 417 on the third chip 312 before bonding the third chip 312 to the third bond layer 409. The fourth insulating layer 427 is dielectrically bonded to the third insulating layer 425, and the fourth plurality of metal bond pads 419 are bonded to the third plurality of metal bond pads 414. The combination of using inter-dielectric bonds between the insulating layers and inter-metal bonds between the metal bond pads demonstrates a hybrid bond at the second bond interface 426. The inter-dielectric bonds between the insulating layers and inter-metal bonds between the metal bond pads at the second bond interface 426 are formed by performing a pressure process to initially bond the fourth insulating layer 427 to the third insulating layer 425, and a subsequent anneal to strengthen the bonds between the third and fourth insulating layers 425, 427 and form bonds between the third and fourth plurality of metal bond pads 414, 419. In other embodiments, a hybrid bond is not used to bond the first chip 306 to the third chip 312, and a different method of bonding the first chip 306 to the third chip 312 is implemented.

[0043] 9, a plurality of front-end-of-line (FEOL) circuit components 902 are formed on the first surface 202a of the first substrate 202. The plurality of FEOL circuit components 902 includes a plurality of pixel circuit reset transistors 110, components of the conversion gain circuit 402, a source follower transistor 116, and a row select transistor 120. In some embodiments, the plurality of FEOL circuit components 902 formed in the image sensor are a plurality of metal oxide semiconductor field effect transistor (MOSFET) devices. In some embodiments, the plurality of FEOL circuit components 902 are formed using one or more PVD, ALD, CVD, or implantation processes.

[0044] As shown in cross-sectional view 1000 of FIG. 10 , contacts 1002, including first contact 206 and second contact 212, and an upper wiring layer 1004 are formed on a first surface of first substrate 202. First contact 206 is coupled to fourth source / drain terminal 130 of row select transistor 120, and second contact 212 is coupled to first gate electrode 118 of source follower transistor 116. Contact 1002 is coupled to a plurality of FEOL circuit components 902, connecting them to a subsequently formed first interconnect structure (see 208 in FIG. 11 ). Additionally, TSVs 410 are formed, coupling fourth source / drain terminal 130 of row select transistor 120 to third interconnect structure 412 and ISP circuit 310 (via upper wiring layer 1004). In some embodiments, contacts 1002, TSVs, and upper wiring layer 1004 are formed using one or more of an etching, CVD, ALD, PVD, and planarization (e.g., chemical mechanical planarization) process. In some embodiments, the contact 1002 and the upper wiring layer 1004 are formed simultaneously.

[0045] As shown in cross-sectional view 1100 of FIG. 11 , a first interconnect structure 208 is formed over contact 1002. First interconnect structure 208 includes multiple wiring levels and multiple via levels arranged to form at least a first conductive path 214 and a second conductive path 216. First conductive path 214 electrically couples a first gate electrode 118 of source follower transistor 116, a source / drain terminal of reset transistor 110, and transistors of conversion gain circuit 402, and extends to the top wiring level of the first interconnect structure. Second conductive path 216 is coupled to a fourth source / drain terminal 130 of row select transistor 120 and ISP circuit 310, and extends to the top wiring level of first interconnect structure 208. In some embodiments, an upper wiring layer (see 1004 in FIG. 10 ) is part of first interconnect structure 208.

[0046] 12, a first bond layer 408 is formed on and coupled to the first interconnect structure 208. The first bond layer 408 includes the first insulating layer 220, the first plurality of metal bond pads 405 (including the second electrode 210), and the first plurality of shield structures 407 (including the first electrode 204), as shown in the top-view layouts of FIGS. 5A and 5B. The spacing between the first plurality of metal bond pads 405 and the first plurality of shield structures 407 forms a plurality of capacitors, including the second capacitor 134. The capacitance of the plurality of capacitors is based on both the distance between opposing surfaces of the first plurality of metal bond pads 405 (e.g., outer walls of the first plurality of metal bond pads 405) and the first plurality of shield structures 407 (e.g., inner walls of the first plurality of shield structures 407), and the surface area of ​​the opposing surfaces of the first plurality of metal bond pads 405 and the first plurality of shield structures 407. The surface area of ​​the opposing surface increases (see FIG. 16) when a second bond layer (see 411 in FIG. 4) is bonded to the first bond layer 408. The first plurality of shielding structures 407 are coupled to the output node 128 of the pixel circuit (see 104 in FIG. 1A) by second conductive paths 216 in the first interconnect structure 208. The first plurality of metal bond pads 405 are coupled to the source follower transistor 116 by first conductive paths 214.

[0047] The first plurality of metal bond pads 405 are or include one or more of aluminum, copper, aluminum copper, or the like. The first insulating layer 220 is or includes one or more of silicon dioxide (SiO), silicon nitride (SiN), or the like. The first insulating layer 220 is formed using one or more of PVD, ALD, CVD, etching, or the like. The first plurality of metal bond pads 405 are formed using one or more of PVD, ALD, CVD, a damascene process, or the like. In some embodiments, the first plurality of metal bond pads 405 are formed simultaneously with the underlying contact layer by using a dual damascene process.

[0048] 13, the plurality of transfer transistors 304, the plurality of photodetectors 302, and the floating diffusion node 106 are formed on a second substrate 418 of a second chip 308. The floating diffusion node 106 and the plurality of photodetectors 302 are formed using an implantation process that implants n-type dopants into the second substrate 418. In some embodiments, the plurality of transfer transistors 304 are formed using one or more of PVD, ALD, CVD, and etching processes.

[0049] As shown in cross-sectional view 1400 of FIG. 14, a second interconnect structure 406 is formed on a second substrate 418. The second interconnect structure 406 forms a third conductive path 404 coupled to the floating diffusion node 106 and an additional conductive path coupled to the gate electrode of the transfer transistor 304. The second interconnect structure 406 includes multiple wiring levels and multiple via levels. Multiple interlevel dielectric layers 218 surround the second interconnect structure 406 and are formed between the formation of individual wiring levels. In some embodiments, the second interconnect structure 406 includes a conductive material such as copper, aluminum, copper, tungsten, a conductive metal alloy, or the like. In some embodiments, the multiple interlevel dielectric layers 218 are or include an insulating material such as silicon dioxide (SiO), silicon nitride (SiN), or the like. The second interconnect structure 406 is formed using one or more of PVD, ALD, CVD, a damascene process, a dual damascene process, or the like.

[0050] 15, in some embodiments, a second bond layer 411 is formed on the second interconnect structure 406 of the second chip 308. The second bond layer 411 includes a second insulating layer 423 made of the same material as the first insulating layer 220, a second plurality of shield structures 413 made of the same material as the first plurality of shield structures 407, and a second plurality of metal bond pads 415 made of the same material as the first plurality of metal bond pads 405. The second plurality of metal bond pads 415 are positioned to contact and bond with exposed surfaces of the first plurality of metal bond pads 405 during a bonding process described below (see FIG. 16). The second plurality of shield structures 413 are positioned to contact and bond with exposed surfaces of the first plurality of shield structures 407 during a bonding process described below (see FIG. 16). In some embodiments, the second plurality of metal bond pads 415 have the same top surface shape as the first plurality of metal bond pads (see 405 in FIG. 4), and the second plurality of shield structures 413 have the same top surface shape as the first plurality of shield structures (see 407 in FIG. 4). In other embodiments, the second bond layer 411 is omitted.

[0051] 16, multiple DTI structures 420 are formed in the second substrate 418 around the multiple photodetectors 302. In some embodiments, the multiple DTI structures 420 are formed using one or more of a PVD, ALD, CVD, or etching process. In some embodiments, the multiple DTI structures 420 are formed after the second chip 308 is bonded to the first chip 306 (e.g., after the steps shown in FIG. 17).

[0052] As shown in cross-sectional view 1700 of FIG. 17 , second chip 308 is bonded to first chip 306, with third conductive pathway 404 electrically coupled to first conductive pathway 214 by first plurality of metal bond pads 405 (including second electrode 210) and second plurality of metal bond pads 415. Second chip 308 is bonded to first chip 306 using a combination of inter-dielectric bonds between the insulating layers and inter-metal bonds between the metal bond pads. Second insulating layer 423 and first insulating layer 220 are bonded using a pressure process and subsequent annealing. Additionally, first plurality of metal bond pads 405 are bonded to second plurality of metal bond pads 415, and first plurality of shielding structures 407 are bonded to second plurality of shielding structures 413 during a pressure process and subsequent annealing. By joining first bond layer 408 to second bond layer 411, the area of ​​second capacitor 134 increases, increasing the capacitance of second capacitor 134.

[0053] 18 , in some embodiments, the plurality of color filters 422 and the plurality of microlenses 424 are formed on the second substrate 418 above the photodetectors 302. In some embodiments, the plurality of color filters 422 and the plurality of microlenses 424 are formed after the formation of the plurality of photodetectors 302 and the plurality of DTI structures 420, but before the second chip 308 is bonded to the first chip 306. In some embodiments, the plurality of color filters 422 and the plurality of microlenses 424 are centered over individual photodetectors of the plurality of photodetectors 302, and the plurality of microlenses 424 direct light toward the photodetectors 302. In other embodiments, the plurality of microlenses 424 are offset from the center of the individual photodetectors based on the position of the individual photodetectors within the photodetector array. For example, in some embodiments, individual photodetectors near the center of the photodetector array have microlenses positioned closer to the center on the individual photodetector, while individual photodetectors near the outer edge of the array have microlenses with a greater offset from the center on the individual photodetector to more effectively refract incident light toward the individual photodetector.

[0054] FIG. 19 illustrates a flowchart 1900 of some embodiments of a method for forming an image sensor having a capacitor between an output node and a floating diffusion node. While this method, and other methods illustrated and / or described herein, are illustrated as a series of acts or events, it is understood that the invention is not limited to the illustrated order or acts. Thus, in some embodiments, acts may be performed in an order different from that illustrated and / or may be performed simultaneously. Furthermore, in some embodiments, an illustrated act or event may be subdivided into multiple acts or events, which may be performed at different times or simultaneously with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other non-illustrated acts or events may be included.

[0055] At 1902, an output stage is formed on a first substrate and includes a row select transistor electrically coupled from a source follower transistor to an output node. An example diagram illustrating this step can be seen, for example, in FIG.

[0056] At 1904, a first interconnect structure is formed above the output stage, the first interconnect structure including a first conductive path electrically coupled to the gate electrode of the source follower transistor and a second conductive path electrically coupled to the output node. Example diagrams illustrating this step can be found, for example, in Figures 10-11.

[0057] At 1906, a first bond layer is formed over the first interconnect structure, the first bond layer including a bond electrode and a shield electrode surrounding the bond electrode, the shield electrode being formed electrically coupled to the second conductive path. An example diagram illustrating this step can be seen, for example, in FIG.

[0058] At 1908, a photodetector is formed in the second substrate. An example diagram illustrating this step can be seen, for example, in FIG.

[0059] At 1910, a transfer transistor is formed over the second substrate, the transfer transistor being electrically coupled from the photodetector to the floating diffusion node. An example diagram illustrating this step can be seen, for example, in FIG.

[0060] At 1912, a second interconnect structure is formed above the transfer transistor and includes a third conductive path electrically coupled to the floating diffusion node. Example diagrams illustrating this step can be seen, for example, in Figures 13-14.

[0061] At 1914, the second interconnect structure is bonded to the first interconnect structure via the first bond layer, and the bonding electrically couples the first and third conductive paths via the bond electrodes. An example diagram illustrating this step can be seen, for example, in FIG.

[0062] Some embodiments relate to an image sensor, the image sensor including a photodetector and a pixel circuit, the pixel circuit including a floating diffusion node and an output node, a transfer transistor electrically coupled from the floating diffusion node to the photodetector, a source follower transistor including a gate electrode electrically coupled to the floating diffusion node, a row select transistor electrically coupled from a source / drain region of the source follower transistor to the output node, and a capacitor electrically coupled from the output node to the floating diffusion node. In some embodiments, the image sensor includes a first integrated circuit (IC) chip containing the photodetector, the floating diffusion node, and the transfer transistor, and a second integrated circuit chip bonded to the first integrated circuit chip at an interface and containing the source follower transistor, the row select transistor, and the output node, the capacitor including separate electrodes at the interface. In some embodiments, the interface includes a metal-to-metal interface and a dielectric-to-dielectric interface. In some embodiments, the image sensor further includes a third integrated circuit chip bonded to the second integrated circuit chip and separated from the first integrated circuit chip by the second integrated circuit chip, the third integrated circuit chip including an image signal processor electrically coupled to the output node. In some embodiments, the capacitor includes a first electrode and a second electrode electrically coupled to the output node and the floating diffusion node, respectively, and the first electrode extends in a closed path around the second electrode. In some embodiments, the photodetector and pixel circuit form pixels that are repeated in a plurality of rows and a plurality of columns, and the image sensor further includes an output line that extends along a first column of the plurality of columns and is electrically coupled to the output node of each pixel in the first column. In some embodiments, the source follower transistor has a gain of less than unity.

[0063] Another embodiment relates to an image sensor including: a source follower transistor and a row select transistor on a first substrate, the row select transistor electrically coupling the source follower transistor to an output node, a photodetector and a floating diffusion node in a second substrate, a transfer transistor on the second substrate electrically coupled from the photodetector to the floating diffusion node, first and second interconnect structures between the first and second substrates, and a bond structure between the first and second interconnect structures, the bond structure including a shield electrode and a bond electrode surrounding the shield electrode, the first interconnect structure electrically coupling the shield electrode to the output node and the second interconnect structure electrically coupling the bond electrode to the floating diffusion node. In some embodiments, the first interconnect structure includes multiple wiring levels and multiple via levels alternately stacked from the bond structure toward the first substrate, and the shield electrode has a thickness greater than thicknesses of the wiring levels in the multiple wiring levels. In some embodiments, the bond electrode and the shield electrode form a capacitance that cancels parasitic capacitance at the output node. In some embodiments, the image sensor further includes a plurality of pixels, the plurality of pixels being in a plurality of rows and a plurality of columns, including a first pixel formed in part by a photodetector, a row select transistor, and a source follower transistor, and the bond structure includes a plurality of bond electrodes, individual to the plurality of pixels, including the bond electrode. In some embodiments, the shield electrode extends in a closed path around the bond electrode to isolate the bond electrode from each of the other bond electrodes of the plurality of bond electrodes. In some embodiments, the first pixel is in a first column of the plurality of columns, and the shield electrode extends in a closed path around a plurality of bond electrodes of the plurality of bond electrodes corresponding to the pixels in the first column.

[0064] Yet another embodiment relates to a method of forming an image sensor, the method including: forming an output stage on a first substrate, the output stage including a row select transistor electrically coupled from a source follower transistor to an output node; forming a first interconnect structure over the output stage, the first interconnect structure including a first conductive path electrically coupled to a gate electrode of the source follower transistor and a second conductive path electrically coupled to the output node; and forming a first bond layer over the first interconnect structure, the first bond layer including a bond electrode and a shield electrode surrounding the bond electrode, the shield electrode connecting the first bond electrode to the output node. forming the first bond layer electrically coupled to a second conductive path, forming a photodetector in a second substrate, forming a transfer transistor on the second substrate, the transfer transistor electrically coupled from the photodetector to a floating diffusion node, forming a second interconnect structure on the transfer transistor, the second interconnect structure including a third conductive path electrically coupled to the floating diffusion node, and bonding the second interconnect structure to the first interconnect structure via the first bond layer, the bonding electrically coupling the first and third conductive paths via the bond electrode. In some embodiments, the bond electrode and the shield electrode form a capacitor electrically coupled from the output node to the floating diffusion node. In some embodiments, the method further includes forming a second bond layer on the second interconnect structure, the second bond layer including an additional bond electrode and an additional shield electrode, the additional bond electrode being electrically coupled to the third conductive path, and the additional bond electrode and the additional shield electrode being bonded to the bond electrode and the shield electrode, respectively, during bonding of the second interconnect structure to the first interconnect structure.In some embodiments, the additional bond electrode has the same top surface shape as the bond electrode, and the additional shield electrode has the same top surface shape as the shield electrode. In some embodiments, the method further includes forming a conversion gain circuit simultaneously with forming the output stage, the conversion gain circuit including a first conversion gain transistor, the first conductive path electrically coupled to a gate electrode of the first conversion gain transistor. In some embodiments, the method further includes forming a third interconnect structure on a back surface of the first substrate, the output stage and the first interconnect structure being formed on a front surface of the first substrate opposite the back surface of the first substrate, and forming a through-substrate via extending through the first substrate to the third interconnect structure, the first interconnect structure being electrically coupled to the through-substrate via. In some embodiments, the method further includes bonding an integrated circuit (IC) chip to the third interconnect structure on the back surface of the first substrate, the IC chip including image signal processing circuitry.

[0065] In this written description and in the claims that follow, terms such as "first," "second," "third," etc., are understood to be merely general identifiers used for convenience of description to distinguish between different elements in a drawing or series of drawings. These terms, by themselves, do not imply any chronological order or structural proximity to these elements, and are not intended to describe corresponding elements in different illustrated and / or non-illustrated embodiments. For example, a "first dielectric layer" described in connection with a first figure does not necessarily correspond to a "first dielectric layer" described in connection with another figure, or to a "first dielectric layer" in a non-illustrated embodiment.

[0066] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of the present invention. Those skilled in the art should appreciate that this invention may readily be used as a basis for designing or modifying other processes and structures which carry out the same purposes and / or achieve the same advantages as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations may be made therein without departing from the spirit and scope of the present invention. [Industrial Applicability]

[0067] The present invention is used to improve the quality of images produced by an image sensor. [Explanation of symbols]

[0068] 100a circuit diagram 102 Photodetector 104 pixel circuit 106 Floating Diffusion Node 108 Transfer transistor 110 Reset transistor 112 Source / Drain Terminal 114 Output Stage 116 Source follower transistor 118 First gate electrode 120 Row select transistor 122 First source / drain terminal 124 Second source / drain terminal 126 Third source / drain terminal 128 output nodes 130 4th source / drain terminal 132 First Capacitor 134 Second Capacitor 140 output line 142 Row Select Line Vdd power supply rail 1900 Flowchart 1902, 1904, 1906, 1908, 1910, 1912, 1914 steps

Claims

1. A photodetector; a pixel circuit; The pixel circuit a floating diffusion node and an output node; a transfer transistor electrically coupled from the floating diffusion node to the photodetector; a source follower transistor including a gate electrode electrically coupled to the floating diffusion node; a row select transistor electrically coupled from the source / drain region of the source follower transistor to the output node; a capacitor electrically coupled from the output node to the floating diffusion node; device.

2. a first integrated circuit chip containing the source follower transistor, the row select transistor, and the output node; a second integrated circuit chip interfaced to the first integrated circuit chip and housing the photodetector, the floating diffusion node, and the transfer transistor; further comprising The device of claim 1 , wherein the capacitor includes separate electrodes at the interface.

3. The device of claim 2 , wherein the interfaces include metal-to-metal and dielectric-to-dielectric interfaces.

4. a third integrated circuit chip bonded to the first integrated circuit chip and separated from the second integrated circuit chip by the first integrated circuit chip; 3. The device of claim 2, wherein said third integrated circuit chip includes an image signal processor electrically coupled to said output node.

5. the capacitor includes first and second electrodes electrically coupled to the output node and the floating diffusion node, respectively; The device of claim 1 , wherein the first electrode extends in a closed path around the second electrode.

6. the photodetector and the pixel circuit form a pixel, the pixel being repeated in multiple rows and multiple columns; The device comprises: an output line extending along a first column of the plurality of columns and electrically coupled to the output node of each pixel of the first column; The device of claim 1 .

7. The device of claim 1 , wherein the source follower transistor has a gain of less than unity.

8. a source follower transistor and a row select transistor on a first substrate, the row select transistor electrically coupled from the source follower transistor to an output node; a photodetector and a floating diffusion node in the second substrate; a transfer transistor electrically coupled on the second substrate from the photodetector to the floating diffusion node; a first interconnect structure and a second interconnect structure between the first substrate and the second substrate; a bond structure between the first interconnect structure and the second interconnect structure, the bond structure including a bond electrode and a shield electrode surrounding the bond electrode; the first interconnect structure electrically couples the shield electrode to the output node, and the second interconnect structure electrically couples the bond electrode to the floating diffusion node. device.

9. 9. The device of claim 8, wherein the first interconnect structure includes multiple wiring levels and multiple via levels stacked alternately from the bond structure toward the first substrate, and the shield electrode has a thickness greater than a thickness of a wiring level in the multiple wiring levels.

10. 9. The device of claim 8, wherein the bond electrode and the shield electrode form a capacitance that cancels a parasitic capacitance at the output node.

11. further comprising a plurality of pixels; the plurality of pixels are in a plurality of rows and a plurality of columns and include a first pixel formed in part by the photodetector, the row select transistor, and the source follower transistor; 9. The device of claim 8, wherein the bond structure comprises a plurality of bond electrodes, each of the bond electrodes being individual to the plurality of pixels.

12. The device of claim 11 , wherein the shield electrode extends in a closed path around the bond electrode to separate the bond electrode from each other bond electrode of the plurality of bond electrodes.

13. 12. The device of claim 11, wherein the first pixel is in a first column of the plurality of columns, and the shield electrode extends in a closed path around a plurality of bond electrodes of the plurality of bond electrodes corresponding to pixels in the first column.

14. forming an output stage on a first substrate, the output stage including a row select transistor electrically coupled from a source follower transistor to an output node; forming a first interconnect structure above the output stage, the first interconnect structure including a first conductive path electrically coupled to a gate electrode of the source follower transistor and a second conductive path electrically coupled to the output node; forming a first bond layer over the first interconnect structure, the first bond layer including a bond electrode and a shield electrode surrounding the bond electrode, the shield electrode being electrically coupled to the second conductive path; forming a photodetector in a second substrate; forming a transfer transistor on the second substrate, the transfer transistor electrically coupled from the photodetector to a floating diffusion node; forming a second interconnect structure over the transfer transistor, the second interconnect structure including a third conductive path electrically coupled to the floating diffusion node; bonding the second interconnect structure to the first interconnect structure via the first bond layer, wherein the bonding electrically couples the first and third conductive paths via the bond electrodes; A method of forming a device comprising:

15. 15. The method of claim 14, wherein the bond electrode and the shield electrode form a capacitor electrically coupled from the output node to the floating diffusion node.

16. forming a second bond layer on the second interconnect structure, the second bond layer including an additional bond electrode and an additional shield electrode, the additional bond electrode electrically coupled to the third conductive path, the additional bond electrode and the additional shield electrode being bonded to the bond electrode and the shield electrode, respectively, during bonding of the second interconnect structure to the first interconnect structure; 15. The method of claim 14, further comprising:

17. The method of claim 16 , wherein the additional bond electrode has the same top surface shape as the bond electrode and the additional shield electrode has the same top surface shape as the shield electrode.

18. forming a conversion gain circuit simultaneously with forming the output stage, the conversion gain circuit including a first conversion gain transistor, the first conduction path electrically coupled to a gate electrode of the first conversion gain transistor; 15. The method of claim 14, further comprising:

19. forming a third interconnect structure on a back surface of the first substrate, the output stage and the first interconnect structure being formed on a front surface of the first substrate opposite the back surface of the first substrate; forming a through-substrate via extending through the first substrate to the third interconnect structure, the first interconnect structure being electrically coupled to the through-substrate via; 15. The method of claim 14, further comprising:

20. bonding an integrated circuit chip including an image signal processing circuit to the third interconnect structure on the back surface of the first substrate; 20. The method of claim 19, further comprising:

Images