Display device

Abstract

To provide a highly reliable semiconductor device using an oxide semiconductor in which variation in electrical characteristics is suppressed.SOLUTION: To provide a semiconductor device including a first oxide semiconductor layer in contact with a source electrode layer and a drain electrode layer, and a second oxide semiconductor layer serving as a current path (channel) of a transistor. The first oxide semiconductor layer functions as a buffer layer for suppressing diffusion of a constituent element of the source and drain electrode layers to a channel. When the first oxide semiconductor layer is provided, the constituent element can be prevented from diffusing into the interface between the first oxide semiconductor layer and the second oxide semiconductor layer and into the second oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The invention disclosed in this specification and the like relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of semiconductor devices, including electro-optical devices, image display devices, semiconductor circuits, and electronic equipment. be. [Background technology]

[0003] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is The transistor is used in integrated circuits (ICs) and image display devices (also known simply as display devices). These are widely used in electronic devices such as semiconductors that can be applied to transistors. Silicon-based semiconductor materials are widely known as thin film semiconductors, but other materials include oxide semiconductors. Conductors are attracting attention.

[0004] For example, zinc oxide or an In-Ga-Zn-based oxide semiconductor is used as the oxide semiconductor. Techniques for fabricating transistors using this method have been disclosed (see Patent Documents 1 and 2).

[0005] In addition, Non-Patent Document 1 describes a transistor including a structure in which oxide semiconductors with different compositions are stacked. The data is disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Non-patent literature]

[0007] [Non-Patent Document 1] Masashi Ono et al., ``Novel High Performance IGZO-TFT with High Mobility over 40 cm2 / Vs and High Photostability Incorporated Oxygen Diffusion'', IDW'11 Late-News Paper, pp. 1689-1690 Summary of the Invention [Problem to be solved by the invention]

[0008] In a transistor using an oxide semiconductor, If trap states (also called interface states) exist at the interface with the layer, the electrical characteristics of the transistor ( For example, this can cause fluctuations in the threshold voltage or subthreshold coefficient (S value).

[0009] For example, in a bottom-gate transistor, the structure of the source electrode layer and the drain electrode layer When a constituent element diffuses into the back channel of the oxide semiconductor layer, the constituent element forms a trap level. In addition, the electrical characteristics of the transistor change. The existence of trap states at the interface can cause fluctuations in the electrical characteristics of transistors. be.

[0010] In view of this, one embodiment of the present invention is to provide a semiconductor device including an oxide semiconductor, which is capable of preventing fluctuations in electrical characteristics. An object of the present invention is to provide a highly reliable semiconductor device by suppressing the generation of noise. [Means for solving the problem]

[0011] One embodiment of the present invention is a bottom-gate transistor including an oxide semiconductor. at least a first oxide semiconductor layer in contact with the source electrode layer and the drain electrode layer; A stacked structure of a second oxide semiconductor layer provided between the oxide semiconductor layer and the gate insulating layer is formed. In the above, the second oxide semiconductor layer is formed as a main current path (channel ) and the first oxide semiconductor layer is formed to suppress diffusion of constituent elements of the source electrode layer and the drain electrode layer. By using it as a buffer layer to suppress fluctuations in the electrical characteristics of transistors More specifically, for example, the following configuration can be adopted.

[0012] One embodiment of the present invention is a gate electrode layer, a gate insulating layer over the gate electrode layer, and a gate insulating layer. an oxide semiconductor stack overlapping with the gate electrode layer via an oxide semiconductor layer; and a source electrode layer and a drain electrode layer, a first oxide semiconductor layer in contact with the drain electrode layer, and a first oxide semiconductor layer and a gate insulating layer and a second oxide semiconductor layer provided between the first oxide semiconductor layer and the second oxide semiconductor layer. Both contain indium and gallium, and the indium composition is equal to or less than the gallium composition. the second oxide semiconductor layer contains at least indium and gallium, and The composition of gallium is larger than the composition of gallium, and the first oxide semiconductor layer is a source electrode layer. and a semiconductor device containing a constituent element of the drain electrode layer as an impurity.

[0013] Another embodiment of the present invention is a gate electrode layer, a gate insulating layer over the gate electrode layer, and a gate insulating layer over the gate electrode layer. an oxide semiconductor stack overlapping the gate electrode layer with a gate insulating layer interposed therebetween; a source electrode layer and a drain electrode layer electrically connected to each other, and the oxide semiconductor stack a first oxide semiconductor layer in contact with the electrode layer and the drain electrode layer; and a third oxide semiconductor layer in contact with the gate insulating layer. the second oxide semiconductor layer and the third oxide semiconductor layer provided between the first oxide semiconductor layer and the third oxide semiconductor layer. The first oxide semiconductor layer and the third oxide semiconductor layer are at least Both contain indium and gallium, and the indium composition is equal to or less than the gallium composition. the second oxide semiconductor layer contains at least indium and gallium, and The composition of gallium is larger than the composition of gallium, and the first oxide semiconductor layer is a source electrode layer. and a semiconductor device containing a constituent element of the drain electrode layer as an impurity.

[0014] Another embodiment of the present invention is a gate electrode layer, a gate insulating layer over the gate electrode layer, and a gate insulating layer over the gate electrode layer. an oxide semiconductor stack overlapping the gate electrode layer with a gate insulating layer interposed therebetween; a source electrode layer and a drain electrode layer electrically connected to each other, and the oxide semiconductor stack a first oxide semiconductor layer in contact with the electrode layer and the drain electrode layer; and a third oxide semiconductor layer in contact with the gate insulating layer. the second oxide semiconductor layer and the third oxide semiconductor layer provided between the first oxide semiconductor layer and the third oxide semiconductor layer. The first oxide semiconductor layer and the third oxide semiconductor layer are at least Both contain indium and gallium, and the indium composition is equal to or less than the gallium composition. the second oxide semiconductor layer contains at least indium and gallium, and The composition of gallium is larger than the composition of gallium, and the first oxide semiconductor layer is a source electrode layer. The third oxide semiconductor layer contains constituent elements of the gate and drain electrode layers as impurities. The semiconductor device contains the constituent elements of the edge layer as impurities.

[0015] In any one of the above semiconductor devices, the source electrode layer and the drain electrode layer contain copper. It is preferable.

[0016] In any one of the above semiconductor devices, the gate insulating layer includes a silicon nitride film. It's okay to be.

[0017] The effect of the configuration according to one aspect of the present invention can be explained as follows. Please note that this is merely one consideration.

[0018] The transistor according to one embodiment of the present invention includes a first oxide film in contact with a source electrode layer and a drain electrode layer. a first oxide semiconductor layer, a second oxide semiconductor layer which serves as the main current path (channel) of the transistor, and Here, the first oxide semiconductor layer is a source electrode layer and a drain electrode layer. It functions as a buffer layer to prevent the constituent elements of the layer from diffusing into the channel. By providing the first oxide semiconductor layer, the first oxide semiconductor layer and the second oxide semiconductor layer This can prevent the constituent elements from diffusing into the interface between the first oxide semiconductor layer and the second oxide semiconductor layer.

[0019] In addition, the energy gap (band gap) of the metal oxide used in the first oxide semiconductor layer The energy gap of the second oxide semiconductor layer is made larger than the energy gap of the metal oxide applied to the second oxide semiconductor layer. By this, a conduction band offset is generated between the second oxide semiconductor layer and the first oxide semiconductor layer. In the oxide semiconductor stack, a conduction band offset is present, which is preferable. Then, carriers do not move at the interface with the first oxide semiconductor layer and within the first oxide semiconductor layer. Since the metal element flows through the second oxide semiconductor layer, it is trapped on the back channel side due to the diffusion of the metal element. Even if a capture level exists, the transistor is not easily affected by the capture level. This can stabilize the electrical characteristics of the capacitor.

[0020] In addition, in the transistor of one embodiment of the present invention, the first oxide semiconductor layer and the second oxide semiconductor layer are In addition to the semiconductor layer, a gate insulating layer is provided between the second oxide semiconductor layer and the gate insulating layer. It is more preferable that the third oxide semiconductor layer be in contact with the third oxide semiconductor layer. The semiconductor layer contains one or more metal elements selected from the constituent elements of the second oxide semiconductor layer. The third oxide semiconductor layer is composed of the first oxide semiconductor layer and has the same properties as the second oxide semiconductor layer. By providing the second oxide semiconductor layer with the gate insulating layer side interface, which functions as a channel, That is, the third oxide semiconductor layer can stabilize the interface. In particular, it acts as a buffer layer for the carriers at the interface of the channel on the gate insulating layer side. By suppressing the capture of ions, light degradation (e.g., negative bias light degradation) of transistors can be reduced. This makes it possible to obtain a highly reliable transistor.

[0021] In addition, similarly to the first oxide semiconductor layer, the third oxide semiconductor layer may be formed by using an elemental metal oxide. The energy gap of the second oxide semiconductor layer is made larger than that of the metal oxide. By increasing the difference between the first and second oxide semiconductor layers, a conduction band gap is created between the third oxide semiconductor layer and the second oxide semiconductor layer. In a normal MISFET, the gate insulating layer At the interface between the semiconductor and the gate, trap levels and other phenomena occur, which deteriorate the electrical characteristics of the FET. By providing an oxide semiconductor layer, a structure in which carriers flow in a region away from the gate insulating layer ( Since the semiconductor layer becomes a so-called buried channel, the influence of the interface can be reduced.

[0022] The first oxide semiconductor, the second oxide semiconductor, and the third oxide semiconductor have the same structure. When metal oxides having different compositions are used, for example, a first oxide The semiconductor, the second oxide semiconductor, and the third oxide semiconductor contain at least indium and Metal oxides containing gallium and gallium can be used. The higher the indium content, the higher the field-effect mobility of the metal oxide. The higher the ratio of gallium to metal elements, the larger the energy gap of the metal oxide. Therefore, the second oxide semiconductor to be the channel formation region is a compound of indium. It is preferable to use a metal oxide having a composition larger than that of gallium, and The first oxide semiconductor and the third oxide semiconductor that function are those having an indium composition of gallium. It is preferable to use a metal oxide having a composition of 1000 ppm or less. [Effects of the Invention]

[0023] According to one embodiment of the present invention, a change in electrical characteristics of a transistor including an oxide semiconductor can be suppressed. This makes it possible to provide a highly reliable semiconductor device. [Brief explanation of the drawings]

[0024] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 2] 1A to 1C are a plan view, a cross-sectional view, and a band diagram illustrating one embodiment of a semiconductor device. [Figure 3] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device. [Figure 4] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 5] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 6] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 7] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 8] 1A and 1B are diagrams illustrating electronic devices. [Figure 9] 1A and 1B are diagrams illustrating electronic devices. [Figure 10] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 11] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 12] FIG. 10 is a diagram showing the results of SIMS measurements in an example. [Figure 13] 1A to 1C illustrate one embodiment of a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Therefore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0026] In the configuration of the present invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and repeated explanations thereof will be omitted. When referring to a part having a specific function, the hatch pattern shall be the same and no specific symbol shall be attached. There is a match.

[0027] In each drawing described in this specification, the size of each component, the thickness of the film, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale.

[0028] In this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of steps or the order of layers. It does not indicate a specific name for the purpose of

[0029] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Straight" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This also includes cases where the angle is between 85° and 95°.

[0030] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0031] (Embodiment 1) In this embodiment mode, one mode of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. In this embodiment, a semiconductor device including a boron nitride semiconductor layer will be described as an example of a semiconductor device. 1 shows a TomGate type transistor.

[0032] 1A to 1C show examples of a transistor 300. 1(B) is a plan view of the resistor 300, and FIG. 1(B) is a cross-sectional view taken along the chain line X1-Y1 in FIG. 1(A). 1(C) is a cross-sectional view taken along the chain line V1-W1 in FIG. 1(A).

[0033] The transistor 300 includes a gate electrode layer 402 provided on a substrate 400 having an insulating surface. a gate insulating layer 404 on the gate electrode layer 402; an oxide semiconductor stack 408 overlapping the second electrode layer 402; The source electrode layer 410a and the drain electrode layer 410b are connected to the source electrode layer 410a. The insulating layer 410 covers the electrode layer 410a and the drain electrode layer 410b and is in contact with the oxide semiconductor stack 408. The edge layer 412 may be included in the components of the transistor 300 .

[0034] In the transistor 300, the oxide semiconductor stack 408 includes a source electrode layer 410a and a drain electrode layer 410b. The oxide semiconductor layer 408a is in contact with the gate electrode layer 410b, and the oxide semiconductor layer 408b is in contact with the gate electrode layer 410b. and an oxide semiconductor layer 408b provided between the insulating layer 404 and the oxide semiconductor layer 408.

[0035] In the oxide semiconductor stack 408, the oxide semiconductor layer 408b is a The oxide semiconductor layer 408b is provided on the back channel side. The oxide semiconductor layer 408a is a gate insulating film between the source electrode layer 410a and the drain electrode layer 410b. The oxide semiconductor layer 408b functions as a buffer layer that prevents the constituent elements from diffusing into the oxide semiconductor layer 408b. That is, the oxide semiconductor layer 408a is formed between the source electrode layer 410a and the drain electrode layer 410b. The buffer layer contains the constituent elements of the transistor 30b as impurities. Since it is possible to suppress the formation of a trap level in the channel of 0, the trap level Therefore, the increase in the S value caused by the variation in the electrical characteristics of the transistor can be suppressed. It is possible to provide a highly reliable semiconductor device by suppressing adhesion or deterioration over time.

[0036] The oxide semiconductor layer 408a and the oxide semiconductor layer 408b are made of oxide semiconductors having different constituent elements. Alternatively, the constituent elements may be the same and the compositions of the two may be different. The oxide semiconductor layer 408b serving as a channel of the transistor 300 is a field-effect transport layer. It is preferable to use an oxide semiconductor having a high conductivity.

[0037] For example, the oxide semiconductor layer 408a and the oxide semiconductor layer 408b may contain the same elements. When an oxide semiconductor containing at least indium and gallium is used, the oxide semiconductor layer As 408b, an oxide semiconductor in which the indium content is larger than the gallium content is used. The oxide semiconductor layer 408a preferably has an indium content greater than or equal to the gallium content. It is preferable to use an oxide semiconductor, which is below the above-mentioned.

[0038] In oxide semiconductors, the s orbitals of heavy metals mainly contribute to carrier conduction, and indium Increasing the content of tends to increase the overlap of s orbitals. In the oxide semiconductor layer 408b, the indium content is made higher than the gallium content. This results in a higher field-effect transition compared to oxides with an indium content equal to or less than that of gallium. It is possible to provide mobility.

[0039] In addition, the higher the ratio of gallium to other metal elements, the larger the energy gap. Since it becomes a metal oxide, by making the indium composition equal to or less than the gallium composition, it becomes an oxide semiconductor. The conductor layer 408a has a larger energy gap than the oxide semiconductor layer 408b. Therefore, a conduction band offset between the oxide semiconductor layer 408b and the oxide semiconductor layer 408a is generated. Gallium is also preferred because it can form oxygen vacancies compared to indium. Since the indium composition is lower than that of gallium, the indium content is low and the oxygen deficiency is small. Some metal oxides have a lower indium content than metal oxides with a higher gallium content. Therefore, the back channel side of the transistor 300 is more stabilized. This becomes possible.

[0040] For example, the oxide semiconductor layer 408a and the oxide semiconductor layer 408b may be formed of In—Ga—Zn When a Zn-based oxide semiconductor is used, the oxide semiconductor layer 408a has a composition of In:Ga:Zn=1:1 :1(=1 / 3:1 / 3:1 / 3), In:Ga:Zn=1:3:2(=1 / 6:3 / 6 :2 / 6), In:Ga:Zn=2:4:3(=2 / 9:4 / 9:3 / 9), or I In- with a composition (atomic ratio) of n:Ga:Zn=1:5:3 (=1 / 9:5 / 9:3 / 9) Ga-Zn oxides and metal oxides with compositions close to those of Ga-Zn oxides can be used. The layer 408b contains In:Ga:Zn=3:1:2 (=3 / 6:1 / 6:2 / 6), In: Ga:Zn=4:2:3(=4 / 9:2 / 9:3 / 9), In:Ga:Zn=5:1:3 (=5 / 9:1 / 9:3 / 9), In:Ga:Zn=5:3:4(=5 / 12:3 / 12 :4 / 12), In:Ga:Zn=6:2:4(=6 / 12:2 / 12:4 / 12), The composition (atomic In-Ga-Zn oxides with a composition ratio of 100 or less and metal oxides with a composition close to that can be used. .

[0041] For example, when the composition of In, Ga, and Zn is In:Ga:Zn=a:b:c (a+b+c= 1) The composition of the oxide is In:Ga:Zn=A:B:C (A+B+C=1). The oxide composition is close to the oxide composition when a, b, and c are (aA) 2 +(bB) 2 +(cC ) 2 ≦r 2 The value of r can be set to, for example, 0.05.

[0042] Note that the metal oxide used for the oxide semiconductor stack 408 is not limited to these, and may be any other metal oxide as needed. The appropriate composition depending on the electrical characteristics (field effect mobility, threshold, variation, etc.) In addition, in order to obtain the required electrical characteristics, the carrier concentration and impurity concentration It is necessary to appropriately set the defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. For example, other metal elements may be contained in place of gallium. However, it is possible to use a metal oxide that does not contain any of the above-mentioned metal oxides. When zinc is contained, the oxide semiconductor layer formed is relatively easily converted into CAAC-OS(C Axis Aligned Crystalline Oxide Semiconductor This is preferable because it can be used as a micro-film.

[0043] Note that the oxide semiconductor layer can be formed by a sputtering method. If the target contains indium, it is possible to reduce the generation of particles during film formation. Therefore, the oxide semiconductor layer 408a containing indium and the oxide semiconductor layer 408b containing indium can be formed. It is more preferable to use the conductive layer 408b.

[0044] The structure of the oxide semiconductor layer will be described below.

[0045] Oxide semiconductor layers are roughly classified into single-crystal oxide semiconductor layers and non-single-crystal oxide semiconductor layers. The single-crystal oxide semiconductor layer includes an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, a polycrystalline oxide semiconductor layer, and a polycrystalline oxide semiconductor layer. physical semiconductor layer, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor film, etc.

[0046] The amorphous oxide semiconductor layer has an irregular atomic arrangement in the film and is an oxide layer that does not contain a crystalline component. The entire film has a completely amorphous structure, with no crystalline parts even in microscopic areas. A typical example is an oxide semiconductor layer.

[0047] The microcrystalline oxide semiconductor layer is made of, for example, microcrystals (nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, the microcrystalline oxide semiconductor layer has a lower atomic number than the amorphous oxide semiconductor layer. Therefore, the microcrystalline oxide semiconductor layer has a higher order of order than the amorphous oxide semiconductor layer. The defect level density is also low.

[0048] The CAAC-OS film is one of the oxide semiconductor layers having multiple crystal parts. The crystal part is so large that it fits inside a cube with a side length of less than 100 nm. The crystals contained in the S film are cubic with sides of less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller defect density than the microcrystalline oxide semiconductor layer. The CAAC-OS film has a low density of recessed states. .

[0049] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a crystalline microscope, clear boundaries between the crystals, i.e., crystal boundaries, are clearly visible. It is not possible to confirm the grain boundary. It can be said that the AC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0050] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). ) It can be confirmed that the metal atoms are arranged in layers in the crystalline part. Each layer has a surface on which the CAAC-OS film is formed (also referred to as a surface on which the CAAC-OS film is formed) or an uneven surface on which the CAAC-OS film is formed. The shape reflects this and is aligned parallel to the surface on which the CAAC-OS film is formed or the top surface.

[0051] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (planar TEM). When observed, it was found that the metal atoms were arranged in triangular or hexagonal shapes in the crystals. However, there is no regularity in the arrangement of metal atoms between different crystal parts. stomach.

[0052] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It turns out that there are.

[0053] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was found by structural analysis using the device. In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0054] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a compound semiconductor layer, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0055] From the above, it is concluded that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. Although it is regular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0056] The crystalline part is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed or the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0057] The crystallinity of the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The area near the surface may have a higher degree of crystallinity than the area near the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region where the impurities are added changes, resulting in partial In some cases, regions of different crystallinity may be formed.

[0058] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ around 31°, a peak also appeared at 2θ around 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferable that the peak is exhibited at 2θ of around 36° and that the peak is not exhibited at 2θ of around 36°.

[0059] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0060] The oxide semiconductor layer may be, for example, an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, or a CA The AC-OS film may be a laminated film having two or more kinds of films.

[0061] The CAAC-OS film is formed by sputtering, for example, using a polycrystalline metal oxide target. When ions collide with the sputtering target, the sputtering occurs. The crystalline region contained in the target for quartz crystal cleaves from the ab plane and forms a plane parallel to the ab plane. In this case, the particles may peel off as flat or pellet-shaped sputtered particles. In this case, the plate-shaped sputtered particles reach the substrate while maintaining their crystalline state. A CAAC-OS film can be formed.

[0062] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0063] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas at a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0064] In addition, by increasing the substrate heating temperature during film formation, migration of sputtered particles after deposition on the substrate can be prevented. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably The film is formed at a temperature between 200°C and 500°C. When a plate-shaped sputtering particle reaches the substrate, migration occurs on the substrate, The flat surface of the sputtered particle adheres to the substrate.

[0065] In addition, increasing the oxygen ratio in the deposition gas and optimizing the power reduces plasma damage during deposition. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0066] As an example of a metal oxide target for sputtering, an In-Ga-Zn-O compound target is used. The get is shown below.

[0067] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified ratio, pressurized, and then By heat treatment at temperatures between 000°C and 1500°C, polycrystalline In-Ga-Z The target is an nO compound, where X, Y, and Z are any positive numbers. The molar ratio of a certain amount is, for example, InO X powder, GaO YPowder and ZnO Z Powder, 2:2 :1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2. The types of powders and the molar ratios to be mixed are determined based on the sputtering target to be produced. The above can be changed as appropriate.

[0068] Note that the oxide semiconductor layers 408a and 408b have different crystallinity. However, the oxide semiconductor layer 408b functioning as the channel of the transistor 300 may be In addition, when the oxide semiconductor layer 408b is a C In the case of an AAC-OS film, the oxide semiconductor layer 408b is provided on and in contact with the oxide semiconductor layer 408b. The precursors are aligned in the layer 408a, and the layer 408a is given so-called order, which results in the formation of an oxide semiconductor layer. In some cases, the layer 408a can be a CAAC-OS film. When the oxide semiconductor layer 408a is an amorphous oxide semiconductor, the source electrode layer 410a and The etching process during the formation of the drain electrode layer 410b causes oxygen deficiency, which makes the layer more likely to become n-type. Therefore, it is preferable to use a crystalline oxide semiconductor for the oxide semiconductor layer 408a. I wish.

[0069] In this embodiment, the oxide semiconductor layer 408a and the oxide semiconductor layer 408b are the same. In this case, the oxide semiconductor stack is formed using only one element. In some cases, the interfaces between the oxide semiconductor layers may become unclear. In this example, the interface between the oxide semiconductor layer 408a and the oxide semiconductor layer 408b is schematically illustrated by a dotted line. This also applies to the subsequent drawings.

[0070] 2A to 2C show examples of the structure of the transistor 310. 2(B) is a plan view of the resistor 310, and FIG. 2(B) is a cross-sectional view taken along the chain line X2-Y2 in FIG. 2(A). 2(C) is a cross-sectional view taken along the chain line V2-W2 in FIG. 2(A). The transistor 310 shown in FIGS. 2A to 2C has the same structure as the transistor 300 shown in FIG. 1, a gate electrode layer 402 provided on a substrate 400 having an insulating surface, and a gate electrode layer 40 2, the gate insulating layer 404 contacts the gate insulating layer 404 and overlaps the gate electrode layer 402. and a source electrode layer electrically connected to the oxide semiconductor stack 408. The source electrode layer 410a and the drain electrode layer 410b are also included. The insulating layer 412 that covers the transistor electrode layer 410b and is in contact with the oxide semiconductor stack 408 is It may be a component of the controller 310.

[0071] The transistor 310 has an oxide semiconductor layer 408b between the oxide semiconductor layer 408b and the gate insulating layer 404. The transistor 300 differs from the transistor 300 in that it includes a semiconductor layer 408c. In the transistor 310, the oxide semiconductor stack 408 includes an oxide semiconductor layer 408a, an oxide semiconductor layer 408b, and an oxide semiconductor layer 408c. The insulating film 408 includes a laminated structure of an oxide semiconductor layer 408b and an oxide semiconductor layer 408c.

[0072] Note that the components of the transistor 310 other than the oxide semiconductor layer 408c are the same as those of the transistor 310. The same applies to the transistor 300, and the description of the transistor 300 can be taken into consideration.

[0073] In the transistor 310, the oxide semiconductor layer 408b in which a channel is formed and the gate By providing the oxide semiconductor layer 408c between the insulating layer 404 and the gate insulating layer 404, carriers can be circulated through the gate insulating layer 408c. The structure is such that the flow passes through the area away from 404 (so-called buried channel). The interface between the insulating layer 404 and the channel can be stabilized, and a trap level is not formed at the interface. This can prevent the transistor from deteriorating, especially when exposed to negative bias light. This prevents light degradation such as deterioration, and makes it possible to provide a highly reliable transistor.

[0074] In metal oxides containing indium and gallium, the ratio of gallium to other metal elements The higher the composition ratio, the larger the energy gap. The conduction band offset is caused by the difference in the band gap between the oxide semiconductor layer 408c and the oxide semiconductor layer 408b. Therefore, the oxide semiconductor layer 408c is formed with a composition of indium and a composition of gallium. When the following metal oxide is used, a channel can be effectively formed in the oxide semiconductor layer 408b. This is preferable because it can

[0075] When an In—Ga—Zn-based oxide semiconductor is used as the oxide semiconductor layer 408c, In: Ga:Zn=1:1:1(=1 / 3:1 / 3:1 / 3), In:Ga:Zn=1:3:2 (=1 / 6:3 / 6:2 / 6), In:Ga:Zn=2:4:3(=2 / 9:4 / 9:3 / 9), or In:Ga:Zn=1:5:3(=1 / 9:5 / 9:3 / 9) composition ( In-Ga-Zn oxides with a composition ratio of 1000 to 10000 (atomic ratio) or oxides with a composition close to that can be used. Note that both the oxide semiconductor layer 408a and the oxide semiconductor layer 408c have an indium content. It is preferable to use a metal oxide having a composition of gallium or less. The composition of the oxide semiconductor layer 408a and the composition of the oxide semiconductor layer 408c may be the same or different. Good too.

[0076] In general, an oxide semiconductor layer is often formed by a sputtering method. On the other hand, rare gas elements (e.g., arsenic) ionized during sputtering of the oxide semiconductor layer The particles ejected from the sputtering target surface are deposited on the gate insulating layer. Such particles may be repelled from the surface on which the oxide semiconductor layer is to be formed. The particles thus repelled from the film on which the film is to be formed are transferred to the oxide semiconductor layer as impurity elements. The impurity element is taken in as an element, and the impurity element is highly concentrated in the vicinity of the surface where the oxide semiconductor layer is formed. In addition, the impurity element may remain in the vicinity of the surface where the oxide semiconductor layer is formed. If the oxide semiconductor layer contains the oxide semiconductor layer, the resistance of the oxide semiconductor layer increases, which may cause deterioration in the electrical characteristics of the transistor. This is a factor.

[0077] However, in the transistor 310 shown in FIGS. 2A to 2C, the channel The oxide semiconductor layer 408b is formed between the oxide semiconductor layer 408b and the gate insulating layer 404. By providing 408c, the constituent elements of the gate insulating layer 404 are prevented from diffusing to the channel. That is, the oxide semiconductor layer 408c can suppress the The oxide semiconductor layer 408c may contain a chemical element (for example, silicon) as an impurity. By including the ion implantation element, the electrical characteristics of the transistor 310 can be further stabilized, and the transistor 310 can be made more reliable. A semiconductor device can be provided.

[0078] FIG. 2(D) is an energy band diagram in the film thickness direction (between D-D') in FIG. 2(B). In this embodiment, the oxide semiconductor layers 408a to 408c are formed using an I The oxide semiconductor layer 40 is formed using an n-Ga-Zn-based oxide semiconductor. The oxide semiconductor layer 8a and the oxide semiconductor layer 408c have an indium content that is lower than or equal to the gallium content. A metal oxide is used, and the oxide semiconductor layer 408b has an indium content and a gallium content. The oxide semiconductor film thickness shown in this embodiment is thus obtained. The layer 408 forms a so-called buried channel as shown in the energy band diagram of FIG. 2(D). It becomes possible to achieve this.

[0079] An example of a method for manufacturing the transistor 310 will be described below with reference to FIGS.

[0080] First, a gate electrode layer 402 (formed from the same layer as this) is formed on a substrate 400 having an insulating surface. (including wiring)

[0081] There are no major restrictions on the substrate that can be used for the substrate 400 having an insulating surface, but at least In both cases, it is necessary to have heat resistance to the extent that it can withstand subsequent heat treatment. Glass substrates such as borosilicate glass and aluminoborosilicate glass, ceramic substrates, and quartz substrates A substrate such as a silicon substrate or a sapphire substrate can be used. crystalline semiconductor substrate, polycrystalline semiconductor substrate, compound semiconductor substrate such as silicon germanium, SOI A substrate or the like can be used, and a substrate having a semiconductor element mounted thereon is called a substrate 400. A base insulating layer may be formed over the substrate 400.

[0082] The material of the gate electrode layer 402 is molybdenum, titanium, tantalum, tungsten, aluminum, or the like. Metallic materials such as aluminum, copper, chromium, neodymium, scandium, etc., or alloys containing these as the main components The gate electrode layer 402 can be formed using an impurity source such as phosphorus. Semiconductor films, such as polycrystalline silicon films doped with silicon, and silicon films such as nickel silicide The gate electrode layer 402 may have a single layer structure or a stacked layer structure. The gate electrode layer 402 may have a tapered shape, for example, with a taper angle of 15° or more. The taper angle is the angle between the side surface of the layer having the tapered shape and the surface of the layer. This refers to the angle between the bottom surface of the layer.

[0083] The material of the gate electrode layer 402 includes indium oxide, tin oxide, and tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium oxide zinc oxide, acid Conductive materials such as silicon dioxide doped indium tin oxide can also be applied.

[0084] Alternatively, the gate electrode layer 402 may be made of a nitrogen-containing In—Ga—Zn-based oxide, ... or a nitrogen-containing In—Ga—Zn-based oxide. In-Sn oxides containing nitrogen, In-Ga oxides containing nitrogen, In-Zn oxides containing nitrogen oxides, Sn-based oxides containing nitrogen, In-based oxides containing nitrogen, metal nitride films (indium nitride Alternatively, a film such as a titanium film, a zinc nitride film, a tantalum nitride film, or a tungsten nitride film may be used. Since the materials have a work function of 5 electron volts or more, it is possible to use these materials to fabricate gate electrodes. By forming the layer 402, the threshold voltage of the transistor can be made positive. An off-switching transistor can be realized.

[0085] Next, a gate insulating layer 404 is formed on the gate electrode layer 402 so as to cover the gate electrode layer 402. The gate insulating layer 404 is formed by a plasma CVD method, a sputtering method, or the like. Silicon oxide film, silicon oxynitride film, silicon nitride oxide film, nitride film, etc. Silicon film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film nium film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, acid The insulating film includes one or more of a cerium oxide film and a neodymium oxide film, and the insulating film is used as a single layer or a laminated layer. do.

[0086] Note that in the gate insulating layer 404, a region in contact with the oxide semiconductor stack 408 to be formed later is The region is preferably an oxide insulating layer, and more preferably has an oxygen excess region. To provide an oxygen-excess region in the gate insulating layer 404, for example, the gate insulating layer 404 is grown in an oxygen atmosphere. Alternatively, oxygen may be introduced into the gate insulating layer 404 after the deposition. An excess region may be formed. The oxygen introduction method may include ion implantation, ion doping, etc. method, plasma immersion ion implantation method, plasma treatment, etc. can be used.

[0087] Next, an oxide semiconductor film to be the oxide semiconductor layer 408c and an oxide semiconductor film to be the oxide semiconductor layer 408c were formed on the gate insulating layer 404. The oxide semiconductor film that becomes the oxide semiconductor layer 408b and the oxide semiconductor film that becomes the oxide semiconductor layer 408a are Conductive films are deposited in order and then processed into island shapes by etching using photolithography. Then, an oxide semiconductor stack 408 is formed (see FIG. 3B).

[0088] The oxide semiconductor layer 408c, the oxide semiconductor layer 408b, and the oxide semiconductor layer 408a are In addition, the oxide semiconductor may be an amorphous oxide semiconductor or a crystalline oxide semiconductor. The oxide semiconductor layer 408b functioning as a channel of the transistor 310 is a crystalline oxide semiconductor. It is preferable that the amorphous oxide semiconductor be a conductor. The amorphous oxide semiconductor may be an oxide semiconductor. °C or higher and 700 °C or lower, preferably 400 °C or higher, more preferably 500 °C or higher, and even more preferably Preferably, the temperature is 550°C or higher. This heat treatment can be used in conjunction with other heat treatments in the manufacturing process. is also possible.

[0089] The deposition methods for each oxide semiconductor film are sputtering, MBE (Molecular Beam Epitaxy), and am Epitaxy) method, CVD method, pulsed laser deposition method, ALD (Atomic L A layer deposition method or the like can be used as appropriate.

[0090] When forming an oxide semiconductor film, it is preferable to reduce the hydrogen concentration in the film as much as possible. In order to reduce the hydrogen concentration, for example, when forming a film by sputtering, The atmospheric gas supplied to the deposition chamber of the sputtering device is hydrogen, water, hydroxyl radicals, or The gas is a high-purity rare gas (typically argon) from which impurities such as hydrides have been removed, oxygen, and A mixed gas of a rare gas and oxygen is used as appropriate.

[0091] In addition, the residual moisture in the film formation chamber is removed and sputtering gas from which hydrogen and moisture have been removed is introduced. By forming the oxide semiconductor film in this manner, the hydrogen concentration in the formed oxide semiconductor film can be reduced. To remove residual moisture in the deposition chamber, an adsorption type vacuum pump, such as a cryopump, is used. It is preferable to use a turbo pump, an ion pump, or a titanium sublimation pump. A molecular pump with a cold trap may be used. , hydrogen molecules, water (H2O), and other compounds containing hydrogen atoms (preferably compounds containing carbon atoms) Because of its high pumping capacity, films are formed in a deposition chamber evacuated using a cryopump. The concentration of impurities contained therein can be reduced.

[0092] Note that the gate insulating layer 404 and the oxide semiconductor film are successively formed without exposure to the air. It is preferable that the gate insulating layer 404 and the oxide semiconductor film be formed in succession without exposure to the air. This prevents adhesion of hydrogen or hydrogen compounds (for example, adsorbed water) to the surface of the oxide semiconductor film. This can prevent the inclusion of impurities, thereby suppressing the inclusion of impurities.

[0093] In addition, when the oxide semiconductor film is formed by a sputtering method, the metal oxide substrate used for the film formation The relative density (filling rate) of the get is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. % or less. By using a metal oxide target with a high relative density, the film to be formed can be made into a dense film.

[0094] Note that the oxide semiconductor film may be formed while the substrate 400 is kept at a high temperature. This is effective in reducing the concentration of impurities that may be contained in the film. The substrate temperature is preferably 150°C or higher and 450°C or lower, and more preferably 200°C or higher and 300°C or lower. The temperature should be 50°C or less. In addition, by heating the substrate at a high temperature during film formation, the crystalline oxide semiconductor A conductive film can be formed.

[0095] A CAAC-OS film is used as an oxide semiconductor layer (for example, the oxide semiconductor layer 408b). In this case, the CAAC-OS film can be obtained by, for example, setting the film formation temperature at 200° C. or higher and 450° C. or higher. ℃ or less, and the c-axis is oriented approximately perpendicular to the surface. Alternatively, after forming a thin oxide semiconductor film, heat treatment at a temperature of 200° C. to 700° C. Alternatively, a thin film may be formed as the first layer, with the c-axis oriented approximately perpendicular to the surface. After that, heat treatment is performed at 200°C to 700°C, and the second layer is formed. The c-axis may be directly oriented.

[0096] The oxide semiconductors used for the oxide semiconductor layers 408a to 408c are It contains at least indium (In). In particular, it is preferable that it contains indium and zinc (Zn). In addition, in order to reduce variations in electrical characteristics of transistors using the oxide semiconductor, It is preferable to have gallium (Ga) in addition to these as a stabilizer.

[0097] As mentioned above, the oxide layer functions as a buffer layer to reduce the influence of trap levels. The semiconductor layer 408a and the oxide semiconductor layer 408c are formed by using a semiconductor material in which the composition of indium is gallium. It is preferable to use a metal oxide having a composition below 1000 ppm. The dielectric layer 408b is made of a metal oxide in which the indium content is greater than the gallium content. It is preferable that

[0098] As a stabilizer, instead of or in addition to gallium (Ga), Tin (Sn), hafnium (Hf), aluminum (Al), zirconium (Zr) The stabilizer may contain one or more of the above. The lanthanides lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Ne) Nemium (Nd), Samarium (Sm), Europium (Eu), Gadolinium (Gd), Te Rubium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er) , thulium (Tm), ytterbium (Yb), lutetium (Lu) or may have a plurality of types.

[0099] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, In-Mg oxides, In-Ga oxides, and ternary metal oxides Oxides such as In-Ga-Zn oxides, In-Al-Zn oxides, and In-Sn-Zn In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide Oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides , In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxides and In-Hf-Ga-Zn oxides, which are quaternary metal oxides Oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-S n-Hf-Zn based oxides and In-Hf-Al-Zn based oxides can be used.

[0100] For example, an In-Ga-Zn oxide is an oxide having In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. Metal elements may also be included.

[0101] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) It is also possible to use a material represented by the formula: where M is selected from Ga, Fe, Mn and Co. In2SnO 5(ZnO) n A material expressed as (n>0 and n is an integer) may be used.

[0102] The oxide semiconductor stack 408 is subjected to a thermal treatment to remove excess hydrogen (including water and hydroxyl groups) contained in the film. It is preferable to carry out a heat treatment for removing (dehydrating or dehydrogenating) the carbonyl group. The temperature should be between 00°C and 700°C, or below the strain point of the substrate. The heat treatment should be carried out under reduced pressure or in a nitrogen atmosphere. This heat treatment can be carried out under the following conditions. Hydrogen can be removed.

[0103] Note that the heat treatment for dehydration or dehydrogenation can be performed after the formation of the oxide semiconductor film. This may be carried out at any time during the process of producing the star. The heat treatment for this purpose may be carried out multiple times or may be carried out in combination with other heat treatments.

[0104] In heat treatment, nitrogen or rare gases such as helium, neon, and argon are mixed with water, hydrogen, etc. It is preferable that the nitrogen, helium, or neon introduced into the heat treatment device is not contained. The purity of the rare gas such as argon is 6N (99.9999%) or more, preferably 7N (99. 99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm or less) It is preferable to do so.

[0105] In addition, after the oxide semiconductor layer (or stacked oxide semiconductor layers) is heated by heat treatment, the heating temperature is maintained. Or, while slowly cooling from the heating temperature, high purity oxygen gas and high purity dinitrogen monoxide are added to the same furnace. Gas or ultra-dry air (CRDS (Cavity Ring Down Laser Spectroscopy) method dew point) The moisture content measured using a water meter is 20 ppm (-55°C in dew point equivalent) or less, preferably Oxygen gas or air (1 ppm or less, more preferably 10 ppb or less) may be introduced. It is preferable that the nitrous oxide gas does not contain water, hydrogen, etc. The purity of the oxygen gas or nitrous oxide gas to be introduced is 6N or more, preferably 7N or more (i.e., The impurity concentration in nitrogen gas or dinitrogen monoxide gas is 1 ppm or less, preferably 0.1 ppm or less. It is preferable to dehydrate or decompose the material by the action of oxygen gas or nitrous oxide gas. The oxide semiconductor that was reduced at the same time by the process of removing impurities through hydrogenation is formed. By supplying oxygen, which is the main component of the oxide semiconductor layer, the oxide semiconductor layer can be highly purified and made into an i-type oxide. It can be made (authentic).

[0106] In addition, there is a risk that oxygen may be simultaneously released and reduced during the dehydration or dehydrogenation treatment. Therefore, oxygen (at least oxygen lamination) is added to the oxide semiconductor layer that has been subjected to dehydration or dehydrogenation treatment. Even if oxygen is supplied to the film by introducing oxygen atoms (including dichlorides, oxygen atoms, or oxygen ions), good.

[0107] Oxygen is introduced into the oxide semiconductor layer that has been subjected to dehydration or dehydrogenation treatment to supply oxygen into the film. By this, the oxide semiconductor layer can be highly purified and made to be i-type (intrinsic). A transistor having a purified i-type (intrinsic) oxide semiconductor has low fluctuations in electrical characteristics. It is controlled and electrically stable.

[0108] When oxygen is introduced into the oxide semiconductor layer, it may be introduced directly into the oxide semiconductor layer or into a layer formed later. Oxygen (at least oxygen radiative) may be introduced into the oxide semiconductor layer through the insulating layer. The method of introducing the silicon dioxide (containing either ions, oxygen atoms, or oxygen ions) is ion implantation. On-doping method, plasma immersion ion implantation method, plasma treatment, etc. can be used. In addition, a gas containing oxygen can be used for the oxygen introduction process. The gases used may include oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, and carbon monoxide. In the oxygen introduction process, a rare gas may be contained in the oxygen-containing gas.

[0109] For example, when oxygen ions are implanted into an oxide semiconductor layer by ion implantation, the dose is set to 1× 10 13 ions / cm 2 5x10 or more 16 ions / cm 2 The following would suffice.

[0110] The timing for supplying oxygen to the oxide semiconductor layer is as follows: There is no particular limitation. Oxygen may be introduced multiple times.

[0111] Next, a conductive film is formed on the oxide semiconductor stack 408 and processed to form a source electrode layer 41 0a and drain electrode layer 410b (including wiring formed in the same layer) are formed ( See Figure 3(C)).

[0112] The source electrode layer 410a and the drain electrode layer 410b are made of, for example, Al, Cr, or Cu. a metal film containing an element selected from the group consisting of Ta, Ti, Mo, and W, or a film containing the above-mentioned elements as components; Metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) can be used. In addition, Ti, M, etc. can be deposited on either or both of the upper and lower sides of the metal film such as Al, Cu, etc. High-melting metal films such as titanium nitride and molybdenum nitride A stack of a source electrode layer 410a and a tungsten nitride film may be used. The drain electrode layer 410b may be formed of a conductive metal oxide. The oxides include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO ), indium oxide tin oxide (In2O3-SnO2), indium oxide zinc oxide (In 2O3-ZnO) or these metal oxide materials containing silicon oxide are used. It is possible.

[0113] The source electrode layer 410a and the drain electrode layer 410b are made of In—Ga— Zn-O film, In-Sn-O film containing nitrogen, In-Ga-O film containing nitrogen, I Metal nitride films such as n-Zn-O film, nitrogen-containing Sn-O film, and nitrogen-containing In-O film are used. These films contain the same constituent elements as the oxide semiconductor stack 408, and therefore, The interface with the nitride semiconductor stack 408 can be stabilized.

[0114] Note that a conductive film containing copper is used for the source electrode layer 410a and the drain electrode layer 410b. This is preferable because it can reduce the wiring resistance. It easily diffuses in silicon films, making the operation of semiconductor devices unstable and significantly reducing yields. However, in the transistor 310, the source electrode layer 410a and The drain electrode layer 410b is in contact with the drain electrode layer 410b to suppress the diffusion of the constituent element (copper in this case) of the electrode layer. Since the oxide semiconductor layer 408a functions as a buffer layer for preventing the diffusion of copper, This can reduce, preferably eliminate, the influence of the trap level on the back channel side.

[0115] Next, the source electrode layer 410a, the drain electrode layer 410b, and the exposed oxide semiconductor stack An insulating layer 412 is formed to cover the layer 408 (see FIG. 3D).

[0116] The insulating layer 412 can be formed by plasma CVD or sputtering. Silicon oxide film, gallium oxide film, aluminum oxide film, silicon nitride film, silicon oxynitride film A single layer or a laminate of a silicon oxide film, an aluminum oxide nitride film, or a silicon nitride oxide film, etc. However, when an oxide insulating layer is formed as the insulating layer 412, the oxide The insulating layer is preferably formed because oxygen can be supplied to the oxide semiconductor stack 408. stomach.

[0117] After forming the insulating layer 412, heat treatment may be performed. The temperature of the heat treatment is preferably 200° C. or higher. For example, 220°C may be used.

[0118] Through the above steps, the transistor 310 of this embodiment can be formed.

[0119] In the transistor described in this embodiment, a constituent element of the source electrode layer or the drain electrode layer is char. a first oxide semiconductor layer that functions as a buffer layer to prevent diffusion of the oxide semiconductor layer into the channel; and a second oxide semiconductor layer that functions as a transistor. This can reduce the influence of interface states that may be formed on the back channel side of the transistor. In addition, the transistor described in this embodiment has an oxide semiconductor layer functioning as a channel and a gate electrode. A buffer layer is provided between the gate insulating layer and the gate electrode to prevent deterioration of the interface of the channel on the gate insulating layer side. It is more preferable that the third oxide semiconductor layer function as a photoresist layer. The inclusion of the conductor layer can reduce light degradation (e.g., negative bias light degradation) of the transistor. This makes it possible to provide a highly reliable semiconductor device.

[0120] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0121] (Embodiment 2) In this embodiment mode, one mode of a semiconductor device different from that in Embodiment Mode 1 will be described with reference to FIG. Specifically, a transistor having a gate insulating layer different from that of the transistor described in Embodiment 1 is used. The following describes the transistor.

[0122] 10A shows a structural example of a transistor 320. 2, the transistor 320 is provided on a substrate 400 having an insulating surface. a gate electrode layer 402 formed thereon, gate insulating layers 403 and 406 on the gate electrode layer 402, and a gate insulating layer an oxide semiconductor stack 408 which is in contact with the gate insulating layer 406 and overlaps with the gate electrode layer 402; The source electrode layer 410a and the drain electrode layer 410b are electrically connected to the nitride semiconductor stack 408. In the transistor 320, the oxide semiconductor stack 408 includes a gate insulating film. The oxide semiconductor layer 408c in contact with the oxide semiconductor layer 406 and the oxide semiconductor layer 408c in contact with the oxide semiconductor layer 408c are The semiconductor layer 408b is provided on and in contact with the oxide semiconductor layer 408b. The source electrode layer 410b is connected to the oxide semiconductor layer 408a. The insulating layer 41 covers the oxide semiconductor stack 408 and the drain electrode layer 410b. 2 may be a component of transistor 320.

[0123] The transistor 320 has a gate insulating layer formed on the gate electrode layer 402 side. The first gate insulating layer 4 includes a gate insulating layer 403a, a gate insulating layer 403b, and a gate insulating layer 403c. 3. The transistor 310 differs from the transistor 310 in that it includes a stacked structure of a gate insulating layer 403 and a second gate insulating layer 406. do.

[0124] Note that the transistor 320 has the same structure as the transistor 310 except for the gate insulating layer. Similarly, the description of the transistor 310 can be referred to.

[0125] In the transistor 320, the first gate insulating layer 403 is a silicon film containing nitrogen. The silicon film containing nitrogen has a higher relative dielectric constant than the silicon oxide film, and Since the film thickness required to obtain this capacitance is large, it is necessary to physically thicken the gate insulating layer. Therefore, the decrease in the dielectric strength voltage of the transistor 320 can be suppressed, and further, the dielectric strength voltage can be improved. This makes it possible to suppress electrostatic breakdown of the semiconductor device.

[0126] The second gate insulating layer 406 in contact with the oxide semiconductor stack 408 is made of silicon oxide. An insulating layer containing oxygen, such as a silicon film, a gallium oxide film, or an aluminum oxide film, is applied. The insulating layer 406 includes a region containing oxygen in excess of the stoichiometric composition (oxygen excess region). It is more preferable that the insulating layer in contact with the oxide semiconductor stack 408 includes an oxygen-excess region. This allows oxygen to be supplied to the oxide semiconductor stack 408. This is because it is possible to prevent oxygen from being released from 8 and to compensate for oxygen vacancies. To provide an oxygen-excess region in the second gate insulating layer 406, for example, Alternatively, the second gate insulating layer 406 may be formed after deposition. Oxygen may be introduced to form an oxygen excess region.

[0127] The silicon film containing nitrogen used for the first gate insulating layer 403 is, for example, silicon nitride. Silicon nitride film, silicon oxide nitride film, silicon oxynitride film, The higher the content, the higher the relative dielectric constant, so it is preferable to use a silicon nitride film. In addition, the energy gap of silicon oxide is 8 eV, while that of silicon nitride is The energy gap is small at 5.5 eV, and the specific resistance is also small accordingly. Higher ESD (Electro-Static Discharge) e) It is possible to provide resistance. The term "silicon nitride oxide film" refers to a film whose composition contains more oxygen than nitrogen. refers to a film whose composition contains more nitrogen than oxygen.

[0128] The gate insulating layer 403a in contact with the gate electrode layer 402 has an ammonia content of at least The silicon film contains nitrogen at a lower concentration than the gate insulating layer 403b. The lone pair of electrons on the molecule acts as a ligand for the metal complex. When copper is used as the layer 402, a gate insulating layer having a high ammonia content is used as the gate electrode. When the gate insulating layer is provided in contact with the gate insulating layer, copper diffuses into the gate insulating layer by the reaction shown in formula (1) below. There is a risk that this may happen.

[0129]

number

[0130] The transistor 320 has a low ammonia content (at least in the gate insulating layer 403 b) is provided in contact with the gate electrode layer 402. The material (for example, copper) of the gate electrode layer 402 diffuses into the first gate insulating layer 403. That is, the gate insulating layer 403a can suppress the gate electrode layer 402. The gate insulating layer 403a can function as a barrier film against the metal material. By doing so, the reliability of the transistor can be further improved.

[0131] The gate insulating layer 403b has a thickness greater than that of the gate insulating layer 403a, and the defects in the film are reduced. For example, the gate insulating layer 403b is formed to a thickness of 300 nm. In addition, the electron spin resonance (ESR) method In the signal measured by the Nc center (g value is 2. 003) the spin density of the signal appearing in the 17 spins / cm 3 below , more preferably 5 × 10 16 spins / cm 3 A silicon film containing nitrogen having a content of 0.01 or less is applied. In this way, a silicon film containing nitrogen with reduced defects in the film is formed to a large thickness (for example, 300 nm or more), the ESD resistance of the gate insulating layer 403b can be increased to, for example, 3 It is possible to set it to 00V or higher.

[0132] The gate insulating layer 403c is a silicon film containing nitrogen with a reduced hydrogen concentration. The hydrogen concentration of the gate insulating layer 403c is at least lower than that of the gate insulating layer 403b. For example, when the gate insulating layer 403c is formed by plasma CVD, the supply The hydrogen concentration in the gas is made lower than that of the supply gas used to form the gate insulating layer 403b. By this, the hydrogen concentration in the gate insulating layer 403c can be reduced more than that in the gate insulating layer 403b. Specifically, the gate insulating layer 403b and the gate insulating layer 403c can be made of silicon nitride. When forming a SiO2 film, ammonia is used as the supply gas rather than the supply gas for forming the gate insulating layer 403b. The gate insulating layer 403c may be formed by reducing the flow rate of ammonia or by using no ammonia.

[0133] By providing a silicon nitride film containing reduced hydrogen as the gate insulating layer 403c, The second gate insulating layer 406 and the oxide semiconductor stack 408 are doped with hydrogen or a hydrogen compound (e.g., For example, the inclusion of hydrogen (water) can be reduced. The part acts as a donor, generating electrons as carriers and minimizing the threshold voltage of the transistor. Silicon nitride film with reduced hydrogen concentration is a factor that causes a shift in the direction of the electron beam. By providing the gate insulating layer 403c, the electrical characteristics of the transistor can be stabilized. In addition, a silicon nitride film with a reduced hydrogen concentration can be used as the gate insulating layer 403c. By providing the insulating layer 403b, impurities such as hydrogen or a hydrogen compound contained in the gate insulating layer 403b can be oxidized. It also functions as a barrier film to prevent diffusion into the compound semiconductor stack 408 .

[0134] In this embodiment, the first gate insulating layer 403 is made up of a gate insulating layer 403a, a gate insulating layer 403b, and a gate insulating layer 403c. The insulating layer 403b and the gate insulating layer 403c are made of silicon nitride films, and the second gate insulating layer 403b is made of silicon nitride films. A silicon oxynitride film is used as the insulating layer 406, and each gate insulating layer is formed by plasma CVD. Specifically, the mixture of silane (SiH4) and nitrogen (N2) After supplying gas to form a silicon nitride film that will become the gate insulating layer 403a, the supply gas is Switch to a mixture of lanthanum (SiH4), nitrogen (N2) and ammonia (NH3) gases. A silicon nitride film that becomes the gate insulating layer 403b is formed, and then the supply gas is changed to silane (Si The gas is switched to a mixture of H4 and nitrogen (N2), and silicon nitride that will become the gate insulating layer 403c is formed. After that, the supply gas was changed to silane (SiH4) and nitrous oxide (N2O). Instead, a silicon oxynitride film to be the second gate insulating layer 406 is formed.

[0135] The thickness of the gate insulating layer 403a is 30 nm or more and 100 nm or less, preferably 30 nm or more. It is preferable to set the thickness to 50 nm or less. The thickness of the gate insulating layer 403b is preferably 300 nm or more and 400 nm or less. The gate insulating layer 40 functions as a barrier film to prevent hydrogen diffusion into the compound semiconductor stack 408. The thickness of the second gate electrode 3c is preferably 25 nm or more and 150 nm or less. The thickness of the insulating layer 406 is preferably 25 nm or more and 100 nm or less. The thickness of the gate insulating layer 403 (the gate insulating layer 403a, the gate insulating layer 403b, and the gate The total thickness of the insulating layer 403c and the second gate insulating layer 406 is 355n. It is preferable to appropriately adjust the film thickness of each gate insulating layer so that the thickness is 500 nm or more and 550 nm or less. stomach.

[0136] Note that as in the transistor 330 shown in FIG. 10B, the first gate insulating layer 403 and the second gate insulating layer 404 are The gate insulating layer including the stack of the gate insulating layer 406 and the oxide semiconductor layer 408b is formed by The oxide semiconductor layer 408 is used in combination with the oxide semiconductor layer 408a. is also possible.

[0137] In the transistor described in this embodiment, a constituent element of the source electrode layer or the drain electrode layer is char. a first oxide semiconductor layer that functions as a buffer layer to prevent diffusion of the oxide semiconductor layer into the channel; and a second oxide semiconductor layer that functions as a transistor. This can reduce the influence of interface states that may be formed on the back channel side of the transistor. In addition, the transistor described in this embodiment has an oxide semiconductor layer functioning as a channel and a gate electrode. A buffer layer is provided between the gate insulating layer and the gate electrode to prevent deterioration of the interface of the channel on the gate insulating layer side. It is more preferable that the third oxide semiconductor layer function as a photoresist layer. The inclusion of the conductor layer can reduce light degradation (e.g., negative bias light degradation) of the transistor. This makes it possible to provide a highly reliable semiconductor device.

[0138] In addition, in the transistor described in this embodiment, a gate insulating layer is formed by using a gate electrode layer. Nitrogen-containing silicon films that function as barrier films against elements (e.g., copper), thick films (e.g., A silicon film containing nitrogen with reduced defects in the film (thickness 300 nm), and a silicon film with low hydrogen concentration a first gate electrode including a silicon film containing nitrogen and having a blocking property against hydrogen; The transistor has a stacked structure of an insulating layer and a second gate insulating layer containing oxygen. Therefore, the transistor of this embodiment can suppress fluctuations in electrical characteristics and electrostatic breakdown. By including such a transistor, highly reliable semiconductor devices can be manufactured with high yield. It can be provided easily.

[0139] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0140] (Embodiment 3) A semiconductor device having a display function (display device) using the transistor described in Embodiment 1 or 2 In addition, a part or the whole of a driver circuit including a transistor can be manufactured. The body can be integrally formed on the same substrate as the pixel portion to form a system-on-panel.

[0141] In FIG. 4A, a substrate 4001 is provided on a substrate 4001 so as to surround a pixel portion 4002. A sealing material 4005 is provided and sealed with a substrate 4006. is deposited in an area different from the area surrounded by the sealing material 4005 on the substrate 4001. C chip or a separately prepared substrate formed with a single crystal semiconductor film or a polycrystalline semiconductor film A scanning line driver circuit 4004 and a signal line driver circuit 4003 are mounted. Various signals and signals are given to the pixel portion 4002 through a line 4003 and a scanning line driver circuit 4004. The potential is FPC (Flexible printed circuit) 4018a, 4 Powered by 018b.

[0142] In FIG. 4B and FIG. 4C, a pixel portion 4002 is provided on a substrate 4001, and A sealant 4005 is provided so as to surround the scanning line driver circuit 4004. A substrate 4006 is provided on the element portion 4002 and the scanning line driver circuit 4004. The pixel portion 4002 and the scanning line driver circuit 4004 are formed by a substrate 4001, a sealing material 4005 and a substrate. The display element is sealed by a plate 4006. is deposited in an area different from the area surrounded by the sealing material 4005 on the substrate 4001. C chip or a separately prepared substrate formed with a single crystal semiconductor film or a polycrystalline semiconductor film A signal line driver circuit 4003 is mounted. Various signals are applied to the pixel portion 4002 through a line driver circuit 4003 and a scanning line driver circuit 4004. Signals and potentials are supplied from FPC4018.

[0143] In addition, in FIG. 4B and FIG. 4C, a signal line driver circuit 4003 is formed separately, and 4001, but the present invention is not limited to this configuration. It may be formed separately and mounted, or only a part of the signal line driver circuit or a part of the scanning line driver circuit may be mounted. It may be formed separately and mounted.

[0144] The method of connecting the separately formed drive circuit is not particularly limited, and may be ip On Glass) method, wire bonding method, or TAB (Tape A The C This is an example in which a signal line driver circuit 4003 and a scanning line driver circuit 4004 are implemented by the OG method. FIG. 4(B) shows an example in which a signal line driver circuit 4003 is mounted by the COG method, and FIG. 4(C) shows an example in which a signal line driver circuit 4003 is mounted by the COG method. ) is an example in which the signal line driver circuit 4003 is mounted by the TAB method.

[0145] The display device is a panel in which a display element is sealed, and a controller connected to the panel. This includes modules in which ICs including lasers are mounted. The display device refers to an image display device, a display device, or a light source (including a lighting device). In addition to the panel in which the display element is sealed, connectors, such as FP A module with a C or TCP attached, a printed wiring board is attached to the end of the TCP or a module in which an IC (integrated circuit) is directly mounted on the display element using the COG method. All modules are included in the display device.

[0146] The pixel portion and the scanning line driver circuit provided on the substrate each have a plurality of transistors. The transistor described in Embodiment 1 or 2 can be applied.

[0147] The display element provided in the display device may be a liquid crystal element (also called a liquid crystal display element), a light-emitting element ( The light-emitting element can change its brightness depending on the current or voltage. This category includes elements that are controlled by the Also included are electronic ink displays (e-page displays), organic EL displays, etc. It can also be used for display media in which the contrast changes due to electrical effects, such as LCD. .

[0148] One mode of a semiconductor device will be described with reference to FIGS. 4A and 4B. FIG. 5 shows the M This corresponds to a cross-sectional view taken along line -N. In FIG. 5, a liquid crystal display device is used in which a liquid crystal element is used as a display element. Here is an example:

[0149] However, in the display device, the transistor 4010 provided in the pixel portion 4002 is electrically connected to the display element. The display element is not particularly limited as long as it can display an image. A variety of display elements can be used.

[0150] As shown in FIGS. 4 and 5, the semiconductor device has a connection terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrodes 4015 and the terminal electrodes 4016 are connected to an FPC 4018 (4018a , 4018b) via an anisotropic conductive layer 4019. .

[0151] The connection terminal electrode 4015 is formed from the same conductive layer as the first electrode layer 4034, and the terminal electrode 4 016 is the same conductor as the source electrode layer and the drain electrode layer of the transistors 4010 and 4011. The insulating layer is formed of a conductive layer.

[0152] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a substrate 4001. 4 and 5, the pixel portion 4002 includes a transistor 4 4004 and a transistor 4011 included in the scan line driver circuit 4004 are shown as examples. In FIG. 5, an insulating layer 4032 is provided over the transistors 4010 and 4011 .

[0153] The transistors 4010 and 4011 are the transistors described in Embodiment 1 or 2. In this embodiment, the transistor 310 described in Embodiment 1 and An example of applying transistors having a similar structure is shown below. Transistors 4010 and 4011 is a transistor with a bottom gate structure.

[0154] The transistors 4010 and 4011 have a source electrode layer or a drain electrode layer containing a charcoal. a first oxide semiconductor layer that functions as a buffer layer to prevent diffusion of the oxide semiconductor layer into the channel; a second oxide semiconductor layer functioning as a panel; and an oxide semiconductor layer functioning as a channel. A gate insulating layer is provided between the gate insulating layer and the channel to prevent deterioration of the interface on the gate insulating layer side. and a third oxide semiconductor layer functioning as a buffer layer. The transistors 4010 and 4011 are formed in a structure that reduces the influence of interface states that may be formed on the back channel side. The reliability of the transistor is improved by reducing light degradation (e.g., negative bias light degradation). It is a high performance transistor.

[0155] In addition, the oxide semiconductor layer of the transistor 4011 for the driver circuit overlaps with the channel formation region of the oxide semiconductor layer. A conductive layer may be further provided at a position overlapping with the channel formation region of the oxide semiconductor layer. By providing the transistor 4011 at a position where the threshold voltage of the transistor 4011 is higher than the threshold voltage of the transistor 4011, the amount of change in the threshold voltage of the transistor 4011 can be further reduced. In addition, the conductive layer has a potential equal to that of the gate electrode layer of the transistor 4011. It may be the same as or different from the first gate electrode layer and may also function as a second gate electrode layer. The potential of the conductive layer may be in a floating state.

[0156] The conductive layer also shields external electric fields, i.e., prevents external electric fields from reaching the internal It also has a function (particularly an electrostatic shielding function against static electricity) to prevent it from acting on the circuitry (including the circuit section). The shielding function of the conductive layer prevents the transistor from being electrically damaged by external electric fields such as static electricity. Fluctuations in characteristics can be prevented.

[0157] In FIG. 5, the liquid crystal element 4013 includes a first electrode layer 4034, a second electrode layer 4031, and a and a liquid crystal layer 4008. The liquid crystal layer 4008 is sandwiched between two layers that function as alignment films. Insulating layers 4038 and 4033 are provided. The second electrode layer 4031 is on the substrate 4006 side. The first electrode layer 4034 and the second electrode layer 4031 are stacked with the liquid crystal layer 4008 interposed therebetween. It has a layered structure.

[0158] The first electrode layer 4034 and the second electrode layer 4031 are made of an indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide , silicon oxide-doped indium tin oxide, graphene, and other transparent conductive materials Fees can be used.

[0159] The first electrode layer 4034 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag), It can be formed by using one or more of the metals, alloys thereof, or metal nitrides thereof. Cut.

[0160] The first electrode layer 4034 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer can be formed using a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or Copolymers consisting of two or more of aniline, pyrrole and thiophene, or derivatives thereof Examples include:

[0161] The spacers 4035 are columnar spacers obtained by selectively etching the insulating layer. and is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. Spherical spacers may also be used.

[0162] When liquid crystal elements are used as display elements, thermotropic liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, These liquid crystal materials can be low molecular weight compounds or high molecular weight compounds. These liquid crystal materials (liquid crystal compositions) may exhibit a cholesteric phase, a smectic phase, or the like depending on the conditions. These phases include nematic, cubic, chiral, and isotropic phases.

[0163] In addition, a liquid crystal composition that exhibits a blue phase without using an alignment film may be used for the liquid crystal layer 4008. In this case, the liquid crystal layer 4008, the first electrode layer 4034, and the second electrode layer 4031 The blue phase is one of the liquid crystal phases, and when the temperature of the cholesteric liquid crystal is increased, The blue phase is the phase that appears just before the transition from the cholesteric phase to the isotropic phase. It can be expressed by using a liquid crystal composition in which a chiral agent and a blue In order to widen the temperature range in which the blue phase appears, a polymerizable monomer is added to the liquid crystal composition that appears the blue phase. A polymerization initiator may also be added to form a liquid crystal layer by carrying out a polymer stabilization process. The liquid crystal composition exhibiting the blue phase has a short response time and is optically isotropic, so Since alignment treatment is not required, the viewing angle dependency is small. This eliminates the need for rubbing, preventing electrostatic damage caused by rubbing. This makes it possible to reduce defects and damage to the liquid crystal display device during the manufacturing process. This makes it possible to improve the productivity of the display device.

[0164] The specific resistance of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. The resistivity values ​​in this document are those measured at 20°C.

[0165] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. It is set so that the charge can be held for a predetermined period, taking into consideration the current and other factors. The size of the oxide film may be set in consideration of the off-state current of the transistor. By using a transistor with a semiconductor layer, the liquid crystal capacitance in each pixel It is sufficient to provide a storage volume having a size of 1 / 3 or less, preferably 1 / 5 or less, of the capacity of the do.

[0166] The transistor including the oxide semiconductor layer disclosed in this specification has a current value ( Therefore, the retention time of electrical signals such as image signals can be controlled to be low. The refresh interval can be set to a longer value. This reduces the power consumption.

[0167] In addition, the transistor including the oxide semiconductor layer disclosed in this specification has a relatively high field effect For example, such a transistor can be used in a liquid crystal display. By using it in a display device, it can be used as a switching transistor in the pixel section and a transistor in the driver circuit section. The driver transistor can be formed on the same substrate. By using such a transistor, high-quality images can be provided.

[0168] There are two types of LCD displays: TN (Twisted Nematic) mode, IPS (In-P lane-Switching) mode, FFS(Fringe Field Switching) mode, ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0169] Furthermore, normally black type liquid crystal display devices, for example, those employing vertical alignment (VA) mode The liquid crystal display device may be a transmission type. For example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode , ASV (Advanced Super View) mode, etc. can be used. It can also be applied to VA type liquid crystal display devices. VA type liquid crystal display devices are: It is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel. VA type liquid crystal display devices are When no voltage is applied, the liquid crystal molecules are oriented perpendicular to the panel surface. In addition, a pixel is divided into several regions (subpixels), each of which is oriented in a different direction. This is called multi-domain or multi-domain design, which is designed to knock down molecules. The following method can be used.

[0170] In addition, in display devices, black matrices (light-shielding layers), polarizing members, phase difference members, reflecting members, Optical members (optical substrates) such as a protection member are provided as appropriate. For example, a polarizing substrate and a retardation substrate are provided as appropriate. Alternatively, a backlight or a sidelight may be used as the light source. It's fine.

[0171] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (W stands for white). , or RGB plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may be different for each dot of the color element. is not limited to color display devices, but also applies to monochrome display devices. It is also possible.

[0172] 11, in the display device shown in FIG. 5, the second electrode layer 403 provided on the substrate 4006 1, a common connection portion (pad portion) for electrically connecting to the substrate 4001 is formed on the substrate 4001. show.

[0173] The common connection portion is located at a position overlapping the sealing material for bonding the substrate 4001 and the substrate 4006. and electrically connected to the second electrode layer 4031 via conductive particles contained in the sealing material. Alternatively, a common connection part is provided in a place where it does not overlap with the sealing material (excluding the pixel part), A paste containing conductive particles is provided separately from the sealing material so as to overlap the common connection portion, forming a second electrode. It may be electrically connected to the pole layer 4031 .

[0174] FIG. 11(A) is a cross-sectional view of the common connection portion, and corresponds to G1-G2 in the top view shown in FIG. 11(B). Equivalent.

[0175] The common potential line 491 is provided on the gate insulating layer 4020 and is connected to the transistor 40 shown in FIG. 10, 4011 are made of the same material and in the same process as the source electrode layer or drain electrode layer of .

[0176] The common potential line 491 is covered with an insulating layer 4032. 91. The openings are formed by A contact that connects one of the source electrode layer and the drain electrode layer to the first electrode layer 4034 It is made using the same process as a hole.

[0177] The common electrode 492 is provided on an insulating layer 4032, and the connection terminal electrode 4015 and the pixel The first electrode layer 4034 is made of the same material and in the same process as the first electrode layer 4034 of the first electrode layer 4034.

[0178] In this way, the common connection portion is formed by the same manufacturing process as the switching element of the pixel portion 4002. It can be manufactured.

[0179] The common electrode 492 is an electrode that comes into contact with the conductive particles contained in the sealing material, and is connected to the substrate 4006 Electrical connection is made with the second electrode layer 4031.

[0180] 11C, the common potential line 491 is connected to the transistors 4010 and 401 It may be made of the same material and in the same process as the gate electrode layer 1.

[0181] In the common connection portion shown in FIG. 11(C), the common potential line 491 is connected to the gate insulating layer 4020 and The gate insulating layer 4020 and the insulating layer 4032 are provided below the gate insulating layer 4020 and the insulating layer 4032. The transistor 4010 has a plurality of openings at positions overlapping with the potential line 491. A contact that connects one of the source electrode layer and the drain electrode layer to the first electrode layer 4034 After etching the insulating layer 4032 in the same process as the hole, the gate insulating layer 4020 is is formed by selectively etching.

[0182] Furthermore, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. The light-emitting element using electroluminescence can be applied to a light-emitting material They are distinguished by whether they are organic or inorganic compounds, and generally, the former are organic E The latter is called an inorganic EL element.

[0183] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element. An example using an organic EL element is shown below.

[0184] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0185] In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes needs to be light-transmitting. Then, a transistor and a light emitting element are formed on the substrate, and light is extracted from the surface opposite to the substrate. There are various types of light sources, including top emission, bottom emission, and light emission from the substrate side and the opposite side of the substrate. There are light emitting elements with a double-sided emission structure that emits light from both sides, and light emitting elements of any emission structure can be applied. It is possible.

[0186] 6A, 6B, and 13 show examples of light-emitting devices using light-emitting elements as display elements.

[0187] FIG. 6A is a plan view of the light emitting device, and dashed lines S1-T1 and S2-T2 in FIG. , and the cross section taken along S3-T3 corresponds to FIG. 6(B). Also, FIG. 13 corresponds to FIG. 6(A). This corresponds to a cross-sectional view taken along the dashed line S4-T4 in FIG. In this figure, the electroluminescent layer 542 and the second electrode layer 543 are omitted and are not shown.

[0188] The light-emitting device shown in FIG. 6 includes a transistor 510, a capacitor 520, a wiring layer 530, and a capacitor 540 disposed on a substrate 500. The transistor 510 has an intersection 530, and is electrically connected to a light emitting element 540. 6 shows a bottom emission type in which light from the light emitting element 540 is extracted through the substrate 500. It is a light emitting device having the following structure.

[0189] The transistor described in Embodiment 1 or 2 can be used as the transistor 510. In this embodiment, a transistor having a structure similar to that of the transistor 330 described in Embodiment 2 can be used. The transistor 510 is a bottom-gate transistor. It is a transistor.

[0190] The transistor 510 includes gate electrode layers 511a and 511b, gate insulating layers 502a and 502b, and a the gate insulating layer 502 including the oxide semiconductor layer 51b and 502c; The oxide semiconductor stack 512 including 2a, the conductive layer serving as a source electrode layer or a drain electrode layer, The transistor 510 includes insulating layers 513a and 513b. An insulating layer 525 is formed on the transistor 510. It is being done.

[0191] The capacitor element 520 includes conductive layers 521a and 521b, a gate insulating layer 502, and an oxide semiconductor layer 5 22b, an oxide semiconductor stack 522 including an oxide semiconductor layer 522a and a conductive layer 523; The conductive layers 521a and 521b and the conductive layer 523 form a gate insulating layer 502 and an oxide semiconductor layer. The layer 522 is sandwiched to form a capacitance.

[0192] The wiring layer intersection 530 is an intersection between the gate electrode layers 511a and 511b and the conductive layer 533. The gate electrode layers 511a and 511b and the conductive layer 533 are provided with a gate insulating layer 502 therebetween. Intersect via.

[0193] In this embodiment, the gate electrode layer 511a and the conductive layer 521a are formed to a thickness of 30 nm. A titanium film of 200 nm thick was used as the gate electrode layer 511b and the conductive layer 521b. Therefore, the gate electrode layer has a stacked structure of a titanium film and a copper film.

[0194] The transistor 510 includes an oxide semiconductor layer 512b functioning as a channel and a conductive layer 51 3a and the conductive layer 513b as a buffer layer to prevent the constituent elements of the conductive layer 513b from diffusing into the channel. and an oxide semiconductor layer 512a functioning as a gate insulating film. The effect of the interface state that can be formed on the back channel side is reduced, resulting in a highly reliable transistor. It is a star.

[0195] The transistor 510 also includes a gate insulating layer 502c having a reduced ammonia content. The gate insulating layer 502a includes a silicon film containing nitrogen, which functions as a barrier film for the copper. The silicon film containing nitrogen and having reduced defects in the thick film (for example, 300 nm thick) is also included. The gate insulating layer 502b has a silicon film containing nitrogen with a reduced hydrogen concentration. By using such a structure, the electrical characteristics of the transistor 510 can be improved. This is advantageous and also prevents electrostatic damage to the transistor 510. As a result, highly reliable semiconductor devices can be provided with a high yield.

[0196] An interlayer insulating layer 504 is formed on the transistor 510, the capacitor element 520, and the wiring layer intersection 530. A color filter is formed on the interlayer insulating layer 504 in an area overlapping the light emitting element 540. A flat insulating layer 505 is provided on the interlayer insulating layer 504 and the color filter layer 505. An insulating layer 506 is provided which functions as a protective insulating layer.

[0197] A first electrode layer 541, an electroluminescent layer 542, and a second electrode layer 543 are stacked in this order on an insulating layer 506. The light emitting element 540 includes a stacked structure. 510 is an opening formed in the insulating layer 506 and the interlayer insulating layer 504 that reaches the conductive layer 513a. At this point, the first electrode layer 541 and the conductive layer 513a are in contact with each other, thereby forming an electrical connection. A partition wall 507 is provided to cover a part of the first electrode layer 541 and the opening. It is being done.

[0198] The insulating layer 506 is a photosensitive acrylic film with a thickness of 1500 nm, and the partition wall 507 is a nm photosensitive polyimide film can be used.

[0199] The color filter layer 505 may be made of, for example, a transparent resin of a chromatic color. As the colored light-transmitting resin, photosensitive or non-photosensitive organic resins can be used. The use of a functional organic resin layer reduces the number of resist masks, simplifying the process. And preferable.

[0200] Chromatic colors are colors other than achromatic colors such as black, gray, and white. It is made of materials that transmit only colored light. Chromatic colors include red, green, and blue. Also, cyan, magenta, yellow, etc. may be used. The color filter layer transmits only light of the selected chromatic color. The color filter layer has a peak at the wavelength of light of It is advisable to appropriately control the optimum film thickness taking into consideration the relationship between the concentration of the color and the light transmittance. The thickness of the filter layer 505 may be set to 1500 nm or more and 2000 nm or less.

[0201] The partition wall 507 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin material. An opening is formed on the first electrode layer 541 using a material, and the sidewall of the opening has a continuous curvature. It is preferable to form the inclined surface so that the inclined surface is formed with a curved surface.

[0202] The electroluminescent layer 542 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's

[0203] The second electrode layer 5 is formed so as to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 540. A protective film may be formed on the insulating film 43 and the partition wall 507. The protective film may be a silicon nitride film, a nitride film, or the like. Silicon oxide films, DLC films, etc. can be formed.

[0204] In addition, in order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 540, A layer containing an organic compound covering 540 may be formed by evaporation.

[0205] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0206] It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display (electrophoretic display), and is a paper It is possible to make it as easy to read as a digital camera, consume less power than other display devices, and have a thinner and lighter form factor. This has the advantage that

[0207] The electrophoretic display device may have various forms, but it has a structure in which first particles having a positive charge and and a second particle having a negative charge, and a plurality of microcapsules containing the first particle and the second particle having a negative charge are dispersed in a solvent. By applying an electric field to the microcapsules, the particles in the microcapsules The particles are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye and do not move in the absence of an electric field. In addition, the color of the first particles and the color of the second particles are different (including colorless).

[0208] The microcapsules dispersed in a solvent are called electronic ink. Color display is also possible by using color filters or particles containing pigments.

[0209] The insulating layer 506, which functions as a planarizing insulating layer, is made of acrylic resin, polyimide, benzo Uses heat-resistant organic materials such as cyclobutene resin, polyamide, and epoxy resin. In addition to the above organic materials, siloxane resin, PSG (phosphor glass), B Low-k materials such as PSG (Phosphorus-Boron Glass) can be used. The insulating layer 506 is formed by stacking a plurality of insulating layers made of these materials. You may do so.

[0210] The method for forming the insulating layer 506 is not particularly limited, and may be a sputtering method, a spin-on method, or the like, depending on the material. Coating, dipping, spray coating, droplet ejection method (inkjet method), screen printing , offset printing, etc. can be used.

[0211] The first electrode layer 541 and the second electrode layer 543 are the same as the first electrode layer of the display device shown in FIG. 4034, the same material as that of the second electrode layer 4031 can be applied.

[0212] In this embodiment, the light emitting device shown in FIG. 6 is a bottom emission type, so the first electrode layer 541 The first electrode layer 541 has a light-transmitting property, and the second electrode layer 543 has a reflective property. When using a conductive film, the film thickness is thin enough to maintain light transmission, and the second electrode layer 543 is made thin enough to maintain light transmission. When a conductive layer is used, it is preferable to laminate a conductive layer having reflectivity.

[0213] A protection circuit for protecting the drive circuit may be provided. The protection circuit is configured using a nonlinear element. It is preferable to do so.

[0214] As described above, by using the transistor described in Embodiment 1 or 2, various functions can be realized. It is possible to provide a semiconductor device having the above structure.

[0215] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0216] (Fourth embodiment) An image sensor that reads information about an object using the transistor shown in the first or second embodiment. Therefore, a semiconductor device having a sensor function can be manufactured.

[0217] FIG. 7A shows an example of a semiconductor device having an image sensor function. 7(A) is an equivalent circuit of the photosensor, and FIG. 7(B) is a cross-sectional view showing a part of the photosensor.

[0218] The photodiode 602 has one electrode connected to a photodiode reset signal line 658 and the other One electrode is electrically connected to the gate of transistor 640. One of the source and drain is connected to the photosensor reference signal line 672, and the other of the source and drain is connected to the photosensor reference signal line 673. The other terminal is electrically connected to one of the source and drain terminals of the transistor 656. The transistor 656 has a gate connected to a gate signal line 659 and a source or drain connected to a photodiode. The signal line 671 is electrically connected to the sensor output signal line 671.

[0219] Note that in the circuit diagrams in this specification, a transistor including an oxide semiconductor layer is not clearly shown. To make it easier to distinguish, the symbol for a transistor using an oxide semiconductor layer is written as “OS.” In FIG. 7A, a transistor 640 and a transistor 656 are the same as those in Embodiment 1 or The transistor shown in 2 can be applied to this transistor, which is a transistor using an oxide semiconductor layer. In this embodiment, a transistor having a structure similar to that of the transistor 320 shown in the first embodiment is used. The transistor 640 is a bottom-gate transistor. be.

[0220] FIG. 7B shows the photodiode 602 and the transistor 640 in the photosensor. 6 is a cross-sectional view showing a substrate 601 (element substrate) having an insulating surface on which a sensor functioning as a sensor is formed. A photodiode 602 and a transistor 640 are provided. 602, a substrate 613 is provided on the transistor 640 using an adhesive layer 608. .

[0221] An insulating layer 632, an interlayer insulating layer 633, and an interlayer insulating layer 634 are provided on the transistor 640. The photodiode 602 is formed on an electrode layer 641b formed on an interlayer insulating layer 633. A first semiconductor film 606a, a second semiconductor film 606b, and a second semiconductor film 606b are stacked in this order on the electrode layer 641b. and the third semiconductor film 606c, and the first to third semiconductor films provided on the interlayer insulating layer 634. an electrode layer 642 electrically connected to the electrode layer 641b via a and an electrode layer 641a that is electrically connected to the electrode layer 642.

[0222] The electrode layer 641b is electrically connected to the conductive layer 643 formed on the interlayer insulating layer 634. The layer 642 is electrically connected to the conductive layer 645 via the electrode layer 641a. is electrically connected to the gate electrode layer of the transistor 640, and 2 is electrically connected to transistor 640.

[0223] Here, the first semiconductor film 606a is a semiconductor film having a p-type conductivity, and the second semiconductor film 606b is a high resistance semiconductor film (i-type semiconductor film), and the third semiconductor film 606c is an n-type A pin-type photodiode in which semiconductor films having different conductivity types are stacked is shown as an example.

[0224] The first semiconductor film 606a is a p-type semiconductor film, and is an amorphous film containing an impurity element that imparts p-type. The first semiconductor film 606a can be formed from a group 13 silicon film. Using semiconductor material gas containing impurity elements (e.g., boron (B)), plasma CVD is used. Silane (SiH4) can be used as the semiconductor material gas. Alternatively, i2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may be used. In addition, after forming an amorphous silicon film that does not contain impurity elements, the film is formed by diffusion or ion implantation. Impurity elements may be introduced into the amorphous silicon film by using a method such as ion implantation. It is preferable to diffuse the impurity element by heating or the like after introducing the impurity element. In this case, the amorphous silicon film can be formed by LPCVD, vapor phase growth, Alternatively, sputtering or the like may be used. The thickness of the first semiconductor film 606a is 10 nm or more and 5 nm or less. It is preferable to form it so that the thickness is 0 nm or less.

[0225] The second semiconductor film 606b is an i-type semiconductor film (intrinsic semiconductor film) and is made of amorphous silicon. The second semiconductor film 606b is formed by amorphous silicon using a semiconductor material gas. A thick silicon film is formed by plasma CVD. The semiconductor material gas is silane. (SiH4) can be used. Alternatively, Si2H6, SiH2Cl2, SiHCl3, S The second semiconductor film 606b may be formed by LPCVD. The second semiconductor film 606b may be formed by vapor deposition, sputtering, or the like. It is preferable to form the film so that the thickness is 00 nm or more and 1000 nm or less.

[0226] The third semiconductor film 606c is an n-type semiconductor film and is an amorphous film containing an impurity element that imparts n-type. The third semiconductor film 606c is formed of a thick silicon film. It is formed by the plasma CVD method using a semiconductor material gas containing silicon (e.g., phosphorus (P)). Silane (SiH4) can be used as the semiconductor material gas. SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. After forming an amorphous silicon film that does not contain elements, the film is then doped with silicon using diffusion or ion implantation. An impurity element may be introduced into the amorphous silicon film by ion implantation or the like. After the element is introduced, the impurity element may be diffused by heating or the like. The amorphous silicon film can be formed by LPCVD, vapor phase growth, or sputtering. The thickness of the third semiconductor film 606c is 20 nm or more and 200 nm or less. It is preferable to form it so that it faces downward.

[0227] The first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c are Instead of an amorphous semiconductor, it may be formed using a polycrystalline semiconductor, or a microcrystalline (semi-amorphous) semiconductor. Rufus (Semi Amorphous Semiconductor: SAS) Semiconductor It may also be formed using a conductor.

[0228] In addition, the mobility of holes generated by the photoelectric effect is smaller than that of electrons, so the pin-type The photodiode exhibits better characteristics when the p-type semiconductor film side is used as the light receiving surface. From the surface of the substrate 601 on which the in-type photodiode is formed to the photodiode 602 This shows an example of converting the light received by the semiconductor film into an electrical signal. Since light from the semiconductor film side having a pattern becomes disturbance light, a conductive layer with light blocking properties is used for the electrode layer. It is also possible to use the n-type semiconductor film side as the light-receiving surface.

[0229] The transistor 640 is a transistor in which a constituent element of the source electrode layer or the drain electrode layer diffuses into a channel. The first oxide semiconductor layer functions as a buffer layer to prevent the formation of a gate insulating film. a second oxide semiconductor layer functioning as a channel and a gate insulating layer; 631, in order to prevent deterioration of the interface of the channel on the gate insulating layer 631 side. and a third oxide semiconductor layer functioning as a buffer layer. The transistor 640 is designed to reduce the influence of the interface state that may be formed on the back channel side. The transistors are highly reliable with reduced light degradation (e.g., negative bias light degradation). It's Jista.

[0230] The insulating layer 632, the interlayer insulating layer 633, and the interlayer insulating layer 634 are made of insulating materials. Depending on the material, sputtering, plasma CVD, spin coating, dipping, and sputtering are used. Using laser coating, droplet ejection method (inkjet method), screen printing, offset printing, etc. It can be formed by

[0231] The interlayer insulating layers 633 and 634 function as planarizing insulating layers to reduce surface irregularities. The interlayer insulating layers 633 and 634 are preferably made of, for example, polyimide or acrylic. Heat-resistant organic resins such as resins, benzocyclobutene-based resins, polyamides, and epoxy resins In addition to the organic insulating materials, low-dielectric-constant materials (low- k material), siloxane resin, PSG (phosphor glass), BPSG (borophosphor glass), etc. A single layer or a laminated layer can be used.

[0232] By detecting the light incident on the photodiode 602, information on the detected object is read. It is possible to read the information of the detected object using a light source such as a backlight. It is possible.

[0233] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0234] (Embodiment 5) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). As electronic equipment, television equipment (also known as television or television receiver) (hereinafter referred to as "computer monitors"), digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, sound players, gaming machines (Pachinko machines, slot machines, etc.) and game cabinets. An example is shown in Figure 8.

[0235] FIG. 8A shows a table 9000 having a display unit. A display unit 9003 is built into the body 9001, and images are displayed on the display unit 9003. It is possible to support the housing 9001 with four legs 9002. The housing 9001 also has a power cord 9005 for power supply.

[0236] The semiconductor device described in any of the above embodiments can be used for the display portion 9003. This makes it possible to provide high reliability to electronic devices.

[0237] The display unit 9003 has a touch input function, and the display unit 9003 of the table 9000 By touching the displayed display button 9004 with a finger or the like, the screen can be operated or information can be input. It can also communicate with other home appliances or control them, making it possible to It may also be a control device that controls other home appliances by operation. If a semiconductor device having an image sensor function as shown in FIG. 3 is used, the display portion 9003 can be touched. It can have input functionality.

[0238] In addition, the screen of the display unit 9003 can be vertically fixed to the floor by a hinge provided in the housing 9001. It can also be set upright and used as a television set. If you install a large screen television, the free space will be narrow, but it is possible to install it on a table. If the display unit is built in, the space in the room can be used more effectively.

[0239] 8B shows a television device 9100. The television device 9100 includes: A display unit 9103 is incorporated in the housing 9101, and images are displayed on the display unit 9103. In this example, the housing 9101 is supported by a stand 9105. This shows the progress.

[0240] The television device 9100 can be operated using an operation switch provided on the housing 9101 or a separate remote control. This can be done by the remote control operation device 9110. The channel and volume can be controlled by the 9109, and the information displayed on the display 9103 is In addition, the remote control unit 9110 can be used to operate the video. A display unit 9107 for displaying information output from 9110 may be provided.

[0241] The television device 9100 shown in FIG. 8(B) includes a receiver, a modem, and the like. The vision device 9100 can receive general television broadcasts using a receiver, and By connecting to a wired or wireless communication network via a modem, Information from sender to receiver) or two-way (between sender and receiver, or between receivers) It is also possible to carry out communication.

[0242] The semiconductor device described in any of the above embodiments can be used for the display portions 9103 and 9107. This makes it possible to provide high reliability to the television set and the remote control. Cut.

[0243] FIG. 8C shows a computer, which includes a main body 9201, a housing 9202, a display unit 9203, and a keyboard. It includes a board 9204, an external connection port 9205, a pointing device 9206, and the like.

[0244] The semiconductor device described in any of the above embodiments can be used for the display portion 9203. This makes it possible to give computers high reliability.

[0245] Figures 9(A) and 9(B) show tablet terminals that can be folded in half. The tablet terminal is in a state where the display unit 9631a is in a housing 9630. 1b, display mode switch 9034, power switch 9035, power saving mode switch It has a replacement switch 9036, a fastener 9033, and an operating switch 9038.

[0246] The semiconductor device described in any of the above embodiments has a display portion 9631a and a display portion 9631b. It is possible to use it as a tablet terminal with high reliability.

[0247] A part of the display unit 9631a can be used as a touch panel area 9632a. By touching the operation keys 9638, data can be input. In 1a, for example, half of the area has a display function only, and the other half The display unit 963 has a touch panel function, but is not limited to this. The entire area of ​​the display unit 96 may have a touch panel function. The entire surface of 31a is displayed as a keyboard button to serve as a touch panel, and the display part 9631b is displayed. It can be used as a screen.

[0248] In addition, in the display unit 9631b, as in the display unit 9631a, a part of the display unit 9631b The area 9632b of the touch panel can be used as the keyboard of the touch panel. By touching the area where the display switch button 9639 is displayed with your finger or a stylus, A keyboard can be displayed on the display portion 9631b.

[0249] In addition, touch panel area 9632a and touch panel area 9632b can be touched simultaneously. You can also input characters using the touchpad.

[0250] A display mode changeover switch 9034 is used to change the display orientation between portrait and landscape. You can select between black and white and color display. The 9036 is a tablet device that detects external light during use using a built-in light sensor. The display brightness can be optimized according to the amount of light. In addition, other detection devices such as gyro, acceleration sensor, etc. that detect tilt are also included. It may be stored.

[0251] FIG. 9A shows an example in which the display area of ​​the display portion 9631b is the same as that of the display portion 9631a. However, there is no particular limitation, and one size may be different from the other size. The quality may also be different. For example, one display panel may be capable of displaying images with higher resolution than the other. You may do so.

[0252] FIG. 9B shows the tablet terminal in a closed state. The tablet terminal includes a housing 9630 and a solar cell 963 3, a charge / discharge control circuit 9634. Note that in FIG. 9B, the charge / discharge control circuit 9634 As an example, a configuration having a battery 9635 and a DC-DC converter 9636 is shown. are.

[0253] In addition, since the tablet device can be folded in half, the housing 9630 can be folded when not in use. Therefore, the display portions 9631a and 9631b can be protected, and thus the display portions 9631a and 9631b can be withstood. This makes it possible to provide a tablet terminal that is highly durable and reliable even from the perspective of long-term use.

[0254] In addition, the tablet terminals shown in Fig. 9(A) and Fig. 9(B) can also display various information ( Functions that display still images, videos, text images, etc., calendars, dates, or times, etc. A function to display information on the display unit, and a touch input device to operate or edit the information displayed on the display unit by touch input. It can have functions such as the ability to control processing by various software (programs), etc. can.

[0255] The solar cell 9633 attached to the surface of the tablet terminal supplies power to the touch panel, The solar cell 9633 can be supplied to a display unit, a video signal processor, or the like. The battery 9635 can be efficiently charged by the battery 9630. The battery 9635 may be a lithium-ion battery. This has the advantage of enabling miniaturization.

[0256] The configuration and operation of the charge / discharge control circuit 9634 shown in FIG. 9B will be described with reference to FIG. 9C. A block diagram is shown and explained. In FIG. 9(C), a solar cell 9633, a battery 9635, DC-DC converter 9636, converter 9637, switches SW1 to SW3, display unit The figure shows the 9631, the battery 9635, the DC-DC converter 9636, 9B. This corresponds to 4.

[0257] First, an example of operation when power is generated by the solar cell 9633 using external light will be described. The power generated by the solar cell is converted to a voltage to charge the Battery 9635. The voltage is increased or decreased by a C converter 9636. When power is being used from the battery 9633, the switch SW1 is turned on and the converter 96 37 increases or decreases the voltage to the voltage required for the display unit 9631. When not displaying in 31, turn SW1 off and SW2 on to charge the battery. 35 charging configuration.

[0258] The solar cell 9633 is shown as an example of a power generating means, but is not particularly limited thereto. Other power generation methods such as piezoelectric elements (piezoelectric elements) and thermoelectric elements (Peltier elements) For example, it may be configured to transmit and receive power wirelessly (contactlessly). A wireless power transmission module that charges by transmitting power, or a configuration that combines other charging methods It may also be possible to use the following.

[0259] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination. [Example]

[0260] In this example, in a transistor in which oxide semiconductor layers are stacked, The measurement results of the concentration of the constituent elements contained in the source electrode layer or the drain electrode layer are shown below. In the semiconductor device, electrode layers containing copper films are formed as source and drain electrode layers, and each oxide semiconductor The copper concentration in the silicon dioxide layer was measured by SIMS (Second-phase ion spectroscopy) from the backside. The measurements were performed by Daily Ion Mass Spectrometry.

[0261] In this example, a method for manufacturing a transistor used in the measurement will be described below. In this case, a transistor having a configuration similar to that of the transistor 300 of the first embodiment is manufactured. In the following description, the same reference numerals as those used for the transistor 300 will be used.

[0262] First, a tungsten film having a thickness of 100 nm is formed on a substrate 400 as a gate electrode layer 402. Successful.

[0263] Next, a gate insulating layer 404 covering the gate electrode layer 402 is formed by plasma CVD. A silicon nitride film with a thickness of 50 nm and a silicon oxynitride film with a thickness of 200 nm were formed successively. did.

[0264] The silicon nitride film was formed by controlling the pressure in the processing chamber of the plasma CVD equipment to 60 Pa. A power of 150 W was supplied from a MHz high frequency power supply, and the substrate temperature was set to 350°C. The film was formed by supplying a nitrogen mixed gas (SiH4:N2 = 50sccm:5000sccm). The plasma CVD device had an electrode area of ​​6000 cm 2The parallel plate type plasma The silicon oxynitride film was formed in the same processing chamber at a pressure of 1000 K. The pressure was set to 40 Pa, and silane and dinitrogen monoxide were added while maintaining the power of the high frequency power source and the substrate temperature. The film was formed by supplying a mixed gas (SiH4:N2O=20sccm:3000sccm) .

[0265] Next, a metal oxide film of In:Ga:Zn=1:1:1 [atomic ratio] was formed on the gate insulating layer 404. A 10 nm thick oxide semiconductor layer 408 was formed by sputtering using an oxide target. The film formation conditions were an atmosphere of 50% oxygen, a pressure of 0.6 Pa, a power supply of 5 kW, and a substrate temperature of 1000°C. The plate temperature was set to 170°C.

[0266] Then, a gold film having an atomic ratio of In:Ga:Zn=3:1:2 was formed on the oxide semiconductor layer 408b. A 30 nm thick oxide semiconductor layer 4 was deposited by sputtering using a metal oxide target. The film formation conditions were an atmosphere of 50% oxygen, a pressure of 0.6 Pa, and a power supply of 5 kW. The substrate temperature was set to 170°C.

[0267] After being processed into an island-shaped oxide semiconductor stack 408, the oxide semiconductor stack 408 is After heat treatment at 0°C for 1 hour, heat treatment at 450°C for 1 hour in a nitrogen and oxygen atmosphere was performed. The theory was carried out.

[0268] Next, the source electrode layer 410a and the drain electrode layer 410b in contact with the oxide semiconductor stack 408 are 0b was formed.

[0269] In this example, a 35-nm-thick film was formed on the gate insulating layer 404 and the oxide semiconductor stack 408. A titanium film and a copper film with a thickness of 200 nm are laminated, and parts of the titanium film and copper film are selectively etched. By this process, a source electrode layer 410a and a drain electrode layer 410b were formed.

[0270] Then, the oxide semiconductor stack 408, the source electrode layer 410a, and the drain electrode layer 410b are As the insulating layer 412, a silicon oxynitride film having a thickness of 400 nm is formed by plasma CVD. Therefore, a film was formed.

[0271] The conditions for forming the silicon oxynitride film were as follows: the pressure in the processing chamber of the plasma CVD device was controlled to 200 Pa; The substrate temperature was controlled by supplying 1500W of power from a 27.12MHz high frequency power supply. The temperature was set at ℃, and a mixture gas of silane and nitrous oxide (SiH4:N2O=160sccm:40 00 sccm) was supplied.

[0272] After heat treatment at 300°C for 1 hour in a nitrogen and oxygen atmosphere, After that, it was heated at 250°C for 1 hour in a nitrogen atmosphere. Heat treatment was carried out.

[0273] In this manner, the transistor of this example was fabricated.

[0274] The copper concentration of the oxide semiconductor stack 408 included in the fabricated transistor was measured from the back surface (here, The measurement was performed by SIMS (from the substrate 400 side). The SIMS measurement results are shown in FIG. The measurement was performed in the region between the source electrode layer 410a and the drain electrode layer 410b (channel The study was carried out on the region where the ion beam is formed.

[0275] 12, the source electrode layer 410a and the drain electrode layer 410b are formed in the oxide semiconductor stack 408. Although diffusion of copper, which is a constituent element of the oxide semiconductor layer 40 b, is observed, the diffusion of copper is not observed. The oxide semiconductor that remains within 8a and functions as the current path (channel) of the transistor. It was confirmed that the electrons did not reach the conductor layer 408b.

[0276] As described above, in the oxide semiconductor stack 408, the oxide semiconductor layer 408b, which serves as a current path, By providing the oxide semiconductor layer 408a on the back channel side, In order to suppress the diffusion of constituent elements of the source electrode layer 410a and the drain electrode layer 410b, It was shown that the oxide semiconductor layer can function as a buffer layer. It is suggested that it is possible to suppress the fluctuation of the electrical characteristics of a transistor including the layer 408. can be. [Explanation of symbols]

[0277] 300 transistors 310 Transistor 320 transistors 330 Transistor 400 boards 402 gate electrode layer 403 Gate insulating layer 403a Gate insulating layer 403b Gate insulating layer 403c Gate insulating layer 404 Gate insulating layer 406 Gate insulating layer 408 Oxide Semiconductor Stack 408a Oxide semiconductor layer 408b Oxide semiconductor layer 408c Oxide semiconductor layer 410a Source electrode layer 410b drain electrode layer 412 Insulating layer 491 Common potential line 492 Common electrode 500 boards 502 Gate insulating layer 502a Gate insulating layer 502b Gate insulating layer 502c Gate insulating layer 504 Interlayer insulation layer 505 Color filter layer 506 Insulation Layer 507 Bulkhead 510 Transistor 511a gate electrode layer 511b gate electrode layer 512 Oxide semiconductor stack 512a Oxide semiconductor layer 512b Oxide semiconductor layer 513a conductive layer 513b Conductive layer 520 Capacitive element 521a conductive layer 521b Conductive layer 522 Oxide semiconductor stack 522a Oxide semiconductor layer 522b Oxide semiconductor layer 523 Conductive Layer 525 Insulation Layer 530 Wiring layer intersection 533 Conductive Layer 540 Light-emitting element 541 Electrode layer 542 Electroluminescent layer 543 Electrode layer 601 Substrate 602 Photodiode 606a Semiconductor film 606b Semiconductor film 606c Semiconductor film 608 Adhesive layer 613 Substrate 631 Gate insulating layer 632 Insulating layer 633 Interlayer insulation layer 634 Interlayer insulation layer 640 transistors 641a Electrode layer 641b Electrode layer 642 Electrode layer 643 Conductive Layer 645 Conductive Layer 656 Transistor 658 Photodiode reset signal line 659 Gate signal line 671 Photo sensor output signal line 672 Photo sensor reference signal line 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 transistor 4011 transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive layer 4020 Gate insulating layer 4031 Electrode layer 4032 Insulation layer 4033 Insulation layer 4034 Electrode layer 4035 Spacer 4038 Insulation layer 9000 tables 9001 Case 9002 Legs 9003 Display section 9004 Display button 9005 Power Cord 9033 Fasteners 9034 Switch 9035 Power Switch 9036 Switch 9038 Operation switch 9100 Television equipment 9101 Housing 9103 Display section 9105 Stand 9107 Display section 9109 Operation key 9110 Remote control device 9201 Main Unit 9202 Housing 9203 Display section 9204 keyboard 9205 External connection port 9206 Pointing Device 9630 chassis 9631 Display section 9631a Display section 9631b Display section 9632a area 9632b area 9633 Solar Cells 9634 Charge / Discharge Control Circuit 9635 Battery 9636 DC / DC Converter 9637 Converter 9638 Operation key 9639 Button

Claims

1. having a plurality of pixels, a display device, wherein at least one of the plurality of pixels includes a transistor and a display element electrically connected to the transistor; a first conductive layer that functions as a gate electrode of the transistor; a first insulating layer having a region located above the first conductive layer, the first insulating layer comprising nitrogen and silicon; a second insulating layer having a region located above the first insulating layer and comprising oxygen and silicon; a first oxide semiconductor layer having a region located above the second insulating layer; a second oxide semiconductor layer having a region located above the first oxide semiconductor layer; a second conductive layer having a region in contact with a top surface of the second oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the transistor; the first oxide semiconductor layer contains at least indium and gallium, the second oxide semiconductor layer contains at least indium and gallium, an atomic ratio of gallium in the second oxide semiconductor layer is equal to or greater than an atomic ratio of indium in the second oxide semiconductor layer; an atomic ratio of gallium to indium in the second oxide semiconductor layer is greater than an atomic ratio of gallium to indium in the first oxide semiconductor layer; The display device, wherein the second oxide semiconductor layer has a crystal part oriented in a c-axis direction.

2. having a plurality of pixels, a display device, wherein at least one of the plurality of pixels includes a transistor and a display element electrically connected to the transistor; a first conductive layer that functions as a gate electrode of the transistor; a first insulating layer having a region located above the first conductive layer, the first insulating layer comprising nitrogen and silicon; a second insulating layer having a region located above the first insulating layer and comprising oxygen and silicon; a first oxide semiconductor layer having a region located above the second insulating layer; a second oxide semiconductor layer having a region located above the first oxide semiconductor layer; a second conductive layer having a region in contact with a top surface of the second oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the transistor; the first oxide semiconductor layer contains at least indium, gallium, and zinc; the second oxide semiconductor layer contains at least indium, gallium, and zinc; an atomic ratio of gallium in the second oxide semiconductor layer is equal to or greater than an atomic ratio of indium in the second oxide semiconductor layer; an atomic ratio of gallium to indium in the second oxide semiconductor layer is greater than an atomic ratio of gallium to indium in the first oxide semiconductor layer; The display device, wherein the second oxide semiconductor layer has a crystal part oriented in a c-axis direction.

Images