Semiconductor device

Abstract

To provide a technique for suppressing deterioration of electrical characteristics of a semiconductor device.SOLUTION: The device 1 has a lower repetitive layer 13A and an upper repetitive layer 13B. At least one of the second conductivity type column lower portion 15A and the second conductivity type column upper portion 15B includes a central portion 4248 and an end portion 4446 provided between the central portion and a boundary surface between the lower-side repetitive layer and the upper-side repetitive layer. Widths Lpa2, Lpb2 of the end portions at the boundary surface measured along the repetition direction are smaller than widths Lpa1, Lpb1 of the central portion measured along the repetition direction.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.

[0002] Semiconductor devices may have a repeating layer in which n-type columns and p-type columns are alternately arranged in a semiconductor substrate. Such a repeating layer is needed for various reasons. For example, a repeating layer called a super junction layer (hereinafter referred to as an "SJ layer") has been developed to achieve both low on-resistance and high breakdown voltage in semiconductor devices. Patent Document 1 discloses an example of a semiconductor device having an SJ layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Re-tabled publication No. 2020 / 110514 Summary of the Invention [Problem to be solved by the invention]

[0004] It is sometimes desirable to increase the thickness of such a repeat layer. For example, when the repeat layer is an SJ layer, increasing the thickness of the SJ layer can further improve the trade-off relationship between lower on-resistance and higher breakdown voltage of the semiconductor device. However, a thick repeat layer increases the aspect ratio of the n-type columns and p-type columns, making it difficult to fabricate the entire repeat layer in one go. Therefore, a manufacturing method has been proposed in which the entire repeat layer is formed through multiple stacking processes.

[0005] However, if misalignment occurs between the lower repeating layer and the upper repeating layer when they are stacked, a narrowed portion may be formed between the columns at the interface between the lower repeating layer and the upper repeating layer, which may deteriorate the electrical characteristics of the semiconductor device. This specification provides a technique for suppressing deterioration of the electrical characteristics of the semiconductor device. [Means for solving the problem]

[0006] This specification discloses a method for manufacturing a semiconductor device (1) having a repeating layer (13) in which first conductivity type columns (14) and second conductivity type columns (15) are alternately arranged along at least one repeating direction when viewed in plan on a semiconductor substrate (10). This manufacturing method can include the step of forming the repeating layer. The step of forming the repeating layer may include the steps of: forming a lower repeating layer (13A) in which first-conductivity-type column lower portions (14A) and second-conductivity-type column lower portions (15A) are alternately repeated along the repeating direction by replacing a portion of a first-conductivity-type lower epitaxial layer (114A) with a second-conductivity-type region; and forming an upper repeating layer (13B) on the lower repeating layer, in which first-conductivity-type column upper portions (14B) and second-conductivity-type column upper portions (15B) are alternately repeated along the repeating direction by replacing a portion of a first-conductivity-type upper epitaxial layer (114B) with a second-conductivity-type region. At least one of the second-conductivity-type column lower portions and second-conductivity-type column upper portions may include a central portion (42, 48) and end portions (44, 46) provided between the central portion and an interface between the lower repeating layer and the upper repeating layer. The widths (Lpa2, Lpb2) of the end portions of the boundary surface measured along the repeating direction are smaller than the widths (Lpa1, Lpb1) of the central portions measured along the repeating direction. The type of the semiconductor device is not particularly limited, and may be, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor).

[0007] By implementing the above manufacturing method, a semiconductor device is manufactured in which the width of the end portion of at least one of the lower portion of the second-conductivity-type column and the upper portion of the second-conductivity-type column is narrowed. In other words, a semiconductor device is manufactured in which the lower portion of the first-conductivity-type column and the upper portion of the first-conductivity-type column can be connected over a wide area at the boundary between the lower repeating layer and the upper repeating layer. Therefore, even if misalignment occurs when the upper repeating layer is stacked on the lower repeating layer, the lower portion of the first-conductivity-type column and the upper portion of the first-conductivity-type column can be well connected at the boundary. Therefore, deterioration of the electrical characteristics of a semiconductor device manufactured by the above manufacturing method is suppressed.

[0008] The semiconductor device (1) disclosed in this specification includes a repeating layer (13) in which, when viewed from above on a semiconductor substrate (10), first-conductivity-type columns (14) and second-conductivity-type columns (15) are alternately arranged in at least one repeating direction. The repeating layer may include a lower repeating layer (13A) in which lower portions (14A) of the first-conductivity-type columns and lower portions (15A) of the second-conductivity-type columns are alternately repeated in the repeating direction, and an upper repeating layer (13B) in which upper portions (14B) of the first-conductivity-type columns and upper portions (15B) of the second-conductivity-type columns are alternately repeated in the repeating direction. At least one of the lower portions (14A) of the second-conductivity-type columns and the upper portions (15B) of the second-conductivity-type columns may include a central portion (42, 48) and end portions (44, 46) provided between the central portion and an interface between the lower repeating layer and the upper repeating layer. The width (Lpa2, Lpb2) of the end portion at the boundary surface measured along the repeat direction is smaller than the width (Lpa1, Lpb1) of the central portion measured along the repeat direction.

[0009] In the semiconductor device, the width of the end portion of at least one of the lower portion of the second conductivity type column and the upper portion of the second conductivity type column is narrowed. In other words, in the semiconductor device, the lower portion of the first conductivity type column and the upper portion of the first conductivity type column can be connected over a wide area at the boundary surface between the lower repeating layer and the upper repeating layer. Therefore, even if misalignment occurs when the upper repeating layer is stacked on the lower repeating layer, the lower portion of the first conductivity type column and the upper portion of the first conductivity type column are well connected at the boundary surface. Therefore, the semiconductor device has a structure that suppresses deterioration of electrical characteristics. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic cross-sectional perspective view of a semiconductor device according to an embodiment of the present invention; [Figure 2] 2 is a schematic enlarged cross-sectional view of a main part of a repeating layer included in the semiconductor device of the present embodiment. [Figure 3] 3 is an enlarged cross-sectional view of a main part of a repeating layer included in the semiconductor device of the present embodiment, and is a schematic enlarged cross-sectional view of a main part taken along line III-III in FIG. 2. [Figure 4] 3 is an enlarged cross-sectional view of a main part of a repeating layer included in a modified example of the semiconductor device of the present embodiment, and is a schematic enlarged cross-sectional view of a main part taken along line III-III in FIG. 2. [Figure 5] FIG. 1 is a schematic enlarged cross-sectional view of a main portion of a repeat layer included in a conventional semiconductor device, illustrating how a current path is narrowed when misalignment occurs between a lower repeat layer and an upper repeat layer. [Figure 6] This is a schematic enlarged cross-sectional view of a main part of the repeat layer provided in the semiconductor device of this embodiment, and explains how a current path is secured when a positional misalignment occurs between the lower repeat layer and the upper repeat layer. [Figure 7] 10 is a schematic enlarged cross-sectional view of a main part of a repeating layer included in a modified example of the semiconductor device of the present embodiment. [Figure 8]10 is a schematic enlarged cross-sectional view of a main part of a repeating layer included in a modified example of the semiconductor device of the present embodiment. [Figure 9] 10 is a schematic enlarged cross-sectional view of a main part of a repeating layer included in a modified example of the semiconductor device of the present embodiment. [Figure 10] 10 is a schematic enlarged cross-sectional view of a main part of a repeating layer included in a modified example of the semiconductor device of the present embodiment. [Figure 11] 3A to 3C are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during the manufacturing process of the first manufacturing method. [Figure 12] 3A to 3C are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during the manufacturing process of the first manufacturing method. [Figure 13] 3A to 3C are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during the manufacturing process of the first manufacturing method. [Figure 14] 3A to 3C are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during the manufacturing process of the first manufacturing method. [Figure 15] 3A to 3C are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during the manufacturing process of the first manufacturing method. [Figure 16] 3A to 3C are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during the manufacturing process of the first manufacturing method. [Figure 17] 3A to 3C are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during the manufacturing process of the first manufacturing method. [Figure 18] 3A to 3C are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during the manufacturing process of the first manufacturing method. [Figure 19] 3A to 3C are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during the manufacturing process of the first manufacturing method. [Figure 20] 3A to 3C are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during the manufacturing process of the first manufacturing method. [Figure 21]3A to 3C are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during the manufacturing process of the first manufacturing method. [Figure 22] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a second manufacturing method. [Figure 23] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a second manufacturing method. [Figure 24] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a second manufacturing method. [Figure 25] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a second manufacturing method. [Figure 26] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a second manufacturing method. [Figure 27] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a second manufacturing method. [Figure 28] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a second manufacturing method. [Figure 29] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a second manufacturing method. [Figure 30] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a third manufacturing method. [Figure 31] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a third manufacturing method. [Figure 32] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a third manufacturing method. [Figure 33] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a third manufacturing method. [Figure 34] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a third manufacturing method. [Figure 35] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a third manufacturing method. [Figure 36] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a third manufacturing method. [Figure 37] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a third manufacturing method. [Figure 38] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a third manufacturing method. [Figure 39] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a third manufacturing method. [Figure 40] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a third manufacturing method. [Figure 41] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a third manufacturing method. [Figure 42] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a third manufacturing method. [Figure 43] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a third manufacturing method. [Figure 44] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a third manufacturing method. [Figure 45] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a fourth manufacturing method. [Figure 46]10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a fourth manufacturing method. [Figure 47] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a fourth manufacturing method. [Figure 48] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a fourth manufacturing method. [Figure 49] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a fourth manufacturing method. [Figure 50] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a fourth manufacturing method. [Figure 51] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a fourth manufacturing method. [Figure 52] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a fourth manufacturing method. [Figure 53] 10A and 10B are enlarged cross-sectional views schematically illustrating a main part of a repeating layer included in the semiconductor device of the present embodiment during a manufacturing process according to a fourth manufacturing method. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments disclosed in this specification will be described with reference to the drawings. For the purpose of clarity of illustration, reference numerals are only used to denote some of the repeatedly arranged components.

[0012] 1, the semiconductor device 1 is a type of power device known as a MOSFET (metal-oxide-semiconductor field effect transistor) and includes a semiconductor substrate 10. The semiconductor substrate 10 is not particularly limited, but may be made of, for example, silicon carbide (SiC). Alternatively, the semiconductor substrate 10 may be made of other semiconductor materials such as silicon, gallium nitride, or gallium oxide.

[0013] A drain electrode 22 is formed on the lower surface 10a of the semiconductor substrate 10, and a source electrode 24 is formed on the upper surface 10b of the semiconductor substrate 10. In this manner, the semiconductor device 1 is a vertical power device in which current flows in the thickness direction of the semiconductor substrate 10. Here, the thickness direction of the semiconductor substrate 10 is the z direction, one direction parallel to the upper surface 10b of the semiconductor substrate 10 (i.e., one direction perpendicular to the z direction) is the x direction, and the direction perpendicular to the z direction and the x direction is the y direction.

[0014] The semiconductor substrate 10 has a drain region 11, a drift region 12, a repeat layer 13, a body region 16, a source region 17, and a body contact region 18.

[0015] The drain region 11 is disposed at a position exposed on the lower surface 10a of the semiconductor substrate 10 and contains a high concentration of n-type impurities. + The drain region 11 is in ohmic contact with the drain electrode 22.

[0016] The drift region 12 is disposed between the drain region 11 and the repeat layer 13, and separates the drain region 11 from the repeat layer 13. The drift region 12 is an n-type region having a lower concentration of n-type impurities than the drain region 11.

[0017] The repeat layer 13 is disposed between the drift region 12 and the body region 16, separating the drift region 12 from the body region 16. The repeat layer 13 has a plurality of n-type columns 14 and a plurality of p-type columns 15. When viewed from a direction perpendicular to the upper surface 10b of the semiconductor substrate 10 (i.e., the z direction) (hereinafter referred to as "when viewed in a plan view"), the repeat layer 13 is configured such that the n-type columns 14 and the p-type columns 15 are alternately arranged along the repeat direction (the y direction in this example).

[0018] Each of the multiple n-type columns 14 has a lower end in contact with the drift region 12 and an upper end in contact with the body region 16. The n-type columns 14 have a higher n-type impurity concentration than the n-type impurity concentration in the drift region 12. Each of the multiple p-type columns 15 also has a lower end in contact with the drift region 12 and an upper end in contact with the body region 16. The p-type columns 15 have a higher p-type impurity concentration than the p-type impurity concentration in the body region 16. The combination of the multiple n-type columns 14 and the multiple p-type columns 15 is configured so that charges are balanced when the semiconductor device 1 is turned off, and forms an SJ layer.

[0019] The body region 16 is disposed on the repeat layer 13, and separates the repeat layer 13 from the source region 17, and separates the repeat layer 13 from the body contact region 18. The body region 16 is a region where a channel is formed when the semiconductor device 1 is turned on.

[0020] The source region 17 is disposed at a position exposed on the upper surface 10b of the semiconductor substrate 10, and is an n-type impurity containing a high concentration + The source region 17 is in ohmic contact with the source electrode 24.

[0021] The body contact region 18 is disposed at a position exposed on the upper surface 10b of the semiconductor substrate 10, and is a p-type region containing a high concentration of p-type impurities. + The body contact region 18 is in ohmic contact with the source electrode 24.

[0022] The semiconductor device 1 further includes a plurality of trench gates 30. Each of the plurality of trench gates 30 is formed so as to extend from the upper surface 10b of the semiconductor substrate 10 through the source region 17 and the body region 16 to reach the repeat layer 13. When the semiconductor substrate 10 is viewed in plan, each of the plurality of trench gates 30 extends parallel to the repeat direction (i.e., the y direction) of the repeat layer 13.

[0023] Each of the multiple trench gates 30 has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is insulated from the semiconductor substrate 10 by the gate insulating film 34, and is also insulated from the source electrode 24 by an interlayer insulating film. The source region 17 and the body region 16 contact the side surfaces of the trench gate 30. The n-type columns 14 and p-type columns 15 that make up the repeating layer 13 contact the side surfaces and bottom surface of the trench gate 30.

[0024] FIG. 2 shows an enlarged cross-sectional view of a main portion of the repeat layer 13 obtained by cutting along a plane (i.e., the y-z plane) parallel to the repeat direction (i.e., the y direction) and the thickness direction (i.e., the z direction). The repeat layer 13 has a lower repeat layer 13A and an upper repeat layer 13B. As will be described in detail in the manufacturing method below, each of the lower repeat layer 13A and the upper repeat layer 13B is a lamination unit when forming the repeat layer 13. In this example, the repeat layer 13 is formed through two lamination steps. Alternatively, the repeat layer 13 may be formed through three or more lamination steps.

[0025] Each of the multiple n-type columns 14 has an n-type column lower portion 14A corresponding to the lower repeating layer 13A and an n-type column upper portion 14B corresponding to the upper repeating layer 13B. Similarly, each of the multiple p-type columns 15 has a p-type column lower portion 15A corresponding to the lower repeating layer 13A and a p-type column upper portion 15B corresponding to the upper repeating layer 13B. In this manner, the lower repeating layer 13A is configured by alternately arranging the n-type column lower portion 14A and the p-type column lower portion 15A along the repeating direction (i.e., the y direction). Similarly, the upper repeating layer 13B is configured by alternately arranging the n-type column upper portion 14B and the p-type column upper portion 15B along the repeating direction (i.e., the y direction). Note that, when "width" is described below, it refers to the width measured along the repeating direction (i.e., the y direction).

[0026] The p-column lower portion 15A has a central portion 42 and end portions 44. The central portion 42 is a portion located toward the center of the p-column lower portion 15A, and has a width Lpa1 that is generally constant in the thickness direction (i.e., the z direction). More specifically, the central portion 42 is a portion in which a pair of side surfaces facing each other in the repeating direction (i.e., the y direction) are parallel to the thickness direction (i.e., the z direction), and is the portion of the p-column lower portion 15A that includes the maximum width. The end portions 44 are portions located toward the ends of the p-column lower portion 15A, and are provided between the central portion 42 and the boundary surface (indicated by the dashed line) between the lower repeating layer 13A and the upper repeating layer 13B. All of the side surfaces of the end portion 44 facing the repeating direction (i.e., the y direction) are located more inward than the side surfaces of the central portion 42 facing the repeating direction (i.e., the y direction). In this example, the end portions 44 have a shape that tapers from the central portion 42 toward the boundary surface. Therefore, the width Lpa2 of the end portion 44 at the boundary surface is smaller than the width Lpa1 of the central portion 42.

[0027] The p-column upper portion 15B has a central portion 48 and end portions 46. The central portion 48 is a portion located toward the center of the p-column upper portion 15B, and has a width Lpb1 that is generally constant in the thickness direction (i.e., z direction). More specifically, the central portion 48 is a portion in which a pair of side surfaces facing each other in the repeating direction (i.e., y direction) are parallel to each other in the thickness direction (i.e., z direction), and is the portion of the p-column upper portion 15B that has the greatest width. The end portions 46 are portions located toward the ends of the p-column upper portion 15B, and are provided between the central portion 48 and the boundary surface (indicated by the dashed line) between the lower repeating layer 13A and the upper repeating layer 13B. Both side surfaces of the end portions 46 facing the repeating direction (i.e., y direction) are located more inward than the side surfaces of the central portion 48 facing the repeating direction (i.e., y direction). In this example, the end portion 46 has a shape that tapers from the central portion 48 toward the boundary surface. Therefore, the width Lpb2 of the end portion 46 at the boundary surface is smaller than the width Lpb1 of the central portion 48.

[0028] As will be explained in the manufacturing method below, the n-column lower portion 14A is formed as a remaining portion after forming the p-column lower portion 15A, and has a shape corresponding to the shape of the adjacent p-column lower portion 15A. Therefore, in the n-column lower portion 14A, the portion adjacent to the central portion 42 of the p-column lower portion 15A has a constant width Lna1, and the portion adjacent to the end portion 44 of the p-column lower portion 15A has a width that gradually increases toward the boundary surface.

[0029] Similarly, the n-column upper portion 14B has a shape corresponding to the shape of the adjacent p-column upper portion 15B. In the n-column upper portion 14B, the portion adjacent to the central portion 48 of the p-column upper portion 15B has a constant width Lnb1, and the portion adjacent to the end portion 46 of the p-column upper portion 15B has a width that gradually increases toward the boundary surface.

[0030] The width Lna1 of the n-column lower portion 14A and the width Lnb1 of the n-column upper portion 14B are both larger than the widths Lpa2 and Lpb2 of the end portions 44 and 46 of the p-column 15. Furthermore, the width Lna1 of the n-column lower portion 14A and the width Lnb1 of the n-column upper portion 14B are not particularly limited, and may be in the range of 0.1 to 1.0 μm, for example.

[0031] 3 shows an enlarged cross-sectional view of the boundary surface between the lower repeating layer 13A and the upper repeating layer 13B, i.e., a main portion of the repeating layer 13 obtained by cutting along line III-III in FIG. 2. As shown in FIG. 3, the widths Lpa2 and Lpb2 of the end portions 44 and 46 of the p-type columns 15 are both constant along the longitudinal direction of the p-type columns 15 (i.e., the x-direction).

[0032] Alternatively, as shown in FIG. 4 , the widths Lpa2, Lpb2 of the end portions 44, 46 of the p-column 15 may both vary along the longitudinal direction (i.e., the x-direction) of the p-column 15. In other words, the end portions 44, 46 of the p-column 15 may have wide portions dispersed along the longitudinal direction (i.e., the x-direction) of the p-column 15. As shown in this example, the wide portions of the end portions 44, 46 of the p-column 15 may be periodically disposed along the longitudinal direction (i.e., the x-direction) of the p-column 15. Furthermore, the wide portions of the end portions 44, 46 of the p-column 15 may have the same width as the widths Lpa1, Lpb1 of the central portions 42, 48.

[0033] If the end portions 44, 46 of the p-type columns 15 have such wide portions, the lower p-type column portion 15A and the upper p-type column portion 15B can be in contact with each other over a wide area. Therefore, when the built-in diode of the semiconductor device 1 is turned off, hole carriers accumulated in the drift region 12 can be efficiently discharged to the source electrode 24. In this example, the wide portions of the end portions 44, 46 of each of the multiple p-type columns 15 are arranged so that they coincide with the repeating direction (i.e., the y direction). Alternatively, the wide portions of the end portions 44, 46 of each of the multiple p-type columns 15 may be arranged so that they do not coincide with the repeating direction (i.e., the y direction). Furthermore, the wide portions of the end portions 44, 46 of adjacent p-type columns 15 may be connected.

[0034] Next, the operation of the semiconductor device 1 will be described. The semiconductor device 1 is used with a higher potential applied to the drain electrode 22 than to the source electrode 24. When a potential equal to or greater than the gate threshold is applied to the gate electrode 32, a channel is formed in the body region 16 near the gate insulating film 34, connecting the source region 17 and the n-type column 14 via the channel. As a result, electrons flow from the source region 17 to the drain region 11 via the channel, the n-type column 14, and the drift region 12. When the potential of the gate electrode 32 is reduced from a value equal to or greater than the gate threshold to a value less than the gate threshold, the channel disappears and the flow of electrons stops. In this way, the semiconductor device 1 can operate as a switching element.

[0035] The effects of the semiconductor device 1 will be described with reference to Figures 5 and 6. For clarity, reference numerals are omitted in the drawings. Figures 5 and 6 are cross-sectional views corresponding to Figure 2, with Figure 5 showing the repeat layer of a semiconductor device of a comparative example and Figure 6 showing the repeat layer of the semiconductor device of this embodiment. Figures 5 and 6 show the state when misalignment occurs along the repeat direction (i.e., the y direction) when an upper repeat layer is stacked on a lower repeat layer.

[0036] In the comparative example shown in FIG. 5, the widths of the n-type columns and p-type columns that make up the repeating layer 13 are both constant in the thickness direction. In this comparative example, if misalignment occurs, a narrowed portion (shown by the dashed line) is formed at the boundary between the lower and upper portions of the n-type columns. The lower and upper portions of the n-type columns are paths through which current flows when the semiconductor device 1 is turned on. Therefore, if misalignment occurs and a narrowed portion is formed between the lower and upper portions of the n-type columns, the on-resistance of the semiconductor device 1 will increase significantly.

[0037] On the other hand, in the present embodiment shown in FIG. 6 , the lower portion 15A of the p-type column and the upper portion 15B of the p-type column each have narrow end portions 44, 46. In other words, the lower portion of the n-type column and the upper portion of the n-type column each have a wide width at the boundary surface. This allows the lower portion of the n-type column and the upper portion of the n-type column to be connected over a wide area at the boundary surface. Therefore, even if misalignment occurs, no narrow portion is formed between the lower portion 14A of the n-type column and the upper portion 14B of the n-type column at the boundary surface, and the connection between the two is maintained well. As a result, the semiconductor device 1 has a structure that is highly robust against misalignment and suppresses deterioration of electrical characteristics.

[0038] The deterioration of electrical characteristics due to misalignment between the lower repeating layer 13A and the upper repeating layer 13B becomes apparent when the width of the n-type columns 14 is small. For example, when the widths Lna1 and Lnb1 of the n-type columns are less than 1.0 μm, the deterioration of electrical characteristics due to misalignment becomes apparent. Therefore, the technology disclosed in this specification is particularly useful when the widths Lna1 and Lnb1 of the n-type columns are less than 1.0 μm.

[0039] The misalignment between the lower repeating layer 13A and the upper repeating layer 13B is significantly affected by the amount of misalignment of the alignment marks. When silicon carbide is used for the semiconductor substrate 10, it is known that the misalignment of the alignment marks increases due to the influence of the off-angle (e.g., 4 degrees) of the semiconductor substrate when epitaxial growth is performed on the alignment marks. Such misalignment of the alignment marks can occur when the upper repeating layer 13B is formed on the lower repeating layer 13A. Therefore, the technology disclosed in this specification is particularly useful when silicon carbide is used for the semiconductor substrate 10.

[0040] In the above-described embodiment, the p-column lower portion 15A and the p-column upper portion 15B each have narrow end portions 44, 46. Alternatively, either the p-column lower portion 15A or the p-column upper portion 15B may have a narrow end portion. Even in this case, it is possible to suppress deterioration of electrical characteristics when misalignment occurs.

[0041] In the above embodiment, the end portions 44, 46 of the p-column lower portion 15A and the p-column upper portion 15B are tapered toward the boundary surface. The end portions 44, 46 may have various shapes as long as the widths Lpa2, Lpb2 of the end portions 44, 46 at the boundary surface are smaller than the widths Lpa1, Lpb1 of the central portions 42, 48.

[0042] For example, the shape of the pair of side surfaces constituting the end portions 44, 46 does not have to be symmetrical. Furthermore, as shown in FIG. 7, the end portions 44, 46 of the p-column lower portion 15A and the p-column upper portion 15B may each have a shape such that their width is constant along the thickness direction (i.e., the z-direction). Furthermore, as shown in FIG. 8, the end portions 44, 46 of the p-column lower portion 15A and the p-column upper portion 15B may each have a shape that is rounded toward the boundary surface. Furthermore, as shown in FIG. 9, the end portions 44, 46 of the p-column lower portion 15A and the p-column upper portion 15B may each have a shape such that only one side surface is located inside the side surfaces of the central portions 42, 48. In other words, one side surface of the end portions 44, 46 of the p-column lower portion 15A and the p-column upper portion 15B may be flush with the side surface of the central portions 42, 48. 9, the p-column lower portion 15A and the p-column upper portion 15B are configured asymmetrically with respect to the boundary surface. Alternatively, the p-column lower portion 15A and the p-column upper portion 15B may be configured symmetrically with respect to the boundary surface.

[0043] In the above embodiment, no particular mention is made of the p-type impurity concentration of the end portions 44, 46 of the p-column lower portion 15A and the p-column upper portion 15B. As shown in FIG. 10 , the p-type impurity concentration of the end portions 44, 46 of the p-column lower portion 15A and the p-column upper portion 15B may be higher than the p-type impurity concentration of the central portions 42, 48. If the p-type impurity concentration of the end portions 44, 46 of the p-column 15 is higher, an increase in resistance due to the narrow end portions 44, 46 can be suppressed. Therefore, when the built-in diode of the semiconductor device 1 is turned off, hole carriers accumulated in the drift region 12 can be efficiently discharged to the source electrode 24.

[0044] Next, some methods for forming the repeating layers among the methods for manufacturing the semiconductor device 1 will be described.

[0045] (First manufacturing method) The first manufacturing method is a method for forming the repeating layer 13 shown in the cross section of Fig. 2. First, as shown in Fig. 11, an n-type lower epitaxial layer 114A is formed on the drift region 12. Next, a mask film 51 and a photoresist film 52 are formed on the n-type lower epitaxial layer 114A.

[0046] 12, after patterning the photoresist film 52, an opening 53 is formed in the mask film 51 by dry etching. At the bottom of the opening 53, the upper surface of the n-type lower epitaxial layer 114A is exposed.

[0047] 13 and 14, using an ion implantation technique, p-type ions are implanted into the n-type lower epitaxial layer 114A through the openings 53 in the mask film 51. The ion implantation angle is oblique to the upper surface of the n-type lower epitaxial layer 114A.

[0048] Next, as shown in FIG. 15 , p-type ions are implanted into the n-type lower epilayer 114A through the openings 53 in the mask film 51 using an ion implantation technique. The ion implantation angle is perpendicular to the upper surface of the n-type lower epilayer 114A. By performing ion implantation multiple times under different ion implantation conditions, multiple p-type column lower portions 15A are formed in the n-type lower epilayer 114A. Additionally, multiple n-type column lower portions 14A are formed in the remaining portion of the n-type lower epilayer 114A after the multiple p-type column lower portions 15A have been formed. As a result, a lower repeat layer 13A is formed, which includes multiple p-type column lower portions 15A and multiple n-type column lower portions 14A.

[0049] 16, after removing the mask film 51, an n-type upper epitaxial layer 114B is formed on the lower repeat layer 13A by epitaxial growth. As described above, in this step, the amount of misalignment of the alignment marks may increase.

[0050] Next, as shown in FIG. 17, a mask film 54 and a photoresist film 55 are formed on the n-type upper epitaxial layer 114B.

[0051] 18, after patterning the photoresist film 55, an opening 56 is formed in the mask film 54 by using a dry etching technique. However, at this stage, the mask film 54 remains on the bottom of the opening 56.

[0052] 19, the openings 56 in the mask film 54 are enlarged using a wet etching technique so that the top surface of the n-type upper epitaxial layer 114B is exposed at the bottom of the openings 56. Note that, because this step is isotropic etching, the sidewalls defining the bottoms of the openings 56 in the mask film 54 may be formed to be rounded.

[0053] Next, as shown in FIG. 20, the photoresist film 55 is removed.

[0054] Next, as shown in FIG. 21 , ion implantation technology is used to implant p-type ions into the n-type upper epilayer 114B through the openings 56 in the mask film 54. The ion implantation angle is perpendicular to the top surface of the n-type upper epilayer 114B. P-type ions are implanted into the n-type upper epilayer 114B in accordance with the shape of the openings 56 in the mask film 54, forming multiple p-type column upper portions 15B. Furthermore, multiple n-type column upper portions 14B are formed in the remaining portions of the n-type upper epilayer 114B after the multiple p-type column upper portions 15B have been formed. As a result, an upper repeat layer 13B is formed that includes multiple p-type column upper portions 15B and multiple n-type column upper portions 14B. Through these steps, a repeat layer 13 can be formed in which a lower repeat layer 13A and an upper repeat layer 13B are stacked.

[0055] (Second manufacturing method) The second manufacturing method is a method for forming the repeating layer 13 shown in the cross section of Figure 7. The steps up to patterning the mask film on the n-type lower epitaxial layer 114A can be the same as the steps of the first manufacturing method (i.e., Figures 11 and 12). Here, in the second manufacturing method, the mask film patterned on the n-type lower epitaxial layer 114A is designated "61", and its opening is designated "62".

[0056] 22, using an ion implantation technique, p-type ions are implanted into the n-type lower epitaxial layer 114A through the openings 62 in the mask film 61. The ion implantation angle is perpendicular to the upper surface of the n-type lower epitaxial layer 114A.

[0057] Next, as shown in FIG. 23, the side surfaces of the mask film 61 that define the openings 62 are etched using a wet etching technique, thereby enlarging the openings 62 of the mask film 61.

[0058] Next, as shown in FIG. 24 , p-type ions are implanted into the n-type lower epilayer 114A through the openings 62 in the mask film 61 using an ion implantation technique. The ion implantation angle is perpendicular to the upper surface of the n-type lower epilayer 114A. Furthermore, by adjusting the ion implantation energy, p-type ions are selectively implanted into portions of the n-type lower epilayer 114A excluding the upper layer portion. By performing ion implantation multiple times under different ion implantation conditions in this manner, multiple p-type column lower portions 15A are formed in the n-type lower epilayer 114A. Furthermore, multiple n-type column lower portions 14A are formed in the remaining portions of the n-type lower epilayer 114A after the multiple p-type column lower portions 15A have been formed. As a result, a lower repeat layer 13A is formed, which includes multiple p-type column lower portions 15A and multiple n-type column lower portions 14A.

[0059] 25, after removing the mask film 61, an n-type upper epitaxial layer 114B is formed on the lower repeat layer 13A using epitaxial growth technology. As described above, this step may increase the amount of misalignment of the alignment marks. Next, a mask film 63 is formed on the n-type upper epitaxial layer 114B.

[0060] 26, an opening 64 is formed in the mask film 63 by dry etching. At the bottom of the opening 64, the upper surface of the n-type upper epitaxial layer 114B is exposed.

[0061] 27, using an ion implantation technique, p-type ions are implanted into the n-type upper epitaxial layer 114B through the openings 64 in the mask film 63. The ion implantation angle is perpendicular to the top surface of the n-type upper epitaxial layer 114B.

[0062] Next, as shown in FIG. 28, the side surfaces of the mask film 63 that define the openings 64 are etched using a wet etching technique, thereby enlarging the openings 64 of the mask film 63.

[0063] Next, as shown in FIG. 29 , p-type ions are implanted into the n-type upper epilayer 114B through the openings 64 in the mask film 63 using ion implantation technology. The ion implantation angle is perpendicular to the upper surface of the n-type upper epilayer 114B. Furthermore, by adjusting the ion implantation energy, p-type ions are selectively implanted into the n-type upper epilayer 114B excluding the lower layer portion. By performing ion implantation multiple times under different ion implantation conditions, multiple p-type column upper portions 15B are formed in the n-type upper epilayer 114B. Furthermore, multiple n-type column upper portions 14B are formed in the remaining portion of the n-type upper epilayer 114B after the multiple p-type column upper portions 15B have been formed. As a result, an upper repeat layer 13B is formed, which includes multiple p-type column upper portions 15B and multiple n-type column upper portions 14B. Through these steps, a repeat layer 13 can be formed in which a lower repeat layer 13A and an upper repeat layer 13B are stacked.

[0064] (Third manufacturing method) The third manufacturing method is a method for forming the repeating layer 13 shown in the cross section of Fig. 7. First, as shown in Fig. 30, an n-type lower epitaxial layer 114A is formed on the drift region 12. Next, a mask film 71 is formed on the n-type lower epitaxial layer 114A.

[0065] 31, an opening 72 is formed in the mask film 71 by dry etching. At the bottom of the opening 72, the upper surface of the n-type lower epitaxial layer 114A is exposed.

[0066] Next, as shown in FIG. 32, a trench T1 is formed in the n-type lower epitaxial layer 114A using a dry etching technique.

[0067] Next, as shown in FIG. 33, a p-type epitaxial layer 115A is formed using an epitaxial growth technique so as to fill the trench T1.

[0068] Next, as shown in FIG. 34, the p-type epitaxial layer 115A formed on the n-type lower epitaxial layer 114A is removed by polishing to expose the upper surface of the n-type lower epitaxial layer 114A.

[0069] Next, as shown in FIG. 35, a mask film 73 is formed on the n-type lower epitaxial layer 114A and the p-type epitaxial layer 115A.

[0070] 36, an opening 74 is formed in the mask film 73 by dry etching. At the bottom of the opening 74, a part of the upper surface of the p-type epitaxial layer 115A is exposed.

[0071] Next, as shown in FIG. 37 , ion implantation is used to implant n-type ions into the p-type epilayer 115A by counterdoping through the openings 74 in the mask film 73. The ion implantation angle is perpendicular to the upper surface of the p-type epilayer 115A. The ion implantation energy is adjusted to selectively implant n-type ions only into the upper layer portion of the p-type epilayer 115A. By combining epitaxial growth and ion implantation in this manner, multiple p-type column lower portions 15A are formed in the n-type lower epilayer 114A. Furthermore, multiple n-type column lower portions 14A are formed in the remaining portion of the n-type lower epilayer 114A after the multiple p-type column lower portions 15A have been formed. As a result, a lower repeat layer 13A is formed, which includes multiple p-type column lower portions 15A and multiple n-type column lower portions 14A.

[0072] 38, after removing the mask film 73, an n-type upper epitaxial layer 114B is formed on the lower repeat layer 13A using epitaxial growth technology. As described above, this step may increase the amount of misalignment of the alignment marks. Next, a mask film 75 is formed on the n-type upper epitaxial layer 114B.

[0073] 39, an opening 76 is formed in the mask film 75 by dry etching. At the bottom of the opening 76, the upper surface of the n-type upper epitaxial layer 114B is exposed.

[0074] 40, trenches T2 are formed in the n-type upper epitaxial layer 114B using a dry etching technique. The trenches T2 are shallowly formed in the upper portion of the n-type upper epitaxial layer 114B.

[0075] Next, as shown in FIG. 41, the side surfaces of the mask film 75 that define the openings 76 are etched using a wet etching technique, thereby enlarging the openings 76 of the mask film 75.

[0076] 42, the trench T2 formed in the n-type upper epitaxial layer 114B is deepened by dry etching. The trench T2 is deepened while maintaining its tip in a convex shape.

[0077] Next, as shown in FIG. 43, after removing the mask film 75, an epitaxial growth technique is used to form a p-type epitaxial layer 115B so as to fill the trench T2.

[0078] Next, as shown in FIG. 44, a polishing technique is used to remove the p-type epitaxial layer 115B formed on the n-type upper epitaxial layer 114B, exposing the top surface of the n-type upper epitaxial layer 114B. In this way, by combining trench processing and epitaxial growth multiple times, multiple p-type column upper portions 15B are formed in the n-type upper epitaxial layer 114B. Furthermore, multiple n-type column upper portions 14B are formed in the remaining portions of the n-type upper epitaxial layer 114B after the multiple p-type column upper portions 15B have been formed. As a result, an upper repeat layer 13B is formed, which includes multiple p-type column upper portions 15B and multiple n-type column upper portions 14B. Through these steps, a repeat layer 13 can be formed in which a lower repeat layer 13A and an upper repeat layer 13B are stacked.

[0079] (Fourth manufacturing method) The fourth manufacturing method is a method for forming the repeat layer 13 shown in the cross section of Fig. 9. The steps up to performing oblique ion implantation into the n-type lower epitaxial layer 114A can be the same as the steps of the first manufacturing method (i.e., Figs. 11, 12, and 13). Here, in the fourth manufacturing method, the mask film patterned on the n-type lower epitaxial layer 114A is designated "81," and its opening is designated "82."

[0080] Next, as shown in FIG. 45 , p-type ions are implanted into the n-type lower epilayer 114A through the openings 82 in the mask film 81 using an ion implantation technique. The ion implantation angle is perpendicular to the upper surface of the n-type lower epilayer 114A. In this way, by performing ion implantation multiple times under different ion implantation conditions, multiple p-type column lower portions 15A are formed in the n-type lower epilayer 114A. Furthermore, multiple n-type column lower portions 14A are formed in the remaining portion of the n-type lower epilayer 114A after the multiple p-type column lower portions 15A have been formed. As a result, a lower repeat layer 13A is formed that includes multiple p-type column lower portions 15A and multiple n-type column lower portions 14A.

[0081] 46, after removing the mask film 81, an n-type upper epitaxial layer 114B is formed on the lower repeat layer 13A by epitaxial growth. As described above, in this step, the amount of misalignment of the alignment marks may increase.

[0082] Next, as shown in FIG. 47, a mask film 83 and a photoresist film 84 are formed on the n-type upper epitaxial layer 114B.

[0083] 48, after patterning the photoresist film 84, an opening 85 is formed in the mask film 83 by using a dry etching technique. However, at this stage, the mask film 83 remains on the bottom of the opening 85.

[0084] 49, the opening 85 in the mask film 83 is enlarged using a wet etching technique so that the top surface of the n-type upper epitaxial layer 114B is exposed at the bottom of the opening 85. Note that, because this step is isotropic etching, the sidewalls defining the bottom of the opening 85 in the mask film 83 may be formed to be rounded.

[0085] 50, after removing the photoresist film 84, a new photoresist film 86 is formed on the mask film 83, and an opening 87 is formed in the photoresist film 86 by dry etching. The photoresist film 86 with the opening 87 formed therein is processed so as to cover one of a pair of side surfaces of the mask film 83 and expose the other.

[0086] Next, as shown in FIG. 51, a part of the bottom of the mask film 83 protruding into the opening 87 of the photoresist film 86 is removed by dry etching.

[0087] Next, as shown in FIG. 52, the photoresist film 86 is removed.

[0088] Next, as shown in FIG. 53 , ion implantation technology is used to implant p-type ions into the n-type upper epilayer 114B through the openings 85 in the mask film 83. The ion implantation angle is perpendicular to the top surface of the n-type upper epilayer 114B. P-type ions are implanted into the n-type upper epilayer 114B in accordance with the shape of the openings 85 in the mask film 83, forming multiple p-type column upper portions 15B. Furthermore, multiple n-type column upper portions 14B are formed in the remaining portions of the n-type upper epilayer 114B after the multiple p-type column upper portions 15B have been formed. As a result, an upper repeat layer 13B is formed that includes multiple p-type column upper portions 15B and multiple n-type column upper portions 14B. Through these steps, a repeat layer 13 can be formed in which a lower repeat layer 13A and an upper repeat layer 13B are stacked.

[0089] The features of the technology disclosed in this specification are summarized below. Note that the technical elements described below are independent technical elements that exhibit technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

[0090] (Feature 1) A method for manufacturing a semiconductor device having a repeating layer in which first conductivity type columns and second conductivity type columns are alternately and repeatedly arranged along at least one repeating direction when a semiconductor substrate is viewed in plan, comprising: forming the repeating layer, The step of forming the repeating layer includes: forming a lower repeating layer in which lower portions of first conductivity type columns and lower portions of second conductivity type columns are alternately repeated along the repeating direction by replacing a portion of a lower epitaxial layer of a first conductivity type with a region of a second conductivity type; forming an upper repeat layer on the lower repeat layer, in which a part of an upper epitaxial layer of a first conductivity type is replaced with a region of a second conductivity type, thereby forming the upper repeat layer in which upper portions of first conductivity type columns and upper portions of second conductivity type columns are alternately repeated along the repeat direction; at least one of the second conductivity type column lower portion and the second conductivity type column upper portion includes a central portion and an end portion provided between the central portion and an interface between the lower repeat layer and the upper repeat layer; A method for manufacturing a semiconductor device, wherein a width of the end portion of the boundary surface measured along the repeat direction is smaller than a width of the central portion measured along the repeat direction.

[0091] (Feature 2) 2. The method for manufacturing a semiconductor device according to Feature 1, wherein the central portion and the end portions are formed by multiple ion implantations under different manufacturing conditions.

[0092] (Feature 3) 2. The method for manufacturing a semiconductor device according to Feature 1, wherein the central portion and the end portions are formed by a combination of crystal growth and ion implantation.

[0093] (Feature 4) 4. The method for manufacturing a semiconductor device according to any one of features 1 to 3, wherein the width of the first conductivity type columns measured along the repeating direction, which is a width of a portion adjacent to the central portion of the second conductivity type columns, is less than 1.0 μm.

[0094] (Feature 5) 5. The method for manufacturing a semiconductor device according to any one of features 1 to 4, wherein both the lower portion of the second conductivity type column and the upper portion of the second conductivity type column include the central portion and the end portion.

[0095] (Feature 6) The method for manufacturing a semiconductor device according to any one of features 1 to 5, wherein the side surfaces of the end portions facing the repeating direction are all located more inward than the side surfaces of the central portion facing the repeating direction.

[0096] (Feature 7) 7. The method for manufacturing a semiconductor device according to any one of Features 1 to 6, wherein the concentration of the second conductivity type impurity in the edge portion is higher than the concentration of the second conductivity type impurity in the central portion.

[0097] (Feature 8) When the semiconductor substrate is viewed from above, the first conductivity type columns and the second conductivity type columns both extend in a direction perpendicular to the repeating direction, 8. The method for manufacturing a semiconductor device according to any one of features 1 to 7, wherein, when the semiconductor substrate is viewed in a plane, the width of the end portion at the boundary surface measured along the repeating direction varies along a direction perpendicular to the repeating direction.

[0098] (Feature 9) 9. The method for manufacturing a semiconductor device according to any one of Features 1 to 8, wherein the repeating layer is an SJ layer.

[0099] (Feature 10) A semiconductor device, The semiconductor substrate includes a repeating layer in which first conductivity type columns and second conductivity type columns are alternately and repeatedly arranged along at least one repeating direction when viewed from above, The repeating layer is a lower repeating layer in which the first conductivity type column lower portions and the second conductivity type column lower portions are alternately repeated along the repeating direction; an upper repeating layer in which upper portions of first conductivity type columns and upper portions of second conductivity type columns are alternately repeated along the repeating direction; at least one of the second conductivity type column lower portion and the second conductivity type column upper portion includes a central portion and an end portion provided between the central portion and an interface between the lower repeat layer and the upper repeat layer; A semiconductor device, wherein a width of the end portion at the boundary surface measured along the repeat direction is smaller than a width of the central portion measured along the repeat direction.

[0100] (Feature 11) 11. The semiconductor device of claim 10, wherein a width of the first conductivity type columns measured along the repeating direction adjacent to the central portion of the second conductivity type columns is less than 1.0 μm.

[0101] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0102] 1: semiconductor device, 10: semiconductor substrate, 11: drain region, 12: drift region, 13: repeat layer, 13A: lower repeat layer, 13B: upper repeat layer, 14: n-type column, 14A: lower portion of n-type column, 14B: upper portion of n-type column, 15: p-type column, 15A: lower portion of p-type column, 15B: upper portion of p-type column, 16: body region, 17: source region, 18: body contact region, 22: drain electrode, 24: source electrode, 30: trench gate, 32: gate electrode, 34: gate insulating film, 42, 48: central portion, 44, 46: end portions

Claims

1. A method for manufacturing a semiconductor device (1) having a repeating layer (13) in which first conductivity type columns (14) and second conductivity type columns (15) are alternately and repeatedly arranged along at least one repeating direction when a semiconductor substrate (10) is viewed in plan, comprising: forming the repeating layer, The step of forming the repeating layer includes: a step of forming a lower repeating layer (13A) in which first conductivity type column lower portions (14A) and second conductivity type column lower portions (15A) are alternately repeated along the repeating direction by replacing a portion of a first conductivity type lower epitaxial layer (114A) with a second conductivity type region; a step of forming an upper repeat layer (13B) on the lower repeat layer, in which a part of an upper epitaxial layer (114B) of a first conductivity type is replaced with a region of a second conductivity type, thereby forming the upper repeat layer in which first conductivity type column upper portions (14B) and second conductivity type column upper portions (15B) are alternately repeated along the repeat direction, At least one of the second conductivity type column lower portion and the second conductivity type column upper portion includes a central portion (42, 48) and end portions (44, 46) provided between the central portion and an interface between the lower repeat layer and the upper repeat layer, A method for manufacturing a semiconductor device, wherein the width (Lpa2, Lpb2) of the end portion of the boundary surface measured along the repeat direction is smaller than the width (Lpa1, Lpb1) of the central portion measured along the repeat direction.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said central portion and said end portions are formed by multiple ion implantations under different manufacturing conditions.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said central portion and said end portions are formed by a combination of crystal growth and ion implantation.

4. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the width (Lna1, Lnb1) of the first conductivity type columns measured along the repeating direction, which width is adjacent to the central portion of the second conductivity type column, is less than 1.0 μm.

5. 2. The method for manufacturing a semiconductor device according to claim 1, wherein both of said second conductivity type column lower portion and said second conductivity type column upper portion include said central portion and said end portion.

6. 2. The method for manufacturing a semiconductor device according to claim 1, wherein all of the side surfaces of the end portions facing the repeating direction are located more inward than the side surfaces of the central portion facing the repeating direction.

7. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a concentration of said second conductivity type impurity in said end portion is higher than a concentration of said second conductivity type impurity in said central portion.

8. When the semiconductor substrate is viewed from above, the first conductivity type columns and the second conductivity type columns both extend in a direction perpendicular to the repeating direction, 2. The method for manufacturing a semiconductor device according to claim 1, wherein, when the semiconductor substrate is viewed in plan, a width of the end portion at the boundary surface measured along the repeating direction varies along a direction perpendicular to the repeating direction.

9. 9. The method for manufacturing a semiconductor device according to claim 1, wherein the repeating layer is an SJ layer.

10. A semiconductor device (1), The semiconductor substrate (10) includes a repeating layer (13) in which first conductivity type columns (14) and second conductivity type columns (15) are alternately and repeatedly arranged along at least one repeating direction when viewed in plan, The repeating layer is a lower repeating layer (13A) in which first conductivity type column lower portions (14A) and second conductivity type column lower portions (15A) are alternately repeated along the repeating direction; an upper repeating layer (13B) in which first conductivity type column upper portions (14B) and second conductivity type column upper portions (15B) are alternately repeated along the repeating direction; At least one of the second conductivity type column lower portion and the second conductivity type column upper portion includes a central portion (42, 48) and end portions (44, 46) provided between the central portion and an interface between the lower repeat layer and the upper repeat layer, A semiconductor device, wherein a width (Lpa2, Lpb2) of the end portion at the boundary surface measured along the repeat direction is smaller than a width (Lpa1, Lpb1) of the central portion measured along the repeat direction.

11. 11. The semiconductor device according to claim 10, wherein the width (Lna1, Lnb1) of the first conductivity type columns measured along the repeating direction, which width is adjacent to the central portion of the second conductivity type columns, is less than 1.0 μm.

Images