Semiconductor device

Abstract

To provide a planar semiconductor device using an oxide semiconductor.SOLUTION: The transistor 150 includes a gate-electrode side 104a, an insulating film 108 including a film containing hydrogen, an insulating film 101 including an oxide-insulating film, an oxide-semiconductor film 126 including a first region 106 overlapping with the gate-electrode side 104a and a pair of second regions side 107a and side 107b sandwiching the first region, a pair of electrodes side 116a and side 116b, a gate-insulating film 112a, and a gate-electrode 114a. The capacitor 160 includes a lower-electrode side 104b, an inter-electrode insulating film, and an upper-electrode side 114b, the lower electrodes contain the same material as the first conductive film, the inter-electrode insulating film includes an insulating film side 102a containing the same material as the insulating film 108 and an insulating film side 112a containing the same material as the gate insulating film side 112b, the upper electrodes contain the same material as the gate insulating film side 114a, and the insulating film 118 containing hydrogen is provided over the transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film, a manufacturing method of the semiconductor device, a semiconductor device including an oxide semiconductor film ... Related to modules and electronic devices.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to a product, a method, or a manufacturing method. Process, Machine, Manufacture, or Composition of Matter In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, The present invention relates to a device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] A transistor (thin film transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology of constructing thin-film transistors (also called thin-film transistors (TFTs)) is attracting attention. It is widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). Semiconductor materials, such as silicon, are widely known as semiconductor thin films that can be used in transistors. However, oxide semiconductors are attracting attention as another material.

[0005] For example, amorphous oxides containing In, Zn, Ga, Sn, etc. are used as oxide semiconductors. Patent Document 1 discloses a technique for fabricating a transistor using a self-aligned transistor. A technique for producing a star is disclosed in Patent Document 2. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165529 [Patent Document 2] Japanese Patent Application Laid-Open No. 2009-278115 Summary of the Invention [Problem to be solved by the invention]

[0007] As a transistor using an oxide semiconductor film, for example, an inverted staggered type (bottom gate structure) The oxide semiconductor is a planar type (also called a top gate structure) or a planar type (also called a top gate structure). When a transistor using a conductor film is applied to a display device, it is more However, the manufacturing process of the inverted staggered transistor is relatively simple and the manufacturing cost can be reduced. However, as the screen size of display devices increases, High definition image quality of devices (for example, 4k x 2k (horizontal pixel count = 3840 pixels, vertical pixel count = 1000 pixels) Prime number = 2048 pixels) or 8k x 4k (horizontal pixel count = 7680 pixels, vertical pixel count = 7680 pixels) As high-resolution display devices (represented by a 4320 pixel display) advance, inverted staggered transistors In the case of a transistor, there is a parasitic capacitance between the gate electrode and the source electrode and between the gate electrode and the drain electrode. The capacitance increases signal delays and the like, which causes problems such as deterioration of the image quality of the display device. In addition, in the case of an inverted staggered transistor, the transistor Therefore, a planar transistor using an oxide semiconductor film is proposed. For Renner-type transistors, the structure has stable semiconductor characteristics and high reliability. Furthermore, there is a demand for the development of a transistor that can be formed through a simple manufacturing process.

[0008] Furthermore, as the screen size of display devices increases or the image quality of display devices becomes higher, The configuration of the transistor formed in the pixel and the capacitor element connected to the transistor is important. The capacitor element functions as a storage capacitor that stores data written to the pixel. Depending on the configuration of the capacitor element, the data written to the pixel may not be retained, and the image of the display device may not be displayed. There was a problem of quality deterioration.

[0009] In view of the above problems, one embodiment of the present invention provides a novel semiconductor device including an oxide semiconductor. In particular, a planar semiconductor device using an oxide semiconductor is provided, or To provide a semiconductor device with a large on-state current using an oxide semiconductor, or to provide a semiconductor device with a large off-state current using an oxide semiconductor To provide a semiconductor device with a small current, or a semiconductor device with a small occupation area using an oxide semiconductor To provide a semiconductor device using an oxide semiconductor and having stable electrical characteristics. or to provide a highly reliable semiconductor device using an oxide semiconductor, or to provide a novel semiconductor One of the objectives is to provide a body device.

[0010] The above description of the problem does not preclude the existence of other problems. The embodiment does not necessarily have to solve all of these problems. Problems other than those mentioned above can be solved by the specification. It is clear from the description of the specification, etc. that the problems other than those mentioned above cannot be extracted from the description of the specification, etc. It is possible to issue it. [Means for solving the problem]

[0011] One embodiment of the present invention includes a transistor and a capacitor. The transistor has a first conductive layer. a first insulating film on the first conductive film, a second insulating film on the first insulating film, and a second insulating film on the second insulating film. an oxide semiconductor film on the insulating film; a pair of electrodes in contact with the oxide semiconductor film; a gate insulating film; and a second conductive film overlapping with the oxide semiconductor film with the gate insulating film interposed therebetween; the first insulating film includes a film containing hydrogen, and the second insulating film includes an oxide insulating film; The oxide semiconductor film includes a first region overlapping with the first conductive film and a pair of second conductive films sandwiching the first region. and a second region, the first region and the second region having different concentrations of impurity elements, The element has a lower electrode, an interelectrode insulating film on the lower electrode, and an upper electrode on the interelectrode insulating film. The lower electrode contains the same material as the first conductive film, and the inter-electrode insulating film contains the same material as the first conductive film. a third insulating film containing the same material as the insulating film; and a gate insulating film containing the same material as the insulating film. a fourth insulating film containing a material, and the upper electrode is made of the same material as the second conductive film. and a fifth insulating film on the transistor, the fifth insulating film including a film containing hydrogen. The semiconductor device is characterized by the above.

[0012] In the above structure, the film containing hydrogen preferably includes a silicon nitride film.

[0013] In the above structure, the oxide insulating film contains more oxygen than the oxygen required for the stoichiometric composition. It is preferable to have a region containing oxygen.

[0014] In the above structure, the second region has a higher concentration of the impurity element than the first region.

[0015] In the above structure, the impurity element is hydrogen, boron, carbon, nitrogen, fluorine, or aluminum. The element has any one selected from the group consisting of nium, silicon, phosphorus, and chlorine.

[0016] In the above configuration, the first region may have a region with a thickness greater than that of the second region. good.

[0017] In another embodiment of the present invention, the first gate electrode and the lower electrode are formed from the same conductive film. Then, a first insulating film is formed on the first gate electrode and the lower electrode, and a second insulating film is formed on the first insulating film. An insulating film is formed, a detachment-inhibiting film is formed on the second insulating film, and the second insulating film is formed through the detachment-inhibiting film. Oxygen is added to the film, the detachment suppression film is removed, and the area where the second insulating film and the lower electrode overlap each other is removed. The first insulating film is exposed by processing, an oxide semiconductor film is formed on the second insulating film, and the oxide semiconductor A third insulating film is formed on the conductor film, the first insulating film, and the second insulating film; A first conductive film is formed on the first gate electrode and the upper electrode is formed by processing the first conductive film. The third insulating film is processed to form a gate insulating film and a fourth insulating film, and the second gate insulating film is formed. Using the electrode as a mask, impurities are added to the oxide semiconductor film to form a first gate electrode overlapping the second gate electrode. a pair of second regions sandwiching the first region; and an oxide semiconductor layer on the second insulating film. A fifth insulating film is formed on the conductive film, the second gate electrode, and the upper electrode. The pair of second regions and the region overlapping with each other are processed to expose the pair of second regions, and a fifth insulating film is formed. a source electrode is formed on the insulating film and on one of the pair of second regions, and a fifth insulating film is formed on the A drain electrode is formed on the other of the pair of second regions, and the fifth insulating film is a film containing hydrogen. the first insulating film and the fourth insulating film function as inter-electrode insulating films. The present invention relates to a method for manufacturing a semiconductor device.

[0018] Another embodiment of the present invention is a semiconductor device including the above-described semiconductor device and a printed circuit board. This is a module that features:

[0019] Another embodiment of the present invention is a semiconductor device including the above semiconductor device or the above module and a spindle. The electronic device is characterized by having a camera, operation keys, or a battery. [Effects of the Invention]

[0020] According to one embodiment of the present invention, a novel semiconductor device including an oxide semiconductor can be provided. In particular, a planar semiconductor device using an oxide semiconductor can be provided. A semiconductor device using an oxide semiconductor and having a large on-state current can be provided. A semiconductor device using an oxide semiconductor and having low off-state current can be provided. A semiconductor device using an oxide semiconductor and having a small area can be provided. It is possible to provide a semiconductor device using a nitride semiconductor and having stable electrical characteristics. A highly reliable semiconductor device using an oxide semiconductor can be provided. A semiconductor device can be provided.

[0021] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other effects from the descriptions in the aspects and claims. [Brief explanation of the drawings]

[0022] [Figure 1] 1A and 1B are cross-sectional views illustrating one embodiment of a semiconductor device. [Figure 2] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 3] 1A and 1B are cross-sectional views illustrating one embodiment of a semiconductor device. [Figure 4] 1A to 1C illustrate a structure of a transistor. [Figure 5] 1A to 1C illustrate a structure of a transistor. [Figure 6] 1A to 1C illustrate a structure of a transistor. [Figure 7] 1A to 1C illustrate a structure of a transistor. [Figure 8] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 10] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 11] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 12] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 13] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 14] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 15] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 16] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 17] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 18] 1A and 1B are a cross-sectional view and a band structure of a transistor that is a semiconductor device according to one embodiment of the present invention. [Figure 19]1A and 1B are cross-sectional views of a semiconductor device. [Figure 20] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 21] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 22] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 23] Electron diffraction pattern of CAAC-OS. [Figure 24] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 25] 1A and 1B illustrate a structure of a pixel portion of a light-emitting device. [Figure 26] FIG. 1 is a top view illustrating one embodiment of a display device. [Figure 27] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 28] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 29] 1A to 1C illustrate a structure of a transistor. [Figure 30] FIG. 1 is a diagram illustrating a calculation model. [Figure 31] FIG. 1 is a diagram illustrating the initial state and the final state. [Figure 32] 1 is a diagram illustrating the activation barrier. [Figure 33] FIG. 1 is a diagram illustrating the initial state and the final state. [Figure 34] 1 is a diagram illustrating the activation barrier. [Figure 35] A diagram explaining VoH transition levels. [Figure 36] 1A and 1B are a top view and a circuit diagram of a display device including a semiconductor device according to one embodiment of the present invention. [Figure 37] 1A and 1B are a circuit diagram and a timing chart of a display device including a semiconductor device according to one embodiment of the present invention. [Figure 38] 1A and 1B are a circuit diagram and a timing chart of a display device including a semiconductor device according to one embodiment of the present invention. [Figure 39]1A and 1B are a circuit diagram and a timing chart of a display device including a semiconductor device according to one embodiment of the present invention. [Figure 40] 1A and 1B are a circuit diagram and a timing chart of a display device including a semiconductor device according to one embodiment of the present invention. [Figure 41] FIG. 2 is a diagram illustrating a display module. [Figure 42] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 43] FIG. 1 is a diagram showing an example of a band structure. [Figure 44] 1A to 1C illustrate electronic devices. [Figure 45] FIG. 10 is a diagram illustrating the temperature dependence of resistivity. [Figure 46] Schematic diagram illustrating a film formation model of CAAC-OS, and cross-sectional views of a pellet and CAAC-OS. [Figure 47] Schematic diagram explaining the film formation model of nc-OS and a diagram showing the pellet. [Figure 48] FIG. [Figure 49] 10A and 10B are diagrams illustrating the force applied to a pellet on a surface to be formed. [Figure 50] 10A and 10B are diagrams illustrating the movement of pellets on a surface to be formed. [Figure 51] A diagram explaining the InGaZnO4 crystal. [Figure 52] A diagram explaining the structure of InGaZnO4 before the atoms collide. [Figure 53] A diagram explaining the structure of InGaZnO4 after the atoms collide. [Figure 54] A diagram explaining the trajectories of atoms after they collide. [Figure 55] Cross-sectional HAADF-STEM images of the CAAC-OS and target. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments will be described with reference to the drawings. It is possible to implement the present invention in various ways without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0024] In the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. are shown in the drawings, and are not limited to the shapes or values ​​shown in the drawings.

[0025] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the number of components. It should be noted that this is added to avoid confusion and is not intended to limit the number.

[0026] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used to indicate the position of components. The positional relationship is used for convenience in describing the structure with reference to the drawings. The relationship between the two components changes depending on the direction in which each component is depicted. The terms are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0027] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to a state in which two lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0028] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0029] In this specification, the terms "film" and "layer" are interchangeable. It is also possible to distinguish between the term "insulator" and the term "insulating film (or insulating layer)." The notation "conductor" and " The terms "conductive film (or conductive layer)" and "conductive layer" can be interchanged. The term "semiconductor" can be used interchangeably with the term "semiconductor film (or semiconductor layer)." It is possible to replace it.

[0030] In this specification, a transistor includes a gate, a drain, and a source. It is an element having at least three terminals including a drain (drain terminal, drain Between the drain electrode and the source terminal The semiconductor device has a channel region therein, and a current flows through the drain, the channel region, and the source. In this specification and the like, the channel region is a region where a current mainly flows. The flow area.

[0031] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. Let's say.

[0032] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "of" is not subject to any particular restrictions as long as it allows the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. It has various functions such as switching elements, resistors, inductors, capacitors, etc. This includes elements such as:

[0033] Note that in this specification, the channel length refers to, for example, The semiconductor (or the part of the semiconductor through which current flows when the transistor is on) and the gate The source (source electrode) is located in the region where the source electrode and the source electrode overlap each other, or in the region where the channel is formed. The distance between the source electrode and the drain electrode. In addition, if the channel length of one transistor is the same in all regions, That is, the channel length of a transistor may not be determined to a single value. Therefore, in this specification, the channel length is defined as the length of any one of the regions where the channel is formed. The value may be any one of the following: maximum, minimum or average value.

[0034] In this specification, the channel width is, for example, the width of a semiconductor (or transistor) when it is in an on-state. The area where the gate electrode overlaps with the semiconductor (the area where current flows in the semiconductor when the This refers to the width of the source or drain in the region where the channel is formed. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of the transistor may not be determined to a single value. In this case, the channel width is any one value, maximum value, or maximum value in the region where the channel is formed. The minimum or average value.

[0035] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width shown in the figure becomes larger, and the effect becomes non-negligible. For example, in a transistor with a fine, three-dimensional structure, the upper surface of the semiconductor The ratio of the channel region formed on the side of the semiconductor to the ratio of the channel region formed on the inside of the semiconductor In this case, the apparent channel width shown in the top view may be The effective channel width where the channel is actually formed is larger than the actual channel width.

[0036] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width if the channel conditions are not precisely known. .

[0037] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are not mutually connected. The apparent length is the length of the part where the source and drain face each other in the overlapping region. The above channel width is called "Surrounded Channel Width (SCW)". In this specification, it is simply referred to as the channel width. In some cases, it may refer to the enclosed channel width or apparent channel width. In this specification, when simply referring to a channel width, it may refer to an effective channel width. The channel length, channel width, effective channel width, apparent channel width, and The width of the interstitial channel can be determined by acquiring a cross-sectional TEM image and analyzing the image. Thus, the value can be determined.

[0038] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0039] (Embodiment 1) In this embodiment mode, one mode of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to drawings. Reveal.

[0040] <Configuration of semiconductor device> FIG. 1 shows a top-gate transistor as an example of a transistor included in a semiconductor device. 1 shows a capacitor that can be manufactured in the same process as a transistor.

[0041] FIG. 1 shows a cross-sectional view of a transistor 150 and a capacitor 160 included in the semiconductor device. 2A and 2B show a top view and a cross-sectional view of the transistor 150. 2(B) is a cross-sectional view taken along the dashed line A1-A2 in FIG. 2(A). 2(C) is a cross-sectional view taken along the dashed line A3-A4 in FIG. 2(A). For clarity, the substrate 100, the insulating film 101, the insulating film 102, and the gate insulating film 112a are shown. , insulating film 108, insulating film 118, insulating film 128, etc. are omitted. In this top view, as in the following figures, one of the components is a transistor 150. In addition, the direction of the dashed dotted line A1-A2 is the channel length direction, The direction of the dotted chain line A3-A4 may be referred to as the channel width direction.

[0042] The transistor 150 includes a gate electrode 104 on an insulating film 101 formed on a substrate 100. a, the insulating film 102 on the gate electrode 104a, the first region 106 on the insulating film 102, and an oxide semiconductor film 126 having a pair of second regions 107a and 107b sandwiching a first region therebetween; The gate insulating film 112a in contact with the oxide semiconductor film 126 and the gate insulating film 112a are the gate electrode 114a, and the insulating film 108 covering the oxide semiconductor film 126 and the gate electrode 114a. and the insulating film 118, and the insulating film 108 and the openings formed in the insulating film 118. A source electrode 116a contacting the region 107a and a drain electrode 116b contacting the second region 107b 116b.

[0043] The capacitor element 160 includes a lower electrode 104b on an insulating film 101 formed on a substrate 100, The insulating film 102a and the insulating film 112b functioning as inter-electrode insulating films on the lower electrode 104b. , and an upper electrode 114b on the insulating film 112b.

[0044] In the oxide semiconductor film 126, a pair of second gate electrodes 114a and 114b are not overlapped with each other. The regions 107a and 107b contain elements that form oxygen vacancies. The elements that cause the impurity are described as impurity elements. Typical examples of impurity elements are hydrogen, boron, These include carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, chlorine, and rare gas elements. Representative examples of gas elements are helium, neon, argon, krypton, and xenon. .

[0045] When an impurity element is added to an oxide semiconductor film, the metal element and oxygen in the oxide semiconductor film are The bond is broken, and oxygen vacancies are formed. Alternatively, an impurity element is added to the oxide semiconductor film. When the oxide semiconductor film is heated, oxygen that has been bonded to a metal element in the oxide semiconductor film is bonded to an impurity element, and the metal element is As a result, oxygen is released from the element, and oxygen vacancies are formed in the oxide semiconductor film. The carrier density increases, resulting in higher conductivity.

[0046] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by adding an impurity element, oxygen Hydrogen enters the vacancy site and a donor level is formed near the conduction band. As a result, the oxide semiconductor The conductivity of the oxide semiconductor increases and it becomes a conductor. The oxide semiconductor that has become a conductor is called an oxide conductor. Generally, oxide semiconductors have a large energy gap, so they are sensitive to visible light. On the other hand, oxide conductors are oxides that have a donor level near the conduction band. Therefore, the influence of absorption due to the donor level is small, and the oxide is not sensitive to visible light. It has the same level of transparency as nitride semiconductors.

[0047] Here, the resistance in a film formed of an oxide conductor (hereinafter referred to as an oxide conductor film) The temperature dependency of resistivity will be explained with reference to the drawings.

[0048] Here, a sample having an oxide conductor film was fabricated. The oxide conductor film (OC_SiN) formed by the semiconductor film contacting the silicon nitride film x ) In the doping device, argon is added to the oxide semiconductor film, and the silicon nitride film is The oxide conductive film (OC_Ar doped + SiN x ), or In the plasma processing device, the oxide semiconductor film is exposed to argon plasma and silicon nitride is The oxide conductive film formed by contacting with the film (OC_Ar plasma + SiN x )of The silicon nitride film contains hydrogen.

[0049] Oxide conductor film (OC_SiN x The method for preparing a sample containing the SiO2 film is as follows: After forming a silicon oxynitride film with a thickness of 400 nm by plasma CVD, By exposing the silicon oxynitride film to plasma and adding oxygen ions to it, oxygen is released by heating. Next, a silicon oxynitride film that releases oxygen when heated was formed. A sputtering target with an atomic ratio of In:Ga:Zn=1:1:1.2 was placed on the silicon film. A 100 nm thick In-Ga-Zn oxide film was formed by sputtering using After heat treatment in a nitrogen atmosphere at 50°C, heat treatment in a mixed gas atmosphere of nitrogen and oxygen at 450°C Next, a silicon nitride film with a thickness of 100 nm was formed by plasma CVD. Then, the substrate was heat-treated at 350°C in a mixed gas atmosphere of nitrogen and oxygen.

[0050] Oxide conductor film (OC_Ar doped + SiN x The method for preparing the sample containing A 400 nm thick silicon oxynitride film was formed on a glass substrate by plasma CVD. After the formation, the silicon oxynitride film is exposed to oxygen plasma to add oxygen ions to the film. A silicon oxynitride film that releases oxygen by heating was formed. On the silicon oxynitride film, a sputtering layer with an atomic ratio of In:Ga:Zn=1:1:1.2 was formed. Using a 100 nm thick In-Ga-Zn oxide film, a 100 nm thick film was deposited by sputtering. After forming a nitride film, it was heat-treated in a nitrogen atmosphere at 450°C, and then heated in a nitrogen and oxygen mixture at 450°C. Next, a doping device was used to dope the In-Ga-Zn oxide film. The film was irradiated with 10 kV of acceleration voltage and 5 × 10 14 / cm 2 of argon was added Next, oxygen vacancies were formed in the In-Ga-Zn oxide film by plasma CVD. Next, a silicon nitride film with a thickness of 0.1 nm was formed. Next, a nitrogen and oxygen mixed gas atmosphere was added at 350°C. It was heat treated.

[0051] Oxide conductor film (OC_Ar plasma + SiN x The sample preparation method including A silicon oxynitride film with a thickness of 400 nm was formed on a glass substrate by plasma CVD. After forming the silicon oxynitride film, it is exposed to oxygen plasma to release oxygen when heated. Next, a silicon oxynitride film with an atomic ratio of I was formed on the silicon oxynitride film, which releases oxygen when heated. Sputtering was performed using a sputtering target of n:Ga:Zn=1:1:1.2 A 100 nm thick In-Ga-Zn oxide film was formed by the method, and then heated in a nitrogen atmosphere at 450°C. After the heat treatment, the plate was heated at 450°C in a mixed gas atmosphere of nitrogen and oxygen. In the Zuma processing device, argon plasma is generated and accelerated argon ions are The oxygen vacancies were created by colliding the Zn-Ga oxide film with the Zn-Ga oxide film. Next, a silicon nitride film with a thickness of 100 nm was formed by annealing in a mixture of nitrogen and oxygen at 350°C. The heat treatment was carried out in a gas atmosphere.

[0052] Next, the resistivity of each sample was measured and the results are shown in Figure 45. Here, the resistivity was measured using a four-terminal In FIG. 45, the horizontal axis indicates the measurement temperature, and the vertical axis indicates the indicates the resistivity. x ) measurement results are indicated by square marks, Oxide conductor film (OC_Ar doped + SiN x The measurement results of oxide conductors are shown by circles. Electrical film (OC_Ar plasma+SiN x ) measurement results are indicated by triangles.

[0053] Although not shown, the oxide semiconductor film that is not in contact with the silicon nitride film has a high resistivity. Therefore, it is considered that the oxide conductor film has a higher resistivity than the oxide semiconductor film. It is clear that it is low.

[0054] As can be seen from FIG. 45, the oxide conductor film (OC_Ar doped+SiN x ) and acid Compound conductor film (OC_Ar plasma+SiN x ) contains oxygen vacancies and hydrogen The resistivity fluctuation is small. Typically, the resistivity fluctuation is small between 80K and 290K. The resistivity fluctuation is less than ±20%. Or, the resistivity fluctuation is less than ±20% between 150K and 250K. The coefficient is less than ±10%. Therefore, it is assumed that the oxide conductor film is By using it as the source and drain regions of a transistor, the oxide conductor film and the source The contact with the conductive film that functions as the electrode and drain electrode is an ohmic contact, and the oxide conductive The contact resistance between the conductive film and the conductive film that functions as the source electrode and the drain electrode can be reduced. In addition, since the resistivity of the oxide conductor has low temperature dependency, the oxide conductor film and the source electrode and drain electrode can be easily The amount of change in contact resistance with the conductive film that functions as the drain electrode is small, resulting in highly reliable transistors. It is possible to create a star.

[0055] The pair of second regions 107a and 107b function as a source region and a drain region. The source electrode 116a and the drain electrode 116b are made of tungsten, titanium, or aluminum. Conductors that easily bond with oxygen, such as copper, molybdenum, chromium, or tantalum alone or in alloys When the oxide semiconductor film is formed using an oxide semiconductor material, oxygen contained in the oxide semiconductor film and the source electrode 116a and The conductive material contained in the drain electrode 116b is bonded to the oxide semiconductor film, and oxygen is In addition, the source electrode 116a and the drain electrode 116 In some cases, some of the constituent elements of the conductive material that forms b may be mixed in. The pair of second regions 107a and 107b in contact with the electrode 116a and the drain electrode 116b are The conductivity increases and they function as source and drain regions.

[0056] The impurity element is a rare gas element, and the oxide semiconductor film 126 is formed by a sputtering method. In this case, the pair of second regions 107a and 107b each contain a rare gas element, and the first The pair of second regions 107a and 107b has a higher concentration of rare gas elements than the region 106. This is because when the oxide semiconductor film 126 is formed by a sputtering method, Since a rare gas element is used as the ring gas, the rare gas is contained in the oxide semiconductor film 126. and in the pair of second regions 107a and 107b, in order to form oxygen vacancies, This is because a rare gas element is intentionally added. The first region 107b may be doped with a different rare gas element than the first region 106.

[0057] The impurity element is boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, or In the case of chlorine, the impurity element is contained only in the pair of second regions 107a and 107b. Therefore, the pair of second regions 107a and 107b have a higher concentration of impurities than the first region 106. In the pair of second regions 107a and 107b, the secondary ion mass Analysis method (SIMS: Secondary Ion Mass Spectrometry) The concentration of impurity elements obtained by 18 atoms / cm 3 More than 1×10 2 2 atoms / cm 3 or less, or 1 x 10 19 atoms / cm 3 More than 1×10 21 a toms / cm 3 or less, or 5 x 10 19 atoms / cm 3 5x10 or more 20 ato ms / cm 3 It can be as follows:

[0058] When the impurity element is hydrogen, the pair of second regions 107a The pair of second regions 107a and 107b has a higher concentration of impurity elements. The hydrogen concentration obtained by secondary ion mass spectrometry is 8×10 19 atoms / cm 3 or more, or 1×10 20 atoms / cm 3 or more, or 5 x 10 20 ato ms / cm 3 It can be more than that.

[0059] The pair of second regions 107a and 107b contains impurity elements, and therefore oxygen vacancies increase. As a result, the pair of second regions 107a and 107b become conductive. This increases the resistance and functions as a low resistance region.

[0060] The impurity elements are hydrogen, boron, carbon, nitrogen, fluorine, aluminum, silicon, It may be a case of one or more of phosphorus or chlorine and one or more of a rare gas. In the second regions 107a and 107b, oxygen vacancies formed by rare gas elements, and Hydrogen, boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus added to the region or chlorine, the pair of second regions 107a, 107b The electrical conductivity may be increased further.

[0061] The first region 106 functions as a channel. An enlarged view is shown in FIG. 3. When the gate electrode 114a is formed, a pair of oxide semiconductor films 126 Since the regions that will become the second regions 107a and 107b are etched, as shown in FIG. The first region 106 has a larger film thickness than the pair of second regions 107a and 107b. Specifically, the first region 106 is 0.1 n thicker than the pair of second regions 107 a and 107 b. It has a region that is larger than m and smaller than 5 nm.

[0062] The transistor 150 described in this embodiment has a first region functioning as a channel formation region. a pair of second regions 107a and 107b functioning as a source region and a drain region; The pair of second regions 107a and 107b have high conductivity, and therefore, The contact resistance between the second region 107a, 107b and the source electrode 116a and the drain electrode 116b is It is possible to reduce the resistance and increase the on-state current of the transistor. .

[0063] In addition, in the transistor 150, an impurity element is introduced using the gate electrode 114a as a mask. In other words, the impurity region (source A source region and a drain region can be formed.

[0064] In addition, the capacitor 160 can be manufactured simultaneously with the manufacturing process of the transistor 150. . The gate electrode 104a of the transistor 150 and the lower electrode 104b of the capacitor element 160 are the same. Also, the gate insulating film 112a of the transistor 150 and the capacitor element 160 The insulating film 112b of the transistor 150 is formed at the same time. The upper electrode 114a and the upper electrode 114b of the capacitor element 160 are formed at the same time.

[0065] The configuration shown in FIG. 1 will be described in detail below.

[0066] The substrate 100 can be made of various substrates and is not limited to a specific one. Examples of the substrate include a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), a SO I substrate, glass substrate, quartz substrate, plastic substrate, metal substrate, stainless steel substrate , Stainless steel foil substrate, Tungsten substrate, Tungsten foil a substrate having a fibrous material, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film Examples of glass substrates include barium borosilicate glass and aluminophore. silicate glass or soda lime glass. Flexible substrate, lamination film Examples of the film and base material are as follows: For example, polyethylene Polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone Plastics such as acrylic are also used. Synthetic resins are also available. Examples include polypropylene, polyester, and polyfluoride. Examples of suitable materials include polyvinyl chloride, polyvinyl chloride, and polyamide. Imide, aramid, epoxy, inorganic vapor deposition film, paper, etc. By manufacturing transistors using substrates, single crystal substrates, or SOI substrates, etc. , small variations in characteristics, size, or shape, high current capability, and small size It is possible to manufacture transistors. Circuits can be constructed using such transistors. This makes it possible to reduce the power consumption of the circuit or to increase the integration density of the circuit.

[0067] In addition, a flexible substrate is used as the substrate 100, and a transistor is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 100 and the transistor. After completing a part or all of the semiconductor device on it, it is separated from the substrate 100 and In this case, the transistor is transferred to a substrate with poor heat resistance or a flexible substrate. It can also be transferred onto a flexible substrate. The above-mentioned release layer may be formed of, for example, a tungsten film and an oxide silicon film. The laminated structure of inorganic film with silicon film, or organic resin film such as polyimide film formed on the substrate The above configuration can be used.

[0068] An example of a substrate on which a transistor is transferred is a substrate on which the above-mentioned transistor is formed. In addition to the substrates that can be used, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, Lum substrate, stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon) , polyurethane, polyester) or regenerated fiber (acetate, cupra, rayon, These substrates include recycled polyester, leather substrates, and rubber substrates. By using this, it is possible to form transistors with good characteristics and low power consumption. It can be used to create devices that are less prone to breakage, heat resistant, lightweight, or thin. .

[0069] The insulating film 101 functions as a base insulating film. The insulating film 101 has a role of preventing diffusion of substances. Sium, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide Thorium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and thorium oxide oxide insulating films such as tantalum, silicon nitride, silicon nitride oxide, aluminum nitride, It can be formed using a nitride insulating film such as aluminum oxide or a mixture of these materials. Alternatively, the material may be a laminate of the above materials.

[0070] The gate electrode 104a is a stack of a conductive film 104a1 and a conductive film 104a2. The lower electrode 104b is a stack of a conductive film 104b1 and a conductive film 104b2. 4a1, the conductive film 104a2, the conductive film 104b1 and the conductive film 104b2 are made of aluminum, Chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, tungsten or an alloy containing the above metal elements, or It can be formed by using a combination of alloys, etc. Also, manganese, zirconium, etc. One or more metal elements selected from the above may be used. The lower electrode 104b may have a single layer structure or a laminated structure of three or more layers. Single layer structure of aluminum film containing silicon, single layer structure of copper film containing manganese, aluminum Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film, Two-layer structure in which a tungsten film is laminated on a titanium nitride film, a tantalum nitride film or a tungsten nitride film Two-layer structure in which a tungsten film is laminated on a manganese film, and a copper film is laminated on a copper film containing manganese Two-layer structure: titanium film, aluminum film on top of titanium film, and titanium film on top of that. A three-layer structure is formed by laminating a copper film on a copper film containing manganese, and then a manganese film is laminated on top of that. There are also three-layer structures that form a copper film containing titanium, tantalum, and A single branch of an element selected from tungsten, molybdenum, chromium, neodymium, and scandium Alternatively, an alloy film in which a plurality of layers are combined, or a nitride film may be used.

[0071] The gate electrode 104a and the lower electrode 104b are made of indium tin oxide and tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing tungsten, indium tin oxide containing titanium oxide, indium zinc oxide Conductive materials with light transmission properties, such as indium tin oxide containing silicon oxide, are used. In addition, a laminate structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element can be used. It is also possible.

[0072] In this embodiment, the conductive film 104a1 and the conductive film 104b1 are made of titanium film, and the conductive film 104 The conductive film 104a2 and the conductive film 104b2 are made of copper. It is preferable to use a low resistance conductive material such as aluminum. By using conductive materials, signal delay can be reduced.

[0073] The insulating film 102 is a stack of an insulating film 102a and an insulating film 102b.

[0074] The insulating film 102a is a blocking material for oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. It is preferable that the film has a blocking effect and contains hydrogen, and silicon nitride oxide, aluminum nitride, etc. The insulating film 102b can be formed of an oxide semiconductor film, an aluminum nitride oxide film, or the like. In order to improve the interface characteristics with 126, it is preferable to form it with an oxide insulating film. It is preferable that the material contains an oxide material that releases a portion of oxygen by heating, and the material satisfies the stoichiometric composition. It is more preferable to use an oxide containing more oxygen than oxygen containing less oxygen. By using the oxide insulating film that releases oxygen by heating as described above, Oxygen contained in the insulating film 102b can be transferred to the oxide semiconductor film 126. .

[0075] The thickness of the insulating film 102b is 50 nm or more, or 100 nm or more and 3000 nm or less, or Alternatively, the thickness of the insulating film 102b can be set to 200 nm or more and 1000 nm or less. As a result, the amount of oxygen released from the insulating film 102b can be increased, and the insulating film 102b and The interface state at the interface with the oxide semiconductor film 126 and the first It is possible to reduce the oxygen vacancies contained in the region 106.

[0076] The insulating film 102b may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, Silicon nitride, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The material may be a single layer or a multilayer.

[0077] The oxide semiconductor film 126 is typically an In—Ga oxide, an In—Zn oxide, or an In— M-Zn oxide (M is Mg, Al, Ti, Ga, Y, Zr, La, Ce, Nd, or The oxide semiconductor film 126 is formed using a metal oxide such as Hf. Note that the oxide semiconductor film 126 has a light-transmitting property.

[0078] In the case where the oxide semiconductor film 126 is an In-M-Zn oxide, I excluding Zn and O The atomic ratio of n and M is 25% when the sum of In and M is 100 atomic %. atomic% or more, M is less than 75 atomic%, or In is 34 atomic% or more Above, M must be less than 66 atomic%.

[0079] The oxide semiconductor film 126 has an energy gap of 2 eV or more, or 2.5 eV or more. Or it is 3 eV or more.

[0080] The thickness of the oxide semiconductor film 126 is greater than or equal to 3 nm and less than or equal to 200 nm, or greater than or equal to 3 nm and less than or equal to 100 nm. The thickness can be 3 nm or less, or 3 nm to 50 nm.

[0081] When the oxide semiconductor film 126 is an In-M-Zn oxide, the In-M-Zn oxide is deposited. The atomic ratio of the metal elements in the sputtering target used for this purpose is In≧M, Zn≧M. It is preferable that the atomic ratio of the metal elements in such a sputtering target and In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn =2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2:1:3, I Preferably, n:M:Zn=3:1:2, etc. The numerical ratios are calculated by taking into account the atomic fraction of the metal elements contained in the sputtering target. This includes a variation of plus or minus 40% in numerical ratios.

[0082] In addition, the oxide semiconductor film 126 contains silicon or carbon, which is one of the Group 14 elements. If the oxide semiconductor film 126 is filled with oxygen, oxygen vacancies increase in the oxide semiconductor film 126, causing the oxide semiconductor film 126 to become n-type. Therefore, the oxide semiconductor film 126, particularly the first region 106, contains silicon and carbon. The concentration of (obtained by secondary ion mass spectrometry) is 2 × 10 18 atoms / cm 3 or less, or 2 x 10 17 atoms / cm 3 As a result, A transistor has an electrical characteristic in which the threshold voltage is positive (also known as a normally-off characteristic). It has.

[0083] In addition, in the oxide semiconductor film 126, especially in the first region 106, secondary ion species The concentration of alkali metals or alkaline earth metals obtained by quantitative analysis is 1 × 10 18 a toms / cm 3 or less, or 2 x 10 16 atoms / cm 3 It can be Alkali metals and alkaline earth metals generate carriers when bonded to oxide semiconductors. This may increase the off-state current of the transistor. It is preferable to reduce the concentration of alkali metals or alkaline earth metals in region 106. As a result, the transistor has normally-off characteristics.

[0084] In addition, when the oxide semiconductor film 126 contains nitrogen, particularly in the first region 106, As a result, electrons acting as carriers are generated, the carrier density increases, and the material becomes n-type. As a result, a transistor using an oxide semiconductor film containing nitrogen has normally-on characteristics. Therefore, in the oxide semiconductor film, particularly in the first region 106, nitrogen is easily For example, the value obtained by secondary ion mass spectrometry is The nitrogen concentration is 5 x 10 18 atoms / cm 3 It can be the following:

[0085] The oxide semiconductor film 126 is formed by reducing impurity elements, particularly in the first region 106. By doing so, the carrier density of the oxide semiconductor film can be reduced. The conductor film 126, particularly in the first region 106, has a carrier density of 1×10 17 pieces / cm 3 or less, or 1 x 1015 pieces / cm 3 or less, or 1 x 10 13 pieces / cm 3 Below Below, or 1×10 11 pieces / cm 3 It can be as follows:

[0086] The oxide semiconductor film 126 is an oxide semiconductor film having a low impurity concentration and a low density of defect states. By using the above, a transistor with better electrical characteristics can be manufactured. Here, a low impurity concentration and a low defect level density (few oxygen vacancies) are referred to as high purity pure silicon. High purity intrinsic or substantially high purity intrinsic oxides In semiconductors, the carrier density can be reduced in some cases because there are few carrier sources. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film In addition, high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors are prone to Since the defect level density of the thin film is low, the trap level density may also be low. A highly intrinsic or substantially highly purified intrinsic oxide semiconductor film has an extremely small off-state current and When the voltage between the source and drain electrodes (drain voltage) is in the range of 1V to 10V, The off-current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10 -13 Below A Therefore, a channel region is formed in the oxide semiconductor film. Such a transistor may have little fluctuation in electrical characteristics and may be a highly reliable transistor. do.

[0087] The oxide semiconductor film 126 may have a non-single-crystal structure, for example. For example, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline, microcrystalline, or amorphous Among non-single crystal structures, the amorphous structure has the highest defect level density, and CAAC- OS has the lowest defect level density.

[0088] Note that the oxide semiconductor film 126 may have an amorphous structure, a microcrystalline structure, or a polycrystalline structure. The film may be a mixed film having two or more of the following: a CAAC-OS region, a CAAC-OS region, and a single crystal structure region. The mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CA In the case of a single-layer structure having two or more regions, either an AC-OS region or a single-crystal structure region The mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, and the like. A structure in which two or more of the following are stacked: a CAAC-OS region, a CAAC-OS region, and a single-crystal structure region. There are cases where this happens.

[0089] Note that in the oxide semiconductor film 126, the pair of second regions 107a and 107b and the first region The crystallinity of the pair of second regions 107a and 106 may be different. When an impurity element is added to the second regions 107a and 107b, damage occurs to the pair of second regions 107a and 107b. This is because the crystallinity decreases due to the inclusion of the crystalline structure.

[0090] In this embodiment, the oxide semiconductor film 126 has a multilayer structure (here, The lower layer has a channel forming region 106a, a low resistance region 107a1, and a low resistance region 107b. a channel forming region 106b, a low resistance region 107a2, and It has a low resistance region 107b2.

[0091] In addition, a channel region is formed in the lower layer of the oxide semiconductor film having a two-layer structure. The upper layer of the oxide semiconductor film is typically an In-Ga oxide, an In-Zn oxide, or an In- Mg oxide, Zn-Mg oxide, In-M-Zn oxide (M is Mg, Al, Ti, Ga , Y, Zr, La, Ce, Nd, or Hf) and have a lower energy level at the bottom of the conduction band than the lower layer. The energy is close to the vacuum level, and typically, the energy of the bottom of the conduction band of the oxide semiconductor film (upper layer) is The difference in energy between the conduction band minimum of the oxide semiconductor film (lower layer) and the conduction band minimum of the oxide semiconductor film (lower layer) is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more and 2 eV or less, 1 eV or more The energy difference between the vacuum level and the bottom of the conduction band is 0.5 eV or less, or 0.4 eV or less. The energy difference is also called electron affinity.

[0092] The oxide semiconductor film (upper layer) is In-M-Zn oxide (M is Mg, Al, Ti, Ga, Y , Zr, La, Ce, Nd, or Hf), in order to form an oxide semiconductor film (upper layer), In the target used for this purpose, the atomic ratio of the metal elements is In:M:Zn=x1:y1:z If we set it to 1, 、 x1 / y1 is 1 / 3 or more and 6 or less, and further 1 or more and 6 or less, and z1 / It is preferable that y1 is 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. When y1 is set to 1 or more and 6 or less, a CAAC-OS film is formed as the oxide semiconductor film (upper layer). A typical example of the atomic ratio of the target metal elements is In:M:Zn. =1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:1.5, I n:M:Zn=2:1:2.3, In:M:Zn=2:1:3, In:M:Zn=3:1 :There are 2nd class.

[0093] The atomic ratios of the oxide semiconductor film (upper layer) and the oxide semiconductor film (lower layer) are each determined by an error. The atomic ratios listed above may vary by ±40%.

[0094] The atomic ratio is not limited to these, and an appropriate atomic ratio may be selected depending on the required semiconductor characteristics. Just use something.

[0095] The gate insulating film 112a and the insulating film 112b are formed of a single layer of an oxide insulating film or a nitride insulating film. Alternatively, the oxide semiconductor film 126 may be formed by stacking the oxide semiconductor film 126. In order to form the oxide semiconductor film 126, at least a region in contact with the oxide semiconductor film 126 is formed using an oxide insulating film. The gate insulating film 112a and the insulating film 112b are preferably made of, for example, silicon oxide. silicon oxide nitride, silicon nitride oxide, silicon nitride, aluminum oxide, The material may be aluminum, gallium oxide, Ga-Zn oxide, or the like, and may be a single layer or a multilayer. It can be established.

[0096] The gate insulating film 112a and the insulating film 112b are formed of a material containing a blocker such as oxygen, hydrogen, or water. By providing an insulating film having a blocking effect, oxygen from the oxide semiconductor film 126 to the outside can be prevented from diffusing. This can prevent hydrogen, water, and the like from entering the oxide semiconductor film 126 from the outside. Examples of insulating films that have a blocking effect against hydrogen, water, etc. include aluminum oxide and aluminum oxynitride. Aluminum, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride Examples include hafnium, hafnium oxide, and hafnium oxynitride.

[0097] The gate insulating film 112a and the insulating film 112b are made of hafnium silicate (Hf Six O y ), nitrogen-doped hafnium silicate (HfSi x O y ), nitrogen added Hafnium aluminate (HfAl x O y ), hafnium oxide, yttrium oxide The use of high-k materials such as these can reduce gate leakage of transistors.

[0098] The gate insulating film 112a and the insulating film 112b are formed by heating the insulating film 112a and the insulating film 112b. Preferably, the oxide material contains more oxygen than the stoichiometric composition. It is more preferable to use an oxide insulating film containing the gate insulating film 112a and the insulating film 112b. By using the oxide insulating film that releases oxygen by heating as described above as b, As a result, oxygen contained in the gate insulating film 112a is transferred to the oxide semiconductor film 126. is possible.

[0099] The gate insulating film 112a and the insulating film 112b are made of silicon oxynitride with few defects. A silicon oxynitride film with few defects can be used after heat treatment. In the spectrum obtained by ESR measurement below 100K, the g value is 2.037 or more. a first signal with a g value of 0.039 or less, a second signal with a g value of 2.001 or more and 2.003 or less, And the spin density of a third signal with a g value of 1.964 or more and 1.966 or less is observed. The split width of the first signal and the second signal, and the split width of the second signal and The split width of the signal 3 is about 5 mT in the X-band ESR measurement. The first signal has a g value of 2.037 or more and 2.039 or less, and the second signal has a g value of 2.001 or more and 2.00 or less. The second signal is 3 or less, and the third signal is between 1.964 and 1.966. The total density of spins is 1×10 18 spins / cm 3 less than 1 × 10 17 spins / cm 3 More than 1×10 18 spins / cm 3 is less than.

[0100] In addition, the g value is between 2.037 and 2.039 in the ESR spectrum below 100K. The first signal has a g value of 2.001 or more and 2.003 or less, and the second signal has a g value of 1 The third signal, between 0.964 and 1.966, is nitrogen oxide (NO x , x is between 0 and 2 This corresponds to a signal caused by a g-value of 2.037 or greater, or 1 or greater but less than 2. a first signal with a g value of 0.039 or less, a second signal with a g value of 2.001 or more and 2.003 or less, The sum of the spin densities of the third signals with g values ​​between 1.964 and 1.966 is small. It can be said that the smaller the content of nitrogen oxides in the silicon oxynitride film, the smaller the content of nitrogen oxides in the silicon oxynitride film.

[0101] In addition, the silicon oxynitride film with few defects has a nitrogen concentration measured by secondary ion mass spectrometry. Degrees are 6 x 10 20 atoms / cm 3 The gate insulating film 112a and the insulating film 1 By using a silicon oxynitride film with few defects as 12b, nitrogen oxides are not generated. This reduces carrier traps at the interface between the oxide semiconductor film 126 and the insulating film. In addition, it is possible to prevent a shift in the threshold voltage of a transistor included in a semiconductor device. Therefore, the variation in the electrical characteristics of the transistor can be reduced.

[0102] The gate electrode 114a is a stack of a conductive film 114a1 and a conductive film 114a2. The upper electrode 114b is a stack of a conductive film 114b1 and a conductive film 114b2. The materials of the conductive film 4a1, the conductive film 114a2, the conductive film 114b1, and the conductive film 114b2 are 104a1, conductive film 104a2, conductive film 104b1, and conductive film 104b2. can be done.

[0103] In this embodiment, the conductive film 114a1 and the conductive film 114b1 are formed of a tantalum nitride film and a conductive film A tungsten film is used for the conductive film 114a2 and the conductive film 114b2.

[0104] As shown in FIG. 1, in the cross section in the channel length direction, the end of the conductive film 114a1 The portion is located outside the end of the conductive film 114a2, and the conductive film 114a1 has a tapered shape. That is, the surface where the gate insulating film 112a and the conductive film 114a1 contact each other and the conductive film 114a1 may be formed as follows. The angle formed by the side surface of the film 114a1 is less than 90°, or 5° to 45°, or 5° or more. The angle between the end of the conductive film 114b1 and the end of the conductive film 114b2 may be 30° or less. The insulating film 114b1 may be positioned further outward and have a tapered shape. The angle formed by the surface where the conductive film 112b and the conductive film 114b1 are in contact with each other and the side surface of the conductive film 114b1 is 90°. The angle may be less than 45°, or may be 5° or more and 45° or less, or may be 5° or more and 30° or less.

[0105] Furthermore, the end of the gate insulating film 112a is located outside the end of the conductive film 114a1. In addition, the end of the insulating film 112b may be positioned outside the end of the conductive film 114b1. Good too.

[0106] Furthermore, the side surfaces of the gate insulating film 112a and the insulating film 112b may be curved.

[0107] Furthermore, the gate insulating film 112a may have a tapered shape. The angle between the surface where the film 126 and the gate insulating film 112a contact and the side surface of the gate insulating film 112a The angle may be less than 90°, preferably 30° or more and less than 90°.

[0108] The insulating film 108 may be made of the same material as the insulating film 102a.

[0109] The insulating film 118 can be made of the same material as the insulating film 102b.

[0110] The source electrode 116a is a stack of a conductive film 116a1 and a conductive film 116a2. The drain electrode 116b is a stack of a conductive film 116b1 and a conductive film 116b2. The materials of the conductive film 116a1, the conductive film 116a2, the conductive film 116b1, and the conductive film 116b2 are conductive. The conductive film 104a1, the conductive film 104a2, the conductive film 104b1, and the conductive film 104b2 are referred to. It is possible.

[0111] In this embodiment, the conductive film 116a1 and the conductive film 116b1 are formed of a tungsten film and a conductive film A copper film is used for the conductive film 116a2 and the conductive film 116b2. It is preferable that 2 is made of a low resistance conductive material such as copper or aluminum. By using a highly conductive material, signal delay can be reduced.

[0112] The insulating film 128 is preferably a film that functions as a barrier film against hydrogen, water, etc. from the outside. The insulating film 128 may be made of, for example, silicon nitride, silicon nitride oxide, or aluminum oxide. The above may be used, and the layer may be formed as a single layer or a laminate.

[0113] Here, modified examples of the transistor will be described with reference to FIGS. 4 to 7 and 29. FIG. The transistor shown in FIG. 4 includes an oxide semiconductor film formed over an insulating film 453 on a substrate 400. an insulating film 455 in contact with the oxide semiconductor film 455; an insulating film 457 in contact with the oxide semiconductor film 455; The insulating film 457 includes a conductive film 459 and a nitride semiconductor film 455 overlapping each other. The conductive film 459 functions as a gate insulating film. The substrate 400 can be the substrate 100. The insulating film 453 is an insulating film. The oxide semiconductor film 126 can be used as the oxide semiconductor film 455. The insulating film 457 can be formed using the gate insulating film 112a. , the gate electrode 114a can be used.

[0114] The nitride insulating film 465 in contact with the oxide semiconductor film 455 and the nitride insulating film 465 The nitride insulating film 465 and the insulating film 467 are provided in contact with each other. In the opening of the insulating film 467, the conductive films 468 and 469 in contact with the oxide semiconductor film 455 are The conductive films 468 and 469 are provided in the transistor. The nitride insulating film 465 functions as a gate electrode. The insulating film 467 can be formed using the insulating film 118. The conductive films 468 and 469 can be formed using the insulating film 118. , a source electrode 116a, and a drain electrode 116b can be used.

[0115] In the transistor illustrated in FIG. 4A, the oxide semiconductor film 455 overlaps with the conductive film 459. and a channel region 455a formed in a region including impurities. The conductive film 46 has regions containing organic elements, i.e., low resistance regions 455b and 455c. The conductive films 468 and 469 are in contact with the low resistance regions 455b and 455c. , and functions as wiring.

[0116] Alternatively, as in the transistor illustrated in FIG. 4B, The regions 455d and 455e in contact with the conductive films 468 and 469 are not doped with impurity elements. In this case, the regions 455d and 455e in contact with the conductive films 468 and 469 and the channel Between the region 455a, there are regions containing impurity elements, i.e., low resistance regions 455b and 455c. Note that the regions 455d and 455e are formed when a voltage is applied to the conductive films 468 and 469. Since the SiO 2 layer has conductivity, it functions as a source region and a drain region.

[0117] Note that in the transistor shown in FIG. 4B, after the conductive films 468 and 469 are formed, An impurity element is added to the oxide semiconductor film using the conductive films 459 and 468 and 469 as masks. It can be formed by

[0118] The conductive film 459 may have a tapered edge. The angle θ1 between the surface where the insulating film 457 and the conductive film 459 contact and the side surface of the conductive film 459 is 90 Less than °, 10° to 85°, or 15° to 85°, or 30° to 85° The angle may be 45° or less, or 45° or more and 85° or less, or 60° or more and 85° or less. θ1 is set to less than 90°, 10° or more and 85° or less, or 15° or more and 85° or less, or 30 45° to 85°, or 45° to 85°, or 60° to 85°. This improves the coverage of the nitride insulating film 465 on the side surfaces of the insulating film 457 and the conductive film 459. It is possible to do this.

[0119] Next, modifications of the low resistance regions 455b and 455c will be described. 4F is an enlarged view of the oxide semiconductor film 455 and its vicinity shown in FIG. The channel length L is the distance between the pair of low resistance regions.

[0120] As shown in FIG. 4C, in the cross section in the channel length direction, the channel region 455a The boundary between the low resistance regions 455b and 455c is connected to the edge of the conductive film 459 via the insulating film 457. That is, in the top view, the channel region 455a and the The boundaries of the low resistance regions 455b and 455c coincide or approximately coincide with the edges of the conductive film 459. are.

[0121] Alternatively, as shown in FIG. 4(D), in the cross section in the channel length direction, The conductive film 455a has a region that does not overlap with the conductive film 459. The region functions as an offset region. The length of the offset region in the channel length direction is L off In addition, offset If there are multiple offset areas, the length of one offset area is L. off That is said. off teeth , included in the channel length L. Also, L off is less than 20% of the channel length L, or 10 %, or less than 5%, or less than 2%.

[0122] Alternatively, as shown in FIG. 4(E), in the cross section in the channel length direction, the low resistance region 4 The insulating film 457 is interposed between the conductive film 459 and the insulating film 457. The overlap region in the channel length direction functions as an overlap region. Length is L ov L ov is less than 20% of the channel length L, or less than 10%, or Less than 5% or less than 2%.

[0123] Alternatively, as shown in FIG. 4(F), in the cross section in the channel length direction, the channel region The low resistance region 455f is located between the channel region 455a and the low resistance region 455b. The low resistance region 455g is located between the low resistance region 455f and the low resistance region 455c. The low-resistivity regions 455g have a lower concentration of impurity elements than the low-resistivity regions 455b and 455c, and have a higher resistivity. In this example, the low resistance regions 455f and 455g overlap the insulating film 457, but the insulating film 457 and the conductive film 455f are not It may overlap with the conductive film 459.

[0124] Note that in FIGS. 4C to 4F, the description of the transistor in FIG. However, the transistor shown in FIG. 4B may also have the structures shown in FIGS. 4C to 4F. It can be applied as appropriate.

[0125] In the transistor illustrated in FIG. 5A, the edge of the insulating film 457 is located outside the edge of the conductive film 459. That is, the insulating film 457 is located on the conductive film 459 side. Since the nitride insulating film 465 can be kept away from the panel region 455a, the nitride insulating film To prevent nitrogen, hydrogen, etc. contained in the film 465 from entering the channel region 455a. can be done.

[0126] In the transistor shown in FIG. 5B, the insulating film 457 and the conductive film 459 have tapered shapes. The angles of the tapered portions are different. The angle θ1 between the contact surface and the side surface of the conductive film 459 and the oxide semiconductor film 455 and the insulating film 4 The angle θ2 formed by the surface with which the insulating film 457 is in contact and the side surface of the insulating film 457 is different. It may be less than 90°, or between 30° and 85°, or between 45° and 70°. For example, if the angle θ2 is greater than the angle θ1, the transistor can be miniaturized.

[0127] Next, regarding modifications of the low resistance regions 455b and 455c, FIGS. 5(C) to 5(F) are shown. 5C to 5F show the oxide semiconductor film shown in FIG. This is an enlarged view of the vicinity of 455.

[0128] As shown in FIG. 5C, in the cross section in the channel length direction, the channel region 455a The boundary between the low-resistance regions 455b and 455c is formed between the end of the conductive film 459 and the insulating film 457. That is, in the top view, the channel region 455a and the The boundaries of the low resistance regions 455b and 455c coincide or almost coincide with the edge of the conductive film 459. is doing.

[0129] Alternatively, as shown in FIG. 5(D), in the cross section in the channel length direction, The conductive film 455a has a region that does not overlap with the conductive film 459. The region functions as an offset region. That is, in the top view, the ends of the low resistance regions 455b and 455c are formed in the insulating film 45 7 and does not overlap with the edge of the conductive film 459.

[0130] Alternatively, as shown in FIG. 5(E), in the cross section in the channel length direction, the low resistance region 4 The insulating film 457 is interposed between the conductive film 459 and the insulating film 457. In other words, in the top view, the low resistance regions 455b and 455 The end of c overlaps with the conductive film 459.

[0131] Alternatively, as shown in FIG. 5(F), in the cross section in the channel length direction, The low resistance region 455f is located between the channel region 455a and the low resistance region 455b. The low resistance region 455g is located between the low resistance region 455f and the low resistance region 455c. The low-resistivity regions 455g have a lower concentration of impurity elements than the low-resistivity regions 455b and 455c, and have a higher resistivity. In this example, the low resistance regions 455f and 455g overlap the insulating film 457, but the insulating film 457 and the conductive film 455f are not It may overlap with the conductive film 459.

[0132] Note that in FIGS. 5C to 5F, the transistor shown in FIG. However, the transistor shown in FIG. 5B may also have the structures shown in FIGS. 5C to 5F. It can be applied as appropriate.

[0133] The transistor shown in FIG. 6A has a stacked structure in which the conductive film 459 is in contact with the insulating film 457. The conductive film 459a is in contact with the conductive film 459a, and the conductive film 459b is in contact with the conductive film 459a. The end of the conductive film 459a is located outside the end of the conductive film 459b. The portion a has a shape that protrudes from the conductive film 459b.

[0134] Next, modifications of the low resistance regions 455b and 455c will be described. 6E, 7A, and 7B show the oxide semiconductor film 455 shown in FIG. FIG.

[0135] As shown in FIG. 6B, in the cross section in the channel length direction, the channel region 455a The boundary between the low resistance regions 455b and 455c is formed by the conductive film 459a included in the conductive film 459. The edge of the insulating film 457 is aligned or substantially aligned with the edge of the insulating film 457. The boundary between the channel region 455a and the low-resistance regions 455b and 455c is the edge of the conductive film 459. It matches or nearly matches.

[0136] Alternatively, as shown in FIG. 6C, in the cross section in the channel length direction, The conductive film 455a has a region that does not overlap with the conductive film 459. The region functions as an offset region. That is, in the top view, the ends of the low resistance regions 455b and 455c are It does not overlap with the end of the 9.

[0137] Alternatively, as shown in FIG. 6(D), in the cross section in the channel length direction, the low resistance region 4 The conductive film 459a in this case is overlapped with the conductive film 459b. The overlapping region is called an overlapping region. The end of 5c overlaps with the conductive film 459a.

[0138] Alternatively, as shown in FIG. 6(E), in the cross section in the channel length direction, the channel region The low resistance region 455f is located between the channel region 455a and the low resistance region 455b. The impurity element is introduced into the conductive film 459. a and added to the low resistance regions 455f and 455g. The region 55g has a lower concentration of impurity elements and a higher resistivity than the low-resistivity regions 455b and 455c. Here, the low resistance regions 455f and 455g overlap the conductive film 459a. The conductive film 459a and the conductive film 459b may overlap with each other.

[0139] Alternatively, as shown in FIG. 7A, the conductive film 459 The end of the conductive film 459a is located outside the end of the conductive film 459b, and the conductive film 459a has a tapered shape. That is, the surface where the insulating film 457 and the conductive film 459a are in contact with each other and the surface where the conductive film 459a is in contact with each other may have a shape similar to that of the insulating film 457. The angle between the sides of a is less than 90°, or 5° to 45°, or 5° to 30° may be.

[0140] Furthermore, the edge of the insulating film 457 may be located outside the edge of the conductive film 459a.

[0141] Furthermore, the side surface of the insulating film 457 may be curved.

[0142] Furthermore, the insulating film 457 may have a tapered shape. The angle between the surface of the insulating film 457 and the side surface of the insulating film 457 is preferably less than 90°. may be greater than or equal to 30° and less than 90°.

[0143] The oxide semiconductor film 455 illustrated in FIG. 7A includes a channel region 455a and a channel region 455b. The low resistance regions 455f and 455g sandwich the channel region 455a and the low resistance region 45 5f, 455g are sandwiched between low resistance regions 455h, 455i, a channel region 455a, and a low resistance The low resistance regions 455f and 455g and the low resistance region 455b sandwiching the low resistance regions 455h and 455i The impurity element passes through the insulating film 457 and the conductive film 459a and is a low-resistance impurity element. Since it is added to the resistance regions 455f, 455g, 455h, and 455i, the low resistance region 455f , 455g, 455h, and 455i have a higher concentration of impurity elements than the low-resistance regions 455b and 455c. It has low viscosity and high resistivity.

[0144] The oxide semiconductor film 455 illustrated in FIG. 7B includes a channel region 455a and a channel region 455b. The low resistance regions 455h and 455i sandwich the channel region 455a and the low resistance region 45 The impurity element is an insulating film. Since it passes through 457 and is added to the low resistance region 455h, 455i, , 455i have a lower concentration of impurity elements than the low resistance regions 455b, 455c, and have a higher resistivity. stomach.

[0145] In the channel length direction in FIG. 7A, the channel region 455a is formed by the conductive film 459b. The low resistance regions 455f and 455g are conductive regions that protrude outside the conductive film 459b. The low resistance regions 455h and 455i overlap the conductive film 459a, and protrude outside the conductive film 459a. The low-resistance regions 455b and 455c are located outside the insulating film 457. It is being released.

[0146] As shown in FIG. 7A, the oxide semiconductor film 455 is formed in a region where the resistance of the oxide semiconductor film 455 is greater than that of the low-resistance regions 455b and 455c. , low-resistivity regions 455f, 455g, 455h, 4 where the concentration of impurity elements is low and the resistivity is high By having 55i, the electric field in the drain region can be relaxed. It is possible to reduce the degradation of the transistor, such as the fluctuation of the threshold voltage, caused by the electric field of the be.

[0147] The transistor shown in FIG. 29A has a channel region 455a, a low-resistance region 455b, The oxide semiconductor film 455 includes the low-resistance regions 455b and 455c. Typically, the low resistance regions 455b and 455c have a thickness smaller than that of the low resistance region 455a. 5c has a region whose thickness is 0.1 nm or more and 5 nm or less smaller than that of the channel region 455a. .

[0148] The transistor in FIG. 29B includes insulating films 453 and 454 in contact with the oxide semiconductor film 455. At least one of the insulating films 453a and 57 has a multilayer structure. The insulating film 453b is in contact with the insulating film 453a and the oxide semiconductor film 455. The insulating film 457 includes an insulating film 457a in contact with the oxide semiconductor film 455 and an insulating film 457b in contact with the insulating film 457a. The insulating film 457b is formed on the insulating film 457a.

[0149] The insulating films 453b and 457a have an energy level at the top of the valence band (E v_ os ) and the energy at the bottom of the conduction band (E c_os ) between the nitrogen oxides and the acid It can be formed using a carbide insulating film. v_os and E c_os Nitrogen oxides during As an oxide insulating film with a low level density, a silicon oxynitride film that emits a small amount of nitrogen oxide, Alternatively, an aluminum oxynitride film or the like that emits less nitrogen oxides can be used. The insulating films 453b and 457a have an average film thickness of 0.1 nm or more and 50 nm or less, or 0.1 nm or more and 50 nm or less. It is between 0.5nm and 10nm.

[0150] The silicon oxynitride film, which emits a small amount of nitrogen oxides, was analyzed by thermal desorption spectroscopy (TD). In Thermal Desorption Spectroscopy (S), This membrane releases more ammonia than nitrogen oxides, and typically releases ammonia. Output is 1 x 10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 The following is the case. The amount of a release of a film is determined when the surface temperature of the film is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. The amount released by the following heat treatment is assumed.

[0151] The insulating films 453a and 457b are formed using an oxide insulating film that releases oxygen by heating. The insulating films 453a and 457b have an average film thickness of 5 nm or more and 1000 nm or less. m or less, or 10 nm to 500 nm.

[0152] Typical examples of oxide insulating films that release oxygen when heated include silicon oxynitride films and oxide Examples include an aluminum nitride film.

[0153] Nitrogen oxides (NO x , x is 0 or more and 2 or less, preferably 1 or more and 2 or less), typically NO 2 or NO forms a level in the insulating film 453, the insulating film 457, etc. The nitride semiconductor film 455 is located within the energy gap of the nitride semiconductor film 455. When the oxide semiconductor film 455 is diffused to the interface between the insulating film 453 and the oxide semiconductor film 457, the level 3, 457 side, electrons may be trapped. As a result, the trapped electrons , and the insulating films 453 and 457 and the oxide semiconductor film 455 remain in the vicinity of the interface. This shifts the threshold voltage in the positive direction.

[0154] Nitrogen oxide reacts with ammonia and oxygen during heat treatment. The nitrogen oxides contained in the insulating films 453b and 457a are deposited on the insulating films 453b and 457a during the heat treatment. The nitrogen oxides contained in the insulating films 453a and 457b react with the ammonia contained therein. Therefore, at the interface between the insulating films 453 and 457 and the oxide semiconductor film 455, , electrons are less likely to be trapped.

[0155] The insulating films 453b and 457a are made of E v_os and E c_os The density of nitrogen oxides between By using an oxide insulating film with a low conductivity, the shift in the threshold voltage of a transistor is reduced. This makes it possible to reduce fluctuations in the electrical characteristics of the transistor.

[0156] The heat treatment in the manufacturing process of a transistor is typically performed at a temperature of 300° C. or higher but below the substrate distortion point. By the heat treatment, the insulating films 453 and 457 show the same properties as those obtained by ESR measurement at 100K or less. The first signal in the spectrum has a g value between 2.037 and 2.039, and the g value is 2.0 A second signal between 01 and 2.003, and a g value between 1.964 and 1.966 The third signal is observed. Note that the split width of the first and second signals is , and the split widths of the second and third signals are set to the values ​​used in the X-band ESR measurement. The g-value is about 5 mT. The first signal, g-value is 2.037 or more and 2.039 or less. The second signal has a g value between 2.001 and 2.003, and a g value between 1.964 and 1.96 The sum of the spin densities of the six or fewer third signals is 1 × 10 18 spins / cm 3 Less than Typically 1×10 17 spins / cm3 More than 1×10 18 spins / cm 3 is less than.

[0157] In addition, the g value is between 2.037 and 2.039 in the ESR spectrum below 100K. The first signal has a g value of 2.001 or more and 2.003 or less, and the second signal has a g value of 1 The third signal, between 0.964 and 1.966, corresponds to the signal caused by nitrogen dioxide. That is, the first signal with a g value of 2.037 or more and 2.039, and the second signal with a g value of 2.001 or more and 2. A second signal with a g value of 1.964 or greater and a third signal with a g value of 1.966 or less. The smaller the total spin density of the electrons, the smaller the nitrogen dioxide content in the oxide insulating film. It can be said that there is no such thing.

[0158] In addition, the heat treatment in the manufacturing process of the transistor is typically performed at temperatures above 300°C and below the substrate distortion point. The oxide insulating film containing nitrogen and having few defects in the heat treatment is analyzed by SIMS (Sec The nitrogen concentration measured by ion mass spectrometry (Ion Mass Spectrometry) 6×10 20 atoms / cm 3 The following is the result.

[0159] The substrate temperature is 220°C or higher, or 280°C or higher, or 350°C or higher, and silane and Using the plasma CVD method using nitrous oxide and dinitrogen monoxide, an oxide containing nitrogen and with few defects was produced. By forming a nitride insulating film, a dense film with high hardness can be formed.

[0160] The transistor in FIG. 29C includes an oxide semiconductor film 455, an insulating film 457, and a conductive film. An insulating film 475 is provided between the film 459 and the nitride insulating film 465. The insulating film 475 is 29(B) shows the insulating films 453b and 457a, which are oxides containing nitrogen and having a small amount of defects. The insulating film can be used.

[0161] In addition, in the cross section in the channel length direction, the channel region 455a and the low resistance region 45 5b, and the low resistance region 455f is formed between the channel region 455a and the low resistance region 455c. The low resistance regions 455f and 455g are the low resistance regions 455 The concentration of impurity elements is lower than that of 455c, and the resistivity is higher. The insulating film 455f and the insulating film 475 are in contact with the side surfaces of the insulating film 457 and the conductive film 459. The low resistance regions 455f and 455g are formed by insulating film 457 and conductive film 45 May overlap with 9.

[0162] In the transistor illustrated in FIG. 29D, the insulating film 457 is formed on the channel of the oxide semiconductor film 455. The insulating layer 455a is in contact with the low resistance regions 455b and 455c. The film 457 has low resistance regions 455b and 455c compared to the region in contact with the channel region 455a. The film thickness in the area in contact with 5c is thin, typically with an average film thickness of 0.1 nm or more and 50 nm or less. As a result, the oxide film 456 is formed on the insulating film 457. The semiconductor film 455 can be doped with an impurity element, and the nitride insulating film 465 can be doped with an impurity element. The contained hydrogen can be transferred to the oxide semiconductor film 455 through the insulating film 457. As a result, low resistance regions 455b and 455c can be formed.

[0163] Furthermore, the insulating film 453 has a multilayer structure of insulating films 453a and 453b, and is heated to remove oxygen. The insulating film 453a is formed using an oxide insulating film that emits nitrogen and has few defects. The insulating film 453b is formed using a thin oxide insulating film. The insulating film 457 is formed using an oxide insulating film with a small amount of defects. The oxide semiconductor film 455 can be covered with a small amount of the oxide insulating film. The oxygen contained in the oxide semiconductor film 53a is transferred to the oxide semiconductor film 455 by heat treatment. While reducing oxygen vacancies in the channel region 455a of the insulating film 455, The carrier traps at the interface between the oxide semiconductor film 457a and the oxide semiconductor film 455 are reduced. As a result, it is possible to reduce the shift in the threshold voltage of the transistor. As a result, fluctuations in the electrical characteristics of the transistor can be reduced.

[0164] <(1). V o Ease of formation and stability of H> When the oxide semiconductor film (hereinafter referred to as IGZO) is a perfect crystal, H is predominantly During the heat treatment at 450°C, H diffuses along the ab plane and In this study, oxygen vacancies in IGZO are considered. o If there is In this case, H is oxygen deficiency V o Here, we will explain whether it is easy to enter the oxygen vacancy V o Medium The state where there is H in V o It is written as H.

[0165] For the calculation, the InGaZnO4 crystal model shown in Figure 30 was used. Here, V o H in H V o The activation barrier (E a ) to NEB (Nud The calculation conditions are shown in Table 1.

[0166] [Table 1]

[0167] In addition, in the InGaZnO4 crystal model, the difference in the number and metal elements to which oxygen is bonded Therefore, there are oxygen sites 1 to 4 as shown in FIG. V o The calculation was carried out for oxygen site 1 and oxygen site 2, which are likely to form

[0168] First, oxygen deficiency V o As oxygen site 1, which is likely to form The calculations were carried out for the oxygen sites bonded to the .

[0169] The model of the initial state is shown in Figure 31(A), and the model of the final state is shown in Figure 31(B). In addition, the calculated activation barrier (E a ) is shown in Figure 32. , here the initial state is oxygen vacancy V o There is an H inside (V o H) and the final state is is oxygen deficiency V o and the state where oxygen bonded to one Ga and two Zn atoms is bonded to H ( HO).

[0170] As a result of the calculation, oxygen deficiency V o It takes about 1.52 eV of energy for the H in the is required, whereas H bonded to O is oxygen vacant V o To enter, it takes about 0.46 eV Energy was needed.

[0171] Here, the calculated activation barrier (Ea ) and Equation 1 to calculate the reaction frequency (Γ) In addition, in the formula 1, k B is the Boltzmann constant and T is the absolute temperature.

[0172]

number

[0173] Frequency factor ν=10 13 The reaction frequency at 350°C was calculated assuming [1 / sec] The frequency of H moving from the model shown in Figure 31(A) to the model shown in Figure 31(B) is 5.5 2×10 0 [1 / sec]. Also, from the model shown in Figure 31(B), The frequency of H transfer to the model shown in is 1.82 × 10 9 [1 / sec]. Therefore, H diffusing in IGZO is attracted to nearby oxygen vacancies V. o There is V o It is easy to form H Once V o H forms oxygen vacancy V o It is thought that it is difficult to be released from

[0174] Next, oxygen deficiency V o As oxygen site 2, which is likely to form a bond with one Ga and two Zn, Calculations were performed for the combined oxygen sites.

[0175] The model of the initial state is shown in Figure 33(A), and the model of the final state is shown in Figure 33(B). In addition, the calculated activation barrier (E a ) is shown in Figure 34. , here the initial state is oxygen vacancy V o There is an H inside (V o H) and the final state is is oxygen deficiency V oand the state where oxygen bonded to one Ga and two Zn atoms is bonded to H ( HO).

[0176] As a result of the calculation, oxygen deficiency V o The H in the bond with another O requires about 1.75 eV of energy is required, whereas H bonded to O is oxygen vacant V o To enter, it takes about 0.35 eV Energy was needed.

[0177] In addition, the calculated activation barrier (E a ) and the above formula 1, the reaction frequency (Γ) is Calculated.

[0178] Frequency factor ν=10 13 The reaction frequency at 350°C was calculated assuming [1 / sec] The frequency of H moving from the model shown in Figure 33(A) to the model shown in Figure 33(B) is 7.5 3×10 -2 [1 / sec]. Also, from the model shown in Figure 33(B), ) the frequency of H transfer to the model shown is 1.44 × 10 10 [1 / sec]. Therefore, once V o H forms oxygen vacancy V o It is thought that H is difficult to release from

[0179] From the above, it can be seen that H in IGZO is easily diffused during annealing, and oxygen vacancy V o If there is is oxygen deficiency V o Enter V o It was found that H is easily obtained.

[0180] <(2). V o H transition level > Oxygen vacancy V in IGZO o and if H exists, then <(1). V o H formation From the calculation using the NEB method shown in the section on ease and stability, oxygen vacancies V o and H is V o H shape Easy to achieve and V o H is considered stable. Therefore, V o H is a career tracker To investigate whether V o The transition levels of H were calculated.

[0181] The calculation was performed using an InGaZnO4 crystal model (112 atoms). V for oxygen sites 1 and 2 o An H model was created and the transition level was calculated. The conditions are shown in Table 2.

[0182] [Table 2]

[0183] By adjusting the mixing ratio of the exchange terms to obtain a band gap close to the experimental value, we obtained a defect-free The band gap of the new InGaZnO4 crystal model is 3.08 eV, which is lower than the experimental value of 3.1 The result was close to 5 eV.

[0184] The transition level (ε(q / q')) of the model with defect D is calculated by the following formula 2: In addition, ΔE(D q ) is the formation energy of defect D at charge q, calculated from Eq. It is served.

[0185]

number

[0186]

number

[0187] In Equation 2 and Equation 3, E tot (D q ) is the charge q of the model including the defect D. Total energy, E tot (bulk) is the total energy of a defect-free model (perfect crystal), Δn i is the number of atoms i that are added or removed due to the defect, μ i is the chemical potential of atom i, ε VBM Missing The energy of the top of the valence band in the defect-free model, ΔV q is related to the electrostatic potential Correction term, E F is the Fermi energy.

[0188] Calculated V o The transition levels of H are shown in Figure 35. The values ​​in Figure 35 represent the depth from the bottom of the conduction band. From Figure 35, V for oxygen site 1 o The transition level of H is 0.0 below the conduction band edge. 5 eV, V for oxygen site 2 o The transition level of H is 0.11e below the conduction band edge. V, so each V o H is thought to be involved in electron trapping. , V o It was revealed that H acts as a donor. o IGZO with H It was revealed that the material is electrically conductive.

[0189] <Band structure> The band structure of the above-mentioned transistor at an arbitrary cross section will be described below.

[0190] FIG. 18A is a cross-sectional view of a transistor that is a semiconductor device according to one embodiment of the present invention. .

[0191] The transistor shown in FIG. 18A is similar to the transistor 150 shown in FIG. do.

[0192] FIG. 18B shows a line A-A' including the channel formation region of the transistor shown in FIG. 18A. The band structure in the cross section is shown. The energy gap of the oxide semiconductor layer is slightly larger than that of the oxide semiconductor layer including the channel formation region 106b. The insulating film 102a, the insulating film 102b, and the gate insulating film 112a are formed in a channel shape. The oxide semiconductor including the channel formation region 106a and the oxide semiconductor including the channel formation region 106b The energy gap is sufficiently larger than that of the channel forming region 106a. an oxide semiconductor, an oxide semiconductor including a channel formation region 106b, an insulating film 102a, and an insulating film The Fermi levels (denoted as Ef) of the gate insulating film 102b and the gate insulating film 112a are The position of the intrinsic Fermi level (denoted as Ei) is also defined as the position of the gate electrode 104a and the gate The work function of the gate electrode 114a is set to the same position as the Fermi level.

[0193] When the gate voltage is set to be equal to or higher than the threshold voltage of the transistor, the channel forming region 106a the conduction band minimum between the oxide semiconductor including the channel formation region 106b and the oxide semiconductor including the channel formation region 106c. Due to the difference in energy between the oxide semiconductor layer and the channel formation region 106a, the electrons preferentially pass through the oxide semiconductor layer including the channel formation region 106a. That is, when electrons are embedded in the oxide semiconductor including the channel formation region 106a, The energy at the bottom of the conduction band is denoted as Ec, and the energy at the top of the valence band is denoted as Energy is represented as Ev.

[0194] Therefore, a transistor that is a semiconductor device according to one embodiment of the present invention has an electron embedding Therefore, the influence of interface scattering is reduced. A transistor having a channel resistance of 0.1 Ω or less has a low channel resistance.

[0195] Next, in FIG. 18(C), a line B-B' including the source region or drain region of the transistor is shown. The band structure in the cross section is shown. The low resistance region 107a2 and the low resistance region 107b2 are in a degenerated state. In 107b1, the Fermi level of the oxide semiconductor including the channel formation region 106a is The energy of the low-resistance region 107b2 is set to be approximately the same as the energy of the lower edge of the conduction band. The Fermi level of the oxide semiconductor including the formation region 106b is approximately the same as the energy of the bottom of the conduction band. The same applies to the low resistance region 107a1 and the low resistance region 107a2.

[0196] At this time, the drain electrode 116b and the low resistance region 107b2 have a sufficient energy barrier. Since the low resistance region 107b2 is smaller than the low resistance region 107b1, an ohmic contact is formed. Similarly, the source electrode 116a and the low resistance region 107 form an ohmic contact. The energy barrier between a2 and a3 is small enough to form an ohmic contact. The source 107a2 and the low resistance region 107a1 are in ohmic contact. The oxide semiconductor including the electrode 116a, the drain electrode 116b, and the channel forming region 106a Electrons are smoothly exchanged between the oxide semiconductor layer and the oxide semiconductor layer including the channel formation region 106b. I know it will be done.

[0197] As described above, the transistor which is a semiconductor device according to one embodiment of the present invention has a source Electrons are smoothly exchanged between the drain electrode and the channel forming region, In addition, it is a transistor with low channel resistance, i.e., it has excellent switching characteristics. It turns out to be a transistor.

[0198] In addition, a transistor structure in which an oxide semiconductor film is formed in three layers, such as the transistor shown in FIG. The band structure of the transistor with two oxide semiconductor layers, such as the transistor shown in Figure 1, The band structure of the transistor shown in FIG. FIG. 43(B) shows the band structure of the transistor 150 shown in FIG. For ease of understanding, the insulating film 102, the first region 106, and the gate insulating film 112a are shown. The energy (Ec) of the conduction band edge of

[0199] As shown in FIG. 43(A), a channel forming region 106a, a channel forming region 106b, In the channel formation region 106c, the energy of the conduction band minimum changes continuously. This is a channel forming region 106a, a channel forming region 106b, and a channel forming region 106c. This is also understood from the fact that the elements that make up 106c are common, making it easy for oxygen to diffuse between them. Therefore, the channel forming region 106a, the channel forming region 106b, and the channel The panel-forming region 106c is a laminate of films with different compositions, but is physically continuous. It is also possible.

[0200] The oxide semiconductor film, which is stacked with a common main component, is not simply stacked, but is continuously Junction (here, specifically, a U-shaped well where the energy of the bottom of the conduction band changes continuously between layers) The structure is fabricated so that a U-Shape Well structure is formed. In the oxide semiconductor, defect levels such as trap centers and recombination centers, or carrier The laminated structure is formed so that there are no impurities that hinder the flow of oxygen. When impurities are mixed between layers of a semiconductor film, the continuity of the energy band is lost, and the boundary At this surface, carriers disappear due to trapping or recombination.

[0201] In FIG. 43A, the E Although the case where c is the same is shown, they may be different.

[0202] As shown in FIG. 43A, the channel forming region 106a becomes a well, and the transistor It can be seen that a channel is formed in the channel formation region 106a. The panel forming region 106a, the channel forming region 106b, and the channel forming region 106c are conductive. Since the energy of the lower band edge changes continuously, a U-shaped well structure channel is embedded. It can also be called a channel.

[0203] As shown in FIG. 43(B), the channel forming region 106a and the channel forming region 10 In 6b, the energy of the conduction band minimum may change continuously.

[0204] As shown in FIG. 43(B), the channel forming region 106a becomes a well, and the transistor It can be seen that a channel is formed in the channel formation region 106a.

[0205] The transistor shown in FIG. 42 includes one or more metal elements that form the channel formation region 106a. Since the channel forming region 106b and the channel forming region 106c are included , the interface between the channel formation region 106a and the channel formation region 106c, and Therefore, an interface state is less likely to be formed at the interface between the region 106a and the channel formation region 106b. By providing the channel forming region 106b and the channel forming region 106c, This can reduce variations and fluctuations in electrical characteristics such as the threshold voltage of the transistor.

[0206] The transistor shown in FIG. 1 includes one or more metal elements that form the channel formation region 106a. Since the channel forming region 106b includes the channel forming region 106a, Therefore, the interface state is hardly formed at the interface with the channel forming region 106b. By providing the region 106b, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. This can reduce noise and fluctuations.

[0207] <Method for manufacturing semiconductor device> Next, a method for manufacturing the transistor 150 and the capacitor 160 shown in FIG. 1 will be described with reference to FIGS. This will be explained using FIG.

[0208] The transistor 150 and the capacitor 160 are made of films (insulating films, oxide semiconductor films, conductive films, etc.). The deposition methods include sputtering, chemical vapor deposition (CVD), vacuum deposition, and pulse laser. It can be formed using a deposition (PLD) method, or it can be formed by a coating method or a printing method. The film formation method includes sputtering and plasma enhanced chemical vapor deposition (PECV). The typical method is MOCVD (metal organic chemical vapor deposition), but thermal CVD may also be used. Alternatively, an organic metal chemical vapor deposition (AMCVD) method or an ALD (atomic layer deposition) method may be used.

[0209] In the thermal CVD method, the pressure in the chamber is atmospheric or reduced, and the source gas and oxidant are simultaneously mixed. The reaction is carried out in the chamber near or on the substrate, where it is deposited on the substrate to form a film. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0210] In addition, in the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is The gases are introduced into the chamber in sequence, and the film is formed by repeating this gas introduction sequence. By switching each switching valve (also called high-speed valve), two or more types of raw materials can be The source gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the source gases. Simultaneously with or after the second gas, an inert gas (argon, nitrogen, etc.) is introduced. Introduce the source gas. If an inert gas is introduced at the same time, the inert gas is used as a carrier gas. In addition, an inert gas may be introduced at the same time as the second source gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is discharged by vacuum evacuation, and then the second source gas is introduced. The first source gas may be adsorbed on the surface of the substrate to form a first monoatomic layer. The second monoatomic layer is formed by reacting with the second source gas introduced later. Layer upon layer is laminated to form a thin film.

[0211] This gas introduction sequence is repeated multiple times while controlling it until the desired thickness is achieved. The thickness of the thin film increases depending on the number of times the gas introduction sequence is repeated. Therefore, precise film thickness control is possible, and fine transistors can be fabricated. It is suitable for manufacturing.

[0212] First, an insulating film 101 is formed on a substrate 100, and a gate electrode 104a and a Then, the lower electrode 104b is formed (see FIG. 8).

[0213] The gate electrode 104a and the lower electrode 104b are formed by sputtering, vacuum deposition, pulse deposition, or the like. It can be formed by using a laser deposition (PLD) method, a thermal CVD method, etc. Instead of the above-mentioned method, the gate electrode 104a and the gate electrode 104b are formed by electroplating, printing, ink jetting, or the like. A lower electrode 104b may be formed.

[0214] Next, the insulating film 102a and the insulating film 102b are formed on the insulating film 101, the gate electrode 104a, and the lower electrode 104b. and an insulating film 132 are formed (see FIG. 9).

[0215] The insulating film 102a and the insulating film 132 can be formed by a sputtering method, a CVD method, a vapor deposition method, a pulse laser method, or the like. The layer can be formed by appropriately using a laser deposition (PLD) method, a printing method, a coating method, or the like. The insulating film 132 may be made of the same material as the insulating film 102b.

[0216] Next, a desorption suppression film 113 that suppresses desorption of oxygen is formed on the insulating film 132. Oxygen 140 is added to the insulating film 132 through the release inhibitor film 113 (see FIG. 10).

[0217] The detachment inhibiting film 113 is made of aluminum, chromium, tantalum, titanium, molybdenum, nickel, or the like. a metal element selected from the group consisting of zinc, iron, cobalt, and tungsten; Alloys, alloys combining the above-mentioned metal elements, metal nitrides having the above-mentioned metal elements, Conductive metal oxides containing the above-mentioned metal elements, metal nitride oxides containing the above-mentioned metal elements, etc. It is formed using a material having such properties.

[0218] The thickness of the detachment-inhibiting film 113 can be set to 0.1 nm or more and 10 nm or less.

[0219] As a method for adding oxygen 140 to the insulating film 132 through the detachment suppression film 113, ion The methods include doping, ion implantation, and plasma treatment. By providing the insulating film 132 and adding oxygen, the detachment suppression film 113 prevents oxygen from being detached from the insulating film 132. Therefore, the insulating film 132 is doped with a large amount of oxygen. can be added.

[0220] In addition, when oxygen is introduced in plasma treatment, the oxygen is excited by microwaves to form high-density oxygen. By generating oxygen plasma, the amount of oxygen introduced into the insulating film 132 can be increased. .

[0221] Next, the detachment suppression film 113 is removed to form an insulating film 132 to which oxygen is added. This is possible (see Figure 11).

[0222] The insulating film 132 can be formed by sputtering, CVD, vapor deposition, pulsed laser deposition ( The insulating film 132 can be formed by appropriately using a PLD method, a printing method, a coating method, or the like. After forming the insulating film, oxygen may be added to the insulating film. There are radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. The methods include ion doping, ion implantation, and plasma treatment.

[0223] In addition, the substrate placed in the evacuated processing chamber of the plasma CVD device is heated to 180°C or higher. The temperature is kept at 280°C or below, or between 200°C and 240°C, and the raw material gas is introduced into the processing chamber. The pressure in the processing chamber should be between 100 Pa and 250 Pa, or between 100 Pa and 200 Pa. a or less, and the electrode installed in the processing chamber is 0.17 W / cm 2 More than 0.5W / cm 2 below , or 0.25 W / cm 2 More than 0.35W / cm 2 The following high frequency power supply conditions are met: Therefore, a silicon oxide film or a silicon oxynitride film capable of releasing oxygen by heat treatment is used. The insulating film 132 can be formed of a silicon film.

[0224] Next, a mask is formed on the insulating film 132 by a lithography process, and then the mask is used to By etching a part of the insulating film 132 that overlaps with the lower electrode 104b, Form 102b.

[0225] Next, the oxide semiconductor film 126a and the oxide semiconductor film 126b are stacked over the insulating film 102b. An oxide semiconductor film 126 containing the compound (III) is formed (see FIG. 12).

[0226] A method for forming the oxide semiconductor film 126 is described below. Tarring method, coating method, pulsed laser deposition method, laser ablation method, thermal CVD method, etc. The oxide semiconductor films 126a and 126b are formed by the above-mentioned method. Next, a mask is formed over the oxide semiconductor film by a lithography process. By etching part of the oxide semiconductor film using a fluorine-containing compound, the oxide semiconductor film is The conductive film 126 can be formed. After that, the mask is removed. After the oxide semiconductor film 126 is formed by etching part of the film, heat treatment may be performed. .

[0227] In addition, by using a printing method for the oxide semiconductor film 126, an oxide semiconductor film having element isolation can be formed. The membrane 126 can be formed directly.

[0228] When an oxide semiconductor film is formed by a sputtering method, a power source for generating plasma is used. The device may be an RF power supply device, an AC power supply device, a DC power supply device, or the like. The CAAC-OS film can be formed by using an AC power supply or a DC power supply. It is also possible to form an oxide semiconductor film by sputtering using an RF power supply. Rather than using a sputtering method using an AC power supply or a DC power supply, an oxide semiconductor film is formed by sputtering. It is preferable to form the film on a thin film substrate because the film thickness distribution, film composition distribution, or crystallinity distribution will be uniform. stomach.

[0229] The sputtering gas is a rare gas (typically argon), oxygen, or a mixture of rare gas and oxygen. In the case of a mixture of rare gas and oxygen, the ratio of the oxygen gas to the rare gas is A higher ratio is preferred.

[0230] The target may be appropriately selected depending on the composition of the oxide semiconductor film to be formed. .

[0231] Note that when the oxide semiconductor film is formed by, for example, a sputtering method, The temperature is set to 150°C or higher and 750°C or lower, or 150°C or higher and 450°C or lower, or 200°C or higher. The oxide semiconductor film is formed at a temperature of 350° C. or lower to form a CAAC-OS film. Furthermore, by setting the substrate temperature to 25°C or higher and lower than 150°C, it is possible to form a microcrystalline oxide semiconductor. A conductive film can be formed.

[0232] In addition, in order to form a CAAC-OS film described later, the following conditions are preferably applied: It's nice.

[0233] By suppressing the inclusion of impurities during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas having a temperature of -80°C or lower or -100°C or lower is used.

[0234] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition can be reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, or 100% by volume or more. Let it be %.

[0235] After the oxide semiconductor film is formed, heat treatment is performed to dehydrogenate or The temperature of the heat treatment is typically 150° C. or higher and lower than the substrate distortion point. Alternatively, the temperature is 250°C or higher and 450°C or lower, or 300°C or higher and 450°C or lower.

[0236] Heat treatment is carried out using rare gases such as helium, neon, argon, xenon, krypton, or It is carried out in an inert gas atmosphere containing nitrogen, or after heating in an inert gas atmosphere, it is heated in an oxygen atmosphere. It should be noted that the inert atmosphere and oxygen atmosphere do not contain hydrogen, water, etc. The treatment time is preferably from 3 minutes to 24 hours.

[0237] The heat treatment can be carried out using an electric furnace, an RTA device, or the like. Therefore, heat treatment can be performed at a temperature above the strain point of the substrate for a short period of time. The processing time can be reduced.

[0238] The oxide semiconductor film is formed while being heated, and after the oxide semiconductor film is formed, By performing heat treatment, the oxide semiconductor film is The hydrogen concentration is 5×10 19 atoms / cm 3 or less, or 1 x 10 19 atoms / c m 3 Below, 5 x 10 18 atoms / cm 3 or less, or 1 x 10 18 atoms / cm 3 or less, or 5 x 10 17 atoms / cm 3 or less, or 1 x 10 16 atoms / cm 3 It can be as follows:

[0239] Oxide semiconductor films, such as InGaZnO, are formed using a deposition system that uses ALD. X (X>0) When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form InO Then, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form a GaO layer. Then, Zn(CH3)2 and O3 gases are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. Also, by mixing these gases, the InGaO2 layer and mixed compound layers such as InZnO2 layer, GaInO layer, ZnInO layer, and GaZnO layer. It is also possible to use H2O gas bubbled with an inert gas such as Ar instead of O3 gas. However, it is preferable to use O3 gas that does not contain H. In(CH3) In place of the gas In(C2H5)3, gas Ga(CH3)3 may be used. Alternatively, Ga(C2H5)3 gas may be used. That's fine.

[0240] Here, an oxide semiconductor film having a thickness of 35 nm is formed by a sputtering method. Heat treatment is performed to move oxygen contained in the insulating film 102b to the oxide semiconductor film. A mask is formed over the oxide semiconductor film, and part of the oxide semiconductor film is selectively etched. In this way, the oxide semiconductor film 126 is formed.

[0241] The heat treatment should be performed at a temperature between 350°C and 650°C, or between 450°C and 600°C. By performing the above process, it is possible to obtain an oxide semiconductor film with reduced contents of hydrogen, water, and the like. That is, an oxide semiconductor film having a low impurity concentration and a low density of defect states can be formed. Cut.

[0242] Next, an insulating film and two conductive films are formed over the oxide semiconductor film 126 and the insulating film 102a. After forming a mask on the two conductive layers by a lithography process, the two conductive layers are By etching a part of the conductive film and insulating film of the layer, the gate electrode 114a and the upper electrode 1 14b, a gate insulating film 112a and an insulating film 112b are formed (see FIG. 13).

[0243] The insulating films that become the gate insulating film 112a and the insulating film 112b are formed by sputtering, CVD, or the like. It is formed by the vacuum deposition method, the pulsed laser deposition (PLD) method, the thermal CVD method, etc. The two conductive layers that form the electrode 114a and the upper electrode 114b are formed by sputtering or vacuum deposition. The two-layer conductive film is formed by the pulsed laser deposition (PLD) method, thermal CVD method, etc. Instead of this forming method, electrolytic plating, printing, ink jetting, etc. may be used.

[0244] In addition, a tungsten film is formed as a two-layer conductive film using a film formation device that uses ALD. In this case, WF6 gas and B2H6 gas are introduced repeatedly in sequence to form the initial Then, WF6 gas and H2 gas are introduced simultaneously to form a tungsten film. It should be noted that SiH4 gas may be used instead of B2H6 gas.

[0245] Although not shown, after forming the insulating films that will become the gate insulating film 112a and the insulating film 112b, An opening is provided in the insulating film and the insulating film 102, and the gate electrode 114a and the upper Two layers of conductive film that will become the electrode 114b are formed and etched to form the gate electrode 104a and the gate The electrodes 114a may be electrically connected.

[0246] Next, as shown in FIG. 13, the oxide semiconductor film 12 is formed using the gate electrode 114a as a mask. As a result, the impurity element 142 is added to the gate electrode 114 in the oxide semiconductor film. The impurity element 142 is added to the region not covered by a. In the oxide semiconductor film that has been damaged by this, defects, typically oxygen vacancies, are formed. When hydrogen is added to an oxide semiconductor with oxygen vacancies, hydrogen enters the oxygen vacancy sites and the conduction band is increased. A donor level is formed adjacent to the first region 106, and a pair of second regions sandwiching the first region 106 The first region 106 is formed with the impurity ions 107a and 107b (see FIG. 14). This is a region to which no elements are added, and can be made highly pure and intrinsic.

[0247] The impurity element 142 can be added by ion doping, ion implantation, plasma There are various processing methods.

[0248] The addition of the impurity element 142 is controlled by appropriately setting implantation conditions such as acceleration voltage and dose amount. For example, when adding argon by ion implantation, the acceleration voltage is 10 kV and the The amount of noise is 1 x 10 13 ions / cm 2 More than 1×10 16 ions / cm 2 If we assume the following Well, for example, 1 x 10 14 ions / cm 2 In addition, phosphorus can be implanted by ion implantation. When ions are added, the acceleration voltage is 30 kV and the dose is 1 × 10 13 ions / cm 2 5x10 or more 16 ions / cm 2 For example, 1×10 15 ions / cm 2 This can be done as follows.

[0249] Note that instead of the impurity element 142, the oxide semiconductor film 126 is irradiated with ultraviolet light or the like to form an oxide semiconductor film. Alternatively, oxygen vacancies may be formed in the oxide semiconductor film 126. Oxygen vacancies may be formed in the oxide semiconductor film 126 by irradiation with ultraviolet light.

[0250] Next, the insulating film 138 and the insulating film 148 are formed (see FIG. 15). The insulating film 148 may be produced by the same method as the insulating film 102a, the insulating film 132, etc. This can be done.

[0251] Next, a mask is formed on the insulating film 148 by a lithography process, and then the insulating film 138 and and a part of the insulating film 148 is etched to remove a part of the pair of second regions 107a and 107b. Two openings are formed to expose the insulating film 108 and the insulating film 118. (See Figure 16.)

[0252] Next, two layers of conductive film are formed on the insulating film 118 and the pair of second regions 107a and 107b. After forming a mask on the upper conductive film of the two-layer conductive film by a lithography process, The conductive film of the layer is partially etched to form the source electrode 116a and the drain electrode 116b. (See Figure 17.)

[0253] Next, an insulating film 128 is formed on the insulating film 118, the source electrode 116a, and the drain electrode 116b. Form.

[0254] Through the above steps, the transistor 150 and the capacitor 160 can be formed at the same time. Cut.

[0255] In addition, the connection of each wiring in a semiconductor device according to one embodiment of the present invention will be described below. do.

[0256] As shown in FIG. 19A, a gate electrode serving as a back gate electrode of the transistor 150 is The wiring 204 (conductive film 204a and conductive film 204) is formed in the same process as the port electrode 104a. The insulating film 102 formed on the insulating film 102b and the insulating film 112a that will become the gate insulating film 112a are stacked on the insulating film 102. After forming a mask by a lithography process, a part of the laminated insulating layer is The wiring 204 is then etched to form an opening that reaches the wiring 204. A conductive film that will become the gate electrode 114a is formed, and a mask is formed on the conductive film by a lithography process. After forming the mask, the conductive film and one of the insulating films that will become the gate insulating film 112a are formed using the mask. The wiring 214 (a laminate of the conductive film 214a and the conductive film 214b) and the insulating film are removed by etching. Further, the insulating film 108 and the insulating film 118 are formed on the wiring 214. After forming a mask on the film 118 by a lithography process, the insulating film 10 is formed using the mask. 8 and a part of the insulating film 118 are etched to provide an opening that reaches the wiring 214. A conductive film that will become the source electrode or drain electrode of the transistor 150 is formed through the conductive film. A mask is formed on the conductive film by a lithography process, and then a part of the conductive film is removed using the mask. The resulting film is etched to form the wiring 216 (a stack of a conductive film 216a and a conductive film 216b). By going through the above steps, the wiring 204 as shown in FIG. 19(A) is formed via the wiring 214. 216. In addition, a lithography process may be performed on the laminate of the insulating layer. After forming a mask by a film process, the insulating film 102b and the gate insulating film are formed using the mask. After etching a part of the insulating film that will become 112a, the insulating film 102a, the insulating film 102b, and After forming a mask on the insulating film that will become the gate insulating film 112a by a lithography process, A part of the insulating film 102a is etched using a mask to form an opening that reaches the wiring 204. Good too.

[0257] The upper layer of the wiring 204 (conductive film 204b) and the upper layer of the wiring 216 (conductive film 216b) It is preferable to use a low resistance conductive material such as copper or aluminum. By using a highly conductive material, signal delay can be reduced.

[0258] 19(B), the wiring 214 is formed on the insulating film 108 and The portion electrically connected to the wiring 216 through the opening provided in the insulating film 118 and the portion shown in FIG. 19(C) As shown in FIG. 2, the wiring 204 is formed through the opening provided in the laminate of the insulating layers by the above-mentioned process. 12 and 13, the wiring 214 may be electrically connected to the wiring 214. The method of electrically connecting the gate electrode 104a and the gate electrode 114a described in FIG. The connection method in 9(C) can be used.

[0259] In this embodiment, the wiring 214 is wired through an opening provided in the laminate of the insulating layers. 204, and the wiring 204 and the wiring 216 are configured to cross each other. Therefore, as shown in FIG. 19(D), the insulating film 102 and the insulating film 216 are formed between the wiring 204 and the wiring 216. 108 and the insulating film 118, the parasitic capacitance at the intersection of the wirings As a result, the signal delay due to the parasitic capacitance can be reduced. .

[0260] In this embodiment, when an oxide semiconductor film is used for a channel or the like, Although an example has been given, one aspect of the embodiment of the present invention is not limited to this. For example, In the vicinity thereof, in the source region, the drain region, etc., depending on the circumstances, Therefore, Si (silicon), Ge (germanium), SiGe (silicon germanium), It may be formed of a material including GaAs (gallium arsenide), etc.

[0261] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0262] (Embodiment 2) In this embodiment, a structure of an oxide semiconductor included in a semiconductor device of one embodiment of the present invention will be described. I will explain.

[0263] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor) uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous l Examples include amorphous oxide semiconductors, amorphous oxide semiconductors, and amorphous oxide semiconductors.

[0264] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxides. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductor, and nc-OS.

[0265] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond is short-range. This can also be described as a structure that has a high degree of order but no long-range order.

[0266] On the other hand, in the case of an essentially stable oxide semiconductor, it is possible to obtain a completely amorphous structure. It cannot be called an oxide semiconductor (isotropic amorphous). The oxide semiconductor is then oxidized to form a completely amorphous structure. However, a-like OS is a semiconductor that can be used in a microscopic area. Although it has a periodic structure, it has voids and is an unstable structure. It can be said that the physical properties are similar to those of an amorphous oxide semiconductor.

[0267] <caac-os> First, let me explain about CAAC-OS.

[0268] CAAC-OS is an oxide having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0269] Transmission Electron Microscope (TEM) A combined analysis image (high resolution) of the bright-field image and diffraction pattern of CAAC-OS was obtained by using a microscope. When observing a high-resolution TEM image, multiple pellets can be confirmed. On the other hand, high-resolution TEM images reveal the boundaries between pellets, i.e., grain boundaries. Therefore, the CAAC-OS is not clearly characterized by the grain boundaries. It can be said that the resulting decrease in electron mobility is unlikely to occur.

[0270] Below, we will explain the CAAC-OS observed by TEM. 1 shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction is required. The spherical aberration correction function was used to obtain high-resolution TEM images. , specifically referred to as a Cs-corrected high-resolution TEM image. Cs-corrected high-resolution TEM images can be obtained, for example, This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0271] An enlarged Cs-corrected high-resolution TEM image of area (1) in Figure 20(A) is shown in Figure 20(B). From Figure 20(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). Or it reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0272] As shown in Figure 20(B), CAAC-OS has a characteristic atomic arrangement. ) shows the characteristic atomic arrangement with auxiliary lines. ) the size of each pellet can be 1 nm or more, or 3 nm or more. It can be seen that the size of the gap caused by the tilt between the sintered body and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). CAAC-OS is also used for CANC (C-Axis Aligned Nanoclip). The semiconductor may also be referred to as an oxide semiconductor having metals.

[0273] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on the substrate 6120 were The layout of the 6100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 20(D)). Between the pellets observed in FIG. 20(C), The portion where the tilt occurs corresponds to the region 6161 shown in FIG. 20(D).

[0274] FIG. 21(A) shows the C of the plane of the CAAC-OS observed from a direction approximately perpendicular to the sample surface. The s-corrected high-resolution TEM images are shown. Regions (1), (2), and (3) in Figure 21(A). ) are enlarged Cs-corrected high-resolution TEM images shown in Fig. 21(B), Fig. 21(C), and Fig. 21(D), respectively. As shown in Figure 21(D), Figure 21(B), Figure 21(C) and Figure 21(D) show that the pellet It can be seen that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0275] Next, C analyzed by X-ray diffraction (XRD) For example, CAAC-O with InGaZnO4 crystals When S is subjected to structural analysis using the out-of-plane method, the results are as shown in Figure 22(A). As shown in the figure, a peak may appear at a diffraction angle (2θ) of around 31°. Since this is attributed to the (009) plane of the ZnO4 crystal, it is believed that the CAAC-OS crystal is c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0276] In addition, in the structural analysis of CAAC-OS using the out-of-plane method, 2θ is 31 In addition to the peak around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks in the vicinity indicate that some of the CAAC-OS crystals do not have a c-axis orientation. The more preferable CAAC-OS is a structure produced by the out-of-plane method. The analysis shows a peak at 2θ around 31°, but no peak at 2θ around 36°.

[0277] On the other hand, in-pla, X-rays are incident on the CAAC-OS from a direction almost perpendicular to the c-axis. When structural analysis is performed using the NE method, a peak appears at 2θ around 56°. This peak is due to I It is attributed to the (110) plane of the nGaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 5 The sample is fixed at approximately 6° and analyzed while rotating around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears, as shown in Figure 22(B). On the other hand, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ When scanned, it is assigned to a crystal plane equivalent to the (110) plane as shown in Figure 22(C). Six peaks are observed. Therefore, from the structural analysis using XRD, CAAC-OS It can be seen that the orientation of the a-axis and b-axis is irregular.

[0278] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the probe diameter is 300 nm parallel to the sample surface. When an electron beam is incident on the sample, a diffraction pattern (selected area transmission electron diffraction) as shown in FIG. This diffraction pattern may appear due to the presence of InGaZnO4 This includes spots due to the (009) plane of the crystal. The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis faces the surface to be formed or the upper surface. On the other hand, when the probe was applied to the same sample perpendicular to the sample surface, The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in Figure 23(B). 3(B), a ring-shaped diffraction pattern is confirmed. Therefore, electron diffraction It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. The first ring in FIG. 23(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and the like. This is thought to be due to the (110) surface.

[0279] As described above, CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the incorporation of impurities or the generation of defects, so the opposite view can be taken. Therefore, CAAC-OS can be considered an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0280] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon are more oxidative than metal elements that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0281] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0282] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. There is. Specifically, 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than, More preferably, 1 × 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than Such an oxide semiconductor can be a high-purity intrinsic or The CAAC-OS is essentially a highly pure intrinsic oxide semiconductor. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0283] <nc-os> Next, we will explain nc-OS.

[0284] In the high-resolution TEM image, nc-OS has two distinct regions: one where crystals can be confirmed and the other where clear crystals can be confirmed. The crystalline part contained in nc-OS is The size is often between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, nc-OS shows grain boundaries. In some cases, the nanocrystals are not clearly visible. Therefore, in the following, the crystalline part of nc-OS is referred to as the pellet. There is a chance to call.

[0285] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. For example, in contrast to nc-OS, there are cases where it is difficult to distinguish the particles from the pellets. When X-rays are used, the peaks that indicate the crystal planes are In addition, for nc-OS, a probe diameter larger than the pellet (e.g., 50 When electron diffraction is performed using an electron beam of 1000 nm or more, a halo-like diffraction pattern is produced. On the other hand, for nc-OS, pellets with sizes close to or smaller than the pellets were observed. When nanobeam electron diffraction is performed using an electron beam with a lobe diameter, spots are observed. When nanobeam electron diffraction is performed on nc-OS, high brightness regions are observed in a circular (ring-like) pattern. In addition, multiple spots may be observed within a ring-shaped area. This may be the case.

[0286] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc -OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) The semiconductor may also be referred to as an oxide semiconductor having a structure (s).

[0287] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in the crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0288] <a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a semiconductor.

[0289] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystalline parts can be clearly seen, and areas where crystalline parts can be seen. and areas where it is not possible to

[0290] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0291] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS (hereinafter referred to as Sample B) and CAAC-OS (hereinafter referred to as Sample C) are prepared. Both samples are In-Ga-Zn oxides.

[0292] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all the materials have crystalline parts.

[0293] The determination of which part is to be regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, six of which are stacked in layers in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing is 0.28 nm or more and 0.30 nm or less are considered to be InGaZnO4 crystal parts. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0294] Figure 24 shows an example of investigating the average size of the crystal parts (22 to 45 locations) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystalline part of ke OS grows in size according to the cumulative amount of electron irradiation. Specifically, as shown by (1) in Figure 24, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2 × 10 8 e - / n m 2 On the other hand, in the nc-O For S and CAAC-OS, the cumulative electron irradiation dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystal part within the range of As shown in (2) and (3) in Figure 24, regardless of the cumulative electron dose, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. It can be seen that...

[0295] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in nc-OS and CAAC-OS, the growth of the crystals by electron irradiation is almost nonexistent. In other words, a-like OS is not as good as nc-OS and CAAC- It is clear that it has an unstable structure compared to the OS.

[0296] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal of the same composition. The density of the nc-OS is 78.6% or more and less than 92.3% of that of the normal crystal. The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0297] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It will be less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0298] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions may be used in any proportion. By combining single crystals with the desired composition, the density equivalent to that of a single crystal can be estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate by combining different types of single crystals.

[0299] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the above-mentioned compounds.

[0300] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0301] (Embodiment 3) In this embodiment, a deposition model of a CAAC-OS and an nc-OS will be described.

[0302] FIG. 46(A) shows a process of forming a CAAC-OS film by sputtering. Schematic diagram of the inside of the membrane chamber.

[0303] The target 630 is adhered onto a backing plate. A plurality of magnets are arranged under the backing plate. A magnetic field is generated above the target 630. The film deposition rate is controlled by using the magnetic field of the magnet. The sputtering method that enhances this is called magnetron sputtering.

[0304] The target 630 has a polycrystalline structure, and each crystal grain includes a cleavage plane. The cleavage plane will be described in detail later.

[0305] The substrate 620 is disposed so as to face the target 630, and the distance therebetween is d (target The distance between the get and the substrate (also called the distance between the TS) is 0.01 m or more and 1 m or less, preferably The thickness of the film deposition chamber is between 0.02m and 0.5m. Most of the film deposition gas (e.g., oxygen) , argon, or a gas mixture containing 50% or more by volume of oxygen) and The pressure is controlled to be in the range of 0.1 Pa to 100 Pa, preferably in the range of 0.1 Pa to 10 Pa. By applying a voltage above a certain level to the target 630, discharge begins and plasma is observed. A high density plasma region is formed by the magnetic field above the target 630. In the high density plasma region, the deposition gas is ionized to generate ions 601. The ion 601 is, for example, an oxygen cation (O + ) and argon cations (Ar + ) etc. do.

[0306] The ions 601 are accelerated toward the target 630 by the electric field, and eventually reach the target 63 At this time, pellets, which are sputtered particles in the shape of plates or pellets, are ejected from the cleavage plane. The pellet 600a and the pellet 600b are separated and knocked out. The structure of the pellet 600b may be distorted by the impact of the ion 601. There is.

[0307] The pellet 600a is a flat or pellet-shaped pellet having a triangular, for example, equilateral triangular, plane. The pellet 600b is a sputtered particle. The pellet 600b has a hexagonal, for example, regular hexagonal, plane. The pellets 600a and 600b are sputtered particles in the form of plates or pellets. The plate-shaped or pellet-shaped sputtered particles such as 600b are collectively referred to as pellets 600. The planar shape of the pellet 600 is not limited to a triangle or a hexagon. For example, two triangles may be used. For example, if two triangles (equilateral triangles) are joined together, the shape may be formed by joining more than six triangles. It may also be a rectangular (diamond) shape.

[0308] The thickness of the pellet 600 is determined depending on the type of deposition gas, etc. The reason for this will be described later. It is preferable that the thickness of the pellet 600 is uniform. Pellets are preferred over thick cubes.

[0309] The pellet 600 receives an electric charge as it passes through the plasma, causing the sides to become negative or positive. The pellet 600 has oxygen atoms on the side, and the oxygen atoms are negatively charged. For example, if pellet 600a has negatively charged oxygen atoms on the side, An example of this is shown in Figure 48. In this way, the sides are charged with the same polarity, This causes a repulsion of the particles, allowing the plate-like shape to be maintained. In the case of In-Ga-Zn oxide, the oxygen atoms bonded to the indium atoms are negatively charged. Or, oxygen bonded to an indium atom, a gallium atom, or a zinc atom Atoms can become negatively charged.

[0310] As shown in FIG. 46(A), for example, a pellet 600 flies like a kite through the plasma. The pellet 600 then flutters up onto the substrate 620. Therefore, when an area where other pellets 600 have already accumulated approaches, a repulsive force is generated. On the upper surface of the substrate 620, a magnetic field is generated in a direction parallel to the upper surface of the substrate 620. A potential difference is applied between the plate 620 and the target 630, so that the A current flows toward the target 630. Therefore, the pellet 600 is The upper surface of the 0 is subjected to a force (Lorentz force) due to the action of the magnetic field and current (Figure 4 9.) This can be understood by Fleming's left-hand rule. In order to increase the force applied to the substrate 600, the upper surface of the substrate 620 The magnetic field parallel to the More preferably, a region where the voltage is 50 G or more is provided. In this case, the magnetic field parallel to the upper surface of the substrate 620 is larger than the magnetic field perpendicular to the upper surface of the substrate 620. 1.5 times or more, preferably 2 times or more, more preferably 3 times or more, and even more preferably 5 times or more It is a good idea to set up an upper area.

[0311] In addition, the substrate 620 is heated, and friction or the like is prevented between the pellet 600 and the substrate 620. As a result, as shown in FIG. 50(A), the pellet 600 The pellet 600 glides over the top surface of the substrate 620. This occurs in a state facing the plate 620. Then, as shown in FIG. 50(B), When the pellet reaches the side of another pellet 600, the sides join together. The oxygen atom on the side of 600 is released. The released oxygen atom causes the Since the oxygen vacancies in the CAAC-OS can be filled, the CAAC-OS has a low density of defect states.

[0312] Furthermore, when the pellet 600 is heated on the substrate 620, the atoms are rearranged, and the ions are The distortion of the structure caused by the collision of the pellet 601 is relaxed. The pellets 600 become almost single crystals. Even if the pellet 600 is heated after bonding, it is unlikely that the pellet 600 itself will expand or contract. Therefore, the gaps between the pellets 600 widen, forming defects such as grain boundaries, and The gaps are filled with elastic metal atoms, It is thought that the sides of the misaligned pellets 600 are connected like a highway.

[0313] Based on the above model, it is considered that the pellets 600 are deposited on the substrate 620. Therefore, unlike epitaxial growth, if the surface on which the film is to be formed does not have a crystalline structure, For example, it is possible to form a CAAC-OS film on the upper surface of the substrate 620. Even if the structure of the surface to be formed is amorphous, it is possible to form a CAAC-OS film. do.

[0314] In addition, the CAAC-OS can be formed not only on a flat surface but also on the substrate 620, which is the surface on which the CAAC-OS is formed. Even if the surface is uneven, the pellets 600 are aligned along the shape of the surface. For example, if the top surface of the substrate 620 is atomically flat, the pellet 600 will have a flat surface parallel to the ab plane. The flat surfaces are arranged side by side with the surface facing downwards, resulting in a uniform thickness, flatness, and high crystallinity. Then, by stacking these layers n levels (n is a natural number), CAAC- The OS can be obtained (see Figure 46(B)).

[0315] On the other hand, even if the upper surface of the substrate 620 has unevenness, the CAAC-OS can be easily formed by the pellet 600. The substrate 620 has a structure in which layers arranged side by side along the convex surface are stacked in n stages (n is a natural number). Since the surface of the CAAC-OS has unevenness, gaps may easily occur between the pellets 600. However, intermolecular forces act between the pellets 600, so even if there are irregularities, there are no gaps between the pellets. Therefore, CA with high crystallinity is obtained even if there are irregularities. It can be AC-OS (see Figure 46(C)).

[0316] Therefore, CAAC-OS does not require laser crystallization and can be grown on large-area glass substrates. Even if the thickness is small, a uniform film can be formed.

[0317] Since the CAAC-OS film is formed using this model, the sputtered particles are distributed evenly across the film thickness. It is preferable that the sputtered particles are in the form of thick dices. In this case, the surface facing the substrate 620 may not be uniform, and the thickness and crystal orientation may not be uniform. be.

[0318] The film formation model shown above allows for highly crystalline films to be formed even on a surface with an amorphous structure. Therefore, a CAAC-OS having the desired properties can be obtained.

[0319] In addition to pellet 600, CAAC-OS also has a coating model with zinc oxide particles. This can also be explained.

[0320] The zinc oxide particles have a smaller mass than the pellets 600 and therefore reach the substrate 620 first. On the upper surface of the substrate 620, zinc oxide particles grow preferentially in the horizontal direction. A thin zinc oxide layer is formed. The zinc oxide layer has a c-axis orientation. The c-axis of the crystal is oriented parallel to the normal vector of the substrate 620. The CAAC-OS crystallinity was improved by acting as a seed layer for the growth of AC-OS. The zinc oxide layer has a thickness of 0.1 nm or more and 5 nm or less, and The zinc oxide layer is thin enough that the grain boundaries are barely visible. It cannot be recognized.

[0321] Therefore, in order to form a CAAC-OS film with high crystallinity, it is necessary to use a composition other than the stoichiometric composition. It is preferred to use a target containing a high percentage of zinc.

[0322] Similarly, the nc-OS can be understood by the film formation model shown in FIG. The only difference between FIG. 47 and FIG. 46(A) is whether or not the substrate 620 is heated.

[0323] Therefore, the substrate 620 is not heated, and friction between the pellet 600 and the substrate 620 occurs. As a result, the pellet 600 is in a state where the resistance to friction and the like is large. Since it cannot glide across the surface, it accumulates irregularly. -OS can be obtained.

[0324] <cleavage plane> Below, we explain the cleavage plane of the target described in the CAAC-OS film formation model. Reveal.

[0325] First, the cleavage plane of the target will be explained using Figure 51. Figure 51 shows the cleavage plane of InGaZ The crystal structure of nO4 is shown in Figure 51(A). The c-axis is oriented upward and parallel to the b-axis. The structure of the InGaZnO4 crystal is shown when observed from the direction of the crystal. This shows the structure of an InGaZnO4 crystal when observed from a direction parallel to the axis.

[0326] The energy required for cleavage on each crystal plane of InGaZnO4 crystal was calculated using first-principles calculations. The calculation is performed using a pseudopotential and a density functional function using a plane wave basis. The pseudopotential used is an ultra-soft pseudopotential. The potential is used. The functional is GGA PBE. The cutoff The energy is set to 400 eV.

[0327] The energy of the structure in the initial state was derived after structural optimization including the cell size. In addition, the energy of the structure after cleavage on each plane is calculated by the atomic ratio with the cell size fixed. It is derived after structural optimization of the arrangement.

[0328] Based on the crystal structure of InGaZnO4 shown in Figure 51, the first plane, second plane, and third plane A structure cleaved at either the first or fourth plane was fabricated, and structural optimization calculations were performed with the cell size fixed. Here, the first plane is a crystal plane between the Ga-Zn-O layer and the In-O layer, and ( The second plane is a crystal plane parallel to the (001) plane (or ab plane) (see Figure 51(A)). , the crystal plane between the Ga-Zn-O layer and the Ga-Zn-O layer, and the (001) plane (or a The third plane is a crystal plane parallel to the (110) plane (see Figure 51(A)). The fourth plane is the (100) plane (or bc plane) (see Figure 51(B)). The crystal planes are parallel (see Figure 51(B)).

[0329] Under the above conditions, the energy of the structure after cleavage on each plane is calculated. Divide the difference between the energy of the structure and the energy of the structure in its initial state by the area of ​​the cleavage plane. The cleavage energy, which is a measure of the ease of cleavage on each plane, is calculated. The energy is the kinetic energy of the electrons and the interatomic and atomic energy for the atoms and electrons contained in the structure. This is the energy that takes into account interactions between electrons and between electrons.

[0330] As a result of calculations, the cleavage energy of the first facet is 2.60 J / m 2 , the cleavage energy of the second face -0.68J / m 2 , the cleavage energy of the third face is 2.18 J / m 2 , cleavage of the fourth plane Energy is 2.12J / m 2 It was found that (see table below).

[0331] [Table 3]

[0332] From this calculation, in the crystal structure of InGaZnO4 shown in Figure 51, The cleavage energy is lowest at the Ga-Zn-O layer and the Ga-Zn-O layer. It can be seen that the plane between the two is the plane (cleavage plane) that is easiest to cleave. When the term "cleavage plane" is used, it refers to the second plane, which is the plane that is easiest to cleave.

[0333] Since the cleavage plane is on the second plane between the Ga-Zn-O layers, The InGaZnO4 crystal shown in 51(A) is separated by a plane equivalent to the two second planes. Therefore, when ions or the like are bombarded with the target, the highest cleavage energy is obtained. The wafer-like units (we call them pellets) cleaved from the lower surface of the ghee are the best. In this case, the InGaZnO4 pellets The resulting layer is a Ga-Zn-O layer, an In-O layer, and a Ga-Zn-O layer.

[0334] The first plane (a crystal plane between the Ga-Zn-O layer and the In-O layer, which is the (001) plane) (or ab plane)), the third plane (a crystal plane parallel to the (110) plane), The cleavage energy of the fourth plane (a crystal plane parallel to the (100) plane (or bc plane)) is low. This suggests that the planar shape of the pellets is often triangular or hexagonal.

[0335] Next, classical molecular dynamics calculations were performed to identify the target InGa Assuming a ZnO4 crystal, the target is sintered with argon (Ar) or oxygen (O). The cleavage plane of the InGaZnO4 crystal (26 The cross-sectional structure of the 88 atoms is shown in FIG. 52(A), and the top view structure is shown in FIG. 52(B). The fixed layer shown in (A) is a layer in which the atomic arrangement is fixed so that the position does not fluctuate. The temperature control layer shown at 52(A) is a layer that is always kept at a constant temperature (300K).

[0336] For classical molecular dynamics calculations, Fujitsu Materials Explorer 5 was used. .0 is used. The initial temperature is 300K, the cell size is constant, and the time step width is 0.01f. The calculation assumes that the number of steps is 10 million femtoseconds. eV of energy is applied, and atoms are introduced into the cell from a direction perpendicular to the ab plane of the InGaZnO4 crystal. is incident.

[0337] FIG. 53(A) shows the state in which argon is introduced into the cell having the InGaZnO4 crystal shown in FIG. Figure 53(B) shows the atomic arrangement 99.9 picoseconds (psec) after irradiation. The atomic arrangement shown in Figure 53 is 99.9 picoseconds after oxygen is incident on the electron beam. A part of the fixed layer shown in (A) is omitted.

[0338] From Figure 53(A), within 99.9 picoseconds after argon entered the cell, ) the cracks occur from the cleavage plane corresponding to the second plane shown in Fig. 1. Therefore, InGaZnO4 When argon collides with the crystal, if the top surface is the second surface (0th), It can be seen that a large crack occurs in the second

[0339] On the other hand, from Figure 53(B), within 99.9 picoseconds after oxygen entered the cell, the It can be seen that cracks occur from the cleavage plane corresponding to the second plane shown in A). In the event of a collision, a large crack will occur on the second (first) surface of the InGaZnO4 crystal. You can see that this is happening.

[0340] Therefore, the top surface of the target containing InGaZnO4 crystals with a homologous structure When atoms (ions) collide from the surface, the InGaZnO4 crystal cleaves along the second plane, It can be seen that flat particles (pellets) are peeled off. At this time, the size of the pellets It was found that the collision with oxygen was smaller than that with argon. Light.

[0341] The above calculations suggest that the detached pellet contains a damaged area. Damaged regions in the matrix can be repaired by reacting oxygen with the defects caused by the damage. There are cases where this happens.

[0342] Therefore, we investigated whether the pellet size differs depending on the atom that is collided. do.

[0343] In FIG. 54(A), argon is introduced into the cell having the InGaZnO4 crystal shown in FIG. The trajectory of each atom is shown from 0 picoseconds to 0.3 picoseconds after irradiation. 54(A) corresponds to the period between FIG. 52 and FIG. 53(A).

[0344] As shown in Figure 54(A), argon collides with gallium (Ga) in the first layer (Ga-Zn-O layer). Then, after the gallium collides with the zinc (Zn) in the third layer (Ga-Zn-O layer), It can be seen that zinc reaches the vicinity of the sixth layer (Ga-Zn-O layer). The colliding argon is repelled outwards. Therefore, the crystals containing InGaZnO4 When argon is bombarded onto the target, a turtle appears on the second surface (second) in Figure 52(A). It is thought that cracks will occur.

[0345] Also, in FIG. 54(B), oxygen is added to the cell having the InGaZnO4 crystal shown in FIG. The trajectory of each atom from 0 picoseconds to 0.3 picoseconds after injection is shown. Therefore, FIG. 54(B) corresponds to the period between FIG. 52 and FIG. 53(A).

[0346] On the other hand, as shown in Figure 54(B), oxygen collides with gallium (Ga) in the first layer (Ga-Zn-O layer). When the gallium collides with the zinc (Zn) in the third layer (Ga-Zn-O layer), It can be seen that the zinc does not reach the fifth layer (In-O layer). Oxygen is expelled outwards. Therefore, for a target containing InGaZnO4 crystals, When oxygen is bombarded, it is thought that cracks will appear on the second surface (first surface) in Figure 52(A). can be.

[0347] From this calculation, it is clear that when atoms (ions) collide with InGaZnO4 crystals, the cleavage plane It is suggested that the tissue peels off.

[0348] In addition, we consider the difference in crack depth from the viewpoint of conservation laws. The conservation laws can be expressed as Equations 4 and 5, where E is the Argo The energy of ion or oxygen (300 eV), m A is the mass of argon or oxygen, v A is the velocity of argon or oxygen before the collision, v' A is the velocity of argon or oxygen after the collision, m Ga is the mass of gallium, v Ga is the velocity of gallium before the collision, v' Ga is the gallium after the collision is the speed.

[0349]

number

[0350]

number

[0351] Assuming that the collisions of argon or oxygen are elastic, v A , v' A , v Ga Oh ビv' Ga The relationship can be expressed as in Equation 6.

[0352]

number

[0353] From Equation 4, Equation 5 and Equation 6, v Ga If argon or oxygen collides, The velocity of gallium after the Ga can be expressed as in Equation 7.

[0354]

number

[0355] In Equation 7, m A Substitute the mass of argon or the mass of oxygen into Compare the velocity of gallium after the collision. The energy of argon and oxygen before the collision When the ratio is the same, the collision with argon is 1.24 times greater than the collision with oxygen. Therefore, the energy of gallium is also higher than that of Argon. When an electron collides with an electron, the velocity is higher by the square of the velocity than when an oxygen collides with an electron.

[0356] When argon is bombarded, the gallium after the bombardment is more dense than when oxygen is bombarded. Therefore, when argon is collided, It is thought that cracks occurred at deeper positions in the case of oxygen bombardment than in the case of oxygen bombardment.

[0357] From the above calculations, it is possible to obtain a target containing InGaZnO4 crystals with a homologous structure. When sputtered, it peels off from the cleaved surface and forms a pellet. Sputtering other structural areas of the target that do not have a surface does not result in pellet formation. The sputtered particles are formed in an atomic level, which are smaller than the particles. Because it is smaller than a pellet, it can be easily removed by a vacuum pump connected to the sputtering equipment. Therefore, the crystal structure of InGaZnO4 with homologous structure When a target containing argon is sputtered, particles of various sizes and shapes fly to the substrate and accumulate. It is difficult to imagine a model in which a film is formed by deposition of sputtered pellets. The model shown in Figure 46(A) for forming a C-OS film is reasonable.

[0358] The density of the CAAC-OS film formed in this way is comparable to that of single-crystal OS. For example, the density of a single crystal OS with a homologous structure of InGaZnO4 is 6.36g. / cm 3 In contrast, the density of CAAC-OS, which has a similar atomic ratio, is 6.3 g / c m 3 It will be about that amount.

[0359] Figure 55 shows the In-Ga-Zn oxide (CAAC-OS) film formed by sputtering. (See Figure 55(A)) and the cross section of the target (See Figure 55(B)). The atomic arrangement is shown. The atomic arrangement was observed using high-angle annular dark-field scanning transmission electron microscopy (HAEC). ADF-STEM:High-Angle Annular Dark Field S canning Transmission Electron Microscopy In HAADF-STEM, the image intensity of each atom is proportional to the square of the atomic number. Therefore, Zn (atomic number 30) and Ga (atomic number 31) have similar atomic numbers. The HAADF-STEM uses a Hitachi HD-27 scanning transmission electron microscope. Use 00.

[0360] Comparing Figure 55(A) and Figure 55(B), the CAAC-OS and the target are Both have homologous structures, and it can be seen that the arrangement of their atoms corresponds to each other. Therefore, as shown in the film formation model in Figure 46(A), the crystal structure of the target is The image shows that a CAAC-OS film has been formed.

[0361] (Fourth embodiment) In this embodiment, one embodiment of a light-emitting device using a semiconductor device according to one embodiment of the present invention will be described. In this embodiment, the structure of the pixel portion of the light emitting device will be explained. B) will be used to explain.

[0362] In FIG. 25A, a plurality of FETs 500 are formed on a first substrate 502, and each F The ET500 is electrically connected to each light emitting element (504R, 504G, 504B, 504W). Specifically, the first conductive film 506 of each FET 500 and the light emitting element is electrically connected to the first conductive film 506. Each light emitting element (504R, 504G, 504B, 504W) is , the first conductive film 506, the second conductive film 507, the EL layer 510, and the third conductive film 512. Therefore, it is composed.

[0363] Also, at positions facing each light emitting element (504R, 504G, 504B, 504W), Each of the color layers (514R, 514G, 514B, 514W) is provided. The color layers (514R, 514G, 514B, 514W) are in contact with the second substrate 516. A sealing film 518 is provided between the first substrate 502 and the second substrate 516. The sealing film 518 is made of, for example, a glass material such as glass frit, Hardening resins that harden at room temperature, such as two-component mixed resins, photo-hardening resins, thermosetting resins, etc. The resin material can be used.

[0364] In addition, the partition wall 5 is formed so as to cover the ends of the first conductive film 506 and the second conductive film 507 adjacent to each other. A structure 509 is provided on the partition wall 508. The first conductive film 506 functions as a reflective electrode and as an anode of the light-emitting element. The second conductive film 507 has a function of adjusting the optical path length of each light-emitting element. An EL layer 510 is formed on the second conductive film 507, and a third The third conductive film 512 is formed as a semi-transmissive and semi-reflective electrode. The structure 509 functions as a light-emitting element and a cathode of the light-emitting element. It is provided between the colored layers and functions as a spacer.

[0365] In addition, the EL layer 510 is formed by the respective light-emitting elements (504R, 504G, 504B, 504 W). , 504W) are formed by the first conductive film 506 and the third conductive film 512 from the EL layer 510. It has a micro-optical resonator (also called a microcavity) structure that resonates light emission, and Even with the EL layer 510, it is possible to narrow the spectrum of light of different wavelengths and extract it. Specifically, each of the light-emitting elements (504R, 504G, 504B, 504W) has an EL layer By adjusting the film thickness of the second conductive film 507 provided below 510, The spectrum obtained from the EL layer 510 is set to the desired emission spectrum, and light emission with good color purity is obtained. Therefore, by using the structure shown in FIG. 25(A), the coating of the EL layer can be This eliminates the need for a separation process, making it easier to achieve high definition.

[0366] The light-emitting device shown in FIG. 25(A) has a colored layer (color filter). Therefore, by combining the microcavity structure with a color filter, the color purity can be further improved. Specifically, the light emitting element 504R emits red light. The optical path length of the light emitting element is adjusted so that red light passes through the colored layer 514R in the direction of the arrow. The light emitting element 504G emits light of a green color. The path length is adjusted, and green light is emitted in the direction of the arrow through the colored layer 514G. In addition, the light path length of the light emitting element 504B is adjusted so that blue light can be emitted. Blue light is emitted in the direction of the arrow through the colored layer 514B. The optical path length of the light emitting element is adjusted to obtain white light, and the light passes through the colored layer 514W. White light is emitted in the direction of the arrow.

[0367] The method for adjusting the optical path length of each light-emitting element is not limited to this. In the optical element, the optical path length may be adjusted by adjusting the film thickness of the EL layer 510.

[0368] The colored layers (514R, 514G, 514B) transmit light in a specific wavelength range. For example, a red (R) color filter that transmits light in the red wavelength band may be used. -filter, green (G) color filter that transmits light in the green wavelength band, blue wave A blue (B) color filter that transmits long-band light can be used. For example, an acrylic resin material that does not contain a pigment may be used as the coloring layer 514W. Various materials can be used for the colored layers (514R, 514G, 514B, 514W). Printing, inkjet printing, etching using photolithography technology, etc. It can be formed.

[0369] The first conductive film 506 is, for example, a film with high reflectivity (visible light reflectivity of 40% or more). A metal film having a film thickness of 0.00% or less, preferably 70% to 100% can be used. The conductive film 506 is made of aluminum, silver, or an alloy containing these metal materials (for example, For example, an alloy of silver, palladium, and copper) can be formed as a single layer or a multilayer.

[0370] The second conductive film 507 may be formed using, for example, a conductive metal oxide. Conductive metal oxides include indium oxide, tin oxide, zinc oxide, and indium Indium tin oxide (also known as ITO), indium zinc Lead oxide (Indium Zinc Oxide), or these metal oxide materials with acid The second conductive film 50 may contain silicon oxide or tungsten oxide. 7, a thin film is formed between the EL layer 510 to be formed later and the first conductive film 506. This is advantageous because it can suppress the formation of an insulating film formed on the first conductive film 50. A conductive metal oxide film used as a second conductive film 507 may be formed below the layer 6 .

[0371] The third conductive film 512 is made of a conductive material having a reflectivity and a conductive material having a light-transmitting property. and the reflectance of visible light is 20% or more and 80% or less, preferably 40% or more. The third conductive film 512 is preferably made of, for example, silver, magnesium, or the like. or an alloy containing these metal materials is formed thinly (for example, 10 nm or less), and After that, a conductive metal oxide that can be used for the second conductive film 507 may be formed.

[0372] In the configuration described above, the structure in which light is extracted to the second substrate 516 side (top electrode) is used. The light emitting device has a mission structure, and the first substrate 501 on which the FET 500 is formed is a structure in which light is extracted from the first substrate 501 side (bottom emission structure), or a structure in which light is extracted from the first substrate 501 side and the second substrate 502 side The light emitting device has a structure (dual emission structure) in which light is extracted from both sides of the substrate 516. In the case of a bottom emission structure, for example, the colored layers (514R, 514G, 51 4B, 514W) may be formed below the first conductive film 506. A light-transmitting substrate may be used for the substrate on the light-emitting side, and a transparent substrate may be used for the substrate on the non-light-emitting side. Both light-transmitting and light-shielding substrates can be used.

[0373] In addition, in FIG. 25(A), the light emitting element has four colors (red (R), green (G), blue (B), and white However, the present invention is not limited to this. For example, if the light emitting element has three colors (red, red, (R), green (G), and blue (B).

[0374] Here, the connection relationship between each light emitting element and each FET will be described in detail with reference to FIG. 25(B). Note that FIG. 25(B) shows one example of the configuration of the area 520 surrounded by the dashed line shown in FIG. 25(A). Here is an example.

[0375] In FIG. 25(B), an insulating film 522 that functions as a planarizing film is formed on the FET 500. The insulating film 522 is provided with a source electrode or a drain electrode of the FET 500. An opening 524 is formed on the insulating film 522, reaching the conductive film. A first conductive film is connected to the conductive film that functions as the source electrode or the drain electrode of the ET500. A conductive film 506 is formed on the first conductive film 506. A second conductive film 507 is formed on the first conductive film 506. It is formed.

[0376] The FET 500 has the same configuration as the transistor 150 shown in the previous embodiment. Therefore, the description here will be omitted.

[0377] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. You can be there.

[0378] (Embodiment 5) In this embodiment, the transistor and the capacitor described in the previous embodiment are used. An example of such a display device will be described below with reference to FIGS. 26 to 28. FIG.

[0379] 26 is a top view showing an example of a display device. The display device 700 shown in FIG. A pixel portion 702 is provided on the first substrate 701, and a source driver 703 is provided on the second substrate 701. The pixel section 702, the source driver circuit section 704, the gate driver circuit section 706, a sealant 712 disposed to surround the path portion 704 and the gate driver circuit portion 706; and a second substrate 705 provided so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are The first substrate 701, the sealant 712, and the second substrate 705 seal the entire structure. Although not shown in FIG. 26, a display element is provided between the first substrate 701 and the second substrate 705. It can be done.

[0380] The display device 700 is surrounded by a sealant 712 on the first substrate 701. The pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are arranged in a region different from the region. The flexible printed circuit (FPC) terminal 708 is electrically connected to the flexible printed circuit (FPC) circuit 706. In addition, the FPC terminal section 708 is provided with an FP The pixel section 702 and the source driver circuit section 704 are connected by the FPC 716. Various signals are supplied to the pixel portion 702, the gate driver circuit portion 706, and the like. The base driver circuit section 704, the gate driver circuit section 706, and the FPC terminal section 708 are , and signal lines 710 are connected to the FPC 716. The pixel section 702, the source driver circuit section 704, the gate driver circuit section 706, and the like are connected via a line 710. 706 and an FPC terminal portion 708.

[0381] Furthermore, the display device 700 may be provided with a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example in which the pixel portion 702 is formed on the same first substrate 701 is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit etc. is formed (for example, A driving circuit board formed of a monocrystalline semiconductor film or a polycrystalline semiconductor film is mounted on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited. Instead of COG (Chip On Glass) method, wire bonding method, etc. can be used.

[0382] The display device 700 also includes a pixel section 702, a source driver circuit section 704, and a gate The driver circuit portion 706 includes a plurality of transistors. In addition, in the pixel portion 702, a transistor A transistor and a capacitor which are one embodiment of the semiconductor device can be applied.

[0383] The display device 700 can also include various elements, such as liquid crystal Elements, EL (electroluminescence) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs) transistors (transistors that emit light according to the current), electron emitters, electron insulators Electrophoretic element, Grating light valve (GLV), Plasma display (P Display elements using DP, MEMS (microelectromechanical systems), Digital Micromirror Device (DMD), DMS (Digital Micro Shutter) ), MIRASOL (registered trademark), IMOD (Interference Modulation ) element, shutter type MEMS display element, optical interference type MEMS display element, elect Low-wetting element, piezoelectric ceramic display, display using carbon nanotubes In addition to these, it has at least one of an electric or magnetic function. The display medium may have a contrast, brightness, reflectance, transmittance, etc. that change depending on the display device. An example of a display device using an EL element is an EL display. An example of a display device using electrons is a field emission display (FED). or SED type flat panel display (SED: Surface-conduction LCDs are liquid crystal displays. An example of a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display). Spray, reflective LCD, direct-view LCD, projection LCD An example of a display device using electronic ink or electrophoretic elements is an electronic pen. In addition, there are also other LCDs that can be used to realize semi-transmissive LCDs and reflective LCDs. In this case, a part or all of the pixel electrodes should function as a reflective electrode. For example, a part or the whole of the pixel electrode may contain aluminum, silver, etc. Furthermore, in this case, a memory circuit such as an SRAM may be provided under the reflective electrode. This makes it possible to further reduce power consumption.

[0384] The display method of the display device 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying colors include R It is not limited to the three colors GB (R stands for red, G stands for green, B stands for blue). For example, It may be composed of four pixels: a pixel, a B pixel, and a W (white) pixel. Like the column, two colors of RGB make up one color element, and two different colors are created by the color element. Alternatively, you can select one or more colors such as yellow, cyan, magenta, etc. for RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, but also to monochrome display devices. The present invention can also be applied to display devices such as those shown in the accompanying drawings.

[0385] In this embodiment, a liquid crystal element and an EL element are used as display elements. 27 and 28. Note that FIG. 27 shows the area indicated by the dashed line QR in FIG. 28 is a cross-sectional view of the display device, which uses a liquid crystal element as the display element. 26, a cross-sectional view taken along the dashed line QR, and a configuration in which an EL element is used as a display element. is.

[0386] First, the common parts shown in Figures 27 and 28 will be explained, and then the different parts will be explained. This will be explained below.

[0387] <Explanation of common parts of display devices> The display device 700 shown in FIGS. 27 and 28 includes a wiring portion 711, a pixel portion 702, and a , a source driver circuit section 704, and an FPC terminal section 708. The line portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and The source driver circuit portion 704 includes a transistor 752. Has.

[0388] Transistor 750 and transistor 752 are similar to transistor 150 shown above. The structures of the transistors 750 and 752 are the same as those described above. Any of the other transistors shown in the embodiment modes may be used.

[0389] The transistor used in this embodiment is made of a highly purified oxide in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The transistor has a low current value in an off state (off-state current value). Therefore, the retention time of the electric signals such as the image signals can be extended, and the power supply When it is on, the write interval can be set longer. Therefore, the frequency of refresh operations can be reduced. This has the effect of reducing power consumption.

[0390] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed driving can be used in a liquid crystal display. By using this in a display device, the switching transistor in the pixel section and the driver circuit section can be In other words, the driver transistor can be formed on the same substrate as a separate driver circuit. Therefore, it is not necessary to use a semiconductor device formed from a silicon wafer or the like. The number of components can be reduced. By using a register, high quality images can be provided.

[0391] The capacitor 790 has the same configuration as the capacitor 160 shown above.

[0392] 27 and 28, the transistor 750, the transistor 752, and the capacitor An insulating film 766 and a planarizing insulating film 770 are provided on the capacitor 790 .

[0393] The insulating film 766 can be formed using a material and a method similar to those of the insulating film 128 described in the above embodiment. The planarization insulating film 770 can be formed by a method. Acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, epoxy Heat-resistant organic materials such as epoxy resins can be used. The planarization insulating film 770 may be formed by stacking a plurality of insulating films. The planarizing insulating film 770 may not be provided.

[0394] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed in the same process as the conductive film that functions as the transistor 75. 0, 752 source electrode and drain electrode, for example, a conductive film formed in a different process A conductive film that functions as the first gate electrode or a conductive film that functions as the second gate electrode is used. For example, when a material containing copper is used for the signal line 710, the wiring resistance There is little signal delay, etc., which makes it possible to display on a large screen.

[0395] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 71. 6. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed in the same process as the conductive film that functions as the drain electrode. The terminal of the PC 716 is electrically connected via an anisotropic conductive film 780 .

[0396] The first substrate 701 and the second substrate 705 may be made of, for example, glass. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. do.

[0397] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film. The distance (cell gap) between the first substrate 701 and the second substrate 705 is controlled. It should be noted that the structures 778 may be spherical spacers.

[0398] On the second substrate 705 side, there is a light-shielding film 738 that functions as a black matrix, A colored film 736 that functions as a color filter, a light-shielding film 738, and a film that contacts the colored film 736 An insulating film 734 is provided.

[0399] <Configuration example of a display device using a liquid crystal element as a display element> The display device 700 shown in FIG. 27 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film The conductive film 774 is formed on the second substrate 705. The display device 700 shown in FIG. The alignment state of the liquid crystal layer 776 changes depending on the voltage applied to the conductive film 772 and the conductive film 774. This controls whether light is transmitted or not, allowing images to be displayed.

[0400] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is connected to a conductive film that functions as a pixel electrode. The conductive film 772 functions as a reflective electrode, that is, one of the electrodes of the display element. The display device 700 shown in FIG. 27 uses external light and emits light through a conductive film 772. and displays the reflected light through the colored film 736, which is a so-called reflective color liquid crystal display device.

[0401] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a light-transmitting property in visible light can be used. For example, a material containing one of the elements selected from indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum In this embodiment, the conductive film 772 may be formed using a material containing silver or silver. A conductive film that is reflective in visible light is used.

[0402] In the display device 700 shown in FIG. 27, the planarization insulating film 770 of the pixel section 702 The unevenness is formed in a part of the insulating film 770 by, for example, forming the planarization insulating film 770 with an organic resin film or the like. The reflection current can be formed by forming a film on the surface of the organic resin film and providing irregularities on the surface of the organic resin film. The conductive film 772 that functions as an electrode is formed along the above-mentioned unevenness. When light is incident on the conductive film 772, it is possible for the light to be diffused on the surface of the conductive film 772. This makes it possible to improve visibility.

[0403] The display device 700 shown in FIG. 27 is a reflective color liquid crystal display device. However, the conductive film 772 is not limited to this. For example, the conductive film 772 may be a conductive film that transmits visible light. A transmissive color liquid crystal display device may be formed by using the above. In this case, the unevenness provided in the planarization insulating film 770 does not necessarily have to be provided.

[0404] Although not shown in FIG. 27, the conductive films 772 and 774 are in contact with the liquid crystal layer 776. Although not shown in FIG. Optical members (optical substrates) such as optical members, phase difference members, and anti-reflection members may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. Critters, sidelights, etc. may also be used.

[0405] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, The liquid crystals that can be used include polymer dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, the liquid crystal material can be in a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0406] In addition, when the in-plane switching method is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. Therefore, in order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is used in a liquid crystal layer. It has a short response time, is optically isotropic so alignment treatment is not required, and has little viewing angle dependency. In addition, since there is no need to provide an alignment film, rubbing treatment is also unnecessary. Therefore, it is possible to prevent electrostatic breakdown caused by the electrostatic discharge, and to prevent defects in the liquid crystal display device during the manufacturing process. Damage can be reduced.

[0407] When a liquid crystal element is used as a display element, a TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero) lectric Liquid Crystal) mode, AFLC (AntiFerr It can be used in dielectric liquid crystal mode. .

[0408] In addition, normally black type liquid crystal display devices, for example, those employing vertical alignment (VA) mode The liquid crystal display device may be a transmission type. For example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode , ASV mode, etc. can be used.

[0409] <Display device using light-emitting elements as display elements> The display device 700 shown in FIG. 28 includes a light-emitting element 782. The light-emitting element 782 includes a conductive film 28 includes a light-emitting layer 784, an EL layer 786, and a conductive film 788. The EL layer 786 of the light element 782 emits light, thereby displaying an image. do.

[0410] The conductive film 784 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is connected to a conductive film that functions as a pixel electrode. The conductive film 784 functions as an electrode, that is, one electrode of the display element. In this case, a conductive film that is light-transmitting or a conductive film that is reflective to visible light can be used. Examples of conductive films that are transparent to visible light include indium (In) and zinc (Zn). It is recommended to use a material containing one of the following elements: (Zn) and tin (Sn). As the reflective conductive film, for example, a material containing aluminum or silver is preferably used. stomach.

[0411] 28, the display device 700 has an insulating film over the planarization insulating film 770 and the conductive film 784. An insulating film 730 is provided. The insulating film 730 covers part of the conductive film 784. 782 has a top emission structure. Therefore, the conductive film 788 has a light transmitting property, and It transmits light emitted by the L layer 786. In this embodiment, the top emission The structure is exemplified, but is not limited to, for example, a bottom emission structure in which light is emitted to both the conductive film 784 and the conductive film 788; It can also be applied to al-emission structures.

[0412] A colored film 736 is provided at a position overlapping the light-emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided in the position where the light-shielding film 738 is to be drawn, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is exemplified. For example, when the EL layer 786 is formed by coloring, The film 736 may not be provided.

[0413] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0414] (Embodiment 6) In this embodiment, a structural example of a display device according to one embodiment of the present invention will be described.

[0415] [Configuration example] FIG. 36A is a top view of a display device including a semiconductor device according to one embodiment of the present invention. FIG. 36B shows a pixel of a display device using a semiconductor device according to one embodiment of the present invention. 36(C) shows a pixel circuit in the case where a liquid crystal element is used. Pixel circuit when organic EL elements are used for pixels of a display device using the semiconductor device Show the way.

[0416] The transistor used in the pixel can be any of the above-described transistors. An example in which an n-channel transistor is used will be shown. A transistor manufactured through the same process may be used for a driver circuit. The transistors used as the driving circuit and the transistors used as the driving circuit may be separately manufactured. The transistors used in the driver circuits are the transistors described above, and the transistors used in the pixels are The single-gate transistor is not provided with the gate electrode 104a of the above-mentioned transistor. The capacitor element used in the pixel may be the capacitor element described above. In this way, by using the above-described transistors and capacitors in the pixel and driver circuit, This results in a display device with high display quality and / or high reliability.

[0417] An example of a top view of an active matrix display device is shown in FIG. On the plate 5000, a pixel section 5001, a first scanning line driving circuit 5002, a second scanning line driving circuit 5003, a A pixel portion 5001 includes a signal line driver circuit 5003 and a signal line driver circuit 5004. 5004, and the first scanning line is electrically connected to the signal line driver circuit 5004 by a plurality of scanning lines. The first scanning line driver circuit 5002 and the second scanning line driver circuit 5003 are electrically connected to each other. In the areas separated by the scanning lines and the signal lines, pixels each having a display element are arranged. The substrate 5000 of the display device is made of an FPC (Flexible Printed Circuit). d Circuit) and other connections, C).

[0418] The first scanning line driver circuit 5002, the second scanning line driver circuit 5003, and the signal line driver circuit 5 004 is formed on the same substrate 5000 as the pixel portion 5001. The cost of manufacturing the display device can be reduced compared to when the display device is manufactured by using a drive circuit. If a separate operating circuit is created, the number of connections between the wiring will increase. By providing a driver circuit in the and / or improve yield.

[0419] [Liquid crystal display device] An example of the circuit configuration of a pixel is shown in Figure 36(B). 1 shows a pixel circuit that can be applied to a pixel or the like.

[0420] This pixel circuit can be applied to a configuration in which one pixel has a plurality of pixel electrodes. The pixel electrodes are connected to different transistors, and each transistor can be driven by a different gate signal. This allows the individual pixel voltages of the multi-domain designed pixels to be The signals applied to the poles can be controlled independently.

[0421] The gate wiring 5012 of the transistor 5016 and the gate wiring 5017 of the transistor 5017 013 are separated so that different gate signals can be applied. The source or drain electrode 5014, which functions as a data line, is connected to the transistor 5016. It is commonly used with transistor 5017. The above-described transistors can be used as appropriate for the capacitor 5023 and the The above-described capacitors can be used as appropriate for the capacitor 5029. Therefore, it is possible to provide a liquid crystal display device with high quality and / or high reliability.

[0422] a first pixel electrode electrically connected to the transistor 5016; The shape of the second pixel electrode that is electrically connected to the first pixel electrode and the second pixel electrode will be described. The electrodes are separated by slits. The first pixel electrode has a V-shaped configuration. The second pixel electrode is formed so as to surround the outside of the first pixel electrode.

[0423] The gate electrode of the transistor 5016 is electrically connected to the gate wiring 5012. The gate electrode of the transistor 5017 is electrically connected to the gate wiring 5013. Different gate signals are applied to the line 5012 and the gate wiring 5013, and the transistor 5016 and the transistor The alignment of the liquid crystal can be controlled by varying the operation timing of the transistor 5017.

[0424] Also, the capacitor wiring 5010, the gate insulator acting as a dielectric, and the first pixel electrode Alternatively, a capacitance element may be formed by a capacitance electrode electrically connected to the second pixel electrode.

[0425] The multi-domain structure has a first liquid crystal element 5018 and a second liquid crystal element 5019 in one pixel. The first liquid crystal element 5018 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween. The second liquid crystal element 5019 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween. can be.

[0426] Note that the display device according to one embodiment of the present invention is not limited to the pixel circuit shown in FIG. For example, if a switch, a resistor, a capacitor, a transistor, etc. are newly added to the pixel shown in FIG. 36(B), Additional components such as sensors, logic circuits, etc. may be added.

[0427] [Light-emitting device] Another example of the circuit configuration of a pixel is shown in Figure 36(C). 1 shows a pixel structure of a display device (also referred to as a light-emitting device) using a light-emitting element.

[0428] When a voltage is applied to the light-emitting element, the organic EL element Electrons are injected from one electrode and holes are injected from the other electrode into a layer containing a light-emitting organic compound. When electrons and holes recombine, a light-emitting organic compound An excited state is formed, and light is emitted when the excited state returns to the ground state. Therefore, such a light-emitting element is called a current-excited light-emitting element.

[0429] FIG. 36(C) is a diagram showing an example of a pixel circuit. Here, one pixel has an n-channel type An example using two n-channel transistors and one capacitor is shown. The transistor can be the transistor described above. In addition, the pixel circuit is suitable for digital time gray scale driving. It can be used.

[0430] Regarding the configuration of applicable pixel circuits and pixel operation when digital time gray scale driving is applied, and explain.

[0431] The pixel 5020 includes a switching transistor 5021 and a driving transistor 5022. The switching transistor 502 includes a light-emitting element 5024 and a capacitor 5023. 1, the gate electrode is connected to the scanning line 5026, and the first electrode (the source electrode, the drain electrode) The first electrode (the other of the source and drain electrodes) is connected to a signal line 5025, and the second electrode (the other of the source and drain electrodes) is connected to a drive The gate electrode of the driving transistor 5022 is connected to the gate electrode of the driving transistor 5022. The gate electrode is connected to a power supply line 5027 via a capacitor element 5023, and the first electrode is connected to a power supply line 5026. The second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 5024. The second electrode of the light emitting element 5024 corresponds to the common electrode 5028. are electrically connected to a common potential line formed on the same substrate.

[0432] The switching transistor 5021 and the driving transistor 5022 are the transistors described above. In addition, the above-described capacitor can be used as the capacitor 5023. This makes it possible to provide an organic EL display device with high display quality and / or high reliability. This becomes:

[0433] The potential of the second electrode (common electrode 5028) of the light emitting element 5024 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 5027. For example, GND, 0V, or the like can be set as the low power supply potential. The high and low power supply potentials are set so that they are equal to or greater than the threshold voltage in the direction of the By applying a voltage to the element 5024, a current flows through the light emitting element 5024, causing it to emit light. The forward voltage of the light emitting element 5024 refers to the voltage required to achieve a desired luminance. At least the forward threshold voltage.

[0434] The capacitor 5023 is substituted for the gate capacitance of the driving transistor 5022. The gate capacitance of the driving transistor 5022 can be reduced by A capacitance may be formed between the channel forming region and the gate electrode.

[0435] Next, a signal input to the driving transistor 5022 will be described. In the case of the driving method, the driving transistor 5022 is in two states, on or off. A video signal is input to the driving transistor 5022. In order to operate the inverter 22 in the linear region, a voltage higher than the voltage of the power supply line 5027 is applied to the driving transistor. The signal line 5025 is supplied to the gate electrode of the transistor 5022. A voltage equal to or greater than the threshold voltage Vth of the power transistor 5022 is applied.

[0436] When analog gradation driving is performed, the gate electrode of the driving transistor 5022 is connected to the light emitting element 5 024 plus the threshold voltage Vth of the driving transistor 5022 or more In addition, the voltage of the video is applied so that the driving transistor 5022 operates in the saturation region. A signal is inputted to cause a current to flow through the light emitting element 5024. In addition, the driving transistor 5022 is saturated. In order to operate the driving transistor 5022 in the sum region, the potential of the power supply line 5027 is By converting the video signal into an analog signal, the light emitting element 5024 receives the video signal. A current corresponding to a signal is passed through the liquid crystal panel, enabling analog grayscale driving.

[0437] Note that a display device using a semiconductor device according to one embodiment of the present invention has a pixel structure shown in FIG. For example, the pixel circuit shown in FIG. Additional elements, sensors, transistors or logic circuits may be added.

[0438] For example, FIG. 37(A) is a diagram showing an example of a pixel circuit. Here, one pixel has n transistors. An example using three channel transistors and one capacitor will be shown.

[0439] FIG. 37A shows an example of a circuit diagram of a pixel 5111. The pixel 5111 includes a transistor 5155, a transistor 5156, a transistor 5157, a capacitor 5158, and a light-emitting element 5154.

[0440] The pixel electrode of the light emitting element 5154 is turned on in accordance with the image signal Sig input to the pixel 5111. The luminance of the light emitting element 5154 is controlled by the potential between the pixel electrode and the common electrode. It is determined by the difference.

[0441] The transistor 5156 is connected to the wiring SL and the gate of the transistor 5155. The transistor 5155 has a function of controlling the state of the transistor. The other of the source and drain is electrically connected to the wiring VL. The transistor 5157 is connected to the wiring ML and the The capacitor 5158 has a function of controlling the conduction state between the source and the drain. One of the pair of electrodes is electrically connected to the gate of the transistor 5155, and the other is It is electrically connected to the anode of element 5154.

[0442] Also, the switching of the transistor 5156 is performed by applying an electric current to the gate of the transistor 5156. The potential of the wiring GL connected to the transistor 5157 is controlled by the potential of the switch 5157. The switching is performed according to the potential of the wiring GL electrically connected to the gate of the transistor 5157. This is carried out.

[0443] In addition, the transistors 5155, 5156, and 5157 At least one of the above-described transistors can be used for the capacitor 515. The above-mentioned capacitance element can be used for 8.

[0444] Next, an example of the operation of the pixel 5111 shown in FIG. 37(A) will be described.

[0445] FIG. 37B shows the voltage of the wiring GL electrically connected to the pixel 5111 shown in FIG. 37A. 10 shows a timing chart of the potential of the image signal Sig supplied to the wiring SL. The timing chart shown in FIG. 37B is included in the pixel 5111 shown in FIG. This is an example in which all the transistors used are n-channel type.

[0446] First, in the period t1, a high-level potential is applied to the wiring GL. The transistor 5156 and the transistor 5157 are turned on. The potential Vdata of ig is given, and the potential Vdata is and applied to the gate of transistor 5155.

[0447] In addition, a potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. The potential Vano is the threshold voltage Vthe of the light emitting element 5154 and the transistor potential Vcat. It is preferable to set the potential higher than the threshold voltage Vth of the transistor 5155. By providing the above potential difference between VL and the wiring CL, The drain current of the transistor 5155 is determined by the above equation. is supplied to the light emitting element 5154, thereby determining the luminance of the light emitting element 5154.

[0448] In addition, when the transistor 5155 is an n-channel transistor, the voltage of the wiring ML is The potential is higher than the potential of the wiring CL plus the threshold voltage Vthe of the light emitting element 5154. The potential of the wiring VL is lower than the potential of the wiring ML by the threshold voltage Vth of the transistor 5155. With the above configuration, the transistor 5157 is turned on. Even if the transistor 5155 is connected to the wiring, the drain current of the transistor 5155 is not connected to the light emitting element 5154. Priority can be given to ML.

[0449] Next, in a period t2, a low-level potential is applied to the wiring GL. Transistor 5156 and transistor 5157 are turned off. Transistor 5156 is turned off. As a result, the potential Vdata is held at the gate of the transistor 5155. A potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. The light emitting element 5154 emits light at the luminance determined in the period t1.

[0450] Next, in a period t3, a high-level potential is applied to the wiring GL. The transistor 5156 and the transistor 5157 are turned on. A potential is applied such that the gate voltage of 5155 becomes greater than the threshold voltage Vth. A potential Vcat is applied to the wiring CL. The potential of the wiring ML is The potential becomes lower than the potential obtained by adding the threshold voltage Vthe of the light emitting element 5154 to the potential of the wiring V The potential of L is the potential of the wiring ML plus the threshold voltage Vth of the transistor 5155. With the above configuration, the drain current of the transistor 5155 is It is possible to give priority to wiring ML rather than 5154.

[0451] The drain current of the transistor 5155 is supplied to the monitor circuit via the wiring ML. The monitor circuit uses the drain current flowing through the wiring ML to measure the drain current. Then, a signal including the value of the signal is generated using a semiconductor device according to one embodiment of the present invention. In the light emitting device, the potential V of the image signal Sig supplied to the pixel 5111 is adjusted by using the signal. The data value can be corrected.

[0452] In the light-emitting device having the pixel 5111 shown in FIG. 37A, after the operation in the period t2, For example, in the pixel 5111, the operation in the period t1 to the period t2 may not be performed. The operation of the period t2 may be repeated several times, and then the operation of the period t3 may be performed. After the operation for the period t3 is performed in the pixel 5111 of the row, the image signal corresponding to the minimum gradation value 0 is output. By writing a signal to the pixels 5111 of one row where the operation has been performed, the light emitting element 5154 is made to emit no light. After the pixel 5111 in the next row is set to the light state, the operation for the period t3 is performed. good.

[0453] Also, for example, FIG. 38(A) is a diagram showing an example of a pixel circuit. An example in which four n-channel transistors and one capacitor are used is shown.

[0454] FIG. 38A shows an example of a circuit diagram of a pixel 5211. The pixel 5211 includes a transistor 5215, a transistor 5216, a transistor 5217, and a capacitor 5218, It includes a light-emitting element 5214 and a transistor 5219 .

[0455] The pixel electrode of the light emitting element 5214 is turned on in accordance with the image signal Sig input to the pixel 5211. The luminance of the light emitting element 5214 is controlled by the potential between the pixel electrode and the common electrode. It is determined by the difference.

[0456] The transistor 5219 is connected to the wiring SL and the gate of the transistor 5215. The transistor 5215 has a function of controlling the state of the transistor. The transistor 5216 is electrically connected to the anode of the photoelement 5214. , the function of controlling the conduction state between the other of the source and drain of the transistor 5215. The transistor 5217 is connected to the wiring ML and the source and drain of the transistor 5215. The capacitor 5218 has a function of controlling the conduction state between the pair of electrodes. One of them is electrically connected to the gate of the transistor 5215, and the other is electrically connected to the gate of the light-emitting element 521 4 anode.

[0457] Also, the switching of the transistor 5219 is performed by applying an electric current to the gate of the transistor 5219. The switching of the transistor 5216 is performed according to the potential of the wiring GLa which is electrically connected to the transistor 5216. The potential of the wiring GLb electrically connected to the gate of the transistor 5216 is set to The switching of the transistor 5217 is performed by the gate of the transistor 5217. This is done according to the potential of the wiring GLc electrically connected to the gate.

[0458] The transistors 5215, 5216, 5217, and The above-described transistors can be used for at least one of the transistors 5219. The capacitor 5218 can be any of the capacitors described above.

[0459] Next, an example of the operation of external correction of the pixel 5211 shown in FIG. 38(A) will be described.

[0460] FIG. 38B shows a wiring GLa electrically connected to the pixel 5211 shown in FIG. 38A. The timing of the potential of the wiring GLb and the wiring GLc and the potential of the image signal Sig supplied to the wiring SL The timing chart shown in FIG. 38(B) is the same as that shown in FIG. 38(A). ) is an example in which all transistors included in the pixel 5211 shown in FIG. It is something.

[0461] First, in a period t1, a high-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A high level potential is applied to the wiring GLc, and a low level potential is applied to the wiring GLd. Transistor 5219 and transistor 5216 are turned on, and transistor 5217 is turned off. The wiring SL is supplied with a potential Vdata of the image signal Sig, and the potential V The data is applied to the gate of transistor 5215 via transistor 5219. .

[0462] In addition, a potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. The potential Vano is obtained by adding the threshold voltage Vthe of the light emitting element 5214 to the potential Vcat. The potential Vano of the wiring VL is preferably higher than the potential of the transistor 5216. The voltage is applied to the other of the source and drain of the transistor 5215 via the The value of the drain current of the transistor 5215 is determined according to the level Vdata. Then, the drain current is supplied to the light emitting element 5214, and the light emitting element 5214 emits light. The degree is determined.

[0463] Next, in a period t2, a low-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A high level potential is applied to the wiring GLc, and a low level potential is applied to the wiring GLd. The transistor 5216 is turned on, and the transistor 5219 and the transistor 5217 are turned off. When transistor 5219 is turned off, a voltage is applied to the gate of transistor 5215. The potential Vdata is maintained. The potential Vano is applied to the wiring VL, and the potential Vdata is maintained at the wiring C. Therefore, in the light emitting element 5214, a constant potential Vcat is applied to L during the period t1. The brightness is maintained.

[0464] Next, in a period t3, a low-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A potential of the bell is applied to the wiring GLc, and a high-level potential is applied to the wiring GLc. The transistor 5217 is turned on, and the transistor 5219 and the transistor 5216 are turned off. A potential Vcat is applied to the wiring CL. A potential Vano is applied to the wiring ML. is provided and is connected to a monitor circuit.

[0465] By the above operation, the drain voltage of the transistor 5215 is The drain current is supplied to the light emitting element 5214. The monitor circuit uses the drain current flowing through the wiring ML to A signal including the value of the drain current as information is generated. In a light emitting device using such a semiconductor device, the pixel signal supplied to the pixel 5211 is The value of the potential Vdata of the image signal Sig can be corrected.

[0466] In the light-emitting device having the pixel 5211 shown in FIG. 38A, after the operation in the period t2, For example, in a light emitting device, the operation in the period t1 to the period t2 may be omitted. After repeating the above operation several times, the operation in the period t3 may be performed. After the operation of the pixel 5211 for the period t3, an image signal corresponding to the minimum gradation value 0 is input. By writing to the pixels 5211 in one row where the operation has been performed, the light emitting element 5214 is turned into a non-light emitting state. After this state is reached, the operation for the period t3 may be performed for the pixels 5211 in the next row. .

[0467] Also, for example, FIG. 39(A) is a diagram showing an example of a pixel circuit. An example in which five n-channel transistors and one capacitor are used is shown.

[0468] FIG. 39A shows an example of a circuit diagram of the pixel 5311. The pixel 531 shown in FIG. 1 includes a transistor 5315, a transistor 5316, a transistor 5317, and a capacitor A capacitor 5318, a light-emitting element 5314, a transistor 5319, and a transistor 532 0 and .

[0469] The transistor 5320 controls the conduction state between the wiring RL and the anode of the light-emitting element 5314. The transistor 5319 has a function of controlling the gate of the transistor 5315. The transistor 5315 has a function of controlling the conduction state between the source and the drain. One of the drains is electrically connected to the anode of the light-emitting element 5314. 16 is a conductive state between the wiring VL and the other of the source and drain of the transistor 5315. The transistor 5317 has a function of controlling the state of the transistor 531. The capacitance element 53 has a function of controlling the conduction state between the other of the source and drain of the capacitance element 53. One of the pair of electrodes of 18 is electrically connected to the gate of the transistor 5315, and the other One side is electrically connected to the anode of the light emitting element 5314 .

[0470] Also, the switching of the transistor 5319 is performed by applying an electric current to the gate of the transistor 5319. The switching of the transistor 5316 is performed according to the potential of the wiring GLa which is electrically connected to the transistor 5316. The potential of the wiring GLb electrically connected to the gate of the transistor 5316 is set to The switching of the transistor 5317 is performed by the gate of the transistor 5317. The potential of the wiring GLc electrically connected to the transistor 5320 is used. The switching of the transistor 5320 is performed by the voltage of the wiring GLd electrically connected to the gate of the transistor 5320. It is carried out according to rank.

[0471] In addition, transistors 5315, 5316, 5317, At least one of the transistors 5319 and 5320 is The capacitor 5318 can be any of the above-described capacitors. can.

[0472] Next, an example of the operation of external correction of the pixel 5311 shown in FIG. 39(A) will be described.

[0473] FIG. 39B shows a wiring GLa electrically connected to the pixel 5311 shown in FIG. The potentials of the wirings GLb, GLc, and GLd and the potential of the image signal Sig supplied to the wiring SL The timing chart shown in FIG. 39(B) is an example of a timing chart of the potential. In the case where all the transistors included in the pixel 5311 shown in FIG. 39(A) are n-channel transistors, This is an example of a case.

[0474] First, in a period t1, a high-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A low level potential is applied to the wiring GLc, a high level potential is applied to the wiring GLd. Therefore, the transistor 5319, the transistor 5316, and The transistor 5320 is turned on and the transistor 5317 is turned off. The potential Vdata of the image signal Sig is applied to L. The potential Vd is applied to the gate of the transistor 5315 through the resistor 5319. The value of the drain current of the transistor 5315 is determined according to the ata. The potential Vano is applied to the wiring VL, and the potential V1 is applied to the wiring RL. The drain current is connected to the wiring VL via the transistor 5316 and the transistor 5320. It flows between the lines RL.

[0475] The potential Vano is obtained by adding the threshold voltage Vthe of the light emitting element 5314 to the potential Vcat. The potential Vano of the wiring VL is preferably higher than the potential of the transistor 5316. The signal is applied to the other of the source and drain of the transistor 5315 through a wiring The potential V1 applied to RL is applied to the solenoid of the transistor 5315 via the transistor 5320. A potential Vcat is applied to the line CL.

[0476] The potential V1 is obtained by subtracting the threshold voltage Vth of the transistor 5315 from the potential V0. During the period t1, the potential V1 is set to be sufficiently lower than the potential Vcat. The potential can be made sufficiently lower than the potential obtained by subtracting the threshold voltage Vthe of the light emitting element 5314 from the potential. Therefore, the light emitting element 5314 does not emit light.

[0477] Next, in a period t2, a low-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A high level potential is applied to the wiring GLc, a low level potential is applied to the wiring GLd, and Therefore, transistor 5316 is turned on, and transistor 5317 is turned on. 319, transistor 5317, and transistor 5320 are turned off. 319 is turned off, the potential Vdata is Retained.

[0478] In addition, a potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. Therefore, the drain current of the transistor 5315, whose value is determined in the period t1, is When the transistor 5320 is turned off, the light is supplied to the light emitting element 5314. The drain current is supplied to the light emitting element 5314, and the luminance of the light emitting element 5314 is determined. The luminance is maintained for a period t2.

[0479] Next, in a period t3, a low-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A low level potential is applied to the wiring GLc, a high level potential is applied to the wiring GLd, and Therefore, transistor 5317 is turned on, and transistor 5318 is turned on. 319, the transistor 5316, and the transistor 5320 are turned off. A potential Vcat is applied to the wiring ML. A potential Vano is applied to the wiring ML. and connected to a monitor circuit.

[0480] By the above operation, the drain voltage of the transistor 5315 is The drain current is supplied to the light emitting element 5314. In addition, the drain current is supplied to the light emitting element 5314 via the wiring ML. The monitor circuit uses the drain current flowing through the wiring ML to A signal including the value of the drain current as information is generated. In a light emitting device using such a semiconductor device, the pixel signal supplied to the pixel 5311 is The value of the potential Vdata of the image signal Sig can be corrected.

[0481] In the light-emitting device having the pixel 5311 shown in FIG. 39A, after the operation in the period t2, For example, in a light emitting device, the operation in the period t1 to the period t2 may be omitted. After repeating the above operation several times, the operation in the period t3 may be performed. After the operation of the pixel 5311 for the period t3, an image signal corresponding to the minimum gradation value 0 is input. By writing to the pixels 5311 in one row where the operation has been performed, the light emitting element 5314 is turned into a non-light emitting state. After this state, the operation for the period t3 may be performed for the pixels 5311 in the next row. .

[0482] In addition, in the pixel 5311 shown in FIG. 39(A), the light emitting element 5314 is degraded and the light emitting element 5314 is no longer emitting light. Even if the resistance value between the anode and cathode of the photoelement 5314 varies among pixels, the potential Vdata can be tracked. When applying a voltage to the gate of transistor 5315, the potential of the source of transistor 5315 is set to a predetermined value. Therefore, the luminance of the light emitting element 5314 can be varied between the pixels. This can prevent the occurrence of fluctuations.

[0483] Also, for example, FIG. 40(A) is a diagram showing an example of a pixel circuit. An example in which six n-channel transistors and one capacitor are used is shown.

[0484] 40A shows an example of a circuit diagram of a pixel 5411. The pixel 5411 includes a transistor 5415, a transistor 5416, a transistor 5417, a capacitor 5418, A light-emitting element 5414, a transistor 5440, a transistor 5441, and a transistor 5442 and has.

[0485] The pixel electrode of the light emitting element 5414 is turned on in accordance with the image signal Sig input to the pixel 5411. The luminance of the light emitting element 5414 is controlled by the potential between the pixel electrode and the common electrode. It is determined by the difference.

[0486] The transistor 5440 is connected to a wiring SL and one of a pair of electrodes of a capacitor 5418. The other of the pair of electrodes of the capacitor 5418 is , electrically connected to one of the source and drain of the transistor 5415. The transistor 5416 controls the conduction state between the wiring VL1 and the gate of the transistor 5415. The transistor 5441 has a function of forming a gate electrode of one of a pair of electrodes of the capacitor 5418. and the gate of the transistor 5415. The transistor 5442 is connected to one of the source and drain of the transistor 5415 and the light-emitting element 541 The transistor 5417 has a function of controlling the conduction state between the anode of the transistor 5417 and the anode of the transistor 4. A function of controlling the conduction state between one of the source and drain of the sta 5415 and the wiring ML. It has.

[0487] Furthermore, in FIG. 40A, the other of the source and drain of the transistor 5415 is connected to a wiring. It is electrically connected to VL.

[0488] Also, the selection of whether the transistor 5440 is on or off is determined by the transistor 5440 The potential of the wiring GLa electrically connected to the gate of the transistor 5 is used. The on or off selection in 416 is electrically connected to the gate of transistor 5416. The on / off state of the transistor 5441 is controlled by the potential of the wiring GLa. The selection of the off state is performed by changing the potential of the wiring GLb electrically connected to the gate of the transistor 5441. The selection of whether the transistor 5442 is on or off is performed according to the This is done according to the potential of the wiring GLb electrically connected to the gate of the resistor 5442. The on / off selection of transistor 5417 is performed by the gate of transistor 5417. This is done according to the potential of the wiring GLc electrically connected to the

[0489] FIG. 40B shows a wiring GLa electrically connected to the pixel 5411 shown in FIG. 40A. The timing of the potential of the wiring GLb and the wiring GLc and the potential of the image signal Sig supplied to the wiring SL The timing chart shown in FIG. 40(B) is the same as that shown in FIG. 40(A). ) is an example in which all transistors included in the pixel 5411 are n-channel transistors. It is something.

[0490] First, in a period t1, a low-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A potential of the bell is applied to the wiring GLc, and a high-level potential is applied to the wiring GLc. The transistor 5441, the transistor 5442 and the transistor 5417 are turned on. Transistor 5440 and transistor 5416 are turned off. Transistor 5442 and transistor When the transistor 5417 is turned on, one of the source and drain of the transistor 5415 The other of the pair of electrodes of the capacitor 5418 (illustrated as node A) is connected to a wiring The potential V0 of ML is given.

[0491] In addition, a potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. The potential Vano is a potential obtained by adding the threshold voltage Vthe of the light emitting element 5414 to the potential V0. The potential V0 is preferably set higher than the potential Vcat of the light emitting element 5414. It is preferable that the potential V0 is set to the above value, which is lower than the potential obtained by adding the threshold voltage Vthe. By setting the value, it is possible to prevent current from flowing to the light-emitting element 5414 during the period t1. .

[0492] Next, a low-level potential is applied to the wiring GLb, whereby the transistors 5441 and Transistor 5442 is turned off and node A is held at potential V0.

[0493] Next, in a period t2, a high-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A high level potential is applied to the wiring GLc, and a low level potential is applied to the wiring GLd. The transistor 5440 and the transistor 5416 are turned on, and the transistor 5441 and the transistor The transistor 5442 and the transistor 5417 are turned off.

[0494] When the period t1 is changed to the period t2, the potential applied to the wiring GLa is changed from a low level to a high level. After switching to high level, the potential applied to the wiring GLc is switched from high level to low level. By performing such an operation, the current given to the wiring GLa is This can prevent the potential of node A from fluctuating due to potential switching.

[0495] In addition, a potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. The wiring SL is supplied with a potential Vdata of the image signal Sig, and the wiring VL1 is supplied with a potential Vdata of the image signal Sig. The potential V1 is given by multiplying the potential Vcat by the threshold voltage of the transistor 5415. Vth is added to the potential Vano, and the threshold voltage of the transistor 5415 is added to the potential Vano. It is preferable that the potential is lower than the potential obtained by adding Vth.

[0496] In the pixel configuration shown in FIG. 40A, the potential V1 is set to the threshold voltage of the light emitting element 5414. Even if the voltage Vthe is increased to a value greater than the sum of the voltage Vcat, the transistor 5442 will not be turned off. Therefore, the range of values ​​that can be set as the potential V0 is It is possible to widen the range of values ​​that can be taken as V1-V0. Therefore, the degree of freedom in setting the values ​​of V1-V0 increases, so the transistor 5415 When the time required to obtain the threshold voltage Vth is shortened or when the time required to obtain the threshold voltage Vth is shortened Even if the period is limited, the threshold voltage Vth of the transistor 5415 is accurately Acquisition can be performed.

[0497] By the above operation, a node B is applied to the gate of the transistor 5415. A potential V1 higher than the potential obtained by adding the threshold voltage Vth to the potential of node A is input. The transistor 5415 is turned on. The charge of 18 is released, and the potential of node A, which was at potential V0, begins to rise. At this time, the potential of the node A converges to V1-Vth, and the gate voltage of the transistor 5415 reaches a threshold value. When the voltage Vth converges to a lower voltage Vth, transistor 5415 turns off.

[0498] In addition, one of the pair of electrodes of the capacitor 5418 (illustrated as node C) The potential Vdata of the image signal Sig applied to the wiring SL is input to the transistor 5440. and is given.

[0499] Next, in a period t3, a low-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A high level potential is applied to the wiring GLc, and a low level potential is applied to the wiring GLd. The transistor 5441 and the transistor 5442 are turned on, and the transistor 5440 and the transistor The transistor 5416 and the transistor 5417 are turned off.

[0500] When the period t2 transitions to the period t3, the potential applied to the wiring GLa changes from a high level to a low level. After switching to low level, the potential applied to the wiring GLb is changed from low level to high level. With the above configuration, it is preferable to switch the potential applied to the wiring GLa. This can prevent fluctuations in the potential at node A.

[0501] In addition, a potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. .

[0502] By the above operation, the potential Vdata is applied to the node B, and the transistor 5415 The gate voltage of the transistor 5415 is Vdata-V1+Vth. The threshold voltage Vth can be set to a value that takes the threshold voltage Vth into account. This makes it possible to suppress variations in the threshold voltage Vth of the transistor 5415. Therefore, it is possible to suppress variations in the current value supplied to the light emitting element 5414, and the luminance of the light emitting device It is possible to reduce unevenness.

[0503] Note that by increasing the fluctuation of the potential applied to the wiring GLb, The variation in the threshold voltage of the light emitting element 5414 is prevented from affecting the current value supplied to the light emitting element 5414. That is, the high-level potential applied to the wiring GLb can be The low level potential applied to the wiring GLb is sufficiently higher than the threshold voltage of the transistor. By making the threshold voltage of the transistor 5442 sufficiently smaller than the threshold voltage of the transistor 5442, and the threshold voltage of the transistor 5442. This can prevent the influence of the light emitting element 5414 on the current value.

[0504] Next, in a period t4, a low-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A potential of the bell is applied to the wiring GLc, and a high-level potential is applied to the wiring GLc. The transistor 5417 is turned on, and the transistor 5416, the transistor 5440, and the transistor The transistor 5441 and the transistor 5442 are turned off.

[0505] A potential Vano is applied to the wiring VL, and the wiring ML is connected to the monitor circuit. .

[0506] By the above operation, the drain current Id of the transistor 5415 is The monitor circuit does not flow to the wiring ML but flows to the wiring ML via the transistor 5417. Using the drain current Id, a signal containing the value of the drain current Id as information is generated. This drain current Id is determined by the mobility of the transistor 5415 and the The size of the channel depends on the size of the channel (channel length, channel width, etc.). In a light-emitting device using the semiconductor device according to one embodiment of the present invention, the pixel 5411 is The value of the potential Vdata of the supplied image signal Sig can be corrected. The influence of variations in the mobility of the transistor 5415 can be reduced.

[0507] In the light-emitting device having the pixel 5411 shown in FIG. 40A, after the operation in the period t3, For example, in a light emitting device, the operation in the period t1 to the period t3 may be omitted. After repeating the above operation several times, the operation in the period t4 may be performed. After the operation of the pixel 5411 during the period t4, an image signal corresponding to the minimum gradation value 0 is output. By writing to the pixels 5411 in one row where the operation has been performed, the light emitting element 5414 is turned into a non-light emitting state. After this state is reached, the operation for the period t4 may be performed for the pixels 5411 in the next row. .

[0508] In the light-emitting device having the pixel 5411 shown in FIG. The other of the source and drain is electrically isolated from the gate of the transistor 5415. Therefore, during the period t2, the potentials of the transistors 1 and 2 can be controlled individually. The potential of the other of the source and drain of the transistor 5415 is connected to the gate of the transistor 5415. The potential can be set to a value higher than the potential obtained by adding the threshold voltage Vth to the potential. Therefore, when the transistor 5415 is normally on, that is, when the threshold voltage Vt When h has a negative value, the source potential of the transistor 5415 is Charge can be stored in the capacitor 5418 until the potential becomes higher than the gate potential V1. Therefore, in a light-emitting device using a semiconductor device according to one embodiment of the present invention, the transistor 541 Even if the transistor 5 is normally on, the threshold voltage Vth can be obtained during the period t2. During the period t3, the transistor 5 The gate voltage of 415 can be set.

[0509] Therefore, in a light-emitting device using a semiconductor device according to one embodiment of the present invention, transistor 5 Even if the 415 is normally on, it is possible to reduce display unevenness and display high quality images. can.

[0510] In addition to the characteristics of the transistor 5415, the characteristics of the light-emitting element 5414 were also monitored. At this time, the potential Vdata of the image signal Sig may be controlled to It is preferable to prevent current from flowing through the transistor 5415. The current of the light emitting element 5414 can be extracted. As a result, the current characteristic of the light emitting element 5414 It is possible to obtain the state of deterioration and variation of the

[0511] For example, in this specification, a display element, a display device which is a device having a display element, a light-emitting device, A light-emitting device, which is a device having an element and a light-emitting element, can be used in various forms or in various The display element, the display device, the light-emitting element or the light-emitting device may include, for example, For example, EL elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LE D (white LED, red LED, green LED, blue LED, etc.), transistor (responding to current transistors that emit light when exposed to light, electron-emitting devices, liquid crystal devices, electronic ink, electrophoretic devices, graphene Rating light valves (GLV), plasma displays (PDP), MEMS (mechanical Display element using microelectromechanical system, digital micromirror Device (DMD), DMS (Digital Micro Shutter), IMOD (Interface Optical interference MEMS display elements, electrowetting elements, piezoelectric ceramic displays , a display element using carbon nanotubes, etc. In addition, contrast, brightness, reflectivity, transmittance, etc. change due to electrical or magnetic effects. An example of a display device using an EL element is an EL display. An example of a display device using electron-emitting elements is a field emitter. Flat panel display (FED) or SED (Surface Emitting Diode) ace-conduction Electron-emitter Display) An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal Displays, semi-transmissive LCD displays, reflective LCD displays, direct-view LCD displays (Electronic ink, electronic liquid powder (registered trademark), An example of a display device using an electrophoretic element is electronic paper. When realizing a semi-transmissive or reflective LCD, one of the pixel electrodes For example, a part or the whole of the pixel electrode may be made to function as a reflective electrode. A part or the whole of the material may contain aluminum, silver, etc. It is also possible to provide a memory circuit such as an SRAM under the reflective electrode. Power consumption can be further reduced.

[0512] In addition, if the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) is white light ( In order to display full color using a colored layer (also called a color filter), The colored layer may be, for example, red (R), green (G), blue (B), or the like. ), yellow (Y), etc. can be used in combination as appropriate. In this case, the color reproducibility can be improved compared to when no color layer is used. By disposing a region having a colored layer and a region not having a colored layer, The white light in the region may be directly used for display. By placing the color layer in the display, the decrease in brightness caused by the color layer can be reduced during bright display, and power consumption can be reduced by 2. However, it may be possible to reduce the emission by approximately 100% to 30%. When using optical elements to display full color, R, G, B, Y, and W are emitted by each color. By using a self-luminous element, it is possible to make the light emitted from a colored layer. In some cases, power consumption can be further reduced.

[0513] <module> A display module using a semiconductor device according to one embodiment of the present invention will be described below with reference to FIG. The explanation will be given using 1.

[0514] The display module 8000 shown in FIG. 41 includes an upper cover 8001 and a lower cover 8002. Between them, touch panel 8004 connected to FPC8003 and a cell 8006, a backlight unit 8007, a frame 8009, a printed circuit board 80 10, and a battery 8011. 8011, the touch panel 8004, etc. may not be provided.

[0515] The semiconductor device according to one embodiment of the present invention can be used for the cell 8006, for example.

[0516] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the cell 800 The shape and dimensions can be changed as needed to fit the size of 6.

[0517] The touch panel 8004 is a resistive or capacitive touch panel. 6. Also, the opposing substrate (sealing substrate) of the cell 8006 can be attached to the Alternatively, each pixel of the cell 8006 may have a touch panel function. It is also possible to provide an optical sensor in the cell 80 to make it an optical touch panel. 06: A touch sensor electrode is provided in each pixel to create a capacitive touch panel. is also possible.

[0518] The backlight unit 8007 includes a light source 8008. It may be provided at the end of the light source unit 8007 and may be configured to use a light diffusion plate.

[0519] The frame 8009 has a function of protecting the cell 8006 and also functions as a The frame may also have a function as an electromagnetic shield to block electromagnetic waves generated by the frame. The frame 8009 may also function as a heat sink.

[0520] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. In this case, the battery 8011 may not be required.

[0521] The display module 8000 also includes components such as a polarizing plate, a retardation plate, and a prism sheet. Additional ones may be provided.

[0522] (Embodiment 7) In this embodiment, electronic devices in which the semiconductor device of one embodiment of the present invention can be used will be described. This will be explained using FIG.

[0523] 44(A) to 44(H) are diagrams showing electronic devices. These electronic devices are Body 6000, display unit 6001, speaker 6003, LED lamp 6004, operation keys 6 005 (including power switch or operation switch), connection terminal 6006, sensor 60 07 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration , including the function of measuring odor or infrared rays), microphone 6008, etc. It is possible.

[0524] FIG. 44(A) shows a mobile computer, which includes, in addition to the above, a switch 6009 , an infrared port 6010, etc. FIG. 44(B) shows a portable terminal equipped with a recording medium. A portable image playback device (for example, a DVD playback device) that, in addition to the above, has a display unit 6002, a recording medium reading unit 6011, etc. In addition to the above, it is a display unit 6002, a support unit 6012, and an earphone. 44(D) shows a portable gaming machine, which can have the above-mentioned In addition, it can have a recording medium reading unit 6011, etc. In addition to the above, it is a digital camera with an imaging function, and includes an antenna 6014, a shutter It may have buttons 6015, an image receiving unit 6016, etc. In addition to the above, it has a display unit 6002, a recording medium reading unit 6011, etc. Figure 44(G) shows a television receiver, which in addition to the above-mentioned components, includes a tuner, a picture FIG. 44(H) shows a portable television receiver. In addition to those mentioned above, it may have a charger 6017 capable of transmitting and receiving signals, etc.

[0525] The electronic devices shown in FIGS. 44(A) to 44(H) can have various functions. For example, functions to display various information (still images, videos, text images, etc.) on the display, Touch panel function, calendar, date or time display function, various software ( It has the function of controlling processing by using a program, wireless communication function, and various functions using wireless communication function. Functions for connecting to computer networks, transmitting various data using wireless communication functions, or receiving the program or data recorded on the recording medium, and Furthermore, electronic devices having multiple display units can also have a function of displaying information on the display unit. In this case, one display unit is used mainly to display image information, and another display unit is used mainly to display text. It is possible to display text information on multiple displays, or to display images that take parallax into account. Furthermore, electronic devices having an image receiving unit can have a function of displaying a physical image. In this case, the camera has the functions of taking still images, taking videos, and saving the images automatically or manually. Function to automatically correct the image, and function to save the captured image to a recording medium (external or built-in to the camera) , and the function of displaying the captured image on the display unit. The functions that the electronic devices shown in FIGS. 44(A) to 44(H) can have are not limited to these, and various It can have such functions.

[0526] The electronic device described in this embodiment has a display unit for displaying some information. Note that the semiconductor device of one embodiment of the present invention is not limited to an electronic device that does not have a display portion. It can also be applied to

[0527] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done. [Explanation of symbols]

[0528] 100 boards 101 insulating film 102 insulating film 102a Insulating film 102b insulating film 104a gate electrode 104a1 Conductive film 104a2 Conductive film 104b Lower electrode 104b1 Conductive film 104b2 Conductive film 106 First Area 106a Channel formation region 106b Channel formation region 106c Channel formation region 107a Second Area 107a1 Low resistance area 107a2 Low resistance area 107b Second Area 107b1 Low resistance region 107b2 Low resistance area 108 insulating film 112a Gate insulating film 112b insulating film 113 Desorption prevention membrane 114a Gate electrode 114a1 Conductive film 114a2 Conductive film 114b Upper electrode 114b1 Conductive film 114b2 Conductive film 116a Source electrode 116a1 Conductive film 116a2 Conductive film 116b Drain electrode 116b1 Conductive film 116b2 Conductive film 118 insulating film 126 Oxide semiconductor film 126a Oxide semiconductor film 126b Oxide semiconductor film 128 insulating film 132 insulating film 138 insulating film 140 Oxygen 142 Impurity elements 148 insulating film 150 transistors 160 Capacitor 204 Wiring 204a Conductive film 204b Conductive film 212 insulating film 214 Wiring 214a Conductive film 214b Conductive film 216 Wiring 216a Conductive film 216b Conductive film 400 boards 453 Insulating Film 453a Insulating film 453b insulating film 455 Oxide semiconductor film 455a Channel region 455b Low resistance area 455c low resistance area 455d area 455e area 455f Low resistance area 455g low resistance area 455h Low resistance region 455i low resistance area 457 Insulating Film 457a Insulating film 457b insulating film 459 Conductive Film 459a Conductive film 459b Conductive film 465 Nitride insulating film 467 Insulating Film 468 Conductive Film 469 Conductive Film 475 insulating film 500 FET 501 PCB 502 board 504R Light-emitting element 504G Light-emitting element 504B Light-emitting element 504W light emitting element 506 Conductive film 507 Conductive film 508 Bulkhead 509 Structure 510 EL layer 512 Conductive film 514R colored layer 514G colored layer 514B Colored layer 514W colored layer 516 PCB 518 Sealing film 520 areas 522 insulating film 524 Opening 600 pellets 600a pellets 600b pellets 601 Aeon 620 board 630 Target 700 Display device 701 PCB 702 pixel section 704 Source driver circuit section 705 PCB 706 Gate driver circuit section 708 FPC terminal section 710 Signal Line 711 Wiring section 712 Sealing material 716 FPC 730 insulating film 732 Sealing film 734 Insulating Film 736 Colored film 738 Light-shielding film 750 transistors 752 transistors 760 connecting electrode 766 Insulating Film 770 Planarization insulating film 772 Conductive film 774 Conductive film 775 Liquid Crystal Elements 776 Liquid Crystal Layer 778 Structure 780 Anisotropic Conductive Film 782 Light-emitting element 784 Conductive Film 786 EL layer 788 Conductive Film 790 Capacitor 5000 boards 5001 Pixel unit 5002 Scanning line driver circuit 5003 Scanning line driver circuit 5004 Signal line driver circuit 5010 Capacitor wiring 5012 Gate wiring 5013 Gate wiring 5014 Drain electrode 5016 Transistor 5017 Transistor 5018 Liquid crystal element 5019 Liquid crystal element 5020 pixels 5021 Switching transistor 5022 Drive transistor 5023 Capacitor element 5024 Light-emitting element 5025 signal line 5026 scan lines 5027 Power line 5028 Common electrode 5029 Capacitor 5111 pixels 5154 Light-emitting element 5155 Transistor 5156 Transistor 5157 Transistor 5158 Capacitor element 5211 pixels 5214 Light-emitting element 5215 Transistor 5216 Transistor 5217 Transistor 5218 Capacitor element 5219 Transistor 5311 pixels 5314 Light-emitting elements 5315 Transistor 5316 Transistor 5317 Transistor 5318 Capacitor element 5319 Transistor 5320 Transistor 5411 pixels 5414 Light-emitting element 5415 Transistor 5416 Transistor 5417 Transistor 5418 Capacitor element 5440 transistor 5441 Transistor 5442 transistor 6000 cabinet 6001 Display section 6002 Display section 6003 Speaker 6004 LED lamp 6005 Operation key 6006 Connection terminal 6007 Sensor 6008 Microphone 6009 Switch 6010 Infrared port 6011 Recording medium reading unit 6012 Support part 6013 Earphones 6014 Antenna 6015 Shutter button 6016 Image receiving unit 6017 charger 6100 pellets 6120 PCB 6161 area 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 cells 8007 Backlight Unit 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery

Claims

1. A semiconductor device including a pixel having a first transistor, a second transistor, a third transistor, a capacitor, a light-emitting element, a first wiring, a second wiring, and a third wiring, a gate of the first transistor is always electrically connected to one of the source and drain of the second transistor; a gate of the first transistor is always electrically connected to one electrode of the capacitance element; one of the source and the drain of the first transistor is always electrically connected to the light emitting element; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the third transistor; one of the source and the drain of the first transistor is always electrically connected to the other electrode of the capacitor element; the other of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the second transistor is always electrically connected to the second wiring; the other of the source and the drain of the third transistor is always electrically connected to the third wiring; The first transistor is a first conductive film; a first insulating film having a region in contact with an upper surface of the first conductive film; an oxide semiconductor film having an upper surface and a region of the first insulating film; a second insulating film having a region in contact with an upper surface of the oxide semiconductor film; a second conductive film having a region in contact with an upper surface of the second insulating film; a third conductive film having a region in contact with an upper surface of the second conductive film; a third insulating film having a region in contact with an upper surface of the second conductive film; a fourth conductive film having a region in contact with a top surface of the oxide semiconductor film, The capacitive element is a fifth conductive film; the first insulating film having a region in contact with an upper surface of the fifth conductive film; a fourth insulating film having a region in contact with an upper surface of the first insulating film; a sixth conductive film having a region in contact with an upper surface of the fourth insulating film; a seventh conductive film having a region in contact with an upper surface of the sixth conductive film; the first conductive film has the same material as the fifth conductive film; the second insulating film has the same material as the fourth insulating film; the second conductive film has the same material as the sixth conductive film; the third conductive film has the same material as the seventh conductive film; the oxide semiconductor film has a region overlapping with the first conductive film, when viewed in a cross section of the first transistor in a channel length direction, both ends of the second conductive film are located outside both ends of the third conductive film; when viewed in a cross section of the first transistor in a channel length direction, both ends of the second insulating film are located outside both ends of the second conductive film; In a cross-sectional view of the first transistor in a channel length direction, both ends of the second insulating film are located inside both ends of the first conductive film, the oxide semiconductor film has a first region and a second region adjacent to the first region, the second region has a thickness smaller than the thickness of the first region; the first region overlaps the first conductive film, the second region has a region overlapping with the first conductive film and a region not overlapping with the first conductive film, the third insulating film has a region in contact with the fourth conductive film, a region in contact with the third conductive film, a region in contact with the second insulating film, a region in contact with the oxide semiconductor film, a region in contact with the first insulating film, a region in contact with the seventh conductive film, a region in contact with the sixth conductive film, and a region in contact with the fourth insulating film; In a cross-sectional view of the first transistor in a channel length direction, a shape of an end of the second insulating film has a region where an angle formed between a tangent to a side surface of the second insulating film and a surface of the oxide semiconductor film changes.

2. A semiconductor device including a pixel having a first transistor, a second transistor, a third transistor, a capacitor, a light-emitting element, a first wiring, a second wiring, and a third wiring, a gate of the first transistor is always electrically connected to one of the source and drain of the second transistor; a gate of the first transistor is always electrically connected to one electrode of the capacitance element; one of the source and the drain of the first transistor is always electrically connected to the light emitting element; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the third transistor; one of the source and the drain of the first transistor is always electrically connected to the other electrode of the capacitor element; the other of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the second transistor is always electrically connected to the second wiring; the other of the source and the drain of the third transistor is always electrically connected to the third wiring; The first transistor is a first conductive film; a first insulating film having a region in contact with an upper surface of the first conductive film; an oxide semiconductor film having an upper surface and a region of the first insulating film; a second insulating film having a region in contact with an upper surface of the oxide semiconductor film; a second conductive film having a region in contact with an upper surface of the second insulating film; a third conductive film having a region in contact with an upper surface of the second conductive film; a third insulating film having a region in contact with an upper surface of the second conductive film; a fourth conductive film having a region in contact with a top surface of the oxide semiconductor film, The capacitive element is a fifth conductive film; the first insulating film having a region in contact with an upper surface of the fifth conductive film; a fourth insulating film having a region in contact with an upper surface of the first insulating film; a sixth conductive film having a region in contact with an upper surface of the fourth insulating film; a seventh conductive film having a region in contact with an upper surface of the sixth conductive film; the first conductive film has the same material as the fifth conductive film; the second insulating film has the same material as the fourth insulating film; the second conductive film has the same material as the sixth conductive film; the third conductive film has the same material as the seventh conductive film; the oxide semiconductor film has a region overlapping with the first conductive film, when viewed in a cross section of the first transistor in a channel length direction, both ends of the second conductive film are located outside both ends of the third conductive film; when viewed in a cross section of the first transistor in a channel length direction, both ends of the second insulating film are located outside both ends of the second conductive film; In a cross-sectional view of the first transistor in a channel length direction, both ends of the second insulating film are located inside both ends of the first conductive film, the oxide semiconductor film has a first region and a second region adjacent to the first region, the second region has a thickness smaller than the thickness of the first region; the first region overlaps the first conductive film, the second region has a region overlapping with the first conductive film and a region not overlapping with the first conductive film, the third insulating film has a region in contact with the fourth conductive film, a region in contact with the third conductive film, a region in contact with the second insulating film, a region in contact with the oxide semiconductor film, a region in contact with the first insulating film, a region in contact with the seventh conductive film, a region in contact with the sixth conductive film, and a region in contact with the fourth insulating film; In a cross-sectional view of the first transistor in a channel length direction, a shape of an end portion of the second insulating film has a region in which an angle formed between a tangent to a side surface of the second insulating film and a surface of the oxide semiconductor film changes; In a cross-sectional view, both ends of the sixth conductive film are located outside both ends of the seventh conductive film, In a cross-sectional view, both ends of the fourth insulating film are located outside both ends of the sixth conductive film, A semiconductor device, wherein, in a cross-sectional view, the shape of the end of the fourth insulating film has a region where the angle between a tangent to a side surface of the fourth insulating film and a surface of the first insulating film changes.

3. In claim 1 or 2, The semiconductor device has a region in which the film thickness of the second region is smaller than the film thickness of the first region by 0.1 nm or more and 5 nm or less.

4. In any one of claims 1 to 3, The semiconductor device, wherein the oxide semiconductor film contains In, Ga, and Zn.

Images