Semiconductor device
A planar transistor using an oxide semiconductor with a simplified manufacturing process addresses parasitic capacitance issues in high-resolution displays, ensuring stable electrical performance and reliable image quality.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-11-19
- Publication Date
- 2026-03-04
AI Technical Summary
As display devices increase in size and resolution, inverted staggered transistors using oxide semiconductors face issues with parasitic capacitance between electrodes, leading to signal delays and image quality deterioration, while planar transistors require a complex manufacturing process.
A semiconductor device with a planar transistor structure using an oxide semiconductor, incorporating a gate electrode, gate insulating film, and a capacitor connected to the transistor, with specific insulating films and conductive films to reduce parasitic capacitance and simplify manufacturing.
The solution provides a semiconductor device with stable electrical characteristics, high on-state current, low off-state current, and reliable operation, suitable for high-resolution displays with reduced manufacturing complexity.
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Abstract
Citation Information
Patent Citations
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JP2009278115A