Data decompression device, memory system, information processing system, and data decoding device

Abstract

To provide a data expanding device capable of efficiently using the band width of a RAM.SOLUTION: According to an embodiment, a data decompression device includes a read control unit, a decompression unit, and a write control unit. The read control unit transfers the compressed data stored in the first storage area starting from the first address in the RAM to the data decompression device. The decompression unit sequentially decompresses the transferred compressed data from the beginning to generate decompressed data. The write control unit transfers one or more data portions, which are designated by the first information and are to be stored in the RAM, of the generated decompressed data to a second storage area starting from a second address in the RAM. The write control unit outputs a signal indicating that the transfer of the one or more data portions is completed to the read control unit. In response to receiving the signal, the read control unit performs control to stop reading the compressed data stored in the first storage area.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to techniques for decompressing or decoding data. [Background technology]

[0002] A data compression unit is a unit in which data is compressed independently of other data. In certain compression methods, increasing the compression unit increases the amount of data that can be referenced in the compression process. A particular compression method is a compression method that compresses data sequentially from the beginning, such as dictionary compression. Therefore, increasing the compression unit can improve the data compression efficiency.

[0003] However, when decompressing compressed data to obtain a portion of the decompressed data, a large compression unit may waste the bandwidth of the random access memory (RAM) in which the compressed and decompressed data are stored. The RAM bandwidth is the data transfer capacity of the transmission path between the RAM and an external element, such as a data decompression device that decompresses the compressed data.

[0004] The same applies to obtaining a portion of the decrypted data obtained by decrypting encrypted data, which is data encrypted using an encryption method such as a stream cipher that encrypts data sequentially from the beginning. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Application Publication No. 2021 / 0144226 [Patent Document 2] US Patent Application Publication No. 2024 / 0111587 [Patent Document 3] U.S. Patent No. 10,444,991 Summary of the Invention [Problem to be solved by the invention]

[0006] An embodiment of the present invention provides a data decompression device, a memory system, an information processing system, and a data decoding device that can efficiently use RAM bandwidth when decompressing compressed data or decrypting encrypted data. [Means for solving the problem]

[0007] According to an embodiment, a data decompression device is connectable to a host. The data decompression device includes a read control unit, a decompression unit, and a write control unit. In response to receiving a first address from the host, the read control unit transfers compressed data stored in a first storage area in a random access memory, the first address being the starting address, to the data decompression device. The decompression unit decompresses the transferred compressed data sequentially from the beginning to generate decompressed data. In response to receiving from the host first information specifying one or more data portions to be stored in the random access memory and a second address, the write control unit transfers the one or more data portions specified by the first information to a second storage area in the random access memory, the second address being the starting address. The write control unit outputs a signal to the read control unit indicating that the transfer of the one or more data portions has been completed. In response to receiving the signal, the read control unit controls to stop reading of the compressed data stored in the first storage area. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram showing an example of the configuration of an information processing system including a data decompression device according to a first embodiment. [Figure 2] FIG. 10 is a diagram showing the amount of data transferred between a data decompression device according to a comparative example and a RAM. [Figure 3] FIG. 1 is a block diagram showing an example of the configuration and operation of a data decompression device according to a first embodiment. [Figure 4]3 is a diagram showing an example of the structure of decompressed data for specifying a partial decompression position in the data decompression device according to the first embodiment. FIG. [Figure 5] 3A and 3B are diagrams showing a first example of partial decompression position information and a second example of partial decompression position information, respectively, in the data decompression device according to the first embodiment. [Figure 6] 10 is a flowchart showing an example of the procedure of a read control process executed in the data decompression device according to the first embodiment. [Figure 7] 10 is a flowchart showing an example of the procedure of a write control process executed in the data decompression device according to the first embodiment. [Figure 8] FIG. 10 is a block diagram showing an example of the configuration and operation of a data decompression device according to a second embodiment. [Figure 9] 10 is a flowchart showing an example of the procedure of a verification process executed in a data decompression device according to the second embodiment. [Figure 10] FIG. 10 is a block diagram showing an example of the configuration and operation of a data decompression device according to a third embodiment. [Figure 11] 10 is a diagram showing an example of the data structure of a decompressed data portion including a checksum value in a data decompression device according to a third embodiment. [Figure 12] 11 is a flowchart showing an example of the procedure of a verification process executed in a data decompression device according to the third embodiment. [Figure 13] FIG. 10 is a block diagram showing an example of the configuration and operation of a data decoding device according to a fourth embodiment. [Figure 14] 10A and 10B are diagrams showing an example of encryption of plaintext data and an example of decryption of encrypted data in an encryption method used in a data decryption device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings.

[0010] (First embodiment) 1 shows an example of the configuration of an information processing system including a data decompression device according to Embodiment 1. The information processing system 1 includes a host device 2 and a memory system 3.

[0011] The host device 2 is an information processing device that stores data in the memory system 3. The host device 2 is, for example, a storage server or a personal computer that stores a large amount of diverse data in the memory system 3. Hereinafter, the host device 2 will be referred to as the host 2.

[0012] The memory system 3 is a semiconductor storage device configured to write data to and read data from a nonvolatile memory. The nonvolatile memory is, for example, a NAND flash memory 4. The memory system 3 is realized, for example, as a solid state drive (SSD). The following describes an example in which the memory system 3 is realized as an SSD. Note that the memory system 3 may also be realized as another type of storage device, such as a hard disk drive (HDD).

[0013] The memory system 3 can be used as storage for the host 2. The memory system 3 may be built into the host 2, or may be connected to the host 2 via a cable or a network.

[0014] The interface for connecting the host 2 and the memory system 3 is SCSI, Serial Attached SCSI (SAS), ATA (AT Attachment), Serial ATA (SATA), PCI Express TM (PCIe TM ), Ethernet TM , Fiber channel, NVM Express TM (NVMe TM ) and other standards.

[0015] The memory system 3 includes, for example, a NAND flash memory 4, a dynamic random access memory (DRAM) 5, and a controller 6.

[0016] The NAND flash memory 4 includes one or more memory chips. Each memory chip includes multiple blocks. A block functions as the smallest unit of a data erase operation. A block is also called an erase block or a physical block. Each of the multiple blocks includes multiple pages. Each of the multiple pages includes multiple memory cells connected to a single word line. A page functions as a unit of a data write operation and a data read operation. Note that a word line may also function as a unit of a data write operation and a data read operation.

[0017] There is an upper limit to the number of program / erase cycles (P / E cycles) for each block, called the maximum number of P / E cycles. One P / E cycle for a block includes an erase operation to erase all memory cells in the block, and a write operation to write data to each page of the block.

[0018] The DRAM 5 is a volatile memory. The storage area of ​​the DRAM 5 is allocated as, for example, a storage area for firmware (FW), a cache area for a logical-physical address conversion table, and a buffer area for user data. Here, the user data is data that the host 2 stores in the memory system 3 and is write data transmitted from the host 2.

[0019] At least a portion of the storage area in the DRAM 5 can be used by the host 2 as a buffer area. Specifically, for example, when issuing a command to the memory system 3, the host 2 can specify an address in the buffer area (i.e., an address in the DRAM 5) where data acquired in response to the command is to be stored. In this case, the data acquired in response to the command is stored in a storage area in the DRAM 5 starting from the specified address. The host 2 can also read data from the buffer area and transfer it to the host 2. Such use of the DRAM 5 by the host 2 is realized, for example, by using at least a portion of the storage area in the DRAM 5 as a controller memory buffer (CMB) defined by NVMe. The storage area in the DRAM 5 used as the CMB is a storage area available to the host 2.

[0020] At least a part of the storage area of ​​the DRAM 5 is allocated as a first data buffer 51 and a second data buffer 52, for example.

[0021] The first data buffer 51 is a storage area for storing compressed data. The starting address of the first data buffer 51 in the storage area of ​​the DRAM 5 is specified by, for example, the host 2. Furthermore, the size of the first data buffer 51 may also be specified by the host 2. The compressed data stored in the first data buffer 51 is, for example, compressed data read from the NAND flash memory 4. Alternatively, the compressed data stored in the first data buffer 51 may be compressed data transferred from the host 2.

[0022] The second data buffer 52 is a storage area that stores decompressed data (uncompressed data) obtained by decompressing compressed data. The decompressed data is, for example, user data. The starting address of the second data buffer 52 in the storage area of ​​the DRAM 5 is specified, for example, by the host 2. Furthermore, the size of the second data buffer 52 may also be specified by the host 2.

[0023] The DRAM 5 and the controller 6 are connected via a transmission path 16. The transmission path 16 is a physical transmission medium for transmitting data. The transmission path is also called a communication path. Specifically, data read from the DRAM 5 is transferred from the DRAM 5 via the transmission path 16. Data written to the DRAM 5 is transferred to the DRAM 5 via the transmission path 16. The amount of data that the transmission path 16 can transmit (data transfer capacity) is called the bandwidth of the DRAM 5.

[0024] The controller 6 is a memory controller that controls the NAND flash memory 4 and the DRAM 5. The controller 6 is realized by a circuit such as a System-on-a-chip (SoC), for example.

[0025] The controller 6 functions as, for example, a flash translation layer (FTL) configured to perform data management and block management of the NAND flash memory 4. The data management performed by the FTL includes (1) management of mapping information indicating the correspondence between each logical address and each physical address of the NAND flash memory 4, and (2) processing for concealing the difference between page-based data read / write operations and block-based data erase operations. The block management includes management of bad blocks, wear leveling, and garbage collection.

[0026] The logical address is used by the host 2 to address a storage area in the memory system 3. The logical address is, for example, a logical block address (LBA).

[0027] The management of the mapping between each logical address and each physical address is performed using, for example, a logical-physical address conversion table. The controller 6 uses the logical-physical address conversion table to manage mapping information between each logical address and each physical address in specific management size units. A physical address corresponding to a certain logical address indicates a physical storage location in the NAND flash memory 4 where user data of this logical address is written. The logical-physical address conversion table may be loaded from the NAND flash memory 4 to the DRAM 5 when the memory system 3 is started up.

[0028] Data can be written to one page only once per P / E cycle. Therefore, the controller 6 writes updated user data corresponding to a certain logical address to a different physical storage location, rather than to the physical storage location where the previous user data corresponding to this logical address is stored. The controller 6 then invalidates the previous user data by updating the logical-physical address translation table so as to associate this logical address with this different physical storage location.

[0029] The controller 6 includes, for example, a CPU 11, a NAND interface (NAND I / F) 12, a DRAM interface (DRAM I / F) 13, a host interface (host I / F) 14, and a data decompression device 15. The CPU 11, the NAND I / F 12, the DRAM I / F 13, the host I / F 14, and the data decompression device 15 are connected via, for example, a bus 10.

[0030] The controller 6 may have a built-in static random access memory (SRAM) 17 or a DRAM. In this case, the DRAM 5 external to the controller 6 may not be provided.

[0031] The SRAM 17 is a volatile memory. The storage area of ​​the SRAM 17 can be allocated as, for example, at least one of a storage area for the FW, a cache area for the logical-physical address conversion table, and a buffer area for user data. The storage area of ​​the SRAM 17 can also be allocated as a first data buffer 51 and a second data buffer 52.

[0032] The SRAM 17 and each part in the controller 6 are connected via a transmission path 18. Specifically, data read from the SRAM 17 is transferred from the SRAM 17 via the transmission path 18. Data written to the SRAM 17 is transferred to the SRAM 17 via the transmission path 18. The data transfer capacity of the transmission path 18 is called the bandwidth of the SRAM 5.

[0033] The following mainly illustrates a case where the storage areas of the DRAM 5 are allocated as the first data buffer 51 and the second data buffer 52. Note that the DRAM 5 in the following description may be replaced with another RAM in the memory system 3, such as the SRAM 17.

[0034] The CPU 11 is a processor configured to control the NAND I / F 12, the DRAM I / F 13, the host I / F 14, and the data decompression device 15. The CPU 11 performs various processes by executing FW loaded from the NAND flash memory 4 to the DRAM 5. The FW is a control program including a group of instructions for causing the CPU 11 to perform various processes. In addition to the FTL processing described above, the CPU 11 also performs command processing for processing various commands from the host 2. The operation of the CPU 11 is controlled by the FW executed by the CPU 11. Note that some or all of the FTL processing and command processing may be performed by dedicated hardware within the controller 6.

[0035] The NAND I / F 12 electrically connects the controller 6 and the NAND flash memory 4. The NAND I / F 12 supports interface standards such as Toggle DDR and Open NAND Flash Interface (ONFI).

[0036] The NAND I / F 12 functions as a NAND control circuit configured to control the NAND flash memory 4. The NAND I / F 12 may be connected to multiple memory chips in the NAND flash memory 4 via multiple channels. By driving multiple memory chips in parallel, it is possible to widen the bandwidth of access to the entire NAND flash memory 4.

[0037] The DRAM I / F 13 functions as a DRAM control circuit configured to control access to the DRAM 5 .

[0038] The host I / F 14 is a circuit that functions as an interface for communication between the memory system 3 and the host 2. The host I / F 14 includes a circuit that receives various commands (e.g., input / output (I / O) commands and control commands) from the host 2. The I / O commands are, for example, read commands or write commands. The control commands are, for example, unmap commands (trim commands) or format commands. The host I / F 11 includes a circuit that transmits responses and data according to the commands to the host 2.

[0039] The data decompression device 15 is a decompressor that decompresses compressed data. The compressed data is, for example, data transmitted from the host 2 to the memory system 3 or data read from the NAND flash memory 4. For example, the CPU 11 stores the compressed data read from the NAND flash memory 4 in the DRAM 5 (for example, the first data buffer 51) in response to receiving a read command from the host 2. The data decompression device 15 reads the compressed data stored in the DRAM 5 and decodes the read compressed data to generate decompressed data.

[0040] The data decompression device 15 decompresses the compressed data in compression units. A compression unit is a group of data that is compressed at one time. Within the data of a compression unit, dependencies such as references to data portions are closed. In other words, it is not possible to reference data portions beyond the compression unit. In this way, a compression unit is a unit in which data is compressed independently of other data. In certain compression methods, increasing the compression unit increases the amount of data that can be referenced in the compression process, improving the data compression efficiency. A certain compression method is, for example, a compression method that compresses data sequentially from the beginning, such as dictionary compression.

[0041] Here, the amount of data transferred between the data decompression device and the DRAM will be described using a data decompression device according to a comparative example.

[0042] FIG. 2 is a diagram showing the amount of data transferred between a data decompression device and a DRAM according to a comparative example. A data decompression device 15C according to the comparative example includes a decompression unit 32C. The decompression unit 32C decompresses compressed data 61C transferred from DRAM 5C to generate decompressed data 62C. Here, it is assumed that the compression unit is 32 KB and the compression ratio is 2. The DRAM 5C stores 16 KB of compressed data 61C. The 16 KB of compressed data 61C is data obtained by compressing plaintext data in the compression unit (32 KB) at a compression ratio of 2. Note that in FIG. 2, the data actually stored in DRAM 5C is indicated by a diagonal line pattern.

[0043] Consider a case where the host 2C acquires only a 4 KB partial area 622C of the 32 KB decompressed data 62C obtained by decompressing 16 KB compressed data 61C. Two examples of the amount of data transferred between the data decompression device 15C and the DRAM 5C in this case will be described.

[0044] 2(a), the entire 16 KB compressed data 61C is transferred from the beginning to the decompression unit 32C. The decompression unit 32C then decompresses the 16 KB compressed data 61C and transfers the entire 32 KB decompressed data 62C obtained by decompressing the 16 KB compressed data 61C to the DRAM 5C. After the 32 KB decompressed data 62C has been transferred to the DRAM 5C, the host 2C (e.g., the CPU of the host 2C) accesses the 4 KB partial area 622C to be acquired.

[0045] In this case, the total amount of data transferred between the data decompression device 15C and the DRAM 5C is 48 KB (= 16 KB + 32 KB). That is, in the example shown in FIG. 2(a), not only the 4 KB partial area 622C to be acquired but also the partial areas 621C and 623C before and after it are transferred to the DRAM 5C. Therefore, the bandwidth of the DRAM 5C is wasted in transferring the partial areas 621C and 623C to the DRAM 5C.

[0046] 2(b), the entire 16 KB compressed data 61C is transferred from the beginning to the decompression unit 32C, but the data decompression device 15C further includes a selector 331C. The selector 331 selectively transfers only a specified partial area of ​​the decompressed data 62C output from the decompression unit 32C to the DRAM 5C.

[0047] Specifically, the decompression unit 32C sequentially decompresses the compressed data transferred from the DRAM 5C from the beginning, and outputs the decompressed data to the selector 331C.

[0048] The selector 331C receives offset information and size information from the host 2. The offset information and size information are information for identifying the 4 KB partial area 622C to be acquired. More specifically, the offset information indicates the relative position of the start of the partial area 622C with respect to the start of the decompressed data 62C. The size information indicates the size of the partial area 622C (here, 4 KB).

[0049] Based on the offset information and size information, the selector 331C transfers only a 4 KB partial area 622C of the decompressed data output from the decompression unit 32C to the DRAM 5C. In other words, the selector 331C does not transfer the partial areas 621C and 623C before and after the partial area 622C to the DRAM 5C. In FIG. 2(b), the partial area 622C (transferred portion) to be transferred to the DRAM 5C is indicated by a solid line, and the partial areas 621C and 623C (non-transferred portions) not to be transferred to the DRAM 5C are indicated by a dashed line. In this case, the total amount of data transferred between the data decompression device 15C and the DRAM 5C is 20 KB (= 16 KB + 4 KB), which is reduced from the example shown in FIG. 2(a).

[0050] However, in the data decompression device 15C of the comparative example shown in Figure 2(b), even after the partial area 622C to be acquired is transferred to the DRAM 5C, the transfer of compressed data 61C from the DRAM 5C to the decompression unit 32C continues. Therefore, the bandwidth of the DRAM 5C is wasted because compressed data that is not necessary for acquiring the partial area 622C is transferred from the DRAM 5C to the decompression unit 32C. Furthermore, if the compression unit is increased from the perspective of compression efficiency, the wasted bandwidth of the DRAM 5C will become even greater.

[0051] In contrast, the data decompression device 15 according to this embodiment controls to stop the transfer of compressed data from the DRAM 5 to the data decompression device 15 in response to completion of the transfer of the acquisition target partial region of the decompressed data to the DRAM 5. This reduces the amount of data transferred between the data decompression device 15 and the DRAM 5. In other words, the data decompression device 15 can minimize the consumption of the bandwidth of the DRAM 5. Therefore, the data decompression device 15 can efficiently use the bandwidth of the DRAM 5.

[0052] For example, assume that the 4 KB partial area to be acquired appears uniformly and randomly in the 32 KB decompressed data. In this case, it is considered sufficient to acquire, on average, a 4 KB partial area near the center of the 32 KB decompressed data. Therefore, on average, the 4 KB partial area to be acquired in the decompressed data is acquired by decompressing approximately half of the first partial area of ​​the 16 KB compressed data. Therefore, the amount of compressed data transferred from the DRAM 5 to the data decompression device 15 is approximately 8 KB on average. Therefore, by stopping the transfer of the compressed data from the DRAM 5 to the data decompression device 15 upon completion of the transfer of the 4 KB partial area to the DRAM 5, the total amount of data transferred between the data decompression device 15 and the DRAM 5 can be reduced to approximately 12 KB (= 8 KB + 4 KB).

[0053] FIG. 3 is a block diagram showing an example of the configuration and operation of the data decompression device 15. As shown in FIG.

[0054] The data decompression device 15 may acquire information (data) transmitted by the host 2 via, for example, the host I / F 14. The information transmitted by the host 2 includes, for example, an input address 41, an output address 42, and partial decompression position information 43.

[0055] The input address 41 is the starting address of a storage area in the DRAM 5 where the compressed data 61 is stored. In other words, the input address 41 indicates the starting address of the first data buffer 51 in the DRAM 5. The compressed data 61 is stored in the first data buffer 51. In FIG. 3 and the following figures, the data stored in the DRAM 5 is indicated by a diagonal line pattern.

[0056] The output address 42 is the starting address of a storage area in the DRAM 5 that should store a portion of the decompressed data 62 obtained by decompressing the compressed data 61. In other words, the output address 42 indicates the starting address of the second data buffer 52 in the DRAM 5. The decompressed data 62 is data corresponding to a compression unit of data. In the second data buffer 52, a partial area 622 of the decompressed data 62 that is to be acquired by the host 2 is stored in order from the beginning.

[0057] The partial decompression position information 43 is information that specifies the partial decompression position in the decompressed data 62 that is to be acquired by the host 2. One partial decompression position represents one partial area 622 in the decompressed data 62.

[0058] FIG. 4 shows an example of the structure of the decompression data 62 for specifying the partial decompression position.

[0059] The decompressed data 62 of a compression unit (i.e., the uncompressed data of a compression unit) includes L data portions each having a first size. In other words, the first size is 1 / L of the compression unit. Each of the L data portions is a data unit for specifying data to be acquired from the decompressed data 62. Hereinafter, the data portions of the first size included in the decompressed data 62 will also be referred to as decompressed data portions. The L decompressed data portions are assigned numbers ranging from 0 to (L-1), for example, in order from the beginning. One partial decompression position representing one decompressed data portion 622 to be acquired by the host 2 can be specified using, for example, one of the numbers ranging from 0 to (L-1).

[0060] 4, the compression unit is 32 KB, and the first size is 4 KB. In this case, the decompressed data 62 includes eight decompressed data portions. That is, the decompressed data 62 includes the first to eighth decompressed data portions. The eight decompressed data portions are assigned numbers from 0 to 7, respectively, starting from the top. Therefore, one partial decompression position (decompressed data portion 622) to be acquired by the host 2 can be specified using, for example, one of the numbers from 0 to 7.

[0061] 5A and 5B show a first example of the partial decompression position information 43 and a second example of the partial decompression position information 43 in the data decompression device 15. In FIG.

[0062] The partial decompression position information 43 may specify M partial decompression positions. The number M of partial decompression positions is, for example, an integer between 1 and (L-1). The M partial decompression positions are arranged in the partial decompression position information 43 in order of proximity to the beginning of the decompressed data 62, for example.

[0063] 5(a), in the partial decompression position information 43, for example, a number indicating the decompressed data portion 622 is specified. The decompressed data portion 622 to which the specified number is assigned is the decompressed data portion 622 to be acquired by the host 2. In the partial decompression position information 43, numbers from 1 to (L-1) can be specified.

[0064] When the decompressed data 62 includes eight decompressed data portions, the bit length of the information specifying the number assigned to each decompressed data portion is three bits. Specifically, for example, when the fourth decompressed data portion from the beginning is designated as the decompressed data portion 622 to be acquired, the partial decompression position information 43 includes "0x3," which indicates the number "3" assigned to the fourth decompressed data portion. For example, when the first and third decompressed data portions from the beginning are designated as the decompressed data portions 622 to be acquired, the partial decompression position information 43 includes "0x0" and "0x2," which indicate the numbers "0" and "2" assigned to the first and third decompressed data portions, respectively. Therefore, the partial decompression position information 43 can specify from one to a maximum of seven decompressed data portions 622 to be acquired, with three bits of information per decompressed data portion.

[0065] Alternatively, as shown in FIG. 5(b), the partial decompression position information 43 may be bitmap information indicating whether or not each of the L decompressed data portions needs to be acquired. The bit length of the bitmap information is L bits. The L-bit bit strings included in the bitmap information correspond to the L decompressed data portions, respectively. More specifically, the L-bit bit strings correspond to the numbers from 0 to (L-1) assigned to the L decompressed data portions, respectively. In the L-bit bit string, for example, "1" is set to the bit corresponding to the decompressed data portion 622 to be acquired. Furthermore, for example, "0" is set to the bit corresponding to the decompressed data portion not to be acquired.

[0066] When the decompressed data 62 includes eight decompressed data portions, the partial decompression position information 43 is 8-bit bitmap information. For example, if the fourth decompressed data portion from the beginning is the target of acquisition and the other decompressed data portions are not, in the 8-bit bitmap information, the bit corresponding to the number "3" assigned to the fourth decompressed data portion from the beginning is set to "1," and the remaining seven bits are set to "0." That is, in this case, the partial decompression position information 43 is "8'b00010000." Note that a data string of bit values ​​of 0 or 1 following "X'b" indicates an X-bit bit data string. In "8'b00010000," the most significant bit (MSB) corresponds to the first decompressed data portion (the decompressed data portion assigned the number "0"), and the least significant bit (LSB) corresponds to the eighth decompressed data portion (the decompressed data portion assigned the number "7").

[0067] By receiving such partial decompression position information 43 from the host 2, the data decompression device 15 can identify the decompressed data portion 622 (partial decompression position) to be acquired by the host 2.

[0068] Return to Figure 3.

[0069] The data decompression device 15 is configured to read data from the DRAM 5 and write data to the DRAM 5, for example, via the DRAM I / F 13. That is, the data decompression device 15 is configured to control data transfer from and to the DRAM 5. Furthermore, the data decompression device 15 is configured to decompress the compressed data 61 read from the DRAM 5 in sequence from the beginning, and generate decompressed data 62 in sequence from the beginning. When the decompressed data portion 622 to be acquired within the decompressed data 62 is designated by the partial decompression position information 43, the data decompression device 15 controls to stop the transfer of the compressed data 61 from the DRAM 5 to the data decompression device 15 in response to completion of the transfer of the decompressed data portion 622 to be acquired to the DRAM 5.

[0070] The data decompression device 15 includes, for example, a read control unit 31, a decompression unit 32, and a write control unit 33. The components of the data decompression device 15, such as the read control unit 31, the decompression unit 32, and the write control unit 33, are realized by at least one of, for example, a register, a memory, an adder, a multiplier, a selector, and other arithmetic units. The register is realized by, for example, a sequential circuit such as a flip-flop. The memory is realized by, for example, a storage element such as an SRAM or a DRAM. The adder, multiplier, selector, and other arithmetic units are realized by, for example, a combinational logic circuit.

[0071] The read control unit 31 is a circuit that controls the reading (transfer) of compressed data 61 from the DRAM 5. The read control unit 31 reads the compressed data 61 from the DRAM 5 sequentially from the beginning, and outputs the read compressed data 61 to the decompression unit 32 one by one.

[0072] The decompression unit 32 is a circuit that generates decompressed data 62 by sequentially decompressing the compressed data 61 received from the read control unit 31. The decompression unit 32 generates decompressed data 62 obtained by decompressing the compressed data 61, sequentially from the beginning. The decompression unit 32 sequentially outputs the generated decompressed data 62 to the write control unit 33.

[0073] The write control unit 33 is a circuit that controls the writing (transfer) of the decompressed data 62 output by the decompression unit 32 to the DRAM 5 and the output of the partial area transfer completion signal 45 to the read control unit 31. The partial area transfer completion signal 45 is a signal that causes the read control unit 31 to stop reading the compressed data 61 from the DRAM 5.

[0074] The write control unit 33 includes, for example, a selector 331 and a transfer completion detection unit 332. The selector 331 selectively writes only the decompressed data portion 622 specified by the host 2 out of the decompressed data 62 output by the decompression unit 32 to the DRAM 5. The transfer completion detection unit 332 outputs a partial area transfer completion signal 45 to the read control unit 31 in response to the completion of writing of all the decompressed data portions 622 specified by the host 2 to the DRAM 5.

[0075] The operations of the read control unit 31, the decompression unit 32, and the write control unit 33 will be described in more detail below. The following mainly illustrates a case where the compression unit is 32 KB, the compression ratio is 2, and the size of one decompressed data portion (first size) is 4 KB. 16 KB of compressed data 61 is stored in the DRAM 5. The 16 KB of compressed data 61 is data obtained by compressing plaintext data of a compression unit (32 KB) at a compression ratio of 2. The decompressed data 62 obtained by decompressing the entire 16 KB of compressed data 61 is 32 KB of data. The 32 KB of decompressed data 62 includes eight 4 KB decompressed data portions. Therefore, these eight 4 KB decompressed data portions are respectively identified by eight partial decompression positions indicated by numbers from 0 to 7, for example. Here, it is assumed that the partial decompression position information 43 is “0x3,” which specifies the decompressed data portion 622 corresponding to the fourth partial decompression position of the eight partial decompression positions.

[0076] The read control unit 31 and the write control unit 33 receive the input address 41, the output address 42, and the partial decompression position information 43 sent by the host 2 ((1) in FIG. 3). Specifically, the read control unit 31 receives the input address 41. Furthermore, the write control unit 33 receives the output address 42 and the partial decompression position information 43.

[0077] The read control unit 31 transmits an input transfer request 44 to the DRAM 5 to read the compressed data 61 stored in a storage area (first data buffer 51) in the DRAM 5, starting from the input address 41, sequentially from the beginning, for example, in units of the second size ((2) in FIG. 3). The input transfer request 44 is a request to the DRAM 5 to transfer a data portion of the second size (hereinafter also referred to as a compressed data portion) included in the compressed data 61 to the read control unit 31. The second size may be smaller than the compression unit and smaller than the first size. The second size is a size that can be set arbitrarily, for example, 512 B (bytes) or 1 KB. The input transfer request 44 specifies, for example, the beginning address and size of the storage area in which the compressed data portion to be transferred is stored. For example, the input transfer request 44 that the read control unit 31 initially transmits to the DRAM 5 to read the compressed data 61 specifies the input address 41 and the second size.

[0078] The read control unit 31 receives the compressed data portion read in response to the transmitted input transfer request 44 from the DRAM 5 ((3) in FIG. 3). Then, the read control unit 31 outputs the received compressed data portion to the decompression unit 32 ((4) in FIG. 3).

[0079] The decompression unit 32 generates decompressed data by decompressing the compressed data portion received from the read control unit 31, and outputs the generated decompressed data to the write control unit 33 ((5) in FIG. 3). The decompression unit 32 generates decompressed data 62 sequentially from the beginning by decompressing the compressed data portion that is part of the compressed data 61 sequentially from the beginning.

[0080] Based on the partial decompression position information 43 and the output address 42, the selector 331 of the write control unit 33 writes only the decompressed data portion 622 of the decompressed data output by the decompression unit 32 that corresponds to the partial decompression position specified by the partial decompression position information 43 to a storage area (second data buffer 52) starting from the output address 42 in the DRAM 5 ((6) in FIG. 3). Specifically, the selector 331 does not write the 12 KB decompressed data portion 621 of the decompressed data output by the decompression unit 32 that corresponds to the partial decompression positions not specified by the partial decompression position information 43 (the first to third partial decompression positions in FIG. 3). Then, the selector 331 writes the 4 KB decompressed data portion 622 of the decompressed data output by the decompression unit 32 that corresponds to the partial decompression position specified by the partial decompression position information 43 (the fourth partial decompression position in FIG. 3) to the DRAM 5. In FIG. 3, the decompressed data portion 622 (transfer portion) that is written to the DRAM 5 is indicated by a solid line, and the decompressed data portions 621 and 623 (non-transfer portions) that are not written to the DRAM 5 are indicated by dashed lines.

[0081] Furthermore, the transfer completion detection unit 332 outputs a partial area transfer completion signal 45 to the read control unit 31 in response to completion of writing to the DRAM 5 of the decompressed data portions corresponding to all of the partial decompression positions specified in the partial decompression position information 43 ((7) in FIG. 3). Specifically, the transfer completion detection unit 332 outputs the partial area transfer completion signal 45 to the read control unit 31 in response to completion of writing of the decompressed data portion 622 to the DRAM 5. That is, the transfer completion detection unit 332 asserts the partial area transfer completion signal 45 in response to completion of writing of the decompressed data portion 622 to the DRAM 5. Note that the transfer completion detection unit 332 may also output the partial area transfer completion signal 45 to the read control unit 31 in response to detection of the decompressed data portions (decompressed data portion 622 in FIG. 3) corresponding to all of the partial decompression positions specified in the partial decompression position information 43 from the decompressed data output by the decompressor 32.

[0082] In response to receiving a partial area transfer completion signal 45 from the transfer completion detection unit 332, the read control unit 31 performs control to stop reading of the compressed data 61 from the DRAM 5. Specifically, the read control unit 31 stops sending an input transfer request 44 to the DRAM 5. The read control unit 31 may also receive a compressed data portion transferred from the DRAM 5 in response to an input transfer request 44 that has already been sent. This is because, if the read control unit 31 does not receive a compressed data portion transferred from the DRAM 5, components related to data transfer, such as the DRAM I / F 13 and bus 10, may be locked. The read control unit 31 discards the received compressed data portion without outputting it to, for example, the decompression unit 32.

[0083] For example, after the transfer completion detection unit 332 outputs the partial area transfer completion signal 45, the host 2 reads the decompressed data portion 622 from the second data buffer 52 in the DRAM 5 and controls the transfer to the host 2. This allows the host 2 to obtain the decompressed data portion 622 specified by the partial decompression position information 43.

[0084] 3, when the read control unit 31 reads an 8 KB compressed data portion 611 from the beginning of the compressed data 61 and the decompression unit 32 decompresses the 8 KB compressed data portion 611, the decompression unit 32 outputs a decompressed data portion 621 and a decompressed data portion 622 to the write control unit 33. In response to the output of the decompressed data portion 622, the selector 331 writes the decompressed data portion 622 to the DRAM 5, and the transfer completion detection unit 332 outputs a partial area transfer completion signal 45 to the read control unit 31. Then, in response to the partial area transfer completion signal 45, the read control unit 31 performs control to stop reading of the compressed data 61 from the DRAM 5.

[0085] As a result, for example, the latter 8 KB compressed data portion 612 of the compressed data 61 is not read from the DRAM 5. In Fig. 3, the compressed data portion 611 (transfer portion) that is read from the DRAM 5 is indicated by a solid line, and the compressed data portion 612 (non-transfer portion) that is not read from the DRAM 5 is indicated by a dashed line.

[0086] Since the 8 KB compressed data portion 612 is not read from the DRAM 5 , the 16 KB decompressed data portion 623 obtained by decompressing the compressed data portion 612 is neither generated by decompression nor written to the DRAM 5 .

[0087] In this way, when the partial decompression position information 43 specifies the decompressed data portion 622 corresponding to the fourth partial decompression position of the eight partial decompression positions, for example, the 4 KB decompressed data portion 622 is transferred from the data decompression device 15 to the DRAM 5, and on average, the 8 KB compressed data portion 611 in the first half of the 16 KB compressed data 61 is transferred from the DRAM 5 to the data decompression device 15. This allows the data decompression device 15 to reduce the total data transfer amount between the data decompression device 15 and the DRAM 5 to about 12 KB (= 4 KB + 8 KB). Therefore, for example, compared with the total data transfer amount of 20 KB between the data decompression device 15C and the DRAM 5C in the comparative example shown in FIG. 2(b), the data decompression device 15 of the first embodiment can reduce the total data transfer amount to 60%.

[0088] Therefore, the data decompression device 15 can efficiently use the bandwidth of the DRAM 5 when acquiring a portion of the decompressed data 62 obtained by decompressing the compressed data 61. Furthermore, by not decompressing the entire compressed data 61, the data decompression device 15 can also reduce the latency in the decompression process by the decompression unit 32 on average.

[0089] Next, the procedure of the process executed in the data decompression device 15 will be described with reference to FIGS.

[0090] 6 is a flowchart showing an example of the procedure of a read control process executed in the data decompression device 15. The read control process is a process for controlling the reading of compressed data from the DRAM 5 to the data decompression device 15. The read control unit 31 of the data decompression device 15 executes the read control process in response to, for example, receiving an input address 41 transmitted by the host 2. It is assumed that compressed data 61 is stored in a first data buffer 51 in the DRAM 5, the first data buffer having the input address 41 as its head.

[0091] First, the read control unit 31 sets a variable i to 1 (step S11). The read control unit 31 can send a plurality of input transfer requests 44 to the DRAM 5 in order to read the compressed data 61 stored in the first data buffer 51 for each second size in order from the beginning. The variable i is a variable for identifying the ith input transfer request 44 from the beginning among the plurality of input transfer requests 44.

[0092] The read control unit 31 transmits the i-th input transfer request 44 to the DRAM 5 (step S12). For example, the first input transfer request 44 is a request to transfer data stored in a second-size storage area (hereinafter referred to as the first storage area) from the beginning of the first data buffer 51 to the read control unit 31. For example, the second input transfer request 44 is a request to transfer data stored in a second-size storage area whose beginning address is immediately after the first storage area to the read control unit 31. The same applies to the third and subsequent input transfer requests 44. In other words, in response to the i-th input transfer request 44, the i-th data portion of the compressed data 61 from the beginning of the second size is transferred to the read control unit 31. Hereinafter, the i-th data portion of the compressed data 61 of the second size will also be simply referred to as the i-th compressed data portion.

[0093] Next, the read control unit 31 determines whether or not the ith compressed data portion transferred in response to the ith input transfer request 44 has been received from the DRAM 5 (step S13). If the ith compressed data portion has not been received from the DRAM 5 (No in step S13), the read control unit 31 returns to step S13. In other words, the read control unit 31 waits until the ith compressed data portion is received from the DRAM 5.

[0094] When the i-th compressed data portion is received from the DRAM 5 (Yes in step S13), the read control unit 31 determines whether or not it has received a partial area transfer completion signal 45 from the write control unit 33 (more specifically, the transfer completion detection unit 332) (step S14).

[0095] If the partial area transfer completion signal 45 has not been received (No in step S14), the read control unit 31 outputs the i-th compressed data portion to the decompression unit 32 (step S15). The output i-th compressed data portion is decompressed by the decompression unit 32, and decompressed data is generated. Then, the read control unit 31 updates the variable i by adding 1 to it (step S16), and returns to step S12. That is, the read control unit 31 transmits the i-th input transfer request 44 to the DRAM 5 based on the updated variable i, and performs processing to receive the i-th compressed data portion from the DRAM 5.

[0096] When the partial area transfer completion signal 45 is received (Yes in step S14), the read control unit 31 discards the i-th compressed data portion (step S17) and ends the read control process.

[0097] Through the above read control process, the read control unit 31 transfers the compressed data 61 from the DRAM 5 in units of the second size sequentially from the beginning and outputs it to the decompression unit 32, from the time it receives the input address 41 sent by the host 2 until it receives the partial area transfer completion signal 45 from the write control unit 33. Then, in response to receiving the partial area transfer completion signal 45, the read control unit 31 performs control to stop reading the compressed data 61 from the DRAM 5. As a result, the remaining compressed data portion of the compressed data 61 is not transferred from the DRAM 5 to the read control unit 31. Therefore, the data decompression device 15 can efficiently use the bandwidth of the DRAM 5.

[0098] 7 is a flowchart showing an example of the procedure of a write control process executed in the data decompression device 15. The write control process is a process for controlling writing of decompressed data from the data decompression device 15 to the DRAM 5. The write control unit 33 of the data decompression device 15 executes the write control process in response to receiving, for example, the output address 42 and the partial decompression position information 43 transmitted by the host 2.

[0099] First, the write control unit 33 acquires M partial decompression positions specified in the received partial decompression position information 43 (step S201). The write control unit 33 sets a variable j to 1 (step S202). The variable j is a variable for specifying the j-th partial decompression position from the beginning among the M partial decompression positions.

[0100] The write control unit 33 monitors the decompressed data output by the decompression unit 32 and determines whether the output decompressed data has reached the beginning of the j-th partial decompression position (step S203). Specifically, the write control unit 33 determines whether the decompressed data output by the decompression unit 32 has reached the beginning of the decompressed data portion 622 (partial area 622) corresponding to the j-th partial decompression position.

[0101] If the decompressed data output by the decompression unit 32 has not reached the beginning of the j-th partial decompression position (No in step S203), that is, if the decompressed data is decompressed data at a position not specified in the partial decompression position information 43, the write control unit 33 discards the decompressed data (step S204) and returns to step S203. That is, the write control unit 33 discards the decompressed data up to just before reaching the beginning of the j-th partial decompression position. Therefore, the write control unit 33 does not transfer the decompressed data corresponding to a position not specified in the partial decompression position information 43 to the DRAM 5.

[0102] When the decompressed data output by the decompression unit 32 reaches the beginning of the j-th partial decompression position (Yes in step S203), the write control unit 33 starts transferring the decompressed data corresponding to the j-th partial decompression position to the DRAM 5 (step S205). Specifically, the write control unit 33 writes the decompressed data to the second data buffer 52 in the DRAM 5, the beginning of which is the output address 42.

[0103] Next, the write control unit 33 determines whether the decompressed data transferred to the DRAM 5 has reached the end of the j-th partial decompression position (step S206). Specifically, the write control unit 33 determines whether the decompressed data output from the decompression unit 32 and transferred to the DRAM 5 has reached the end of the decompressed data portion 622 corresponding to the j-th partial decompression position.

[0104] If the decompressed data transferred to the DRAM 5 has not reached the end of the j-th partial decompression position (No in step S206), the write control unit 33 returns to step S206. That is, the write control unit 33 continues transferring the decompressed data to the DRAM 5 until the decompressed data output from the decompression unit 32 and transferred to the DRAM 5 reaches the end of the j-th partial decompression position.

[0105] If the decompressed data transferred to the DRAM 5 reaches the end of the j-th partial decompression position (Yes in step S206), the write control unit 33 stops transferring the decompressed data to the DRAM 5 (step S207). Then, the write control unit 33 updates the variable j by adding 1 to it (step S208). The write control unit 33 determines whether the updated variable j exceeds the total number M of partial decompression positions (step S209). In other words, the write control unit 33 determines whether the transfer of M decompressed data portions 622 corresponding to the M partial decompression positions, respectively, to the DRAM 5 has been completed.

[0106] If the updated variable j is equal to or less than the total number M of partial decompression positions (No in step S209), the write control unit 33 returns to step S203. That is, the write control unit 33 further performs processing to transfer the decompressed data portion 622 corresponding to the j-th partial decompression position to the DRAM 5 based on the updated variable j.

[0107] If the updated variable j exceeds the total number M of partial decompression positions (Yes in step S209), the write control unit 33 outputs a partial area transfer completion signal 45 to the read control unit 31 (step S210) and ends the write control process. In response to the partial area transfer completion signal 45, the read control unit 31 controls the DRAM 5 to stop reading the stored compressed data 61.

[0108] Through the above write control process, the write control unit 33 transfers to the DRAM 5 (more specifically, the second data buffer 52) only the M decompressed data portions 622 corresponding to the M partial decompression positions specified in the partial decompression position information 43. In other words, the write control unit 33 does not transfer to the DRAM 5 the decompressed data portions corresponding to positions not specified in the partial decompression position information 43.

[0109] Furthermore, in response to the completion of the transfer of the M decompressed data portions 622 to the DRAM 5, the write control unit 33 outputs a partial area transfer completion signal 45 to the read control unit 31. As a result, the read control unit 31 performs control so as to stop reading of the compressed data 61 stored in the DRAM 5.

[0110] Therefore, the data decompression device 15 can use the bandwidth of the DRAM 5 efficiently.

[0111] (Second embodiment) The data decompression device 15 according to the second embodiment includes a configuration for verifying the integrity of the decompressed data in addition to the configuration of the data decompression device 15 according to the first embodiment. The integrity verification is a process for confirming that no data corruption has occurred through the compression and decompression processes, such that the decompressed data does not match the plaintext data from which the compressed data was obtained. Specifically, the data decompression device 15 according to the second embodiment verifies the integrity of the decompressed data portion corresponding to the partial decompression position specified in the partial decompression position information 43.

[0112] In the data decompression device 15C of the comparative example described above with reference to FIG. 2, for example, to verify the integrity of decompressed data 62C, the entire compressed data 61C of a compression unit is transferred from the DRAM 5C to the decompression unit 32C. For example, if the compressed data 61C is in gzip format, the compressed data 61C includes the data size before compression and a checksum value of the data before compression. In this case, the decompression unit 32C decompresses the entire compressed data 61C to generate decompressed data 62C. The decompression unit 32C then verifies the integrity of the decompressed data 62C based on whether the size of the decompressed data 62C matches the data size before compression and whether the checksum value of the decompressed data 62C matches the checksum value of the data before compression.

[0113] As described above, in the data decompression device 15C of the comparative example, in order to verify the integrity of the decompressed data 62C, it is necessary to transfer the entire compressed data 61C from the DRAM 5C to the decompression unit 32C.

[0114] In contrast to this, the data decompression device 15 of the second embodiment has a configuration for verifying the integrity of the decompressed data portion 622 even when control is performed to stop the transfer of the compressed data 61 from the DRAM 5 to the data decompression device 15 in response to completion of transfer of the decompressed data portion 622 to be acquired within the decompressed data 62 to the DRAM 5. In other words, the data decompression device 15 of the second embodiment verifies the integrity of the decompressed data portion 622 without decompressing the entire compressed data 61.

[0115] The configuration of the data decompression device 15 of the second embodiment is similar to that of the data decompression device 15 of the first embodiment. The data decompression device 15 of the second embodiment differs from the data decompression device 15 of the first embodiment in that the data decompression device 15 of the second embodiment further includes a configuration for verifying the integrity of the decompressed data. The following mainly describes the differences from the data decompression device 15 of the first embodiment.

[0116] FIG. 8 is a block diagram showing an example of the configuration and operation of the data decompression device 15 of the second embodiment.

[0117] The data decompression device 15 may acquire information transmitted by the host 2, for example, via the host I / F 14. The information transmitted by the host 2 includes, for example, an input address 41, an output address 42, partial decompression position information 43, and checksum information 46. The input address 41, the output address 42, and the partial decompression position information 43 are as described above with reference to FIGS. 3 to 5.

[0118] The checksum information 46 is information about M checksum values ​​corresponding to the M partial decompression positions specified by the partial decompression position information 43. To confirm that data corruption has not occurred, the file system of the host 2 may, for example, add a checksum value as metadata to each data portion of a first size (e.g., 4 KB) of plaintext data in a compression unit. The plaintext data in a compression unit is the original data from which the compressed data 61 is obtained by compression. The checksum value is, for example, a CRC code calculated by the host 2 using a cyclic redundancy check (CRC) of the corresponding data portion of the first size. For example, CRC-16 or CRC-32 is used as the CRC for calculating the checksum value. The type of CRC used to calculate the checksum value is predetermined, for example, in the information processing system 1 (i.e., the host 2 and the memory system 3). Furthermore, the checksum information 46 about the M checksum values ​​calculated by the host 2 is stored, for example, in the RAM 22 in the host 2. Therefore, the host 2 can provide the data decompression device 15 with M checksum values ​​corresponding to the M partial decompression locations, respectively.

[0119] Specifically, the checksum information 46 includes, for example, M checksum values. That is, the checksum information 46 is information (pass-by-value) for passing the M checksum values ​​themselves to the data decompression device 15. The M checksum values ​​are arranged in order of proximity of the corresponding partial decompression positions to the beginning of the decompressed data 62 (in other words, in order of proximity to the beginning of the original plaintext data).

[0120] Alternatively, the checksum information 46 may be information indicating a storage area in a memory (for example, RAM 22) within the host 2 where the M checksum values ​​are stored. In other words, the checksum information 46 may be information (pointer passing) for passing a pointer to the storage area where the M checksum values ​​are stored to the data decompression device 15. The pointer indicates, for example, the start address of the storage area where the M checksum values ​​are stored.

[0121] Note that pointer passing may also be used when transmitting other information such as partial decompression position information 43 from the host 2 to the data decompression device 15. For example, the partial decompression position information 43 may be information indicating a pointer to a storage area in the host 2 in which information indicating M partial decompression positions is stored.

[0122] The data decompression device 15 includes, for example, a read control unit 31, a decompression unit 32, a write control unit 33, and a verification unit 34. The operations of the read control unit 31 and the decompression unit 32 are as described above with reference to Fig. 3. The operation of the write control unit 33 is as described above with reference to Fig. 3, except that the selector 331 transmits (outputs) the decompressed data portion 622 not only to the DRAM 5 but also to the verification unit 34. The decompressed data portion 622 is decompressed data that corresponds to the partial decompression position specified by the partial decompression position information 43, among the decompressed data output from the decompression unit 32.

[0123] Therefore, operations (1) to (6) and (11) in Figure 8 are the same as operations (1) to (7) in Figure 3, except that in operation (1), the verification unit 34 receives the checksum information 46 sent by the host 2.

[0124] The verification unit 34 is a circuit that verifies the integrity of the decompressed data portion 622 received from the selector 331 using the checksum information 46 sent by the host 2. The verification unit 34 notifies the host 2 of the verification result of the integrity of the decompressed data portion 622.

[0125] The verification unit 34 includes, for example, a checksum acquisition unit 341, a checksum calculation unit 342, and a checksum comparison unit 343. The checksum acquisition unit 341 uses the checksum information 46 to acquire M checksum values ​​corresponding to the M partial decompression positions specified by the partial decompression position information 43. The checksum calculation unit 342 calculates a checksum value for each of the M decompressed data portions 622 received from the selector 331. The checksum comparison unit 343 compares the M checksum values ​​calculated by the checksum calculation unit 342 with the M checksum values ​​acquired by the checksum acquisition unit 341, starting from the top, and notifies the host 2 of the comparison result.

[0126] The operations of the checksum acquisition unit 341, checksum calculation unit 342, and checksum comparison unit 343 will be described in more detail below. The following mainly illustrates a case where the compression unit is 32 KB and the compression ratio is 2. 16 KB of compressed data 61 is stored in the DRAM 5. The decompressed data 62 obtained when the entire 16 KB of compressed data 61 is decompressed is 32 KB of data. The 32 KB of decompressed data 62 includes eight 4 KB decompressed data portions. Here, it is assumed that the partial decompression position information 43 specifies one decompressed data portion 622 corresponding to the fourth partial decompression position of the eight partial decompression positions (i.e., M=1).

[0127] The checksum acquisition unit 341 receives the checksum information 46 sent by the host 2 ((1) in FIG. 8). The checksum acquisition unit 341 acquires the checksum value included in the received checksum information 46. Alternatively, the checksum acquisition unit 341 acquires (transfers) the checksum value from the RAM 22 in the host 2 based on the pointer included in the checksum information 46. The acquired checksum value is also referred to as checksum value A. The checksum acquisition unit 341 outputs the checksum value A to the checksum comparison unit 343 ((7) in FIG. 8).

[0128] The checksum calculation unit 342 receives the decompressed data portion 622 from the selector 331 ((8) in FIG. 8). The checksum calculation unit 342 calculates a checksum value for the received decompressed data portion 622. The calculated checksum value is also referred to as checksum value B. The same CRC (e.g., CRC-16) as the CRC used by the host 2 to calculate checksum value A is used to calculate checksum value B. The checksum calculation unit 342 outputs checksum value B to the checksum comparison unit 343 ((9) in FIG. 8).

[0129] The checksum comparison unit 343 verifies the integrity of the decompressed data portion 622 by comparing the checksum value A received from the checksum acquisition unit 341 with the checksum value B received from the checksum calculation unit 342. Specifically, the checksum comparison unit 343 generates a verification result (comparison result) indicating whether data corruption has occurred in the decompressed data portion 622, depending on whether the checksum value A and the checksum value B match. In other words, if the checksum value A and the checksum value B match, the checksum comparison unit 343 generates a verification result indicating that data corruption has not occurred in the decompressed data portion 622. On the other hand, if the checksum value A and the checksum value B do not match, the checksum comparison unit 343 generates a verification result indicating that data corruption has occurred in the decompressed data portion 622. The checksum comparison unit 343 then notifies the host 2 of the generated verification result ((10) in FIG. 8 ). The checksum comparison unit 343 notifies the host 2 of the verification result by including the verification result in a response (completion) to a request (for example, a command) from the host 2 to acquire the decompressed data portion 622, for example.

[0130] If the partial decompression position information 43 specifies M partial decompression positions, the checksum comparison unit 343 generates M verification results by, for example, comparing each of the M checksum values ​​acquired based on the checksum information 46 with a checksum value calculated from each of the M decompressed data portions 622. The checksum comparison unit 343 notifies the host 2 of the M verification results. The checksum comparison unit 343 may notify the host 2 of either a verification result indicating a decompressed data portion 622 in which data corruption has occurred or a verification result indicating a decompressed data portion 622 in which data corruption has not occurred, out of the M verification results.

[0131] Alternatively, the checksum comparator 343 may notify the host 2 of a verification result based on the M verification results indicating either that no data corruption has occurred in any of the M decompressed data portions 622 or that data corruption has occurred in at least one of the M decompressed data portions 622. In this case, the checksum comparator 343 may generate the verification result by comparing the exclusive OR (first exclusive OR) of the M checksum values ​​acquired based on the checksum information 46 with the exclusive OR (second exclusive OR) of the M checksum values ​​calculated from the M decompressed data portions 622, respectively. In other words, if the first exclusive OR and the second exclusive OR match, the checksum comparator 343 notifies the host 2 of the verification result indicating that no data corruption has occurred in any of the M decompressed data portions 622. On the other hand, if the first exclusive OR and the second exclusive OR do not match, the checksum comparison unit 343 notifies the host 2 of a verification result indicating that data corruption has occurred in at least one of the M decompressed data portions 622.

[0132] With the above configuration and operation, the data decompression device 15 can verify the integrity of the decompressed data portion 622 to be acquired, without transferring and decompressing the entire compressed data 61. More specifically, unlike the data decompression device 15C of the comparative example, which verifies the integrity of the entire decompressed data 62C using the pre-compression data size and the checksum value of the pre-compression data included in the compressed data 61C, the data decompression device 15 can verify the integrity of each decompressed data portion 622. This allows the bandwidth of the DRAM 5 to be used efficiently even when acquiring a portion of the decompressed data 62 obtained by decompressing the compressed data 61 (i.e., the decompressed data portion 622) and verifying the integrity of the decompressed data portion 622.

[0133] Next, the procedure of the process executed in the data decompression device 15 will be described.

[0134] The read control process executed in the data decompression device 15 is the same as the read control process described above with reference to the flowchart of FIG.

[0135] 7, the write control process executed in the data decompression device 15 corresponds to the process in which the transfer destination of the decompressed data is changed from only the DRAM 5 to the DRAM 5 and the verification unit 34. That is, in the write control process executed in the data decompression device 15 of the second embodiment, the decompressed data portion 622 corresponding to the partial decompression position specified in the partial decompression position information 43 is transferred not only to the DRAM 5 but also to the verification unit 34.

[0136] 9 is a flowchart showing an example of the procedure of a verification process executed in the data decompression device 15. The verification process is a process for verifying the integrity of decompressed data. The verification unit 34 of the data decompression device 15 executes the verification process, for example, in response to receiving checksum information 46 from the host 2. Here, an example is shown in which the checksum information 46 includes M checksum values ​​corresponding to the M partial decompression positions specified in the partial decompression position information 43.

[0137] First, the verification unit 34 sets a variable k to 1 (step S301). The variable k is a variable for identifying the kth checksum value from the beginning among the M checksum values ​​included in the checksum information 46. The verification unit 34 acquires the kth checksum value (checksum value A) among the M checksum values ​​(step S302).

[0138] Next, the verification unit 34 determines whether or not it has received the decompressed data portion 622 from the write control unit 33 (more specifically, the selector 331) (step S303). This decompressed data portion 622 is the decompressed data portion 622 (hereinafter also referred to as the kth decompressed data portion 622) corresponding to the kth partial decompression position among the M partial decompression positions specified by the partial decompression position information 43.

[0139] If the k-th decompressed data portion 622 has not been received from the write control unit 33 (No in step S303), the verification unit 34 returns to step S303. In other words, the verification unit 34 waits until the k-th decompressed data portion 622 is received from the write control unit 33.

[0140] When the kth decompressed data portion 622 is received from the write control unit 33 (Yes in step S303), the verification unit 34 calculates a checksum value (checksum value B) for the received kth decompressed data portion 622 (step S304).The verification unit 34 then compares checksum value A with checksum value B to determine whether checksum value A and checksum value B match (step S305).

[0141] If the checksum value A and the checksum value B match (Yes in step S305), the verification unit 34 generates a verification result indicating that no data corruption has occurred in the kth decompressed data portion 622 (step S306), and proceeds to step S308.

[0142] If the checksum value A and the checksum value B do not match (No in step S305), the verification unit 34 generates a verification result indicating that data corruption has occurred in the kth decompressed data portion 622 (step S307), and proceeds to step S308.

[0143] Next, the verification unit 34 updates the variable k by adding 1 to it (step S308). Then, the verification unit 34 determines whether the updated variable k exceeds the total number M of checksum values ​​included in the checksum information 46 (step S309). In other words, the verification unit 34 determines whether verification of the integrity of the corresponding decompressed data portion 622 using all M checksum values ​​has been completed.

[0144] If the updated variable k is equal to or less than the total number M of checksum values ​​(No in step S309), the verification unit 34 returns to step S302. That is, the verification unit 34 further performs processing to verify the integrity of the k-th decompressed data portion 622 using the k-th checksum value based on the updated variable k.

[0145] If the updated variable k exceeds the total number M of checksum values ​​(Yes in step S309), the verification unit 34 notifies the host 2 of the verification result of the integrity of the M decompressed data portions 622 (step S310) and ends the verification process. Specifically, the verification unit 34 notifies the host 2 of the verification result by including the verification result of the integrity of the M decompressed data portions 622 in a response to a request from the host 2 to acquire the M decompressed data portions 622, for example.

[0146] Through the above verification process, the verification unit 34 verifies the integrity of the corresponding decompressed data portion 622 using the checksum information 46 acquired from the host 2. This allows the host 2 to acquire the M decompressed data portions 622 corresponding to the M partial decompression positions specified in the partial decompression position information 43, as well as the verification results of the integrity of these M decompressed data portions 622.

[0147] (Third embodiment) The data decompression device 15 according to the second embodiment verifies the integrity of the decompressed data using checksum information 46 received from the host 2. In contrast, the data decompression device 15 according to the third embodiment verifies the integrity of the decompressed data using checksum information included in the decompressed data, without receiving checksum information 46 from the host 2.

[0148] The configuration of the data decompression device 15 of the third embodiment is similar to that of the data decompression device 15 of the first and second embodiments. The data decompression device 15 of the third embodiment differs from the data decompression device 15 of the first and second embodiments in that the data decompression device 15 of the third embodiment has a configuration for verifying the integrity of the decompressed data by a method different from that of the data decompression device 15 of the second embodiment. The following mainly describes the differences from the data decompression device 15 of the first and second embodiments.

[0149] FIG. 10 is a block diagram showing an example of the configuration and operation of a data decompression device 15 according to the third embodiment.

[0150] The data decompression device 15 may acquire information transmitted by the host 2, for example, via the host I / F 14. The information transmitted by the host 2 includes, for example, an input address 41, an output address 42, and partial decompression position information 43. The input address 41, the output address 42, and the partial decompression position information 43 are as described above with reference to FIGS. 3 to 5.

[0151] The data decompression device 15 includes, for example, a read control unit 31, a decompression unit 32, a write control unit 33, and a verification unit 35. The operation of the read control unit 31 is as described above with reference to Fig. 3. The operation of the decompression unit 32 is as described above with reference to Fig. 3, except that the decompressed data (decompressed data portion) that is generated and output includes a checksum value.

[0152] In the memory system 3, a format in which protection information (PI) is added to user data to be written to the NAND flash memory 4 for each specific size may be used.

[0153] 11 shows an example of the data structure of a decompressed data portion including a checksum value. Decompressed data portion 622E is data in a format in which PI72 is added to a first-size decompressed data portion for each specific size. In the following, the first-size decompressed data portion included in decompressed data portion 622E corresponds to decompressed data portion 622 corresponding to the partial decompression position specified by partial decompression position information 43.

[0154] The decompressed data portion 622E includes, for example, N pairs of a user data portion 71 and a PI 72, where N is an integer equal to or greater than 1. The size of the decompressed data portion 622E (hereinafter also referred to as a third size) is larger than the size (first size) of the decompressed data portion 622 that includes only user data by the amount that the decompressed data portion 622E includes N PIs 72.

[0155] The concatenated N user data portions 71 correspond to the decompressed data portion 622 of the first size. That is, one user data portion 71 is at least a part of the decompressed data portion 622. The size of one user data portion 71 (hereinafter also referred to as the fourth size) is obtained by dividing the first size by N. The fourth size is, for example, defined in advance in the memory system 3. For example, if the first size is 4 KB (4096 B (bytes)) and N is 8, the fourth size is 512 B.

[0156] The PI 72 is information for protecting the user data portion 71. The size of the PI 72 is defined as a fifth size. The fifth size is, for example, predefined in the memory system 3. The fifth size is, for example, 8B. The PI 72 includes, for example, a checksum value 721, a tag 722, and a reference tag (Ref. Tag) 723.

[0157] The checksum value 721 is a checksum value calculated for the user data portion 71. The checksum value 721 is, for example, a CRC code according to CRC-16. The checksum value 721 is also called a sector CRC 721.

[0158] Tag 722 contains data that is not interpreted by controller 6 and can be used to override the checks of PI 72.

[0159] The Ref. Tag 723 includes information for associating the user data portion 71 with an address. The Ref. Tag 723 includes, for example, at least a part of the LBA specified in a write request (write command) received from the host 2 along with the N user data portions 71.

[0160] 11 shows an example in which the decompressed data portion 622E includes eight pairs of user data portions 71 and PIs 72 (i.e., N=8), the size of the user data portion 71 (fourth size) is 512 B, and the size of the PIs 72 (fifth size) is 8 B. In this case, the size of the decompressed data portion 622E (third size) is 4160 B (= (512 B + 8 B) × 8).

[0161] In the decompressed data portion 622E having such a data structure, the checksum value 721 included in the PI 72 can be used to verify the integrity of the corresponding user data portion 71. That is, in the decompressed data portion 622E, the N checksum values ​​721 can be used to verify the integrity of the N user data portions 71.

[0162] Return to Figure 10.

[0163] 11 to the write control unit 33. In other words, the decompression unit 32 outputs the decompressed data, in which a PI 72 is added to each user data portion 71 of the fourth size, to the write control unit 33.

[0164] Therefore, when the partial decompression position specified in the partial decompression position information 43 corresponds to the decompressed data portion 622, the selector 331 of the write control unit 33 transfers the decompressed data portion 622E (i.e., decompressed data including N PIs 72) output from the decompression unit 32 to the DRAM 5. In this case, the host 2 can transfer the decompressed data portion 622E from the DRAM 5 and perform processing using the PIs 72 included in the decompressed data portion 622E. In addition, the selector 331 outputs the decompressed data portion 622E output from the decompression unit 32 to the verification unit 35.

[0165] Therefore, the operations (1) to (6) and (12) in Figure 10 are the same as the operations (1) to (7) in Figure 3, except that the selector 331 transfers the decompressed data portion 622E output from the decompression unit 32 to the DRAM 5.

[0166] The verification unit 35 is a circuit that verifies the integrity of the decompressed data portion 622 using the decompressed data portion 622E received from the selector 331. Specifically, the verification unit 35 verifies the integrity of the N user data portions 71 using, for example, the N checksum values ​​721 included in the decompressed data portion 622E. The verification unit 35 notifies the host 2 of the verification result of the integrity of the decompressed data portion 622.

[0167] The verification unit 35 includes, for example, a checksum acquisition unit 351, a checksum calculation unit 352, and a checksum comparison unit 353. The checksum acquisition unit 351 acquires N user data portions 71 and N checksum values ​​721 from the decompressed data portion 622E. The checksum calculation unit 352 calculates a checksum value for each of the N user data portions 71 acquired by the checksum acquisition unit 351. The checksum comparison unit 353 compares each of the N checksum values ​​721 acquired by the checksum acquisition unit 351 with each of the N checksum values ​​calculated by the checksum calculation unit 352, starting from the top, and notifies the host 2 of the comparison results.

[0168] The operations of the checksum acquisition unit 351, the checksum calculation unit 352, and the checksum comparison unit 353 will now be described in more detail.

[0169] The checksum acquisition unit 351 receives the decompressed data portion 622E output by the selector 331 ((7) in FIG. 10). The checksum acquisition unit 351 acquires N user data portions 71 and N checksum values ​​721, starting from the beginning of the received decompressed data portion 622E. The acquired checksum value 721 is also referred to as checksum value C. The checksum acquisition unit 351 outputs the N checksum values ​​C to the checksum comparison unit 353 ((8) in FIG. 10). The checksum acquisition unit 351 also outputs the acquired N user data portions 71 to the checksum calculation unit 352 ((9) in FIG. 10).

[0170] The checksum calculation unit 352 calculates N checksum values ​​corresponding to the N user data portions 71 received from the checksum acquisition unit 351. The calculated checksum value is also referred to as checksum value D. The same CRC (e.g., CRC-16) as the CRC used to calculate the checksum value C in the memory system 3 is used to calculate the checksum value D. The checksum calculation unit 352 outputs the N checksum values ​​D to the checksum comparison unit 353 ((10) in FIG. 10).

[0171] The checksum comparison unit 353 compares, starting from the beginning, each of the N checksum values ​​C received from the checksum acquisition unit 351 with each of the N checksum values ​​B received from the checksum calculation unit 352, thereby verifying the integrity of each of the N user data portions 71. The checksum comparison unit 353 then generates N verification results corresponding to the N user data portions 71, respectively.

[0172] Specifically, the checksum comparison unit 353 generates a verification result indicating whether data corruption has occurred in the first user data portion 71 of the N user data portions 71, depending on whether the first checksum value C of the N checksum values ​​C matches the first checksum value D of the N checksum values ​​D. That is, if the first checksum value C matches the first checksum value D, the checksum comparison unit 353 generates a verification result indicating that data corruption has not occurred in the first user data portion 71. On the other hand, if the first checksum value C does not match the first checksum value D, the checksum comparison unit 353 generates a verification result indicating that data corruption has occurred in the first user data portion 71. The same applies to the verification of the integrity of the second and subsequent user data portions 71 by the checksum comparison unit 353.

[0173] The checksum comparison unit 353 then notifies the host 2 of the generated verification result ((11) in FIG. 10). The checksum comparison unit 353 notifies the host 2 of the verification result, for example, by including the verification result in a response to a request from the host 2 to acquire the decompressed data portion 622. Specifically, the checksum comparison unit 353 notifies the host 2 of, for example, N verification results. Of the N verification results, the checksum comparison unit 353 may notify the host 2 of either a verification result that indicates a user data portion 71 in which data corruption has occurred or a verification result that indicates a user data portion 71 in which data corruption has not occurred.

[0174] Alternatively, the checksum comparator 353 may notify the host 2 of a verification result based on the N verification results indicating either that no data corruption has occurred in all of the N user data portions 71 (i.e., the entire decompressed data portion 622) or that data corruption has occurred in at least one of the N user data portions 71. In this case, the checksum comparator 353 may generate the verification result by comparing the exclusive OR (third exclusive OR) of the N checksum values ​​C with the exclusive OR (fourth exclusive OR) of the N checksum values ​​D. In other words, if the third exclusive OR and the fourth exclusive OR match, the checksum comparator 353 notifies the host 2 of the verification result indicating that no data corruption has occurred in all of the N user data portions 71. On the other hand, if the third exclusive OR and the fourth exclusive OR do not match, the checksum comparison unit 353 notifies the host 2 of a verification result indicating that data corruption has occurred in at least one of the N user data portions 71.

[0175] If the partial decompression position information 43 specifies M partial decompression positions, the checksum acquisition unit 351, checksum calculation unit 352, and checksum comparison unit 353 generate (N×M) verification results by verifying the integrity of the N user data portions 71 described above for, for example, the decompressed data portions 622E corresponding to each of the M partial decompression positions. The checksum comparison unit 353 notifies the host 2 of, for example, the (N×M) verification results. Based on the (N×M) verification results, the checksum comparison unit 353 may notify the host 2 of either a verification result indicating a decompressed data portion 622 in which data corruption has occurred or a verification result indicating a decompressed data portion 622 in which data corruption has not occurred. Alternatively, the checksum comparison unit 353 may notify the host 2 of a verification result indicating either that no data corruption has occurred in any of the M decompressed data portions 622, or that data corruption has occurred in at least one of the M decompressed data portions 622, based on the (N×M) verification results.

[0176] With the above configuration and operation, the data decompression device 15 can verify the integrity of the N user data portions 71 included in the decompressed data portion 622 to be acquired, without transferring and decompressing the entire compressed data 61. Therefore, the data decompression device 15 can verify the integrity of the decompressed data portion 622 to be acquired. This allows the bandwidth of the DRAM 5 to be used efficiently even when acquiring a portion of the decompressed data 62 obtained by decompressing the compressed data 61 (i.e., the decompressed data portion 622) and verifying the integrity of the decompressed data portion 622.

[0177] Next, the processing executed in the data decompression device 15 will be described.

[0178] The read control process executed in the data decompression device 15 is the same as the read control process described above with reference to the flowchart of FIG.

[0179] 7, the write control process executed in the data decompression device 15 corresponds to the process in which the transfer destination of the decompressed data is changed from only the DRAM 5 to the DRAM 5 and the verification unit 35. Note that the decompressed data output from the decompression unit 32 has a PI 72 added to each user data portion 71 of the fourth size. Therefore, the write control unit 33 (more specifically, the selector 331) transfers the decompressed data including the PI 72 output from the decompression unit 32 to the DRAM 5. The write control unit 33 also outputs the decompressed data including the PI 72 output from the decompression unit 32 to the verification unit 35.

[0180] 12 is a flowchart showing an example of the procedure of the verification process executed in the data decompression device 15. The verification unit 35 of the data decompression device 15 executes the verification process in response to receiving the decompressed data portion 622E of the third size from the write control unit 33 (more specifically, the selector 331), for example.

[0181] First, the verification unit 35 acquires N checksum values ​​721 (hereinafter referred to as checksum values ​​C) from the N PIs 72 included in the decompressed data portion 622E, starting from the beginning (step S401). The checksum value 721 included in one PI 72 is the checksum value (sector CRC) of the user data portion 71 paired with that PI 72.

[0182] The verification unit 35 also acquires N user data portions 71 from the decompressed data portion 622E in order from the beginning (step S402), and then calculates N checksum values ​​(hereinafter referred to as checksum values ​​D) corresponding to the acquired N user data portions 71 (step S403).

[0183] The verification unit 35 may perform step S401 after step S402 and step S403, or may perform step S401, step S402, and step S403 in parallel.

[0184] Next, the verification unit 35 compares each of the N checksum values ​​C with each of the N checksum values ​​D in order from the beginning, and determines whether all of the N checksum values ​​C and the N checksum values ​​D match (step S404).

[0185] If all N checksum values ​​C and N checksum values ​​D match (Yes in step S404), the verification unit 35 generates a verification result indicating that no data corruption has occurred in the decompressed data portion 622 (i.e., the N user data portions 71) (step S405), and proceeds to step S407.

[0186] If there are any checksum values ​​that do not match between the N checksum values ​​C and the N checksum values ​​D (No in step S404), the verification unit 35 generates a verification result indicating that data corruption has occurred in the decompressed data portion 622 (step S406) and proceeds to step S407.

[0187] Next, the verification unit 35 notifies the host 2 of the verification result of the integrity of the decompressed data portion 622 (step S407), and ends the verification process. Specifically, the verification unit 35 notifies the host 2 of the verification result by, for example, including the verification result of the integrity of the decompressed data portion 622 in a response to a request from the host 2 to acquire the decompressed data portion 622.

[0188] Through the above verification process, the verification unit 35 verifies the integrity of the N user data portions 71 included in the decompressed data portion 622E of the third size, using the N checksum values ​​721 (sector CRC) included in that decompressed data portion 622E received from the write control unit 33. This allows the host 2 to obtain the decompressed data portion 622 corresponding to the partial decompression position specified in the partial decompression position information 43, as well as the verification result of the integrity of that decompressed data portion 622.

[0189] When M partial decompression positions are specified in the partial decompression position information 43, the verification unit 35 performs verification processing using the above-described decompressed data portion 622E for each of the M decompressed data portions 622 corresponding to the M partial decompression positions. In this case, the verification unit 35 notifies the host 2 of the verification result by including the verification result of the integrity of the M decompressed data portions 622 in a response to a request from the host 2 to acquire the M decompressed data portions 622, for example.

[0190] (Fourth embodiment) The data decompression device 15 according to the first embodiment has a configuration for efficiently using the bandwidth of the DRAM 5 when acquiring a specific partial region 622 (decompressed data portion 622) of decompressed data 62 obtained by decompressing compressed data 61. To acquire the specific partial region 622 of the decompressed data 62, the data decompression device 15 according to the first embodiment decompresses the compressed data 61 sequentially from the beginning.

[0191] Another example of obtaining a partial region of data obtained by sequentially processing the data from the beginning is when data encrypted using a specific encryption method is decrypted. The specific encryption method is, for example, a stream cipher.

[0192] The data decryption device according to the fourth embodiment has a configuration in which the configuration of the data decompression device 15 according to the first embodiment is applied to decryption of data encrypted by a specific encryption method. In other words, the data decryption device according to the fourth embodiment has a configuration for efficiently using the bandwidth of the DRAM 5 when acquiring a specific partial area of ​​decrypted data obtained by decrypting encrypted data.

[0193] The configuration of the data decoding device of the fourth embodiment is similar to that of the data decompression device 15 of the first embodiment. The data decoding device of the fourth embodiment differs from the data decompression device 15 of the first embodiment in that the compression in the data decompression device 15 of the first embodiment is replaced by encryption, and the decompression is replaced by decryption. The following mainly describes the differences from the data decompression device 15 of the first embodiment.

[0194] FIG. 13 is a block diagram showing an example of the configuration and operation of a data decoding device.

[0195] The data decryption device 19 is provided, for example, in the controller 6 of the memory system 3 shown in FIG. 1. The data decryption device 19 is a decoder that decrypts encrypted data 81. The encrypted data 81 is, for example, data transmitted from the host 2 to the memory system 3 or data read from the NAND flash memory 4. For example, the CPU 11 stores the encrypted data 81 read from the NAND flash memory 4 in response to receiving a read command from the host 2 in the DRAM 5 (for example, the first data buffer 51). The data decryption device 19 can read the encrypted data 81 stored in the DRAM 5 and decrypt the read encrypted data 81 to generate decrypted data 82.

[0196] The data decryption device 19 decrypts the encrypted data 81 for each encryption unit. An encryption unit is a group of data that is encrypted at one time. In other words, an encryption unit is a unit in which data is encrypted independently of other data.

[0197] The data decoding device 19 may obtain information transmitted by the host 2, for example, via the host I / F 14. The information transmitted by the host 2 includes, for example, an input address 41, an output address 42, and partial decoding position information 47.

[0198] The input address 41 is the start address of a storage area in the DRAM 5 where the encrypted data 81 is stored. In other words, the input address 41 indicates the start address of the first data buffer 51 in the DRAM 5. The encrypted data 81 is stored in the first data buffer 51.

[0199] The output address 42 is the starting address of a storage area in the DRAM 5 where a portion of the decrypted data 82 obtained by decrypting the encrypted data 81 should be stored. In other words, the output address 42 indicates the starting address of the second data buffer 52 in the DRAM 5. The decrypted data 82 is data corresponding to an encrypted unit of data. In the second data buffer 52, a partial area 822 of the decrypted data 82 to be acquired by the host 2 is stored in order from the beginning.

[0200] The partial decryption position information 47 is information that specifies the partial decryption position in the decrypted data 82 that is to be acquired by the host 2. One partial decryption position represents one partial area 822 in the decrypted data 82. Hereinafter, the partial area 822 will also be referred to as a decrypted data portion 822. Note that the encryption unit and the size (first size) of one decrypted data portion 822 can be set arbitrarily.

[0201] The configuration of the decryption data 82 for specifying the partial decryption position corresponds to, for example, a configuration in which compression is replaced with encryption and decryption is replaced with decryption in the configuration of the decryption data 62 for specifying the partial decryption position described above with reference to Fig. 4. A specific example of the partial decryption position information 47 is the same as the example of the partial decryption position information 43 described above with reference to Fig. 5, with decryption replaced with decryption.

[0202] The data decryption device 19 is configured to read data from the DRAM 5 and write data to the DRAM 5, for example, via the DRAM I / F 13. That is, the data decryption device 19 is configured to control data transfer from and to the DRAM 5. Furthermore, the data decryption device 19 is configured to decrypt encrypted data 81 read from the DRAM 5 in sequence from the beginning, and generate decrypted data 82 in sequence from the beginning. When a decrypted data portion 822 to be acquired within the decrypted data 82 is designated by the partial decryption position information 47, the data decryption device 19 controls to stop the transfer of the encrypted data 81 from the DRAM 5 to the data decryption device 19 in response to completion of the transfer of the decrypted data portion 822 to be acquired to the DRAM 5.

[0203] The data decoding device 19 includes, for example, a read control unit 31, a decoding unit 36, and a write control unit 33. The components in the data decoding device 19, such as the read control unit 31, the decoding unit 36, and the write control unit 33, are realized by, for example, at least one of a register, a memory, an adder, a multiplier, a selector, and other arithmetic units.

[0204] The read control unit 31 is a circuit that controls the reading (transfer) of encrypted data 81 from the DRAM 5. The read control unit 31 reads the encrypted data 81 from the DRAM 5 sequentially from the beginning, and outputs the read encrypted data 81 to the decryption unit 36 ​​one by one.

[0205] The decryption unit 36 ​​is a circuit that generates decrypted data 82 by sequentially decrypting the encrypted data 81 received from the read control unit 31. The decryption unit 36 ​​generates decrypted data 82 obtained by decrypting the encrypted data 81, sequentially from the beginning. The decryption unit 36 ​​sequentially outputs the generated decrypted data 82 to the write control unit 33.

[0206] The write control unit 33 is a circuit that controls the writing (transfer) of the decrypted data 82 output by the decryption unit 36 ​​to the DRAM 5 and the output of the partial area transfer completion signal 45 to the read control unit 31. The partial area transfer completion signal 45 is a signal that causes the read control unit 31 to stop reading the encrypted data 81 from the DRAM 5.

[0207] The write control unit 33 includes, for example, a selector 331 and a transfer completion detection unit 332. The selector 331 selectively writes only the decoded data portion 822 specified by the host 2 out of the decoded data 82 output by the decoding unit 36 ​​to the DRAM 5. The transfer completion detection unit 332 outputs a partial area transfer completion signal 45 to the read control unit 31 in response to the completion of writing of all the decoded data portions 822 specified by the host 2 to the DRAM 5.

[0208] Here, the encryption method used in the data decryption device 19 will be explained.

[0209] 14 shows (a) an example of encryption of plaintext data and (b) an example of decryption of encrypted data 81 in an encryption method used in data decryption device 19. Here, a case where the encryption method used in data decryption device 19 is a stream encryption is illustrated. Note that the encryption method may be another method that processes data sequentially from the beginning.

[0210] As shown in Fig. 14(a), when plaintext data 80 is encrypted in a stream cipher, a key sequence 93 having the same length as the plaintext data 80 is generated. The key sequence 93 is generated in an initial state (i.e., the first internal state) using a key 91 and an initial value 92. The next value (next generation unit) of the key sequence 93 is generated based on the next internal state obtained by transitioning the internal state using a specific function. The initial state is determined based on the key 91 and the initial value 92.

[0211] Then, an exclusive OR operation is performed on the generated key sequence 93 and the plaintext data 80 to generate encrypted data 81. The encrypted data 81 basically has the same length as the plaintext data 80.

[0212] 14(b), when encrypted data 81 is decrypted, a key sequence 93 having the same length as the encrypted data 81 is generated. In its initial state, the key sequence 93 is generated using the same key 91 and initial value 92 as those used in encryption. The next value of the key sequence 93 is generated based on the next internal state obtained by transitioning the internal state using a specific function. In this way, by using the same key 91 and initial value 92 as those used in encryption and the same key generation method, the key sequence 93 used in encrypting the plaintext data 80 can be obtained.

[0213] Then, decrypted data 82 is generated by performing an exclusive OR operation on the generated key series 93 and the encrypted data 81. If the processes from encryption to decryption are performed without error, decrypted data 82 that is identical to plaintext data 80 can be obtained. The decrypted data 82 basically has the same length as the encrypted data 81.

[0214] In this way, in the stream cipher, a key series 93 is generated sequentially from the first value using a key 91 and an initial value 92. Therefore, the data decryption device 19 using the stream cipher sequentially decrypts the encrypted data 81 from the beginning to obtain a specific partial region 822 (decrypted data portion 822) of the decrypted data 82. Therefore, similar to the data decompression device 15 of the first embodiment, the data decryption device 19 has a configuration for efficiently using the bandwidth of the DRAM 5 when obtaining a specific partial region 822 of the decrypted data 82 obtained by decrypting the encrypted data 81.

[0215] Returning to FIG. 13 , the operations of the read control unit 31, the decryption unit 36, and the write control unit 33 will be described in more detail. The following mainly illustrates a case where the encryption unit is 32 KB and the size (first size) of one decrypted data portion is 4 KB. 32 KB of encrypted data 81 is stored in the DRAM 5. The 32 KB of encrypted data 81 is data obtained by encrypting the encryption unit (32 KB) of plaintext data 80. The decrypted data 82 obtained by decrypting the entire 32 KB of encrypted data 81 is 32 KB of data. In other words, the encrypted data 81 and the decrypted data 82 have, for example, the same size. The 32 KB of decrypted data 82 includes eight 4 KB decrypted data portions. Therefore, these eight 4 KB decrypted data portions are respectively identified by eight partial decryption positions indicated by, for example, numbers 0 to 7. Here, it is assumed that the partial decryption position information 47 specifies the decrypted data portion 822 corresponding to the fourth partial decompression position among the eight partial decryption positions.

[0216] The read control unit 31 and the write control unit 33 receive the input address 41, the output address 42, and the partial decryption position information 47 sent by the host 2 ((1) in FIG. 13). Specifically, the read control unit 31 receives the input address 41. Furthermore, the write control unit 33 receives the output address 42 and the partial decryption position information 47.

[0217] The read control unit 31 transmits an input transfer request 44 to the DRAM 5 in order to read encrypted data 81 stored in a storage area (first data buffer 51) in the DRAM 5 starting from the input address 41, for example, in units of the second size ((2) in FIG. 13). The input transfer request 44 is a request to the DRAM 5 to transfer a data portion of the second size (hereinafter also referred to as an encrypted data portion) included in the encrypted data 81 to the read control unit 31. The second size may be smaller than the encryption unit and smaller than the first size. The second size is a size that can be set arbitrarily, such as 512 B or 1 KB. The input transfer request 44 specifies, for example, the starting address and size of the storage area in which the encrypted data portion to be transferred is stored. For example, the input transfer request 44 that the read control unit 31 initially transmits to the DRAM 5 in order to read the encrypted data 81 specifies the input address 41 and the second size.

[0218] The read control unit 31 receives the encrypted data portion read in response to the transmitted input transfer request 44 from the DRAM 5 ((3) in FIG. 13). Then, the read control unit 31 outputs the received encrypted data portion to the decryption unit 36 ​​((4) in FIG. 13).

[0219] The decryption unit 36 ​​generates decrypted data by decrypting the encrypted data portion received from the read control unit 31, and outputs the generated decrypted data to the write control unit 33 ((5) in FIG. 13). The decryption unit 36 ​​generates decrypted data 82 sequentially from the beginning by decrypting the encrypted data portion that is part of the encrypted data 81 sequentially from the beginning.

[0220] Based on the partial decoding position information 47 and the output address 42, the selector 331 of the write control unit 33 writes only the decoded data portion 822 of the decoded data output by the decoding unit 36 ​​that corresponds to the partial decoding position specified by the partial decoding position information 47 into a storage area (second data buffer 52) in the DRAM 5 starting from the output address 42 ((6) in FIG. 13). Specifically, the selector 331 does not write the 12 KB decoded data portion 821 of the decoded data output by the decoding unit 36 ​​that corresponds to the partial decoding positions not specified by the partial decoding position information 47 (the first to third partial decoding positions in FIG. 13) into the DRAM 5. Then, the selector 331 writes the 4 KB decoded data portion 822 of the decoded data output by the decoding unit 36 ​​that corresponds to the partial decoding position specified by the partial decoding position information 47 (the fourth partial decoding position in FIG. 3). In FIG. 13, a decoded data portion 822 (transfer portion) that is written to the DRAM 5 is indicated by a solid line, and decoded data portions 821 and 823 (non-transfer portions) that are not written to the DRAM 5 are indicated by dashed lines.

[0221] Furthermore, the transfer completion detection unit 332 outputs a partial area transfer completion signal 45 to the read control unit 31 in response to completion of writing to the DRAM 5 of the decoded data portions corresponding to all the partial decoding positions specified in the partial decoding position information 47 ((7) in FIG. 13). Specifically, the transfer completion detection unit 332 outputs the partial area transfer completion signal 45 to the read control unit 31 in response to completion of writing to the DRAM 5 of the decoded data portion 822. Note that the transfer completion detection unit 332 may also output the partial area transfer completion signal 45 to the read control unit 31 in response to detection of the decoded data portions (the decoded data portion 822 in FIG. 13) corresponding to all the partial decoding positions specified in the partial decoding position information 47 from the decoded data output by the decoding unit 36.

[0222] In response to receiving the partial area transfer completion signal 45 from the transfer completion detection unit 332, the read control unit 31 performs control to stop reading of the encrypted data 81 from the DRAM 5. Specifically, the read control unit 31 stops sending the input transfer request 44 to the DRAM 5. The read control unit 31 may also receive an encrypted data portion transferred from the DRAM 5 in response to an input transfer request 44 that has already been sent. This is because, if the read control unit 31 does not receive an encrypted data portion transferred from the DRAM 5, components related to data transfer, such as the DRAM I / F 13 and bus 10, may be locked. The read control unit 31 discards the received encrypted data portion without outputting it to the decryption unit 36, for example.

[0223] For example, after the partial area transfer completion signal 45 is output from the transfer completion detection unit 332, the host 2 reads the decoded data portion 822 from the second data buffer 52 in the DRAM 5 and controls the read data portion 822 to be transferred to the host 2. This allows the host 2 to obtain the decoded data portion 822 specified by the partial decoding position information 47.

[0224] 13, when the read control unit 31 reads a 16 KB encrypted data portion 811 from the beginning of the encrypted data 81 and the decryption unit 36 ​​decrypts the 16 KB encrypted data portion 811, the decryption unit 36 ​​outputs a decrypted data portion 821 and a decrypted data portion 822 to the write control unit 33. In response to the output of the decrypted data portion 822, the selector 331 writes the decrypted data portion 822 to the DRAM 5, and the transfer completion detection unit 332 outputs a partial area transfer completion signal 45 to the read control unit 31. Then, in response to the partial area transfer completion signal 45, the read control unit 31 performs control to stop reading of the encrypted data 81 from the DRAM 5.

[0225] As a result, for example, the latter 16 KB encrypted data portion 812 of the encrypted data 81 is not read from the DRAM 5. In Fig. 13, the encrypted data portion 811 (transfer portion) that is read from the DRAM 5 is indicated by a solid line, and the encrypted data portion 812 (non-transfer portion) that is not read from the DRAM 5 is indicated by a dashed line.

[0226] Since the 16 KB encrypted data portion 812 is not read from the DRAM 5 , the 16 KB decrypted data portion 823 obtained by decrypting the encrypted data portion 812 is neither generated by decryption nor written to the DRAM 5 .

[0227] In this manner, if the partial decryption position information 47 specifies the decrypted data portion 822 corresponding to the fourth partial decompression position among the eight partial decryption positions, for example, the 4 KB decrypted data portion 822 is transferred from the data decryption device 19 to the DRAM 5, and on average, the first 16 KB encrypted data portion 811 of the 32 KB encrypted data 81 is transferred from the DRAM 5 to the data decryption device 19. This allows the data decryption device 19 to reduce the total data transfer amount between the data decryption device 19 and the DRAM 5 to approximately 20 KB (= 4 KB + 16 KB). For example, in a case where the entire 32 KB encrypted data 81 and the 4 KB decrypted data portion 822 to be acquired are transferred between the data decryption device 19 and the DRAM in the same manner as the data decompression device 15C of the comparative example shown in FIG. 2(b), the total data transfer amount is 36 KB. The data decryption device 19 of the fourth embodiment can reduce the total data transfer amount to approximately 56% compared to this case.

[0228] Therefore, data decryption device 19 can efficiently use the bandwidth of DRAM 5 when acquiring a portion of decrypted data 82 obtained by decrypting encrypted data 81. Furthermore, by not decrypting the entire encrypted data 81, data decryption device 19 can also reduce the latency in the decryption process by decryption unit 36 ​​on average.

[0229] The processing executed by the data decoding device 19 corresponds to the read control processing described above with reference to FIG. 6 and the write control processing described above with reference to FIG. 7, with compression replaced by encryption and decompression replaced by decryption.

[0230] As described above, according to the first to fourth embodiments, the RAM bandwidth can be used efficiently when expanding compressed data or decrypting encrypted data.

[0231] In response to receiving an input address 41 from the host 2, the read control unit 31 transfers compressed data 61 stored in a first storage area (e.g., a first data buffer 51) in RAM (e.g., DRAM 5) starting from the input address 41 to the data decompression device 15. The decompression unit 32 decompresses the transferred compressed data sequentially from the beginning to generate decompressed data. The write control unit 33 receives from the host 2 partial decompression position information 43 that specifies one or more decompressed data portions 622 (i.e., partial decompression positions) to be stored in RAM within the generated decompressed data 62, and an output address 42. The selector 331 of the write control unit 33 transfers the one or more decompressed data portions 622 specified by the partial decompression position information 43 to a second storage area (e.g., a second data buffer 52) in RAM starting from the output address 42. The transfer completion detection unit 332 of the write control unit 33 outputs a partial area transfer completion signal 45 indicating that the transfer of one or more decompressed data portions 622 has been completed to the read control unit 31. In response to receiving the partial area transfer completion signal 45, the read control unit 31 performs control to stop reading of the compressed data 61 stored in the first storage area.

[0232] This allows the data decompression device 15 to reduce the amount of data transfer between the data decompression device 15 and the RAM to a transfer amount equivalent to one or more decompressed data portions 622 and a portion of the compressed data 61 that has been transferred before acquiring the one or more decompressed data portions 622. Therefore, the data decompression device 15 can efficiently use the bandwidth of the RAM when acquiring a portion of the decompressed data 62 obtained by decompressing the compressed data 61.

[0233] The configuration of the data decompression device 15 described above can also be applied to the data decryption device 19 that uses an encryption method such as a stream cipher that encrypts data sequentially from the beginning. Therefore, the data decryption device 19 can efficiently use the RAM bandwidth when acquiring a portion of the decrypted data 82 obtained by decrypting the encrypted data 81.

[0234] Each of the various functions described in the first to fourth embodiments may be realized by a circuit (processing circuit). An example of a processing circuit includes a programmed processor, such as a central processing unit (CPU). This processor performs each of the described functions by executing a computer program (a set of instructions) stored in a memory. This processor may be a microprocessor including electrical circuits. Examples of processing circuits include a digital signal processor (DSP), an application specific integrated circuit (ASIC), a microcontroller, a controller, and other electrical circuit components. Each of the components other than the CPU described in these embodiments may also be realized by a processing circuit.

[0235] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0236] 1...information processing system, 2...host, 3...memory system, 4...NAND flash memory, 5...DRAM, 11...CPU, 12...NAND I / F, 13...DRAM I / F, 14...host I / F, 15...data decompression device, 16...transmission path, 17...SRAM, 18...transmission path, 19...data decoding device, 21...CPU, 22...RAM, 31...read control unit, 32...decompression unit, 33...write control unit, 331...selector, 332...transfer completion detection unit, 34, 35...verification unit, 341, 351...checksum acquisition unit, 342, 352...checksum calculation unit, 343, 353...checksum comparison unit, 36...decryption unit, 41...input address, 42...output address, 43...partial decompression position information, 44...input transfer request, 45...partial area transfer completion signal, 46...checksum information, 61...compressed data, 62...decompressed data, 622...decompressed data portion, 71...user data portion, 72...PI, 721...checksum value (sector CRC), 81...encrypted data, 82...decrypted data, 822...decrypted data portion.

Claims

1. A data decompression device connectable to a host, a read control unit that transfers compressed data stored in a first storage area in a random access memory starting from the first address to the data decompression device in response to receiving the first address from the host; an expansion unit that expands the transferred compressed data in order from the beginning to generate expanded data; in response to receiving from the host first information specifying one or more data portions of the generated decompressed data to be stored in the random access memory and a second address; transferring the one or more data portions designated by the first information to a second storage area in the random access memory starting at the second address; a write control unit that outputs a signal indicating that the transfer of the one or more data portions has been completed to the read control unit; Equipped with In response to receiving the signal, the read control unit controls to stop reading of the compressed data stored in the first storage area. Data decompressor.

2. each of the one or more data portions has a first size; the decompressed data obtained by decompressing the compressed data stored in the first storage area includes a plurality of data portions of the first size, the first information designates a number indicating a position of each of the one or more data portions among the plurality of data portions of the first size; 2. The data decompression device according to claim 1.

3. each of the one or more data portions has a first size; the decompressed data obtained by decompressing the compressed data stored in the first storage area includes a plurality of data portions of the first size, the first information designates whether each of the plurality of data portions of the first size is a data portion to be stored in the random access memory; 2. The data decompression device according to claim 1.

4. the write control unit includes a selector and a transfer completion detection unit; the selector transfers the one or more data portions of the generated decompressed data to the second storage area based on the first information; the transfer completion detection unit outputs the signal to the read control unit in response to completion of transfer of the one or more data portions to the second storage area; 2. The data decompression device according to claim 1.

5. The read control unit In response to receiving the first address, transmitting a transfer request to the random access memory to transfer the compressed data stored in the first storage area in units of a second size in order from the beginning; suspending transmission of the transfer request to the random access memory in response to the signal; 2. The data decompression device according to claim 1.

6. the second size is smaller than the size of each of the one or more data portions; 6. The data decompression device according to claim 5.

7. receiving one or more first checksum values ​​from the host, each corresponding to one or more data portions; calculating one or more second checksum values ​​respectively corresponding to the one or more data portions included in the generated decompressed data; The one or more first checksum values ​​are compared with the one or more second checksum values ​​in order from the beginning, and the verification unit notifies the host of the results of the comparison.

2. The data decompression device according to claim 1.

8. the verification unit receives second information from the host, the second information including the one or more first checksum values; 8. The data decompression device according to claim 7.

9. the host includes a second random access memory; The verification unit receiving second information from the host indicating storage locations within the second random access memory where the one or more first checksum values ​​are stored; transferring the one or more first checksum values ​​from the second random access memory based on the second information; 8. The data decompression device according to claim 7.

10. each of the one or more data portions has a third size; a first data portion of the one or more data portions included in the generated decompressed data includes a plurality of second data portions of a fourth size smaller than the third size; each of the plurality of second data portions includes user data and a third checksum value of the user data; obtaining a plurality of the third checksum values ​​from the plurality of second data portions; obtaining a plurality of pieces of user data respectively included in the plurality of second data portions, and calculating a plurality of fourth checksum values ​​respectively corresponding to the plurality of pieces of user data; The computer further includes a verification unit that notifies the host of the results of comparing the third checksum values ​​with the fourth checksum values ​​in order from the beginning.

2. The data decompression device according to claim 1.

11. a data decompression device according to any one of claims 1 to 10; the random access memory; a non-volatile memory; electrically connected to the nonvolatile memory; reading the compressed data from the nonvolatile memory; a controller that stores the compressed data in the first storage area in the random access memory. Memory system.

12. the host; and the memory system according to claim 11. Information processing system.

13. A data decoding device connectable to a host, a read control unit that transfers encrypted data stored in a first storage area in a random access memory starting from the first address to the data decryption device in response to receiving the first address from the host; a decryption unit that decrypts the transferred encrypted data in order from the beginning to generate decrypted data; in response to receiving from the host first information specifying one or more data portions of the generated decoded data to be stored in the random access memory and a second address; transferring the one or more data portions designated by the first information to a second storage area in the random access memory starting at the second address; a write control unit that outputs a signal indicating that the transfer of the one or more data portions has been completed to the read control unit; Equipped with In response to receiving the signal, the read control unit controls to stop reading of the encrypted data stored in the first storage area. Data decoding device.

14. each of the one or more data portions has a first size; the decrypted data obtained by decrypting the encrypted data stored in the first storage area includes a plurality of data portions of the first size, the first information designates a number indicating a position of each of the one or more data portions among the plurality of data portions of the first size; 14. The data decoding device according to claim 13.

15. each of the one or more data portions has a first size; the decrypted data obtained by decrypting the encrypted data stored in the first storage area includes a plurality of data portions of the first size, the first information designates whether each of the plurality of data portions of the first size is a data portion to be stored in the random access memory; 14. The data decoding device according to claim 13.

16. the write control unit includes a selector and a transfer completion detection unit; the selector transfers the one or more data portions of the generated decoded data to the second storage area based on the first information; the transfer completion detection unit outputs the signal to the read control unit in response to completion of transfer of the one or more data portions to the second storage area; 14. The data decoding device according to claim 13.

17. The read control unit In response to receiving the first address, transmitting a transfer request to the random access memory to transfer the encrypted data stored in the first storage area in units of a second size in order from the beginning; suspending transmission of the transfer request to the random access memory in response to the signal; 14. The data decoding device according to claim 13.

18. the second size is smaller than the size of each of the one or more data portions; 18. The data decoding device according to claim 17.

19. a data decoding device according to any one of claims 13 to 18; the random access memory; a non-volatile memory; electrically connected to the nonvolatile memory; reading the encrypted data from the nonvolatile memory; a controller that stores the encrypted data in the first storage area in the random access memory. Memory system.

20. the host; and the memory system of claim 19. Information processing system.

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