Clock signal generation circuit, power supply control device, and switching power supply device

Abstract

Reduce radiated noise through frequency spreading of clock signals. [Solution] The clock signal generation circuit (10) includes a first modulation signal generation circuit (11) that generates a first modulation signal (Sm1) having a first frequency (f1), a second modulation signal generation circuit (12) that generates a second modulation signal (Sm2) having a second frequency (f2) lower than the first frequency, a signal synthesis circuit (13) that generates a synthetic modulation signal (Smc) by synthesizing the first modulation signal and the second modulation signal, and an oscillator (14) that generates a clock signal (CLK) having a frequency corresponding to the synthetic modulation signal.

Description

[Technical Field]

[0001] The present disclosure relates to a clock signal generation circuit, a power supply control device, and a switching power supply device. [Background technology]

[0002] Clock signal generation circuits that generate clock signals are incorporated into a variety of devices. For example, there is a switching power supply unit (DC / DC converter) that performs DC / DC conversion using the frequency of the clock signal as the switching frequency. When the frequency of the clock signal is fixed, the radiated noise at that frequency increases. Spread spectrum technology is a technology that can suppress the effects of radiated noise. Spread spectrum technology spreads noise over a wide band, making it possible to effectively suppress the effects of noise. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2023 / 286459

[0004] [overview] However, there is room for improvement in current spread spectrum techniques for clock signals.

[0005] A clock signal generation circuit according to one embodiment of the present disclosure includes a first modulation signal generation circuit configured to generate a first modulation signal having a first frequency, a second modulation signal generation circuit configured to generate a second modulation signal having a second frequency lower than the first frequency, a signal synthesis circuit configured to generate a synthesized modulation signal by synthesizing the first modulation signal and the second modulation signal, and an oscillator configured to generate a clock signal having a frequency corresponding to the synthesized modulation signal. [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 is a diagram illustrating the overall configuration of a switching power supply device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a waveform diagram of a first modulated signal according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a waveform diagram of a second modulated signal according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a waveform diagram of a composite modulated signal according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a configuration diagram of a first modulation signal generating circuit according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a configuration diagram of a signal synthesis circuit according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a waveform diagram of a modulated current serving as a second modulated signal according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a circuit diagram for generating a composite modulated signal according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is an explanatory diagram of the noise reduction effect according to the embodiment of the present disclosure. [Figure 10] FIG. 10 is a schematic configuration diagram of a switching power supply device according to a second example of an embodiment of the present disclosure. [Figure 11] FIG. 11 is an external perspective view of a power supply control device according to a second example of the embodiment of the present disclosure. [Figure 12] FIG. 12 is a detailed configuration diagram of a switching power supply device according to a second example of an embodiment of the present disclosure. [Figure 13] FIG. 13 is a diagram showing the relationship between a clock signal and two gate signals according to a second example belonging to an embodiment of the present disclosure. [Figure 14] FIG. 14 is a configuration diagram of a switching power supply device according to a first reference configuration. [Figure 15] FIG. 15 is a configuration diagram of a switching power supply device according to the second reference configuration.

[0007] [Detailed explanation] Prior to describing the switching power supply device according to the embodiment of the present disclosure, switching power supply devices according to first and second reference configurations will be described.

[0008] Fig. 14 shows the configuration of a switching power supply 1100 according to a first reference configuration. The switching power supply 1100 includes an oscillator 1110 and a converter 1120. In the switching power supply 1100, a fixed-frequency clock signal 1112 is output from the oscillator 1110 and supplied to the converter 1120. The converter 1120 generates an output voltage Vout by performing a switching operation on an input voltage Vin using the frequency of the clock signal 1112 as a switching frequency. The input voltage Vin and the output voltage Vout are different DC voltages. In the configuration of Fig. 14, large noise is generated at the frequency of the clock signal 1112, and this noise can cause degradation of EMI (Electro Magnetic Interference) characteristics.

[0009] FIG. 15 shows the configuration of a switching power supply 1200 according to a second reference configuration. The switching power supply 1200 includes a triangular wave generating circuit 1210, an oscillator 1220, and a converter 1230. A triangular wave signal 1212 is output from the triangular wave generating circuit 1210. The oscillator 1220 supplies a clock signal 1222 having a frequency corresponding to the value of the triangular wave signal 1212 to the converter 1230. The converter 1230 is a circuit similar to the converter 1120 shown in FIG. 14 and generates an output voltage Vout from an input voltage Vin by switching synchronized with the clock signal 1222. By modulating the frequency of the clock signal 1222 based on the triangular wave signal 1212, the second reference configuration reduces radiation noise at the switching frequency compared to the first reference configuration. However, the second reference configuration generates new noise at the triangular wave frequency and its harmonic frequencies, which becomes a new cause of EMI characteristic degradation.

[0010] In consideration of these circumstances, embodiments of the present disclosure are described below. In each drawing referred to in the embodiments of the present disclosure, identical parts are designated by the same reference numerals, and redundant explanations of identical parts are generally omitted. For the sake of simplicity, this specification may use symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components, and may omit or abbreviate the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs. For example, the first modulation signal generation circuit referred to by "11" below (see FIG. 1) may be written as the first modulation signal generation circuit 11, or may be abbreviated as the modulation signal generation circuit 11, the generation circuit 11, or the circuit 11, but all of these refer to the same thing.

[0011] Some terms used in describing the embodiments of the present disclosure will be explained below. Ground refers to a reference conductor having a reference potential of 0V (zero volts), or refers to the 0V potential itself. The reference conductor may be formed using a conductor such as metal. The 0V potential may also be referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a specific reference represents the potential seen from ground. Level refers to the level (height) of potential, and for any given signal or voltage, a high level has a higher potential than a low level. For any given signal or voltage, a transition from a low level to a high level may be referred to as a rising edge, and a transition from a high level to a low level may be referred to as a falling edge.

[0012] For any transistor configured as a FET (field effect transistor) exemplified by a MOSFET, the on-state refers to a state in which the drain and source of the transistor are conducting, and the off-state refers to a state in which the drain and source of the transistor are non-conducting (blocked state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. MOSFET is an abbreviation of "metal-oxide-semiconductor field-effect transistor". Also, unless otherwise specified, in any MOSFET, the back gate may be considered to be short-circuited to the source. Hereinafter, for any transistor, the on-state and off-state may also be simply expressed as on and off, respectively.

[0013] For any signal having a high-level or low-level signal level, the period during which the level of the signal is high is referred to as the high-level period, and the period during which the level of the signal is low is referred to as the low-level period. The same applies to any voltage having a high-level or low-level voltage level.

[0014] Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection.

[0015] When any two voltages to be compared are voltage v1 and v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0016] FIG. 1 shows a schematic overall configuration of a switching power supply 1 according to an embodiment of the present disclosure. The switching power supply 1 includes a clock signal generation circuit 10 and a converter 20. An input voltage Vin is supplied to the switching power supply 1 from a DC voltage source (not shown). The switching power supply 1 generates an output voltage Vout by power conversion of the input voltage Vin (i.e., converts the input voltage Vin to the output voltage Vout). The input voltage Vin and the output voltage Vout are different positive DC voltages. The output voltage Vout may be lower or higher than the input voltage Vin. In other words, the switching power supply 1 may be a step-down switching power supply, a step-up switching power supply, or a step-up / step-down switching power supply. The clock signal generation circuit 10 and the converter 20 are driven based on the input voltage Vin. Some circuits in the clock signal generation circuit 10 and the converter 20 may be driven based on an internal power supply voltage generated based on the input voltage Vin.

[0017] The clock signal generating circuit 10 includes a first modulating signal generating circuit 11, a second modulating signal generating circuit 12, a signal combining circuit 13, an oscillator 14, and a clock controller 15.

[0018] The first modulation signal generating circuit 11 generates a modulation signal Sm1, which is a first modulation signal (first modulation signal), and outputs it to the signal synthesizing circuit 13. The modulation signal Sm1 is a pulsating signal having a predetermined frequency f1, and therefore the signal value of the modulation signal Sm1 fluctuates over time. For the sake of concrete explanation, it is assumed here that the modulation signal Sm1 is a triangular wave signal having a frequency f1, as shown in FIG. 2. However, the triangular wave signal serving as the modulation signal Sm1 does not necessarily have a strictly triangular waveform, and may have a waveform approximating a triangular wave. The modulation signal Sm1 may be a sine wave signal having a sine wave waveform, a pseudo-sine wave signal having a waveform approximating a sine wave waveform, or a mixed signal obtained by mixing a triangular wave signal and a sine wave signal.

[0019] The second modulation signal generating circuit 12 generates a modulation signal Sm2, which is a second modulation signal (second modulation signal), and outputs it to the signal synthesizing circuit 13. The modulation signal Sm2 is a pulsating signal having a predetermined frequency f2, and therefore the signal value of the modulation signal Sm2 fluctuates over time. For the sake of concrete explanation, it is assumed here that the modulation signal Sm2 is a triangular wave signal having a frequency f2, as shown in FIG. 3. However, the triangular wave signal serving as the modulation signal Sm2 does not necessarily have a strictly triangular waveform, and may have a waveform approximating a triangular wave. The modulation signal Sm2 may be a sine wave signal having a waveform similar to a sine wave, a pseudo-sine wave signal having a waveform approximating a sine wave, or a mixed signal obtained by mixing a triangular wave signal and a sine wave signal.

[0020] Frequency f2 is lower than frequency f1. For example, frequency f1 has a frequency range of 1 kHz to 10 kHz (or a frequency nearby), while frequency f2 has a frequency range of several tens of Hz to several hundreds of Hz (or a frequency nearby). The numerical values ​​described here are merely examples, and the values ​​of frequencies f1 and f2 are arbitrary as long as frequency f2 is lower than frequency f1.

[0021] The signal synthesis circuit 13 synthesizes (in other words, mixes) the modulation signals Sm1 and Sm2 to generate a composite modulation signal Smc. The signal synthesis circuit 13 outputs the composite modulation signal Smc to the oscillator 14. Figure 4 shows an example waveform of the composite modulation signal Smc. The composite modulation signal Smc has a signal component with a frequency f1 and a signal component with a frequency f2.

[0022] The oscillator 14 generates and outputs a clock signal CLK having a frequency corresponding to the composite modulation signal Smc. The clock signal CLK is a rectangular wave signal that alternates between high and low levels. The frequency of the clock signal CLK is set to a frequency f CLK It is written as follows.

[0023] The oscillator 14 includes a VCO 4a, which is a voltage controlled oscillator. The composite modulation signal Smc is input to the VCO 4a. The composite modulation signal Smc is an analog voltage signal. The VCO 4a converts the composite modulation signal Smc into a signal having a frequency f CLK Convert to frequency f CLK The clock signal CLK having a frequency f CLK increases as the voltage value of the composite modulation signal Smc increases, and decreases as the voltage value of the composite modulation signal Smc decreases. The frequency f CLK is modulated (spread). Note that the frequency f CLK The change in frequency f CLK The frequency f may be constant throughout the entire range of CLK The oscillator 14 provides a clock signal CLK to the converter 20. ... clock signal CLK may be directly proportional to the composite modulation signal Smc.

[0024] The clock controller 15 controls the operations of the first modulation signal generation circuit 11, the second modulation signal generation circuit 12, and the signal synthesis circuit 13. The operation of the oscillator 14 may also be controlled by the clock controller 15. The clock controller 15 operates in synchronization with a master clock signal (not shown). The master clock signal has a higher frequency than the clock signal CLK.

[0025] The converter 20 receives an input voltage Vin from a DC voltage source (not shown), and generates and outputs an output voltage Vout by DC / DC converting the input voltage Vin. The converter 20 includes a switching controller 21 and a power conversion circuit 22. A clock signal CLK is input to the converter 20. The converter 20 converts the input voltage Vin into the output voltage Vout by performing switching control using the frequency of the clock signal CLK as a switching frequency. More specifically, the power conversion circuit 22 has an output stage circuit provided between an application terminal of the input voltage Vin and an application terminal of the output voltage Vout, and the output stage circuit includes at least an output transistor. The switching controller 21 converts the input voltage Vin into the output voltage Vout by controlling the frequency f of the clock signal CLK. CLK The output transistor is switched using the switching frequency Vout to generate an output voltage Vout.

[0026] 5 shows the internal configuration of the first modulation signal generation circuit 11. The modulation signal generation circuit 11 includes a ladder resistor circuit 111, a buffer circuit 112, and a VI conversion circuit 113.

[0027] An internal voltage Vreg, which is a predetermined positive DC voltage, is supplied to the ladder resistor circuit 111. The internal voltage Vreg is generated based on the input voltage Vin within the clock signal generation circuit 10 or within a device including the clock signal generation circuit 10 (for example, a power supply control device 100 described below; see FIG. 12). The ladder resistor circuit 111 has a series circuit of first to m-th voltage dividing resistors R, and is provided with a switching element SW connected in parallel to each voltage dividing resistor R. However, it is possible that a switching element SW is not connected in parallel to some of the first to m-th voltage dividing resistors R. m is an integer value sufficiently larger than 2. The switching element SW may be configured by a MOSFET.

[0028] A series circuit of the first to m-th voltage dividing resistors R is provided between the application terminal of the internal voltage Vreg and ground. A first terminal of the first voltage dividing resistor R is connected to the application terminal of the internal voltage Vreg. A second terminal of the i-th voltage dividing resistor R is connected to the first terminal of the (i+1)th voltage dividing resistor R. A second terminal of the m-th voltage dividing resistor R is connected to ground. i represents any natural number. However, the upper limit of the symbol "i" in the (i+1)th voltage dividing resistor R is (m-1).

[0029] An intermediate node ND1 is set in the series circuit of the first to m-th voltage-dividing resistors R. The intermediate node ND1 is, for example, a connection node between the second end of the (2 / m)-th voltage-dividing resistor R and the first end of the ((2 / m)+1)-th voltage-dividing resistor R (assuming m is an even number). A divided voltage of the internal voltage Vreg is generated at the intermediate node ND1 as a modulation voltage Vm1. The clock controller 15 individually controls the on / off of each switching element SW in the ladder resistor circuit 111 to generate, as the modulation voltage Vm1, a triangular wave voltage that periodically fluctuates within a voltage range from a predetermined lower limit voltage to a predetermined upper limit voltage. The upper limit voltage is higher than the lower limit voltage. The clock controller 15 sets the frequency of the modulation voltage Vm1 to a frequency f1 by varying the voltage division ratio (voltage division ratio in the ladder resistor circuit 111) for generating the modulation voltage Vm1 from the internal voltage Vreg at a frequency f1.

[0030] The input terminal of the buffer circuit 112 is connected to the intermediate node ND1. The buffer circuit 112 receives the modulation voltage Vm1 with a sufficiently high input impedance, and outputs a modulation voltage Vm1' having the same voltage value as the modulation voltage Vm1 from its own output terminal with a sufficiently low output impedance. The buffer circuit 112 can be formed by a voltage follower circuit. The modulation voltage Vm1' is input to the VI conversion circuit 113. The VI conversion circuit 113 performs voltage / current conversion to convert the modulation voltage Vm1', which is an analog voltage signal, into a modulation current Im1, which is an analog current signal. The modulation current Im1 has a current value that is directly proportional to the value of the modulation voltage Vm1'. That is, Im1=k VI×Vm1'. The modulation current Im1 has a triangular current waveform (strictly speaking, a current waveform similar to a triangular wave). The frequency of the modulation current Im1 is frequency f1. k VI is a predetermined coefficient in units of [ampere / volt]. The modulation current Im1 is output from the first modulation signal generation circuit 11 as the modulation signal Sm1.

[0031] FIG. 6 shows the internal configuration of the signal combining circuit 13. The signal combining circuit 13 includes a linear arithmetic circuit 131 and an IV conversion circuit 132. The modulation current Im1 is input to the linear arithmetic circuit 131 as the modulation signal Sm1 from the first modulation signal generating circuit 11. On the other hand, the modulation current Im2 from the second modulation signal generating circuit 12 is also input to the linear arithmetic circuit 131. The modulation current Im2 corresponds to the modulation signal Sm2. Like the modulation current Im1, the modulation current Im2 has a triangular current waveform (strictly speaking, a current waveform similar to a triangular wave). However, the frequency of the modulation current Im2 is frequency f2.

[0032] The linear arithmetic circuit 131 is an analog circuit that generates and outputs a composite current Imc, which is a current obtained by combining the modulation currents Im1 and Im2. "Imc = Im1 + Im2" However, while the modulation current Im1 always has a positive current value, the modulation current Im2 may have either a positive current value or a negative current value.

[0033] The IV conversion circuit 132 performs current / voltage conversion to convert the composite current Imc, which is an analog current signal, into a composite voltage Vmc, which is an analog voltage signal. The composite voltage Vmc has a voltage value that is directly proportional to the value of the composite current Imc. That is, "Vmc=k IV ×Imc”. IV is a predetermined coefficient in units of volts / amperes. The composite voltage Vmc is the composite modulation signal Smc and is supplied to the oscillator 14.

[0034] The waveform of the modulation current Im2 is shown in Figure 7. The period of one cycle of the modulation current Im2 is called the unit period P UNIT The unit period P UNIT The length of the unit period P is equal to the reciprocal of the frequency f2.UNIT is the combined period of periods P[1] to P

[12] . Based on the master clock signal, the unit period P is generated by the clock controller 15 UNIT and the periods P[1] to P

[12] are set and defined. For any natural number i, the periods P[i] and P[i + 1] are adjacent periods, and the period P[i + 1] is the period after the period P[i]. When the period P

[12] in a certain unit period P UNIT ends, the period P[1] in the next unit period P UNIT starts. The lengths of the periods P[1] to P

[12] are equal to each other. Therefore, the length of each of the periods P[1] to P

[12] is 1 / 12 of the length of the unit period P UNIT . However, some of the lengths of the periods P[1] to P

[12] may be different from some of the other lengths. That is, the length of the period P[i A may be different from the length of the period P[i B (where i A and i B represent different natural numbers less than or equal to 12).

[0035] The current value of the modulated current Im2 is one of the seven current values Ival_0 to Ival_6. The current values Ival_0 to Ival_6 are seven predetermined current values that satisfy "Ival_6 < Ival_5 < Ival_4 < Ival_0 < Ival_1 < Ival_2 < Ival_3". Among the current values Ival_0 to Ival_6, the current values Ival_1, Ival_2, and Ival_3 have positive current values, and the current values Ival_4, Ival_5, and Ival_6 have negative current values. Here, it is assumed that the current value Ival_0 is zero (zero amperes). However, the current value Ival_0 may be a positive or negative minute value.

[0036] In the periods P[1] and P[7], the modulated current Im2 has the current value Ival_0. In the periods P[2] and P[6], the modulated current Im2 has the current value Ival_1. In the periods P[3] and P[5], the modulated current Im2 has the current value Ival_2. In period P[4], the modulation current Im2 has a current value Ival_3. In periods P[8] and P

[12] , the modulation current Im2 has a current value Ival_4. In periods P[9] and P

[11] , the modulation current Im2 has a current value Ival_5. In period P

[10] , the modulation current Im2 has a current value Ival_6.

[0037] That is, each unit period P UNIT In this example, the modulation current Im2 increases from period P[1] to period P[4], then decreases from period P[4] to period P

[10] , and then increases from period P

[10] to period P

[12] .

[0038] Referring to FIG. 8, the second modulation signal generation circuit 12 includes variable current sources 12a and 12b. The variable current source 12a is connected to a linear arithmetic circuit 131 and supplies an adding current Ia to the linear arithmetic circuit 131. However, as will be described later, there is also a period during which the adding current Ia is set to zero. The variable current source 12b is connected to the linear arithmetic circuit 131 and draws a subtracting current Ib from the linear arithmetic circuit 131. However, as will be described later, there is also a period during which the subtracting current Ib is set to zero. Both the variable current sources 12a and 12b are driven based on the internal voltage Vreg. The variable current source 12a has the ability to change the magnitude of the adding current Ia, and the variable current source 12b has the ability to change the magnitude of the subtracting current Ib.

[0039] The clock controller 15 controls whether or not an addition current Ia flows between the variable current source 12a and the linear operation circuit 131, and also controls the magnitude of the addition current Ia when the addition current Ia is generated between the variable current source 12a and the linear operation circuit 131. The clock controller 15 controls whether or not a subtraction current Ib flows between the variable current source 12b and the linear operation circuit 131, and also controls the magnitude of the subtraction current Ib when the subtraction current Ib is generated between the variable current source 12b and the linear operation circuit 131.

[0040] The clock controller 15 switches the magnitude of the addition current Ia between zero and absolute values ​​|Ival_1|, |Ival_2|, and |Ival_3|. The clock controller 15 switches the magnitude of the subtraction current Ib between zero and absolute values ​​|Ival_4|, |Ival_5|, and |Ival_6|. The absolute values ​​|Ival_1| to |Ival_6| represent the absolute values ​​of the current values ​​Ival_1 to Ival_6, respectively. However, because the current values ​​Ival_1 to Ival_3 have positive polarity, the absolute values ​​|Ival_1| to |Ival_3| are equal to the current values ​​Ival_1 to Ival_3, respectively.

[0041] The modulation current Im2 is composed of the addition current Ia and the subtraction current Ib. The linear arithmetic circuit 131 generates a combined current Imc by combining the modulation current Im1 with the addition current Ia or the subtraction current Ib. However, in this combination, the addition current Ia is added to the modulation current Im1, while the subtraction current Ib is subtracted from the modulation current Im1. In other words, "Imc = Im1 + Ia - Ib".

[0042] In periods P[1] and P[7], the clock controller 15 sets the magnitude of both the adding current Ia and the subtracting current Ib to zero. Therefore, in periods P[1] and P[7], "Imc=Im1" (i.e., the composite current Imc is equal to the modulation current Im1).

[0043] In periods P[2] and P[6], the clock controller 15 sets the magnitude of the adding current Ia to the absolute value |Ival_1| and sets the magnitude of the subtracting current Ib to zero. Therefore, in periods P[2] and P[6], "Imc = Im1 + Ia", and the composite current Imc is greater than the modulation current Im1 by the absolute value |Ival_1|.

[0044] In periods P[3] and P[5], the clock controller 15 sets the magnitude of the adding current Ia to the absolute value |Ival_2| and sets the magnitude of the subtracting current Ib to zero. Therefore, in periods P[3] and P[5], "Imc = Im1 + Ia", and the composite current Imc is greater than the modulation current Im1 by the absolute value |Ival_2|.

[0045] During period P[4], the clock controller 15 sets the magnitude of the adding current Ia to the absolute value |Ival_3| and sets the magnitude of the subtracting current Ib to zero. Therefore, during period P[4], "Imc = Im1 + Ia", and the composite current Imc is greater than the modulation current Im1 by the absolute value |Ival_3|.

[0046] During periods P[8] and P

[12] , the clock controller 15 sets the magnitude of the subtraction current Ib to the absolute value |Ival_4| and sets the magnitude of the addition current Ia to zero. Therefore, during periods P[8] and P

[12] , "Imc = Im1 - Ib", and the composite current Imc is smaller than the modulation current Im1 by the absolute value |Ival_4|.

[0047] During periods P[9] and P

[11] , the clock controller 15 sets the magnitude of the subtraction current Ib to the absolute value |Ival_5| and sets the magnitude of the addition current Ia to zero. Therefore, during periods P[9] and P

[11] , "Imc = Im1 - Ib", and the composite current Imc is smaller than the modulation current Im1 by the absolute value |Ival_5|.

[0048] During period P

[10] , the clock controller 15 sets the magnitude of the subtraction current Ib to the absolute value |Ival_6| and sets the magnitude of the addition current Ia to zero. Therefore, during period P

[10] , "Imc = Im1 - Ib", and the combined current Imc is smaller than the modulation current Im1 by the absolute value |Ival_6|. Note that the lower limit of the modulation current Im1 is larger than the absolute value |Ival_6|. Therefore, the combined current Imc never becomes zero or less.

[0049] In this way, the signal synthesis circuit 13 generates a synthetic current Imc by adding the adding current Ia to the modulation current Im1 or subtracting the subtraction current Ib from the modulation current Im1, and generates a synthetic voltage Vmc as a synthetic modulation signal Smc by converting the synthetic current Imc into a voltage signal. At this time, under the control of the clock controller 15, the adding current Ia and the subtraction current Ib vary according to the frequency f2.

[0050] Specifically, the clock controller 15 calculates a unit period P that includes an addition period in which the addition current Ia is added to the modulation current Im1 and a subtraction period in which the subtraction current Ib is subtracted from the modulation current Im1. UNIT is repeatedly set by the clock controller 15. UNIT The repetition frequency of each unit period P UNIT In the case of the addition period and the subtraction period, the subtraction period is provided after the addition period. However, each unit period P UNIT In the above, an addition period may be provided after the subtraction period.

[0051] The periods P[2] to P[6] belong to the addition period, and the periods P[8] to P

[12] belong to the subtraction period. During the addition period, the modulation current Im2 is formed by the addition current Ia, while during the subtraction period, the modulation current Im2 is formed by the subtraction current Ib. The periods P[1] and P[7] do not belong to either the addition period or the subtraction period. However, it is also possible to modify the period so that either one or both of the periods P[1] and P[7] belong to the addition period or the subtraction period.

[0052] Under the control of the clock controller 15, the second modulation signal generation circuit 12 (12a, 12b) monotonically increases and then decreases the addition current Ia during the addition period (period P[2] to P[6]), and monotonically increases and then decreases the subtraction current Ib during the subtraction period (period P[8] to P

[12] ). This allows the modulation current Im2 to be gradually changed.

[0053] According to the method of this embodiment, the frequency f of the clock signal CLK CLKis modulated (spread) by the frequency f1 of the modulating signal Sm1 and also by the frequency f2 of the modulating signal Sm2. Therefore, as shown in FIG. 9, the noise generated at frequency f1 is reduced, and improved EMI characteristics are expected. In FIG. 9, waveform 610 shows a schematic representation of the power spectrum of the noise generated in the second reference configuration of FIG. 15. In FIG. 9, waveform 620 shows a schematic representation of the power spectrum of the noise generated in the configuration of FIG. 1. By improving the second reference configuration of FIG. 15 to the configuration of FIG. 1, the noise generated at frequency f1 can be significantly reduced. Although not shown in particular, in comparison with the second reference configuration of FIG. 15, the configuration of FIG. 1 shows a significant reduction in the noise generated not only near frequency f1 but also near the switching frequency (f CLK ) can reduce noise generated in a wide range of bands.

[0054] Although it has been considered to achieve spectrum spread by superimposing a random number signal on a triangular wave signal, the circuitry required for random number generation is large. The method of this embodiment achieves good spectrum spread with a simple configuration (small-scale circuit configuration).

[0055] This embodiment includes the following first to fourth examples. The matters described above in this embodiment apply to each of the following examples unless otherwise specified and unless there is a contradiction. If there are any matters in each example that contradict the matters described above, the description in that example may take precedence. Furthermore, unless there is a contradiction, matters described in any of the multiple examples described below can also be applied to any of the other examples (i.e., any two or more of the multiple examples can also be combined).

[0056] <<First Example>> A first embodiment will be described. The variable current source 12a switches the magnitude of the addition current Ia in x steps during the addition period. In the above configuration, "x=3", but x can be any integer equal to or greater than 2. Similarly, the variable current source 12b switches the magnitude of the subtraction current Ib in y steps during the subtraction period. In the above configuration, "y=3", but y can be any integer equal to or greater than 2.

[0057] <<Second Example>> A second embodiment will now be described. Fig. 10 shows a schematic configuration of a switching power supply device 1 according to the second embodiment. The switching power supply device 1 of Fig. 10 comprises a power supply control device 100 and a group of discrete components 200. The group of discrete components 200 is made up of a plurality of discrete components that are externally connected to the power supply control device 100.

[0058] Fig. 11 shows an external perspective view of the power supply control device 100. The power supply control device 100 is an electronic component that includes a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing CS (package) that houses the semiconductor chip, and a plurality of external terminals that are exposed to the outside of the power supply control device 100 from the housing CS. The power supply control device 100 is formed by sealing the semiconductor chip in a housing CS made of resin. Note that the number of external terminals of the power supply control device 100 and the type of housing CS of the power supply control device 100 shown in Fig. 11 are merely examples, and can be designed as desired.

[0059] The above-described clock signal generation circuit 10 and switching controller 21 (see FIG. 1) are provided within the power supply control device 100. A part of the power conversion circuit 22 (output transistors, etc.) is provided within the power supply control device 100, and the remainder of the power conversion circuit 22 is formed by a group of discrete components 200.

[0060] FIG. 12 shows a detailed configuration of a switching power supply 1 according to a second embodiment. The switching power supply 1 of FIG. 12 includes a power supply control device 100, and also includes a coil L1, an output capacitor C1, and feedback resistors R1 and R2 as components of a discrete component group 200. In the configuration of FIG. 12, the output stage circuit MM, the coil L1, and the output capacitor C1 form a power conversion circuit 22 (see FIG. 1). The switching power supply 1 of FIG. 12 is configured as a step-down switching power supply (DC / DC converter) that generates a desired output voltage Vout from an input voltage Vin supplied from a DC voltage source (not shown). The output voltage Vout is generated at the output terminal OUT. In other words, the output terminal OUT is the application terminal of the output voltage Vout (the terminal to which the output voltage Vout is applied). The output voltage Vout is supplied to a load LD connected to the output terminal OUT.

[0061] Except in a transient state, the input voltage Vin and the output voltage Vout are positive DC voltages, and the output voltage Vout is lower than the input voltage Vin. For example, when the input voltage Vin is 12 V, the output voltage Vout can be stabilized at a desired positive voltage value less than 12 V (for example, 3.3 V or 5 V) by adjusting the resistance values ​​of the feedback resistors R1 and R2.

[0062] 12 shows an input terminal IN, a switch terminal SW, a ground terminal GND, and a feedback terminal FB as part of a group of external terminals provided on the power supply control device 100.

[0063] The external configuration of the power supply control device 100 will now be described. An input voltage Vin is supplied to an input terminal IN from a DC voltage source (not shown) provided external to the power supply control device 100. A coil L1 is connected in series between a switch terminal SW and an output terminal OUT. That is, a first terminal of the coil L1 is connected to the switch terminal SW, and a second terminal of the coil L1 is connected to the output terminal OUT. The output terminal OUT is also connected to ground via an output capacitor C1. That is, a first terminal of the output capacitor C1 is connected to the output terminal OUT, and a second terminal of the output capacitor C1 is connected to ground. Furthermore, the output terminal OUT is connected to a first terminal of a feedback resistor R1, a second terminal of the feedback resistor R1 is connected to a first terminal of a feedback resistor R2, and a second terminal of the feedback resistor R2 is connected to ground. A feedback voltage Vfb is generated at a connection node between the feedback resistors R1 and R2. The connection node between the feedback resistors R1 and R2 is connected to a feedback terminal FB, thereby inputting the feedback voltage Vfb to the feedback terminal FB. The ground terminal GND is connected to ground.

[0064] The following describes the internal configuration of the power supply control device 100. The power supply control device 100 includes an output stage circuit MM, a switching controller 21, and a clock signal generation circuit 10.

[0065] The output stage circuit MM includes transistors MH and ML. In the configuration example of FIG. 12, the transistors MH and ML are configured by N-channel MOSFETs. The transistors MH and ML are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (i.e., ground). The transistor MH functions as an output transistor, and the transistor ML functions as a rectifying element (synchronous rectifying transistor). The transistor MH is provided on a higher potential side than the transistor ML. Specifically, the drain of the transistor MH is connected to the input terminal IN, which is the application terminal of the input voltage Vin, and is supplied with the input voltage Vin. The source of the transistor MH and the drain of the transistor ML are commonly connected to the switch terminal SW. The source of the transistor ML is connected to the ground terminal GND (and therefore to ground). However, a resistor for current detection may be inserted between the source of the transistor ML and the ground terminal GND.

[0066] The switching of the output stage circuit MM is controlled by a switching controller 21. In the switching control of the output stage circuit MM, the transistors MH and ML are switched so that they are alternately turned on and off. The switching control of the output stage circuit MM causes a square-wave switch voltage Vsw to appear at the switch terminal SW. The coil L1 and the output capacitor C1 form a rectifying and smoothing circuit that rectifies and smoothes the square-wave switch voltage Vsw that appears at the switch terminal SW to generate the output voltage Vout. The feedback resistors R1 and R2 form a feedback voltage generating circuit that divides the output voltage Vout to generate a feedback voltage Vfb that corresponds to the output voltage Vout. The feedback voltage Vfb is proportional to the output voltage Vout, and the feedback voltage Vfb also rises and falls as the output voltage Vout rises and falls.

[0067] Alternatively, the output voltage Vout itself may be used as the feedback voltage Vfb. In either case, the feedback voltage Vfb is a voltage corresponding to the output voltage Vout. The feedback voltage generating circuit (R1, R2) may be provided within the power supply control device 100. In this case, the feedback terminal FB is connected to the output terminal OUT.

[0068] Gate signals GH and GL are supplied to the gates of the transistors MH and ML as drive signals, respectively, and the transistors MH and ML are turned on and off in response to the gate signals GH and GL. When the gate signal GH is at a high level, the transistor MH is on, and when the gate signal GH is at a low level, the transistor MH is off. Similarly, when the gate signal GL is at a high level, the transistor ML is on, and when the gate signal GL is at a low level, the transistor ML is off.

[0069] Basically, the transistors MH and ML are alternately turned on and off, but both transistors MH and ML may be maintained in the off state. That is, the state of the output stage circuit MM is one of an output high state, an output low state, and a both-off state. In the output high state, the transistor MH is on and the transistor ML is off. In the output low state, the transistor MH is off and the transistor ML is on. In the both-off state, both transistors MH and ML are off. The transistors MH and ML are never on at the same time. In the switching control by the switching controller 21, alternately turning the transistors M1 and M2 on and off refers to the concept of both-off states being present between the output low state and the output high state, taking into account dead time, etc. Note that at least one of the transistors MH and ML may be provided external to the power supply control device 100. The entire output stage circuit MM may also be provided external to the power supply control device 100.

[0070] The switching controller 21 is connected to a feedback terminal FB and receives a feedback voltage Vfb. Based on the feedback voltage Vfb, the switching controller 21 controls the on / off states of the transistors MH and ML by controlling the levels of the gate signals GH and GL, thereby generating a desired output voltage Vout at the output terminal OUT. A reference voltage Vref having a predetermined positive DC voltage value is generated within the power supply control device 100, and the switching controller 21 adjusts the output duty of the output stage circuit MM using pulse width modulation so that the feedback voltage Vfb matches the reference voltage Vref. The output duty represents the ratio of the period during which the output stage circuit MM is in the output high state to the sum of the period during which the output stage circuit MM is in the output high state and the period during which the output stage circuit MM is in the output low state.

[0071] The switching controller 21 determines the switching frequency of the transistors MH and ML based on the clock signal CLK output from the clock signal generation circuit 10. Specifically, as shown in FIG. 13, the switching controller 21 switches the state of the output stage circuit MM from the output low state to the output high state at the timing when a rising edge occurs in the clock signal CLK, and then performs a unit operation of switching the state of the output stage circuit MM from the output high state to the output low state based on another signal (not shown). This unit operation is repeated by switching control. The switching controller 21 controls the output duty by generating the other signal so that the error between the feedback voltage Vfb and the reference voltage Vref approaches zero. The duty of the clock signal CLK is arbitrary.

[0072] Since the transistor MH (output transistor) is switched from the off state to the on state every time a rising edge occurs in the clock signal CLK, the switching frequency of the transistor MH is frequency f CLK As mentioned above, the frequency f CLKrepresents the frequency of the clock signal CLK. However, in the power supply control device 100, the clock signal CLK may be divided by n to generate a divided clock signal, and the state of the output stage circuit MM may be switched from an output low state to an output high state at the timing when a rising edge of the divided clock signal occurs (n represents any integer equal to or greater than 2). In this case, the transistor MH (output transistor) is switched from an off state to an on state every time a rising edge occurs in the divided clock signal, so the switching frequency of the transistor MH is a frequency f CLK In any case, the frequency f CLK The transistor MH is switched at a switching frequency proportional to

[0073] Although not specifically shown, the power supply control device 100 is provided with an internal power supply circuit that generates an internal power supply voltage based on the input voltage Vin. Each circuit within the power supply control device 100 is driven by the input voltage Vin or the internal power supply voltage. The internal voltage Vreg (see FIG. 5) described above is one type of internal power supply voltage. Furthermore, the gate signal GL is a signal referenced to the ground potential, while the gate signal GH is a signal referenced to the potential of the switch terminal SW. A low-level gate signal GH has the potential of the switch terminal SW, and a high-level gate signal GH is a predetermined voltage higher than the potential of the switch terminal SW. This predetermined voltage is greater than the gate threshold voltage of the transistor MH. A well-known bootstrap circuit (not shown) can be used to generate a boost power supply for generating the gate signal GH. The transistor MH may be configured as a P-channel MOSFET, in which case a boost power supply is not required.

[0074] As a modification, a diode rectification system may be adopted in the switching power supply device 1. In this case, instead of the transistor ML, a synchronous rectification diode having an anode connected to the ground terminal GND and a cathode connected to the switch terminal SW is provided in the switching power supply device 1 as a rectifying element. In this case, only the transistor MH is turned on and off in the switching control of the output stage circuit MM. In either case, the input voltage Vin is converted to the output voltage Vout by switching the transistor MH between on and off in the switching control of the output stage circuit MM.

[0075] <<Third Example>> A third embodiment will be described below. Although Fig. 12 shows an example in which the switching power supply device 1 is a step-down switching power supply device, the switching power supply device 1 may also be a step-up or step-up / step-down switching power supply device.

[0076] The switching power supply 1 in Fig. 1 may be a composite power supply having multiple built-in DC / DC converters. In this case, the first to Kth DC / DC converters included in the multiple DC / DC converters may each be a step-down DC / DC converter including a switching controller 21, an output stage circuit MM, a coil L1, an output capacitor C1, and feedback resistors R1 and R2 (K is an integer equal to or greater than 2) as shown in Fig. 12. In this case, the switching controller 21 and the output stage circuit MM of each DC / DC converter are built into the power supply control device 100 (however, each output stage circuit MM may be provided external to the power supply control device 100). When the switching power supply 1 is a composite power supply having multiple built-in DC / DC converters, the power supply control device 100 may be an electronic component classified as a PMIC (power management IC).

[0077] A single clock signal generation circuit 10 may be shared by the first to Kth DC / DC converters. In this case, first to Kth clock signals having different phases from each other may be generated from the clock signal CLK within the power supply control device 100, and switching control of the output stage circuits MM of the first to Kth DC / DC converters may be performed in synchronization with the first to Kth clock signals, respectively. The frequencies of the first to Kth clock signals are equal to the frequency of the clock signal CLK. Alternatively, the power supply control device 100 may be provided with first to Kth clock signal generation circuits 10 corresponding to the first to Kth DC / DC converters.

[0078] The multiple DC / DC converters built into the composite power supply may include a step-up DC / DC converter, and the composite power supply may further include a linear regulator.

[0079] 1 may also be an isolated DC / DC converter having a transformer (not shown). In this case, the switching power supply 1 includes a primary circuit and a secondary circuit that are isolated from each other, with the primary winding of the transformer arranged in the primary circuit and the secondary winding of the transformer arranged in the secondary circuit. A voltage that is higher than the reference potential point of the primary circuit by the input voltage Vin is applied to a first end of the primary winding, and an output transistor is inserted between a second end of the primary winding and the reference potential point of the primary circuit. When the switching power supply 1 is an isolated DC / DC converter having a transformer, the output transistor, the transformer, and the secondary circuit form a power conversion circuit 22 (see FIG. 1), and the switching controller 21 switches the output transistor in synchronization with a clock signal CLK to generate an output voltage Vout in the secondary circuit.

[0080] <<Fourth Example>> A fourth embodiment will now be described.

[0081] The clock signal generation circuit 10 can be applied not only to the switching power supply device 1 but also to any semiconductor device that requires a clock signal. Any semiconductor device that requires a clock signal includes the clock signal generation circuit 10 and a synchronous circuit that operates in synchronization with the clock signal CLK. In the configuration of Fig. 12, the synchronous circuit includes a switching controller 21 and an output stage circuit MM.

[0082] For example, a first semiconductor device includes a clock signal generating circuit 10, a half-bridge circuit, and a controller that switches the half-bridge circuit in synchronization with a clock signal CLK, and the synchronous circuit in the first semiconductor device includes the half-bridge circuit and the controller. An arbitrary load (e.g., an armature winding of a motor) is connected to the half-bridge circuit of the first semiconductor device, and current is supplied to the load through the half-bridge circuit. In the first semiconductor device, the half-bridge circuit has the same configuration as the output stage circuit MM in Figure 12, and the controller can switch the half-bridge circuit at the frequency of the clock signal CLK.

[0083] Alternatively, for example, a second semiconductor device may include a clock signal generating circuit 10, half-bridge circuits for U, V, and W phases, and a controller that switches the half-bridge circuits for each phase in synchronization with the clock signal CLK, and the synchronization circuit in the second semiconductor device includes the half-bridge circuits for each phase and the controller. A three-phase motor is connected to the half-bridge circuits for U, V, and W phases in the second semiconductor device, and current is supplied to the three-phase motor through the half-bridge circuits for each phase. In the second semiconductor device, the half-bridge circuits for each phase have the same configuration as the output stage circuit MM in Figure 12, and the controller can switch the half-bridge circuits for each phase at the frequency of the clock signal CLK.

[0084] The switching power supply device 1 or the above-described semiconductor device can be mounted in any electrical device, such as an electrical component mounted in a vehicle such as an automobile, a computer, a home appliance, or an industrial device.

[0085] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0086] The channel types of the FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0087] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0088] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0089] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0090] A clock signal generation circuit (10) according to one aspect of the present disclosure has a configuration (first configuration) including a first modulation signal generation circuit (11) configured to generate a first modulation signal (Sm1) having a first frequency (f1), a second modulation signal generation circuit (12) configured to generate a second modulation signal (Sm2) having a second frequency (f2) lower than the first frequency, a signal synthesis circuit (13) configured to generate a synthesized modulation signal (Smc) by synthesizing the first modulation signal and the second modulation signal, and an oscillator (14) configured to generate a clock signal (CLK) having a frequency corresponding to the synthesized modulation signal.

[0091] This allows the frequency of the clock signal to be spread over a wide band, which in turn reduces the peaks in the power spectrum of the noise radiated from the clock signal generation circuit or from a device that includes a clock signal generation circuit, leading to improved EMI characteristics.

[0092] In the clock signal generating circuit according to the first configuration, the signal synthesis circuit may be configured (second configuration) to generate the synthesized modulation signal by synthesizing a first modulation current (Im1) as the first modulation signal and a second modulation current (Im2) as the second modulation signal.

[0093] By employing a method of generating a composite modulated signal by combining current signals having different frequencies, a desired composite modulated signal can be generated with a small circuit scale.

[0094] In the clock signal generation circuit according to the second configuration, the first modulation signal generation circuit generates the first modulation current (Im1) by converting a modulation voltage (Vm1) having the first frequency into a current signal, the second modulation current being composed of an addition current (Ia) and a subtraction current (Ib), the signal synthesis circuit generates a composite current (Imc) by adding the addition current to the first modulation current or subtracting the subtraction current from the first modulation current, and converts the composite current into a voltage signal to generate a composite voltage (Vmc) as the composite modulation signal, and the addition current and the subtraction current may vary according to the second frequency (third configuration).

[0095] The clock signal generating circuit according to the third configuration further comprises a clock controller (15) configured to control operations of the first modulation signal generating circuit, the second modulation signal generating circuit, and the signal synthesis circuit, and the clock controller controls a unit period (P UNIT ) may be repeatedly set, the repetition frequency of the plurality of unit periods is the second frequency, and in each unit period, one of the addition period and the subtraction period is provided after the other period (fourth configuration).

[0096] In the clock signal generating circuit according to the fourth configuration, the second modulation signal generating circuit may be configured (fifth configuration) to monotonically increase and then monotonically decrease the addition current during the addition period, and to monotonically increase and then monotonically decrease the subtraction current during the subtraction period.

[0097] In the clock signal generation circuit according to any one of the third to fifth configurations, the first modulation signal generation circuit may be configured (sixth configuration) to generate the modulation voltage by dividing a predetermined DC voltage (Vreg) using a ladder resistor circuit (111), and to give the modulation voltage the first frequency by varying a voltage division ratio for generating the modulation voltage from the DC voltage at the first frequency.

[0098] A power supply control device according to one aspect of the present disclosure is a power supply control device (100) provided in a switching power supply device (1) configured to generate an output voltage (Vout) from an input voltage (Vin) through switching of an output transistor, and has a configuration (seventh configuration) including a clock signal generation circuit (10) according to any of the first to sixth configurations and a switching controller (21) configured to switch the output transistor at a switching frequency corresponding to the clock signal.

[0099] A switching power supply device according to one aspect of the present disclosure is a switching power supply device (1) configured to generate an output voltage (Vout) from an input voltage (Vin) through switching of an output transistor (MH), and is configured (eighth configuration) to include a clock signal generation circuit (10) according to any of the first to sixth configurations, and a converter (20) having the output transistor and configured to convert the input voltage to the output voltage by switching the output transistor at a switching frequency corresponding to the clock signal.

[0100] The switching power supply device according to the eighth configuration may be configured (ninth configuration) to include: an output stage circuit (MM) having the output transistor (MH) provided between an application terminal of the input voltage and a switch terminal, and a rectifier element (ML) provided between the switch terminal and a ground terminal having a ground potential lower than the input voltage; a rectifying and smoothing circuit (L1, C1) configured to generate the output voltage by rectifying and smoothing a switch voltage (Vsw) generated at the switch terminal by switching of the output transistor; and a switching controller (21) configured to control the switching of the output transistor based on a feedback voltage (Vfb) corresponding to the output voltage. [Explanation of symbols]

[0101] 1. Switching power supply 10 Clock signal generation circuit 11 First modulation signal generating circuit 12 Second modulation signal generating circuit 13 Signal synthesis circuit 14 oscillators 14a VCO 15 Clock Controller 20 Converter 21 Switching Controller 22 Power Conversion Circuit Vin Input voltage Vout Output voltage Sm1, Sm2 modulation signals SMC composite modulated signal CLK Clock signal 111 Ladder resistor circuit 112 Buffer Circuit 113 VI conversion circuit Vm1 modulation voltage Im1 modulation current 131 Linear Arithmetic Circuit 132 IV conversion circuit Im2 modulation current Imc composite current Vmc composite voltage 12a, 12b Variable current source Ia Addition current Ib Subtraction current 100 Power supply control device 200 discrete components MM output stage circuit MH, ML transistors GH, GL gate signals SW Switch terminal IN input terminal GND Ground terminal FB Feedback terminal OUT output terminal LD load L1 coil C1 Output capacitor R1, R2 feedback resistors Vref Reference voltage

Claims

1. a first modulating signal generating circuit configured to generate a first modulating signal having a first frequency; a second modulation signal generating circuit configured to generate a second modulation signal having a second frequency lower than the first frequency; a signal combining circuit configured to combine the first modulated signal and the second modulated signal to generate a combined modulated signal; an oscillator configured to generate a clock signal having a frequency responsive to the composite modulated signal. , clock signal generation circuit.

2. In the signal synthesis circuit, a first modulation current as the first modulation signal and a second modulation current as the second modulation signal are synthesized to generate the synthesized modulation signal.

2. The clock signal generating circuit according to claim 1.

3. the first modulation signal generating circuit converts a modulation voltage having the first frequency into a current signal to generate the first modulation current; the second modulation current is composed of an addition current and a subtraction current, the signal synthesis circuit generates a synthesized current by adding the current for addition to the first modulation current or subtracting the current for subtraction from the first modulation current, and converts the synthesized current into a voltage signal to generate a synthesized voltage as the synthesized modulation signal; The adding current and the subtracting current vary according to the second frequency.

3. The clock signal generating circuit according to claim 2.

4. a clock controller configured to control operations of the first modulation signal generation circuit, the second modulation signal generation circuit, and the signal synthesis circuit; the clock controller repeatedly sets a unit period including an addition period in which the addition current is added to the first modulation current and a subtraction period in which the subtraction current is subtracted from the first modulation current; a repetition frequency of the plurality of unit periods is the second frequency, In each unit period, one of the addition period and the subtraction period is provided after the other period.

4. The clock signal generating circuit according to claim 3.

5. The second modulation signal generating circuit monotonically increases and then monotonically decreases the addition current during the addition period, and monotonically increases and then monotonically decreases the subtraction current during the subtraction period.

5. The clock signal generating circuit according to claim 4.

6. The first modulation signal generation circuit generates the modulation voltage by dividing a predetermined DC voltage using a ladder resistor circuit, and causes the modulation voltage to have the first frequency by varying a voltage division ratio for generating the modulation voltage from the DC voltage at the first frequency.

4. The clock signal generating circuit according to claim 3.

7. A power supply control device provided in a switching power supply device configured to generate an output voltage from an input voltage through switching of an output transistor, A clock signal generating circuit according to any one of claims 1 to 6; a switching controller configured to switch the output transistor at a switching frequency responsive to the clock signal. , power control device.

8. A switching power supply configured to generate an output voltage from an input voltage through switching of an output transistor, A clock signal generating circuit according to any one of claims 1 to 6; a converter having the output transistor and configured to convert the input voltage to the output voltage by switching the output transistor at a switching frequency responsive to the clock signal. , switching power supply.

9. The converter comprises: an output stage circuit including the output transistor provided between an application terminal of the input voltage and a switch terminal, and a rectifying element provided between the switch terminal and a ground terminal having a ground potential lower than the input voltage; a rectifying and smoothing circuit configured to generate the output voltage by rectifying and smoothing a switch voltage generated at the switch terminal by switching the output transistor; a switching controller configured to perform switching control of the output transistor based on a feedback voltage corresponding to the output voltage.

9. The switching power supply device according to claim 8.

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