Display device and manufacturing method thereof

Abstract

To improve the yield of display devices. [Solution] According to an embodiment, a display device includes a substrate having a display area for displaying an image, an insulating layer disposed above the substrate, and a display element including a first electrode disposed above the insulating layer in the display area. The first electrode includes a transparent first conductive oxide layer and a transparent second conductive oxide layer covering the first conductive oxide layer. Furthermore, the transmittance of the first conductive oxide layer is higher than the transmittance of the second conductive oxide layer.

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have come into practical use. Techniques for improving the yield of such display devices are needed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device and a manufacturing method thereof that can improve yield. [Means for solving the problem]

[0005] Generally, according to an embodiment, a display device includes a substrate having a display area for displaying an image, an insulating layer disposed above the substrate, and a display element including a first electrode disposed above the insulating layer in the display area. The first electrode includes a transparent first conductive oxide layer and a transparent second conductive oxide layer covering the first conductive oxide layer. Furthermore, the transmittance of the second conductive oxide layer is lower than the transmittance of the first conductive oxide layer.

[0006] Also, generally according to an embodiment, a method for manufacturing a display device includes forming an insulating layer above a substrate and forming a first electrode of a display element above the insulating layer. The first electrode includes a transparent first conductive oxide layer and a transparent second conductive oxide layer covering the first conductive oxide layer. Furthermore, forming the first electrode includes forming the first conductive oxide layer by performing a first sputtering process in an atmosphere not containing water vapor, and forming the second conductive oxide layer by performing a second sputtering process in an atmosphere containing water vapor. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display panel taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view showing an example of a configuration that can be applied to the lower electrode. [Figure 5] FIG. 5 is a schematic plan view of a motherboard according to the embodiment. [Figure 6] FIG. 6 is a flowchart showing an example of a method for manufacturing the display device according to the first embodiment. [Figure 7A] FIG. 7A is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 7B] FIG. 7B is a schematic cross-sectional view of a step subsequent to FIG. 7A. [Figure 7C] FIG. 7C is a schematic cross-sectional view of a step subsequent to FIG. 7B. [Figure 7D] FIG. 7D is a schematic cross-sectional view of a step subsequent to FIG. 7C. [Figure 7E] FIG. 7E is a schematic cross-sectional view of a step subsequent to FIG. 7D. [Figure 8A] FIG. 8A is a schematic cross-sectional view of a step subsequent to FIG. 7E. [Figure 8B] FIG. 8B is a schematic cross-sectional view of a step subsequent to FIG. 8A. [Figure 8C] FIG. 8C is a schematic cross-sectional view of a step subsequent to FIG. 8B. [Figure 8D] FIG. 8D is a schematic cross-sectional view of a step subsequent to FIG. 8C. [Figure 8E] FIG. 8E is a schematic cross-sectional view of a step subsequent to FIG. 8D. [Figure 8F] FIG. 8F is a schematic cross-sectional view of a step subsequent to FIG. 8E. [Figure 8G] FIG. 8G is a schematic cross-sectional view of a step subsequent to FIG. 8F. [Figure 8H] FIG. 8H is a schematic cross-sectional view of a step subsequent to FIG. 8G. [Figure 8I] FIG. 8I is a schematic cross-sectional view of a step subsequent to FIG. 8H. [Figure 9] FIG. 9 is a table showing an example of film formation conditions for the conductive oxide layer. [Figure 10] FIG. 10 is a graph showing the transmittance of a conductive oxide layer formed to a thickness of 7 nm. [Figure 11] FIG. 11 is a graph showing the transmittance of a conductive oxide layer formed to a thickness of 11 nm. [Figure 12] FIG. 12 is a graph showing the transmittance of a conductive oxide layer formed to a thickness of 25 nm. [Figure 13] FIG. 13 is a schematic cross-sectional view showing the configuration of the lower electrode according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. The Z direction is the normal direction of a plane including the X and Y directions. Viewing various elements parallel to the Z direction is referred to as planar view.

[0010] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 and the display area DA in a plan view is circular. However, the shape of the substrate 10 and the display area DA in a plan view is not limited to circular, and may be other shapes such as rectangular, square, or elliptical.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. The pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0014] The display device DSP further includes a terminal section T arranged in the peripheral area SA. To the terminal section T, for example, a flexible circuit board is connected that supplies voltages and signals for driving the display device DSP.

[0015] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0016] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL. In the example of Fig. 1, the scanning lines GL and the power supply lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0018] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3 that constitute one pixel PX. In the example of Fig. 2, the subpixels SP1 and SP3 are aligned in the Y direction. Furthermore, the subpixels SP1 and SP3 are aligned with the subpixel SP2 in the X direction.

[0020] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP1 and SP3 are alternately arranged in the Y direction, and columns in which multiple subpixels SP2 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0021] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of FIG. 2, the pixel openings AP1 and AP3 are quadrangles with the same area. On the other hand, the pixel opening AP2 is a rectangle that is longer in the Y direction than the pixel openings AP1 and AP3. However, the shapes of the pixel openings AP1, AP2, and AP3 are not limited to this example.

[0022] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap pixel aperture AP3.

[0023] In this embodiment, the lower electrodes LE1, LE2, and LE3 are examples of first electrodes, and the upper electrodes UE1, UE2, and UE3 are examples of second electrodes.

[0024] The portions of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlap with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The portions of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlap with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The portions of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlap with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0025] Conductive partition walls 6 are disposed above the rib layer 5. The partition walls 6 serve as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition walls 6 entirely overlap the rib layer 5 and have the same planar shape as the rib layer 5. The partition walls 6 surround each of the pixel openings AP1, AP2, and AP3.

[0026] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0027] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 3 , the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0028] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. That is, the partition wall 6 has an overhanging shape in which both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61.

[0029] In the example of FIG. 3, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0030] 3, the upper portion 62 includes a first top layer 65 and a second top layer 66 disposed on the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, the present invention is not limited to this, and the first top layer 65 and the second top layer 66 may have the same width.

[0031] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6.

[0032] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0033] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0034] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the display element DE1 and the partition wall 6 around it. The sealing layer SE12 continuously covers the display element DE2 and the partition wall 6 around it. The sealing layer SE13 continuously covers the display element DE3 and the partition wall 6 around it.

[0035] 3, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the partition wall 6. In addition, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact with each other above the partition wall 6.

[0036] For example, gaps are formed between the sealing layers SE11, SE12, and SE13 and the upper portion 62 of the partition wall 6. The stacked films FL1, FL2, and FL3 may be disposed in at least a part of these gaps.

[0037] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0038] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0039] The electrodes constituting the touch panel may be disposed on the sealing layer SE2. Also, color filters corresponding to the colors of the subpixels SP1, SP2, SP3 may be disposed above the display elements DE1, DE2, DE3, respectively.

[0040] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0041] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0042] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0043] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0044] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0045] The first top layer 65 of the partition wall 6 is formed of, for example, a metal material. The second top layer 66 of the partition wall 6 is formed of, for example, a conductive oxide. Examples of the metal material that can be used to form the first top layer 65 include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the second top layer 66 include ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and IGZO (Indium Gallium Zinc Oxide). The upper portion 62 may include three or more layers or may be formed of a single layer. The upper portion 62 may also include a layer formed of an insulating material.

[0046] A common voltage is supplied to the partition wall 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. A pixel voltage corresponding to the video signal on the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0047] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0048] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0049] 4 is a schematic cross-sectional view showing an example of a configuration applicable to the lower electrodes LE1, LE2, and LE3. This figure shows the vicinity of the end E of the lower electrodes LE1, LE2, and LE3. The end E is covered with a rib layer 5 (see FIG. 3).

[0050] In this embodiment, the lower electrodes LE1, LE2, and LE3 include a reflective layer RF, a conductive oxide layer CL1 (first conductive oxide layer), a conductive oxide layer CL2 (second conductive oxide layer), and a conductive oxide layer CL3 (third conductive oxide layer).

[0051] The conductive oxide layer CL1 covers the upper surface F1 of the reflective layer RF. The conductive oxide layer CL2 covers the conductive oxide layer CL1. The conductive oxide layer CL3 covers the lower surface F2 of the reflective layer RF.

[0052] In this embodiment, it is assumed that the reflective layer RF is made of silver (Ag) and the conductive oxide layers CL1, CL2, and CL3 are made of ITO. As another example, the reflective layer RF may be made of a metal material other than silver that has excellent reflectivity, or may have a laminated structure of multiple metal materials. Furthermore, the conductive oxide layers CL1, CL2, and CL3 may be made of a transparent conductive oxide other than ITO, such as IZO or IGZO.

[0053] The reflective layer RF reflects light emitted by the organic layers OR1, OR2, and OR3 upward. The conductive oxide layers CL1 and CL2 suppress oxidation of the reflective layer RF and improve the work function of the lower electrodes LE1, LE2, and LE3. The conductive oxide layers CL1 and CL2 also protect the reflective layer RF from etching, which is performed after the formation of the lower electrodes LE1, LE2, and LE3 during the manufacture of the display device DSP. The conductive oxide layer CL3 improves adhesion between the lower electrodes LE1, LE2, and LE3 and the organic insulating layer 12.

[0054] The end portion E includes an end portion Er of the reflective layer RF, an end portion Ec1 of the conductive oxide layer CL1, an end portion Ec2 of the conductive oxide layer CL2, and an end portion Ec3 of the conductive oxide layer CL3. In the example of FIG. 4, the end portions Er, Ec1, Ec2, and Ec3 are aligned. Note that the alignment of the end portions Er, Ec1, Ec2, and Ec3 includes not only the case where these end portions are aligned to form a single plane, but also the case where they are slightly misaligned but can be said to be in agreement compared to the overall size of the lower electrodes LE1, LE2, and LE3.

[0055] The reflective layer RF, the conductive oxide layer CL1, the conductive oxide layer CL2, and the conductive oxide layer CL3 each have thicknesses Tr, T1, T2, and T3. In the example of FIG. 4, the thickness Tr is greater than any of the thicknesses T1, T2, and T3 (Tr > T1, T2, T3). Also, the thickness T2 is greater than the thickness T1 (T1 < T2). The thickness T3 is, for example, equal to the thickness T1 (T3 = T1). In this case, the thickness T3 is smaller than the thickness T2 (T2 > T3). However, the thicknesses T1 and T3 may be different.

[0056] For example, the thickness T1 is 7 nm or more and 13 nm or less, and the thickness T2 is 15 nm or more and 20 nm or less. Illustrating more specific numerical values, the thickness Tr is 100 nm, the thicknesses T1 and T3 are 7 nm, and the thickness T2 is 18 nm. However, the values of the thicknesses Tr, T1, T2, and T3 are not limited to this example.

[0057] Subsequently, an example of a method for manufacturing the display device DSP will be described. When manufacturing the display device DSP, a large mother substrate on which a plurality of regions (panel portions) corresponding to the display device DSP are formed is produced. The configuration applicable to this mother substrate will be described below.

[0058] FIG. 5 is a schematic plan view of a mother substrate MB (mother substrate for a display device) according to the present embodiment. The mother substrate MB has a plurality of panel portions PP arranged in a matrix.

[0059] The outer shape of the panel portion PP corresponds to the cut line CT1 for cutting out each panel portion PP from the motherboard MB. The panel portion PP is provided with a cut line CT2 corresponding to the outer shape of the display device DSP shown in FIG.

[0060] When manufacturing the display device DSP, the mother substrate MB is cut along the cut lines CT1 to cut out each panel portion PP, and then each panel portion PP is cut along the cut lines CT2 to cut out the portion corresponding to the display device DSP.

[0061] Fig. 6 is a flowchart showing an example of a manufacturing method of the display device DSP. Figs. 7A to 7E and 8A to 8I are schematic cross-sectional views showing the manufacturing process of the display device DSP. Figs. 7A to 7E and 8A to 8I mainly focus on the display area DA, and omit elements below the organic insulating layer 12.

[0062] In forming the panel portion PP, first, a circuit layer 11 is formed above the substrate 10 of the mother substrate MB (step PR1 in FIG. 6). Then, an organic insulating layer 12 is formed to cover the circuit layer 11 (step PR2 in FIG. 6). After step PR2, a step for forming lower electrodes LE1, LE2, and LE3 is carried out (step PR3 in FIG. 6).

[0063] 7A, in step PR3, a conductive oxide layer CL3a to be processed into a conductive oxide layer CL3 is formed on the organic insulating layer 12 (step PR3a in FIG. 6), a reflective layer RFa to be processed into a reflective layer RF is formed on the conductive oxide layer CL3a (step PR3b in FIG. 6), and a conductive oxide layer CL1a to be processed into a conductive oxide layer CL1 is formed on the reflective layer RFa (step PR3c in FIG. 6). In this embodiment, the conductive oxide layer CL3a and the conductive oxide layer CL1a are made of ITO, and the reflective layer RFa is made of silver.

[0064] The conductive oxide layer CL3a, the reflective layer RFa, and the conductive oxide layer CL1a can be formed, for example, by sputtering in the same chamber CM1. In this case, the sputtering target for the conductive oxide layer CL3a, which is ITO, and the conductive oxide layer CL1a may be the same. As another example, the conductive oxide layer CL3a, the reflective layer RFa, and the conductive oxide layer CL1a may be formed by sputtering in separate chambers.

[0065] After the conductive oxide layer CL3a, the reflective layer RFa, and the conductive oxide layer CL1a are formed, as shown in FIG. 7B, a conductive oxide layer CL2a to be processed into the conductive oxide layer CL2 is formed on the conductive oxide layer CL1a by sputtering (step PR3d in FIG. 6). In this embodiment, the conductive oxide layer CL2a is formed of ITO. The sputtering for forming the conductive oxide layer CL2a can be performed, for example, in a chamber CM2 different from the chamber CM1.

[0066] During sputtering to form the conductive oxide layer CL3a, the reflective layer RFa, the conductive oxide layer CL1a, and the conductive oxide layer CL2a, the chambers CM1 and CM2 are filled with an inert gas, such as argon (Ar) gas. However, water vapor (H2O) is introduced into the chamber CM2. On the other hand, water vapor is not introduced into the chamber CM1.

[0067] As described above, both the conductive oxide layers CL1a and CL2a are formed of ITO, but the sputtering (first sputtering) for forming the conductive oxide layer CL1a is performed in an atmosphere that does not contain water vapor, and the sputtering (second sputtering) for forming the conductive oxide layer CL2a is performed in an atmosphere that contains water vapor.

[0068] Although the sputtering for forming the conductive oxide layers CL1a and CL2a is performed in separate chambers in this example, these sputtering processes may alternatively be performed in the same chamber.

[0069] After step PR3d, as shown in FIG. 7C, a resist R1 having a planar shape corresponding to the lower electrodes LE1, LE2, and LE3 is disposed on the conductive oxide layer CL2a (step PR3e in FIG. 6). Furthermore, etching is performed using the resist R1 as a mask (step PR3f in FIG. 6). As a result, as shown in FIG. 7D, the conductive oxide layers CL1a, CL2a, and CL3a and the reflective layer RFa are removed from the resist R1. This etching is, for example, wet etching.

[0070] After step PR3f, the resist R1 is removed (stripped) (step PR3g in FIG. 6). Furthermore, the conductive oxide layers CL1a, CL2a, and CL3a made of ITO are baked (step PR3h in FIG. 6).

[0071] Through these steps, lower electrodes LE1, LE2, and LE3 can be obtained, in which a conductive oxide layer CL3, a reflective layer RF, a conductive oxide layer CL1, and a conductive oxide layer CL2 are stacked in this order, as shown in FIG. 7E.

[0072] In this example, the conductive oxide layers CL1a, CL2a, CL3a and the reflective layer RFa are etched using the same resist R1 as a mask, so that the edges Er, Ec1, Ec2, Ec3 of the reflective layer RF and the conductive oxide layers CL1, CL2, CL3 are aligned with the edges of the lower electrodes LE1, LE2, LE3.

[0073] The sputtering for forming the conductive oxide layer CL2a in step PR3d is performed in an atmosphere containing water vapor. Therefore, water is added to the conductive oxide layer CL2a. In this case, before the baking in step PR3h, the crystallinity of the conductive oxide layer CL2a is lower than that of the conductive oxide layer CL1a formed in an atmosphere not containing water vapor. As a result, the etching rate of the conductive oxide layer CL2a in the etching in step PR3f is higher than that of the conductive oxide layer CL1a in the etching. Note that the crystallinity of the conductive oxide layers CL1a and CL2a is improved by the baking in step PR3h. The baking also removes the water added to the conductive oxide layer CL2a.

[0074] After the lower electrodes LE1, LE2, and LE3 are formed, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed over the entire mother substrate MB (step PR4 in FIG. 6), as shown in FIG. 8A. At this point, pixel openings AP1, AP2, and AP3 are not provided in the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0075] After the rib layer 5 is formed, a step for forming the partition walls 6 is carried out (step PR5 in FIG. 6). In step PR5, as shown in FIG. 8B, a first layer L1 to be processed into the bottom layer 63, a second layer L2 to be processed into the shaft layer 64, a third layer L3 to be processed into the first top layer 65, and a fourth layer L4 to be processed into the second top layer 66 are formed in this order over the entire mother substrate MB. Furthermore, a resist R2 is disposed on the fourth layer L4. The resist R2 is patterned into the shape of the partition walls 6. The first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 can be formed by, for example, sputtering.

[0076] Then, using the resist R2 as a mask, the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 are patterned. In one example, the first layer L1 is formed of titanium nitride, the second layer L2 is formed of aluminum, the third layer L3 is formed of titanium, and the fourth layer L4 is formed of ITO. In this case, the patterning may include wet etching to remove portions of the fourth layer L4 exposed by the resist R2, dry etching to remove portions of the first layer L1, the second layer L2, and the third layer L3 exposed by the resist R2, and wet etching to reduce the width of the second layer L2.

[0077] After step PR5, the partition walls 6 are formed in the display area DA as shown in Fig. 8C. After the partition walls 6 are formed, the resist R2 is removed (peeled off).

[0078] Next, a step for providing pixel openings AP1, AP2, and AP3 is performed (step PR6 in FIG. 6). In this step PR6, a resist R3 is formed to cover the partition wall 6, as shown in FIG. 8D. Furthermore, using the resist R3 as a mask, dry etching is performed on the rib layer 5. As a result, pixel openings AP1, AP2, and AP3 that expose the lower electrodes LE1, LE2, and LE3 are formed in the rib layer 5, as shown in FIG. 8E. After the dry etching, the resist R3 is removed (peeled off). Note that the pixel openings AP1, AP2, and AP3 may be formed before the partition wall 6 is formed.

[0079] After step PR6, a step for forming the display element DE1 is performed (step PR7 in FIG. 6). To form the display element DE1, first, as shown in FIG. 8F, a stacked film FL1 and a sealing layer SE11 are formed over the entire mother substrate MB.

[0080] As shown in FIG. 3, the laminated film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed by, for example, vapor deposition. The sealing layer SE11 can be formed by, for example, CVD. The laminated film FL1 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6.

[0081] Next, the stacked film FL1 and the sealing layer SE11 are patterned. In this patterning, a resist R4 is disposed on the sealing layer SE11, as shown in Fig. 8F. The resist R4 covers the subpixel SP1 and part of the partition wall 6 around it.

[0082] Then, an etching process is performed using the resist R4 as a mask. As a result, as shown in FIG. 8G, the portions of the stacked film FL1 and the sealing layer SE11 exposed by the resist R4 are removed. In other words, the portions of the stacked film FL1 and the sealing layer SE11 that overlap the lower electrode LE1 are left, and the other portions are removed. This forms a display element DE1 in the subpixel SP1. The etching process may include wet etching or dry etching that is performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching processes, the resist R4 is removed (peeled off).

[0083] After step PR7, a step for forming display element DE2 is performed (step PR8 in FIG. 6). Display element DE2 can be formed using the same procedure as display element DE1. That is, when forming display element DE2, a stacked film FL2 and a sealing layer SE12 are formed over the entire mother substrate MB. As shown in FIG. 3, stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2.

[0084] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed by, for example, vapor deposition. The sealing layer SE12 can be formed by, for example, CVD. By patterning the stacked film FL2 and the sealing layer SE2, a display element DE2 is formed in the subpixel SP2, as shown in FIG. 8H.

[0085] After step PR8, a step for forming display element DE3 is performed (step PR9 in FIG. 6). Display element DE3 can be formed using the same procedure as display elements DE1 and DE2. That is, when forming display element DE3, a stacked film FL3 and a sealing layer SE13 are formed over the entire mother substrate MB. As shown in FIG. 3, stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3.

[0086] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed by, for example, vapor deposition. The sealing layer SE13 can be formed by, for example, CVD. By patterning the stacked film FL3 and the sealing layer SE13, a display element DE3 is formed in the subpixel SP3, as shown in FIG. 8I.

[0087] Although it is assumed here that the display elements DE1, DE2, and DE3 are formed in this order, the display elements DE1, DE2, and DE3 may be formed in a different order.

[0088] After the display elements DE1, DE2, and DE3 are formed, a resin layer RS1 is formed, for example, by an inkjet method (step PR10 in FIG. 6). After step PR10, a sealing layer SE2 is formed to cover the resin layer RS1, for example, by CVD (step PR11 in FIG. 6). Furthermore, a resin layer RS2 is formed to cover the sealing layer SE2, for example, by an inkjet method (step PR12 in FIG. 6).

[0089] After step PR11, the mother substrate MB is cut along the cut lines CT1 (step PR13 in FIG. 6). This cuts out the panel portion PP. The panel portion PP is further cut along the cut lines CT2 (step PR14 in FIG. 6). This completes the display device DSP. For cutting in steps PR13 and PR14, for example, laser cutting can be used, in which an infrared laser is irradiated along the cut lines CT1 and CT2. However, cutting in steps PR13 and PR14 may also be performed by other methods, such as scribe cutting.

[0090] In the present embodiment, the conductive oxide layers CL1 and CL2 are disposed on the reflective layers RF of the lower electrodes LE1, LE2, and LE3. If a single conductive oxide layer were formed instead of these conductive oxide layers CL1 and CL2, the following problems could arise.

[0091] That is, if the conductive oxide layer on the reflective layer RF has defects such as tiny pinholes, the etching solution may reach the reflective layer RF through the defects during various wet etching processes performed after the formation of the lower electrodes LE1, LE2, and LE3. In this case, at least a portion of the reflective layer RF may be lost. In contrast, forming a thick conductive oxide layer on the reflective layer RF can suppress the occurrence of defects such as pinholes. However, forming a thick conductive oxide layer on the reflective layer RF increases the time required for sputtering, and heat during sputtering is likely to accumulate in the conductive oxide layer. If this heat causes crystallization of the conductive oxide layer, the crystallized conductive oxide layer may not be completely removed by etching in step PR3f, resulting in the conductive oxide layer remaining in unintended locations.

[0092] In contrast, in this embodiment, the conductive oxide layer on the reflective layer RF is divided into a conductive oxide layer CL1 and a conductive oxide layer CL2. Furthermore, the conductive oxide layer CL2a, which is the base of the upper conductive oxide layer CL2, has low crystallinity due to the addition of water, as described above. The crystallization onset temperature of such a conductive oxide layer CL2a is higher than when water is not added. Therefore, even when the conductive oxide layer CL2a is formed thick, the conductive oxide layer CL2a is less likely to crystallize due to the heat generated during sputtering. Furthermore, the conductive oxide layer CL1a covered by the conductive oxide layer CL2a is less susceptible to heat, thereby suppressing crystallization of the conductive oxide layer CL1a. As a result, the conductive oxide layer CL1a and the conductive oxide layer CL2a can be efficiently removed by etching in step PR3f, improving the yield of the display device DSP.

[0093] If the conductive oxide layer CL2a is formed directly on the reflective layer RFa, the reflective layer RFa may be oxidized due to water vapor during the formation of the conductive oxide layer CL2a or moisture contained in the conductive oxide layer CL2a. In contrast, if a conductive oxide layer CL1a to which no water is added is provided between the reflective layer RFa and the conductive oxide layer CL2a as in this embodiment, the oxidation of the reflective layer RFa can be suppressed.

[0094] Here, the film formation conditions to be applied to the conductive oxide layers CL1a and CL2a to obtain the above-mentioned effects will be described. Fig. 9 is a table showing an example of the film formation conditions. For each of the conductive oxide layers CL1a and CL2a, the following preferable ranges are shown: thickness T [nm], film formation power W [kW] applied to the target during sputtering, water vapor flow rate Qa [sccm] into the atmosphere during sputtering, argon flow rate Qb [sccm] into the atmosphere during sputtering, and atmospheric pressure P [Pa] during sputtering.

[0095] The relationship between the thickness T1 of the conductive oxide layer CL1a and the thickness T2 of the conductive oxide layer CL2a is the same as that described above for the conductive oxide layers CL1 and CL2 in the description of FIG. 4. That is, the thickness T1 is 7 nm or more and 13 nm or less, and the thickness T2 is 15 nm or more and 20 nm or less. Also, the relationship T1 < T2 holds. Thus, by reducing the thickness T1, excessive heat accumulation during the formation of the conductive oxide layer CL1a and crystallization of the conductive oxide layer CL1a due to that heat can be suppressed. Note that the conductive oxide layer CL2a formed under the condition of water addition is difficult to crystallize even when formed thick as described above.

[0096] The film formation power W1 during sputtering of the conductive oxide layer CL1a is 2.0 kW or more and 4.0 kW or less. On the other hand, the film formation power W2 during sputtering of the conductive oxide layer CL2a is 6.0 kW or more and 10.0 kW or less. That is, the relationship W1 < W2 holds.

[0097] The water vapor flow rate Qa during sputtering of the conductive oxide layer CL1a is 0 sccm. On the other hand, the water vapor flow rate Qa during sputtering of the conductive oxide layer CL2a is, for example, 5 sccm.

[0098] The argon flow rate Qb1 during sputtering of the conductive oxide layer CL1a is 180 sccm or more and 220 sccm or less. On the other hand, the argon flow rate Qb2 during sputtering of the conductive oxide layer CL2a is 180 sccm or more and 220 sccm or less. That is, Qb1 and Qb2 are equivalent.

[0099] The pressure P1 during sputtering of the conductive oxide layer CL1a is 0.60 Pa or more and 0.80 Pa or less. On the other hand, the pressure P2 during sputtering of the conductive oxide layer CL2a is 0.30 Pa or more and 0.50 Pa or less. That is, the relationship P1 > P2 holds.

[0100] The conductive oxide layers CL1 and CL2 have different transmittances due to the difference in film formation conditions. Specifically, the transmittance of the conductive oxide layer CL2 is lower than that of the conductive oxide layer CL1. This point will be described in detail below.

[0101] 10 to 12 are graphs showing the transmittance of conductive oxide layers made of ITO when the conductive oxide layers are formed to thicknesses of 7 nm, 11 nm, and 25 nm, respectively. In each graph, the horizontal axis represents the wavelength of light λ [nm], and the vertical axis represents the transmittance TM [%]. The conductive oxide layers measured were formed by sputtering, then fired and crystallized.

[0102] In Figures 10 to 12, the dashed curves indicate the transmittance distribution of a conductive oxide layer formed without adding water (Qa = 0 sccm). The solid curves indicate the transmittance distribution of a conductive oxide layer formed with adding water (Qa = 5 sccm). In all of Figures 10 to 12, when adding water, the transmittance decreases across most wavelength ranges. The decrease tends to be particularly large in the short wavelength range (e.g., the blue wavelength range). Furthermore, the thicker the conductive oxide layer, the lower the transmittance.

[0103] The transmittance distribution of a laminate consisting of an ITO layer formed to a thickness of 7 nm without added water (Qa = 0 sccm) and an ITO layer formed to a thickness of 18 nm with added water (Qa = 5 sccm) is also shown by the dashed line in Figure 12. The transmittance distribution of this laminate is roughly equivalent to the transmittance distribution of a conductive oxide layer formed to a thickness of 25 nm with added water (shown by the solid line), but the transmittance is slightly improved in the wavelength range above 400 nm.

[0104] 10 to 12, the transmittance of the conductive oxide layer CL2 formed with added water is lower than that of the conductive oxide layer CL1 formed without added water. Furthermore, the thinner the conductive oxide layer CL2, the higher the transmittance of the conductive oxide layer CL2. In light of this, and from the viewpoint of favorable transmission of light reflected by the reflective layer RF, it is preferable to set the thickness of the conductive oxide layer CL2 within the range of thickness T2 shown in the table of FIG. 9.

[0105] [Second embodiment] A second embodiment will be described below, which discloses another configuration that can be applied to the lower electrodes LE1, LE2, and LE3.

[0106] 13 is a schematic cross-sectional view showing the configuration of lower electrodes LE1, LE2, and LE3 according to the second embodiment. In this embodiment, conductive oxide layers CL11, CL12, and CL13 are disposed in this order on a reflective layer RF. These conductive oxide layers CL11, CL12, and CL13 are all made of ITO. However, the conductive oxide layers CL11, CL12, and CL13 may also be made of a transparent conductive oxide other than ITO, such as IZO or IGZO.

[0107] The conductive oxide layers CL11, CL12, and CL13 are formed by sputtering under film formation conditions without adding water, similar to the conductive oxide layer CL1 (conductive oxide layer CL1a) in the first embodiment. For example, the conductive oxide layers CL11, CL12, and CL13 are formed by sputtering in the same chamber. However, after forming the conductive oxide layer CL11 and before forming the conductive oxide layer CL12, the mother substrate MB is temporarily removed from the chamber and cooled. Similarly, after forming the conductive oxide layer CL12, the mother substrate MB is temporarily removed from the chamber and cooled before forming the conductive oxide layer CL13.

[0108] By forming the conductive oxide layers CL11, CL12, and CL13 in this manner, it is possible to suppress the temperature rise due to heat accumulation during sputtering compared to when a thick conductive oxide layer is continuously formed on the reflective layer RF, and as a result, it is possible to suppress the crystallization of the conductive oxide layers CL11, CL12, and CL13 due to the heat during sputtering, as described above in the first embodiment.

[0109] The conductive oxide layers CL11, CL12, and CL13 have thicknesses T11, T12, and T13, respectively. In one example, the thicknesses T11, T12, and T13 are 7 nm or more and 13 nm or less. To give a more specific example, the thickness T11 is 7 nm, and the thicknesses T12 and T13 are each 9 nm. However, the values ​​of the thicknesses T11, T12, and T13 are not limited to this example.

[0110] In this embodiment, the conductive oxide layer on the reflective layer RF is divided into three layers, but the conductive oxide layer may be divided into four or more layers.

[0111] Furthermore, the configurations of the first and second embodiments can be combined as appropriate. For example, when the conductive oxide layer on the reflective layer RF is divided into three or four or more layers as in the second embodiment, the uppermost layer may be formed under film formation conditions with added water, as in the conductive oxide layer CL2 (conductive oxide layer CL2a) in the first embodiment.

[0112] All display devices and manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the display devices and manufacturing methods disclosed in the above embodiments also fall within the scope of the present invention as long as they include the gist of the present invention.

[0113] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0114] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0115] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, RF...reflective layer, CL1, CL2, CL3...conductive oxide layer, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE2...sealing layer, MB...motherboard, PP...panel portion, 5...rib layer, 6...partition wall.

Claims

1. a substrate having a display area for displaying an image; an insulating layer disposed above the substrate; a display element including a first electrode disposed above the insulating layer in the display region; Equipped with The first electrode is a transparent first conductive oxide layer; a transparent second conductive oxide layer covering the first conductive oxide layer; Including, the transmittance of the second conductive oxide layer is lower than the transmittance of the first conductive oxide layer; Display device.

2. an end of the first conductive oxide layer and an end of the second conductive oxide layer are aligned; The display device according to claim 1 .

3. the second conductive oxide layer is thicker than the first conductive oxide layer; The display device according to claim 1 .

4. The first electrode is a reflective layer covered with the first conductive oxide layer; a transparent third conductive oxide layer covered by the reflective layer; further comprising: The display device according to claim 1 .

5. the third conductive oxide layer is thinner than the second conductive oxide layer; The display device according to claim 4 .

6. the first conductive oxide layer and the second conductive oxide layer are formed of ITO; The display device according to any one of claims 1 to 5.

7. a rib layer covering an end portion of the first electrode and having a pixel opening overlapping the first electrode; The display element is an organic layer that contacts the first electrode through the pixel opening and emits light in response to application of a voltage; a second electrode covering the organic layer; further comprising: The display device according to any one of claims 1 to 5.

8. a partition wall surrounding the pixel opening; The partition wall is a conductive lower portion disposed above the rib layer; an upper portion having an end portion protruding from a side surface of the lower portion; Including, the second electrode is in contact with the lower portion; The display device according to claim 7 .

9. forming an insulating layer above the substrate; forming a first electrode of a display element above the insulating layer; This includes: The first electrode is a transparent first conductive oxide layer; a transparent second conductive oxide layer covering the first conductive oxide layer; Including, The formation of the first electrode includes: forming the first conductive oxide layer by performing a first sputtering in an atmosphere that does not contain water vapor; forming the second conductive oxide layer by performing a second sputtering in an atmosphere containing water vapor; A method for manufacturing a display device, comprising:

10. The formation of the first electrode includes: placing a resist in the shape of the first electrode on the second conductive oxide layer; removing the portions of the first conductive oxide layer and the second conductive oxide layer exposed from the resist by etching; Including, The method for manufacturing a display device according to claim 9 .

11. an etching rate of the second conductive oxide layer in the etching is greater than an etching rate of the first conductive oxide layer in the etching; The method for manufacturing a display device according to claim 10 .

12. The power applied to the target in the second sputtering is greater than the power applied to the target in the first sputtering. The method for manufacturing a display device according to claim 9 .

13. the pressure of the atmosphere in the second sputtering is lower than the pressure of the atmosphere in the first sputtering; The method for manufacturing a display device according to claim 9 .

14. the pressure of the atmosphere in the first sputtering is 0.6 Pa or more and 0.8 Pa or less; the pressure of the atmosphere in the second sputtering is 0.3 Pa or more and 0.5 Pa or less; The method for manufacturing a display device according to claim 13 .

15. the first conductive oxide layer is formed thinner than the second conductive oxide layer; The method for manufacturing a display device according to claim 9 .

16. the thickness of the first conductive oxide layer is 7 nm or more and 13 nm or less; the thickness of the second conductive oxide layer is 15 nm or more and 20 nm or less; The method for manufacturing a display device according to claim 15.

17. The formation of the first electrode includes: forming a transparent third conductive oxide layer before forming the first conductive oxide layer; forming a reflective layer covering the third conductive oxide layer; It further includes: the first conductive oxide layer is formed to cover the reflective layer; The method for manufacturing a display device according to claim 9 .

18. the first conductive oxide layer and the second conductive oxide layer are formed of ITO; A method for manufacturing the display device according to any one of claims 9 to 17.

19. forming a rib layer that covers an end portion of the first electrode and has a pixel opening that overlaps the first electrode; forming an organic layer that contacts the first electrode through the pixel opening and emits light in response to application of a voltage; forming a second electrode covering the organic layer; further comprising: A method for manufacturing the display device according to any one of claims 9 to 17.

20. forming a partition wall surrounding the pixel opening after forming the rib layer and before forming the organic layer and the second electrode; The partition wall is a conductive lower portion disposed above the rib layer; an upper portion having an end portion protruding from a side surface of the lower portion; Equipped with the second electrode is formed to contact the lower portion. The method for manufacturing a display device according to claim 19.

Images