Optical signal receiver and optical signal receiving method
The optical signal receiver addresses the challenges of high-speed signal processing by dividing buffered digital signals into FFT blocks and performing parallel frequency domain equalization, achieving efficient filter coefficient updates and equalization.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2026-03-10
AI Technical Summary
Conventional adaptive filtering methods face challenges in high-speed signal processing due to increased calculation time and inability to accommodate rapid signal fluctuations, particularly in long-distance or high-speed optical transmission scenarios, especially when implementing filters with a large number of taps.
An optical signal receiver that buffers digital signals into unit intervals, divides them into multiple FFT blocks, and performs frequency domain equalization processing in parallel using multiple threads to update filter coefficients efficiently.
Enables high-speed filter coefficient updating and equalization processing, even with large numbers of taps, by utilizing parallel processing and thread-based updates.
Smart Images
Figure 2026040874000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to an optical signal receiver and an optical signal receiving method. [Background technology]
[0002] In real-time hardware implementations of adaptive filtering, filter coefficients are updated based on the results of filtering input data. On the other hand, in real-time software implementations of Digital Signal Processing (DSP), high-frequency data transfers are avoided compared to hardware implementations, so long input data is stored and processed in batches.
[0003] In conventional adaptive filter processing for polarization multiplexed signals, in order to deal with cases where the optimal filter coefficients fluctuate over time, the filter coefficients for each data in the buffer are updated before filter processing is performed. Furthermore, dividing the buffer has also been proposed (see, for example, Non-Patent Document 1). Specifically, the buffer is divided into multiple regions, and common filter coefficients are used within each region, with multiple threads used to calculate the filter coefficients within each region. This configuration achieves high-speed processing of the adaptive filter.
[0004] FIG. 7 shows a specific example of such a conventional configuration. In the configuration shown in FIG. 7, the signal is divided into regions of L symbols, and a filter coefficient h is calculated based on the results of filtering P symbols. Filtering is then performed on all L symbols using an average value of multiple calculated filter coefficients. However, when chromatic dispersion is significant, such as in long-distance or high-speed transmission, appropriate waveform equalization is required. This requires increasing the number of taps in the filter that compensates for chromatic dispersion. This increases the amount of calculation required for adaptive filtering.
[0005] Figure 8 is a flowchart showing a specific example of processing using a conventional frequency domain filter. When variance is large, such as in long-distance, high-speed transmission, or when the number of taps is large, a frequency domain filter is suitable for filter processing (see, for example, Non-Patent Document 2). In Figure 8, FFT represents Fourier transform, and IFFT represents inverse Fourier transform. Furthermore, filter processing refers to filter calculation in the frequency domain, error calculation refers to the process of calculating the error of the filter output relative to the target value, and filter update refers to the process of updating the filter based on the error. [Prior art documents] [Non-patent literature]
[0006] [Non-Patent Document 1] Takahiro Suzuki, Sang-Yuep Kim, Jun-ichi Kani, and Tomoaki Yoshida, "Real-Time Polarization Demultiplexing by Multi-Thread Constant Modulus Algorithm for Fully Softwarized Access Networks" IEEE / OSA Journal of Lightwave Technology, Vol. 41, Issue 5, pp. 1346-1356, Mar. 2023 [Non-patent document 2] JJ Shynk, “Frequency-domain and multirate adaptive filtering”, IEEE Signal processing magazine, vol. 9, no. 1, pp. 14-37, 1992. Summary of the Invention [Problem to be solved by the invention]
[0007] However, implementing an adaptive filter in software has the following problems. With the technology disclosed in Non-Patent Document 1, as mentioned above, the calculation time increases significantly when the number of taps increases. Furthermore, with the technology disclosed in Non-Patent Document 2, the filter is updated sequentially and cannot accommodate high-speed signal fluctuations. Note that these problems are not necessarily limited to software implementation; similar problems, although to varying degrees, can occur even when some or all of the filter is implemented in hardware.
[0008] The present invention has been made in view of the above circumstances, and provides a technique that enables equalization processing to be performed in a shorter time. [Means for solving the problem]
[0009] One aspect of the present invention is an optical signal receiver comprising: a buffer that buffers a digital signal of a received optical signal and outputs a digital signal of a unit interval including a predetermined number of samples from the digital signal; a division unit that divides the digital signal of the unit interval into a predetermined number of FFT blocks (two or more); and an equalization unit that performs frequency domain equalization processing on the digital signals of the FFT blocks in parallel.
[0010] One aspect of the present invention is an optical signal receiving method comprising the steps of: buffering a digital signal of a received optical signal; outputting a digital signal of a unit interval including a predetermined number of samples from the digital signal; dividing the digital signal of the unit interval into two or more predetermined number of FFT blocks; and performing frequency domain equalization processing on the digital signals of the FFT blocks in parallel. [Effects of the Invention]
[0011] The present invention allows the equalization process to be performed in a shorter time. [Brief explanation of the drawings]
[0012] [Figure 1]1 is a schematic block diagram showing the functional configuration of an optical signal receiver 10 according to the present invention. [Figure 2] FIG. 10 is a diagram showing an outline of division processing performed by a processor 15. [Figure 3] FIG. 2 is a schematic block diagram showing an outline of the functions of a processor 15. [Figure 4] The overall process of filter processing and filter update performed by the processor 15 is shown. [Figure 5] 10 is a flowchart showing a specific example of the flow of processing performed by the optical signal receiver 10. [Figure 6] FIG. 2 is a diagram illustrating an outline of an example of the hardware configuration of an information processing device 90 applied to the present embodiment. [Figure 7] FIG. 1 is a diagram showing a specific example of a conventional configuration. [Figure 8] 1 is a flowchart illustrating an example of a process employing a conventional frequency domain filter. DETAILED DESCRIPTION OF THE INVENTION
[0013] In the following description, subscripts (characters written in relatively small letters to the lower right of other characters) may be shown with an underscore next to the other characters. For example, if B is written in relatively small letters to the lower right of A as a subscript, it may be shown as "A_B."
[0014] [Summary] A digital signal processing device of the present invention will be described. The optical signal receiver of the present invention is a device used in optical communications. In the present invention, a set of multiple digital signal values received by the optical signal receiver is buffered and the buffered set of multiple digital signal values is divided into multiple FFT blocks. The optical signal receiver then executes processing to be performed on the set of buffered digital signal values in parallel for the multiple FFT blocks. Specific examples of such processing include Fourier transform, frequency domain filtering, and filter coefficient calculation. The filter coefficient calculation may involve, for example, updating filter coefficients in multiple threads based on the output obtained as a result of the filtering process (hereinafter referred to as "filter output"), and calculating a representative filter coefficient based on the multiple filter coefficients. This configuration enables filter coefficients to be updated in a shorter time, even for filters with a large number of taps.
[0015] [detail] 1 is a schematic block diagram showing the functional configuration of an optical signal receiver 10 according to the present invention. The optical signal receiver 10 may be used, for example, as an optical coherent receiver. The optical signal receiver 10 includes an optical front end 11, multiple ADCs 12, an IF card 13, a buffer 14, and a processor 15.
[0016] The optical front end 11 receives an optical signal from a transmission line and converts the received optical signal into an electrical signal. For example, the optical front end 11 may separate orthogonal components of the received optical signal and convert them into electrical signals.
[0017] The ADC 12 performs analog-to-digital conversion processing on the electrical signal output from the optical front end 11 and outputs a digital signal. The IF card 13 transfers the digital signal output from the ADC 12 to the buffer 14.
[0018] The buffer 14 functions as a memory for the processor 15. The transfer from the IF card 13 to the buffer 14 may be implemented by, for example, Direct Memory Access (DMA). The buffer 14 is configured using a semiconductor storage device.
[0019] The buffer 14 holds the digital signals transferred from the IF card 13. The buffer 14 transfers to the processor 15 a predetermined number of samples of the digital signals it holds.
[0020] The processor 15 functions as a digital signal processing device. The processor 15 may operate in cooperation with a memory (main storage device) (not shown). The processor 15 functions by executing a program stored in advance in the memory.
[0021] All or part of the functions of the optical signal receiver 10 may be realized using hardware such as an ASIC (Application Specific Integrated Circuit), a PLD (Programmable Logic Device), or an FPGA (Field Programmable Gate Array). The above program may be recorded on a computer-readable recording medium. Examples of computer-readable recording media include portable media such as flexible disks, magneto-optical disks, ROMs, CD-ROMs, and semiconductor storage devices (e.g., SSDs: Solid State Drives), as well as storage devices such as hard disks and semiconductor storage devices built into computer systems. The above program may be transmitted via a telecommunications line.
[0022] FIG. 2 is a diagram illustrating an outline of the division process performed by the processor 15. The buffer 14 transfers N_S samples (N_S is an integer greater than or equal to 2) to the processor 15 as data for one unit interval. Data is transferred from the buffer 14 to the processor 15 for each unit interval. When the processor 15 receives data for one unit interval (N_S samples), it divides the received data for one unit interval into multiple FFT blocks. Dividing into FFT blocks. In the example of FIG. 2, the data for one unit interval is divided into N_B FFT blocks (N_B is an integer greater than or equal to 2). One FFT block contains N_F samples (N_F is an integer greater than or equal to 2). Therefore, the following relationship holds between the number of samples N_S included in one unit interval, the number of samples N_F included in one FFT block, and the number N_B of FFT blocks generated by the division: N_S=N_B×N_F
[0023] FIG. 3 is a schematic block diagram illustrating an outline of the functions of the processor 15. As shown in FIG. 3, the processor 15 executes the above-described program to function as an FFT block division unit 151 and multiple FDEs 152. The multiple FDEs 152 operate on multiple threads of the processor and function as a multi-threaded FDE. The processor 15 preferably includes N_B or more FDEs 152. Upon receiving data for one unit interval from the buffer 14, the FFT block division unit 151 divides the data for one unit interval into N_B FFT blocks. The FFT block division unit 151 batch-transfers the divided N_B FFT blocks to the corresponding FDEs 152. Upon receiving an FFT block (N_F samples), each FDE 152 performs frequency-domain equalization processing on the received data. With this configuration, the multi-threaded FDE adaptively performs frequency-domain equalization processing (filtering processing) on data for one unit interval (data for multiple FFT blocks) in N_B parallel fashion.
[0024] FIG. 4 shows the overall processing of filter processing and filter update performed by processor 15. Processor 15 calculates errors from the results of frequency-domain filter processing. In the example of FIG. 4, processor 15 performs filter coefficient update processing using multiple threads in parallel for four filter coefficients. Specifically, processor 15 performs Fourier transforms and frequency-domain filter processing in parallel for multiple FFT blocks. Processor 15 updates the filter coefficients using multiple threads based on the filter output. Then, processor 15 calculates a representative filter coefficient from the multiple filter coefficients. For example, processor 15 may calculate the average of each filter coefficient as the representative value of the filter coefficient.
[0025] 5 is a flowchart showing a specific example of the flow of processing performed by the optical signal receiver 10. The buffer 14 buffers the received data (step S101). The buffer 14 transfers the buffered data to the processor 15 for each unit interval (step S102). When the FFT block division unit 151 of the processor 15 receives the data for the unit interval, it divides the data for the unit interval into multiple (N_B) FFT blocks (step S103). The FFT block division unit 151 transfers the N_B FFT blocks in parallel to the FDE 152 in a batch (step S104). The multiple FDEs 152 perform filtering and filter coefficient updating for each FFT block in parallel (step S105). That is, the multiple FDEs 152 perform equalization processing in parallel.
[0026] With this configuration, high-speed filter coefficient updating is achieved even when the number of taps is large by combining section division of buffer samples, parallel filter processing, and updating of filter coefficients in multiple threads.
[0027] 6 is a diagram showing an outline of an example hardware configuration of an information processing device 90 applied to this embodiment. The information processing device 90 includes a processor 91, a main memory device 92, an auxiliary memory device 93, an input / output interface 94, and an internal bus 95. The processor 91, the main memory device 92, the auxiliary memory device 93, and the input / output interface 94 are communicably connected to each other via the internal bus 95. The information processing device 90 may be applied to, for example, the optical signal receiver 10.
[0028] Although an embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and includes designs within the scope of the gist of the present invention. [Explanation of symbols]
[0029] 10...optical signal receiver, 11...optical front end, 12...ADC, 13...IF card, 14...buffer, 15...processor, 151...FFT block division unit, 152...FDE (Frequency Domain Equalization)
Claims
1. a buffer that buffers a digital signal of a received optical signal and outputs a digital signal of a unit section including a predetermined number of samples from the digital signal; a division unit that divides the digital signal of the unit interval into a predetermined number of FFT blocks that is equal to or greater than two; an equalization unit that performs frequency domain equalization processing on the digital signals of the FFT blocks in parallel; An optical signal receiver comprising:
2. 2. The optical signal receiver according to claim 1, comprising at least the predetermined number of equalization sections.
3. 2. The optical signal receiver according to claim 1, wherein the dividing unit transfers the predetermined number of FFT blocks to the equalization unit in a batch.
4. buffering a digital signal of the received optical signal; outputting a digital signal of a unit section including a predetermined number of samples from the digital signal; Dividing the digital signal of the unit section into a predetermined number of FFT blocks, which is equal to or greater than two; performing frequency domain equalization processing on the digital signals of the FFT blocks in parallel; An optical signal receiving method comprising: