Electro-optical device and electronic device

Abstract

In the configuration of the prior art, it is difficult to reduce the influence of the parasitic capacitance generated between the wirings. [Solution] The electro-optical device comprises a first transistor of a first conductivity type, a second transistor of a second conductivity type, a first source-drain electrode electrically connected to a first source-drain region of the first transistor, a second source-drain electrode electrically connected to a second source-drain region of the second transistor, a first scanning line arranged in a first layer between the first transistor and the first source-drain electrode and electrically connected to a first gate electrode of the first transistor, and a second scanning line arranged in a second layer on the opposite side of the second source-drain electrode from the second transistor side and electrically connected to a second gate electrode of the second transistor.

Description

[Technical Field]

[0001] The present disclosure relates to an electro-optical device and an electronic device. [Background technology]

[0002] Liquid crystal display devices having transistors are known. Liquid crystal display devices are an example of electro-optical devices. The liquid crystal display device described in Patent Document 1 includes data lines, gate lines, and thin film transistors for pixels. The data lines and gate lines intersect at right angles. Pixel regions are formed at positions corresponding to the intersections of the data lines and gate lines. In the pixel regions, liquid crystal cells are formed to which image signals are input via thin film transistors. The thin film transistors include N-type thin film transistors and P-type thin film transistors. The gate lines are formed of a first gate line and a second gate line. The first gate line is connected to the N-type thin film transistor. The second gate line is connected to the P-type thin film transistor. The first gate line and the second gate line are arranged on the same plane of the liquid crystal display device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 9-189922 Summary of the Invention [Problem to be solved by the invention]

[0004] In the configuration of the prior art, it is difficult to reduce the influence of the parasitic capacitance generated between the wirings. [Means for solving the problem]

[0005] The electro-optical device of the present disclosure comprises a first transistor of a first conductivity type, a second transistor of a second conductivity type, a first source-drain electrode electrically connected to a first source-drain region of the first transistor, a second source-drain electrode electrically connected to a second source-drain region of the second transistor, a first scanning line disposed in a first layer between the first transistor and the first source-drain electrode and electrically connected to a first gate electrode of the first transistor, and a second scanning line disposed in a second layer on the opposite side of the second source-drain electrode from the second transistor side and electrically connected to a second gate electrode of the second transistor.

[0006] An electronic device according to the present disclosure includes the electro-optical device described above. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a schematic configuration of a liquid crystal device. [Figure 2] FIG. 1 is a diagram schematically illustrating a configuration of a liquid crystal device. [Figure 3] FIG. 2 is a diagram showing the electrical configuration of an element substrate. [Figure 4] FIG. 2 is a diagram showing a schematic configuration of a first element substrate. [Figure 5] FIG. 2 is a diagram showing a schematic configuration of a first element substrate. [Figure 6] FIG. 2 is a diagram showing a schematic configuration of a first element substrate. [Figure 7] FIG. 2 is a diagram showing a schematic configuration of a first element substrate. [Figure 8] FIG. 2 is a diagram showing a schematic configuration of a first element substrate. [Figure 9] 3A to 3C are diagrams showing a process for producing a first element substrate. [Figure 10] 3A to 3C are diagrams showing a process for producing a first element substrate. [Figure 11] 3A to 3C are diagrams showing a process for producing a first element substrate. [Figure 12] 3A to 3C are diagrams showing a process for producing a first element substrate. [Figure 13] 3A to 3C are diagrams showing a process for producing a first element substrate. [Figure 14]3A to 3C are diagrams showing a process for producing a first element substrate. [Figure 15] 3A to 3C are diagrams showing a process for producing a first element substrate. [Figure 16] 3A to 3C are diagrams showing a process for producing a first element substrate. [Figure 17] FIG. 3 is a diagram showing a schematic configuration of a second element substrate. [Figure 18] FIG. 3 is a diagram showing a schematic configuration of a second element substrate. [Figure 19] FIG. 3 is a diagram showing a schematic configuration of a second element substrate. [Figure 20] 5A to 5C are diagrams showing a process for producing a second element substrate. [Figure 21] 5A to 5C are diagrams showing a process for producing a second element substrate. [Figure 22] 5A to 5C are diagrams showing a process for producing a second element substrate. [Figure 23] 5A to 5C are diagrams showing a process for producing a second element substrate. [Figure 24] 5A to 5C are diagrams showing a process for producing a second element substrate. [Figure 25] 5A to 5C are diagrams showing a process for producing a second element substrate. [Figure 26] FIG. 1 is a diagram showing a schematic configuration of a projection display device. DETAILED DESCRIPTION OF THE INVENTION

[0008] FIG. 1 shows a schematic configuration of a liquid crystal device 100. The liquid crystal device 100 corresponds to an example of an electro-optical device. The liquid crystal device 100 is an active-drive transmissive liquid crystal device that includes a TFT (Thin Film Transistor) as a switching element for each pixel P. FIG. 1 shows a plan view of the liquid crystal device 100. The liquid crystal device 100 includes an element substrate 10, a counter substrate 20, and a sealing member 60. The liquid crystal device 100 includes a display area A1 and a peripheral area A2.

[0009] In some figures, including Figure 1, the dimensions of each component may be drawn differently from their actual dimensions to make each component easier to understand. The dimensional ratios of each component in the drawings may differ from those of the actual components.

[0010] Several figures, including FIG. 1, illustrate an XYZ coordinate system. The X, Y, and Z directions are perpendicular to one another. The Z direction is parallel to the direction in which the element substrate 10 and the counter substrate 20 are stacked. The +Z direction is the direction from the element substrate 10 toward the counter substrate 20. The -Z direction is the direction from the counter substrate 20 toward the element substrate 10. The X direction is parallel to the direction in which the external connection terminals 105 are arranged. The +X direction is the direction from left to right in FIG. 1. The -X direction is the direction from right to left in FIG. 1. The Y direction is perpendicular to the X and Z directions. The +Y direction is the direction from bottom to top in FIG. 1. The -Y direction is the direction from top to bottom in FIG. 1.

[0011] The element substrate 10 is disposed on the light-emitting side of the liquid crystal layer 50. The element substrate 10 is made of a light-transmitting material. Light-transmitting means that the element has transparency to visible light. Light-transmitting preferably means that the transmittance of visible light is 50% or more. The element substrate 10 is configured to be approximately rectangular in plan view from the +Z direction. The element substrate 10 is bonded to the counter substrate 20 via a sealing member 60. The element substrate 10 is configured to be larger than the counter substrate 20 in plan view from the +Z direction. The element substrate 10 has a data line driving circuit 101, a scanning line driving circuit 103, an inspection circuit (not shown), and a plurality of external connection terminals 105.

[0012] The data line driving circuit 101 is electrically connected to a plurality of data lines 5, which will be described later. The data line driving circuit 101 supplies an image signal to each of the plurality of data lines 5.

[0013] The scanning line driving circuit 103 is electrically connected to a plurality of scanning lines 3, which will be described later. The scanning line driving circuit 103 supplies a scanning signal to each of the plurality of scanning lines 3.

[0014] The test circuit is electrically connected to the plurality of data lines 5. The test circuit supplies a test signal to each of the plurality of data lines 5.

[0015] The external connection terminals 105 are mounting terminals on which external connection lines such as FPCs (Flexible Printed Circuits) (not shown) are mounted. Various signals such as image signals, synchronization signals, inspection signals, common potentials, and power supply potentials are supplied from the outside via the external connection lines to the external connection terminals 105. The external connection terminals 105 are provided in an area of ​​the element substrate 10 that does not overlap with the counter substrate 20.

[0016] The counter substrate 20 is disposed on the light incident side of the liquid crystal layer 50. The counter substrate 20 is configured to have a substantially rectangular shape when viewed from above in the +Z direction. The counter substrate 20 is configured from a light-transmitting material. The counter substrate 20 is bonded to the element substrate 10 via a sealing member 60.

[0017] The sealing member 60 is provided in a frame shape surrounding the display area A1. The sealing member 60 is disposed between the element substrate 10 and the counter substrate 20. The sealing member 60 is made of an adhesive or the like containing a curable resin such as an epoxy resin.

[0018] The display area A1 is provided in an area inside the seal member 60. The display area A1 is a pixel area including a plurality of pixels P. The plurality of pixels P are arranged in a matrix along the X direction and the Y direction.

[0019] The peripheral region A2 is provided in an area outside the display region A1. The peripheral region A2 is provided in a rectangular shape surrounding the display region A1. The peripheral region A2 is provided with a sealing member 60, a data line driving circuit 101, a scanning line driving circuit 103, etc. Dummy pixels that do not contribute to display may be arranged in the peripheral region A2.

[0020] Fig. 2 schematically illustrates the configuration of the liquid crystal device 100. Fig. 2 illustrates a cross section along the YZ plane, including the line AA in Fig. 1. Fig. 2 illustrates the size and number of liquid crystals 50a included in the liquid crystal layer 50 in a manner different from the actual size and number.

[0021] The liquid crystal device 100 shown in FIG. 2 is a transmissive liquid crystal device. Incident light L is incident on the +Z direction surface of the counter substrate 20. The incident light L passes through the liquid crystal layer 50 and exits from the -Z direction surface of the element substrate 10. When passing through the liquid crystal layer 50, the incident light L is modulated according to the alignment state of the liquid crystals 50a. The incident surface of the incident light L is not limited to the +Z direction surface of the counter substrate 20. The incident surface of the incident light L may also be the -Z direction surface of the element substrate 10. The liquid crystal device 100 is not limited to a transmissive liquid crystal device. The liquid crystal device 100 may be a reflective liquid crystal device. The liquid crystal device 100 employs an optical design for a normally white mode or a normally black mode. The liquid crystal device 100 may include a polarizing element.

[0022] The element substrate 10 and the counter substrate 20 are disposed opposite each other with a sealing member 60 interposed therebetween. The liquid crystal layer 50 is disposed between the element substrate 10 and the counter substrate 20. The liquid crystal layer 50 is disposed at a position surrounded by the element substrate 10, the counter substrate 20, and the sealing member 60.

[0023] The liquid crystal layer 50 includes liquid crystal 50a. The liquid crystal 50a has positive or negative dielectric anisotropy. The liquid crystal 50a shown in Figure 2 has negative dielectric anisotropy, for example. The liquid crystal 50a is made up of individual liquid crystal molecules or an aggregate of individual liquid crystal molecules.

[0024] The element substrate 10 has an element substrate base 11, pixel electrodes 15, and a first alignment film 18. The element substrate base 11, pixel electrodes 15, and first alignment film 18 are arranged facing the liquid crystal layer 50 in this order: element substrate base 11, pixel electrodes 15, and first alignment film 18.

[0025] The element substrate base 11 is a flat plate that is light-transmitting and insulating. The element substrate base 11 is made of a glass substrate or a quartz substrate. The element substrate base 11 is disposed on the exit side of the liquid crystal layer 50, from which light that has passed through the liquid crystal layer 50 is emitted.

[0026] The pixel electrode 15 is provided in the display region A1. The pixel electrode 15 is light-transmitting. For example, the pixel electrode 15 is made of ITO (Indium Tin Oxide). The pixel electrode 15 may also be made of a transparent conductive material such as IZO (Indium Zinc Oxide) or FTO (Fluorine-doped tin oxide).

[0027] The first alignment film 18 aligns the liquid crystal 50a. The first alignment film 18 is formed based on the optical design of the liquid crystal device 100. The first alignment film 18 is disposed in a position where it contacts the sealing member 60. The first alignment film 18 has a region that contacts the -Z direction surface of the sealing member 60 and a region that faces the liquid crystal layer 50. The first alignment film 18 is disposed between the multiple pixel electrodes 15 and the liquid crystal layer 50. The first alignment film 18 includes a first evaporated film 18a and a second evaporated film 18b.

[0028] The first deposited film 18a is formed by vacuum deposition from above the +Z direction surface of the element substrate 10. The first deposited film 18a includes a plurality of columns whose major axes are aligned in the Z direction. The first deposited film 18a is made of silicon oxide, aluminum oxide, magnesium oxide, or the like.

[0029] The second deposited film 18b is formed on the first deposited film 18a. The thickness of the second deposited film 18b in the Z direction is thinner than the thickness of the first deposited film 18a in the Z direction. The second deposited film 18b includes multiple columns whose major axes intersect with the Z direction at a predetermined angle. The columns of the second deposited film 18b are columnar crystals of silicon oxide. The columns of the second deposited film 18b are formed by oblique deposition using a vacuum deposition method.

[0030] The counter substrate 20 has a counter substrate base 21, a parting portion 24, an insulating layer 25, a common electrode 22, and a second alignment film 23. The counter substrate base 21, the parting portion 24, the insulating layer 25, the common electrode 22, and the second alignment film 23 are arranged in this order facing the liquid crystal layer 50.

[0031] The counter substrate base 21 is a flat plate that is light-transmitting and insulating. The counter substrate base 21 is disposed on the incident side where the incident light L is incident. The counter substrate base 21 is made of a glass substrate or a quartz substrate. As an example, the counter substrate base 21 is made of silicon oxide (SiO2) with a refractive index of 1.48.

[0032] The parting portion 24 is made of a light-shielding metal film, etc. The parting portion 24 is disposed at a position further in the +Z direction than the common electrode 22.

[0033] The insulating layer 25 has light-transmitting and insulating properties. The insulating layer 25 is made of an inorganic material such as silicon oxide. The insulating layer 25 may function as an optical path adjustment layer that adjusts the optical path of the incident light L.

[0034] The common electrode 22 is disposed opposite the plurality of pixel electrodes 15. The common electrode 22 is formed of ITO. The common electrode 22 may also be formed of a transparent conductive material such as IZO or FTO. The common electrode 22 and the pixel electrodes 15 apply an electric field to the liquid crystal layer 50. The common electrode 22 is electrically connected to one of the plurality of external connection terminals 105 provided on the element substrate 10. A common electrode potential is applied to the common electrode 22 via the external connection terminal 105. The common electrode potential is, for example, 6.5 V.

[0035] The second alignment film 23 aligns the liquid crystal 50a. The second alignment film 23 is formed based on the optical design of the liquid crystal device 100. The second alignment film 23 is disposed in a position where it contacts the sealing member 60. The second alignment film 23 has a region that contacts the surface of the sealing member 60 in the +Z direction and a region that faces the liquid crystal layer 50. The second alignment film 23 is disposed between the common electrode 22 and the liquid crystal layer 50. The second alignment film 23 includes a third evaporated film 23a and a fourth evaporated film 23b.

[0036] The third deposited film 23a is formed by vacuum deposition on the −Z direction surface of the opposing substrate 20. The third deposited film 23a includes a plurality of columns whose major axes are aligned in the Z direction. The third deposited film 23a is made of silicon oxide, aluminum oxide, magnesium oxide, or the like.

[0037] The fourth deposited film 23b is formed on the third deposited film 23a. The thickness of the fourth deposited film 23b in the Z direction is thinner than the thickness of the third deposited film 23a in the Z direction. The fourth deposited film 23b includes multiple columns whose major axes intersect with the Z direction at a predetermined angle. The columns of the fourth deposited film 23b are columnar crystals of silicon oxide. The columns of the fourth deposited film 23b are formed by oblique deposition using a vacuum deposition method.

[0038] The first alignment film 18 and the second alignment film 23 align the liquid crystal 50a, which has negative dielectric anisotropy, in a substantially vertical direction. The substantially vertical alignment is an inverted alignment state where a pretilt angle of less than 90° is applied. The first alignment film 18 and the second alignment film 23 apply a pretilt to align the liquid crystal 50a vertically. The tilt direction of the pretilt is along a direction intersecting the X and Y directions. When the liquid crystal layer 50 is driven, the alignment state of the liquid crystal 50a, which is vertically aligned due to the pretilt, changes in the tilt direction.

[0039] 2 are each made up of two layers, but are not limited to this. The first alignment film 18 and the second alignment film 23 may each be made up of three or more layers.

[0040] FIG. 3 shows the electrical configuration of the element substrate 10. FIG. 3 shows the electrical configuration of the element substrate 10 in the form of an equivalent circuit diagram. A plurality of transistors 1, a plurality of scanning lines 3, a plurality of data lines 5, and a plurality of pixel electrodes 15 are provided in the display region A1 of the element substrate 10. The plurality of scanning lines 3 are electrically connected to a scanning line driving circuit 103. The plurality of data lines 5 are electrically connected to a data line driving circuit 101. The plurality of scanning lines 3 and the plurality of data lines 5 are insulated from each other. The transistor 1, the pixel electrode 15, and the capacitor 16 are provided in a region of a pixel P separated by the scanning lines 3 and the data lines 5. The transistor 1, the pixel electrode 15, and the capacitor 16 constitute a pixel circuit of the pixel P.

[0041] The transistors 1 are switching elements provided corresponding to the pixel electrodes 15. One example of the transistors 1 is a TFT (Thin Film Transistor). The transistors 1 are provided corresponding to each intersection of the plurality of scanning lines 3 and the plurality of data lines 5. The plurality of transistors 1 include an N-channel transistor 1a and a P-channel transistor 1b. The N-channel transistor 1a corresponds to an example of a first transistor of a first conductivity type. The P-channel transistor 1b corresponds to an example of a second transistor of a second conductivity type.

[0042] 3, the N-channel transistors 1a and the P-channel transistors 1b are alternately arranged along the X and Y directions, but this is not limiting. The N-channel transistors 1a and the P-channel transistors 1b may be alternately arranged in rows or columns, or may be alternately arranged every predetermined number of transistors. It is preferable that the N-channel transistors 1a and the P-channel transistors 1b be alternately arranged along the X and Y directions.

[0043] The scanning lines 3 are electrically connected to the gate electrodes 73 of the transistors 1. The scanning lines 3 shown in FIG. 3 extend along the X direction. The scanning lines 3 include an N-channel scanning line 31 provided corresponding to the N-channel transistor 1a and a P-channel scanning line 32 provided corresponding to the P-channel transistor 1b. The N-channel scanning line 31 corresponds to an example of a first scanning line. The P-channel scanning line 32 corresponds to an example of a second scanning line. The arrangement of the N-channel scanning line 31 and the P-channel scanning line 32 will be described later. The N-channel scanning line 31 simultaneously controls the on / off of the N-channel transistors 1a provided in the same row. The P-channel scanning line 32 simultaneously controls the on / off of the P-channel transistors 1b provided in the same row. The N-channel scanning line 31 and the P-channel scanning line 32 are electrically connected to the scanning line driving circuit 103. The scanning lines 3 supply scanning signals provided from the scanning line driving circuit 103 to the pixels P. The scanning signal is supplied to the scanning line 3 at a predetermined timing.

[0044] The data line 5 is electrically connected to the first data line side source / drain region 71d of the N-channel transistor 1a or the second data line side source / drain region 72d of the P-channel transistor 1b. The first data line side source / drain region 71d and the second data line side source / drain region 72d will be described later. The data line 5 shown in FIG. 3 extends along the Y direction. The data line 5 is electrically connected to a data line driving circuit 101. The data line 5 supplies an image signal supplied from the data line driving circuit 101 to the pixel P.

[0045] The pixel electrode 15 is electrically connected to the first pixel electrode side source / drain region 71p of the N-channel transistor 1a or the second pixel electrode side source / drain region 72p of the P-channel transistor 1b. The first pixel electrode side source / drain region 71p and the second pixel electrode side source / drain region 72p will be described later. When the transistor 1 is turned on for a certain period by inputting a scanning signal, an image signal is applied to the pixel electrode 15 at a predetermined timing. The image signal is written at a predetermined level into the liquid crystal layer 50 via the pixel electrode 15. The image signal is held for a certain period between the pixel electrode 15 and the common electrode 22 sandwiching the liquid crystal layer 50. The orientation state of the liquid crystal 50a changes depending on the potential applied in accordance with the image signal.

[0046] The capacitor 16 has two electrodes. One electrode of the capacitor 16 is electrically connected to a capacitor line 7, which will be described later. The other electrode of the capacitor 16 is electrically connected to the pixel electrode 15. The capacitor 16 prevents the image signal held in the pixel electrode 15 from leaking.

[0047] A plurality of transmission gates 102 are provided between the data line driving circuit 101 and the data lines 5. The plurality of transmission gates 102 are provided corresponding to the respective data lines 5. The transmission gates 102 are, for example, configured with complementary transistors. The transmission gates 102 function as switches. The transmission gates 102 are, for example, configured with CMOS (Complementary Metal-Oxide-Semiconductor). By providing the transmission gates 102, potential fluctuations caused by parasitic capacitance occurring in the data lines 5 are reduced. The transmission gates 102 correspond to an example of complementary sampling transistors.

[0048] The liquid crystal device 100 preferably includes a transmission gate 102 electrically connected to the data line 5 . By providing the transmission gate 102, the potential fluctuation caused by the parasitic capacitance occurring in the data line 5 is reduced.

[0049] An inverter circuit 104 is provided between the scanning line driving circuit 103 and the scanning line 3. The inverter circuit 104 inverts the gate signal. For example, the inverter circuit 104 inverts a gate signal generated for a pixel P having an N-channel transistor 1a into a gate signal for a pixel P having a P-channel transistor 1b.

[0050] First embodiment In the first embodiment, the configuration of a first element substrate 10a is shown. The first element substrate 10a is an example of the element substrate 10. In the first element substrate 10a, pixel relay electrodes 81 and data line relay electrodes 82 are arranged between N-channel scanning lines 31 and P-channel scanning lines 32.

[0051] Fig. 4 shows a schematic configuration of the first element substrate 10a. Fig. 4 shows a part of the first element substrate 10a in the display region A1 in a plan view from the +Z direction. Fig. 4 shows the scanning lines 3, the data lines 5, and the relay electrodes 80. A first semiconductor layer 71 and a second semiconductor layer 72 are disposed at positions on the data lines 5 in the -Z direction. Fig. 4 also shows the lines BB and CC. The lines BB and CC are virtual lines.

[0052] The relay electrode 80 is electrically connected to the pixel relay electrode 81 and the pixel electrode 15. A drain potential is applied to the relay electrode 80. The relay electrode 80 is formed in the same layer as the plurality of data lines 5.

[0053] Fig. 5 shows a schematic configuration of the first element substrate 10a. Fig. 5 shows a part of the first element substrate 10a in the display region A1 in a plan view from a position in the +Z direction of the N-channel scanning lines 31. Fig. 5 shows a plurality of first semiconductor layers 71, a plurality of second semiconductor layers 72, a plurality of gate electrodes 73, a plurality of N-channel scanning lines 31, and a plurality of first gate connection contact holes 84.

[0054] The first semiconductor layer 71 includes an N-channel transistor 1a. The N-channel transistor 1a has an LDD (Lightly Doped Drain) structure. The first semiconductor layer 71 has a first pixel electrode side source / drain region 71p, a first pixel electrode side LDD region 71a, a first channel region 71c, a first data line side LDD region 71b, and a first data line side source / drain region 71d. The first semiconductor layer 71 is made of polysilicon, for example. Regions other than the first channel region 71c are doped with predetermined impurities that improve conductivity.

[0055] The first pixel electrode side source / drain region 71p and the first data line side source / drain region 71d are, for example, made of an N-type silicon semiconductor. The first channel region 71c is made of a P-type silicon semiconductor. The first pixel electrode side source / drain region 71p and the first data line side source / drain region 71d correspond to an example of a first source / drain region.

[0056] The first pixel electrode side LDD region 71a is disposed between the first pixel electrode side source / drain region 71p and the first channel region 71c. The impurity concentration in the first pixel electrode side LDD region 71a is lower than the impurity concentration in the first pixel electrode side source / drain region 71p and the impurity concentration in the first data line side source / drain region 71d. The first pixel electrode side LDD region 71a corresponds to an example of an LDD region.

[0057] The first data line side LDD region 71b is disposed between the first data line side source / drain region 71d and the first channel region 71c. The impurity concentration in the first data line side LDD region 71b is lower than the impurity concentration in the first pixel electrode side source / drain region 71p and the impurity concentration in the first data line side source / drain region 71d. The first data line side LDD region 71b corresponds to an example of an LDD region.

[0058] The second semiconductor layer 72 includes a P-channel transistor 1b. The P-channel transistor 1b has an LDD (Lightly Doped Drain) structure. The second semiconductor layer 72 has a second pixel electrode side source / drain region 72p, a second pixel electrode side LDD region 72a, a second channel region 72c, a second data line side LDD region 72b, and a second data line side source / drain region 72d. The second semiconductor layer 72 is made of polysilicon, for example. Regions other than the second channel region 72c are doped with predetermined impurities to improve conductivity.

[0059] The second pixel electrode side source / drain region 72p and the second data line side source / drain region 72d are, for example, made of a P-type silicon semiconductor. The second channel region 72c is made of an N-type silicon semiconductor. The second pixel electrode side source / drain region 72p and the second data line side source / drain region 72d correspond to an example of a second source / drain region.

[0060] The second pixel electrode side LDD region 72a is disposed between the second pixel electrode side source / drain region 72p and the second channel region 72c. The impurity concentration in the second pixel electrode side LDD region 72a is lower than the impurity concentration in the second pixel electrode side source / drain region 72p and the impurity concentration in the second data line side source / drain region 72d. The second pixel electrode side LDD region 72a corresponds to an example of an LDD region.

[0061] The second data line side LDD region 72b is disposed between the second data line side source / drain region 72d and the second channel region 72c. The impurity concentration in the second data line side LDD region 72b is lower than the impurity concentration in the second pixel electrode side source / drain region 72p and the impurity concentration in the second data line side source / drain region 72d. The second data line side LDD region 72b corresponds to an example of an LDD region.

[0062] The multiple gate electrodes 73 include a first gate electrode 73a and a second gate electrode 73b. The first gate electrode 73a is disposed on the first semiconductor layer 71 with a gate insulating layer 99 interposed therebetween. The first gate electrode 73a corresponds to an example of a first gate electrode. The first gate electrode 73a is disposed at a position overlapping with the first channel region 71c in a planar view from the +Z direction. The second gate electrode 73b is disposed on the second semiconductor layer 72 with the gate insulating layer 99 interposed therebetween. The second gate electrode 73b corresponds to an example of a second gate electrode. The second gate electrode 73b is disposed at a position overlapping with the second channel region 72c in a planar view from the +Z direction.

[0063] The gate electrode 73 is formed by, for example, doping polysilicon with a predetermined impurity that improves conductivity. The gate electrode 73 may be formed of a conductive material such as a metal, a metal silicide, or a metal compound.

[0064] The N-channel scanning line 31 is disposed at a position intersecting the first semiconductor layer 71 and the second semiconductor layer 72. The N-channel scanning line 31 is disposed at a position in the +Z direction of the first semiconductor layer 71 and the second semiconductor layer 72. The N-channel scanning line 31 is formed of a conductive material having light-blocking properties. Here, the light-blocking properties indicate light-blocking properties against visible light, and it is preferable that the transmittance of visible light is less than 50%. The conductive material is made of metals such as tungsten, titanium, chromium, iron, and aluminum, metal nitrides, metal silicides, etc. The N-channel scanning line 31 has a main body portion 31a and a protruding portion 31b.

[0065] The main body 31a extends in the +X direction and is connected to the protrusion 31b. The +X direction corresponds to an example of a first direction. The protrusion 31b is connected to the main body 31a and extends in the -Y direction. The -Y direction corresponds to an example of a second direction. The protrusion 31b is arranged along the first semiconductor layer 71 or the second semiconductor layer 72. The protrusion 31b arranged along the first semiconductor layer 71 extends along the first pixel electrode side LDD region 71a and the first channel region 71c. The protrusion 31b arranged along the second semiconductor layer 72 extends along the second pixel electrode side LDD region 72a and the second channel region 72c. The provision of the protrusion 31b improves light blocking properties.

[0066] The first gate connection contact hole 84 electrically connects the first gate electrode 73a and the N-channel scanning line 31. The first gate connection contact hole 84 includes a first contact plug 84p. The first contact plug 84p is made of tungsten, for example.

[0067] Fig. 6 shows a schematic configuration of the first element substrate 10a. Fig. 6 shows a part of the first element substrate 10a in the display region A1 in a plan view from a position in the +Z direction of the P-channel scanning lines 32. Fig. 6 shows a plurality of P-channel scanning lines 32, a plurality of first semiconductor layers 71, a plurality of second semiconductor layers 72, a plurality of second gate connection contact holes 85, a plurality of pixel relay electrodes 81, and a plurality of data line relay electrodes 82.

[0068] The P-channel scanning line 32 is disposed at a position where it intersects with the first semiconductor layer 71 and the second semiconductor layer 72. The P-channel scanning line 32 is disposed at a position in the +Z direction of the N-channel scanning line 31. The P-channel scanning line 32 is formed of a conductive material having light-blocking properties. The conductive material is composed of metals such as tungsten, titanium, chromium, iron, and aluminum, metal nitrides, metal silicides, etc.

[0069] The second gate connection contact hole 85 electrically connects the second gate electrode 73b and the P-channel scanning line 32. The second gate connection contact hole 85 includes a second contact plug 85p. The second contact plug 85p is made of tungsten, for example.

[0070] The multiple pixel relay electrodes 81 include a first pixel relay electrode 81a and a second pixel relay electrode 81b. The first pixel relay electrode 81a is electrically connected to the first pixel electrode side source / drain region 71p of the first semiconductor layer 71. The first pixel relay electrode 81a is disposed in a position in the +Z direction of the first pixel electrode side source / drain region 71p. The first pixel relay electrode 81a corresponds to an example of a first source / drain electrode. The second pixel relay electrode 81b is electrically connected to the second pixel electrode side source / drain region 72p of the second semiconductor layer 72. The second pixel relay electrode 81b is disposed in a position in the +Z direction of the second pixel electrode side source / drain region 72p. The second pixel relay electrode 81b corresponds to an example of a second source / drain electrode. The pixel relay electrode 81 shields the first semiconductor layer 71 and the second semiconductor layer 72 from light.

[0071] The multiple data line relay electrodes 82 include a first data line relay electrode 82a and a second data line relay electrode 82b. The first data line relay electrode 82a is electrically connected to the first data line side source / drain region 71d of the first semiconductor layer 71. The first data line relay electrode 82a is arranged in a position in the +Z direction of the first data line side source / drain region 71d. The first data line relay electrode 82a corresponds to an example of a first source / drain electrode. The second data line relay electrode 82b is electrically connected to the second data line side source / drain region 72d of the second semiconductor layer 72. The second data line relay electrode 82b is arranged in a position in the +Z direction of the second data line side source / drain region 72d. The second data line relay electrode 82b corresponds to an example of a second source / drain electrode. The data line relay electrode 82 shields the first semiconductor layer 71 and the second semiconductor layer 72 from light.

[0072] FIG. 7 shows a schematic configuration of the first element substrate 10a. FIG. 7 shows a YZ cross section including line BB shown in FIG. 4. FIG. 7 shows a portion of the first element substrate 10a in the display region A1 in a cross section viewed from the +X direction. FIG. 7 shows a first semiconductor layer 71, a second semiconductor layer 72, a first gate electrode 73a, a second gate electrode 73b, a first light-shielding layer 74, a first relay layer 75, a second relay layer 76, a second light-shielding layer 77, a conductive layer 78, a first gate connection contact hole 84, a second gate connection contact hole 85, a first contact hole 86, a second contact hole 87, a data line connection contact hole 88, and an insulating layer group 90. The insulating layer group 90 includes a first interlayer insulating layer 91, a second interlayer insulating layer 92, a third interlayer insulating layer 93, a fourth interlayer insulating layer 94, a fifth interlayer insulating layer 95, and a gate insulating layer 99.

[0073] The first interlayer insulating layer 91 has light-transmitting and insulating properties. The first interlayer insulating layer 91 is formed of an inorganic material such as silicon oxide, for example. The first interlayer insulating layer 91 is formed on the element substrate base 11.

[0074] The first semiconductor layer 71 and the second semiconductor layer 72 are provided on a first interlayer insulating layer 91. In the first element substrate 10a shown in Fig. 7, the second semiconductor layer 72 and the first semiconductor layer 71 are alternately arranged in this order from the -Y direction. The first semiconductor layer 71 and the second semiconductor layer 72 are arranged adjacent to each other.

[0075] The second interlayer insulating layer 92 is provided on the first semiconductor layer 71 and the second semiconductor layer 72. The second interlayer insulating layer 92 is light-transmitting and insulating. The second interlayer insulating layer 92 is formed of an inorganic material such as silicon oxide, for example.

[0076] The first gate electrode 73a is provided on the first channel region 71c in the first semiconductor layer 71. The first gate electrode 73a is provided on the first semiconductor layer 71 with a gate insulating layer 99 interposed therebetween.

[0077] The second gate electrode 73b is provided on the second channel region 72c in the second semiconductor layer 72. The second gate electrode 73b is provided on the second semiconductor layer 72 with a gate insulating layer 99 interposed therebetween.

[0078] The gate insulating layer 99 has insulating properties and is made of silicon oxide formed by, for example, thermal oxidation, CVD (Chemical Vapor Deposition), or the like.

[0079] The first light-shielding layer 74 is disposed on the second interlayer insulating layer 92. The first light-shielding layer 74 is disposed along the Z direction between the first semiconductor layer 71 and the first pixel relay electrode 81a and the first data line relay electrode 82a. The first light-shielding layer 74 is disposed along the Z direction between the second semiconductor layer 72 and the second pixel relay electrode 81b and the second data line relay electrode 82b. The first light-shielding layer 74 is a thin film extending along the X direction. The first light-shielding layer 74 corresponds to an example of a first layer. The first light-shielding layer 74 includes an N-channel scanning line 31. The N-channel scanning line 31 is disposed on the first light-shielding layer 74 and is electrically connected to the first gate electrode 73a.

[0080] The first gate connection contact hole 84 penetrates the second interlayer insulating layer 92. The first gate connection contact hole 84 electrically connects the first gate electrode 73a and the N-channel scanning line 31 to each other, thereby establishing conduction between them.

[0081] The third interlayer insulating layer 93 is provided on the first light-shielding layer 74. The third interlayer insulating layer 93 is provided between the pixel relay electrode 81 and the data line relay electrode 82 and the N-channel scanning line 31. The third interlayer insulating layer 93 corresponds to an example of the second insulating layer. The third interlayer insulating layer 93 has light-transmitting and insulating properties. The third interlayer insulating layer 93 is formed of an inorganic material, such as silicon oxide, for example.

[0082] A plurality of first relay layers 75 are disposed on the third interlayer insulating layer 93. The first relay layers 75 are formed of a light-blocking conductive material. Each of the plurality of first relay layers 75 includes either a first pixel relay electrode 81a or a second pixel relay electrode 81b. The first pixel relay electrode 81a is electrically connected to the first pixel electrode side source / drain region 71p of the first semiconductor layer 71. The second pixel relay electrode 81b is electrically connected to the second pixel electrode side source / drain region 72p of the second semiconductor layer 72.

[0083] The first contact hole 86 penetrates the second interlayer insulating layer 92 and the third interlayer insulating layer 93. The first contact hole 86 is electrically connected to either the first pixel electrode side source / drain region 71p of the first semiconductor layer 71 or the second pixel electrode side source / drain region 72p of the second semiconductor layer 72, thereby establishing conduction therebetween.

[0084] A plurality of second relay layers 76 are disposed on the third interlayer insulating layer 93. The second relay layers 76 are formed of a light-blocking conductive material. Each of the plurality of second relay layers 76 includes either a first data line relay electrode 82a or a second data line relay electrode 82b. The first data line relay electrode 82a is electrically connected to the first data line side source / drain region 71d of the first semiconductor layer 71. The second data line relay electrode 82b is electrically connected to the second data line side source / drain region 72d of the second semiconductor layer 72.

[0085] The second contact holes 87 penetrate the second interlayer insulating layer 92 and the third interlayer insulating layer 93. The multiple second contact holes 87 are each electrically connected to either the first data line side source / drain region 71 d of the first semiconductor layer 71 or the second data line side source / drain region 72 d of the second semiconductor layer 72, thereby establishing conduction therebetween.

[0086] The fourth interlayer insulating layer 94 is provided on the first relay layer 75 including the pixel relay electrode 81 and the second relay layer 76 including the data line relay electrode 82. The fourth interlayer insulating layer 94 is provided between the first pixel relay electrode 81a and the second pixel relay electrode 81b and the P-channel scanning line 32. The fourth interlayer insulating layer 94 is provided between the first data line relay electrode 82a and the second data line relay electrode 82b and the P-channel scanning line 32. The fourth interlayer insulating layer 94 corresponds to an example of a first insulating layer. The fourth interlayer insulating layer 94 is transparent and insulating. The fourth interlayer insulating layer 94 is formed of an inorganic material such as silicon oxide, for example. The fourth interlayer insulating layer 94 may be made of the same material as the third interlayer insulating layer 93.

[0087] The second light-shielding layer 77 is disposed on the fourth interlayer insulating layer 94. The second light-shielding layer 77 is disposed along the Z direction between the data line 5 and the pixel relay electrode 81 and the data line relay electrode 82. The second light-shielding layer 77 is disposed on the side of the first pixel relay electrode 81a and the first data line relay electrode 82a opposite to the first semiconductor layer 71. The second light-shielding layer 77 is disposed on the side of the second pixel relay electrode 81b and the second data line relay electrode 82b opposite to the second semiconductor layer 72. The second light-shielding layer 77 is a thin film extending along the X direction. The second light-shielding layer 77 corresponds to an example of a second layer. The second light-shielding layer 77 includes a P-channel scanning line 32. The P-channel scanning line 32 is disposed on the second light-shielding layer 77 and is electrically connected to the second gate electrode 73b.

[0088] The second gate connection contact hole 85 penetrates the second interlayer insulating layer 92, the third interlayer insulating layer 93, and the fourth interlayer insulating layer 94. The second gate connection contact hole 85 electrically connects the second gate electrode 73b and the P-channel scanning line 32 to establish conduction therebetween.

[0089] The fifth interlayer insulating layer 95 is provided on the fourth interlayer insulating layer 94 and the second light-shielding layer 77. The fifth interlayer insulating layer 95 is light-transmitting and insulating. The fifth interlayer insulating layer 95 is formed of an inorganic material such as silicon oxide, for example.

[0090] The conductive layer 78 is disposed on the fifth interlayer insulating layer 95. The conductive layer 78 shown in FIG. 7 is a thin film extending along the Y direction. The conductive layer 78 is formed of a light-shielding conductive material. The conductive material forming the conductive layer 78 is composed of metals such as tungsten, titanium, chromium, iron, and aluminum, metal nitrides, metal silicides, etc. The conductive layer 78 includes a data line 5. The data line 5 is disposed on the conductive layer 78 and is electrically connected to the first data line side source / drain region 71d and the second data line side source / drain region 72d via a data line relay electrode 82.

[0091] The data line connection contact hole 88 penetrates the fourth interlayer insulating layer 94 and the fifth interlayer insulating layer 95. The data line connection contact hole 88 electrically connects the data line 5 and the data line relay electrode 82, thereby establishing conduction between them.

[0092] FIG. 8 shows a schematic configuration of the first element substrate 10a. FIG. 8 shows an XZ cross section including line CC shown in FIG. 4. FIG. 8 shows a portion of the first element substrate 10a in the display region A1 in a cross section viewed from the -Y direction. FIG. 8 shows a first semiconductor layer 71, a second semiconductor layer 72, a gate electrode 73, a first light-shielding layer 74, a first relay layer 75, a second light-shielding layer 77, a conductive layer 78, a relay electrode 80, a pixel relay electrode 81, a first gate connection contact hole 84, a second gate connection contact hole 85, and an insulating layer group 90. The insulating layer group 90 includes a first interlayer insulating layer 91, a second interlayer insulating layer 92, a third interlayer insulating layer 93, a fourth interlayer insulating layer 94, a fifth interlayer insulating layer 95, and a gate insulating layer 99.

[0093] FIG. 8 shows the first gate connection contact hole 84 and the second gate connection contact hole 85 to clearly show the positional relationship, but the first gate connection contact hole 84 and the second gate connection contact hole 85 are not arranged on the same cross section.

[0094] 8 schematically shows a first parasitic capacitance PC1, a second parasitic capacitance PC2, a third parasitic capacitance PC3, and a fourth parasitic capacitance PC4. The first parasitic capacitance PC1 occurs between the N-channel scanning line 31 and the first pixel relay electrode 81a. The second parasitic capacitance PC2 occurs between the P-channel scanning line 32 and the first pixel relay electrode 81a. The third parasitic capacitance PC3 occurs between the N-channel scanning line 31 and the second pixel relay electrode 81b. The fourth parasitic capacitance PC4 occurs between the P-channel scanning line 32 and the second pixel relay electrode 81b.

[0095] The first pixel relay electrode 81a and the second pixel relay electrode 81b are arranged between the N-channel scanning line 31 and the P-channel scanning line 32 in the Z direction. A first gate potential is applied to the N-channel scanning line 31. A second gate potential, which is opposite in phase to the first gate potential, is applied to the P-channel scanning line 32. The first pixel relay electrode 81a and the second pixel relay electrode 81b are supplied with the potential applied to the pixel electrode 15. The first gate potential and the second gate potential cancel the influence of the first parasitic capacitance PC1 and the second parasitic capacitance PC2 on the potential applied to the first pixel relay electrode 81a. Similarly, the first gate potential and the second gate potential cancel the influence of the third parasitic capacitance PC3 and the fourth parasitic capacitance PC4 on the potential applied to the second pixel relay electrode 81b. Fluctuations in the potential applied to the pixel electrode 15 due to parasitic capacitances are reduced. This makes it possible to prevent display defects in the liquid crystal device 100 from occurring due to potential fluctuations.

[0096] FIG. 8 shows a first distance D1, a second distance D2, a third distance D3, and a fourth distance D4. The first distance D1 is the distance between the N-channel scanning line 31 and the first pixel relay electrode 81a along the Z direction. The second distance D2 is the distance between the P-channel scanning line 32 and the first pixel relay electrode 81a along the Z direction. The third distance D3 is the distance between the N-channel scanning line 31 and the second pixel relay electrode 81b along the Z direction. The fourth distance D4 is the distance between the P-channel scanning line 32 and the second pixel relay electrode 81b along the Z direction. The first distance D1 and the third distance D3 are the same distance. The second distance D2 and the fourth distance D4 are the same distance. The first distance D1, the second distance D2, the third distance D3, and the fourth distance D4 are set appropriately.

[0097] The liquid crystal device 100 includes an N-channel transistor 1a, a P-channel transistor 1b, a first pixel relay electrode 81a electrically connected to the first pixel electrode side source / drain region 71p of the N-channel transistor 1a, a second pixel relay electrode 81b electrically connected to the second pixel electrode side source / drain region 72p of the P-channel transistor 1b, an N-channel scanning line 31 disposed on a first light-shielding layer 74 between the N-channel transistor 1a and the first pixel relay electrode 81a and electrically connected to the first gate electrode 73a of the N-channel transistor 1a, and a P-channel scanning line 32 disposed on a second light-shielding layer 77 on the opposite side of the second pixel relay electrode 81b from the P-channel transistor 1b side and electrically connected to the second gate electrode 73b of the P-channel transistor 1b. By disposing the pixel relay electrode 81 between the N-channel scanning line 31 and the P-channel scanning line 32, fluctuations in the potential applied to the pixel electrode 15 due to parasitic capacitance are reduced, making it possible to prevent display defects in the liquid crystal device 100 from occurring due to potential fluctuations.

[0098] In plan view from the +Z direction, the N-channel transistor 1a and the P-channel transistor 1b are preferably disposed adjacent to each other. The influence of the parasitic capacitance occurring within the element substrate 10 is further reduced.

[0099] The liquid crystal device 100 preferably includes a fourth interlayer insulating layer 94 arranged in a layer between the first pixel relay electrode 81a and the second pixel relay electrode 81b and the P-channel scanning line 32, and a third interlayer insulating layer 93 arranged in a layer between the first pixel relay electrode 81a and the second pixel relay electrode 81b and the N-channel scanning line 31 and made of the same material as the fourth interlayer insulating layer 94. The influence of the parasitic capacitance occurring within the element substrate 10 is further reduced.

[0100] It is preferable that the first pixel electrode side LDD region 71a is provided between the first pixel electrode side source / drain region 71p and the first channel region 71c of the N-channel transistor 1a, and the N-channel scanning line 31 has a main body 31a extending in the +X direction and a protrusion 31b extending from the main body 31a along the first pixel electrode side LDD region 71a in the -Y direction intersecting the +X direction. The provision of the protrusion 31b improves the light blocking effect on the N-channel transistor 1a.

[0101] 9 to 16 show the manufacturing process of the first element substrate 10a. 9 to 16 show the manufacturing process from the formation of the transistors 1 to the formation of the data lines 5. 9 to 16 show a part of the first element substrate 10a in the display region A1 in a plan view from the +Z direction.

[0102] 9 shows a state in which a first semiconductor layer 71, a second semiconductor layer 72, a gate electrode 73, and a first gate connection contact hole 84 have been formed. The first semiconductor layer 71 corresponds to the N-channel transistor 1a. The second semiconductor layer 72 corresponds to the P-channel transistor 1b.

[0103] The first semiconductor layer 71 and the second semiconductor layer 72 are formed on a first interlayer insulating layer 91. The first semiconductor layer 71 and the second semiconductor layer 72 shown in Fig. 9 extend along the Y direction. The first semiconductor layer 71 and the second semiconductor layer 72 shown in Fig. 9 are alternately arranged along the X direction.

[0104] The first gate electrode 73a is formed on the first semiconductor layer 71 with a gate insulating layer 99 interposed therebetween. The second gate electrode 73b is formed on the second semiconductor layer 72 with the gate insulating layer 99 interposed therebetween. After the first gate electrode 73a is formed, a second interlayer insulating layer 92 is formed on the first semiconductor layer 71 and the second semiconductor layer 72.

[0105] A first gate connection contact hole 84 is formed on the first gate electrode 73a. The first gate connection contact hole 84 is formed in the second interlayer insulating layer 92. The first gate connection contact hole 84 is formed to be electrically connectable to the N-channel scanning line 31.

[0106] 10 shows a state in which the first light-shielding layer 74 has been formed. The first light-shielding layer 74 is formed on the second interlayer insulating layer 92. The first light-shielding layer 74 extends along the X direction. The first light-shielding layer 74 includes an N-channel scanning line 31. The N-channel scanning line 31 has a main body portion 31a and a protrusion portion 31b.

[0107] The N-channel scanning line 31 is formed at a position overlapping the first gate electrode 73a and the second gate electrode 73b. The N-channel scanning line 31 is formed at a position where a part of the first gate electrode 73a and a part of the second gate electrode 73b are exposed in a plan view from the +Z direction. The N-channel scanning line 31 is formed on the first gate connection contact hole 84. After the N-channel scanning line 31 is formed, a third interlayer insulating layer 93 is formed on the N-channel scanning line 31.

[0108] 11 shows a state in which the first contact hole 86 and the second contact hole 87 have been formed. The first contact hole 86 and the second contact hole 87 are formed in the third interlayer insulating layer 93.

[0109] The first contact holes 86 are formed on the first pixel electrode side source / drain regions 71 p of the first semiconductor layer 71 and on the second pixel electrode side source / drain regions 72 p of the second semiconductor layer 72 .

[0110] The second contact holes 87 are formed on the first data line side source / drain regions 71 d of the first semiconductor layer 71 and on the second data line side source / drain regions 72 d of the second semiconductor layer 72 .

[0111] 12 shows the state where the first relay layer 75 and the second relay layer 76 have been formed. The first relay layer 75 and the second relay layer 76 are formed on the third interlayer insulating layer 93. The first relay layer 75 and the second relay layer 76 are formed in a state where a portion of the gate electrode 73 is exposed in a plan view from the +Z direction. The first relay layer 75 includes a plurality of pixel relay electrodes 81. The second relay layer 76 includes a plurality of data line relay electrodes 82.

[0112] Each of the plurality of pixel relay electrodes 81 includes either a first pixel relay electrode 81a or a second pixel relay electrode 81b. The first pixel relay electrode 81a is formed on the first pixel electrode side source / drain region 71p of the first semiconductor layer 71 and on the N-channel scanning line 31. The first pixel relay electrode 81a is formed on the protruding portion 31b and main body portion 31a of the N-channel scanning line 31. The second pixel relay electrode 81b is formed on the second pixel electrode side source / drain region 72p of the second semiconductor layer 72 and on the N-channel scanning line 31. The second pixel relay electrode 81b is formed on the protruding portion 31b and main body portion 31a of the N-channel scanning line 31.

[0113] Each of the multiple data line relay electrodes 82 includes either a first data line relay electrode 82a or a second data line relay electrode 82b. The first data line relay electrode 82a is formed on the first data line side source / drain region 71d of the first semiconductor layer 71. The second data line relay electrode 82b is formed on the second data line side source / drain region 72d of the second semiconductor layer 72.

[0114] 12 shows a first overlap region R1 and a third overlap region R3. The first overlap region R1 is a region where the N-channel scanning line 31 and the first pixel relay electrode 81a overlap in a plan view from the +Z direction. The first overlap region R1 corresponds to an example of a first region. The third overlap region R3 is a region where the N-channel scanning line 31 and the second pixel relay electrode 81b overlap in a plan view from the +Z direction. The third overlap region R3 corresponds to an example of a third region.

[0115] The first overlap region R1 includes a part of the main body 31a of the N-channel scanning line 31 and a protruding portion 31b extending along the first semiconductor layer 71. The third overlap region R3 includes a part of the main body 31a of the N-channel scanning line 31 and a protruding portion 31b extending along the second semiconductor layer 72.

[0116] 13 shows a state in which the second gate connection contact hole 85 has been formed. After the first relay layer 75 and the second relay layer 76 are formed, a fourth interlayer insulating layer 94 is formed on the first relay layer 75 and the second relay layer 76. The second gate connection contact hole 85 is formed in the second interlayer insulating layer 92, the third interlayer insulating layer 93, and the fourth interlayer insulating layer 94.

[0117] The second gate connection contact hole 85 is formed to be electrically connectable to the second gate electrode 73b on the second semiconductor layer 72. The second gate connection contact hole 85 is formed at a position further in the +Y direction than the first gate connection contact hole 84.

[0118] 14 shows a state in which the second light-shielding layer 77 has been formed. The second light-shielding layer 77 is formed on the fourth interlayer insulating layer 94. The second light-shielding layer 77 extends along the X direction. The second light-shielding layer 77 includes the P-channel scanning line 32.

[0119] The P-channel scanning line 32 is formed on the main body 31a of the N-channel scanning line 31 and on the gate electrode 73. The P-channel scanning line 32 is formed on the second gate connection contact hole 85. The P-channel scanning line 32 is formed so as to be electrically connectable to the second gate connection contact hole 85. The P-channel scanning line 32 is electrically connected to the second gate electrode 73b via the second gate connection contact hole 85.

[0120] 14 shows the second overlap region R2 and the fourth overlap region R4. The second overlap region R2 is a region where the P-channel scanning line 32 and the first pixel relay electrode 81a overlap in a plan view from the +Z direction. The second overlap region R2 corresponds to an example of the second region. The fourth overlap region R4 is a region where the P-channel scanning line 32 and the second pixel relay electrode 81b overlap in a plan view from the +Z direction. The fourth overlap region R4 corresponds to an example of the fourth region.

[0121] The second overlap region R2 overlaps with a portion of the first overlap region R1 where the main body 31a of the N-channel scanning line 31 and the first pixel relay electrode 81a overlap. A first area of ​​the first overlap region R1 in plan view from the +Z direction is larger than a second area of ​​the second overlap region R2 in plan view from the +Z direction.

[0122] The fourth overlap region R4 overlaps with a portion of the third overlap region R3 where the main body 31a of the N-channel scanning line 31 and the second pixel relay electrode 81b overlap. A third area of ​​the third overlap region R3 in plan view from the +Z direction is larger than a fourth area of ​​the fourth overlap region R4 in plan view from the +Z direction.

[0123] 12 and 14, when the first area is larger than the second area, the first parasitic capacitance PC1 shown in FIG. 8 is larger than the second parasitic capacitance PC2. If the first parasitic capacitance PC1 is larger than the second parasitic capacitance PC2, the effect of reducing the potential fluctuation occurring in the first pixel relay electrode 81a is reduced. In this case, it is preferable that the first distance D1 shown in FIG. 8 is larger than the second distance D2. By making the first distance D1 larger than the second distance D2, it is possible to prevent the effect of reducing the potential fluctuation occurring in the first pixel relay electrode 81a from being reduced.

[0124] When the third area is larger than the fourth area, the third parasitic capacitance PC3 shown in FIG. 8 is larger than the fourth parasitic capacitance PC4. If the third parasitic capacitance PC3 is larger than the fourth parasitic capacitance PC4, the effect of reducing the potential fluctuation occurring in the second pixel relay electrode 81b is reduced. In this case, it is preferable that the third distance D3 shown in FIG. 8 is larger than the fourth distance D4. By making the third distance D3 larger than the fourth distance D4, it is possible to prevent the effect of reducing the potential fluctuation occurring in the second pixel relay electrode 81b from being reduced.

[0125] It is preferable that a first area of ​​a first overlap region R1 where the first pixel relay electrode 81a and the N-channel scanning line 31 overlap in a planar view is larger than a second area of ​​a second overlap region R2 where the first pixel relay electrode 81a and the P-channel scanning line 32 overlap, a third area of ​​a third overlap region R3 where the second pixel relay electrode 81b and the N-channel scanning line 31 overlap in a planar view is larger than a fourth area of ​​a fourth overlap region R4 where the second pixel relay electrode 81b and the P-channel scanning line 32 overlap, a first distance D1 between the first pixel relay electrode 81a and the N-channel scanning line 31 is larger than a second distance D2 between the first pixel relay electrode 81a and the P-channel scanning line 32, and a third distance D3 between the second pixel relay electrode 81b and the N-channel scanning line 31 is larger than a fourth distance D4 between the second pixel relay electrode 81b and the P-channel scanning line 32. This can prevent the effect of reducing the potential fluctuations occurring in the first pixel relay electrode 81a and the second pixel relay electrode 81b from becoming smaller.

[0126] 15 shows a state in which a plurality of data line connection contact holes 88 and a plurality of relay electrode connection contact holes 89 have been formed. After the P-channel scanning lines 32 have been formed, a fifth interlayer insulating layer 95 is formed on the P-channel scanning lines 32. The data line connection contact holes 88 and relay electrode connection contact holes 89 are formed in the fourth interlayer insulating layer 94 and the fifth interlayer insulating layer 95.

[0127] Each of the plurality of data line connecting contact holes 88 is formed so as to be electrically connectable to either the first data line relay electrode 82a or the second data line relay electrode 82b.

[0128] Each of the plurality of relay electrode connection contact holes 89 is formed so as to be electrically connectable to either the first pixel relay electrode 81a or the second pixel relay electrode 81b.

[0129] 16 shows a state in which the conductive layer 78 and the third relay layer 79 have been formed. The conductive layer 78 and the third relay layer 79 are formed on a fifth interlayer insulating layer 95. The conductive layer 78 extends along the Y direction. The third relay layer 79 is formed in an island shape. The conductive layer 78 includes a data line 5. The third relay layer 79 includes a relay electrode 80.

[0130] The data line 5 is formed on the first semiconductor layer 71 and the second semiconductor layer 72. The data line 5 is formed on the data line connection contact hole 88. The data line 5 is formed so as to be electrically connectable to the data line connection contact hole 88. The data line 5 is electrically connected to the data line relay electrode 82 via the data line connection contact hole 88.

[0131] The relay electrode 80 is formed on the pixel relay electrode 81. The relay electrode 80 is formed on the relay electrode connection contact hole 89. The relay electrode 80 is formed so as to be electrically connectable to the relay electrode connection contact hole 89. The relay electrode 80 is electrically connected to the pixel relay electrode 81 via the relay electrode connection contact hole 89.

[0132] Second embodiment In the second embodiment, the configuration of a second element substrate 10b is shown. The second element substrate 10b is an example of the element substrate 10. In the second element substrate 10b, pixel relay electrodes 81 and data line relay electrodes 82 are arranged between the N-channel scanning lines 31 and the P-channel scanning lines 32. The second element substrate 10b is provided with capacitance lines 7.

[0133] FIG. 17 shows a schematic configuration of the second element substrate 10b. FIG. 17 shows a part of the second element substrate 10b in the display region A1 in a plan view from the +Z direction. FIG. 17 shows the scanning lines 3, the data lines 5, the capacitance lines 7, and the relay electrodes 80. The capacitance lines 7, the first semiconductor layers 71, and the second semiconductor layers 72 are arranged at positions in the -Z direction of the data lines 5. The scanning lines 3 and the relay electrodes 80 shown in FIG. 17 have the same configuration as the scanning lines 3 and the relay electrodes 80 shown in FIG. 4. FIG. 17 also shows the DD lines and the EE lines. The DD lines and the EE lines are virtual lines.

[0134] The data line 5 has a data line main body 5m and a data line protrusion 5p. The data line main body 5m extends along the Y direction. The data line protrusion 5p is provided at a position that does not overlap with the data line main body 5m in a plan view from the +Z direction. The data line protrusion 5p shown in FIG. 17 protrudes from the data line main body 5m in the -X direction, but is not limited to this. The data line protrusion 5p may also protrude from the data line main body 5m in the +X direction.

[0135] The capacitance line 7 is electrically connected to the capacitance element 16 shown in FIG. 3. The capacitance line 7 shown in FIG. 17 extends along the Y direction. The capacitance line 7 may extend along the X direction. A constant potential such as a common electrode potential or a ground potential applied to the common electrode 22 is supplied to the capacitance line 7 via the external connection terminal 105. The capacitance line 7 corresponds to an example of a constant potential wiring.

[0136] Fig. 18 shows a schematic configuration of the second element substrate 10b. Fig. 18 shows a YZ cross section including line DD shown in Fig. 17. Fig. 18 shows a part of the second element substrate 10b in the display region A1 in a cross section viewed from the +X direction. Fig. 18 shows the first semiconductor layer 71, the second semiconductor layer 72, the first gate electrode 73a, the second gate electrode 73b, the first light-shielding layer 74, the first relay layer 75, the second relay layer 76, the second light-shielding layer 77, the conductive layer 78, the capacitive electrode layer 171, the first gate connection contact hole 84, the second gate connection contact hole 85, the first contact hole 86, the second contact hole 87, the data line connection contact hole 88, and the insulating layer group 90.

[0137] FIG. 18 shows the data line connecting contact hole 88 to clearly show the layout relationship, but the first gate connecting contact hole 84 and the data line connecting contact hole 88 are not arranged on the same cross section.

[0138] 18 is the same as the first element substrate 10a shown in Fig. 7 except for the capacitive electrode layer 171, the conductive layer 78, and the insulating layer group 90. The insulating layer group 90 of the second element substrate 10b includes a first interlayer insulating layer 91, a second interlayer insulating layer 92, a third interlayer insulating layer 93, a fourth interlayer insulating layer 94, a sixth interlayer insulating layer 96, a seventh interlayer insulating layer 97, and a gate insulating layer 99. The sixth interlayer insulating layer 96 and the seventh interlayer insulating layer 97 are provided in place of the fifth interlayer insulating layer 95 included in the insulating layer group 90 of the first element substrate 10a.

[0139] The sixth interlayer insulating layer 96 is provided on the fourth interlayer insulating layer 94 and the second light-shielding layer 77. The sixth interlayer insulating layer 96 is light-transmitting and insulating. The sixth interlayer insulating layer 96 is formed of an inorganic material such as silicon oxide, for example.

[0140] The capacitive electrode layer 171 is disposed on the sixth interlayer insulating layer 96. The capacitive electrode layer 171 is provided between the P-channel scanning line 32 and the data line 5 along the Z direction. The capacitive electrode layer 171 shown in FIG. 18 is a thin film extending along the Y direction. The capacitive electrode layer 171 is formed of a light-shielding conductive material. The conductive material forming the capacitive electrode layer 171 includes metals such as tungsten, titanium, chromium, iron, and aluminum, metal nitrides, metal silicides, etc. The capacitive electrode layer 171 includes a capacitive line 7. The capacitive line 7 is disposed on the capacitive electrode layer 171. The capacitive electrode layer 171 corresponds to an example of a fourth layer.

[0141] The capacitance line 7 to which a constant potential is applied is arranged along the Z direction between the P-channel scanning line 32 and the data line 5. By arranging the capacitance line 7 between the P-channel scanning line 32 and the data line 5, the parasitic capacitance occurring between the P-channel scanning line 32 and the data line 5 is reduced. This reduces display defects in the liquid crystal device 100 due to the parasitic capacitance occurring between the P-channel scanning line 32 and the data line 5.

[0142] The seventh interlayer insulating layer 97 is provided on the sixth interlayer insulating layer 96 and the capacitive electrode layer 171. The seventh interlayer insulating layer 97 is light-transmitting and insulating. The seventh interlayer insulating layer 97 is formed of an inorganic material such as silicon oxide, for example.

[0143] The conductive layer 78 is disposed on the seventh interlayer insulating layer 97. The conductive layer 78 is provided on the side of the P-channel scanning line 32 opposite to the pixel relay electrode 81. The conductive layer 78 corresponds to an example of the third layer. The conductive layer 78 shown in FIG. 18 is a thin film extending along the Y direction. The conductive layer 78 is formed of a light-shielding conductive material. The conductive material forming the conductive layer 78 includes metals such as tungsten, titanium, chromium, iron, and aluminum, metal nitrides, metal silicides, etc. The conductive layer 78 includes a data line 5. The data line 5 is disposed on the conductive layer 78 and is electrically connected to either the first data line side source / drain region 71d or the second data line side source / drain region 72d via a data line relay electrode 82.

[0144] The liquid crystal device 100 preferably includes a data line 5 arranged on the conductive layer 78 on the side opposite to the first pixel relay electrode 81a side of the P-channel scanning line 32, and a capacitance line 7 arranged on the capacitance electrode layer 171 between the P-channel scanning line 32 and the data line 5. By providing the capacitance line 7 between the P-channel scanning line 32 and the data line 5, the parasitic capacitance occurring between the P-channel scanning line 32 and the data line 5 is reduced. This reduces display defects in the liquid crystal device 100 due to the parasitic capacitance occurring between the P-channel scanning line 32 and the data line 5.

[0145] Fig. 19 shows a schematic configuration of the second element substrate 10b. Fig. 19 shows an XZ cross section including the EE line shown in Fig. 17. Fig. 19 shows a part of the second element substrate 10b in the display region A1 in a cross section seen from the -Y direction. Fig. 19 shows the first semiconductor layer 71, the second semiconductor layer 72, the gate electrode 73, the first light-shielding layer 74, the first relay layer 75, the second light-shielding layer 77, the capacitance electrode layer 171, the conductive layer 78, the relay electrode 80, the pixel relay electrode 81, the first gate connection contact hole 84, the second gate connection contact hole 85, and the insulating layer group 90.

[0146] FIG. 19 shows the first gate connection contact hole 84 and the second gate connection contact hole 85 to clearly show the positional relationship, but the first gate connection contact hole 84 and the second gate connection contact hole 85 are not arranged on the same cross section.

[0147] 19 is the same as the first element substrate 10a shown in FIG. 8 except for the capacitive electrode layer 171, the conductive layer 78, and the insulating layer group 90. The insulating layer group 90 of the second element substrate 10b includes a first interlayer insulating layer 91, a second interlayer insulating layer 92, a third interlayer insulating layer 93, a fourth interlayer insulating layer 94, a sixth interlayer insulating layer 96, a seventh interlayer insulating layer 97, and a gate insulating layer 99. The sixth interlayer insulating layer 96 and the seventh interlayer insulating layer 97 are provided in place of the fifth interlayer insulating layer 95 included in the insulating layer group 90 of the first element substrate 10a.

[0148] 20 to 25 show the manufacturing process of the second element substrate 10b. Figures 20 to 25 show the manufacturing process from the formation of the pixel relay electrodes 81 and the data line relay electrodes 82 to the formation of the data lines 5. The manufacturing process before the pixel relay electrodes 81 and the data line relay electrodes 82 are formed is the same as the manufacturing process of the first element substrate 10a shown in Figures 9, 10, and 11. Figures 20 to 25 show a part of the second element substrate 10b in the display region A1 in a plan view from the +Z direction.

[0149] 20 shows the state where the first relay layer 75 and the second relay layer 76 have been formed. The first relay layer 75 and the second relay layer 76 are formed on the third interlayer insulating layer 93 after the first contact hole 86 and the second contact hole 87 shown in FIG. 11 have been formed. The first relay layer 75 and the second relay layer 76 are formed in a state where a portion of the gate electrode 73 is exposed in a plan view from the +Z direction. The first relay layer 75 includes a plurality of pixel relay electrodes 81. The second relay layer 76 includes a plurality of data line relay electrodes 82.

[0150] The plurality of pixel relay electrodes 81 include a first pixel relay electrode 81a and a second pixel relay electrode 81b. The first pixel relay electrode 81a is formed on the first pixel electrode side source / drain region 71p of the first semiconductor layer 71 and on the N-channel scanning line 31. The first pixel relay electrode 81a is formed on the protruding portion 31b and main body portion 31a of the N-channel scanning line 31. The second pixel relay electrode 81b is formed on the second pixel electrode side source / drain region 72p of the second semiconductor layer 72 and on the N-channel scanning line 31. The second pixel relay electrode 81b is formed on the protruding portion 31b and main body portion 31a of the N-channel scanning line 31.

[0151] Each of the plurality of pixel relay electrodes 81 includes either a first pixel relay electrode 81a or a second pixel relay electrode 81b. The first pixel relay electrode 81a is formed on the first pixel electrode side source / drain region 71p of the first semiconductor layer 71 and on the N-channel scanning line 31. The first pixel relay electrode 81a is formed on the protruding portion 31b and main body portion 31a of the N-channel scanning line 31. The second pixel relay electrode 81b is formed on the second pixel electrode side source / drain region 72p of the second semiconductor layer 72 and on the N-channel scanning line 31. The second pixel relay electrode 81b is formed on the protruding portion 31b and main body portion 31a of the N-channel scanning line 31.

[0152] The multiple data line relay electrodes 82 include a first data line relay electrode 82a and a second data line relay electrode 82b. The first data line relay electrode 82a is formed on the first data line side source / drain region 71d of the first semiconductor layer 71. The second data line relay electrode 82b is formed on the second data line side source / drain region 72d of the second semiconductor layer 72.

[0153] The first data line relay electrode 82a and the second data line relay electrode 82b have data line relay electrode protrusions 82p. The data line relay electrode protrusions 82p shown in Fig. 20 extend in the -X direction. The data line relay electrode protrusions 82p extend in the same direction as the data line protrusions 5p.

[0154] 21 shows a state in which the second gate connection contact hole 85 has been formed. After the first relay layer 75 and the second relay layer 76 are formed, a fourth interlayer insulating layer 94 is formed on the first relay layer 75 and the second relay layer 76. The second gate connection contact hole 85 is formed in the second interlayer insulating layer 92, the third interlayer insulating layer 93, and the fourth interlayer insulating layer 94.

[0155] The second gate connection contact hole 85 is formed to be electrically connectable to the second gate electrode 73b on the second semiconductor layer 72. The second gate connection contact hole 85 is formed at a position further in the +Y direction than the first gate connection contact hole 84.

[0156] 22 shows a state in which the second light-shielding layer 77 has been formed. The second light-shielding layer 77 is formed on the fourth interlayer insulating layer 94. The second light-shielding layer 77 extends along the X direction. The second light-shielding layer 77 includes the P-channel scanning line 32. After the second light-shielding layer 77 is formed, a sixth interlayer insulating layer 96 is formed on the second light-shielding layer 77 and the fourth interlayer insulating layer 94.

[0157] The P-channel scanning line 32 is formed on the main body 31a of the N-channel scanning line 31 and on the gate electrode 73. The P-channel scanning line 32 is formed on the second gate connection contact hole 85. The P-channel scanning line 32 is formed so as to be electrically connectable to the second gate connection contact hole 85. The P-channel scanning line 32 is electrically connected to the second gate electrode 73b via the second gate connection contact hole 85.

[0158] 23 shows a state in which the capacitive electrode layer 171 has been formed. The capacitive electrode layer 171 is formed on the sixth interlayer insulating layer 96. The capacitive electrode layer 171 extends along the Y direction. The capacitive electrode layer 171 is formed at a position where the data line relay electrode protrusion 82p is exposed in a plan view from the +Z direction. The capacitive electrode layer 171 includes the capacitive line 7.

[0159] 24 shows a state in which a plurality of data line connection contact holes 88 and a plurality of relay electrode connection contact holes 89 have been formed. After the capacitor electrode layer 171 has been formed, a seventh interlayer insulating layer 97 is formed on the sixth interlayer insulating layer 96 and the capacitor electrode layer 171. The data line connection contact holes 88 and the relay electrode connection contact holes 89 are formed in the fourth interlayer insulating layer 94, the sixth interlayer insulating layer 96, and the seventh interlayer insulating layer 97.

[0160] The plurality of data line connection contact holes 88 are each formed so as to be electrically connectable to either the data line relay electrode protrusion 82p of the first data line relay electrode 82a or the data line relay electrode protrusion 82p of the second data line relay electrode 82b.

[0161] Each of the plurality of relay electrode connection contact holes 89 is formed so as to be electrically connectable to either the first pixel relay electrode 81a or the second pixel relay electrode 81b.

[0162] 25 shows a state in which the conductive layer 78 and the third relay layer 79 have been formed. The conductive layer 78 and the third relay layer 79 are formed on the seventh interlayer insulating layer 97. The conductive layer 78 is formed on the capacitive electrode layer 171. The conductive layer 78 extends along the Y direction. The third relay layer 79 is formed in an island shape. The conductive layer 78 includes a data line 5. The third relay layer 79 includes a relay electrode 80.

[0163] The data line 5 is formed on the first semiconductor layer 71 and the second semiconductor layer 72. The data line main body 5m of the data line 5 is formed on the capacitance line 7. The data line protrusion 5p of the data line 5 is formed on either the data line relay electrode protrusion 82p of the first data line relay electrode 82a or the data line relay electrode protrusion 82p of the second data line relay electrode 82b. The data line protrusion 5p of the data line 5 is formed so as to be electrically connectable to the data line connecting contact hole 88. The data line 5 is electrically connected to the data line relay electrode 82 via the data line connecting contact hole 88.

[0164] The relay electrode 80 is formed on the pixel relay electrode 81. The relay electrode 80 is formed on the relay electrode connection contact hole 89. The relay electrode 80 is formed so as to be electrically connectable to the relay electrode connection contact hole 89. The relay electrode 80 is electrically connected to the pixel relay electrode 81 via the relay electrode connection contact hole 89.

[0165] The first element substrate 10a shown in the first embodiment and the second element substrate 10b shown in the second embodiment include the N-channel scanning lines 31 in the first light-shielding layer 74 and the P-channel scanning lines 32 in the second light-shielding layer 77, but are not limited to this. The element substrate 10 may also have a configuration in which the first light-shielding layer 74 includes the P-channel scanning lines 32 and the second light-shielding layer 77 includes the N-channel scanning lines 31.

[0166] In the first and second embodiments, the suppression of the fluctuation in the potential to the pixel relay electrode 81 by the gate signal applied to the N-channel scanning line 31 and the gate signal applied to the P-channel scanning line 32 is shown, but the present invention is not limited to this. The gate signal applied to the N-channel scanning line 31 and the gate signal applied to the P-channel scanning line 32 can have the effect of suppressing the fluctuation in the potential at the data line relay electrode 82.

[0167] 26 shows a schematic configuration of a projection display device 1000. The projection display device 1000 corresponds to an example of an electronic device. As an example, the projection display device 1000 is a three-panel projector equipped with three liquid crystal devices 100. The projection display device 1000 includes an illumination device 1001, an illumination optical system 1002, a projection optical system 1003, and a control unit 1004.

[0168] The illumination device 1001 is a light source that emits light to the illumination optical system 1002. The illumination device 1001 has a lamp light source such as a halogen lamp, a xenon lamp, or an ultra-high pressure mercury lamp. The illumination device 1001 may also have a solid-state light source such as an LED (Light Emitting Diode) or a laser light source.

[0169] The illumination optical system 1002 separates the light emitted from the illumination device 1001 into red light RL, green light GL, and blue light BL. The illumination optical system 1002 supplies the red light RL, green light GL, and blue light BL to the liquid crystal devices 100 provided corresponding to each color light.

[0170] The liquid crystal device 100 modulates light supplied from the illumination optical system 1002. The liquid crystal device 100 includes either a liquid crystal device 100 having a first element substrate 10a or a liquid crystal device 100 having a second element substrate 10b. Each of the three liquid crystal devices 100 functions as a light modulation device that modulates one of the separated lights of red light RL, green light GL, and blue light BL in accordance with a display image. A first polarizing plate 210 is disposed on the light incident side of each liquid crystal device 100. A second polarizing plate 220 is disposed on the light exit side of each liquid crystal device 100. The first polarizing plate 210 and the second polarizing plate 220 disposed in the liquid crystal device 100 are disposed in a crossed Nicol configuration in which the transmission axes of the respective polarizing plates for transmitting light are orthogonal to each other. The liquid crystal device 100 emits light to the projection optical system 1003 via the second polarizing plate 220.

[0171] The projection optical system 1003 forms image light by combining the red light RL, green light GL, and blue light BL modulated by the liquid crystal devices 100. The projection optical system 1003 projects the image light onto a screen SC.

[0172] The control unit 1004 is a controller that controls each unit of the projection display device 1000. The control unit 1004 is, for example, a processor having a CPU (Central Processing Unit). The control unit 1004 is composed of one or more processors. The control unit 1004 may have semiconductor memory such as a ROM (Read Only Memory) or a RAM (Random Access Memory). The semiconductor memory functions as a work area for the control unit 1004. The control unit 1004 controls each liquid crystal device 100 to modulate the red light RL, green light GL, and blue light BL supplied from the illumination optical system 1002 in accordance with the display image.

[0173] The projection display device 1000 is not limited to a three-panel projector. The projection display device 1000 may be a single-panel projector, a two-panel projector, or a projector equipped with four or more liquid crystal devices 100. Devices equipped with the liquid crystal device 100 may be smartphones, PDAs (Personal Digital Assistants), cameras, televisions, car navigation systems, personal computers, displays, electronic paper, calculators, videophones, and devices equipped with POS (Point of Sale), printers, scanners, copiers, video players, or touch panels. Devices equipped with the liquid crystal device 100 correspond to examples of electronic devices.

[0174] The projection display device 1000 includes either a liquid crystal device 100 including a first element substrate 10a or a liquid crystal device 100 including a second element substrate 10b. By disposing the pixel relay electrode 81 between the N-channel scanning line 31 and the P-channel scanning line 32, fluctuations in the potential applied to the pixel electrode 15 due to parasitic capacitance are reduced, making it possible to provide a projection-type display device 1000 in which display defects in the liquid crystal device 100 caused by potential fluctuations are suppressed. [Explanation of symbols]

[0175] 1...transistor, 1a...N-channel transistor, 1b...P-channel transistor, 3...scanning line, 5...data line, 5m...data line main body, 5p...data line protrusion, 7...capacitance line, 10...element substrate, 10a...first element substrate, 10b...second element substrate, 11...element substrate base, 15...pixel electrode, 16...capacitance element, 18...first alignment film, 18a...first evaporated film, 18b...second evaporated film, 20...counter substrate, 21...counter substrate base, 22...common electrode, 23...second alignment film, 23a...third evaporated film, 23b...fourth evaporated film, 24...partition portion, 25...insulating layer, 31...N-channel scanning line, 31a...main body portion, 31b...protrusion portion, 32...P-channel scanning line, 50...liquid crystal layer, 50a...liquid crystal, 60...sealing member, 71...first semiconductor layer, 71a...first pixel electrode side LDD region, 71b...first data line side LDD region, 71c...first channel region, 71d...first data line side source / drain region, 71p...first pixel electrode side source / drain region, 72...second semiconductor layer, 72a...second pixel electrode side LDD region, 72b...second data line side LDD region, 72c...second channel region, 72d...second data line side source / drain region, 72p...second pixel electrode side source / drain region region, 73...gate electrode, 73a...first gate electrode, 73b...second gate electrode, 74...first light-shielding layer, 75...first relay layer, 76...second relay layer, 77...second light-shielding layer, 78...conductive layer, 79...third relay layer, 80...relay electrode, 81...pixel relay electrode, 81a...first pixel relay electrode, 81b...second pixel relay electrode, 82...data line relay electrode, 82a...first data line relay electrode, 82b...second data line relay electrode, 82p...data line relay electrode protrusion, 84...first gate connection contact hole, 84p...first contact plug, 85...second gate connection contact hole, 85p...second contact Tact plug, 86...first contact hole, 87...second contact hole, 88...data line connection contact hole, 89...relay electrode connection contact hole, 90...insulating layer group, 91...first interlayer insulating layer, 92...second interlayer insulating layer, 93...third interlayer insulating layer, 94...fourth interlayer insulating layer, 95...fifth interlayer insulating layer, 99...gate insulating layer, 100...liquid crystal device, 101...data line driving circuit, 102...transmission gate, 103...scanning line driving circuit, 104...inverter circuit, 105...external connection terminal, 171...capacitive electrode layer, 210...first polarizer, 220...second polarizer,1000...projection display device, 1001...illumination device, 1002...illumination optical system, 1003...projection optical system, 1004...controller, A1...display area, A2...peripheral area, BL...blue light, D1...first interval, D2...second interval, D3...third interval, D4...fourth interval, GL...green light, L...incident light, P...pixel, PC1...first parasitic capacitance, PC2...second parasitic capacitance, PC3...third parasitic capacitance, PC4...fourth parasitic capacitance, R1...first overlap region, R2...second overlap region, R3...third overlap region, R4...fourth overlap region, RL...red light,

Claims

1. a first transistor of a first conductivity type; a second transistor of a second conductivity type; a first source-drain electrode electrically connected to a first source-drain region of the first transistor; a second source-drain electrode electrically connected to the second source-drain region of the second transistor; a first scanning line disposed in a first layer between the first transistor and the first source / drain electrode, and electrically connected to the first gate electrode of the first transistor; a second scanning line disposed in a second layer on the opposite side of the second source / drain electrode from the second transistor, the second scanning line being electrically connected to the second gate electrode of the second transistor; An electro-optical device comprising:

2. a data line disposed in a third layer on the opposite side of the second scanning line from the first source / drain electrode side; a constant potential wiring disposed in a fourth layer between the second scanning line and the data line; The electro-optical device according to claim 1 ,

3. In a plan view, the first transistor and the second transistor are arranged adjacent to each other. The electro-optical device according to claim 1 .

4. a first area of ​​a first region where the first source-drain electrode and the first scanning line overlap in a plan view is larger than a second area of ​​a second region where the first source-drain electrode and the second scanning line overlap; a third area of ​​a third region where the second source-drain electrode and the first scanning line overlap in a plan view is larger than a fourth area of ​​a fourth region where the second source-drain electrode and the second scanning line overlap; a first distance between the first source / drain electrode and the first scanning line is larger than a second distance between the first source / drain electrode and the second scanning line; a third distance between the second source / drain electrode and the first scanning line is greater than a fourth distance between the second source / drain electrode and the second scanning line; The electro-optical device according to claim 1 .

5. a first insulating layer disposed between the first source / drain electrode and the second scan line; a second insulating layer disposed between the first source-drain electrode and the second source-drain electrode and the first scanning line, the second insulating layer being made of the same material as the first insulating layer; The electro-optical device according to claim 1 ,

6. an LDD region between the first source / drain region and a first channel region of the first transistor; the first scanning line has a main body portion extending in a first direction and a protrusion portion extending from the main body portion along the LDD region in a second direction intersecting the first direction; The electro-optical device according to claim 1 .

7. a complementary sampling transistor electrically connected to the data line; The electro-optical device according to claim 2 .

8. An electronic device comprising the electro-optical device according to claim 1 .

Images