Power supplies, semiconductor devices, electronic equipment

Abstract

Reduce radiated noise. [Solution] The power supply device 1 includes, for example, a pulse generation circuit 10 that generates a first drive pulse Pa1 and a second drive pulse Pb1 in opposite phases to each other, a rectifier and smoothing circuit 20 that rectifies and smooths a third drive pulse Ia and a fourth drive pulse Ib to generate an output voltage Vo, and a first isolation capacitor 31 and a second isolation capacitor 32 that insulate the pulse generation circuit 10 and the rectifier and smoothing circuit 20 while transmitting the first drive pulse Pa1 and the second drive pulse Pb1 generated by the pulse generation circuit 10 to the rectifier and smoothing circuit 20 as a third drive pulse Ia and a fourth drive pulse Ib, respectively.

Description

Technical Field

[0001] The present disclosure relates to a power supply device, a semiconductor device, and an electronic device.

Background Art

[0002] A power supply device that generates an output voltage from an input voltage is mounted in various applications.

[0003] As an example of the related prior art, Patent Document 1 can be cited.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] In a conventional power supply device, there has been room for consideration regarding reduction of radiation noise.

[0006] For example, the power supply device according to the present disclosure includes a pulse generation circuit configured to generate a first drive pulse and a second drive pulse in opposite phases to each other, a rectifying and smoothing circuit configured to rectify and smooth a third drive pulse and a fourth drive pulse to generate an output voltage, and a first insulating capacitor and a second insulating capacitor configured to transmit the first drive pulse and the second drive pulse generated by the pulse generation circuit to the rectifying and smoothing circuit as the third drive pulse and the fourth drive pulse, respectively, while insulating between the pulse generation circuit and the rectifying and smoothing circuit.

Brief Description of the Drawings

[0007] [Figure 1] FIG. 1 is a diagram showing a power supply device according to a first comparative example. [Figure 2] FIG. 2 is a diagram showing a power supply device according to a second comparative example. [Figure 3]Figure 3 shows the drive pulse in the second comparative example. [Figure 4] Figure 4 shows a first embodiment of the power supply unit. [Figure 5] Figure 5 shows the drive pulse in the first embodiment. [Figure 6] Figure 6 shows a second embodiment of the power supply unit. [Figure 7] Figure 7 shows a third embodiment of the power supply unit. [Figure 8] Figure 8 shows a fourth embodiment of the power supply unit. [Figure 9] Figure 9 shows a fifth embodiment of the power supply unit. [Figure 10] Figure 10 shows the drive pulse in the fifth embodiment. [Figure 11] Figure 11 shows a sixth embodiment of the power supply unit. [Figure 12] Figure 12 shows a seventh embodiment of the power supply unit. [Figure 13] Figure 13 shows an example of packaging in the seventh embodiment. [Figure 14] Figure 14 shows an eighth embodiment of the power supply unit. [Figure 15] Figure 15 shows an example of packaging in the eighth embodiment. [Figure 16] Figure 16 shows the ninth embodiment of the power supply unit. [Figure 17] Figure 17 shows an example of packaging in the ninth embodiment. [Figure 18] Figure 18 shows a tenth embodiment of the power supply unit. [Figure 19] Figure 19 shows an example of packaging in the tenth embodiment. [Figure 20] Figure 20 shows the overall configuration of the electronic device. [Figure 21] Figure 21 shows the 11th embodiment of the power supply unit. [Figure 22]Figure 22 shows a modified example of an electronic device.

[0008] [Detailed explanation] <Power supply device (1st comparative example)> Figure 1 shows a power supply device X according to the first comparative example (a configuration to be compared with the embodiment described later). The power supply device X of this comparative example is an isolated DC [direct current] / DC converter that isolates the primary circuit system Xp (GND1 system) and the secondary circuit system Xs (GND2 system) while converting the input voltage VX1 supplied to the primary circuit system Xp into an output voltage VX2 and supplying it to the secondary circuit system Xs. For example, the power supply device X comprises a transformer X1, a transistor X2, a driver X3, a diode X4, and a capacitor X5. The transistor X2 may be, for example, an N-channel type.

[0009] The transformer X1 includes a primary coil X1p and a secondary coil X1s that are magnetically coupled to each other while insulating the primary circuit system Xp and the secondary circuit system Xs. The first end of the primary coil X1p is connected to the input voltage VX1 application terminal. The second end of the primary coil X1p is connected to the drain of transistor X2. The source of transistor X2 is connected to the ground voltage GND1 application terminal. The gate of transistor X2 is connected to the output terminal of driver X3. The input terminal of driver X3 is connected to the drive pulse SX application terminal. The first end of the secondary coil X1s is connected to the anode of diode X4. The cathode of diode X4 and the first end of capacitor X5 are connected to the output voltage VX2 application terminal. The second end of the secondary coil X1s and the second end of capacitor X5 are connected to the ground voltage GND2 application terminal.

[0010] When the transistor X2 is in the on state, a primary current IX flows from the applied end of the input voltage VX1 through the primary winding X1p and the transistor X2 to the applied end of the ground voltage GND1. At this time, electrical energy is stored in the primary winding X1p. Then, when the transistor X2 is switched to the off state, an induced voltage VX3 is generated in the secondary winding X1s magnetically coupled to the primary winding X1p. The output voltage VX2 is generated by rectifying and smoothing the induced voltage VX3.

[0011] In the power supply device X of this comparative example, the output voltage VX2 can be generated from the input voltage VX1 while insulating between the primary circuit system Xp and the secondary circuit system Xs. However, since the flyback type power supply device X requires the transformer X1, it can be costly.

[0012] <Power supply device (Second Comparative Example)> FIG. 2 is a diagram showing a power supply device Y according to the second comparative example (= another configuration compared with the embodiment described later). The power supply device Y of this comparative example is an isolated DC / DC converter that converts the input voltage VY1 supplied to the primary circuit system Yp into the output voltage VY2 and supplies it to the secondary circuit system Ys while insulating between the primary circuit system Yp (GND1 system) and the secondary circuit system Ys (GND2 system). For example, the power supply device Y includes a driver Y1, an isolation capacitor Y2, diodes Y3 and Y4, and an output capacitor Y5.

[0013] The input terminal of the driver Y1 is connected to the applied terminal of the drive pulse SY. The output terminal of the driver Y1 is connected to the first terminal of the isolation capacitor Y2. The second terminal of the isolation capacitor Y2 is connected to the cathode of the diode Y3 and the anode of the diode Y4. The cathode of the diode Y4 and the first terminal of the output capacitor Y5 are connected to the applied terminal of the output voltage VY2. The anode of the diode Y3 and the second terminal of the output capacitor Y5 are connected to the applied terminal of the ground voltage GND2. The isolation capacitor Y2 is preferably a high withstand voltage element.

[0014] The driver Y1 is provided in the primary circuit system Yp. Diodes Y3 and Y4 and output capacitor Y5 are provided in the secondary circuit system Ys. The isolation capacitor Y2 isolates the primary circuit system Yp from the secondary circuit system Ys and transmits the drive pulse SY of the primary circuit system Yp as the drive pulse IY of the secondary circuit system Ys. The output voltage VY2 is generated by rectifying and smoothing the drive pulse IY. The drive pulse IY can be understood as a current signal.

[0015] Unlike the first comparative example (Figure 1), the power supply unit Y in this comparative example does not require a transformer X1, thus enabling cost reduction.

[0016] Figure 3 shows the drive pulse IY in the second comparative example. In this figure, the current direction from the primary circuit system Yp through the isolation capacitor Y2 to the secondary circuit system Ys is defined as the positive direction (>0).

[0017] When the drive pulse IY is at a high level, a positive current flows from the driver Y1 through the isolation capacitor Y2 and diode Y4 to the first terminal of the output capacitor Y5. On the other hand, when the drive pulse IY is at a low level, a negative current flows from the second terminal of the output capacitor Y5 through the diode Y3 and isolation capacitor Y2 to the driver Y1.

[0018] Thus, in the power supply unit Y of this comparative example, the drive pulse IY flowing through the isolation capacitor Y2 frequently switches between the positive and negative directions. Therefore, radiated noise can become a problem.

[0019] <Power supply unit (first embodiment)> Figure 4 shows a first embodiment of the power supply unit 1. The power supply unit 1 of this embodiment is an isolated DC / DC converter that isolates the primary circuit system 1p (GND1 system) and the secondary circuit system 1s (GND2 system) while converting the input voltage Vi supplied to the primary circuit system 1p into an output voltage Vo and supplying it to the secondary circuit system 1s. For example, the power supply unit 1 includes a pulse generation circuit 10, drivers 11 and 12, a rectifier and smoothing circuit 20, and isolation capacitors 31 and 32.

[0020] The pulse generation circuit 10 is provided in the primary circuit system 1p. The pulse generation circuit 10 generates drive pulses Pa1 and Pb1 in opposite phases to each other. That is, when the drive pulse Pa1 is at a high level (for example, the input voltage Vi or a lower voltage), the drive pulse Pb1 is at a low level (for example, the ground voltage GND1). Conversely, when the drive pulse Pa1 is at a low level, the drive pulse Pb1 is at a high level.

[0021] The driver 11 is provided in the primary circuit system 1p. The input terminal of the driver 11 is connected to the first output terminal of the pulse generation circuit 10 (= the application terminal of the drive pulse Pa1). The output terminal of the driver 11 is connected to the first terminal of the isolation capacitor 31. The driver 11 drives the isolation capacitor 31 in accordance with the drive pulse Pa1. For example, when the drive pulse Pa1 is at a high level, the driver 11 sources current from the application terminal of the input voltage Vi to the isolation capacitor 31. On the other hand, when the drive pulse Pa1 is at a low level, the driver 11 sinks current from the isolation capacitor 31 to the application terminal of the ground voltage GND1.

[0022] The driver 12 is provided in the primary circuit system 1p. The input terminal of the driver 12 is connected to the second output terminal of the pulse generation circuit 10 (= the application terminal of the drive pulse Pb1). The output terminal of the driver 12 is connected to the first terminal of the isolation capacitor 32. The driver 12 drives the isolation capacitor 32 in accordance with the drive pulse Pb1. For example, when the drive pulse Pb1 is at a high level, the driver 12 sources current from the application terminal of the input voltage Vi to the isolation capacitor 32. On the other hand, when the drive pulse Pb1 is at a low level, the driver 12 sinks current from the isolation capacitor 32 to the application terminal of the ground voltage GND1.

[0023] The rectifier-smoothing circuit 20 is provided in the secondary circuit system 1s. The rectifier-smoothing circuit 20 rectifies and smooths the drive pulses Ia and Ib transmitted via the isolation capacitors 31 and 32 to generate the output voltage Vo. Referring to this figure, the rectifier-smoothing circuit 20 includes diodes D1 to D4 and an output capacitor Co1.

[0024] The cathode of diode D1 is connected to the second terminal of the insulating capacitor 31. The anode of diode D1 is connected to the terminal to which the ground voltage GND2 is applied. The anode of diode D2 is connected to the second terminal of the insulating capacitor 31. The cathode of diode D2 is connected to the terminal to which the output voltage Vo is applied. Diodes D1 and D2 can be understood as a rectifier circuit 21 for rectifying the drive pulse Ia transmitted through the insulating capacitor 31.

[0025] The cathode of diode D3 is connected to the second terminal of the insulating capacitor 32. The anode of diode D3 is connected to the terminal to which the ground voltage GND2 is applied. The anode of diode D4 is connected to the second terminal of the insulating capacitor 32. The cathode of diode D4 is connected to the terminal to which the output voltage Vo is applied. Diodes D3 and D4 can be understood as a rectifier circuit 22 for rectifying the drive pulse Ib transmitted through the insulating capacitor 32.

[0026] The output capacitor Co1 is connected between the terminal to which the output voltage Vo is applied and the terminal to which the ground voltage GND2 is applied. In other words, the output capacitor Co1 is shared by rectifier circuits 21 and 22, which are connected in parallel to the terminal to which the output voltage Vo is applied.

[0027] The terminal to which ground voltage GND1 is applied can be understood as the ground terminal of the primary circuit system 1p. The terminal to which ground voltage GND2 is applied can be understood as the ground terminal of the secondary circuit system 1s.

[0028] The insulating capacitor 31 insulates the pulse generation circuit 10 from the rectifier and smoothing circuit 20, while transmitting the drive pulse Pa1 generated by the pulse generation circuit 10 to the rectifier and smoothing circuit 20 as a drive pulse Ia.

[0029] The insulating capacitor 32 insulates the pulse generation circuit 10 from the rectifier and smoothing circuit 20, while transmitting the drive pulse Pb1 generated by the pulse generation circuit 10 to the rectifier and smoothing circuit 20 as a drive pulse Ib.

[0030] The output voltage Vo is generated by rectifying and smoothing the drive pulses Ia and Ib. Note that both drive pulses Ia and Ib can be understood as current signals.

[0031] Figure 5 shows the drive pulses Ia and Ib in the first embodiment. In this figure, the current direction from the primary circuit system 1p to the secondary circuit system 1s via the isolation capacitors 31 and 32 is defined as the positive direction (>0).

[0032] As shown in the lower part of this figure, when the drive pulse Ia is at a high level, a current flows in the positive direction from the driver 11 through the isolation capacitor 31 and diode D2 to the first terminal of the output capacitor Co1. On the other hand, when the drive pulse Ia is at a low level, a current flows in the negative direction from the second terminal of the output capacitor Co1 through diode D1 and isolation capacitor 31 to the driver 11.

[0033] Furthermore, as shown in the upper part of this figure, when the drive pulse Ib is at a high level, a current flows in the positive direction from the driver 12 through the isolation capacitor 32 and diode D4 to the first terminal of the output capacitor Co1. On the other hand, when the drive pulse Ib is at a low level, a current flows in the negative direction from the second terminal of the output capacitor Co1 through diode D3 and isolation capacitor 32 to the driver 12.

[0034] Thus, in the power supply device 1 of this embodiment, the drive pulses Ia and Ib flowing through the isolation capacitors 31 and 32, respectively, frequently switch between the positive and negative directions.

[0035] However, the drive pulses Ia and Ib are driven in opposite phases. That is, when drive pulse Ia is high, drive pulse Ib is low, and when drive pulse Ia is low, drive pulse Ib is high. Therefore, the sum of the currents of drive pulses Ia and Ib is ideally always zero.

[0036] Therefore, with the power supply device 1 of this embodiment, fluctuations in the current flowing through the output capacitor Co1 are suppressed, and thus radiated noise can be reduced.

[0037] <Power supply unit (second embodiment)> Figure 6 shows a second embodiment of the power supply unit 1. This embodiment of the power supply unit 1 is based on the first embodiment (Figure 4) described above, but with the addition of an output capacitor Co2 to the rectifier and smoothing circuit 20. In addition, the connection relationship of diodes D2 and D3 has also been changed due to the addition of the output capacitor Co2.

[0038] Referring to this diagram, the cathode of diode D2 is connected to the internal node nd, not to the terminal where the output voltage Vo is applied. The anode of diode D3 is connected to the internal node nd, not to the terminal where the ground voltage GND2 is applied. The output capacitor Co2 is connected between the internal node nd and the terminal where the ground voltage GND2 is applied.

[0039] In other words, in the power supply device 1 of this embodiment, two rectifier circuits 21 and 22 are connected in tandem to the application terminal of the output voltage Vo. With this configuration, a higher output voltage Vo can be obtained than in the first embodiment described above (Figure 4). Also, the current waveforms of the drive pulses Ia and Ib are the same as in the first embodiment described above (Figure 5). Therefore, the effect of reducing radiated noise remains unchanged.

[0040] As shown by the dashed line in the figure, the output capacitor Co2 can be omitted by replacing diodes D2 and D3 with a single diode D23. However, the voltage applied across diode D23 will be twice the voltage applied across diodes D2 and D3, respectively. Therefore, diode D23 must be a component with a high voltage rating against reverse bias. On the other hand, in this configuration, diodes D2 and D3 with lower voltage ratings than diode D23 can be used.

[0041] <Power supply unit (third embodiment)> Figure 7 shows a third embodiment of the power supply unit 1. In this embodiment of the power supply unit 1, while being based on the first embodiment (Figure 4) described above, the diodes D1 to D4 interposed in the current path of the rectifier-smoothing circuit 20 are replaced with transistors M1 to M4, respectively. Transistors M1 and M3 may be, for example, N-channel type. Transistors M2 and M4 may be, for example, P-channel type. The rectifier-smoothing circuit 20 also includes capacitors C1 to C4, diodes D5 to D8, and resistors R1 to R4 as circuit elements associated with each of the transistors M1 to M4.

[0042] The drain of transistor M1 is connected to the second terminal of the insulating capacitor 31. The source of transistor M1 is connected to the terminal to which the ground voltage GND2 is applied. In other words, transistor M1 is connected between the second terminal of the insulating capacitor 31 and the terminal to which the ground voltage GND2 is applied.

[0043] The drain of transistor M2 is connected to the second terminal of the insulating capacitor 31. The source of transistor M2 is connected to the terminal to which the output voltage Vo is applied. In other words, transistor M2 is connected between the second terminal of the insulating capacitor 31 and the terminal to which the output voltage Vo is applied.

[0044] The drain of transistor M3 is connected to the second terminal of the insulating capacitor 32. The source of transistor M3 is connected to the terminal to which the ground voltage GND2 is applied. In other words, transistor M3 is connected between the second terminal of the insulating capacitor 32 and the terminal to which the ground voltage GND2 is applied.

[0045] The drain of transistor M4 is connected to the second terminal of the insulating capacitor 32. The source of transistor M4 is connected to the terminal to which the output voltage Vo is applied. In other words, transistor M4 is connected between the second terminal of the insulating capacitor 32 and the terminal to which the output voltage Vo is applied.

[0046] Capacitor C1 is connected between the gate of transistor M1 and the second terminal of insulating capacitor 32. Capacitor C2 is connected between the gate of transistor M2 and the second terminal of insulating capacitor 32. Capacitor C3 is connected between the gate of transistor M3 and the second terminal of insulating capacitor 31. Capacitor C4 is connected between the gate of transistor M4 and the second terminal of insulating capacitor 31.

[0047] Resistors R1 to R4 are connected between the gate and source of transistors M1 to M4, respectively. In other words, the voltage across resistors R1 to R4 corresponds to the gate-source voltages Vgs(M1) to Vgs(M4) of transistors M1 to M4.

[0048] The cathode of diode D5 is connected to the gate of transistor M1. The anode of diode D5 is connected to the source of transistor M1. In this way, diode D5 is connected in parallel with resistor R1.

[0049] The anode of diode D6 is connected to the gate of transistor M2. The cathode of diode D6 is connected to the source of transistor M2. In this way, diode D6 is connected in parallel with resistor R2.

[0050] The cathode of diode D7 is connected to the gate of transistor M3. The anode of diode D7 is connected to the source of transistor M3. In this way, diode D7 is connected in parallel with resistor R3.

[0051] The anode of diode D8 is connected to the gate of transistor M4. The cathode of diode D8 is connected to the source of transistor M4. In this way, diode D8 is connected in parallel with resistor R4.

[0052] The drain-source voltages Vds(M1) to Vds(M4) of transistors M1 to M4 when they are ON are lower than the forward voltage drops Vf(D1) to Vf(D4) of diodes D1 to D4. Therefore, with this configuration, the voltage loss in the rectifier-smoothing circuit 20 is reduced compared to the first embodiment described above (Figure 4). The drain-source voltages Vds(M1) to Vds(M4) are expressed as Vds(M1)=Ia×Ron(M1), Vds(M2)=Ia×Ron(M2), Vds(M3)=Ib×Ron(M3), and Vds(M4)=Ib×Ron(M4). Ron(M1) to Ron(M4) are the ON-resistance values ​​of transistors M1 to M4.

[0053] Transistors M1 and M2 are driven according to the drive pulse Ib. When the drive pulse Ib is high level, the gate-source voltages Vgs(M1) and Vgs(M2) of transistors M1 and M2 rise. As a result, transistor M1 turns on and transistor M2 turns off. On the other hand, when the drive pulse Ib is low level, the gate-source voltages Vgs(M1) and Vgs(M2) of transistors M1 and M2 fall. As a result, transistor M1 turns off and transistor M2 turns on.

[0054] Transistors M3 and M4 are driven according to the drive pulse Ia. When the drive pulse Ia is high level, the gate-source voltages Vgs(M3) and Vgs(M4) of transistors M3 and M4 rise. As a result, transistor M3 turns on and transistor M4 turns off. On the other hand, when the drive pulse Ia is low level, the gate-source voltages Vgs(M3) and Vgs(M4) of transistors M3 and M4 fall. As a result, transistor M3 turns off and transistor M4 turns on.

[0055] With this configuration, it is not necessary to prepare separate control signals for each of the transistors M1 to M4. If it is necessary to lower the on-resistance values ​​Ron(M1) to Ron(M4) of each of the transistors M1 to M4, diodes D5 to D8 should be connected in parallel to resistors R1 to R4, respectively, in order to raise the gate-source voltages Vgs(M1) to Vgs(M4) of each of the transistors M1 to M4.

[0056] <Power supply unit (fourth embodiment)> Figure 8 shows a fourth embodiment of the power supply unit 1. The power supply unit 1 of this embodiment is based on the third embodiment (Figure 7) described above, but is equipped with a boost circuit 40 in the primary circuit system 1p.

[0057] The boost circuit 40 receives the input voltage Vi and supplies boost voltages VCPa and VCPb, which are higher than the input voltage Vi, to the drivers 11 and 12. As shown in the figure, the boost circuit 40 includes charge pumps 41 and 42.

[0058] Furthermore, in this figure, transistors M5 to M8 are explicitly shown as components of drivers 11 and 12. Transistors M5 and M7 may be, for example, P-channel type. Transistors M6 and M8 may be, for example, N-channel type.

[0059] The source of transistor M5 is connected to the application terminal of the boost voltage VCPa. The drains of transistors M5 and M6 are connected to the first terminal of the insulating capacitor 31. The source of transistor M6 is connected to the application terminal of the ground voltage GND1. The gates of transistors M5 and M6 are connected to the application terminal of the inverting drive pulse Pa1B. Transistors M5 and M6 form a CMOS (complementary metal-oxide-semiconductor) inverter that drives the first terminal of the insulating capacitor 31 in accordance with the inverting drive pulse Pa1B, and consequently the drive pulse Pa1.

[0060] The source of transistor M7 is connected to the application terminal of the boosted voltage VCPb. The drains of transistors M7 and M8 are connected to the first terminal of the insulating capacitor 32. The source of transistor M8 is connected to the application terminal of the ground voltage GND1. The gates of transistors M7 and M8 are connected to the application terminal of the inverting drive pulse Pb1B. Transistors M7 and M8 form a CMOS inverter that drives the first terminal of the insulating capacitor 32 in accordance with the inverting drive pulse Pb1B, and consequently the drive pulse Pb1.

[0061] The charge pump 41 receives an input voltage Vi and generates a boosted voltage VCPa. Referring to the figure, the charge pump 41 includes a flying capacitor Ca, a diode D9, an inverter INV1, and transistors M9 and M10. Transistor M9 may be, for example, a P-channel type. Transistor M10 may be, for example, an N-channel type.

[0062] The first terminal of the flying capacitor Ca is connected to the application terminal of the boosted voltage VCPa. The second terminal of the flying capacitor Ca is connected to the drains of transistors M9 and M10, respectively.

[0063] The source of transistor M9 is connected to the input voltage Vi application terminal. The drains of transistors M9 and M10 are connected to the second terminal of the flying capacitor Ca. The source of transistor M10 is connected to the ground voltage GND1 application terminal. The gates of transistors M9 and M10 are connected to the application terminal of the inverting drive pulse Pa1B. Transistors M9 and M10 form a CMOS inverter that drives the second terminal of the flying capacitor Ca in accordance with the inverting drive pulse Pa1B, and consequently the drive pulse Pa1.

[0064] The inverter INV1 generates an inverting drive pulse Pa1B by inverting the logic level of the drive pulse Pa1. When the drive pulse Pa1 is at a high level, the inverting drive pulse Pa1B is at a low level. Conversely, when the drive pulse Pa1 is at a low level, the inverting drive pulse Pa1B is at a high level. Note that the inverter INV1 may be understood as part of the driver 11.

[0065] The anode of diode D9 is connected to the input voltage Vi application terminal. The cathode of diode D9 is connected to the first terminal of the flying capacitor Ca. In other words, diode D9 can be understood as an example of a switching element that conducts / blocks the connection between the input voltage Vi application terminal and the first terminal of the flying capacitor Ca.

[0066] The charge pump 42 receives an input voltage Vi and generates a boosted voltage VCPb. Referring to the figure, the charge pump 42 includes a flying capacitor Cb, a diode D10, an inverter INV2, and transistors M11 and M12. Transistor M11 may be, for example, a P-channel type. Transistor M12 may be, for example, an N-channel type.

[0067] The first terminal of the flying capacitor Cb is connected to the application terminal of the boosted voltage VCPb. The second terminal of the flying capacitor Cb is connected to the drains of transistors M11 and M12, respectively.

[0068] The source of transistor M11 is connected to the input voltage Vi application terminal. The drains of transistors M11 and M12 are connected to the second terminal of the flying capacitor Cb. The source of transistor M12 is connected to the ground voltage GND1 application terminal. The gates of transistors M11 and M12 are connected to the application terminal of the inverting drive pulse Pb1B. Transistors M11 and M12 form a CMOS inverter that drives the second terminal of the flying capacitor Cb in accordance with the inverting drive pulse Pb1B, and consequently the drive pulse Pb1.

[0069] Inverter INV2 generates an inverting drive pulse Pb1B by inverting the logic level of the drive pulse Pb1. When the drive pulse Pb1 is high level, the inverting drive pulse Pb1B is low level. Conversely, when the drive pulse Pb1 is low level, the inverting drive pulse Pb1B is high level. Note that inverter INV2 may be understood as part of driver 12.

[0070] The anode of diode D10 is connected to the terminal to which the input voltage Vi is applied. The cathode of diode D10 is connected to the first terminal of the flying capacitor Cb. In other words, diode D10 can be understood as an example of a switching element that conducts / blocks the connection between the terminal to which the input voltage Vi is applied and the first terminal of the flying capacitor Cb.

[0071] The introduction of the boost circuit 40 supplies drivers 11 and 12 with boost voltages VCPa and VCPb that are higher than the input voltage Vi. Therefore, even when the input voltage Vi is low, a sufficient output voltage Vo can be ensured.

[0072] <Power supply unit (5th embodiment)> Figure 9 shows a fifth embodiment of the power supply unit 1. In this embodiment of the power supply unit 1, the diodes D9 and D10 that form the boost circuit 40 are replaced with transistors M13 and M14, respectively. Transistors M13 and M14 may be, for example, N-channel type. The boost circuit 40 also includes buffers BUF1 and BUF2, capacitors C5 and C6, and diodes D11 and D12 as circuit elements associated with transistors M13 and M14, respectively.

[0073] The source of transistor M13 is connected to the input voltage Vi application terminal. The drain of transistor M13 is connected to the first terminal of the flying capacitor Ca. In other words, transistor M13 can be understood as an example of a switching element that conducts / blocks the connection between the input voltage Vi application terminal and the first terminal of the flying capacitor Ca.

[0074] The input terminal of buffer BUF1 is connected to the third output terminal of pulse generation circuit 10 (= the application terminal of control pulse Pa2). The output terminal of buffer BUF1 is connected to the first terminal of capacitor C5. The second terminal of capacitor C5 is connected to the cathode of diode D11 and the gate of transistor M13. The anode of diode D11 is connected to the source of transistor M13.

[0075] The source of transistor M14 is connected to the input voltage Vi application terminal. The drain of transistor M14 is connected to the first terminal of the flying capacitor Cb. In other words, transistor M14 can be understood as an example of a switching element that conducts / blocks the connection between the input voltage Vi application terminal and the first terminal of the flying capacitor Cb.

[0076] The input terminal of buffer BUF2 is connected to the fourth output terminal of pulse generation circuit 10 (= application terminal of control pulse Pb2). The output terminal of buffer BUF2 is connected to the first terminal of capacitor C6. The second terminal of capacitor C6 is connected to the cathode of diode D12 and the gate of transistor M14. The anode of diode D12 is connected to the source of transistor M14.

[0077] Transistor M13 is driven in response to a control pulse Pa2. When the control pulse Pa2 is at a high level, transistor M13 is turned on. Conversely, when the control pulse Pa2 is at a low level, transistor M13 is turned off.

[0078] Transistor M14 is driven in response to the control pulse Pb2. When the control pulse Pb2 is at a high level, transistor M14 is turned on. Conversely, when the control pulse Pb2 is at a low level, transistor M14 is turned off.

[0079] The drain-source voltages Vds(M13) and Vds(M14) of transistors M13 and M14 when they are ON are lower than the forward voltage drops Vf(D10) and Vf(D11) of diodes D9 and D10, respectively. Therefore, with this configuration, the voltage loss in the boost circuit 40, and consequently the decrease in the boosted voltages VCPa and VCPb, is suppressed compared to the fourth embodiment described above (Figure 8).

[0080] Figure 10 shows the drive pulses Pa1 and Pb1 and the control pulses Pa2 and Pb2 in the fifth embodiment. In this figure, the drive pulse Pb1, control pulse Pb2, drive pulse Pa1, and control pulse Pa2 are depicted from top to bottom.

[0081] As shown in this figure, the drive pulse Pa1 and the control pulse Pa2 should be driven in opposite phases. However, the high-level period Ta2 of the control pulse Pa2 should be shorter than the low-level period Ta1 of the drive pulse Pa1. For example, it is preferable that the drive pulse Pa1 falls to a low level before the control pulse Pa2 rises to a high level. Alternatively, it is preferable that the control pulse Pa2 falls to a low level before the drive pulse Pa1 rises to a high level. In other words, the ON period of transistor M13 should be contained within the low-level output period of the driver 11 (= the period when transistor M5 is in the OFF state and transistor M6 is in the ON state).

[0082] Furthermore, the drive pulse Pb1 and the control pulse Pb2 should be driven in opposite phases. However, the high-level period Tb2 of the control pulse Pb2 should be shorter than the low-level period Tb1 of the drive pulse Pb1. For example, it is preferable that the drive pulse Pb1 falls to a low level before the control pulse Pb2 rises to a high level. Alternatively, it is preferable that the control pulse Pb2 falls to a low level before the drive pulse Pb1 rises to a high level. In other words, the ON period of transistor M14 should be contained within the low-level output period of driver 12 (=the period when transistor M7 is in the OFF state and transistor M8 is in the ON state).

[0083] Furthermore, as mentioned earlier, the drive pulses Pa1 and Pb1 should preferably be driven in opposite phases to each other.

[0084] <Power supply unit (6th embodiment)> Figure 11 shows a sixth embodiment of the power supply unit 1. This embodiment of the power supply unit 1 is based on the fifth embodiment (Figure 10) described above, and, following the second embodiment (Figure 6), an output capacitor Co2 is added to the rectifier and smoothing circuit 20. In addition, the connection relationship between transistors M2 and M3 has also been changed due to the addition of the output capacitor Co2.

[0085] Referring to this diagram, the source of transistor M2 is connected to the internal node nd, not to the terminal where the output voltage Vo is applied. The source of transistor M3 is connected to the internal node nd, not to the terminal where the ground voltage GND2 is applied. The output capacitor Co2 is connected between the internal node nd and the terminal where the ground voltage GND2 is applied.

[0086] In other words, in the power supply device 1 of this embodiment, two rectifier circuits 21 and 22 are connected in tandem to the terminal to which the output voltage Vo is applied. With this configuration, a higher output voltage Vo can be obtained than in the fifth embodiment described above (Figure 10).

[0087] <Power supply unit (7th embodiment)> Figure 12 shows a seventh embodiment of the power supply unit 1. The power supply unit 1 of this embodiment is based on the previously described third embodiment (Figure 7) and includes a first chip 110, a second chip 120, and isolation capacitors 31 and 32.

[0088] The first chip 110 integrates a pulse generation circuit 10 and drivers 11 and 12. The first chip 110 includes, for example, pads 111 and 112 as means for establishing an electrical connection with the outside of the chip. The output terminal of driver 11 is connected to the first terminal of isolation capacitor 31 via pad 111. The output terminal of driver 12 is connected to the first terminal of isolation capacitor 32 via pad 112.

[0089] The second chip 120 integrates a rectifier and smoothing circuit 20. The second chip 120 includes, for example, pads 121 to 124 as means for establishing an electrical connection with the outside of the chip. The drains of transistors M1 and M2 and the gates of transistors M3 and M4 are all connected to the second terminal of the isolation capacitor 31 via pad 121. The drains of transistors M3 and M4 and the gates of transistors M1 and M2 are all connected to the second terminal of the isolation capacitor 32 via pad 122. The sources of transistors M2 and M4 are all connected to the application terminal of the output voltage Vo via pad 123. The sources of transistors M1 and M3 are all connected to the application terminal of the ground voltage GND2 via pad 124.

[0090] Figure 13 shows an example of packaging for the power supply unit 1 in the seventh embodiment. The power supply unit 1 in this embodiment comprises a semiconductor device 100, insulating capacitors 31 and 32, and an output capacitor Co1.

[0091] The semiconductor device 100 is comprised of a first chip 110 and a second chip 120 sealed in a single package. On the other hand, the insulating capacitors 31 and 32 and the output capacitor Co1 are all large in size, making it difficult to integrate them into the semiconductor device 100. Therefore, it is desirable to provide the insulating capacitors 31 and 32 and the output capacitor Co1 as discrete components externally attached to the semiconductor device 100. This configuration makes it possible to increase the production efficiency of the power supply unit 1.

[0092] <Power supply unit (8th embodiment)> Figure 14 shows the eighth embodiment of the power supply unit 1. This embodiment of the power supply unit 1 is based on the fifth embodiment (Figure 9) described above, and follows the seventh embodiment (Figure 13), and includes a first chip 110, a second chip 120, and isolation capacitors 31 and 32. The following description will focus on the differences from the seventh embodiment (Figure 13).

[0093] The first chip 110 integrates a pulse generation circuit 10, drivers 11 and 12, and charge pumps 41 and 42. In addition, the first chip 110 includes pads 113 to 117, as means of establishing an electrical connection with the outside of the chip, in addition to the aforementioned pads 111 and 112.

[0094] The sources of transistors M9, M11, M13, and M14 are connected to the input voltage Vi application terminals via pad 113.

[0095] The source of transistor M5, the drain of transistor M13, and the anode of diode D11 are all connected to the first terminal of flying capacitor Ca via pad 114. The drains of transistors M9 and M10 are both connected to the second terminal of flying capacitor Ca via pad 115.

[0096] The source of transistor M7, the drain of transistor M14, and the anode of diode D12 are all connected to the first terminal of the flying capacitor Cb via pad 116. The drains of transistors M11 and M12 are both connected to the second terminal of the flying capacitor Cb via pad 117.

[0097] Figure 15 shows an example of packaging in the eighth embodiment. The power supply unit 1 of this embodiment comprises a semiconductor device 100, isolation capacitors 31 and 32, output capacitor Co1, and flying capacitors Ca and Cb.

[0098] The semiconductor device 100, like the seventh embodiment described above (Figure 13), is formed by encapsulating the first chip 110 and the second chip 120 in a single package. On the other hand, the insulating capacitors 31 and 32, the output capacitor Co1, and the flying capacitors Ca and Cb are all large in size, making it difficult to integrate them into the semiconductor device 100. Therefore, it is desirable to provide the insulating capacitors 31 and 32, the output capacitor Co1, and the flying capacitors Ca and Cb as discrete components externally attached to the semiconductor device 100. With this configuration, it is possible to increase the production efficiency of the power supply unit 1.

[0099] <Power supply unit (9th embodiment)> Figure 16 shows the ninth embodiment of the power supply unit 1. The power supply unit 1 of this embodiment is based on the eighth embodiment (Figure 14) described above, but only the charge pump 41 is integrated on the first chip 110. However, the inverter INV2 is integrated as part of the driver 12. In addition, the second chip 120 includes a pad 125 in addition to the pads 121 to 124 described above. The following explanation will focus on the differences from the eighth embodiment (Figure 14).

[0100] In the first chip 110, the source of transistor M7 is directly connected to pad 113. Therefore, the source of transistor M7, along with the sources of transistors M9 and M13 respectively, is connected to the application terminal of the input voltage Vi via pad 113.

[0101] On the other hand, in the second chip 120, one end each of capacitors C3 and C4 is connected to pad 125. In other words, the gates corresponding to the control terminals of transistors M3 and M4 are conducted to pad 125, not pad 121.

[0102] The connection destination of pad 125 is switched outside the second chip 120 depending on whether the charge pump 41 is used or not. As shown in this figure, when the flying capacitor Ca is connected to the first chip 110 and the charge pump 41 is used, pad 125 is connected outside the second chip 120 to the application terminal of the ground voltage GND2. Therefore, transistors M3 and M4 are always in the off state regardless of the drive pulse Ia. To add to this, since DC is blocked by capacitor C4, transistor M4 is fixed in the off state. As a result, the current supply to the output capacitor Co1 is single-drive by drive pulse Ia only. In other words, drive pulse Ib is used only for drive control of transistors M1 and M2.

[0103] Figure 17 shows an example of packaging in the ninth embodiment. The power supply unit 1 of this embodiment comprises a semiconductor device 100, isolation capacitors 31 and 32, output capacitor Co1, and flying capacitor Ca.

[0104] As is clear from comparing it with Figure 15 shown earlier, with this configuration, the charge pump 42 is omitted, and the pads 116 and 117, the external terminals connected to them, and the flying capacitor Cb can be reduced. On the other hand, in this configuration, an external terminal connected to pad 125 is added. A ground voltage GND2 can be applied to this external terminal.

[0105] <Power supply unit (10th embodiment)> Figure 18 shows a tenth embodiment of the power supply unit 1. This embodiment of the power supply unit 1 is based on the ninth embodiment (Figure 16) described earlier, but corresponds to a case where the charge pump 41 is not used. For example, this configuration can be adopted when the input voltage Vi is sufficiently high.

[0106] As shown in the diagram, in the first chip 110, pad 114 is connected to the terminal to which the input voltage Vi is applied, and pad 115 is left open. Therefore, the driver 11 is supplied with the input voltage Vi, not the boosted voltage VCPa. In the second chip 120, pad 125 is connected to the second terminal of the isolation capacitor 31. Therefore, transistors M3 and M4 are driven according to the drive pulse Ia.

[0107] Figure 19 shows an example of packaging in the tenth embodiment. Focusing on the external terminals of the semiconductor device 100, an input voltage Vi is applied to the external terminal that is conductive to pad 114. The external terminal that is conductive to pad 115 is left open. The external terminal that is conductive to pad 125 is connected to the second terminal of the insulating capacitor 31.

[0108] <Electronic equipment> Figure 20 shows the overall configuration of electronic device A. Electronic device A in this example configuration comprises a semiconductor device 100, a microcontroller 200, and an isolation capacitor circuit 30. The isolation capacitor circuit 30 includes the previously mentioned isolation capacitors 31 and 32.

[0109] The semiconductor device 100 integrates an isolated ADC (analog to digital converter) 2 in addition to a part of the power supply unit 1. The isolated ADC 2 isolates the first chip 110 and the second chip 120, and transmits the analog input signal AI input to the second chip 120 as a digital output signal DO output from the first chip 110. The digital output signal DO is output to the microcontroller 200.

[0110] Referring to this diagram, the isolated ADC2 includes a ΔΣADC61, a transmitting circuit62, an isolated communication circuit63, a receiving circuit64, an interface65, a transmitting circuit66, an isolated communication circuit67, and a receiving circuit68.

[0111] The ΔΣADC61 receives an external input of an analog input signal AI and converts it into a digital signal S1. The ΔΣADC61 may operate in synchronization with the drive clock signal S8 output from the receiving circuit 68. The ΔΣADC61 may be integrated into the second chip 120.

[0112] The transmitting circuit 62 outputs a transmit pulse signal S2 to the isolated communication circuit 63 in accordance with the digital signal S1 output from the ΔΣADC 61. The transmitting circuit 62 may be integrated into the second chip 120.

[0113] The isolated communication circuit 63 transmits the transmitted pulse signal S2 as a received pulse signal S3 while isolating the transmitting circuit 62 and the receiving circuit 64. The isolated communication circuit 63 may be connected between the first chip 110 and the second chip 120. The isolated communication circuit 63 may be packaged together with the first chip 110 and the second chip 120 in a single package. The isolated communication circuit 63 may include a transformer or a capacitor as an isolated communication element.

[0114] The receiving circuit 64 outputs a digital signal S4 in response to a received pulse signal S3 transmitted via the isolated communication circuit 63. The receiving circuit 64 may be integrated into the first chip 110.

[0115] Interface 65 performs bidirectional communication with the microcontroller 200. For example, interface 65 outputs a digital output signal DO to the microcontroller 200 in response to the digital signal S4 output from the receiving circuit 64. Interface 65 also outputs the clock signal CLK output from the microcontroller 200 as an internal clock signal S5 to the transmitting circuit 66. Interface 65 may be integrated into the first chip 110.

[0116] The transmitting circuit 66 outputs a transmit clock signal S6 to the isolated communication circuit 67 in accordance with the internal clock signal S5 output from the interface 65. The transmitting circuit 66 may be integrated into the first chip 110.

[0117] The isolated communication circuit 67 transmits the transmit clock signal S6 as a receive clock signal S7 while isolating the transmit circuit 66 and the receive circuit 68. The isolated communication circuit 67 may be connected between the first chip 110 and the second chip 120. The isolated communication circuit 67 may be packaged together with the first chip 110 and the second chip 120 in a single package. The isolated communication circuit 67 may include a transformer or a capacitor as an isolated communication element.

[0118] The isolated communication circuits 63 and 67 may be integrated into a third chip (not shown).

[0119] The receiving circuit 68 outputs a drive clock signal S8 for the ΔΣADC 61 in response to a received clock signal S7 transmitted via the isolated communication circuit 67. The receiving circuit 68 may be integrated into the second chip 120.

[0120] Here, the second chip 120 may integrate a regulator 50 as an additional component forming the power supply unit 1 described above. The regulator 50 generates the drive voltage Vdrv of the ΔΣADC 61 from the output voltage Vo generated by the rectifier-smoothing circuit 20.

[0121] With this configuration, even if a power supply is not provided for the secondary circuit system 1s where the second chip 120 is located, power can be supplied from the first chip 110 in the primary circuit system 1p.

[0122] <Power supply unit (11th embodiment)> Figure 21 shows the eleventh embodiment of the power supply unit 1. The power supply unit 1 of this embodiment is based on the seventh embodiment (Figure 12) described above, and further includes a detection circuit 70 and an isolated communication circuit 80.

[0123] The detection circuit 70 detects the output voltage Vo and generates a feedback signal FB. The feedback signal FB may be, for example, a pulse signal with a duty cycle corresponding to the voltage value of the output voltage Vo. The detection circuit 70 may be integrated into the second chip 120.

[0124] The isolated communication circuit 80 transmits a feedback signal FB from the detection circuit 70 to the pulse generation circuit 10 while insulating the detection circuit 70 from the pulse generation circuit 10. For example, the isolated communication circuit 80 may include a transmitting circuit 81, a receiving circuit 82, and an insulating capacitor 83.

[0125] The transmitting circuit 81 drives the isolation capacitor 83 in response to the feedback signal FB output from the detection circuit 70. The transmitting circuit 81 may be integrated into the second chip 120.

[0126] The receiving circuit 82 receives the feedback signal FB transmitted via the isolation capacitor 83 and outputs it to the pulse generation circuit 10. The receiving circuit 82 may be integrated into the first chip 110.

[0127] The isolation capacitor 83 transmits a feedback signal FB from the transmitting circuit 81 to the receiving circuit 82 while insulating the transmitting circuit 81 from the receiving circuit 82. The isolation capacitor 83 may be connected between the first chip 110 and the second chip 120. The isolation capacitor 83 may be packaged together with the first chip 110 and the second chip 120 in a single package.

[0128] The pulse generation circuit 10 generates drive pulses Pa1 and Pb1 in response to the feedback signal FB output from the isolated communication circuit 80. For example, the pulse generation circuit 10 may stop generating drive pulses Pa1 and Pb1 or lower the drive frequency when the output voltage Vo is higher than the target value.

[0129] With this configuration, it is possible to reduce the power consumption of power supply unit 1.

[0130] Figure 22 shows a modified example of electronic device A. This modified example of electronic device A is equipped with the power supply unit 1 of the 11th embodiment (Figure 21). Therefore, it is possible to supply ΔΣADC61 with just the right amount of power.

[0131] <Combination of Embodiments> Furthermore, the various embodiments described so far may be combined in any way as long as they are not contradictory.

[0132] <Note> The power supply device described in this disclosure can reduce radiated noise. Further details regarding the above disclosure are provided below.

[0133] [Note 1] A pulse generation circuit (10) configured to generate a first drive pulse (Pa1) and a second drive pulse (Pb1) in opposite phases to each other, A rectifier and smoothing circuit (20) is configured to rectify and smooth the third drive pulse (Ia) and the fourth drive pulse (Ib) to generate an output voltage (Vo), A first insulating capacitor (31) and a second insulating capacitor (32) are configured to transmit the first drive pulse (Pa1) and the second drive pulse (Pb1) generated by the pulse generation circuit (10) to the rectifier-smoothing circuit (20) as the third drive pulse (Ia) and the fourth drive pulse (Ib), respectively, while insulating the pulse generation circuit (10) and the rectifier-smoothing circuit (20). A power supply (1) comprising the following:

[0134] [Note 2] The rectifier and smoothing circuit (20) is A first diode (D1) whose cathode is connected to the first insulating capacitor (31) and whose anode is connected to the ground terminal (GND2), A second diode (D2) whose anode is connected to the first insulating capacitor (31) and whose cathode is connected to the terminal to which the output voltage (Vo) is applied, A third diode (D3) whose cathode is connected to the second insulating capacitor (32) and whose anode is connected to the ground terminal (GND2), A fourth diode (D4) whose anode is connected to the second insulating capacitor (32) and whose cathode is connected to the terminal to which the output voltage (Vo) is applied, A first output capacitor (Co1) is connected between the output voltage (Vo) application terminal and the ground terminal (GND2), The power supply unit (1) described in Appendix 1, including the one described in Appendix 1.

[0135] [Note 3] The rectifier and smoothing circuit (20) is A first diode (D1) whose cathode is connected to the first insulating capacitor (31) and whose anode is connected to the ground terminal (GND2), A second diode (D2) whose anode is connected to the first insulating capacitor (31) and whose cathode is connected to the internal node (nd), A third diode (D3) whose cathode is connected to the second insulating capacitor (32) and whose anode is connected to the internal node (nd), A fourth diode (D4) whose anode is connected to the second insulating capacitor (32) and whose cathode is connected to the terminal to which the output voltage (Vo) is applied, A first output capacitor (Co1) is connected between the output voltage (Vo) application terminal and the ground terminal (GND2), A second output capacitor (Co2) is connected between the internal node (nd) and the ground terminal (GND2), The power supply unit (1) described in Appendix 1, including the one described in Appendix 1.

[0136] [Note 4] The rectifier and smoothing circuit (20) is A first transistor (M1) is connected between the first insulating capacitor (31) and the ground terminal, A second transistor (M2) is connected between the first insulating capacitor (31) and the terminal to which the output voltage (Vo) is applied, A third transistor (M3) is connected between the aforementioned second insulating capacitor (32) and the ground terminal (GND2), A fourth transistor (M4) is connected between the second insulating capacitor (32) and the terminal to which the output voltage (Vo) is applied, A first output capacitor (Co1) is connected between the output voltage (Vo) application terminal and the ground terminal (GND2), The power supply unit (1) described in Appendix 1, including the one described in Appendix 1.

[0137] [Note 5] The rectifier and smoothing circuit (20) is A first transistor (M1) is connected between the first insulating capacitor (31) and the ground terminal (GND2), A second transistor (M2) is connected between the first isolation capacitor (31) and the internal node (nd), A third transistor (M3) is connected between the second insulating capacitor (32) and the internal node (nd), A fourth transistor (M4) is connected between the second insulating capacitor (32) and the terminal to which the output voltage (Vo) is applied, A first output capacitor (Co1) is connected between the output voltage (Vo) application terminal and the ground terminal (GND2), A second output capacitor (Co2) is connected between the internal node (nd) and the ground terminal (GND2), The power supply unit (1) described in Appendix 1, including the one described in Appendix 1.

[0138] [Note 6] The power supply (1) described in Appendix 4 or 5, wherein the first transistor (M1) and the second transistor (M2) are driven in accordance with the fourth drive pulse (Ib), and the third transistor (M3) and the fourth transistor (M4) are driven in accordance with the third drive pulse (Ia).

[0139] [Note 7] The rectifier and smoothing circuit (20) is A first capacitor (C1) and a second capacitor (C2) are connected between the gates of the first transistor (M1) and the second transistor (M2) and the second insulating capacitor (32), respectively. A third capacitor (C3) and a fourth capacitor (C4) are connected between the gates of the third transistor (M3) and the fourth transistor (M4) and the first insulating capacitor (31), respectively. The power supply (1) described in Appendix 6, further including the following.

[0140] [Note 8] The rectifier-smoothing circuit (20) further includes a first resistor (R1), a second resistor (R2), a third resistor (R3), and a fourth resistor (R4), respectively, connected between the gate and source of the first transistor (M1), the second transistor (M2), the third transistor (M3), and the fourth transistor (M4), as described in Appendix 7, for the power supply device (1).

[0141] [Note 9] The rectifier-smoothing circuit (20) further includes a fifth diode (D5), a sixth diode (D6), a seventh diode (D7), and an eighth diode (D8) connected in parallel to the first resistor (R1), the second resistor (R2), the third resistor (R3), and the fourth resistor (R4), respectively, as described in Appendix 8, for the power supply device (1).

[0142] [Note 10] A first driver (11) configured to drive the first isolation capacitor (31) in response to the first drive pulse (Pa1), A second driver (12) configured to drive the second isolation capacitor (32) in response to the second drive pulse (Pb1), The power supply device (1) according to any one of the appendices 1 to 9, further comprising a boost circuit (40) configured to receive an input voltage (Vi) and supply a boosted voltage (VCPa, VCPb) higher than the input voltage (Vi) to at least one of the first driver (11) and the second driver (12).

[0143] [Note 11] The aforementioned boost circuit (40) A flying capacitor (Ca, Cb) whose first end is connected to the application terminal of the boosted voltage (VCP1, VCP2), A switch element (D9, D10, M13, M14) configured to conduct / block the connection between the input voltage (Vi) application terminal and the first terminal of the flying capacitor (Ca, Cb), An inverter (M9, M10, M11 and M12) configured to drive the second end of the flying capacitor (Ca, Cb) in response to the first drive pulse (Pa1) or the second drive pulse (Pb1), Power supply device (1) as described in Appendix 10, including the power supply device described in Appendix 10.

[0144] [Note 12] The power supply device (1) described in Appendix 11 is a diode (D9, D10) whose anode is connected to the input voltage (Vi) application terminal and whose cathode is connected to the first terminal of the flying capacitor (Ca, Cb).

[0145] [Note 13] The power supply device (1) described in Appendix 11, wherein the switching elements (M13, M14) are transistors (M13, M14) configured to be driven in accordance with a first control pulse (Pa2) or a second control pulse (Pb2).

[0146] [Note 14] The power supply (1) described in Appendix 13, wherein the ON period (Ta2, Tb2) of the transistors (M13, M14) is included in the low-level output period (Ta1, Tb1) of the first driver (11) or the second driver (12).

[0147] [Note 15] A detection circuit (70) configured to detect the output voltage (Vo) and generate a feedback signal (FB), An isolated communication circuit (80) is configured to transmit the feedback signal (FB) from the detection circuit (70) to the pulse generation circuit (10) while insulating the detection circuit (70) from the pulse generation circuit (10), Furthermore, The pulse generation circuit (10) is a power supply device (1) according to any one of the appendices 1 to 14, which generates the first drive pulse (Pa1) and the second drive pulse (Pb1) in response to the feedback signal (FB).

[0148] [Note 16] A semiconductor device (100) used in a power supply device (1) described in any of the appendices 1 to 15, The pulse generation circuit (10) is integrated into a first chip (110), The rectifier and smoothing circuit (20) is integrated into a second chip (120), A semiconductor device (100) comprising a sealed element.

[0149] [Note 17] A semiconductor device (100) used in a power supply device (1) described in any of the appendices 4 to 9, The pulse generation circuit (10) is integrated into a first chip (110), The rectifier and smoothing circuit (20) is integrated into a second chip (120), It is formed by sealing, The second chip (120) is a semiconductor device (100) comprising pads (125) that are electrically connected to the gates of the third transistor (M3) and the fourth transistor (M4), respectively.

[0150] [Note 18] The semiconductor device (100) according to Appendix 16 or 17, further comprising an isolated ADC (2) configured to transmit an analog signal (AI) input to the second chip (120) as a digital signal (DO) output from the first chip (110) while insulating the first chip (110) from the second chip (120).

[0151] [Note 19] The second chip (120) has, ADC(61) configured to convert the aforementioned analog signal (AI) into digital, A regulator (50) configured to generate the drive voltage (Vdrv) of the ADC (61) from the output voltage (Vo), The semiconductor device (100) described in Appendix 18 is further integrated.

[0152] [Note 20] A semiconductor device (100) described in any of the appendices 16 to 19, The first insulating capacitor (31) and the second insulating capacitor (32) are connected to the semiconductor device (100), An electronic device (A) equipped with [a certain feature].

[0153] <Other> Furthermore, the various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered in all respects to be illustrative and not restrictive. Moreover, the technical scope of this disclosure is defined by the claims and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0154] 1 Power supply 1p primary circuit system 1s secondary circuit system 2 Isolated ADC 10. Pulse generation circuit 11, 12 drivers 20 Rectifier smoothing circuit 30. Isolation Capacitor Circuit 31, 32 Isolation Capacitors 40 Boost Circuit 41, 42 Charge pump 50 Regulator 61 ΔΣADC 62 Transmitter Circuit 63 Isolated Communication Circuits 64 Receiving Circuit 65 Interfaces 66 Transmitter Circuit 67 Isolated Communication Circuits 68 Receiving Circuit 70 Detection Circuit 80 Isolated Communication Circuits 81 Transmitter Circuit 82 Receiving Circuit 83 Isolation Capacitor 100 Semiconductor Equipment 110 First chip Pads 111, 112, 113-117 120 Second chip 121-124, 125 pads 200 microcontrollers A Electronic equipment BUF1, BUF2 buffers C1-C4, C5, C6 Capacitors Ca, Cb flying capacitors CO1, CO2 output capacitor Diodes D1-D4, D5-D8, D9, D10, D11, D12, D23 INV1, INV2 Inverters M1-M4, M5-M12, M13, M14 Transistors nd internal node R1~R4 resistance X Power supply Xp primary circuit system Xs Secondary circuit system X1 Transformer X1p Primary coil X1s secondary coil X2 Transistor X3 Driver X4 Diode X5 Capacitor Y Power supply Yp Primary circuit system Ys Secondary circuit system Y1 Driver Y2 Isolation Capacitor Y3, Y4 diodes Y5 Output Capacitor

Claims

1. A pulse generation circuit configured to generate a first drive pulse and a second drive pulse in opposite phases to each other, A rectifier and smoothing circuit configured to rectify and smooth the third drive pulse and the fourth drive pulse to generate an output voltage, A first insulating capacitor and a second insulating capacitor are configured to transmit the first drive pulse and the second drive pulse generated by the pulse generation circuit to the rectifier and smoothing circuit as the third drive pulse and the fourth drive pulse, respectively, while insulating the pulse generation circuit from the pulse generation circuit and the rectifier and smoothing circuit. A power supply unit equipped with the following features.

2. The rectifier and smoothing circuit described above is A first diode having its cathode connected to the first insulating capacitor and its anode connected to the ground terminal, A second diode whose anode is connected to the first insulating capacitor and whose cathode is connected to the terminal to which the output voltage is applied, A third diode whose cathode is connected to the second insulating capacitor and whose anode is connected to the ground terminal, A fourth diode whose anode is connected to the second insulating capacitor and whose cathode is connected to the terminal to which the output voltage is applied, A first output capacitor connected between the output voltage application terminal and the ground terminal, The power supply device according to claim 1, including the following:

3. The rectifier and smoothing circuit described above is A first diode having its cathode connected to the first insulating capacitor and its anode connected to the ground terminal, A second diode whose anode is connected to the first insulating capacitor and whose cathode is connected to an internal node, A third diode whose cathode is connected to the second insulating capacitor and whose anode is connected to the internal node, A fourth diode whose anode is connected to the second insulating capacitor and whose cathode is connected to the terminal to which the output voltage is applied, A first output capacitor connected between the output voltage application terminal and the ground terminal, A second output capacitor connected between the internal node and the ground terminal, The power supply device according to claim 1, including the following:

4. The rectifier and smoothing circuit described above is A first transistor connected between the first insulating capacitor and the ground terminal, A second transistor connected between the first insulating capacitor and the output voltage application terminal, A third transistor connected between the second insulating capacitor and the ground terminal, A fourth transistor connected between the second insulating capacitor and the output voltage application terminal, A first output capacitor connected between the output voltage application terminal and the ground terminal, The power supply device according to claim 1, including the following:

5. The rectifier and smoothing circuit described above is A first transistor connected between the first insulating capacitor and the ground terminal, A second transistor connected between the first isolation capacitor and the internal node, A third transistor connected between the second insulating capacitor and the internal node, A fourth transistor connected between the second insulating capacitor and the output voltage application terminal, A first output capacitor connected between the output voltage application terminal and the ground terminal, A second output capacitor connected between the internal node and the ground terminal, The power supply device according to claim 1, including the following:

6. The power supply device according to claim 4, wherein the first transistor and the second transistor are driven in accordance with the fourth drive pulse, and the third transistor and the fourth transistor are driven in accordance with the third drive pulse.

7. The rectifier and smoothing circuit described above is A first capacitor and a second capacitor are connected between the gates of the first transistor and the second transistor and the second insulating capacitor, respectively. A third capacitor and a fourth capacitor are connected between the gates of the third transistor and the fourth transistor and the first insulating capacitor, respectively. The power supply device according to claim 6, further comprising:

8. The power supply device according to claim 7, wherein the rectifier-smoothing circuit further includes a first resistor, a second resistor, a third resistor, and a fourth resistor connected between the gate and source of the first transistor, the second transistor, the third transistor, and the fourth transistor, respectively.

9. The power supply device according to claim 8, wherein the rectifier-smoothing circuit further includes a fifth diode, a sixth diode, a seventh diode, and an eighth diode connected in parallel with the first resistor, the second resistor, the third resistor, and the fourth resistor, respectively.

10. A first driver configured to drive the first isolation capacitor in response to the first drive pulse, A second driver configured to drive the second isolation capacitor in response to the second drive pulse, The power supply device according to claim 1, further comprising a boost circuit configured to receive an input voltage and supply a boosted voltage higher than the input voltage to at least one of the first driver and the second driver.

11. The aforementioned boost circuit is A flying capacitor whose first end is connected to the terminal to which the boosted voltage is applied, A switch element configured to conduct / interrupt between the input voltage application terminal and the first terminal of the flying capacitor, An inverter configured to drive the second terminal of the flying capacitor in response to the first drive pulse or the second drive pulse, The power supply device according to claim 10, including the following:

12. The power supply device according to claim 11, wherein the switching element is a diode whose anode is connected to the input voltage application terminal and whose cathode is connected to the first terminal of the flying capacitor.

13. The power supply device according to claim 11, wherein the switching element is a transistor configured to be driven in accordance with a first control pulse or a second control pulse.

14. The power supply device according to claim 13, wherein the ON period of the transistor is included in the low-level output period of the first driver or the second driver.

15. A detection circuit configured to detect the output voltage and generate a feedback signal, An isolated communication circuit configured to transmit the feedback signal from the detection circuit to the pulse generation circuit while insulating the detection circuit from the pulse generation circuit, Furthermore, The power supply device according to claim 1, wherein the pulse generation circuit generates the first drive pulse and the second drive pulse in response to the feedback signal.

16. A semiconductor device used in a power supply device according to any one of claims 1 to 15, The first chip on which the pulse generation circuit is integrated, A second chip on which the rectifier and smoothing circuit is integrated, A semiconductor device comprising a sealed element.

17. A semiconductor device used in a power supply device according to any one of claims 4 to 9, The first chip on which the pulse generation circuit is integrated, A second chip on which the rectifier and smoothing circuit is integrated, It is formed by sealing, The second chip is a semiconductor device comprising pads that are electrically connected to the control terminals of the third transistor and the fourth transistor, respectively.

18. The semiconductor device according to claim 16, further comprising an isolated ADC configured to transmit an analog signal input to the second chip as a digital signal output from the first chip while insulating the first chip from the second chip.

19. The second chip includes: ADC configured to receive the aforementioned analog signal input, A regulator configured to generate the drive voltage of the ADC from the output voltage, The semiconductor device according to claim 18, wherein the components are further integrated.

20. The semiconductor device according to claim 16, The first insulating capacitor and the second insulating capacitor connected to the semiconductor device, An electronic device equipped with the following features.

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